diff options
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 34 |
1 files changed, 23 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f3b2d18482d8..3511effa01ec 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -8058,29 +8058,42 @@ static void intel_enable_pipe_a(struct drm_device *dev) | |||
8058 | 8058 | ||
8059 | } | 8059 | } |
8060 | 8060 | ||
8061 | static bool | ||
8062 | intel_check_plane_mapping(struct intel_crtc *crtc) | ||
8063 | { | ||
8064 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | ||
8065 | u32 reg, val; | ||
8066 | |||
8067 | if (dev_priv->num_pipe == 1) | ||
8068 | return true; | ||
8069 | |||
8070 | reg = DSPCNTR(!crtc->plane); | ||
8071 | val = I915_READ(reg); | ||
8072 | |||
8073 | if ((val & DISPLAY_PLANE_ENABLE) && | ||
8074 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | ||
8075 | return false; | ||
8076 | |||
8077 | return true; | ||
8078 | } | ||
8079 | |||
8061 | static void intel_sanitize_crtc(struct intel_crtc *crtc) | 8080 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
8062 | { | 8081 | { |
8063 | struct drm_device *dev = crtc->base.dev; | 8082 | struct drm_device *dev = crtc->base.dev; |
8064 | struct drm_i915_private *dev_priv = dev->dev_private; | 8083 | struct drm_i915_private *dev_priv = dev->dev_private; |
8065 | u32 reg, val; | 8084 | u32 reg; |
8066 | 8085 | ||
8067 | /* Clear any frame start delays used for debugging left by the BIOS */ | 8086 | /* Clear any frame start delays used for debugging left by the BIOS */ |
8068 | reg = PIPECONF(crtc->pipe); | 8087 | reg = PIPECONF(crtc->pipe); |
8069 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | 8088 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
8070 | 8089 | ||
8071 | /* We need to sanitize the plane -> pipe mapping first because this will | 8090 | /* We need to sanitize the plane -> pipe mapping first because this will |
8072 | * disable the crtc (and hence change the state) if it is wrong. */ | 8091 | * disable the crtc (and hence change the state) if it is wrong. Note |
8073 | if (!HAS_PCH_SPLIT(dev)) { | 8092 | * that gen4+ has a fixed plane -> pipe mapping. */ |
8093 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | ||
8074 | struct intel_connector *connector; | 8094 | struct intel_connector *connector; |
8075 | bool plane; | 8095 | bool plane; |
8076 | 8096 | ||
8077 | reg = DSPCNTR(crtc->plane); | ||
8078 | val = I915_READ(reg); | ||
8079 | |||
8080 | if ((val & DISPLAY_PLANE_ENABLE) == 0 && | ||
8081 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | ||
8082 | goto ok; | ||
8083 | |||
8084 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", | 8097 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
8085 | crtc->base.base.id); | 8098 | crtc->base.base.id); |
8086 | 8099 | ||
@@ -8104,7 +8117,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) | |||
8104 | WARN_ON(crtc->active); | 8117 | WARN_ON(crtc->active); |
8105 | crtc->base.enabled = false; | 8118 | crtc->base.enabled = false; |
8106 | } | 8119 | } |
8107 | ok: | ||
8108 | 8120 | ||
8109 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && | 8121 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
8110 | crtc->pipe == PIPE_A && !crtc->active) { | 8122 | crtc->pipe == PIPE_A && !crtc->active) { |