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-rw-r--r--Documentation/devicetree/bindings/arm/omap/omap.txt3
-rw-r--r--Documentation/devicetree/bindings/arm/vic.txt12
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt19
-rw-r--r--Documentation/devicetree/bindings/crypto/omap-aes.txt31
-rw-r--r--Documentation/devicetree/bindings/crypto/omap-sham.txt28
-rw-r--r--Documentation/devicetree/bindings/hwrng/omap_rng.txt22
-rw-r--r--Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt26
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt859
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt11
-rw-r--r--Documentation/devicetree/bindings/usb/ux500-usb.txt2
-rw-r--r--Documentation/devicetree/bindings/video/exynos_hdmi.txt14
-rw-r--r--Documentation/devicetree/bindings/video/exynos_mixer.txt4
-rw-r--r--MAINTAINERS8
-rw-r--r--arch/arm/boot/dts/Makefile43
-rw-r--r--arch/arm/boot/dts/am335x-base0033.dts16
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi311
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts18
-rw-r--r--arch/arm/boot/dts/am335x-boneblack.dts61
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts771
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts474
-rw-r--r--arch/arm/boot/dts/am335x-igep0033.dtsi278
-rw-r--r--arch/arm/boot/dts/am335x-nano.dts431
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi155
-rw-r--r--arch/arm/boot/dts/am4372.dtsi599
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts168
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn104.dts193
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi20
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi9
-rw-r--r--arch/arm/boot/dts/armada-xp-matrix.dts75
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi1
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi1
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi1
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi10
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi3
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts34
-rw-r--r--arch/arm/boot/dts/atlas6.dtsi33
-rw-r--r--arch/arm/boot/dts/bcm11351-brt.dts1
-rw-r--r--arch/arm/boot/dts/bcm11351.dtsi54
-rw-r--r--arch/arm/boot/dts/bcm28155-ap.dts1
-rw-r--r--arch/arm/boot/dts/dove-cm-a510.dts2
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts20
-rw-r--r--arch/arm/boot/dts/dove-d2plug.dts2
-rw-r--r--arch/arm/boot/dts/dove-d3plug.dts103
-rw-r--r--arch/arm/boot/dts/dove-dove-db.dts2
-rw-r--r--arch/arm/boot/dts/dove.dtsi1037
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts275
-rw-r--r--arch/arm/boot/dts/dra7.dtsi586
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi10
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts21
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts21
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts33
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts8
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi11
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts26
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi75
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts2
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi2
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts16
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts18
-rw-r--r--arch/arm/boot/dts/imx23-pinfunc.h333
-rw-r--r--arch/arm/boot/dts/imx23-stmp378x_devb.dts12
-rw-r--r--arch/arm/boot/dts/imx23.dtsi221
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts26
-rw-r--r--arch/arm/boot/dts/imx27.dtsi1
-rw-r--r--arch/arm/boot/dts/imx28-apf28.dts2
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts36
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts60
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts26
-rw-r--r--arch/arm/boot/dts/imx28-cfa10037.dts18
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts156
-rw-r--r--arch/arm/boot/dts/imx28-cfa10055.dts80
-rw-r--r--arch/arm/boot/dts/imx28-cfa10056.dts38
-rw-r--r--arch/arm/boot/dts/imx28-cfa10057.dts66
-rw-r--r--arch/arm/boot/dts/imx28-cfa10058.dts24
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts59
-rw-r--r--arch/arm/boot/dts/imx28-m28cu3.dts266
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts28
-rw-r--r--arch/arm/boot/dts/imx28-pinfunc.h506
-rw-r--r--arch/arm/boot/dts/imx28-sps1.dts14
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts703
-rw-r--r--arch/arm/boot/dts/imx28.dtsi620
-rw-r--r--arch/arm/boot/dts/imx51-apf51dev.dts27
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts37
-rw-r--r--arch/arm/boot/dts/imx51.dtsi23
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts9
-rw-r--r--arch/arm/boot/dts/imx6q-pinfunc.h4
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts104
-rw-r--r--arch/arm/boot/dts/imx6q-udoo.dts39
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi5
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi18
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard.dtsi23
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi67
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts67
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi172
-rw-r--r--arch/arm/boot/dts/kirkwood-db-88f6281.dts1
-rw-r--r--arch/arm/boot/dts/kirkwood-db-88f6282.dts1
-rw-r--r--arch/arm/boot/dts/kirkwood-db.dtsi44
-rw-r--r--arch/arm/boot/dts/kirkwood-dnskw.dtsi76
-rw-r--r--arch/arm/boot/dts/kirkwood-dockstar.dts40
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts51
-rw-r--r--arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts40
-rw-r--r--arch/arm/boot/dts/kirkwood-ib62x0.dts53
-rw-r--r--arch/arm/boot/dts/kirkwood-iconnect.dts59
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts51
-rw-r--r--arch/arm/boot/dts/kirkwood-km_kirkwood.dts14
-rw-r--r--arch/arm/boot/dts/kirkwood-mplcec4.dts63
-rw-r--r--arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts61
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310-common.dtsi86
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310.dts1
-rw-r--r--arch/arm/boot/dts/kirkwood-openblocks_a6.dts74
-rw-r--r--arch/arm/boot/dts/kirkwood-openblocks_a7.dts223
-rw-r--r--arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi42
-rw-r--r--arch/arm/boot/dts/kirkwood-topkick.dts62
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6282.dts1
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi57
-rw-r--r--arch/arm/boot/dts/mxs-pinfunc.h31
-rw-r--r--arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi52
-rw-r--r--arch/arm/boot/dts/omap-zoom-common.dtsi33
-rw-r--r--arch/arm/boot/dts/omap2420-h4.dts6
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts65
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts46
-rw-r--r--arch/arm/boot/dts/omap3-devkit8000.dts2
-rw-r--r--arch/arm/boot/dts/omap3-evm-37xx.dts151
-rw-r--r--arch/arm/boot/dts/omap3-evm-common.dtsi96
-rw-r--r--arch/arm/boot/dts/omap3-evm.dts60
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dts170
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi11
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts107
-rw-r--r--arch/arm/boot/dts/omap3-igep0030.dts17
-rw-r--r--arch/arm/boot/dts/omap3-n9.dts18
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts484
-rw-r--r--arch/arm/boot/dts/omap3-n950-n9.dtsi174
-rw-r--r--arch/arm/boot/dts/omap3-n950.dts18
-rw-r--r--arch/arm/boot/dts/omap3-zoom3.dts217
-rw-r--r--arch/arm/boot/dts/omap3.dtsi58
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts22
-rw-r--r--arch/arm/boot/dts/omap36xx.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi82
-rw-r--r--arch/arm/boot/dts/omap4-panda-es.dts4
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts21
-rw-r--r--arch/arm/boot/dts/omap4.dtsi37
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts84
-rw-r--r--arch/arm/boot/dts/omap5.dtsi30
-rw-r--r--arch/arm/boot/dts/prima2.dtsi30
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts73
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts1
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi52
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts78
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi35
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw-reference.dts27
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi19
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen-reference.dts8
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi5
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi89
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi33
-rw-r--r--arch/arm/boot/dts/s3c6400.dtsi41
-rw-r--r--arch/arm/boot/dts/s3c6410-mini6410.dts228
-rw-r--r--arch/arm/boot/dts/s3c6410-smdk6410.dts103
-rw-r--r--arch/arm/boot/dts/s3c6410.dtsi57
-rw-r--r--arch/arm/boot/dts/s3c64xx-pinctrl.dtsi687
-rw-r--r--arch/arm/boot/dts/s3c64xx.dtsi199
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts2
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi5
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi297
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi58
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts40
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dtsi (renamed from arch/arm/boot/dts/socfpga_cyclone5.dts)20
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts40
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts37
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi216
-rw-r--r--arch/arm/boot/dts/ste-href-stuib.dtsi (renamed from arch/arm/boot/dts/ste-stuib.dtsi)2
-rw-r--r--arch/arm/boot/dts/ste-href-tvk1281618.dtsi41
-rw-r--r--arch/arm/boot/dts/ste-href.dtsi109
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60-stuib.dts34
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60-tvk.dts19
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60.dtsi (renamed from arch/arm/boot/dts/ste-hrefprev60.dts)37
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus-stuib.dts36
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus-tvk.dts21
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus.dts210
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus.dtsi70
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts85
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi5
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi5
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi5
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi2
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts12
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubietruck.dts63
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts18
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi71
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts32
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi6
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts27
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi149
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi3
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi5
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi49
-rw-r--r--arch/arm/boot/dts/twl6030_omap4.dtsi38
-rw-r--r--arch/arm/boot/dts/vf610-cosmic.dts47
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts17
-rw-r--r--arch/arm/boot/dts/vf610.dtsi12
-rw-r--r--arch/arm/configs/omap2plus_defconfig109
-rw-r--r--arch/arm/configs/u8500_defconfig12
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c1
-rw-r--r--arch/arm/mach-kirkwood/board-dt.c1
-rw-r--r--arch/arm/mach-mxs/mach-mxs.c7
-rw-r--r--arch/arm/mach-omap2/Kconfig56
-rw-r--r--arch/arm/mach-omap2/Makefile14
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c225
-rw-r--r--arch/arm/mach-omap2/board-generic.c40
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c718
-rw-r--r--arch/arm/mach-omap2/board-ldp.c3
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c756
-rw-r--r--arch/arm/mach-omap2/board-rm680.c167
-rw-r--r--arch/arm/mach-omap2/board-zoom-debugboard.c139
-rw-r--r--arch/arm/mach-omap2/board-zoom-display.c71
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c360
-rw-r--r--arch/arm/mach-omap2/board-zoom.c159
-rw-r--r--arch/arm/mach-omap2/board-zoom.h10
-rw-r--r--arch/arm/mach-omap2/common.h7
-rw-r--r--arch/arm/mach-omap2/devices.c38
-rw-r--r--arch/arm/mach-omap2/dss-common.c44
-rw-r--r--arch/arm/mach-omap2/dss-common.h1
-rw-r--r--arch/arm/mach-omap2/gpmc.c38
-rw-r--r--arch/arm/mach-omap2/io.c20
-rw-r--r--arch/arm/mach-omap2/mux.c8
-rw-r--r--arch/arm/mach-omap2/opp.c4
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c174
-rw-r--r--arch/arm/mach-omap2/pm.c12
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h8
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h8
-rw-r--r--arch/arm/mach-omap2/prm_common.c11
-rw-r--r--arch/arm/mach-s3c64xx/Kconfig16
-rw-r--r--arch/arm/mach-s3c64xx/Makefile1
-rw-r--r--arch/arm/mach-s3c64xx/common.c12
-rw-r--r--arch/arm/mach-s3c64xx/dma.c9
-rw-r--r--arch/arm/mach-s3c64xx/irq-pm.c9
-rw-r--r--arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c85
-rw-r--r--arch/arm/mach-s3c64xx/s3c6400.c9
-rw-r--r--arch/arm/mach-s3c64xx/s3c6410.c9
-rw-r--r--arch/arm/mach-ux500/Makefile5
-rw-r--r--arch/arm/mach-ux500/board-mop500-audio.c50
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c51
-rw-r--r--arch/arm/mach-ux500/board-mop500-stuib.c120
-rw-r--r--arch/arm/mach-ux500/board-mop500-u8500uib.c92
-rw-r--r--arch/arm/mach-ux500/board-mop500-uib.c133
-rw-r--r--arch/arm/mach-ux500/board-mop500.c637
-rw-r--r--arch/arm/mach-ux500/board-mop500.h16
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c124
-rw-r--r--arch/arm/mach-ux500/cpu.c19
-rw-r--r--arch/arm/mach-ux500/devices-common.c60
-rw-r--r--arch/arm/mach-ux500/devices-common.h149
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c94
-rw-r--r--arch/arm/mach-ux500/devices-db8500.h110
-rw-r--r--arch/arm/mach-ux500/devices.h8
-rw-r--r--arch/arm/mach-ux500/setup.h1
-rw-r--r--arch/arm/mach-ux500/timer.c4
-rw-r--r--arch/arm/mach-ux500/usb.c135
-rw-r--r--arch/arm/plat-samsung/init.c12
-rw-r--r--drivers/clk/ux500/Makefile1
-rw-r--r--drivers/clk/ux500/u8500_of_clk.c559
-rw-r--r--drivers/clk/ux500/u8540_clk.c2
-rw-r--r--drivers/gpio/gpio-samsung.c34
-rw-r--r--drivers/irqchip/irq-vic.c7
-rw-r--r--drivers/mfd/db8500-prcmu.c1
-rw-r--r--drivers/mfd/dbx500-prcmu-regs.h1
-rw-r--r--drivers/pinctrl/pinctrl-single.c388
-rw-r--r--drivers/usb/musb/ux500.c2
-rw-r--r--include/dt-bindings/mfd/dbx500-prcmu.h83
-rw-r--r--include/dt-bindings/pinctrl/am43xx.h31
-rw-r--r--include/dt-bindings/pinctrl/dra.h50
-rw-r--r--include/linux/mfd/dbx500-prcmu.h70
-rw-r--r--include/linux/platform_data/clk-ux500.h3
-rw-r--r--include/linux/platform_data/pinctrl-single.h12
274 files changed, 15385 insertions, 8921 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 91b7049affa1..808c1543b0f8 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -21,7 +21,8 @@ Required properties:
21Optional properties: 21Optional properties:
22- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module 22- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
23 during suspend. 23 during suspend.
24 24- ti,no-reset-on-init: When present, the module should not be reset at init
25- ti,no-idle-on-init: When present, the module should not be idled at init
25 26
26Example: 27Example:
27 28
diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt
index 266716b23437..dd527216c5fb 100644
--- a/Documentation/devicetree/bindings/arm/vic.txt
+++ b/Documentation/devicetree/bindings/arm/vic.txt
@@ -18,6 +18,15 @@ Required properties:
18Optional properties: 18Optional properties:
19 19
20- interrupts : Interrupt source for parent controllers if the VIC is nested. 20- interrupts : Interrupt source for parent controllers if the VIC is nested.
21- valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
22 represents single interrupt source, starting from source 0 at LSb and ending
23 at source 31 at MSb. A bit that is set means that the source is wired and
24 clear means otherwise. If unspecified, defaults to all valid.
25- valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be
26 configured as wake up source for the system. Order of bits is the same as for
27 valid-mask property. A set bit means that this interrupt source can be
28 configured as a wake up source for the system. If unspecied, defaults to all
29 interrupt sources configurable as wake up sources.
21 30
22Example: 31Example:
23 32
@@ -26,4 +35,7 @@ Example:
26 interrupt-controller; 35 interrupt-controller;
27 #interrupt-cells = <1>; 36 #interrupt-cells = <1>;
28 reg = <0x60000 0x1000>; 37 reg = <0x60000 0x1000>;
38
39 valid-mask = <0xffffff7f>;
40 valid-wakeup-mask = <0x0000ff7f>;
29 }; 41 };
diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
new file mode 100644
index 000000000000..c62391fc0e39
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -0,0 +1,19 @@
1* Core Divider Clock bindings for Marvell MVEBU SoCs
2
3The following is a list of provided IDs and clock names on Armada 370/XP:
4 0 = nand (NAND clock)
5
6Required properties:
7- compatible : must be "marvell,armada-370-corediv-clock"
8- reg : must be the register address of Core Divider control register
9- #clock-cells : from common clock binding; shall be set to 1
10- clocks : must be set to the parent's phandle
11
12Example:
13
14corediv_clk: corediv-clocks@18740 {
15 compatible = "marvell,armada-370-corediv-clock";
16 reg = <0x18740 0xc>;
17 #clock-cells = <1>;
18 clocks = <&pll>;
19};
diff --git a/Documentation/devicetree/bindings/crypto/omap-aes.txt b/Documentation/devicetree/bindings/crypto/omap-aes.txt
new file mode 100644
index 000000000000..fd9717653cbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/omap-aes.txt
@@ -0,0 +1,31 @@
1OMAP SoC AES crypto Module
2
3Required properties:
4
5- compatible : Should contain entries for this and backward compatible
6 AES versions:
7 - "ti,omap2-aes" for OMAP2.
8 - "ti,omap3-aes" for OMAP3.
9 - "ti,omap4-aes" for OMAP4 and AM33XX.
10 Note that the OMAP2 and 3 versions are compatible (OMAP3 supports
11 more algorithms) but they are incompatible with OMAP4.
12- ti,hwmods: Name of the hwmod associated with the AES module
13- reg : Offset and length of the register set for the module
14- interrupts : the interrupt-specifier for the AES module.
15
16Optional properties:
17- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
18 Documentation/devicetree/bindings/dma/dma.txt
19- dma-names: DMA request names should include "tx" and "rx" if present.
20
21Example:
22 /* AM335x */
23 aes: aes@53500000 {
24 compatible = "ti,omap4-aes";
25 ti,hwmods = "aes";
26 reg = <0x53500000 0xa0>;
27 interrupts = <102>;
28 dmas = <&edma 6>,
29 <&edma 5>;
30 dma-names = "tx", "rx";
31 };
diff --git a/Documentation/devicetree/bindings/crypto/omap-sham.txt b/Documentation/devicetree/bindings/crypto/omap-sham.txt
new file mode 100644
index 000000000000..f839acd6f0ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/omap-sham.txt
@@ -0,0 +1,28 @@
1OMAP SoC SHA crypto Module
2
3Required properties:
4
5- compatible : Should contain entries for this and backward compatible
6 SHAM versions:
7 - "ti,omap2-sham" for OMAP2 & OMAP3.
8 - "ti,omap4-sham" for OMAP4 and AM33XX.
9 Note that these two versions are incompatible.
10- ti,hwmods: Name of the hwmod associated with the SHAM module
11- reg : Offset and length of the register set for the module
12- interrupts : the interrupt-specifier for the SHAM module.
13
14Optional properties:
15- dmas: DMA specifiers for the rx dma. See the DMA client binding,
16 Documentation/devicetree/bindings/dma/dma.txt
17- dma-names: DMA request name. Should be "rx" if a dma is present.
18
19Example:
20 /* AM335x */
21 sham: sham@53100000 {
22 compatible = "ti,omap4-sham";
23 ti,hwmods = "sham";
24 reg = <0x53100000 0x200>;
25 interrupts = <109>;
26 dmas = <&edma 36>;
27 dma-names = "rx";
28 };
diff --git a/Documentation/devicetree/bindings/hwrng/omap_rng.txt b/Documentation/devicetree/bindings/hwrng/omap_rng.txt
new file mode 100644
index 000000000000..6a62acd86953
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwrng/omap_rng.txt
@@ -0,0 +1,22 @@
1OMAP SoC HWRNG Module
2
3Required properties:
4
5- compatible : Should contain entries for this and backward compatible
6 RNG versions:
7 - "ti,omap2-rng" for OMAP2.
8 - "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX.
9 Note that these two versions are incompatible.
10- ti,hwmods: Name of the hwmod associated with the RNG module
11- reg : Offset and length of the register set for the module
12- interrupts : the interrupt number for the RNG module.
13 Only used for "ti,omap4-rng".
14
15Example:
16/* AM335x */
17rng: rng@48310000 {
18 compatible = "ti,omap4-rng";
19 ti,hwmods = "rng";
20 reg = <0x48310000 0x2000>;
21 interrupts = <111>;
22};
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index ed271fc255b2..8c8908ab84ba 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -20,8 +20,29 @@ ti,dual-volt: boolean, supports dual voltage cards
20ti,non-removable: non-removable slot (like eMMC) 20ti,non-removable: non-removable slot (like eMMC)
21ti,needs-special-reset: Requires a special softreset sequence 21ti,needs-special-reset: Requires a special softreset sequence
22ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed 22ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
23dmas: List of DMA specifiers with the controller specific format
24as described in the generic DMA client binding. A tx and rx
25specifier is required.
26dma-names: List of DMA request names. These strings correspond
271:1 with the DMA specifiers listed in dmas. The string naming is
28to be "rx" and "tx" for RX and TX DMA requests, respectively.
29
30Examples:
31
32[hwmod populated DMA resources]
33
34 mmc1: mmc@0x4809c000 {
35 compatible = "ti,omap4-hsmmc";
36 reg = <0x4809c000 0x400>;
37 ti,hwmods = "mmc1";
38 ti,dual-volt;
39 bus-width = <4>;
40 vmmc-supply = <&vmmc>; /* phandle to regulator node */
41 ti,non-removable;
42 };
43
44[generic DMA request binding]
23 45
24Example:
25 mmc1: mmc@0x4809c000 { 46 mmc1: mmc@0x4809c000 {
26 compatible = "ti,omap4-hsmmc"; 47 compatible = "ti,omap4-hsmmc";
27 reg = <0x4809c000 0x400>; 48 reg = <0x4809c000 0x400>;
@@ -30,4 +51,7 @@ Example:
30 bus-width = <4>; 51 bus-width = <4>;
31 vmmc-supply = <&vmmc>; /* phandle to regulator node */ 52 vmmc-supply = <&vmmc>; /* phandle to regulator node */
32 ti,non-removable; 53 ti,non-removable;
54 dmas = <&edma 24
55 &edma 25>;
56 dma-names = "tx", "rx";
33 }; 57 };
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
index 3077370c89af..1e70a8aff260 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
@@ -59,16 +59,16 @@ Required subnode-properties:
59 59
60Optional subnode-properties: 60Optional subnode-properties:
61- fsl,drive-strength: Integer. 61- fsl,drive-strength: Integer.
62 0: 4 mA 62 0: MXS_DRIVE_4mA
63 1: 8 mA 63 1: MXS_DRIVE_8mA
64 2: 12 mA 64 2: MXS_DRIVE_12mA
65 3: 16 mA 65 3: MXS_DRIVE_16mA
66- fsl,voltage: Integer. 66- fsl,voltage: Integer.
67 0: 1.8 V 67 0: MXS_VOLTAGE_LOW - 1.8 V
68 1: 3.3 V 68 1: MXS_VOLTAGE_HIGH - 3.3 V
69- fsl,pull-up: Integer. 69- fsl,pull-up: Integer.
70 0: Disable the internal pull-up 70 0: MXS_PULL_DISABLE - Disable the internal pull-up
71 1: Enable the internal pull-up 71 1: MXS_PULL_ENABLE - Enable the internal pull-up
72 72
73Note that when enabling the pull-up, the internal pad keeper gets disabled. 73Note that when enabling the pull-up, the internal pad keeper gets disabled.
74Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up 74Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up
@@ -85,23 +85,32 @@ pinctrl@80018000 {
85 mmc0_8bit_pins_a: mmc0-8bit@0 { 85 mmc0_8bit_pins_a: mmc0-8bit@0 {
86 reg = <0>; 86 reg = <0>;
87 fsl,pinmux-ids = < 87 fsl,pinmux-ids = <
88 0x2000 0x2010 0x2020 0x2030 88 MX28_PAD_SSP0_DATA0__SSP0_D0
89 0x2040 0x2050 0x2060 0x2070 89 MX28_PAD_SSP0_DATA1__SSP0_D1
90 0x2080 0x2090 0x20a0>; 90 MX28_PAD_SSP0_DATA2__SSP0_D2
91 fsl,drive-strength = <1>; 91 MX28_PAD_SSP0_DATA3__SSP0_D3
92 fsl,voltage = <1>; 92 MX28_PAD_SSP0_DATA4__SSP0_D4
93 fsl,pull-up = <1>; 93 MX28_PAD_SSP0_DATA5__SSP0_D5
94 MX28_PAD_SSP0_DATA6__SSP0_D6
95 MX28_PAD_SSP0_DATA7__SSP0_D7
96 MX28_PAD_SSP0_CMD__SSP0_CMD
97 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
98 MX28_PAD_SSP0_SCK__SSP0_SCK
99 >;
100 fsl,drive-strength = <MXS_DRIVE_4mA>;
101 fsl,voltage = <MXS_VOLTAGE_HIGH>;
102 fsl,pull-up = <MXS_PULL_ENABLE>;
94 }; 103 };
95 104
96 mmc_cd_cfg: mmc-cd-cfg { 105 mmc_cd_cfg: mmc-cd-cfg {
97 fsl,pinmux-ids = <0x2090>; 106 fsl,pinmux-ids = <MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT>;
98 fsl,pull-up = <0>; 107 fsl,pull-up = <MXS_PULL_DISABLE>;
99 }; 108 };
100 109
101 mmc_sck_cfg: mmc-sck-cfg { 110 mmc_sck_cfg: mmc-sck-cfg {
102 fsl,pinmux-ids = <0x20a0>; 111 fsl,pinmux-ids = <MX28_PAD_SSP0_SCK__SSP0_SCK>;
103 fsl,drive-strength = <2>; 112 fsl,drive-strength = <MXS_DRIVE_12mA>;
104 fsl,pull-up = <0>; 113 fsl,pull-up = <MXS_PULL_DISABLE>;
105 }; 114 };
106}; 115};
107 116
@@ -112,811 +121,7 @@ adjusting the configuration for pins card-detection and clock from what group
112node mmc0-8bit defines. Only the configuration properties to be adjusted need 121node mmc0-8bit defines. Only the configuration properties to be adjusted need
113to be listed in the config nodes. 122to be listed in the config nodes.
114 123
115Valid values for i.MX28 pinmux-id: 124Valid values for i.MX28/i.MX23 pinmux-id are defined in
116 125arch/arm/boot/dts/imx28-pinfunc.h and arch/arm/boot/dts/imx23-pinfunc.h.
117pinmux id 126The definitions for the padconfig properties can be found in
118------ -- 127arch/arm/boot/dts/mxs-pinfunc.h.
119MX28_PAD_GPMI_D00__GPMI_D0 0x0000
120MX28_PAD_GPMI_D01__GPMI_D1 0x0010
121MX28_PAD_GPMI_D02__GPMI_D2 0x0020
122MX28_PAD_GPMI_D03__GPMI_D3 0x0030
123MX28_PAD_GPMI_D04__GPMI_D4 0x0040
124MX28_PAD_GPMI_D05__GPMI_D5 0x0050
125MX28_PAD_GPMI_D06__GPMI_D6 0x0060
126MX28_PAD_GPMI_D07__GPMI_D7 0x0070
127MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
128MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
129MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
130MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
131MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
132MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
133MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
134MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
135MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
136MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
137MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
138MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
139MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
140MX28_PAD_LCD_D00__LCD_D0 0x1000
141MX28_PAD_LCD_D01__LCD_D1 0x1010
142MX28_PAD_LCD_D02__LCD_D2 0x1020
143MX28_PAD_LCD_D03__LCD_D3 0x1030
144MX28_PAD_LCD_D04__LCD_D4 0x1040
145MX28_PAD_LCD_D05__LCD_D5 0x1050
146MX28_PAD_LCD_D06__LCD_D6 0x1060
147MX28_PAD_LCD_D07__LCD_D7 0x1070
148MX28_PAD_LCD_D08__LCD_D8 0x1080
149MX28_PAD_LCD_D09__LCD_D9 0x1090
150MX28_PAD_LCD_D10__LCD_D10 0x10a0
151MX28_PAD_LCD_D11__LCD_D11 0x10b0
152MX28_PAD_LCD_D12__LCD_D12 0x10c0
153MX28_PAD_LCD_D13__LCD_D13 0x10d0
154MX28_PAD_LCD_D14__LCD_D14 0x10e0
155MX28_PAD_LCD_D15__LCD_D15 0x10f0
156MX28_PAD_LCD_D16__LCD_D16 0x1100
157MX28_PAD_LCD_D17__LCD_D17 0x1110
158MX28_PAD_LCD_D18__LCD_D18 0x1120
159MX28_PAD_LCD_D19__LCD_D19 0x1130
160MX28_PAD_LCD_D20__LCD_D20 0x1140
161MX28_PAD_LCD_D21__LCD_D21 0x1150
162MX28_PAD_LCD_D22__LCD_D22 0x1160
163MX28_PAD_LCD_D23__LCD_D23 0x1170
164MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
165MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
166MX28_PAD_LCD_RS__LCD_RS 0x11a0
167MX28_PAD_LCD_CS__LCD_CS 0x11b0
168MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
169MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
170MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
171MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
172MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
173MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
174MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
175MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
176MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
177MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
178MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
179MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
180MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
181MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
182MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
183MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
184MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
185MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
186MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
187MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
188MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
189MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
190MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
191MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
192MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
193MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
194MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
195MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
196MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
197MX28_PAD_AUART0_RX__AUART0_RX 0x3000
198MX28_PAD_AUART0_TX__AUART0_TX 0x3010
199MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
200MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
201MX28_PAD_AUART1_RX__AUART1_RX 0x3040
202MX28_PAD_AUART1_TX__AUART1_TX 0x3050
203MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
204MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
205MX28_PAD_AUART2_RX__AUART2_RX 0x3080
206MX28_PAD_AUART2_TX__AUART2_TX 0x3090
207MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
208MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
209MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
210MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
211MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
212MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
213MX28_PAD_PWM0__PWM_0 0x3100
214MX28_PAD_PWM1__PWM_1 0x3110
215MX28_PAD_PWM2__PWM_2 0x3120
216MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
217MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
218MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
219MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
220MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
221MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
222MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
223MX28_PAD_SPDIF__SPDIF_TX 0x31b0
224MX28_PAD_PWM3__PWM_3 0x31c0
225MX28_PAD_PWM4__PWM_4 0x31d0
226MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
227MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
228MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
229MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
230MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
231MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
232MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
233MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
234MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
235MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
236MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
237MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
238MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
239MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
240MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
241MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
242MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
243MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
244MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
245MX28_PAD_EMI_D00__EMI_DATA0 0x5000
246MX28_PAD_EMI_D01__EMI_DATA1 0x5010
247MX28_PAD_EMI_D02__EMI_DATA2 0x5020
248MX28_PAD_EMI_D03__EMI_DATA3 0x5030
249MX28_PAD_EMI_D04__EMI_DATA4 0x5040
250MX28_PAD_EMI_D05__EMI_DATA5 0x5050
251MX28_PAD_EMI_D06__EMI_DATA6 0x5060
252MX28_PAD_EMI_D07__EMI_DATA7 0x5070
253MX28_PAD_EMI_D08__EMI_DATA8 0x5080
254MX28_PAD_EMI_D09__EMI_DATA9 0x5090
255MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
256MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
257MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
258MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
259MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
260MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
261MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
262MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
263MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
264MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
265MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
266MX28_PAD_EMI_CLK__EMI_CLK 0x5150
267MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
268MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
269MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
270MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
271MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
272MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
273MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
274MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
275MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
276MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
277MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
278MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
279MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
280MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
281MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
282MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
283MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
284MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
285MX28_PAD_EMI_BA0__EMI_BA0 0x6100
286MX28_PAD_EMI_BA1__EMI_BA1 0x6110
287MX28_PAD_EMI_BA2__EMI_BA2 0x6120
288MX28_PAD_EMI_CASN__EMI_CASN 0x6130
289MX28_PAD_EMI_RASN__EMI_RASN 0x6140
290MX28_PAD_EMI_WEN__EMI_WEN 0x6150
291MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
292MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
293MX28_PAD_EMI_CKE__EMI_CKE 0x6180
294MX28_PAD_GPMI_D00__SSP1_D0 0x0001
295MX28_PAD_GPMI_D01__SSP1_D1 0x0011
296MX28_PAD_GPMI_D02__SSP1_D2 0x0021
297MX28_PAD_GPMI_D03__SSP1_D3 0x0031
298MX28_PAD_GPMI_D04__SSP1_D4 0x0041
299MX28_PAD_GPMI_D05__SSP1_D5 0x0051
300MX28_PAD_GPMI_D06__SSP1_D6 0x0061
301MX28_PAD_GPMI_D07__SSP1_D7 0x0071
302MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
303MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
304MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
305MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
306MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
307MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
308MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
309MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
310MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
311MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
312MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
313MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
314MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
315MX28_PAD_LCD_D03__ETM_DA8 0x1031
316MX28_PAD_LCD_D04__ETM_DA9 0x1041
317MX28_PAD_LCD_D08__ETM_DA3 0x1081
318MX28_PAD_LCD_D09__ETM_DA4 0x1091
319MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
320MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
321MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
322MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
323MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
324MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
325MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
326MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
327MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
328MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
329MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
330MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
331MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
332MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
333MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
334MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
335MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
336MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
337MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
338MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
339MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
340MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
341MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
342MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
343MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
344MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
345MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
346MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
347MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
348MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
349MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
350MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
351MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
352MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
353MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
354MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
355MX28_PAD_AUART1_RTS__USB0_ID 0x3071
356MX28_PAD_AUART2_RX__SSP3_D1 0x3081
357MX28_PAD_AUART2_TX__SSP3_D2 0x3091
358MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
359MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
360MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
361MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
362MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
363MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
364MX28_PAD_PWM0__I2C1_SCL 0x3101
365MX28_PAD_PWM1__I2C1_SDA 0x3111
366MX28_PAD_PWM2__USB0_ID 0x3121
367MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
368MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
369MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
370MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
371MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
372MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
373MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
374MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
375MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
376MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
377MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
378MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
379MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
380MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
381MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
382MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
383MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
384MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
385MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
386MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
387MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
388MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
389MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
390MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
391MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
392MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
393MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
394MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
395MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
396MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
397MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
398MX28_PAD_LCD_D00__ETM_DA0 0x1002
399MX28_PAD_LCD_D01__ETM_DA1 0x1012
400MX28_PAD_LCD_D02__ETM_DA2 0x1022
401MX28_PAD_LCD_D03__ETM_DA3 0x1032
402MX28_PAD_LCD_D04__ETM_DA4 0x1042
403MX28_PAD_LCD_D05__ETM_DA5 0x1052
404MX28_PAD_LCD_D06__ETM_DA6 0x1062
405MX28_PAD_LCD_D07__ETM_DA7 0x1072
406MX28_PAD_LCD_D08__ETM_DA8 0x1082
407MX28_PAD_LCD_D09__ETM_DA9 0x1092
408MX28_PAD_LCD_D10__ETM_DA10 0x10a2
409MX28_PAD_LCD_D11__ETM_DA11 0x10b2
410MX28_PAD_LCD_D12__ETM_DA12 0x10c2
411MX28_PAD_LCD_D13__ETM_DA13 0x10d2
412MX28_PAD_LCD_D14__ETM_DA14 0x10e2
413MX28_PAD_LCD_D15__ETM_DA15 0x10f2
414MX28_PAD_LCD_D16__ETM_DA7 0x1102
415MX28_PAD_LCD_D17__ETM_DA6 0x1112
416MX28_PAD_LCD_D18__ETM_DA5 0x1122
417MX28_PAD_LCD_D19__ETM_DA4 0x1132
418MX28_PAD_LCD_D20__ETM_DA3 0x1142
419MX28_PAD_LCD_D21__ETM_DA2 0x1152
420MX28_PAD_LCD_D22__ETM_DA1 0x1162
421MX28_PAD_LCD_D23__ETM_DA0 0x1172
422MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
423MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
424MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
425MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
426MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
427MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
428MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
429MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
430MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
431MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
432MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
433MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
434MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
435MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
436MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
437MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
438MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
439MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
440MX28_PAD_AUART0_RX__DUART_CTS 0x3002
441MX28_PAD_AUART0_TX__DUART_RTS 0x3012
442MX28_PAD_AUART0_CTS__DUART_RX 0x3022
443MX28_PAD_AUART0_RTS__DUART_TX 0x3032
444MX28_PAD_AUART1_RX__PWM_0 0x3042
445MX28_PAD_AUART1_TX__PWM_1 0x3052
446MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
447MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
448MX28_PAD_AUART2_RX__SSP3_D4 0x3082
449MX28_PAD_AUART2_TX__SSP3_D5 0x3092
450MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
451MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
452MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
453MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
454MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
455MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
456MX28_PAD_PWM0__DUART_RX 0x3102
457MX28_PAD_PWM1__DUART_TX 0x3112
458MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
459MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
460MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
461MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
462MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
463MX28_PAD_I2C0_SCL__DUART_RX 0x3182
464MX28_PAD_I2C0_SDA__DUART_TX 0x3192
465MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
466MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
467MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
468MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
469MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
470MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
471MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
472MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
473MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
474MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
475MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
476MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
477MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
478MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
479MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
480MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
481MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
482MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
483MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
484MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
485MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
486MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
487MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
488MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
489MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
490MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
491MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
492MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
493MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
494MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
495MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
496MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
497MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
498MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
499MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
500MX28_PAD_LCD_D00__GPIO_1_0 0x1003
501MX28_PAD_LCD_D01__GPIO_1_1 0x1013
502MX28_PAD_LCD_D02__GPIO_1_2 0x1023
503MX28_PAD_LCD_D03__GPIO_1_3 0x1033
504MX28_PAD_LCD_D04__GPIO_1_4 0x1043
505MX28_PAD_LCD_D05__GPIO_1_5 0x1053
506MX28_PAD_LCD_D06__GPIO_1_6 0x1063
507MX28_PAD_LCD_D07__GPIO_1_7 0x1073
508MX28_PAD_LCD_D08__GPIO_1_8 0x1083
509MX28_PAD_LCD_D09__GPIO_1_9 0x1093
510MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
511MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
512MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
513MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
514MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
515MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
516MX28_PAD_LCD_D16__GPIO_1_16 0x1103
517MX28_PAD_LCD_D17__GPIO_1_17 0x1113
518MX28_PAD_LCD_D18__GPIO_1_18 0x1123
519MX28_PAD_LCD_D19__GPIO_1_19 0x1133
520MX28_PAD_LCD_D20__GPIO_1_20 0x1143
521MX28_PAD_LCD_D21__GPIO_1_21 0x1153
522MX28_PAD_LCD_D22__GPIO_1_22 0x1163
523MX28_PAD_LCD_D23__GPIO_1_23 0x1173
524MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
525MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
526MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
527MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
528MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
529MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
530MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
531MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
532MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
533MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
534MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
535MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
536MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
537MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
538MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
539MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
540MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
541MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
542MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
543MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
544MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
545MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
546MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
547MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
548MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
549MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
550MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
551MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
552MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
553MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
554MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
555MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
556MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
557MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
558MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
559MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
560MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
561MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
562MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
563MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
564MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
565MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
566MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
567MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
568MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
569MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
570MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
571MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
572MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
573MX28_PAD_PWM0__GPIO_3_16 0x3103
574MX28_PAD_PWM1__GPIO_3_17 0x3113
575MX28_PAD_PWM2__GPIO_3_18 0x3123
576MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
577MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
578MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
579MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
580MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
581MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
582MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
583MX28_PAD_SPDIF__GPIO_3_27 0x31b3
584MX28_PAD_PWM3__GPIO_3_28 0x31c3
585MX28_PAD_PWM4__GPIO_3_29 0x31d3
586MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
587MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
588MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
589MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
590MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
591MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
592MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
593MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
594MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
595MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
596MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
597MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
598MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
599MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
600MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
601MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
602MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
603MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
604MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
605
606Valid values for i.MX23 pinmux-id:
607
608pinmux id
609------ --
610MX23_PAD_GPMI_D00__GPMI_D00 0x0000
611MX23_PAD_GPMI_D01__GPMI_D01 0x0010
612MX23_PAD_GPMI_D02__GPMI_D02 0x0020
613MX23_PAD_GPMI_D03__GPMI_D03 0x0030
614MX23_PAD_GPMI_D04__GPMI_D04 0x0040
615MX23_PAD_GPMI_D05__GPMI_D05 0x0050
616MX23_PAD_GPMI_D06__GPMI_D06 0x0060
617MX23_PAD_GPMI_D07__GPMI_D07 0x0070
618MX23_PAD_GPMI_D08__GPMI_D08 0x0080
619MX23_PAD_GPMI_D09__GPMI_D09 0x0090
620MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
621MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
622MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
623MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
624MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
625MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
626MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
627MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
628MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
629MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
630MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
631MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
632MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
633MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
634MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
635MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
636MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
637MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
638MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
639MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
640MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
641MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
642MX23_PAD_LCD_D00__LCD_D00 0x1000
643MX23_PAD_LCD_D01__LCD_D01 0x1010
644MX23_PAD_LCD_D02__LCD_D02 0x1020
645MX23_PAD_LCD_D03__LCD_D03 0x1030
646MX23_PAD_LCD_D04__LCD_D04 0x1040
647MX23_PAD_LCD_D05__LCD_D05 0x1050
648MX23_PAD_LCD_D06__LCD_D06 0x1060
649MX23_PAD_LCD_D07__LCD_D07 0x1070
650MX23_PAD_LCD_D08__LCD_D08 0x1080
651MX23_PAD_LCD_D09__LCD_D09 0x1090
652MX23_PAD_LCD_D10__LCD_D10 0x10a0
653MX23_PAD_LCD_D11__LCD_D11 0x10b0
654MX23_PAD_LCD_D12__LCD_D12 0x10c0
655MX23_PAD_LCD_D13__LCD_D13 0x10d0
656MX23_PAD_LCD_D14__LCD_D14 0x10e0
657MX23_PAD_LCD_D15__LCD_D15 0x10f0
658MX23_PAD_LCD_D16__LCD_D16 0x1100
659MX23_PAD_LCD_D17__LCD_D17 0x1110
660MX23_PAD_LCD_RESET__LCD_RESET 0x1120
661MX23_PAD_LCD_RS__LCD_RS 0x1130
662MX23_PAD_LCD_WR__LCD_WR 0x1140
663MX23_PAD_LCD_CS__LCD_CS 0x1150
664MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
665MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
666MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
667MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
668MX23_PAD_PWM0__PWM0 0x11a0
669MX23_PAD_PWM1__PWM1 0x11b0
670MX23_PAD_PWM2__PWM2 0x11c0
671MX23_PAD_PWM3__PWM3 0x11d0
672MX23_PAD_PWM4__PWM4 0x11e0
673MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
674MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
675MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
676MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
677MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
678MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
679MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
680MX23_PAD_ROTARYA__ROTARYA 0x2070
681MX23_PAD_ROTARYB__ROTARYB 0x2080
682MX23_PAD_EMI_A00__EMI_A00 0x2090
683MX23_PAD_EMI_A01__EMI_A01 0x20a0
684MX23_PAD_EMI_A02__EMI_A02 0x20b0
685MX23_PAD_EMI_A03__EMI_A03 0x20c0
686MX23_PAD_EMI_A04__EMI_A04 0x20d0
687MX23_PAD_EMI_A05__EMI_A05 0x20e0
688MX23_PAD_EMI_A06__EMI_A06 0x20f0
689MX23_PAD_EMI_A07__EMI_A07 0x2100
690MX23_PAD_EMI_A08__EMI_A08 0x2110
691MX23_PAD_EMI_A09__EMI_A09 0x2120
692MX23_PAD_EMI_A10__EMI_A10 0x2130
693MX23_PAD_EMI_A11__EMI_A11 0x2140
694MX23_PAD_EMI_A12__EMI_A12 0x2150
695MX23_PAD_EMI_BA0__EMI_BA0 0x2160
696MX23_PAD_EMI_BA1__EMI_BA1 0x2170
697MX23_PAD_EMI_CASN__EMI_CASN 0x2180
698MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
699MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
700MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
701MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
702MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
703MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
704MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
705MX23_PAD_EMI_D00__EMI_D00 0x3000
706MX23_PAD_EMI_D01__EMI_D01 0x3010
707MX23_PAD_EMI_D02__EMI_D02 0x3020
708MX23_PAD_EMI_D03__EMI_D03 0x3030
709MX23_PAD_EMI_D04__EMI_D04 0x3040
710MX23_PAD_EMI_D05__EMI_D05 0x3050
711MX23_PAD_EMI_D06__EMI_D06 0x3060
712MX23_PAD_EMI_D07__EMI_D07 0x3070
713MX23_PAD_EMI_D08__EMI_D08 0x3080
714MX23_PAD_EMI_D09__EMI_D09 0x3090
715MX23_PAD_EMI_D10__EMI_D10 0x30a0
716MX23_PAD_EMI_D11__EMI_D11 0x30b0
717MX23_PAD_EMI_D12__EMI_D12 0x30c0
718MX23_PAD_EMI_D13__EMI_D13 0x30d0
719MX23_PAD_EMI_D14__EMI_D14 0x30e0
720MX23_PAD_EMI_D15__EMI_D15 0x30f0
721MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
722MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
723MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
724MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
725MX23_PAD_EMI_CLK__EMI_CLK 0x3140
726MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
727MX23_PAD_GPMI_D00__LCD_D8 0x0001
728MX23_PAD_GPMI_D01__LCD_D9 0x0011
729MX23_PAD_GPMI_D02__LCD_D10 0x0021
730MX23_PAD_GPMI_D03__LCD_D11 0x0031
731MX23_PAD_GPMI_D04__LCD_D12 0x0041
732MX23_PAD_GPMI_D05__LCD_D13 0x0051
733MX23_PAD_GPMI_D06__LCD_D14 0x0061
734MX23_PAD_GPMI_D07__LCD_D15 0x0071
735MX23_PAD_GPMI_D08__LCD_D18 0x0081
736MX23_PAD_GPMI_D09__LCD_D19 0x0091
737MX23_PAD_GPMI_D10__LCD_D20 0x00a1
738MX23_PAD_GPMI_D11__LCD_D21 0x00b1
739MX23_PAD_GPMI_D12__LCD_D22 0x00c1
740MX23_PAD_GPMI_D13__LCD_D23 0x00d1
741MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
742MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
743MX23_PAD_GPMI_CLE__LCD_D16 0x0101
744MX23_PAD_GPMI_ALE__LCD_D17 0x0111
745MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
746MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
747MX23_PAD_AUART1_RX__IR_RX 0x01c1
748MX23_PAD_AUART1_TX__IR_TX 0x01d1
749MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
750MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
751MX23_PAD_LCD_D00__ETM_DA8 0x1001
752MX23_PAD_LCD_D01__ETM_DA9 0x1011
753MX23_PAD_LCD_D02__ETM_DA10 0x1021
754MX23_PAD_LCD_D03__ETM_DA11 0x1031
755MX23_PAD_LCD_D04__ETM_DA12 0x1041
756MX23_PAD_LCD_D05__ETM_DA13 0x1051
757MX23_PAD_LCD_D06__ETM_DA14 0x1061
758MX23_PAD_LCD_D07__ETM_DA15 0x1071
759MX23_PAD_LCD_D08__ETM_DA0 0x1081
760MX23_PAD_LCD_D09__ETM_DA1 0x1091
761MX23_PAD_LCD_D10__ETM_DA2 0x10a1
762MX23_PAD_LCD_D11__ETM_DA3 0x10b1
763MX23_PAD_LCD_D12__ETM_DA4 0x10c1
764MX23_PAD_LCD_D13__ETM_DA5 0x10d1
765MX23_PAD_LCD_D14__ETM_DA6 0x10e1
766MX23_PAD_LCD_D15__ETM_DA7 0x10f1
767MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
768MX23_PAD_LCD_RS__ETM_TCLK 0x1131
769MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
770MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
771MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
772MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
773MX23_PAD_PWM0__ROTARYA 0x11a1
774MX23_PAD_PWM1__ROTARYB 0x11b1
775MX23_PAD_PWM2__GPMI_RDY3 0x11c1
776MX23_PAD_PWM3__ETM_TCTL 0x11d1
777MX23_PAD_PWM4__ETM_TCLK 0x11e1
778MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
779MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
780MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
781MX23_PAD_ROTARYA__AUART2_RTS 0x2071
782MX23_PAD_ROTARYB__AUART2_CTS 0x2081
783MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
784MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
785MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
786MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
787MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
788MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
789MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
790MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
791MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
792MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
793MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
794MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
795MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
796MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
797MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
798MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
799MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
800MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
801MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
802MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
803MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
804MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
805MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
806MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
807MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
808MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
809MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
810MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
811MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
812MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
813MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
814MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
815MX23_PAD_PWM0__DUART_RX 0x11a2
816MX23_PAD_PWM1__DUART_TX 0x11b2
817MX23_PAD_PWM3__AUART1_CTS 0x11d2
818MX23_PAD_PWM4__AUART1_RTS 0x11e2
819MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
820MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
821MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
822MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
823MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
824MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
825MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
826MX23_PAD_ROTARYA__SPDIF 0x2072
827MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
828MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
829MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
830MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
831MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
832MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
833MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
834MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
835MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
836MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
837MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
838MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
839MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
840MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
841MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
842MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
843MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
844MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
845MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
846MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
847MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
848MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
849MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
850MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
851MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
852MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
853MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
854MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
855MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
856MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
857MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
858MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
859MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
860MX23_PAD_LCD_D00__GPIO_1_0 0x1003
861MX23_PAD_LCD_D01__GPIO_1_1 0x1013
862MX23_PAD_LCD_D02__GPIO_1_2 0x1023
863MX23_PAD_LCD_D03__GPIO_1_3 0x1033
864MX23_PAD_LCD_D04__GPIO_1_4 0x1043
865MX23_PAD_LCD_D05__GPIO_1_5 0x1053
866MX23_PAD_LCD_D06__GPIO_1_6 0x1063
867MX23_PAD_LCD_D07__GPIO_1_7 0x1073
868MX23_PAD_LCD_D08__GPIO_1_8 0x1083
869MX23_PAD_LCD_D09__GPIO_1_9 0x1093
870MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
871MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
872MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
873MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
874MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
875MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
876MX23_PAD_LCD_D16__GPIO_1_16 0x1103
877MX23_PAD_LCD_D17__GPIO_1_17 0x1113
878MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
879MX23_PAD_LCD_RS__GPIO_1_19 0x1133
880MX23_PAD_LCD_WR__GPIO_1_20 0x1143
881MX23_PAD_LCD_CS__GPIO_1_21 0x1153
882MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
883MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
884MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
885MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
886MX23_PAD_PWM0__GPIO_1_26 0x11a3
887MX23_PAD_PWM1__GPIO_1_27 0x11b3
888MX23_PAD_PWM2__GPIO_1_28 0x11c3
889MX23_PAD_PWM3__GPIO_1_29 0x11d3
890MX23_PAD_PWM4__GPIO_1_30 0x11e3
891MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
892MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
893MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
894MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
895MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
896MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
897MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
898MX23_PAD_ROTARYA__GPIO_2_7 0x2073
899MX23_PAD_ROTARYB__GPIO_2_8 0x2083
900MX23_PAD_EMI_A00__GPIO_2_9 0x2093
901MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
902MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
903MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
904MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
905MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
906MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
907MX23_PAD_EMI_A07__GPIO_2_16 0x2103
908MX23_PAD_EMI_A08__GPIO_2_17 0x2113
909MX23_PAD_EMI_A09__GPIO_2_18 0x2123
910MX23_PAD_EMI_A10__GPIO_2_19 0x2133
911MX23_PAD_EMI_A11__GPIO_2_20 0x2143
912MX23_PAD_EMI_A12__GPIO_2_21 0x2153
913MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
914MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
915MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
916MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
917MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
918MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
919MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
920MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
921MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
922MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 5a02e30dd262..7069a0b84e3a 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -72,6 +72,13 @@ Optional properties:
72 /* pin base, nr pins & gpio function */ 72 /* pin base, nr pins & gpio function */
73 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>; 73 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
74 74
75- interrupt-controller : standard interrupt controller binding if using
76 interrupts for wake-up events for example. In this case pinctrl-single
77 is set up as a chained interrupt controller and the wake-up interrupts
78 can be requested by the drivers using request_irq().
79
80- #interrupt-cells : standard interrupt binding if using interrupts
81
75This driver assumes that there is only one register for each pin (unless the 82This driver assumes that there is only one register for each pin (unless the
76pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as 83pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
77specified in the pinctrl-bindings.txt document in this directory. 84specified in the pinctrl-bindings.txt document in this directory.
@@ -121,6 +128,8 @@ pmx_core: pinmux@4a100040 {
121 reg = <0x4a100040 0x0196>; 128 reg = <0x4a100040 0x0196>;
122 #address-cells = <1>; 129 #address-cells = <1>;
123 #size-cells = <0>; 130 #size-cells = <0>;
131 #interrupt-cells = <1>;
132 interrupt-controller;
124 pinctrl-single,register-width = <16>; 133 pinctrl-single,register-width = <16>;
125 pinctrl-single,function-mask = <0xffff>; 134 pinctrl-single,function-mask = <0xffff>;
126}; 135};
@@ -131,6 +140,8 @@ pmx_wkup: pinmux@4a31e040 {
131 reg = <0x4a31e040 0x0038>; 140 reg = <0x4a31e040 0x0038>;
132 #address-cells = <1>; 141 #address-cells = <1>;
133 #size-cells = <0>; 142 #size-cells = <0>;
143 #interrupt-cells = <1>;
144 interrupt-controller;
134 pinctrl-single,register-width = <16>; 145 pinctrl-single,register-width = <16>;
135 pinctrl-single,function-mask = <0xffff>; 146 pinctrl-single,function-mask = <0xffff>;
136}; 147};
diff --git a/Documentation/devicetree/bindings/usb/ux500-usb.txt b/Documentation/devicetree/bindings/usb/ux500-usb.txt
index 330d6ec15401..439a41c79afa 100644
--- a/Documentation/devicetree/bindings/usb/ux500-usb.txt
+++ b/Documentation/devicetree/bindings/usb/ux500-usb.txt
@@ -15,7 +15,7 @@ Optional properties:
15Example: 15Example:
16 16
17usb_per5@a03e0000 { 17usb_per5@a03e0000 {
18 compatible = "stericsson,db8500-musb", "mentor,musb"; 18 compatible = "stericsson,db8500-musb";
19 reg = <0xa03e0000 0x10000>; 19 reg = <0xa03e0000 0x10000>;
20 interrupts = <0 23 0x4>; 20 interrupts = <0 23 0x4>;
21 interrupt-names = "mc"; 21 interrupt-names = "mc";
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983be3c30..50decf8e1b90 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,19 @@ Required properties:
12 a) phandle of the gpio controller node. 12 a) phandle of the gpio controller node.
13 b) pin number within the gpio controller. 13 b) pin number within the gpio controller.
14 c) optional flags and pull up/down. 14 c) optional flags and pull up/down.
15 15- clocks: list of clock IDs from SoC clock driver.
16 a) hdmi: Gate of HDMI IP bus clock.
17 b) sclk_hdmi: Gate of HDMI special clock.
18 c) sclk_pixel: Pixel special clock, one of the two possible inputs of
19 HDMI clock mux.
20 d) sclk_hdmiphy: HDMI PHY clock output, one of two possible inputs of
21 HDMI clock mux.
22 e) mout_hdmi: It is required by the driver to switch between the 2
23 parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
24 after configuration, parent is set to sclk_hdmiphy else
25 sclk_pixel.
26- clock-names: aliases as per driver requirements for above clock IDs:
27 "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
16Example: 28Example:
17 29
18 hdmi { 30 hdmi {
diff --git a/Documentation/devicetree/bindings/video/exynos_mixer.txt b/Documentation/devicetree/bindings/video/exynos_mixer.txt
index 3334b0a8e343..7bfde9c9d658 100644
--- a/Documentation/devicetree/bindings/video/exynos_mixer.txt
+++ b/Documentation/devicetree/bindings/video/exynos_mixer.txt
@@ -10,6 +10,10 @@ Required properties:
10- reg: physical base address of the mixer and length of memory mapped 10- reg: physical base address of the mixer and length of memory mapped
11 region. 11 region.
12- interrupts: interrupt number to the cpu. 12- interrupts: interrupt number to the cpu.
13- clocks: list of clock IDs from SoC clock driver.
14 a) mixer: Gate of Mixer IP bus clock.
15 b) sclk_hdmi: HDMI Special clock, one of the two possible inputs of
16 mixer mux.
13 17
14Example: 18Example:
15 19
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a00136a0439..4d66a03e4f57 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -933,7 +933,7 @@ M: Javier Martinez Canillas <javier@dowhile0.org>
933L: linux-omap@vger.kernel.org 933L: linux-omap@vger.kernel.org
934L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 934L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
935S: Maintained 935S: Maintained
936F: arch/arm/mach-omap2/board-igep0020.c 936F: arch/arm/boot/dts/omap3-igep*
937 937
938ARM/INCOME PXA270 SUPPORT 938ARM/INCOME PXA270 SUPPORT
939M: Marek Vasut <marek.vasut@gmail.com> 939M: Marek Vasut <marek.vasut@gmail.com>
@@ -6125,6 +6125,12 @@ L: linux-omap@vger.kernel.org
6125S: Maintained 6125S: Maintained
6126F: drivers/gpio/gpio-omap.c 6126F: drivers/gpio/gpio-omap.c
6127 6127
6128OMAP/NEWFLOW NANOBONE MACHINE SUPPORT
6129M: Mark Jackson <mpfj@newflow.co.uk>
6130L: linux-omap@vger.kernel.org
6131S: Maintained
6132F: arch/arm/boot/dts/am335x-nano.dts
6133
6128OMFS FILESYSTEM 6134OMFS FILESYSTEM
6129M: Bob Copeland <me@bobcopeland.com> 6135M: Bob Copeland <me@bobcopeland.com>
6130L: linux-karma-devel@lists.sourceforge.net 6136L: linux-karma-devel@lists.sourceforge.net
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7662b71628cd..d57c1a65b24f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -40,17 +40,17 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
40dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb 40dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
41dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb 41dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
42dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb 42dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
43
44dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 43dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
45
46dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 44dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
47dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \ 45dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
48 bcm28155-ap.dtb 46 bcm28155-ap.dtb
47dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
49dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ 48dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
50 da850-evm.dtb 49 da850-evm.dtb
51dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ 50dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
52 dove-cubox.dtb \ 51 dove-cubox.dtb \
53 dove-d2plug.dtb \ 52 dove-d2plug.dtb \
53 dove-d3plug.dtb \
54 dove-dove-db.dtb 54 dove-dove-db.dtb
55dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 55dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
56 exynos4210-smdkv310.dtb \ 56 exynos4210-smdkv310.dtb \
@@ -96,22 +96,25 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
96 kirkwood-ns2mini.dtb \ 96 kirkwood-ns2mini.dtb \
97 kirkwood-nsa310.dtb \ 97 kirkwood-nsa310.dtb \
98 kirkwood-nsa310a.dtb \ 98 kirkwood-nsa310a.dtb \
99 kirkwood-openblocks_a6.dtb \
100 kirkwood-openblocks_a7.dtb \
99 kirkwood-sheevaplug.dtb \ 101 kirkwood-sheevaplug.dtb \
100 kirkwood-sheevaplug-esata.dtb \ 102 kirkwood-sheevaplug-esata.dtb \
101 kirkwood-topkick.dtb \ 103 kirkwood-topkick.dtb \
102 kirkwood-ts219-6281.dtb \ 104 kirkwood-ts219-6281.dtb \
103 kirkwood-ts219-6282.dtb \ 105 kirkwood-ts219-6282.dtb
104 kirkwood-openblocks_a6.dtb
105dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 106dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
106dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ 107dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
107 qcom-msm8960-cdp.dtb 108 qcom-msm8960-cdp.dtb
108dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ 109dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
109 armada-370-mirabox.dtb \ 110 armada-370-mirabox.dtb \
110 armada-370-netgear-rn102.dtb \ 111 armada-370-netgear-rn102.dtb \
112 armada-370-netgear-rn104.dtb \
111 armada-370-rd.dtb \ 113 armada-370-rd.dtb \
112 armada-xp-axpwifiap.dtb \ 114 armada-xp-axpwifiap.dtb \
113 armada-xp-db.dtb \ 115 armada-xp-db.dtb \
114 armada-xp-gp.dtb \ 116 armada-xp-gp.dtb \
117 armada-xp-matrix.dtb \
115 armada-xp-openblocks-ax3-4.dtb 118 armada-xp-openblocks-ax3-4.dtb
116dtb-$(CONFIG_ARCH_MXC) += \ 119dtb-$(CONFIG_ARCH_MXC) += \
117 imx25-karo-tx25.dtb \ 120 imx25-karo-tx25.dtb \
@@ -142,8 +145,10 @@ dtb-$(CONFIG_ARCH_MXC) += \
142 imx6q-sabrelite.dtb \ 145 imx6q-sabrelite.dtb \
143 imx6q-sabresd.dtb \ 146 imx6q-sabresd.dtb \
144 imx6q-sbc6x.dtb \ 147 imx6q-sbc6x.dtb \
148 imx6q-udoo.dtb \
145 imx6q-wandboard.dtb \ 149 imx6q-wandboard.dtb \
146 imx6sl-evk.dtb \ 150 imx6sl-evk.dtb \
151 vf610-cosmic.dtb \
147 vf610-twr.dtb 152 vf610-twr.dtb
148dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 153dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
149 imx23-olinuxino.dtb \ 154 imx23-olinuxino.dtb \
@@ -159,6 +164,7 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
159 imx28-cfa10057.dtb \ 164 imx28-cfa10057.dtb \
160 imx28-cfa10058.dtb \ 165 imx28-cfa10058.dtb \
161 imx28-evk.dtb \ 166 imx28-evk.dtb \
167 imx28-m28cu3.dtb \
162 imx28-m28evk.dtb \ 168 imx28-m28evk.dtb \
163 imx28-sps1.dtb \ 169 imx28-sps1.dtb \
164 imx28-tx28.dtb 170 imx28-tx28.dtb
@@ -172,9 +178,15 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
172 omap3-devkit8000.dtb \ 178 omap3-devkit8000.dtb \
173 omap3-beagle-xm.dtb \ 179 omap3-beagle-xm.dtb \
174 omap3-evm.dtb \ 180 omap3-evm.dtb \
181 omap3-evm-37xx.dtb \
182 omap3-n900.dtb \
183 omap3-n9.dtb \
184 omap3-n950.dtb \
175 omap3-tobi.dtb \ 185 omap3-tobi.dtb \
186 omap3-gta04.dtb \
176 omap3-igep0020.dtb \ 187 omap3-igep0020.dtb \
177 omap3-igep0030.dtb \ 188 omap3-igep0030.dtb \
189 omap3-zoom3.dtb \
178 omap4-panda.dtb \ 190 omap4-panda.dtb \
179 omap4-panda-a4.dtb \ 191 omap4-panda-a4.dtb \
180 omap4-panda-es.dtb \ 192 omap4-panda-es.dtb \
@@ -186,17 +198,24 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
186 am335x-evmsk.dtb \ 198 am335x-evmsk.dtb \
187 am335x-bone.dtb \ 199 am335x-bone.dtb \
188 am335x-boneblack.dtb \ 200 am335x-boneblack.dtb \
201 am335x-nano.dtb \
202 am335x-base0033.dtb \
189 am3517-evm.dtb \ 203 am3517-evm.dtb \
190 am3517_mt_ventoux.dtb \ 204 am3517_mt_ventoux.dtb \
191 am43x-epos-evm.dtb 205 am43x-epos-evm.dtb \
206 dra7-evm.dtb
192dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb 207dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
193dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 208dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
194dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ 209dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
195 ste-hrefprev60.dtb \ 210 ste-hrefprev60-stuib.dtb \
196 ste-hrefv60plus.dtb \ 211 ste-hrefprev60-tvk.dtb \
212 ste-hrefv60plus-stuib.dtb \
213 ste-hrefv60plus-tvk.dtb \
197 ste-ccu8540.dtb \ 214 ste-ccu8540.dtb \
198 ste-ccu9540.dtb 215 ste-ccu9540.dtb
199dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 216dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
217dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
218 s3c6410-smdk6410.dtb
200dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 219dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
201 r7s72100-genmai.dtb \ 220 r7s72100-genmai.dtb \
202 r8a7740-armadillo800eva.dtb \ 221 r8a7740-armadillo800eva.dtb \
@@ -214,7 +233,9 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
214 r8a73a4-ape6evm-reference.dtb \ 233 r8a73a4-ape6evm-reference.dtb \
215 sh7372-mackerel.dtb 234 sh7372-mackerel.dtb
216dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb 235dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb
217dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ 236dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
237 socfpga_cyclone5_socdk.dtb \
238 socfpga_cyclone5_sockit.dtb \
218 socfpga_vt.dtb 239 socfpga_vt.dtb
219dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ 240dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
220 spear1340-evb.dtb 241 spear1340-evb.dtb
@@ -236,6 +257,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
236 sun5i-a13-olinuxino.dtb \ 257 sun5i-a13-olinuxino.dtb \
237 sun6i-a31-colombus.dtb \ 258 sun6i-a31-colombus.dtb \
238 sun7i-a20-cubieboard2.dtb \ 259 sun7i-a20-cubieboard2.dtb \
260 sun7i-a20-cubietruck.dtb \
239 sun7i-a20-olinuxino-micro.dtb 261 sun7i-a20-olinuxino-micro.dtb
240dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 262dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
241 tegra20-iris-512.dtb \ 263 tegra20-iris-512.dtb \
@@ -250,7 +272,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
250 tegra30-beaver.dtb \ 272 tegra30-beaver.dtb \
251 tegra30-cardhu-a02.dtb \ 273 tegra30-cardhu-a02.dtb \
252 tegra30-cardhu-a04.dtb \ 274 tegra30-cardhu-a04.dtb \
253 tegra114-dalmore.dtb 275 tegra114-dalmore.dtb \
276 tegra124-venice2.dtb
254dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ 277dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
255 versatile-pb.dtb 278 versatile-pb.dtb
256dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb 279dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts
new file mode 100644
index 000000000000..b4f95c2bbf74
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-base0033.dts
@@ -0,0 +1,16 @@
1/*
2 * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION
3 *
4 * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include "am335x-igep0033.dtsi"
12
13/ {
14 model = "IGEP COM AM335x on AQUILA Expansion";
15 compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
16};
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 2f66deda9f5c..e3f27ec31718 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -21,177 +21,205 @@
21 reg = <0x80000000 0x10000000>; /* 256 MB */ 21 reg = <0x80000000 0x10000000>; /* 256 MB */
22 }; 22 };
23 23
24 am33xx_pinmux: pinmux@44e10800 { 24 leds {
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&clkout2_pin>; 26 pinctrl-0 = <&user_leds_s0>;
27
28 user_leds_s0: user_leds_s0 {
29 pinctrl-single,pins = <
30 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
31 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
32 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
33 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
34 >;
35 };
36 27
37 i2c0_pins: pinmux_i2c0_pins { 28 compatible = "gpio-leds";
38 pinctrl-single,pins = <
39 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
40 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
41 >;
42 };
43 29
44 uart0_pins: pinmux_uart0_pins { 30 led@2 {
45 pinctrl-single,pins = < 31 label = "beaglebone:green:heartbeat";
46 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 32 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
47 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 33 linux,default-trigger = "heartbeat";
48 >; 34 default-state = "off";
49 }; 35 };
50 36
51 clkout2_pin: pinmux_clkout2_pin { 37 led@3 {
52 pinctrl-single,pins = < 38 label = "beaglebone:green:mmc0";
53 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 39 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
54 >; 40 linux,default-trigger = "mmc0";
41 default-state = "off";
55 }; 42 };
56 43
57 cpsw_default: cpsw_default { 44 led@4 {
58 pinctrl-single,pins = < 45 label = "beaglebone:green:usr2";
59 /* Slave 1 */ 46 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
60 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ 47 linux,default-trigger = "cpu0";
61 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ 48 default-state = "off";
62 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
63 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
64 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
65 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
66 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
67 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
68 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
69 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
70 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
71 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
72 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
73 >;
74 }; 49 };
75 50
76 cpsw_sleep: cpsw_sleep { 51 led@5 {
77 pinctrl-single,pins = < 52 label = "beaglebone:green:usr3";
78 /* Slave 1 reset value */ 53 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
79 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) 54 linux,default-trigger = "mmc1";
80 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 55 default-state = "off";
81 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
82 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
83 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
84 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
85 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
86 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
87 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
88 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
89 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
90 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
91 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
92 >;
93 }; 56 };
57 };
94 58
95 davinci_mdio_default: davinci_mdio_default { 59 vmmcsd_fixed: fixedregulator@0 {
96 pinctrl-single,pins = < 60 compatible = "regulator-fixed";
97 /* MDIO */ 61 regulator-name = "vmmcsd_fixed";
98 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 62 regulator-min-microvolt = <3300000>;
99 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 63 regulator-max-microvolt = <3300000>;
100 >; 64 };
101 }; 65};
102 66
103 davinci_mdio_sleep: davinci_mdio_sleep { 67&am33xx_pinmux {
104 pinctrl-single,pins = < 68 pinctrl-names = "default";
105 /* MDIO reset value */ 69 pinctrl-0 = <&clkout2_pin>;
106 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 70
107 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 71 user_leds_s0: user_leds_s0 {
108 >; 72 pinctrl-single,pins = <
109 }; 73 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
74 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
75 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
76 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
77 >;
110 }; 78 };
111 79
112 ocp { 80 i2c0_pins: pinmux_i2c0_pins {
113 uart0: serial@44e09000 { 81 pinctrl-single,pins = <
114 pinctrl-names = "default"; 82 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
115 pinctrl-0 = <&uart0_pins>; 83 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
84 >;
85 };
116 86
117 status = "okay"; 87 uart0_pins: pinmux_uart0_pins {
118 }; 88 pinctrl-single,pins = <
89 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
90 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
91 >;
92 };
119 93
120 musb: usb@47400000 { 94 clkout2_pin: pinmux_clkout2_pin {
121 status = "okay"; 95 pinctrl-single,pins = <
96 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
97 >;
98 };
122 99
123 control@44e10000 { 100 cpsw_default: cpsw_default {
124 status = "okay"; 101 pinctrl-single,pins = <
125 }; 102 /* Slave 1 */
103 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
104 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
105 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
106 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
107 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
108 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
109 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
110 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
111 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
112 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
113 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
114 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
115 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
116 >;
117 };
126 118
127 usb-phy@47401300 { 119 cpsw_sleep: cpsw_sleep {
128 status = "okay"; 120 pinctrl-single,pins = <
129 }; 121 /* Slave 1 reset value */
122 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
123 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
124 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
125 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
126 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
127 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
128 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
129 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
130 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
131 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
135 >;
136 };
130 137
131 usb-phy@47401b00 { 138 davinci_mdio_default: davinci_mdio_default {
132 status = "okay"; 139 pinctrl-single,pins = <
133 }; 140 /* MDIO */
141 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
142 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
143 >;
144 };
134 145
135 usb@47401000 { 146 davinci_mdio_sleep: davinci_mdio_sleep {
136 status = "okay"; 147 pinctrl-single,pins = <
137 }; 148 /* MDIO reset value */
149 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
150 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
151 >;
152 };
138 153
139 usb@47401800 { 154 mmc1_pins: pinmux_mmc1_pins {
140 status = "okay"; 155 pinctrl-single,pins = <
141 dr_mode = "host"; 156 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
142 }; 157 >;
158 };
143 159
144 dma-controller@07402000 { 160 emmc_pins: pinmux_emmc_pins {
145 status = "okay"; 161 pinctrl-single,pins = <
146 }; 162 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
147 }; 163 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
164 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
165 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
166 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
167 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
168 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
169 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
170 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
171 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
172 >;
173 };
174};
148 175
149 i2c0: i2c@44e0b000 { 176&uart0 {
150 pinctrl-names = "default"; 177 pinctrl-names = "default";
151 pinctrl-0 = <&i2c0_pins>; 178 pinctrl-0 = <&uart0_pins>;
152 179
153 status = "okay"; 180 status = "okay";
154 clock-frequency = <400000>; 181};
155 182
156 tps: tps@24 { 183&usb {
157 reg = <0x24>; 184 status = "okay";
158 };
159 185
160 }; 186 control@44e10000 {
187 status = "okay";
161 }; 188 };
162 189
163 leds { 190 usb-phy@47401300 {
164 pinctrl-names = "default"; 191 status = "okay";
165 pinctrl-0 = <&user_leds_s0>; 192 };
166 193
167 compatible = "gpio-leds"; 194 usb-phy@47401b00 {
195 status = "okay";
196 };
168 197
169 led@2 { 198 usb@47401000 {
170 label = "beaglebone:green:heartbeat"; 199 status = "okay";
171 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 200 };
172 linux,default-trigger = "heartbeat";
173 default-state = "off";
174 };
175 201
176 led@3 { 202 usb@47401800 {
177 label = "beaglebone:green:mmc0"; 203 status = "okay";
178 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; 204 dr_mode = "host";
179 linux,default-trigger = "mmc0"; 205 };
180 default-state = "off";
181 };
182 206
183 led@4 { 207 dma-controller@07402000 {
184 label = "beaglebone:green:usr2"; 208 status = "okay";
185 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 209 };
186 default-state = "off"; 210};
187 };
188 211
189 led@5 { 212&i2c0 {
190 label = "beaglebone:green:usr3"; 213 pinctrl-names = "default";
191 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 214 pinctrl-0 = <&i2c0_pins>;
192 default-state = "off"; 215
193 }; 216 status = "okay";
217 clock-frequency = <400000>;
218
219 tps: tps@24 {
220 reg = <0x24>;
194 }; 221 };
222
195}; 223};
196 224
197/include/ "tps65217.dtsi" 225/include/ "tps65217.dtsi"
@@ -260,3 +288,12 @@
260 pinctrl-0 = <&davinci_mdio_default>; 288 pinctrl-0 = <&davinci_mdio_default>;
261 pinctrl-1 = <&davinci_mdio_sleep>; 289 pinctrl-1 = <&davinci_mdio_sleep>;
262}; 290};
291
292&mmc1 {
293 status = "okay";
294 bus-width = <0x4>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&mmc1_pins>;
297 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
298 cd-inverted;
299};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 7993c489982c..94ee427a6db1 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -9,3 +9,21 @@
9 9
10#include "am33xx.dtsi" 10#include "am33xx.dtsi"
11#include "am335x-bone-common.dtsi" 11#include "am335x-bone-common.dtsi"
12
13&ldo3_reg {
14 regulator-min-microvolt = <1800000>;
15 regulator-max-microvolt = <3300000>;
16 regulator-always-on;
17};
18
19&mmc1 {
20 vmmc-supply = <&ldo3_reg>;
21};
22
23&sham {
24 status = "okay";
25};
26
27&aes {
28 status = "okay";
29};
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 197cadf72d2c..6b71ad95a5cf 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -15,3 +15,64 @@
15 regulator-max-microvolt = <1800000>; 15 regulator-max-microvolt = <1800000>;
16 regulator-always-on; 16 regulator-always-on;
17}; 17};
18
19&mmc1 {
20 vmmc-supply = <&vmmcsd_fixed>;
21};
22
23&mmc2 {
24 vmmc-supply = <&vmmcsd_fixed>;
25 pinctrl-names = "default";
26 pinctrl-0 = <&emmc_pins>;
27 bus-width = <8>;
28 status = "okay";
29 ti,vcc-aux-disable-is-sleep;
30};
31
32&am33xx_pinmux {
33 nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
34 pinctrl-single,pins = <
35 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
36 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
37 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
38 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
39 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
40 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
41 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
42 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
43 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
44 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
45 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
46 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
47 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
48 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
49 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
50 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
51 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
52 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
53 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
54 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
55 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
56 >;
57 };
58 nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
59 pinctrl-single,pins = <
60 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
61 >;
62 };
63};
64
65&lcdc {
66 status = "okay";
67};
68
69/ {
70 hdmi {
71 compatible = "ti,tilcdc,slave";
72 i2c = <&i2c0>;
73 pinctrl-names = "default", "off";
74 pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
75 pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
76 status = "okay";
77 };
78};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index e8ec8756e498..987429436171 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -24,324 +24,6 @@
24 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 }; 25 };
26 26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
30
31 matrix_keypad_s0: matrix_keypad_s0 {
32 pinctrl-single,pins = <
33 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
34 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
35 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
36 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
37 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
38 >;
39 };
40
41 volume_keys_s0: volume_keys_s0 {
42 pinctrl-single,pins = <
43 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
44 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
45 >;
46 };
47
48 i2c0_pins: pinmux_i2c0_pins {
49 pinctrl-single,pins = <
50 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
51 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
52 >;
53 };
54
55 i2c1_pins: pinmux_i2c1_pins {
56 pinctrl-single,pins = <
57 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
58 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
59 >;
60 };
61
62 uart0_pins: pinmux_uart0_pins {
63 pinctrl-single,pins = <
64 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
65 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
66 >;
67 };
68
69 clkout2_pin: pinmux_clkout2_pin {
70 pinctrl-single,pins = <
71 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
72 >;
73 };
74
75 nandflash_pins_s0: nandflash_pins_s0 {
76 pinctrl-single,pins = <
77 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
78 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
79 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
80 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
81 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
82 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
83 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
84 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
85 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
86 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
87 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
88 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
89 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
90 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
91 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
92 >;
93 };
94
95 ecap0_pins: backlight_pins {
96 pinctrl-single,pins = <
97 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
98 >;
99 };
100
101 cpsw_default: cpsw_default {
102 pinctrl-single,pins = <
103 /* Slave 1 */
104 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
105 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
106 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
107 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
108 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
109 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
110 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
111 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
112 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
113 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
114 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
115 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
116 >;
117 };
118
119 cpsw_sleep: cpsw_sleep {
120 pinctrl-single,pins = <
121 /* Slave 1 reset value */
122 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
123 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
124 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
125 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
126 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
127 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
128 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
129 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
130 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
131 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 >;
135 };
136
137 davinci_mdio_default: davinci_mdio_default {
138 pinctrl-single,pins = <
139 /* MDIO */
140 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
141 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
142 >;
143 };
144
145 davinci_mdio_sleep: davinci_mdio_sleep {
146 pinctrl-single,pins = <
147 /* MDIO reset value */
148 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
149 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
150 >;
151 };
152 };
153
154 ocp {
155 uart0: serial@44e09000 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&uart0_pins>;
158
159 status = "okay";
160 };
161
162 i2c0: i2c@44e0b000 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c0_pins>;
165
166 status = "okay";
167 clock-frequency = <400000>;
168
169 tps: tps@2d {
170 reg = <0x2d>;
171 };
172 };
173
174 musb: usb@47400000 {
175 status = "okay";
176
177 control@44e10000 {
178 status = "okay";
179 };
180
181 usb-phy@47401300 {
182 status = "okay";
183 };
184
185 usb-phy@47401b00 {
186 status = "okay";
187 };
188
189 usb@47401000 {
190 status = "okay";
191 };
192
193 usb@47401800 {
194 status = "okay";
195 dr_mode = "host";
196 };
197
198 dma-controller@07402000 {
199 status = "okay";
200 };
201 };
202
203 i2c1: i2c@4802a000 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&i2c1_pins>;
206
207 status = "okay";
208 clock-frequency = <100000>;
209
210 lis331dlh: lis331dlh@18 {
211 compatible = "st,lis331dlh", "st,lis3lv02d";
212 reg = <0x18>;
213 Vdd-supply = <&lis3_reg>;
214 Vdd_IO-supply = <&lis3_reg>;
215
216 st,click-single-x;
217 st,click-single-y;
218 st,click-single-z;
219 st,click-thresh-x = <10>;
220 st,click-thresh-y = <10>;
221 st,click-thresh-z = <10>;
222 st,irq1-click;
223 st,irq2-click;
224 st,wakeup-x-lo;
225 st,wakeup-x-hi;
226 st,wakeup-y-lo;
227 st,wakeup-y-hi;
228 st,wakeup-z-lo;
229 st,wakeup-z-hi;
230 st,min-limit-x = <120>;
231 st,min-limit-y = <120>;
232 st,min-limit-z = <140>;
233 st,max-limit-x = <550>;
234 st,max-limit-y = <550>;
235 st,max-limit-z = <750>;
236 };
237
238 tsl2550: tsl2550@39 {
239 compatible = "taos,tsl2550";
240 reg = <0x39>;
241 };
242
243 tmp275: tmp275@48 {
244 compatible = "ti,tmp275";
245 reg = <0x48>;
246 };
247 };
248
249 elm: elm@48080000 {
250 status = "okay";
251 };
252
253 epwmss0: epwmss@48300000 {
254 status = "okay";
255
256 ecap0: ecap@48300100 {
257 status = "okay";
258 pinctrl-names = "default";
259 pinctrl-0 = <&ecap0_pins>;
260 };
261 };
262
263 gpmc: gpmc@50000000 {
264 status = "okay";
265 pinctrl-names = "default";
266 pinctrl-0 = <&nandflash_pins_s0>;
267 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
268 nand@0,0 {
269 reg = <0 0 0>; /* CS0, offset 0 */
270 nand-bus-width = <8>;
271 ti,nand-ecc-opt = "bch8";
272 gpmc,device-nand = "true";
273 gpmc,device-width = <1>;
274 gpmc,sync-clk-ps = <0>;
275 gpmc,cs-on-ns = <0>;
276 gpmc,cs-rd-off-ns = <44>;
277 gpmc,cs-wr-off-ns = <44>;
278 gpmc,adv-on-ns = <6>;
279 gpmc,adv-rd-off-ns = <34>;
280 gpmc,adv-wr-off-ns = <44>;
281 gpmc,we-on-ns = <0>;
282 gpmc,we-off-ns = <40>;
283 gpmc,oe-on-ns = <0>;
284 gpmc,oe-off-ns = <54>;
285 gpmc,access-ns = <64>;
286 gpmc,rd-cycle-ns = <82>;
287 gpmc,wr-cycle-ns = <82>;
288 gpmc,wait-on-read = "true";
289 gpmc,wait-on-write = "true";
290 gpmc,bus-turnaround-ns = <0>;
291 gpmc,cycle2cycle-delay-ns = <0>;
292 gpmc,clk-activation-ns = <0>;
293 gpmc,wait-monitoring-ns = <0>;
294 gpmc,wr-access-ns = <40>;
295 gpmc,wr-data-mux-bus-ns = <0>;
296
297 #address-cells = <1>;
298 #size-cells = <1>;
299 elm_id = <&elm>;
300
301 /* MTD partition table */
302 partition@0 {
303 label = "SPL1";
304 reg = <0x00000000 0x000020000>;
305 };
306
307 partition@1 {
308 label = "SPL2";
309 reg = <0x00020000 0x00020000>;
310 };
311
312 partition@2 {
313 label = "SPL3";
314 reg = <0x00040000 0x00020000>;
315 };
316
317 partition@3 {
318 label = "SPL4";
319 reg = <0x00060000 0x00020000>;
320 };
321
322 partition@4 {
323 label = "U-boot";
324 reg = <0x00080000 0x001e0000>;
325 };
326
327 partition@5 {
328 label = "environment";
329 reg = <0x00260000 0x00020000>;
330 };
331
332 partition@6 {
333 label = "Kernel";
334 reg = <0x00280000 0x00500000>;
335 };
336
337 partition@7 {
338 label = "File-System";
339 reg = <0x00780000 0x0F880000>;
340 };
341 };
342 };
343 };
344
345 vbat: fixedregulator@0 { 27 vbat: fixedregulator@0 {
346 compatible = "regulator-fixed"; 28 compatible = "regulator-fixed";
347 regulator-name = "vbat"; 29 regulator-name = "vbat";
@@ -403,10 +85,447 @@
403 brightness-levels = <0 51 53 56 62 75 101 152 255>; 85 brightness-levels = <0 51 53 56 62 75 101 152 255>;
404 default-brightness-level = <8>; 86 default-brightness-level = <8>;
405 }; 87 };
88
89 panel {
90 compatible = "ti,tilcdc,panel";
91 status = "okay";
92 pinctrl-names = "default";
93 pinctrl-0 = <&lcd_pins_s0>;
94 panel-info {
95 ac-bias = <255>;
96 ac-bias-intrpt = <0>;
97 dma-burst-sz = <16>;
98 bpp = <32>;
99 fdd = <0x80>;
100 sync-edge = <0>;
101 sync-ctrl = <1>;
102 raster-order = <0>;
103 fifo-th = <0>;
104 };
105
106 display-timings {
107 800x480p62 {
108 clock-frequency = <30000000>;
109 hactive = <800>;
110 vactive = <480>;
111 hfront-porch = <39>;
112 hback-porch = <39>;
113 hsync-len = <47>;
114 vback-porch = <29>;
115 vfront-porch = <13>;
116 vsync-len = <2>;
117 hsync-active = <1>;
118 vsync-active = <1>;
119 };
120 };
121 };
122
123 sound {
124 compatible = "ti,da830-evm-audio";
125 ti,model = "AM335x-EVM";
126 ti,audio-codec = <&tlv320aic3106>;
127 ti,mcasp-controller = <&mcasp1>;
128 ti,codec-clock-rate = <12000000>;
129 ti,audio-routing =
130 "Headphone Jack", "HPLOUT",
131 "Headphone Jack", "HPROUT",
132 "LINE1L", "Line In",
133 "LINE1R", "Line In";
134 };
135};
136
137&am33xx_pinmux {
138 pinctrl-names = "default";
139 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
140
141 matrix_keypad_s0: matrix_keypad_s0 {
142 pinctrl-single,pins = <
143 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
144 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
145 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
146 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
147 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
148 >;
149 };
150
151 volume_keys_s0: volume_keys_s0 {
152 pinctrl-single,pins = <
153 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
154 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
155 >;
156 };
157
158 i2c0_pins: pinmux_i2c0_pins {
159 pinctrl-single,pins = <
160 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
161 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
162 >;
163 };
164
165 i2c1_pins: pinmux_i2c1_pins {
166 pinctrl-single,pins = <
167 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
168 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
169 >;
170 };
171
172 uart0_pins: pinmux_uart0_pins {
173 pinctrl-single,pins = <
174 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
175 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
176 >;
177 };
178
179 clkout2_pin: pinmux_clkout2_pin {
180 pinctrl-single,pins = <
181 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
182 >;
183 };
184
185 nandflash_pins_s0: nandflash_pins_s0 {
186 pinctrl-single,pins = <
187 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
188 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
189 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
190 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
191 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
192 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
193 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
194 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
195 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
196 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
197 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
198 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
199 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
200 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
201 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
202 >;
203 };
204
205 ecap0_pins: backlight_pins {
206 pinctrl-single,pins = <
207 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
208 >;
209 };
210
211 cpsw_default: cpsw_default {
212 pinctrl-single,pins = <
213 /* Slave 1 */
214 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
215 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
216 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
217 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
218 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
219 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
220 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
221 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
222 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
223 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
224 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
225 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
226 >;
227 };
228
229 cpsw_sleep: cpsw_sleep {
230 pinctrl-single,pins = <
231 /* Slave 1 reset value */
232 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
233 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
234 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
235 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
236 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
237 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
238 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
239 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
240 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
241 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
242 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
243 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
244 >;
245 };
246
247 davinci_mdio_default: davinci_mdio_default {
248 pinctrl-single,pins = <
249 /* MDIO */
250 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
251 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
252 >;
253 };
254
255 davinci_mdio_sleep: davinci_mdio_sleep {
256 pinctrl-single,pins = <
257 /* MDIO reset value */
258 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
259 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
260 >;
261 };
262
263 lcd_pins_s0: lcd_pins_s0 {
264 pinctrl-single,pins = <
265 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
266 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
267 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
268 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
269 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
270 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
271 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
272 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
273 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
274 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
275 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
276 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
277 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
278 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
279 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
280 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
281 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
282 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
283 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
284 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
285 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
286 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
287 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
288 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
289 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
290 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
291 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
292 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
293 >;
294 };
295
296 am335x_evm_audio_pins: am335x_evm_audio_pins {
297 pinctrl-single,pins = <
298 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
299 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
300 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
301 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
302 >;
303 };
304};
305
306&uart0 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&uart0_pins>;
309
310 status = "okay";
311};
312
313&i2c0 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&i2c0_pins>;
316
317 status = "okay";
318 clock-frequency = <400000>;
319
320 tps: tps@2d {
321 reg = <0x2d>;
322 };
323};
324
325&usb {
326 status = "okay";
327
328 control@44e10000 {
329 status = "okay";
330 };
331
332 usb-phy@47401300 {
333 status = "okay";
334 };
335
336 usb-phy@47401b00 {
337 status = "okay";
338 };
339
340 usb@47401000 {
341 status = "okay";
342 };
343
344 usb@47401800 {
345 status = "okay";
346 dr_mode = "host";
347 };
348
349 dma-controller@07402000 {
350 status = "okay";
351 };
352};
353
354&i2c1 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c1_pins>;
357
358 status = "okay";
359 clock-frequency = <100000>;
360
361 lis331dlh: lis331dlh@18 {
362 compatible = "st,lis331dlh", "st,lis3lv02d";
363 reg = <0x18>;
364 Vdd-supply = <&lis3_reg>;
365 Vdd_IO-supply = <&lis3_reg>;
366
367 st,click-single-x;
368 st,click-single-y;
369 st,click-single-z;
370 st,click-thresh-x = <10>;
371 st,click-thresh-y = <10>;
372 st,click-thresh-z = <10>;
373 st,irq1-click;
374 st,irq2-click;
375 st,wakeup-x-lo;
376 st,wakeup-x-hi;
377 st,wakeup-y-lo;
378 st,wakeup-y-hi;
379 st,wakeup-z-lo;
380 st,wakeup-z-hi;
381 st,min-limit-x = <120>;
382 st,min-limit-y = <120>;
383 st,min-limit-z = <140>;
384 st,max-limit-x = <550>;
385 st,max-limit-y = <550>;
386 st,max-limit-z = <750>;
387 };
388
389 tsl2550: tsl2550@39 {
390 compatible = "taos,tsl2550";
391 reg = <0x39>;
392 };
393
394 tmp275: tmp275@48 {
395 compatible = "ti,tmp275";
396 reg = <0x48>;
397 };
398
399 tlv320aic3106: tlv320aic3106@1b {
400 compatible = "ti,tlv320aic3106";
401 reg = <0x1b>;
402 status = "okay";
403
404 /* Regulators */
405 AVDD-supply = <&vaux2_reg>;
406 IOVDD-supply = <&vaux2_reg>;
407 DRVDD-supply = <&vaux2_reg>;
408 DVDD-supply = <&vbat>;
409 };
410};
411
412&lcdc {
413 status = "okay";
414};
415
416&elm {
417 status = "okay";
418};
419
420&epwmss0 {
421 status = "okay";
422
423 ecap0: ecap@48300100 {
424 status = "okay";
425 pinctrl-names = "default";
426 pinctrl-0 = <&ecap0_pins>;
427 };
428};
429
430&gpmc {
431 status = "okay";
432 pinctrl-names = "default";
433 pinctrl-0 = <&nandflash_pins_s0>;
434 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
435 nand@0,0 {
436 reg = <0 0 0>; /* CS0, offset 0 */
437 nand-bus-width = <8>;
438 ti,nand-ecc-opt = "bch8";
439 gpmc,device-nand = "true";
440 gpmc,device-width = <1>;
441 gpmc,sync-clk-ps = <0>;
442 gpmc,cs-on-ns = <0>;
443 gpmc,cs-rd-off-ns = <44>;
444 gpmc,cs-wr-off-ns = <44>;
445 gpmc,adv-on-ns = <6>;
446 gpmc,adv-rd-off-ns = <34>;
447 gpmc,adv-wr-off-ns = <44>;
448 gpmc,we-on-ns = <0>;
449 gpmc,we-off-ns = <40>;
450 gpmc,oe-on-ns = <0>;
451 gpmc,oe-off-ns = <54>;
452 gpmc,access-ns = <64>;
453 gpmc,rd-cycle-ns = <82>;
454 gpmc,wr-cycle-ns = <82>;
455 gpmc,wait-on-read = "true";
456 gpmc,wait-on-write = "true";
457 gpmc,bus-turnaround-ns = <0>;
458 gpmc,cycle2cycle-delay-ns = <0>;
459 gpmc,clk-activation-ns = <0>;
460 gpmc,wait-monitoring-ns = <0>;
461 gpmc,wr-access-ns = <40>;
462 gpmc,wr-data-mux-bus-ns = <0>;
463
464 #address-cells = <1>;
465 #size-cells = <1>;
466 elm_id = <&elm>;
467
468 /* MTD partition table */
469 partition@0 {
470 label = "SPL1";
471 reg = <0x00000000 0x000020000>;
472 };
473
474 partition@1 {
475 label = "SPL2";
476 reg = <0x00020000 0x00020000>;
477 };
478
479 partition@2 {
480 label = "SPL3";
481 reg = <0x00040000 0x00020000>;
482 };
483
484 partition@3 {
485 label = "SPL4";
486 reg = <0x00060000 0x00020000>;
487 };
488
489 partition@4 {
490 label = "U-boot";
491 reg = <0x00080000 0x001e0000>;
492 };
493
494 partition@5 {
495 label = "environment";
496 reg = <0x00260000 0x00020000>;
497 };
498
499 partition@6 {
500 label = "Kernel";
501 reg = <0x00280000 0x00500000>;
502 };
503
504 partition@7 {
505 label = "File-System";
506 reg = <0x00780000 0x0F880000>;
507 };
508 };
406}; 509};
407 510
408#include "tps65910.dtsi" 511#include "tps65910.dtsi"
409 512
513&mcasp1 {
514 pinctrl-names = "default";
515 pinctrl-0 = <&am335x_evm_audio_pins>;
516
517 status = "okay";
518
519 op-mode = <0>; /* MCASP_IIS_MODE */
520 tdm-slots = <2>;
521 /* 4 serializers */
522 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
523 0 0 1 2
524 >;
525 tx-num-evt = <1>;
526 rx-num-evt = <1>;
527};
528
410&tps { 529&tps {
411 vcc1-supply = <&vbat>; 530 vcc1-supply = <&vbat>;
412 vcc2-supply = <&vbat>; 531 vcc2-supply = <&vbat>;
@@ -477,6 +596,8 @@
477 }; 596 };
478 597
479 vmmc_reg: regulator@12 { 598 vmmc_reg: regulator@12 {
599 regulator-min-microvolt = <1800000>;
600 regulator-max-microvolt = <3300000>;
480 regulator-always-on; 601 regulator-always-on;
481 }; 602 };
482 }; 603 };
@@ -517,3 +638,17 @@
517 ti,adc-channels = <4 5 6 7>; 638 ti,adc-channels = <4 5 6 7>;
518 }; 639 };
519}; 640};
641
642&mmc1 {
643 status = "okay";
644 vmmc-supply = <&vmmc_reg>;
645 bus-width = <4>;
646};
647
648&sham {
649 status = "okay";
650};
651
652&aes {
653 status = "okay";
654};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 4f339fa91c57..03febf85fd2f 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -31,210 +31,6 @@
31 reg = <0x80000000 0x10000000>; /* 256 MB */ 31 reg = <0x80000000 0x10000000>; /* 256 MB */
32 }; 32 };
33 33
34 am33xx_pinmux: pinmux@44e10800 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
37
38 user_leds_s0: user_leds_s0 {
39 pinctrl-single,pins = <
40 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
41 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
42 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
43 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
44 >;
45 };
46
47 gpio_keys_s0: gpio_keys_s0 {
48 pinctrl-single,pins = <
49 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
50 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
51 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
52 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
53 >;
54 };
55
56 i2c0_pins: pinmux_i2c0_pins {
57 pinctrl-single,pins = <
58 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
59 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
60 >;
61 };
62
63 uart0_pins: pinmux_uart0_pins {
64 pinctrl-single,pins = <
65 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
66 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
67 >;
68 };
69
70 clkout2_pin: pinmux_clkout2_pin {
71 pinctrl-single,pins = <
72 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
73 >;
74 };
75
76 ecap2_pins: backlight_pins {
77 pinctrl-single,pins = <
78 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
79 >;
80 };
81
82 cpsw_default: cpsw_default {
83 pinctrl-single,pins = <
84 /* Slave 1 */
85 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
86 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
87 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
88 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
89 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
90 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
91 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
92 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
93 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
94 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
95 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
96 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
97
98 /* Slave 2 */
99 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
100 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
101 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
102 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
103 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
104 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
105 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
106 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
107 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
108 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
109 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
110 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
111 >;
112 };
113
114 cpsw_sleep: cpsw_sleep {
115 pinctrl-single,pins = <
116 /* Slave 1 reset value */
117 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
118 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
119 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
120 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
121 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
122 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
123 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
124 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
125 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
126 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
127 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
128 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
129
130 /* Slave 2 reset value*/
131 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
135 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
136 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
137 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
138 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
139 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
140 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
141 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
142 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
143 >;
144 };
145
146 davinci_mdio_default: davinci_mdio_default {
147 pinctrl-single,pins = <
148 /* MDIO */
149 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
150 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
151 >;
152 };
153
154 davinci_mdio_sleep: davinci_mdio_sleep {
155 pinctrl-single,pins = <
156 /* MDIO reset value */
157 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
158 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
159 >;
160 };
161 };
162
163 ocp {
164 uart0: serial@44e09000 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&uart0_pins>;
167
168 status = "okay";
169 };
170
171 i2c0: i2c@44e0b000 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&i2c0_pins>;
174
175 status = "okay";
176 clock-frequency = <400000>;
177
178 tps: tps@2d {
179 reg = <0x2d>;
180 };
181
182 lis331dlh: lis331dlh@18 {
183 compatible = "st,lis331dlh", "st,lis3lv02d";
184 reg = <0x18>;
185 Vdd-supply = <&lis3_reg>;
186 Vdd_IO-supply = <&lis3_reg>;
187
188 st,click-single-x;
189 st,click-single-y;
190 st,click-single-z;
191 st,click-thresh-x = <10>;
192 st,click-thresh-y = <10>;
193 st,click-thresh-z = <10>;
194 st,irq1-click;
195 st,irq2-click;
196 st,wakeup-x-lo;
197 st,wakeup-x-hi;
198 st,wakeup-y-lo;
199 st,wakeup-y-hi;
200 st,wakeup-z-lo;
201 st,wakeup-z-hi;
202 st,min-limit-x = <120>;
203 st,min-limit-y = <120>;
204 st,min-limit-z = <140>;
205 st,max-limit-x = <550>;
206 st,max-limit-y = <550>;
207 st,max-limit-z = <750>;
208 };
209 };
210
211 musb: usb@47400000 {
212 status = "okay";
213
214 control@44e10000 {
215 status = "okay";
216 };
217
218 usb-phy@47401300 {
219 status = "okay";
220 };
221
222 usb@47401000 {
223 status = "okay";
224 };
225 };
226
227 epwmss2: epwmss@48304000 {
228 status = "okay";
229
230 ecap2: ecap@48304100 {
231 status = "okay";
232 pinctrl-names = "default";
233 pinctrl-0 = <&ecap2_pins>;
234 };
235 };
236 };
237
238 vbat: fixedregulator@0 { 34 vbat: fixedregulator@0 {
239 compatible = "regulator-fixed"; 35 compatible = "regulator-fixed";
240 regulator-name = "vbat"; 36 regulator-name = "vbat";
@@ -319,6 +115,240 @@
319 brightness-levels = <0 58 61 66 75 90 125 170 255>; 115 brightness-levels = <0 58 61 66 75 90 125 170 255>;
320 default-brightness-level = <8>; 116 default-brightness-level = <8>;
321 }; 117 };
118
119 sound {
120 compatible = "ti,da830-evm-audio";
121 ti,model = "AM335x-EVMSK";
122 ti,audio-codec = <&tlv320aic3106>;
123 ti,mcasp-controller = <&mcasp1>;
124 ti,codec-clock-rate = <24576000>;
125 ti,audio-routing =
126 "Headphone Jack", "HPLOUT",
127 "Headphone Jack", "HPROUT";
128 };
129};
130
131&am33xx_pinmux {
132 pinctrl-names = "default";
133 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
134
135 user_leds_s0: user_leds_s0 {
136 pinctrl-single,pins = <
137 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
138 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
139 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
140 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
141 >;
142 };
143
144 gpio_keys_s0: gpio_keys_s0 {
145 pinctrl-single,pins = <
146 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
147 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
148 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
149 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
150 >;
151 };
152
153 i2c0_pins: pinmux_i2c0_pins {
154 pinctrl-single,pins = <
155 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
156 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
157 >;
158 };
159
160 uart0_pins: pinmux_uart0_pins {
161 pinctrl-single,pins = <
162 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
163 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
164 >;
165 };
166
167 clkout2_pin: pinmux_clkout2_pin {
168 pinctrl-single,pins = <
169 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
170 >;
171 };
172
173 ecap2_pins: backlight_pins {
174 pinctrl-single,pins = <
175 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
176 >;
177 };
178
179 cpsw_default: cpsw_default {
180 pinctrl-single,pins = <
181 /* Slave 1 */
182 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
183 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
184 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
185 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
186 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
187 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
188 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
189 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
190 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
191 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
192 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
193 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
194
195 /* Slave 2 */
196 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
197 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
198 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
199 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
200 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
201 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
202 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
203 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
204 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
205 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
206 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
207 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
208 >;
209 };
210
211 cpsw_sleep: cpsw_sleep {
212 pinctrl-single,pins = <
213 /* Slave 1 reset value */
214 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
215 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
216 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
217 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
218 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
219 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
220 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
221 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
222 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
223 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
224 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
225 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
226
227 /* Slave 2 reset value*/
228 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
229 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
230 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
231 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
232 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
233 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
234 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
235 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
236 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
237 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
238 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
239 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
240 >;
241 };
242
243 davinci_mdio_default: davinci_mdio_default {
244 pinctrl-single,pins = <
245 /* MDIO */
246 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
247 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
248 >;
249 };
250
251 davinci_mdio_sleep: davinci_mdio_sleep {
252 pinctrl-single,pins = <
253 /* MDIO reset value */
254 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
255 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
256 >;
257 };
258
259 mcasp1_pins: mcasp1_pins {
260 pinctrl-single,pins = <
261 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
262 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
263 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
264 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
265 >;
266 };
267};
268
269&uart0 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&uart0_pins>;
272
273 status = "okay";
274};
275
276&i2c0 {
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c0_pins>;
279
280 status = "okay";
281 clock-frequency = <400000>;
282
283 tps: tps@2d {
284 reg = <0x2d>;
285 };
286
287 lis331dlh: lis331dlh@18 {
288 compatible = "st,lis331dlh", "st,lis3lv02d";
289 reg = <0x18>;
290 Vdd-supply = <&lis3_reg>;
291 Vdd_IO-supply = <&lis3_reg>;
292
293 st,click-single-x;
294 st,click-single-y;
295 st,click-single-z;
296 st,click-thresh-x = <10>;
297 st,click-thresh-y = <10>;
298 st,click-thresh-z = <10>;
299 st,irq1-click;
300 st,irq2-click;
301 st,wakeup-x-lo;
302 st,wakeup-x-hi;
303 st,wakeup-y-lo;
304 st,wakeup-y-hi;
305 st,wakeup-z-lo;
306 st,wakeup-z-hi;
307 st,min-limit-x = <120>;
308 st,min-limit-y = <120>;
309 st,min-limit-z = <140>;
310 st,max-limit-x = <550>;
311 st,max-limit-y = <550>;
312 st,max-limit-z = <750>;
313 };
314
315 tlv320aic3106: tlv320aic3106@1b {
316 compatible = "ti,tlv320aic3106";
317 reg = <0x1b>;
318 status = "okay";
319
320 /* Regulators */
321 AVDD-supply = <&vaux2_reg>;
322 IOVDD-supply = <&vaux2_reg>;
323 DRVDD-supply = <&vaux2_reg>;
324 DVDD-supply = <&vbat>;
325 };
326};
327
328&usb {
329 status = "okay";
330
331 control@44e10000 {
332 status = "okay";
333 };
334
335 usb-phy@47401300 {
336 status = "okay";
337 };
338
339 usb@47401000 {
340 status = "okay";
341 };
342};
343
344&epwmss2 {
345 status = "okay";
346
347 ecap2: ecap@48304100 {
348 status = "okay";
349 pinctrl-names = "default";
350 pinctrl-0 = <&ecap2_pins>;
351 };
322}; 352};
323 353
324#include "tps65910.dtsi" 354#include "tps65910.dtsi"
@@ -393,6 +423,8 @@
393 }; 423 };
394 424
395 vmmc_reg: regulator@12 { 425 vmmc_reg: regulator@12 {
426 regulator-min-microvolt = <1800000>;
427 regulator-max-microvolt = <3300000>;
396 regulator-always-on; 428 regulator-always-on;
397 }; 429 };
398 }; 430 };
@@ -419,3 +451,37 @@
419 phy_id = <&davinci_mdio>, <1>; 451 phy_id = <&davinci_mdio>, <1>;
420 phy-mode = "rgmii-txid"; 452 phy-mode = "rgmii-txid";
421}; 453};
454
455&mmc1 {
456 status = "okay";
457 vmmc-supply = <&vmmc_reg>;
458 bus-width = <4>;
459};
460
461&sham {
462 status = "okay";
463};
464
465&aes {
466 status = "okay";
467};
468
469&gpio0 {
470 ti,no-reset-on-init;
471};
472
473&mcasp1 {
474 pinctrl-names = "default";
475 pinctrl-0 = <&mcasp1_pins>;
476
477 status = "okay";
478
479 op-mode = <0>; /* MCASP_IIS_MODE */
480 tdm-slots = <2>;
481 /* 4 serializers */
482 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
483 0 0 1 2
484 >;
485 tx-num-evt = <1>;
486 rx-num-evt = <1>;
487};
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
new file mode 100644
index 000000000000..619624479311
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -0,0 +1,278 @@
1/*
2 * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
3 *
4 * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/dts-v1/;
12
13#include "am33xx.dtsi"
14
15/ {
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
26
27 leds {
28 pinctrl-names = "default";
29 pinctrl-0 = <&leds_pins>;
30
31 compatible = "gpio-leds";
32
33 led@0 {
34 label = "com:green:user";
35 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
36 default-state = "on";
37 };
38 };
39
40 vbat: fixedregulator@0 {
41 compatible = "regulator-fixed";
42 regulator-name = "vbat";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
45 regulator-boot-on;
46 };
47
48 vmmc: fixedregulator@0 {
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 };
54};
55
56&am33xx_pinmux {
57 i2c0_pins: pinmux_i2c0_pins {
58 pinctrl-single,pins = <
59 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
60 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
61 >;
62 };
63
64 nandflash_pins: pinmux_nandflash_pins {
65 pinctrl-single,pins = <
66 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
67 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
68 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
69 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
70 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
71 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
72 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
73 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
74 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
75 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
76 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
77 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
78 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
79 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
80 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
81 >;
82 };
83
84 uart0_pins: pinmux_uart0_pins {
85 pinctrl-single,pins = <
86 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
87 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
88 >;
89 };
90
91 leds_pins: pinmux_leds_pins {
92 pinctrl-single,pins = <
93 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
94 >;
95 };
96};
97
98&cpsw_emac0 {
99 phy_id = <&davinci_mdio>, <0>;
100};
101
102&cpsw_emac1 {
103 phy_id = <&davinci_mdio>, <1>;
104};
105
106&elm {
107 status = "okay";
108};
109
110&gpmc {
111 status = "okay";
112 pinctrl-names = "default";
113 pinctrl-0 = <&nandflash_pins>;
114
115 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
116
117 nand@0,0 {
118 reg = <0 0 0>; /* CS0, offset 0 */
119 nand-bus-width = <8>;
120 ti,nand-ecc-opt = "bch8";
121 gpmc,device-nand = "true";
122 gpmc,device-width = <1>;
123 gpmc,sync-clk-ps = <0>;
124 gpmc,cs-on-ns = <0>;
125 gpmc,cs-rd-off-ns = <44>;
126 gpmc,cs-wr-off-ns = <44>;
127 gpmc,adv-on-ns = <6>;
128 gpmc,adv-rd-off-ns = <34>;
129 gpmc,adv-wr-off-ns = <44>;
130 gpmc,we-on-ns = <0>;
131 gpmc,we-off-ns = <40>;
132 gpmc,oe-on-ns = <0>;
133 gpmc,oe-off-ns = <54>;
134 gpmc,access-ns = <64>;
135 gpmc,rd-cycle-ns = <82>;
136 gpmc,wr-cycle-ns = <82>;
137 gpmc,wait-on-read = "true";
138 gpmc,wait-on-write = "true";
139 gpmc,bus-turnaround-ns = <0>;
140 gpmc,cycle2cycle-delay-ns = <0>;
141 gpmc,clk-activation-ns = <0>;
142 gpmc,wait-monitoring-ns = <0>;
143 gpmc,wr-access-ns = <40>;
144 gpmc,wr-data-mux-bus-ns = <0>;
145
146 #address-cells = <1>;
147 #size-cells = <1>;
148 elm_id = <&elm>;
149
150 /* MTD partition table */
151 partition@0 {
152 label = "SPL";
153 reg = <0x00000000 0x000080000>;
154 };
155
156 partition@1 {
157 label = "U-boot";
158 reg = <0x00080000 0x001e0000>;
159 };
160
161 partition@2 {
162 label = "U-Boot Env";
163 reg = <0x00260000 0x00020000>;
164 };
165
166 partition@3 {
167 label = "Kernel";
168 reg = <0x00280000 0x00500000>;
169 };
170
171 partition@4 {
172 label = "File System";
173 reg = <0x00780000 0x007880000>;
174 };
175 };
176};
177
178&i2c0 {
179 status = "okay";
180 pinctrl-names = "default";
181 pinctrl-0 = <&i2c0_pins>;
182
183 clock-frequency = <400000>;
184
185 tps: tps@2d {
186 reg = <0x2d>;
187 };
188};
189
190&mmc1 {
191 status = "okay";
192 vmmc-supply = <&vmmc>;
193 bus-width = <4>;
194};
195
196&uart0 {
197 status = "okay";
198 pinctrl-names = "default";
199 pinctrl-0 = <&uart0_pins>;
200};
201
202#include "tps65910.dtsi"
203
204&tps {
205 vcc1-supply = <&vbat>;
206 vcc2-supply = <&vbat>;
207 vcc3-supply = <&vbat>;
208 vcc4-supply = <&vbat>;
209 vcc5-supply = <&vbat>;
210 vcc6-supply = <&vbat>;
211 vcc7-supply = <&vbat>;
212 vccio-supply = <&vbat>;
213
214 regulators {
215 vrtc_reg: regulator@0 {
216 regulator-always-on;
217 };
218
219 vio_reg: regulator@1 {
220 regulator-always-on;
221 };
222
223 vdd1_reg: regulator@2 {
224 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
225 regulator-name = "vdd_mpu";
226 regulator-min-microvolt = <912500>;
227 regulator-max-microvolt = <1312500>;
228 regulator-boot-on;
229 regulator-always-on;
230 };
231
232 vdd2_reg: regulator@3 {
233 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
234 regulator-name = "vdd_core";
235 regulator-min-microvolt = <912500>;
236 regulator-max-microvolt = <1150000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240
241 vdd3_reg: regulator@4 {
242 regulator-always-on;
243 };
244
245 vdig1_reg: regulator@5 {
246 regulator-always-on;
247 };
248
249 vdig2_reg: regulator@6 {
250 regulator-always-on;
251 };
252
253 vpll_reg: regulator@7 {
254 regulator-always-on;
255 };
256
257 vdac_reg: regulator@8 {
258 regulator-always-on;
259 };
260
261 vaux1_reg: regulator@9 {
262 regulator-always-on;
263 };
264
265 vaux2_reg: regulator@10 {
266 regulator-always-on;
267 };
268
269 vaux33_reg: regulator@11 {
270 regulator-always-on;
271 };
272
273 vmmc_reg: regulator@12 {
274 regulator-always-on;
275 };
276 };
277};
278
diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts
new file mode 100644
index 000000000000..9907b494b99c
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-nano.dts
@@ -0,0 +1,431 @@
1/*
2 * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "am33xx.dtsi"
11
12/ {
13 model = "Newflow AM335x NanoBone";
14 compatible = "ti,am33xx";
15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&dcdc2_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
26
27 leds {
28 compatible = "gpio-leds";
29
30 led@0 {
31 label = "nanobone:green:usr1";
32 gpios = <&gpio1 5 0>;
33 default-state = "off";
34 };
35 };
36};
37
38&am33xx_pinmux {
39 pinctrl-names = "default";
40 pinctrl-0 = <&misc_pins>;
41
42 misc_pins: misc_pins {
43 pinctrl-single,pins = <
44 0x15c (PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
45 >;
46 };
47
48 gpmc_pins: gpmc_pins {
49 pinctrl-single,pins = <
50 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
51 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
52 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
53 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
54 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
55 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
56 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
57 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
58 0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
59 0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
60 0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
61 0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
62 0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
63 0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
64 0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
65 0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
66
67 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
68 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
69 0x80 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */
70 0x84 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */
71 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */
72
73 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
74 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
75 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
76 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */
77
78 0xa4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */
79 0xa8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */
80 0xac (PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */
81 0xb0 (PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */
82 0xb4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */
83 0xb8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */
84 0xbc (PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */
85
86 0xe0 (PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */
87 0xe4 (PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */
88 0xe8 (PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */
89 >;
90 };
91
92 i2c0_pins: i2c0_pins {
93 pinctrl-single,pins = <
94 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */
95 0x18c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */
96 >;
97 };
98
99 uart0_pins: uart0_pins {
100 pinctrl-single,pins = <
101 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
102 0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
103 >;
104 };
105
106 uart1_pins: uart1_pins {
107 pinctrl-single,pins = <
108 0x178 (PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
109 0x17c (PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
110 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
111 0x184 (PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
112 >;
113 };
114
115 uart2_pins: uart2_pins {
116 pinctrl-single,pins = <
117 0xc0 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */
118 0xc4 (PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */
119 0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
120 0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
121 >;
122 };
123
124 uart3_pins: uart3_pins {
125 pinctrl-single,pins = <
126 0xc8 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */
127 0xcc (PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */
128 0x160 (PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */
129 0x164 (PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
130 >;
131 };
132
133 uart4_pins: uart4_pins {
134 pinctrl-single,pins = <
135 0xd0 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */
136 0xd4 (PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */
137 0x168 (PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */
138 0x16c (PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */
139 >;
140 };
141
142 uart5_pins: uart5_pins {
143 pinctrl-single,pins = <
144 0xd8 (PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */
145 0x144 (PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */
146 >;
147 };
148
149 mmc1_pins: mmc1_pins {
150 pinctrl-single,pins = <
151 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
152 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
153 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
154 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
155 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
156 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
157 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
158 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
159 >;
160 };
161};
162
163&uart0 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&uart0_pins>;
166 status = "okay";
167};
168
169&uart1 {
170 pinctrl-names = "default";
171 pinctrl-0 = <&uart1_pins>;
172 status = "okay";
173 rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
174 rs485-rts-active-high;
175 rs485-rx-during-tx;
176 rs485-rts-delay = <1 1>;
177 linux,rs485-enabled-at-boot-time;
178};
179
180&uart2 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&uart2_pins>;
183 status = "okay";
184 rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
185 rs485-rts-active-high;
186 rs485-rts-delay = <1 1>;
187 linux,rs485-enabled-at-boot-time;
188};
189
190&uart3 {
191 pinctrl-names = "default";
192 pinctrl-0 = <&uart3_pins>;
193 status = "okay";
194};
195
196&uart4 {
197 pinctrl-names = "default";
198 pinctrl-0 = <&uart4_pins>;
199 status = "okay";
200};
201
202&uart5 {
203 pinctrl-names = "default";
204 pinctrl-0 = <&uart5_pins>;
205 status = "okay";
206};
207
208&i2c0 {
209 status = "okay";
210 pinctrl-names = "default";
211 clock-frequency = <400000>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&i2c0_pins>;
214
215 gpio@20 {
216 compatible = "mcp,mcp23017";
217 reg = <0x20>;
218 };
219
220 tps: tps@24 {
221 reg = <0x24>;
222 };
223
224 eeprom@53 {
225 compatible = "mcp,24c02";
226 reg = <0x53>;
227 pagesize = <8>;
228 };
229
230 rtc@68 {
231 compatible = "dallas,ds1307";
232 reg = <0x68>;
233 };
234};
235
236&elm {
237 status = "okay";
238};
239
240&gpmc {
241 compatible = "ti,am3352-gpmc";
242 ti,hwmods = "gpmc";
243 status = "okay";
244 gpmc,num-waitpins = <2>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&gpmc_pins>;
247
248 #address-cells = <2>;
249 #size-cells = <1>;
250 ranges = <0 0 0x08000000 0x08000000>; /* CS0: NOR 128M */
251
252 nor@0,0 {
253 reg = <0 0x00000000 0x08000000>;
254 compatible = "cfi-flash";
255 linux,mtd-name = "spansion,s29gl010p11t";
256 bank-width = <2>;
257
258 gpmc,mux-add-data = <2>;
259
260 gpmc,sync-clk-ps = <0>;
261 gpmc,cs-on-ns = <0>;
262 gpmc,cs-rd-off-ns = <160>;
263 gpmc,cs-wr-off-ns = <160>;
264 gpmc,adv-on-ns = <10>;
265 gpmc,adv-rd-off-ns = <30>;
266 gpmc,adv-wr-off-ns = <30>;
267 gpmc,oe-on-ns = <40>;
268 gpmc,oe-off-ns = <160>;
269 gpmc,we-on-ns = <40>;
270 gpmc,we-off-ns = <160>;
271 gpmc,rd-cycle-ns = <160>;
272 gpmc,wr-cycle-ns = <160>;
273 gpmc,access-ns = <150>;
274 gpmc,page-burst-access-ns = <10>;
275 gpmc,cycle2cycle-samecsen;
276 gpmc,cycle2cycle-delay-ns = <20>;
277 gpmc,wr-data-mux-bus-ns = <70>;
278 gpmc,wr-access-ns = <80>;
279
280 #address-cells = <1>;
281 #size-cells = <1>;
282
283 /*
284 MTD partition table
285 ===================
286 +------------+-->0x00000000-> U-Boot start
287 | |
288 | |-->0x000BFFFF-> U-Boot end
289 | |-->0x000C0000-> ENV1 start
290 | |
291 | |-->0x000DFFFF-> ENV1 end
292 | |-->0x000E0000-> ENV2 start
293 | |
294 | |-->0x000FFFFF-> ENV2 end
295 | |-->0x00100000-> Kernel start
296 | |
297 | |-->0x004FFFFF-> Kernel end
298 | |-->0x00500000-> File system start
299 | |
300 | |-->0x014FFFFF-> File system end
301 | |-->0x01500000-> User data start
302 | |
303 | |-->0x03FFFFFF-> User data end
304 | |-->0x04000000-> Data storage start
305 | |
306 +------------+-->0x08000000-> NOR end (Free end)
307 */
308 partition@0 {
309 label = "boot";
310 reg = <0x00000000 0x000c0000>; /* 768KB */
311 };
312
313 partition@1 {
314 label = "env1";
315 reg = <0x000c0000 0x00020000>; /* 128KB */
316 };
317
318 partition@2 {
319 label = "env2";
320 reg = <0x000e0000 0x00020000>; /* 128KB */
321 };
322
323 partition@3 {
324 label = "kernel";
325 reg = <0x00100000 0x00400000>; /* 4MB */
326 };
327
328 partition@4 {
329 label = "rootfs";
330 reg = <0x00500000 0x01000000>; /* 16MB */
331 };
332
333 partition@5 {
334 label = "user";
335 reg = <0x01500000 0x02b00000>; /* 43MB */
336 };
337
338 partition@6 {
339 label = "data";
340 reg = <0x04000000 0x04000000>; /* 64MB */
341 };
342 };
343};
344
345&mac {
346 dual_emac = <1>;
347};
348
349&cpsw_emac0 {
350 phy_id = <&davinci_mdio>, <0>;
351 dual_emac_res_vlan = <1>;
352};
353
354&cpsw_emac1 {
355 phy_id = <&davinci_mdio>, <1>;
356 dual_emac_res_vlan = <2>;
357};
358
359&mmc1 {
360 status = "okay";
361 vmmc-supply = <&ldo4_reg>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&mmc1_pins>;
364 bus-width = <4>;
365 cd-gpios = <&gpio3 8 0>;
366 wp-gpios = <&gpio3 18 0>;
367};
368
369#include "tps65217.dtsi"
370
371&tps {
372 regulators {
373 dcdc1_reg: regulator@0 {
374 /* +1.5V voltage with ±4% tolerance */
375 regulator-min-microvolt = <1450000>;
376 regulator-max-microvolt = <1550000>;
377 regulator-boot-on;
378 regulator-always-on;
379 };
380
381 dcdc2_reg: regulator@1 {
382 /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
383 regulator-name = "vdd_mpu";
384 regulator-min-microvolt = <915000>;
385 regulator-max-microvolt = <1140000>;
386 regulator-boot-on;
387 regulator-always-on;
388 };
389
390 dcdc3_reg: regulator@2 {
391 /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
392 regulator-name = "vdd_core";
393 regulator-min-microvolt = <915000>;
394 regulator-max-microvolt = <1140000>;
395 regulator-boot-on;
396 regulator-always-on;
397 };
398
399 ldo1_reg: regulator@3 {
400 /* +1.8V voltage with ±4% tolerance */
401 regulator-min-microvolt = <1750000>;
402 regulator-max-microvolt = <1870000>;
403 regulator-boot-on;
404 regulator-always-on;
405 };
406
407 ldo2_reg: regulator@4 {
408 /* +3.3V voltage with ±4% tolerance */
409 regulator-min-microvolt = <3175000>;
410 regulator-max-microvolt = <3430000>;
411 regulator-boot-on;
412 regulator-always-on;
413 };
414
415 ldo3_reg: regulator@5 {
416 /* +1.8V voltage with ±4% tolerance */
417 regulator-min-microvolt = <1750000>;
418 regulator-max-microvolt = <1870000>;
419 regulator-boot-on;
420 regulator-always-on;
421 };
422
423 ldo4_reg: regulator@6 {
424 /* +3.3V voltage with ±4% tolerance */
425 regulator-min-microvolt = <3175000>;
426 regulator-max-microvolt = <3430000>;
427 regulator-boot-on;
428 regulator-always-on;
429 };
430 };
431};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index f9c5da9c7fe1..fcb9c8e42ab7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -18,6 +18,9 @@
18 interrupt-parent = <&intc>; 18 interrupt-parent = <&intc>;
19 19
20 aliases { 20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
21 serial0 = &uart0; 24 serial0 = &uart0;
22 serial1 = &uart1; 25 serial1 = &uart1;
23 serial2 = &uart2; 26 serial2 = &uart2;
@@ -30,6 +33,8 @@
30 usb1 = &usb1; 33 usb1 = &usb1;
31 phy0 = &usb0_phy; 34 phy0 = &usb0_phy;
32 phy1 = &usb1_phy; 35 phy1 = &usb1_phy;
36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
33 }; 38 };
34 39
35 cpus { 40 cpus {
@@ -57,6 +62,11 @@
57 }; 62 };
58 }; 63 };
59 64
65 pmu {
66 compatible = "arm,cortex-a8-pmu";
67 interrupts = <3>;
68 };
69
60 /* 70 /*
61 * The soc node represents the soc top level view. It is uses for IPs 71 * The soc node represents the soc top level view. It is uses for IPs
62 * that are not memory mapped in the MPU view or for the MPU itself. 72 * that are not memory mapped in the MPU view or for the MPU itself.
@@ -100,13 +110,25 @@
100 reg = <0x48200000 0x1000>; 110 reg = <0x48200000 0x1000>;
101 }; 111 };
102 112
113 edma: edma@49000000 {
114 compatible = "ti,edma3";
115 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
116 reg = <0x49000000 0x10000>,
117 <0x44e10f90 0x10>;
118 interrupts = <12 13 14>;
119 #dma-cells = <1>;
120 dma-channels = <64>;
121 ti,edma-regions = <4>;
122 ti,edma-slots = <256>;
123 };
124
103 gpio0: gpio@44e07000 { 125 gpio0: gpio@44e07000 {
104 compatible = "ti,omap4-gpio"; 126 compatible = "ti,omap4-gpio";
105 ti,hwmods = "gpio1"; 127 ti,hwmods = "gpio1";
106 gpio-controller; 128 gpio-controller;
107 #gpio-cells = <2>; 129 #gpio-cells = <2>;
108 interrupt-controller; 130 interrupt-controller;
109 #interrupt-cells = <1>; 131 #interrupt-cells = <2>;
110 reg = <0x44e07000 0x1000>; 132 reg = <0x44e07000 0x1000>;
111 interrupts = <96>; 133 interrupts = <96>;
112 }; 134 };
@@ -117,7 +139,7 @@
117 gpio-controller; 139 gpio-controller;
118 #gpio-cells = <2>; 140 #gpio-cells = <2>;
119 interrupt-controller; 141 interrupt-controller;
120 #interrupt-cells = <1>; 142 #interrupt-cells = <2>;
121 reg = <0x4804c000 0x1000>; 143 reg = <0x4804c000 0x1000>;
122 interrupts = <98>; 144 interrupts = <98>;
123 }; 145 };
@@ -128,7 +150,7 @@
128 gpio-controller; 150 gpio-controller;
129 #gpio-cells = <2>; 151 #gpio-cells = <2>;
130 interrupt-controller; 152 interrupt-controller;
131 #interrupt-cells = <1>; 153 #interrupt-cells = <2>;
132 reg = <0x481ac000 0x1000>; 154 reg = <0x481ac000 0x1000>;
133 interrupts = <32>; 155 interrupts = <32>;
134 }; 156 };
@@ -139,7 +161,7 @@
139 gpio-controller; 161 gpio-controller;
140 #gpio-cells = <2>; 162 #gpio-cells = <2>;
141 interrupt-controller; 163 interrupt-controller;
142 #interrupt-cells = <1>; 164 #interrupt-cells = <2>;
143 reg = <0x481ae000 0x1000>; 165 reg = <0x481ae000 0x1000>;
144 interrupts = <62>; 166 interrupts = <62>;
145 }; 167 };
@@ -228,6 +250,50 @@
228 status = "disabled"; 250 status = "disabled";
229 }; 251 };
230 252
253 mmc1: mmc@48060000 {
254 compatible = "ti,omap4-hsmmc";
255 ti,hwmods = "mmc1";
256 ti,dual-volt;
257 ti,needs-special-reset;
258 ti,needs-special-hs-handling;
259 dmas = <&edma 24
260 &edma 25>;
261 dma-names = "tx", "rx";
262 interrupts = <64>;
263 interrupt-parent = <&intc>;
264 reg = <0x48060000 0x1000>;
265 status = "disabled";
266 };
267
268 mmc2: mmc@481d8000 {
269 compatible = "ti,omap4-hsmmc";
270 ti,hwmods = "mmc2";
271 ti,needs-special-reset;
272 dmas = <&edma 2
273 &edma 3>;
274 dma-names = "tx", "rx";
275 interrupts = <28>;
276 interrupt-parent = <&intc>;
277 reg = <0x481d8000 0x1000>;
278 status = "disabled";
279 };
280
281 mmc3: mmc@47810000 {
282 compatible = "ti,omap4-hsmmc";
283 ti,hwmods = "mmc3";
284 ti,needs-special-reset;
285 interrupts = <29>;
286 interrupt-parent = <&intc>;
287 reg = <0x47810000 0x1000>;
288 status = "disabled";
289 };
290
291 hwspinlock: spinlock@480ca000 {
292 compatible = "ti,omap4-hwspinlock";
293 reg = <0x480ca000 0x1000>;
294 ti,hwmods = "spinlock";
295 };
296
231 wdt2: wdt@44e35000 { 297 wdt2: wdt@44e35000 {
232 compatible = "ti,omap3-wdt"; 298 compatible = "ti,omap3-wdt";
233 ti,hwmods = "wd_timer2"; 299 ti,hwmods = "wd_timer2";
@@ -323,6 +389,11 @@
323 interrupts = <65>; 389 interrupts = <65>;
324 ti,spi-num-cs = <2>; 390 ti,spi-num-cs = <2>;
325 ti,hwmods = "spi0"; 391 ti,hwmods = "spi0";
392 dmas = <&edma 16
393 &edma 17
394 &edma 18
395 &edma 19>;
396 dma-names = "tx0", "rx0", "tx1", "rx1";
326 status = "disabled"; 397 status = "disabled";
327 }; 398 };
328 399
@@ -334,6 +405,11 @@
334 interrupts = <125>; 405 interrupts = <125>;
335 ti,spi-num-cs = <2>; 406 ti,spi-num-cs = <2>;
336 ti,hwmods = "spi1"; 407 ti,hwmods = "spi1";
408 dmas = <&edma 42
409 &edma 43
410 &edma 44
411 &edma 45>;
412 dma-names = "tx0", "rx0", "tx1", "rx1";
337 status = "disabled"; 413 status = "disabled";
338 }; 414 };
339 415
@@ -346,7 +422,7 @@
346 ti,hwmods = "usb_otg_hs"; 422 ti,hwmods = "usb_otg_hs";
347 status = "disabled"; 423 status = "disabled";
348 424
349 ctrl_mod: control@44e10000 { 425 usb_ctrl_mod: control@44e10000 {
350 compatible = "ti,am335x-usb-ctrl-module"; 426 compatible = "ti,am335x-usb-ctrl-module";
351 reg = <0x44e10620 0x10 427 reg = <0x44e10620 0x10
352 0x44e10648 0x4>; 428 0x44e10648 0x4>;
@@ -359,7 +435,7 @@
359 reg = <0x47401300 0x100>; 435 reg = <0x47401300 0x100>;
360 reg-names = "phy"; 436 reg-names = "phy";
361 status = "disabled"; 437 status = "disabled";
362 ti,ctrl_mod = <&ctrl_mod>; 438 ti,ctrl_mod = <&usb_ctrl_mod>;
363 }; 439 };
364 440
365 usb0: usb@47401000 { 441 usb0: usb@47401000 {
@@ -407,7 +483,7 @@
407 reg = <0x47401b00 0x100>; 483 reg = <0x47401b00 0x100>;
408 reg-names = "phy"; 484 reg-names = "phy";
409 status = "disabled"; 485 status = "disabled";
410 ti,ctrl_mod = <&ctrl_mod>; 486 ti,ctrl_mod = <&usb_ctrl_mod>;
411 }; 487 };
412 488
413 usb1: usb@47401800 { 489 usb1: usb@47401800 {
@@ -607,6 +683,7 @@
607 reg = <0x44d00000 0x4000 /* M3 UMEM */ 683 reg = <0x44d00000 0x4000 /* M3 UMEM */
608 0x44d80000 0x2000>; /* M3 DMEM */ 684 0x44d80000 0x2000>; /* M3 DMEM */
609 ti,hwmods = "wkup_m3"; 685 ti,hwmods = "wkup_m3";
686 ti,no-reset-on-init;
610 }; 687 };
611 688
612 elm: elm@48080000 { 689 elm: elm@48080000 {
@@ -617,6 +694,15 @@
617 status = "disabled"; 694 status = "disabled";
618 }; 695 };
619 696
697 lcdc: lcdc@4830e000 {
698 compatible = "ti,am33xx-tilcdc";
699 reg = <0x4830e000 0x1000>;
700 interrupt-parent = <&intc>;
701 interrupts = <36>;
702 ti,hwmods = "lcdc";
703 status = "disabled";
704 };
705
620 tscadc: tscadc@44e0d000 { 706 tscadc: tscadc@44e0d000 {
621 compatible = "ti,am3359-tscadc"; 707 compatible = "ti,am3359-tscadc";
622 reg = <0x44e0d000 0x1000>; 708 reg = <0x44e0d000 0x1000>;
@@ -637,6 +723,7 @@
637 gpmc: gpmc@50000000 { 723 gpmc: gpmc@50000000 {
638 compatible = "ti,am3352-gpmc"; 724 compatible = "ti,am3352-gpmc";
639 ti,hwmods = "gpmc"; 725 ti,hwmods = "gpmc";
726 ti,no-idle-on-init;
640 reg = <0x50000000 0x2000>; 727 reg = <0x50000000 0x2000>;
641 interrupts = <100>; 728 interrupts = <100>;
642 gpmc,num-cs = <7>; 729 gpmc,num-cs = <7>;
@@ -645,5 +732,59 @@
645 #size-cells = <1>; 732 #size-cells = <1>;
646 status = "disabled"; 733 status = "disabled";
647 }; 734 };
735
736 sham: sham@53100000 {
737 compatible = "ti,omap4-sham";
738 ti,hwmods = "sham";
739 reg = <0x53100000 0x200>;
740 interrupts = <109>;
741 dmas = <&edma 36>;
742 dma-names = "rx";
743 };
744
745 aes: aes@53500000 {
746 compatible = "ti,omap4-aes";
747 ti,hwmods = "aes";
748 reg = <0x53500000 0xa0>;
749 interrupts = <103>;
750 dmas = <&edma 6>,
751 <&edma 5>;
752 dma-names = "tx", "rx";
753 };
754
755 mcasp0: mcasp@48038000 {
756 compatible = "ti,am33xx-mcasp-audio";
757 ti,hwmods = "mcasp0";
758 reg = <0x48038000 0x2000>,
759 <0x46000000 0x400000>;
760 reg-names = "mpu", "dat";
761 interrupts = <80>, <81>;
762 interrupts-names = "tx", "rx";
763 status = "disabled";
764 dmas = <&edma 8>,
765 <&edma 9>;
766 dma-names = "tx", "rx";
767 };
768
769 mcasp1: mcasp@4803C000 {
770 compatible = "ti,am33xx-mcasp-audio";
771 ti,hwmods = "mcasp1";
772 reg = <0x4803C000 0x2000>,
773 <0x46400000 0x400000>;
774 reg-names = "mpu", "dat";
775 interrupts = <82>, <83>;
776 interrupts-names = "tx", "rx";
777 status = "disabled";
778 dmas = <&edma 10>,
779 <&edma 11>;
780 dma-names = "tx", "rx";
781 };
782
783 rng: rng@48310000 {
784 compatible = "ti,omap4-rng";
785 ti,hwmods = "rng";
786 reg = <0x48310000 0x2000>;
787 interrupts = <111>;
788 };
648 }; 789 };
649}; 790};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index ddc1df77ac52..974d103ab3b1 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -18,12 +18,21 @@
18 18
19 19
20 aliases { 20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
21 serial0 = &uart0; 24 serial0 = &uart0;
25 ethernet0 = &cpsw_emac0;
26 ethernet1 = &cpsw_emac1;
22 }; 27 };
23 28
24 cpus { 29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
25 cpu@0 { 32 cpu@0 {
26 compatible = "arm,cortex-a9"; 33 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <0>;
27 }; 36 };
28 }; 37 };
29 38
@@ -35,16 +44,100 @@
35 <0x48240100 0x0100>; 44 <0x48240100 0x0100>;
36 }; 45 };
37 46
47 l2-cache-controller@48242000 {
48 compatible = "arm,pl310-cache";
49 reg = <0x48242000 0x1000>;
50 cache-unified;
51 cache-level = <2>;
52 };
53
54 am43xx_pinmux: pinmux@44e10800 {
55 compatible = "pinctrl-single";
56 reg = <0x44e10800 0x31c>;
57 #address-cells = <1>;
58 #size-cells = <0>;
59 pinctrl-single,register-width = <32>;
60 pinctrl-single,function-mask = <0xffffffff>;
61 };
62
38 ocp { 63 ocp {
39 compatible = "simple-bus"; 64 compatible = "simple-bus";
40 #address-cells = <1>; 65 #address-cells = <1>;
41 #size-cells = <1>; 66 #size-cells = <1>;
42 ranges; 67 ranges;
68 ti,hwmods = "l3_main";
69
70 edma: edma@49000000 {
71 compatible = "ti,edma3";
72 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
73 reg = <0x49000000 0x10000>,
74 <0x44e10f90 0x10>;
75 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
78 #dma-cells = <1>;
79 dma-channels = <64>;
80 ti,edma-regions = <4>;
81 ti,edma-slots = <256>;
82 };
43 83
44 uart0: serial@44e09000 { 84 uart0: serial@44e09000 {
45 compatible = "ti,am4372-uart","ti,omap2-uart"; 85 compatible = "ti,am4372-uart","ti,omap2-uart";
46 reg = <0x44e09000 0x2000>; 86 reg = <0x44e09000 0x2000>;
47 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 87 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
88 ti,hwmods = "uart1";
89 };
90
91 uart1: serial@48022000 {
92 compatible = "ti,am4372-uart","ti,omap2-uart";
93 reg = <0x48022000 0x2000>;
94 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
95 ti,hwmods = "uart2";
96 status = "disabled";
97 };
98
99 uart2: serial@48024000 {
100 compatible = "ti,am4372-uart","ti,omap2-uart";
101 reg = <0x48024000 0x2000>;
102 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
103 ti,hwmods = "uart3";
104 status = "disabled";
105 };
106
107 uart3: serial@481a6000 {
108 compatible = "ti,am4372-uart","ti,omap2-uart";
109 reg = <0x481a6000 0x2000>;
110 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
111 ti,hwmods = "uart4";
112 status = "disabled";
113 };
114
115 uart4: serial@481a8000 {
116 compatible = "ti,am4372-uart","ti,omap2-uart";
117 reg = <0x481a8000 0x2000>;
118 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
119 ti,hwmods = "uart5";
120 status = "disabled";
121 };
122
123 uart5: serial@481aa000 {
124 compatible = "ti,am4372-uart","ti,omap2-uart";
125 reg = <0x481aa000 0x2000>;
126 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
127 ti,hwmods = "uart6";
128 status = "disabled";
129 };
130
131 mailbox: mailbox@480C8000 {
132 compatible = "ti,omap4-mailbox";
133 reg = <0x480C8000 0x200>;
134 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
135 ti,hwmods = "mailbox";
136 ti,mbox-num-users = <4>;
137 ti,mbox-num-fifos = <8>;
138 ti,mbox-names = "wkup_m3";
139 ti,mbox-data = <0 0 0 0>;
140 status = "disabled";
48 }; 141 };
49 142
50 timer1: timer@44e31000 { 143 timer1: timer@44e31000 {
@@ -52,17 +145,523 @@
52 reg = <0x44e31000 0x400>; 145 reg = <0x44e31000 0x400>;
53 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 146 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
54 ti,timer-alwon; 147 ti,timer-alwon;
148 ti,hwmods = "timer1";
55 }; 149 };
56 150
57 timer2: timer@48040000 { 151 timer2: timer@48040000 {
58 compatible = "ti,am4372-timer","ti,am335x-timer"; 152 compatible = "ti,am4372-timer","ti,am335x-timer";
59 reg = <0x48040000 0x400>; 153 reg = <0x48040000 0x400>;
60 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 154 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
155 ti,hwmods = "timer2";
156 };
157
158 timer3: timer@48042000 {
159 compatible = "ti,am4372-timer","ti,am335x-timer";
160 reg = <0x48042000 0x400>;
161 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
162 ti,hwmods = "timer3";
163 status = "disabled";
164 };
165
166 timer4: timer@48044000 {
167 compatible = "ti,am4372-timer","ti,am335x-timer";
168 reg = <0x48044000 0x400>;
169 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
170 ti,timer-pwm;
171 ti,hwmods = "timer4";
172 status = "disabled";
173 };
174
175 timer5: timer@48046000 {
176 compatible = "ti,am4372-timer","ti,am335x-timer";
177 reg = <0x48046000 0x400>;
178 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
179 ti,timer-pwm;
180 ti,hwmods = "timer5";
181 status = "disabled";
182 };
183
184 timer6: timer@48048000 {
185 compatible = "ti,am4372-timer","ti,am335x-timer";
186 reg = <0x48048000 0x400>;
187 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
188 ti,timer-pwm;
189 ti,hwmods = "timer6";
190 status = "disabled";
191 };
192
193 timer7: timer@4804a000 {
194 compatible = "ti,am4372-timer","ti,am335x-timer";
195 reg = <0x4804a000 0x400>;
196 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
197 ti,timer-pwm;
198 ti,hwmods = "timer7";
199 status = "disabled";
200 };
201
202 timer8: timer@481c1000 {
203 compatible = "ti,am4372-timer","ti,am335x-timer";
204 reg = <0x481c1000 0x400>;
205 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
206 ti,hwmods = "timer8";
207 status = "disabled";
208 };
209
210 timer9: timer@4833d000 {
211 compatible = "ti,am4372-timer","ti,am335x-timer";
212 reg = <0x4833d000 0x400>;
213 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
214 ti,hwmods = "timer9";
215 status = "disabled";
216 };
217
218 timer10: timer@4833f000 {
219 compatible = "ti,am4372-timer","ti,am335x-timer";
220 reg = <0x4833f000 0x400>;
221 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
222 ti,hwmods = "timer10";
223 status = "disabled";
224 };
225
226 timer11: timer@48341000 {
227 compatible = "ti,am4372-timer","ti,am335x-timer";
228 reg = <0x48341000 0x400>;
229 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
230 ti,hwmods = "timer11";
231 status = "disabled";
61 }; 232 };
62 233
63 counter32k: counter@44e86000 { 234 counter32k: counter@44e86000 {
64 compatible = "ti,am4372-counter32k","ti,omap-counter32k"; 235 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
65 reg = <0x44e86000 0x40>; 236 reg = <0x44e86000 0x40>;
237 ti,hwmods = "counter_32k";
238 };
239
240 rtc@44e3e000 {
241 compatible = "ti,am4372-rtc","ti,da830-rtc";
242 reg = <0x44e3e000 0x1000>;
243 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
245 ti,hwmods = "rtc";
246 status = "disabled";
247 };
248
249 wdt@44e35000 {
250 compatible = "ti,am4372-wdt","ti,omap3-wdt";
251 reg = <0x44e35000 0x1000>;
252 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
253 ti,hwmods = "wd_timer2";
254 };
255
256 gpio0: gpio@44e07000 {
257 compatible = "ti,am4372-gpio","ti,omap4-gpio";
258 reg = <0x44e07000 0x1000>;
259 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
260 gpio-controller;
261 #gpio-cells = <2>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 ti,hwmods = "gpio1";
265 status = "disabled";
266 };
267
268 gpio1: gpio@4804c000 {
269 compatible = "ti,am4372-gpio","ti,omap4-gpio";
270 reg = <0x4804c000 0x1000>;
271 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
272 gpio-controller;
273 #gpio-cells = <2>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 ti,hwmods = "gpio2";
277 status = "disabled";
278 };
279
280 gpio2: gpio@481ac000 {
281 compatible = "ti,am4372-gpio","ti,omap4-gpio";
282 reg = <0x481ac000 0x1000>;
283 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
284 gpio-controller;
285 #gpio-cells = <2>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 ti,hwmods = "gpio3";
289 status = "disabled";
290 };
291
292 gpio3: gpio@481ae000 {
293 compatible = "ti,am4372-gpio","ti,omap4-gpio";
294 reg = <0x481ae000 0x1000>;
295 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
296 gpio-controller;
297 #gpio-cells = <2>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
300 ti,hwmods = "gpio4";
301 status = "disabled";
302 };
303
304 gpio4: gpio@48320000 {
305 compatible = "ti,am4372-gpio","ti,omap4-gpio";
306 reg = <0x48320000 0x1000>;
307 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 ti,hwmods = "gpio5";
313 status = "disabled";
314 };
315
316 gpio5: gpio@48322000 {
317 compatible = "ti,am4372-gpio","ti,omap4-gpio";
318 reg = <0x48322000 0x1000>;
319 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 ti,hwmods = "gpio6";
325 status = "disabled";
326 };
327
328 i2c0: i2c@44e0b000 {
329 compatible = "ti,am4372-i2c","ti,omap4-i2c";
330 reg = <0x44e0b000 0x1000>;
331 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
332 ti,hwmods = "i2c1";
333 #address-cells = <1>;
334 #size-cells = <0>;
335 status = "disabled";
336 };
337
338 i2c1: i2c@4802a000 {
339 compatible = "ti,am4372-i2c","ti,omap4-i2c";
340 reg = <0x4802a000 0x1000>;
341 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
342 ti,hwmods = "i2c2";
343 #address-cells = <1>;
344 #size-cells = <0>;
345 status = "disabled";
346 };
347
348 i2c2: i2c@4819c000 {
349 compatible = "ti,am4372-i2c","ti,omap4-i2c";
350 reg = <0x4819c000 0x1000>;
351 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
352 ti,hwmods = "i2c3";
353 #address-cells = <1>;
354 #size-cells = <0>;
355 status = "disabled";
356 };
357
358 spi0: spi@48030000 {
359 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
360 reg = <0x48030000 0x400>;
361 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
362 ti,hwmods = "spi0";
363 #address-cells = <1>;
364 #size-cells = <0>;
365 status = "disabled";
366 };
367
368 mmc1: mmc@48060000 {
369 compatible = "ti,omap4-hsmmc";
370 reg = <0x48060000 0x1000>;
371 ti,hwmods = "mmc1";
372 ti,dual-volt;
373 ti,needs-special-reset;
374 dmas = <&edma 24
375 &edma 25>;
376 dma-names = "tx", "rx";
377 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
378 status = "disabled";
379 };
380
381 mmc2: mmc@481d8000 {
382 compatible = "ti,omap4-hsmmc";
383 reg = <0x481d8000 0x1000>;
384 ti,hwmods = "mmc2";
385 ti,needs-special-reset;
386 dmas = <&edma 2
387 &edma 3>;
388 dma-names = "tx", "rx";
389 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
390 status = "disabled";
391 };
392
393 mmc3: mmc@47810000 {
394 compatible = "ti,omap4-hsmmc";
395 reg = <0x47810000 0x1000>;
396 ti,hwmods = "mmc3";
397 ti,needs-special-reset;
398 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
399 status = "disabled";
400 };
401
402 spi1: spi@481a0000 {
403 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
404 reg = <0x481a0000 0x400>;
405 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
406 ti,hwmods = "spi1";
407 #address-cells = <1>;
408 #size-cells = <0>;
409 status = "disabled";
410 };
411
412 spi2: spi@481a2000 {
413 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
414 reg = <0x481a2000 0x400>;
415 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
416 ti,hwmods = "spi2";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 status = "disabled";
420 };
421
422 spi3: spi@481a4000 {
423 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
424 reg = <0x481a4000 0x400>;
425 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
426 ti,hwmods = "spi3";
427 #address-cells = <1>;
428 #size-cells = <0>;
429 status = "disabled";
430 };
431
432 spi4: spi@48345000 {
433 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
434 reg = <0x48345000 0x400>;
435 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
436 ti,hwmods = "spi4";
437 #address-cells = <1>;
438 #size-cells = <0>;
439 status = "disabled";
440 };
441
442 mac: ethernet@4a100000 {
443 compatible = "ti,am4372-cpsw","ti,cpsw";
444 reg = <0x4a100000 0x800
445 0x4a101200 0x100>;
446 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
447 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
448 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
449 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
450 #address-cells = <1>;
451 #size-cells = <1>;
452 ti,hwmods = "cpgmac0";
453 status = "disabled";
454 cpdma_channels = <8>;
455 ale_entries = <1024>;
456 bd_ram_size = <0x2000>;
457 no_bd_ram = <0>;
458 rx_descs = <64>;
459 mac_control = <0x20>;
460 slaves = <2>;
461 active_slave = <0>;
462 cpts_clock_mult = <0x80000000>;
463 cpts_clock_shift = <29>;
464 ranges;
465
466 davinci_mdio: mdio@4a101000 {
467 compatible = "ti,am4372-mdio","ti,davinci_mdio";
468 reg = <0x4a101000 0x100>;
469 #address-cells = <1>;
470 #size-cells = <0>;
471 ti,hwmods = "davinci_mdio";
472 bus_freq = <1000000>;
473 status = "disabled";
474 };
475
476 cpsw_emac0: slave@4a100200 {
477 /* Filled in by U-Boot */
478 mac-address = [ 00 00 00 00 00 00 ];
479 };
480
481 cpsw_emac1: slave@4a100300 {
482 /* Filled in by U-Boot */
483 mac-address = [ 00 00 00 00 00 00 ];
484 };
485 };
486
487 epwmss0: epwmss@48300000 {
488 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
489 reg = <0x48300000 0x10>;
490 #address-cells = <1>;
491 #size-cells = <1>;
492 ranges;
493 ti,hwmods = "epwmss0";
494 status = "disabled";
495
496 ecap0: ecap@48300100 {
497 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
498 reg = <0x48300100 0x80>;
499 ti,hwmods = "ecap0";
500 status = "disabled";
501 };
502
503 ehrpwm0: ehrpwm@48300200 {
504 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
505 reg = <0x48300200 0x80>;
506 ti,hwmods = "ehrpwm0";
507 status = "disabled";
508 };
509 };
510
511 epwmss1: epwmss@48302000 {
512 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
513 reg = <0x48302000 0x10>;
514 #address-cells = <1>;
515 #size-cells = <1>;
516 ranges;
517 ti,hwmods = "epwmss1";
518 status = "disabled";
519
520 ecap1: ecap@48302100 {
521 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
522 reg = <0x48302100 0x80>;
523 ti,hwmods = "ecap1";
524 status = "disabled";
525 };
526
527 ehrpwm1: ehrpwm@48302200 {
528 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
529 reg = <0x48302200 0x80>;
530 ti,hwmods = "ehrpwm1";
531 status = "disabled";
532 };
533 };
534
535 epwmss2: epwmss@48304000 {
536 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
537 reg = <0x48304000 0x10>;
538 #address-cells = <1>;
539 #size-cells = <1>;
540 ranges;
541 ti,hwmods = "epwmss2";
542 status = "disabled";
543
544 ecap2: ecap@48304100 {
545 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
546 reg = <0x48304100 0x80>;
547 ti,hwmods = "ecap2";
548 status = "disabled";
549 };
550
551 ehrpwm2: ehrpwm@48304200 {
552 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
553 reg = <0x48304200 0x80>;
554 ti,hwmods = "ehrpwm2";
555 status = "disabled";
556 };
557 };
558
559 epwmss3: epwmss@48306000 {
560 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
561 reg = <0x48306000 0x10>;
562 #address-cells = <1>;
563 #size-cells = <1>;
564 ranges;
565 ti,hwmods = "epwmss3";
566 status = "disabled";
567
568 ehrpwm3: ehrpwm@48306200 {
569 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
570 reg = <0x48306200 0x80>;
571 ti,hwmods = "ehrpwm3";
572 status = "disabled";
573 };
574 };
575
576 epwmss4: epwmss@48308000 {
577 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
578 reg = <0x48308000 0x10>;
579 #address-cells = <1>;
580 #size-cells = <1>;
581 ranges;
582 ti,hwmods = "epwmss4";
583 status = "disabled";
584
585 ehrpwm4: ehrpwm@48308200 {
586 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
587 reg = <0x48308200 0x80>;
588 ti,hwmods = "ehrpwm4";
589 status = "disabled";
590 };
591 };
592
593 epwmss5: epwmss@4830a000 {
594 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
595 reg = <0x4830a000 0x10>;
596 #address-cells = <1>;
597 #size-cells = <1>;
598 ranges;
599 ti,hwmods = "epwmss5";
600 status = "disabled";
601
602 ehrpwm5: ehrpwm@4830a200 {
603 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
604 reg = <0x4830a200 0x80>;
605 ti,hwmods = "ehrpwm5";
606 status = "disabled";
607 };
608 };
609
610 sham: sham@53100000 {
611 compatible = "ti,omap5-sham";
612 ti,hwmods = "sham";
613 reg = <0x53100000 0x300>;
614 dmas = <&edma 36>;
615 dma-names = "rx";
616 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
617 };
618
619 aes: aes@53501000 {
620 compatible = "ti,omap4-aes";
621 ti,hwmods = "aes";
622 reg = <0x53501000 0xa0>;
623 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
624 dmas = <&edma 6
625 &edma 5>;
626 dma-names = "tx", "rx";
627 };
628
629 des: des@53701000 {
630 compatible = "ti,omap4-des";
631 ti,hwmods = "des";
632 reg = <0x53701000 0xa0>;
633 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
634 dmas = <&edma 34
635 &edma 33>;
636 dma-names = "tx", "rx";
637 };
638
639 mcasp0: mcasp@48038000 {
640 compatible = "ti,am33xx-mcasp-audio";
641 ti,hwmods = "mcasp0";
642 reg = <0x48038000 0x2000>,
643 <0x46000000 0x400000>;
644 reg-names = "mpu", "dat";
645 interrupts = <80>, <81>;
646 interrupts-names = "tx", "rx";
647 status = "disabled";
648 dmas = <&edma 8>,
649 <&edma 9>;
650 dma-names = "tx", "rx";
651 };
652
653 mcasp1: mcasp@4803C000 {
654 compatible = "ti,am33xx-mcasp-audio";
655 ti,hwmods = "mcasp1";
656 reg = <0x4803C000 0x2000>,
657 <0x46400000 0x400000>;
658 reg-names = "mpu", "dat";
659 interrupts = <82>, <83>;
660 interrupts-names = "tx", "rx";
661 status = "disabled";
662 dmas = <&edma 10>,
663 <&edma 11>;
664 dma-names = "tx", "rx";
66 }; 665 };
67 }; 666 };
68}; 667};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 74174d48f476..fbf9c4c7a94f 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -11,8 +11,176 @@
11/dts-v1/; 11/dts-v1/;
12 12
13#include "am4372.dtsi" 13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/gpio/gpio.h>
14 16
15/ { 17/ {
16 model = "TI AM43x EPOS EVM"; 18 model = "TI AM43x EPOS EVM";
17 compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; 19 compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
20
21 vmmcsd_fixed: fixedregulator-sd {
22 compatible = "regulator-fixed";
23 regulator-name = "vmmcsd_fixed";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 enable-active-high;
27 };
28
29 am43xx_pinmux: pinmux@44e10800 {
30 cpsw_default: cpsw_default {
31 pinctrl-single,pins = <
32 /* Slave 1 */
33 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
34 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
35 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
36 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
37 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
38 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
39 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
40 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
41 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
42 >;
43 };
44
45 cpsw_sleep: cpsw_sleep {
46 pinctrl-single,pins = <
47 /* Slave 1 reset value */
48 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
49 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
50 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
51 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
52 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
53 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
54 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
55 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
56 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
57 >;
58 };
59
60 davinci_mdio_default: davinci_mdio_default {
61 pinctrl-single,pins = <
62 /* MDIO */
63 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
64 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
65 >;
66 };
67
68 davinci_mdio_sleep: davinci_mdio_sleep {
69 pinctrl-single,pins = <
70 /* MDIO reset value */
71 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
72 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
73 >;
74 };
75
76 i2c0_pins: pinmux_i2c0_pins {
77 pinctrl-single,pins = <
78 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
79 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
80 >;
81 };
82 };
83
84 matrix_keypad: matrix_keypad@0 {
85 compatible = "gpio-matrix-keypad";
86 debounce-delay-ms = <5>;
87 col-scan-delay-us = <2>;
88
89 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
90 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
91 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
92 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
93
94 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
95 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
96 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
97 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
98
99 linux,keymap = <0x00000201 /* P1 */
100 0x01000204 /* P4 */
101 0x02000207 /* P7 */
102 0x0300020a /* NUMERIC_STAR */
103 0x00010202 /* P2 */
104 0x01010205 /* P5 */
105 0x02010208 /* P8 */
106 0x03010200 /* P0 */
107 0x00020203 /* P3 */
108 0x01020206 /* P6 */
109 0x02020209 /* P9 */
110 0x0302020b /* NUMERIC_POUND */
111 0x00030067 /* UP */
112 0x0103006a /* RIGHT */
113 0x0203006c /* DOWN */
114 0x03030069>; /* LEFT */
115 };
116};
117
118&mmc1 {
119 status = "okay";
120 vmmc-supply = <&vmmcsd_fixed>;
121 bus-width = <4>;
122};
123
124&mac {
125 pinctrl-names = "default", "sleep";
126 pinctrl-0 = <&cpsw_default>;
127 pinctrl-1 = <&cpsw_sleep>;
128 status = "okay";
129};
130
131&davinci_mdio {
132 pinctrl-names = "default", "sleep";
133 pinctrl-0 = <&davinci_mdio_default>;
134 pinctrl-1 = <&davinci_mdio_sleep>;
135 status = "okay";
136};
137
138&cpsw_emac0 {
139 phy_id = <&davinci_mdio>, <16>;
140 phy-mode = "rmii";
141};
142
143&cpsw_emac1 {
144 phy_id = <&davinci_mdio>, <1>;
145 phy-mode = "rmii";
146};
147
148&i2c0 {
149 status = "okay";
150 pinctrl-names = "default";
151 pinctrl-0 = <&i2c0_pins>;
152
153 at24@50 {
154 compatible = "at24,24c256";
155 pagesize = <64>;
156 reg = <0x50>;
157 };
158
159 pixcir_ts@5c {
160 compatible = "pixcir,pixcir_ts";
161 reg = <0x5c>;
162 interrupt-parent = <&gpio1>;
163 interrupts = <17 0>;
164
165 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
166
167 x-size = <1024>;
168 y-size = <768>;
169 };
170};
171
172&gpio0 {
173 status = "okay";
174};
175
176&gpio1 {
177 status = "okay";
178};
179
180&gpio2 {
181 status = "okay";
182};
183
184&gpio3 {
185 status = "okay";
18}; 186};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
new file mode 100644
index 000000000000..b0b32f5fbeb4
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -0,0 +1,193 @@
1/*
2 * Device Tree file for NETGEAR ReadyNAS 104
3 *
4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/dts-v1/;
13
14#include "armada-370.dtsi"
15
16/ {
17 model = "NETGEAR ReadyNAS 104";
18 compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 earlyprintk";
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0x20000000>; /* 512 MB */
27 };
28
29 soc {
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
31 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
32
33 pcie-controller {
34 status = "okay";
35
36 /* Connected to FL1009 USB 3.0 controller */
37 pcie@1,0 {
38 /* Port 0, Lane 0 */
39 status = "okay";
40 };
41
42 /* Connected to Marvell 88SE9215 SATA controller */
43 pcie@2,0 {
44 /* Port 1, Lane 0 */
45 status = "okay";
46 };
47 };
48
49 internal-regs {
50 serial@12000 {
51 clock-frequency = <200000000>;
52 status = "okay";
53 };
54
55 pinctrl {
56 poweroff: poweroff {
57 marvell,pins = "mpp60";
58 marvell,function = "gpio";
59 };
60
61 backup_key_pin: backup-key-pin {
62 marvell,pins = "mpp52";
63 marvell,function = "gpio";
64 };
65
66 power_key_pin: power-key-pin {
67 marvell,pins = "mpp62";
68 marvell,function = "gpio";
69 };
70
71 backup_led_pin: backup-led-pin {
72 marvell,pins = "mpp63";
73 marvell,function = "gpo";
74 };
75
76 power_led_pin: power-led-pin {
77 marvell,pins = "mpp64";
78 marvell,function = "gpio";
79 };
80
81 reset_key_pin: reset-key-pin {
82 marvell,pins = "mpp65";
83 marvell,function = "gpio";
84 };
85 };
86
87 mdio {
88 phy0: ethernet-phy@0 {
89 reg = <0>;
90 };
91
92 phy1: ethernet-phy@1 {
93 reg = <1>;
94 };
95 };
96
97 ethernet@70000 {
98 status = "okay";
99 phy = <&phy0>;
100 phy-mode = "rgmii-id";
101 };
102
103 ethernet@74000 {
104 status = "okay";
105 phy = <&phy1>;
106 phy-mode = "rgmii-id";
107 };
108
109 usb@50000 {
110 status = "okay";
111 };
112
113 i2c@11000 {
114 compatible = "marvell,mv64xxx-i2c";
115 clock-frequency = <100000>;
116 status = "okay";
117
118 g762: g762@3e {
119 compatible = "gmt,g762";
120 reg = <0x3e>;
121 clocks = <&g762_clk>; /* input clock */
122 fan_gear_mode = <0>;
123 fan_startv = <1>;
124 pwm_polarity = <0>;
125 };
126 };
127 };
128 };
129
130 clocks {
131 #address-cells = <1>;
132 #size-cells = <0>;
133
134 g762_clk: fixedclk {
135 compatible = "fixed-clock";
136 #clock-cells = <0>;
137 clock-frequency = <8192>;
138 };
139 };
140
141 gpio_leds {
142 compatible = "gpio-leds";
143 pinctrl-0 = <&backup_led_pin &power_led_pin>;
144 pinctrl-names = "default";
145
146 blue_backup_led {
147 label = "rn104:blue:backup";
148 gpios = <&gpio1 31 0>; /* GPIO 63 Active High */
149 default-state = "off";
150 };
151
152 blue_power_led {
153 label = "rn104:blue:pwr";
154 gpios = <&gpio2 0 1>; /* GPIO 64 Active Low */
155 linux,default-trigger = "keep";
156 };
157 };
158
159 gpio_keys {
160 compatible = "gpio-keys";
161 #address-cells = <1>;
162 #size-cells = <0>;
163 pinctrl-0 = <&backup_key_pin
164 &power_key_pin
165 &reset_key_pin>;
166 pinctrl-names = "default";
167
168 button@1 {
169 label = "Backup Button";
170 linux,code = <133>; /* KEY_COPY */
171 gpios = <&gpio1 20 1>;
172 };
173
174 button@2 {
175 label = "Power Button";
176 linux,code = <116>; /* KEY_POWER */
177 gpios = <&gpio1 30 0>;
178 };
179
180 button@3 {
181 label = "Reset Button";
182 linux,code = <0x198>; /* KEY_RESTART */
183 gpios = <&gpio2 1 1>;
184 };
185 };
186
187 gpio_poweroff {
188 compatible = "gpio-poweroff";
189 pinctrl-0 = <&poweroff>;
190 pinctrl-names = "default";
191 gpios = <&gpio1 28 1>;
192 };
193};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 1de2dae0fdae..00d6a798c705 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -113,6 +113,7 @@
113 #interrupt-cells = <1>; 113 #interrupt-cells = <1>;
114 #size-cells = <1>; 114 #size-cells = <1>;
115 interrupt-controller; 115 interrupt-controller;
116 msi-controller;
116 }; 117 };
117 118
118 coherency-fabric@20200 { 119 coherency-fabric@20200 {
@@ -137,6 +138,14 @@
137 status = "disabled"; 138 status = "disabled";
138 }; 139 };
139 140
141 coredivclk: corediv-clock@18740 {
142 compatible = "marvell,armada-370-corediv-clock";
143 reg = <0x18740 0xc>;
144 #clock-cells = <1>;
145 clocks = <&mainpll>;
146 clock-output-names = "nand";
147 };
148
140 timer@20300 { 149 timer@20300 {
141 reg = <0x20300 0x30>, <0x21040 0x30>; 150 reg = <0x20300 0x30>, <0x21040 0x30>;
142 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 151 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
@@ -176,7 +185,6 @@
176 185
177 i2c0: i2c@11000 { 186 i2c0: i2c@11000 {
178 compatible = "marvell,mv64xxx-i2c"; 187 compatible = "marvell,mv64xxx-i2c";
179 reg = <0x11000 0x20>;
180 #address-cells = <1>; 188 #address-cells = <1>;
181 #size-cells = <0>; 189 #size-cells = <0>;
182 interrupts = <31>; 190 interrupts = <31>;
@@ -187,7 +195,6 @@
187 195
188 i2c1: i2c@11100 { 196 i2c1: i2c@11100 {
189 compatible = "marvell,mv64xxx-i2c"; 197 compatible = "marvell,mv64xxx-i2c";
190 reg = <0x11100 0x20>;
191 #address-cells = <1>; 198 #address-cells = <1>;
192 #size-cells = <0>; 199 #size-cells = <0>;
193 interrupts = <32>; 200 interrupts = <32>;
@@ -252,4 +259,13 @@
252 259
253 }; 260 };
254 }; 261 };
262
263 clocks {
264 /* 2 GHz fixed main PLL */
265 mainpll: mainpll {
266 compatible = "fixed-clock";
267 #clock-cells = <0>;
268 clock-frequency = <2000000000>;
269 };
270 };
255 }; 271 };
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index e134d7a90c9a..7a4b82e71aaf 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -44,6 +44,7 @@
44 #address-cells = <3>; 44 #address-cells = <3>;
45 #size-cells = <2>; 45 #size-cells = <2>;
46 46
47 msi-parent = <&mpic>;
47 bus-range = <0x00 0xff>; 48 bus-range = <0x00 0xff>;
48 49
49 ranges = 50 ranges =
@@ -218,6 +219,14 @@
218 }; 219 };
219 }; 220 };
220 221
222 i2c0: i2c@11000 {
223 reg = <0x11000 0x20>;
224 };
225
226 i2c1: i2c@11100 {
227 reg = <0x11100 0x20>;
228 };
229
221 usb@50000 { 230 usb@50000 {
222 clocks = <&coreclk 0>; 231 clocks = <&coreclk 0>;
223 }; 232 };
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
new file mode 100644
index 000000000000..e47c49ecd55c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -0,0 +1,75 @@
1/*
2 * Device Tree file for Marvell Armada XP Matrix board
3 *
4 * Copyright (C) 2013 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13/dts-v1/;
14#include "armada-xp-mv78460.dtsi"
15
16/ {
17 model = "Marvell Armada XP Matrix Board";
18 compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 earlyprintk";
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
27 };
28
29 soc {
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
31 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
32
33 internal-regs {
34 serial@12000 {
35 clock-frequency = <250000000>;
36 status = "okay";
37 };
38 serial@12100 {
39 clock-frequency = <250000000>;
40 status = "okay";
41 };
42 serial@12200 {
43 clock-frequency = <250000000>;
44 status = "okay";
45 };
46 serial@12300 {
47 clock-frequency = <250000000>;
48 status = "okay";
49 };
50
51 sata@a0000 {
52 nr-ports = <2>;
53 status = "okay";
54 };
55
56 ethernet@30000 {
57 status = "okay";
58 phy-mode = "sgmii";
59 };
60
61 pcie-controller {
62 status = "okay";
63
64 pcie@1,0 {
65 /* Port 0, Lane 0 */
66 status = "okay";
67 };
68 };
69
70 usb@50000 {
71 status = "okay";
72 };
73 };
74 };
75};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 0358a33cba48..3f5e6121c730 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -57,6 +57,7 @@
57 #address-cells = <3>; 57 #address-cells = <3>;
58 #size-cells = <2>; 58 #size-cells = <2>;
59 59
60 msi-parent = <&mpic>;
60 bus-range = <0x00 0xff>; 61 bus-range = <0x00 0xff>;
61 62
62 ranges = 63 ranges =
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 0e82c5062243..3e9fd1353f89 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -58,6 +58,7 @@
58 #address-cells = <3>; 58 #address-cells = <3>;
59 #size-cells = <2>; 59 #size-cells = <2>;
60 60
61 msi-parent = <&mpic>;
61 bus-range = <0x00 0xff>; 62 bus-range = <0x00 0xff>;
62 63
63 ranges = 64 ranges =
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index e82c1b80af17..31ba6d8fbadf 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -74,6 +74,7 @@
74 #address-cells = <3>; 74 #address-cells = <3>;
75 #size-cells = <2>; 75 #size-cells = <2>;
76 76
77 msi-parent = <&mpic>;
77 bus-range = <0x00 0xff>; 78 bus-range = <0x00 0xff>;
78 79
79 ranges = 80 ranges =
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 3058522f5aad..281c6447e872 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -147,6 +147,16 @@
147 }; 147 };
148 }; 148 };
149 149
150 i2c0: i2c@11000 {
151 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
152 reg = <0x11000 0x100>;
153 };
154
155 i2c1: i2c@11100 {
156 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
157 reg = <0x11100 0x100>;
158 };
159
150 usb@50000 { 160 usb@50000 {
151 clocks = <&gateclk 18>; 161 clocks = <&gateclk 18>;
152 }; 162 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 137354689ad0..cb2c010e08e2 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -96,7 +96,6 @@
96 }; 96 };
97 97
98 spi0: spi@fffc8000 { 98 spi0: spi@fffc8000 {
99 status = "okay";
100 cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; 99 cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
101 mtd_dataflash@0 { 100 mtd_dataflash@0 {
102 compatible = "atmel,at45", "atmel,dataflash"; 101 compatible = "atmel,at45", "atmel,dataflash";
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 9fb7ffd32af2..6224f9fe2f2b 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -437,6 +437,9 @@
437 compatible = "atmel,at91sam9g45-ssc"; 437 compatible = "atmel,at91sam9g45-ssc";
438 reg = <0xf0010000 0x4000>; 438 reg = <0xf0010000 0x4000>;
439 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 439 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
440 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
441 <&dma 0 AT91_DMA_CFG_PER_ID(22)>;
442 dma-names = "tx", "rx";
440 pinctrl-names = "default"; 443 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 444 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
442 status = "disabled"; 445 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 27a9352b9d7a..e9487f6f0166 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -38,9 +38,18 @@
38 status = "okay"; 38 status = "okay";
39 }; 39 };
40 40
41 ssc0: ssc@f0010000 {
42 status = "okay";
43 };
44
41 i2c0: i2c@f8010000 { 45 i2c0: i2c@f8010000 {
42 status = "okay"; 46 status = "okay";
43 47
48 wm8904: codec@1a {
49 compatible = "wm8904";
50 reg = <0x1a>;
51 };
52
44 qt1070: keyboard@1b { 53 qt1070: keyboard@1b {
45 compatible = "qt1070"; 54 compatible = "qt1070";
46 reg = <0x1b>; 55 reg = <0x1b>;
@@ -82,6 +91,13 @@
82 <AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; 91 <AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
83 }; 92 };
84 }; 93 };
94
95 sound {
96 pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
97 atmel,pins =
98 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
99 };
100 };
85 }; 101 };
86 102
87 spi0: spi@f0000000 { 103 spi0: spi@f0000000 {
@@ -142,4 +158,22 @@
142 gpio-key,wakeup; 158 gpio-key,wakeup;
143 }; 159 };
144 }; 160 };
161
162 sound {
163 compatible = "atmel,asoc-wm8904";
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
166
167 atmel,model = "wm8904 @ AT91SAM9N12";
168 atmel,audio-routing =
169 "Headphone Jack", "HPOUTL",
170 "Headphone Jack", "HPOUTR",
171 "IN2L", "Line In Jack",
172 "IN2R", "Line In Jack",
173 "Mic", "MICBIAS",
174 "IN1L", "Mic";
175
176 atmel,ssc-controller = <&ssc0>;
177 atmel,audio-codec = <&wm8904>;
178 };
145}; 179};
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 6db4f81d4795..a49032c6e199 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -65,6 +65,11 @@
65 compatible = "sirf,prima2-rsc"; 65 compatible = "sirf,prima2-rsc";
66 reg = <0x88020000 0x1000>; 66 reg = <0x88020000 0x1000>;
67 }; 67 };
68
69 cphifbg@88030000 {
70 compatible = "sirf,prima2-cphifbg";
71 reg = <0x88030000 0x1000>;
72 };
68 }; 73 };
69 74
70 mem-iobg { 75 mem-iobg {
@@ -75,10 +80,17 @@
75 80
76 memory-controller@90000000 { 81 memory-controller@90000000 {
77 compatible = "sirf,prima2-memc"; 82 compatible = "sirf,prima2-memc";
78 reg = <0x90000000 0x10000>; 83 reg = <0x90000000 0x2000>;
79 interrupts = <27>; 84 interrupts = <27>;
80 clocks = <&clks 5>; 85 clocks = <&clks 5>;
81 }; 86 };
87
88 memc-monitor {
89 compatible = "sirf,prima2-memcmon";
90 reg = <0x90002000 0x200>;
91 interrupts = <4>;
92 clocks = <&clks 32>;
93 };
82 }; 94 };
83 95
84 disp-iobg { 96 disp-iobg {
@@ -120,6 +132,20 @@
120 }; 132 };
121 }; 133 };
122 134
135 graphics2d-iobg {
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0xa0000000 0xa0000000 0x8000000>;
140
141 ble@a0000000 {
142 compatible = "sirf,atlas6-ble";
143 reg = <0xa0000000 0x2000>;
144 interrupts = <5>;
145 clocks = <&clks 33>;
146 };
147 };
148
123 dsp-iobg { 149 dsp-iobg {
124 compatible = "simple-bus"; 150 compatible = "simple-bus";
125 #address-cells = <1>; 151 #address-cells = <1>;
@@ -271,6 +297,11 @@
271 compatible = "sirf,prima2-spi"; 297 compatible = "sirf,prima2-spi";
272 reg = <0xb0170000 0x10000>; 298 reg = <0xb0170000 0x10000>;
273 interrupts = <16>; 299 interrupts = <16>;
300 sirf,spi-num-chipselects = <1>;
301 sirf,spi-dma-rx-channel = <12>;
302 sirf,spi-dma-tx-channel = <13>;
303 #address-cells = <1>;
304 #size-cells = <0>;
274 clocks = <&clks 20>; 305 clocks = <&clks 20>;
275 status = "disabled"; 306 status = "disabled";
276 }; 307 };
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 9d36eb4e3c41..23cd16d736bf 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -40,6 +40,7 @@
40 40
41 sdio4: sdio@3f1b0000 { 41 sdio4: sdio@3f1b0000 {
42 max-frequency = <48000000>; 42 max-frequency = <48000000>;
43 cd-gpios = <&gpio 14 0>;
43 status = "okay"; 44 status = "okay";
44 }; 45 };
45 46
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 05a5aabe3b2c..b0c0610d1395 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -49,6 +49,36 @@
49 reg-io-width = <4>; 49 reg-io-width = <4>;
50 }; 50 };
51 51
52 uart@3e001000 {
53 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
54 status = "disabled";
55 reg = <0x3e001000 0x1000>;
56 clock-frequency = <13000000>;
57 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
58 reg-shift = <2>;
59 reg-io-width = <4>;
60 };
61
62 uart@3e002000 {
63 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
64 status = "disabled";
65 reg = <0x3e002000 0x1000>;
66 clock-frequency = <13000000>;
67 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
68 reg-shift = <2>;
69 reg-io-width = <4>;
70 };
71
72 uart@3e003000 {
73 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
74 status = "disabled";
75 reg = <0x3e003000 0x1000>;
76 clock-frequency = <13000000>;
77 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
78 reg-shift = <2>;
79 reg-io-width = <4>;
80 };
81
52 L2: l2-cache { 82 L2: l2-cache {
53 compatible = "brcm,bcm11351-a2-pl310-cache"; 83 compatible = "brcm,bcm11351-a2-pl310-cache";
54 reg = <0x3ff20000 0x1000>; 84 reg = <0x3ff20000 0x1000>;
@@ -68,31 +98,47 @@
68 clock-frequency = <32768>; 98 clock-frequency = <32768>;
69 }; 99 };
70 100
101 gpio: gpio@35003000 {
102 compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
103 reg = <0x35003000 0x800>;
104 interrupts =
105 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
106 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
107 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
108 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
110 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
111 #gpio-cells = <2>;
112 #interrupt-cells = <2>;
113 gpio-controller;
114 interrupt-controller;
115 };
116
71 sdio1: sdio@3f180000 { 117 sdio1: sdio@3f180000 {
72 compatible = "brcm,kona-sdhci"; 118 compatible = "brcm,kona-sdhci";
73 reg = <0x3f180000 0x10000>; 119 reg = <0x3f180000 0x10000>;
74 interrupts = <0x0 77 0x4>; 120 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
75 status = "disabled"; 121 status = "disabled";
76 }; 122 };
77 123
78 sdio2: sdio@3f190000 { 124 sdio2: sdio@3f190000 {
79 compatible = "brcm,kona-sdhci"; 125 compatible = "brcm,kona-sdhci";
80 reg = <0x3f190000 0x10000>; 126 reg = <0x3f190000 0x10000>;
81 interrupts = <0x0 76 0x4>; 127 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
82 status = "disabled"; 128 status = "disabled";
83 }; 129 };
84 130
85 sdio3: sdio@3f1a0000 { 131 sdio3: sdio@3f1a0000 {
86 compatible = "brcm,kona-sdhci"; 132 compatible = "brcm,kona-sdhci";
87 reg = <0x3f1a0000 0x10000>; 133 reg = <0x3f1a0000 0x10000>;
88 interrupts = <0x0 74 0x4>; 134 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
89 status = "disabled"; 135 status = "disabled";
90 }; 136 };
91 137
92 sdio4: sdio@3f1b0000 { 138 sdio4: sdio@3f1b0000 {
93 compatible = "brcm,kona-sdhci"; 139 compatible = "brcm,kona-sdhci";
94 reg = <0x3f1b0000 0x10000>; 140 reg = <0x3f1b0000 0x10000>;
95 interrupts = <0x0 73 0x4>; 141 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
96 status = "disabled"; 142 status = "disabled";
97 }; 143 };
98 144
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index 96ae67a2f0d3..08e47c285227 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -40,6 +40,7 @@
40 40
41 sdio4: sdio@3f1b0000 { 41 sdio4: sdio@3f1b0000 {
42 max-frequency = <48000000>; 42 max-frequency = <48000000>;
43 cd-gpios = <&gpio 14 0>;
43 status = "okay"; 44 status = "okay";
44 }; 45 };
45}; 46};
diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
index 61a8062e56de..50c0d6904497 100644
--- a/arch/arm/boot/dts/dove-cm-a510.dts
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "dove.dtsi" 3#include "dove.dtsi"
4 4
5/ { 5/ {
6 model = "Compulab CM-A510"; 6 model = "Compulab CM-A510";
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 022646ef4b38..8349a248ecea 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "dove.dtsi" 3#include "dove.dtsi"
4 4
5/ { 5/ {
6 model = "SolidRun CuBox"; 6 model = "SolidRun CuBox";
@@ -99,18 +99,12 @@
99 silabs,pll-master; 99 silabs,pll-master;
100 }; 100 };
101 101
102 clkout1 {
103 reg = <1>;
104 silabs,drive-strength = <8>;
105 silabs,multisynth-source = <1>;
106 silabs,clock-source = <0>;
107 silabs,pll-master;
108 };
109
110 clkout2 { 102 clkout2 {
111 reg = <2>; 103 reg = <2>;
104 silabs,drive-strength = <8>;
112 silabs,multisynth-source = <1>; 105 silabs,multisynth-source = <1>;
113 silabs,clock-source = <0>; 106 silabs,clock-source = <0>;
107 silabs,pll-master;
114 }; 108 };
115 }; 109 };
116}; 110};
@@ -132,3 +126,11 @@
132 reg = <0>; 126 reg = <0>;
133 }; 127 };
134}; 128};
129
130&audio1 {
131 status = "okay";
132 clocks = <&gate_clk 13>, <&si5351 2>;
133 clock-names = "internal", "extclk";
134 pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>;
135 pinctrl-names = "default";
136};
diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts
index e2222ce94f2f..c11d3636c8e5 100644
--- a/arch/arm/boot/dts/dove-d2plug.dts
+++ b/arch/arm/boot/dts/dove-d2plug.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "dove.dtsi" 3#include "dove.dtsi"
4 4
5/ { 5/ {
6 model = "Globalscale D2Plug"; 6 model = "Globalscale D2Plug";
diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts
new file mode 100644
index 000000000000..f5f59bb5a534
--- /dev/null
+++ b/arch/arm/boot/dts/dove-d3plug.dts
@@ -0,0 +1,103 @@
1/dts-v1/;
2
3#include "dove.dtsi"
4
5/ {
6 model = "Globalscale D3Plug";
7 compatible = "globalscale,d3plug", "marvell,dove";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x40000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait";
16 };
17
18 leds {
19 compatible = "gpio-leds";
20 pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
21 pinctrl-names = "default";
22
23 wlan-act {
24 label = "wlan-act";
25 gpios = <&gpio0 0 1>;
26 };
27
28 wlan-ap {
29 label = "wlan-ap";
30 gpios = <&gpio0 1 1>;
31 };
32
33 status {
34 label = "status";
35 gpios = <&gpio0 2 1>;
36 };
37 };
38
39 regulators {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 usb_power: regulator@1 {
45 compatible = "regulator-fixed";
46 reg = <1>;
47 regulator-name = "USB Power";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 enable-active-high;
51 regulator-always-on;
52 regulator-boot-on;
53 gpio = <&gpio0 8 0>;
54 pinctrl-0 = <&pmx_gpio_8>;
55 pinctrl-names = "default";
56 };
57 };
58};
59
60&uart0 { status = "okay"; };
61&sata0 { status = "okay"; };
62&i2c0 { status = "okay"; };
63
64/* Samsung M8G2F eMMC */
65&sdio0 {
66 status = "okay";
67 non-removable;
68 bus-width = <4>;
69};
70
71/* Marvell SD8787 WLAN/BT */
72&sdio1 {
73 status = "okay";
74 non-removable;
75};
76
77&spi0 {
78 status = "okay";
79
80 /* spi0.0: 2M Flash Macronix MX25L1605D */
81 spi-flash@0 {
82 compatible = "st,m25l1605d";
83 spi-max-frequency = <86000000>;
84 reg = <0>;
85 };
86};
87
88&pcie {
89 status = "okay";
90 /* Fresco Logic USB3.0 xHCI controller */
91 pcie-port@0 {
92 status = "okay";
93 reset-gpios = <&gpio0 26 1>;
94 reset-delay-us = <20000>;
95 pinctrl-0 = <&pmx_camera_gpio>;
96 pinctrl-names = "default";
97 };
98 /* Mini-PCIe slot */
99 pcie-port@1 {
100 status = "okay";
101 reset-gpios = <&gpio0 25 1>;
102 };
103};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
index e5a920beab45..bb725dca3a10 100644
--- a/arch/arm/boot/dts/dove-dove-db.dts
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "dove.dtsi" 3#include "dove.dtsi"
4 4
5/ { 5/ {
6 model = "Marvell DB-MV88AP510-BP Development Board"; 6 model = "Marvell DB-MV88AP510-BP Development Board";
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index cc279166646f..113a8bc7bee7 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -1,8 +1,11 @@
1/include/ "skeleton.dtsi" 1/include/ "skeleton.dtsi"
2 2
3#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
4
3/ { 5/ {
4 compatible = "marvell,dove"; 6 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC"; 7 model = "Marvell Armada 88AP510 SoC";
8 interrupt-parent = <&intc>;
6 9
7 aliases { 10 aliases {
8 gpio0 = &gpio0; 11 gpio0 = &gpio0;
@@ -27,482 +30,576 @@
27 marvell,tauros2-cache-features = <0>; 30 marvell,tauros2-cache-features = <0>;
28 }; 31 };
29 32
30 soc@f1000000 { 33 mbus {
31 compatible = "simple-bus"; 34 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
32 #address-cells = <1>; 35 #address-cells = <2>;
33 #size-cells = <1>; 36 #size-cells = <1>;
34 interrupt-parent = <&intc>; 37 controller = <&mbusc>;
35 38 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
36 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */ 39 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
37 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */ 40
38 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */ 41 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
39 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */ 42 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
40 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */ 43 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
41 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */ 44 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
42 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ 45 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
43 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ 46
44 47 pcie: pcie-controller {
45 timer: timer@20300 { 48 compatible = "marvell,dove-pcie";
46 compatible = "marvell,orion-timer";
47 reg = <0x20300 0x20>;
48 interrupt-parent = <&bridge_intc>;
49 interrupts = <1>, <2>;
50 clocks = <&core_clk 0>;
51 };
52
53 intc: main-interrupt-ctrl@20200 {
54 compatible = "marvell,orion-intc";
55 interrupt-controller;
56 #interrupt-cells = <1>;
57 reg = <0x20200 0x10>, <0x20210 0x10>;
58 };
59
60 bridge_intc: bridge-interrupt-ctrl@20110 {
61 compatible = "marvell,orion-bridge-intc";
62 interrupt-controller;
63 #interrupt-cells = <1>;
64 reg = <0x20110 0x8>;
65 interrupts = <0>;
66 marvell,#interrupts = <5>;
67 };
68
69 core_clk: core-clocks@d0214 {
70 compatible = "marvell,dove-core-clock";
71 reg = <0xd0214 0x4>;
72 #clock-cells = <1>;
73 };
74
75 gate_clk: clock-gating-ctrl@d0038 {
76 compatible = "marvell,dove-gating-clock";
77 reg = <0xd0038 0x4>;
78 clocks = <&core_clk 0>;
79 #clock-cells = <1>;
80 };
81
82 thermal: thermal-diode@d001c {
83 compatible = "marvell,dove-thermal";
84 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
85 };
86
87 uart0: serial@12000 {
88 compatible = "ns16550a";
89 reg = <0x12000 0x100>;
90 reg-shift = <2>;
91 interrupts = <7>;
92 clocks = <&core_clk 0>;
93 status = "disabled";
94 };
95
96 uart1: serial@12100 {
97 compatible = "ns16550a";
98 reg = <0x12100 0x100>;
99 reg-shift = <2>;
100 interrupts = <8>;
101 clocks = <&core_clk 0>;
102 pinctrl-0 = <&pmx_uart1>;
103 pinctrl-names = "default";
104 status = "disabled";
105 };
106
107 uart2: serial@12200 {
108 compatible = "ns16550a";
109 reg = <0x12000 0x100>;
110 reg-shift = <2>;
111 interrupts = <9>;
112 clocks = <&core_clk 0>;
113 status = "disabled"; 49 status = "disabled";
114 }; 50 device_type = "pci";
115 51 #address-cells = <3>;
116 uart3: serial@12300 { 52 #size-cells = <2>;
117 compatible = "ns16550a"; 53
118 reg = <0x12100 0x100>; 54 msi-parent = <&intc>;
119 reg-shift = <2>; 55 bus-range = <0x00 0xff>;
120 interrupts = <10>; 56
121 clocks = <&core_clk 0>; 57 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
122 status = "disabled"; 58 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
123 }; 59 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
124 60 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
125 gpio0: gpio-ctrl@d0400 { 61 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
126 compatible = "marvell,orion-gpio"; 62 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
127 #gpio-cells = <2>; 63
128 gpio-controller; 64 pcie-port@0 {
129 reg = <0xd0400 0x20>; 65 device_type = "pci";
130 ngpios = <32>; 66 status = "disabled";
131 interrupt-controller; 67 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
132 #interrupt-cells = <2>; 68 reg = <0x0800 0 0 0 0>;
133 interrupts = <12>, <13>, <14>, <60>; 69 clocks = <&gate_clk 4>;
134 }; 70 marvell,pcie-port = <0>;
135 71
136 gpio1: gpio-ctrl@d0420 { 72 #address-cells = <3>;
137 compatible = "marvell,orion-gpio"; 73 #size-cells = <2>;
138 #gpio-cells = <2>; 74 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
139 gpio-controller; 75 0x81000000 0 0 0x81000000 0x1 0 1 0>;
140 reg = <0xd0420 0x20>; 76
141 ngpios = <32>; 77 #interrupt-cells = <1>;
142 interrupt-controller; 78 interrupt-map-mask = <0 0 0 0>;
143 #interrupt-cells = <2>; 79 interrupt-map = <0 0 0 0 &intc 16>;
144 interrupts = <61>; 80 };
145 }; 81
146 82 pcie-port@1 {
147 gpio2: gpio-ctrl@e8400 { 83 device_type = "pci";
148 compatible = "marvell,orion-gpio"; 84 status = "disabled";
149 #gpio-cells = <2>; 85 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
150 gpio-controller; 86 reg = <0x1000 0 0 0 0>;
151 reg = <0xe8400 0x0c>; 87 clocks = <&gate_clk 5>;
152 ngpios = <8>; 88 marvell,pcie-port = <1>;
153 }; 89
154 90 #address-cells = <3>;
155 pinctrl: pin-ctrl@d0200 { 91 #size-cells = <2>;
156 compatible = "marvell,dove-pinctrl"; 92 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
157 reg = <0xd0200 0x10>; 93 0x81000000 0 0 0x81000000 0x2 0 1 0>;
158 clocks = <&gate_clk 22>; 94
159 95 #interrupt-cells = <1>;
160 pmx_gpio_0: pmx-gpio-0 { 96 interrupt-map-mask = <0 0 0 0>;
161 marvell,pins = "mpp0"; 97 interrupt-map = <0 0 0 0 &intc 18>;
162 marvell,function = "gpio";
163 };
164
165 pmx_gpio_1: pmx-gpio-1 {
166 marvell,pins = "mpp1";
167 marvell,function = "gpio";
168 };
169
170 pmx_gpio_2: pmx-gpio-2 {
171 marvell,pins = "mpp2";
172 marvell,function = "gpio";
173 };
174
175 pmx_gpio_3: pmx-gpio-3 {
176 marvell,pins = "mpp3";
177 marvell,function = "gpio";
178 }; 98 };
179
180 pmx_gpio_4: pmx-gpio-4 {
181 marvell,pins = "mpp4";
182 marvell,function = "gpio";
183 };
184
185 pmx_gpio_5: pmx-gpio-5 {
186 marvell,pins = "mpp5";
187 marvell,function = "gpio";
188 };
189
190 pmx_gpio_6: pmx-gpio-6 {
191 marvell,pins = "mpp6";
192 marvell,function = "gpio";
193 };
194
195 pmx_gpio_7: pmx-gpio-7 {
196 marvell,pins = "mpp7";
197 marvell,function = "gpio";
198 };
199
200 pmx_gpio_8: pmx-gpio-8 {
201 marvell,pins = "mpp8";
202 marvell,function = "gpio";
203 };
204
205 pmx_gpio_9: pmx-gpio-9 {
206 marvell,pins = "mpp9";
207 marvell,function = "gpio";
208 };
209
210 pmx_gpio_10: pmx-gpio-10 {
211 marvell,pins = "mpp10";
212 marvell,function = "gpio";
213 };
214
215 pmx_gpio_11: pmx-gpio-11 {
216 marvell,pins = "mpp11";
217 marvell,function = "gpio";
218 };
219
220 pmx_gpio_12: pmx-gpio-12 {
221 marvell,pins = "mpp12";
222 marvell,function = "gpio";
223 };
224
225 pmx_gpio_13: pmx-gpio-13 {
226 marvell,pins = "mpp13";
227 marvell,function = "gpio";
228 };
229
230 pmx_gpio_14: pmx-gpio-14 {
231 marvell,pins = "mpp14";
232 marvell,function = "gpio";
233 };
234
235 pmx_gpio_15: pmx-gpio-15 {
236 marvell,pins = "mpp15";
237 marvell,function = "gpio";
238 };
239
240 pmx_gpio_16: pmx-gpio-16 {
241 marvell,pins = "mpp16";
242 marvell,function = "gpio";
243 };
244
245 pmx_gpio_17: pmx-gpio-17 {
246 marvell,pins = "mpp17";
247 marvell,function = "gpio";
248 };
249
250 pmx_gpio_18: pmx-gpio-18 {
251 marvell,pins = "mpp18";
252 marvell,function = "gpio";
253 };
254
255 pmx_gpio_19: pmx-gpio-19 {
256 marvell,pins = "mpp19";
257 marvell,function = "gpio";
258 };
259
260 pmx_gpio_20: pmx-gpio-20 {
261 marvell,pins = "mpp20";
262 marvell,function = "gpio";
263 };
264
265 pmx_gpio_21: pmx-gpio-21 {
266 marvell,pins = "mpp21";
267 marvell,function = "gpio";
268 };
269
270 pmx_camera: pmx-camera {
271 marvell,pins = "mpp_camera";
272 marvell,function = "camera";
273 };
274
275 pmx_camera_gpio: pmx-camera-gpio {
276 marvell,pins = "mpp_camera";
277 marvell,function = "gpio";
278 };
279
280 pmx_sdio0: pmx-sdio0 {
281 marvell,pins = "mpp_sdio0";
282 marvell,function = "sdio0";
283 };
284
285 pmx_sdio0_gpio: pmx-sdio0-gpio {
286 marvell,pins = "mpp_sdio0";
287 marvell,function = "gpio";
288 };
289
290 pmx_sdio1: pmx-sdio1 {
291 marvell,pins = "mpp_sdio1";
292 marvell,function = "sdio1";
293 };
294
295 pmx_sdio1_gpio: pmx-sdio1-gpio {
296 marvell,pins = "mpp_sdio1";
297 marvell,function = "gpio";
298 };
299
300 pmx_audio1_gpio: pmx-audio1-gpio {
301 marvell,pins = "mpp_audio1";
302 marvell,function = "gpio";
303 };
304
305 pmx_spi0: pmx-spi0 {
306 marvell,pins = "mpp_spi0";
307 marvell,function = "spi0";
308 };
309
310 pmx_spi0_gpio: pmx-spi0-gpio {
311 marvell,pins = "mpp_spi0";
312 marvell,function = "gpio";
313 };
314
315 pmx_uart1: pmx-uart1 {
316 marvell,pins = "mpp_uart1";
317 marvell,function = "uart1";
318 };
319
320 pmx_uart1_gpio: pmx-uart1-gpio {
321 marvell,pins = "mpp_uart1";
322 marvell,function = "gpio";
323 };
324
325 pmx_nand: pmx-nand {
326 marvell,pins = "mpp_nand";
327 marvell,function = "nand";
328 };
329
330 pmx_nand_gpo: pmx-nand-gpo {
331 marvell,pins = "mpp_nand";
332 marvell,function = "gpo";
333 };
334 };
335
336 spi0: spi-ctrl@10600 {
337 compatible = "marvell,orion-spi";
338 #address-cells = <1>;
339 #size-cells = <0>;
340 cell-index = <0>;
341 interrupts = <6>;
342 reg = <0x10600 0x28>;
343 clocks = <&core_clk 0>;
344 pinctrl-0 = <&pmx_spi0>;
345 pinctrl-names = "default";
346 status = "disabled";
347 };
348
349 spi1: spi-ctrl@14600 {
350 compatible = "marvell,orion-spi";
351 #address-cells = <1>;
352 #size-cells = <0>;
353 cell-index = <1>;
354 interrupts = <5>;
355 reg = <0x14600 0x28>;
356 clocks = <&core_clk 0>;
357 status = "disabled";
358 };
359
360 i2c0: i2c-ctrl@11000 {
361 compatible = "marvell,mv64xxx-i2c";
362 reg = <0x11000 0x20>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 interrupts = <11>;
366 clock-frequency = <400000>;
367 timeout-ms = <1000>;
368 clocks = <&core_clk 0>;
369 status = "disabled";
370 }; 99 };
371 100
372 ehci0: usb-host@50000 { 101 internal-regs {
373 compatible = "marvell,orion-ehci"; 102 compatible = "simple-bus";
374 reg = <0x50000 0x1000>;
375 interrupts = <24>;
376 clocks = <&gate_clk 0>;
377 status = "okay";
378 };
379
380 ehci1: usb-host@51000 {
381 compatible = "marvell,orion-ehci";
382 reg = <0x51000 0x1000>;
383 interrupts = <25>;
384 clocks = <&gate_clk 1>;
385 status = "okay";
386 };
387
388 sdio0: sdio-host@92000 {
389 compatible = "marvell,dove-sdhci";
390 reg = <0x92000 0x100>;
391 interrupts = <35>, <37>;
392 clocks = <&gate_clk 8>;
393 pinctrl-0 = <&pmx_sdio0>;
394 pinctrl-names = "default";
395 status = "disabled";
396 };
397
398 sdio1: sdio-host@90000 {
399 compatible = "marvell,dove-sdhci";
400 reg = <0x90000 0x100>;
401 interrupts = <36>, <38>;
402 clocks = <&gate_clk 9>;
403 pinctrl-0 = <&pmx_sdio1>;
404 pinctrl-names = "default";
405 status = "disabled";
406 };
407
408 sata0: sata-host@a0000 {
409 compatible = "marvell,orion-sata";
410 reg = <0xa0000 0x2400>;
411 interrupts = <62>;
412 clocks = <&gate_clk 3>;
413 nr-ports = <1>;
414 status = "disabled";
415 };
416
417 rtc: real-time-clock@d8500 {
418 compatible = "marvell,orion-rtc";
419 reg = <0xd8500 0x20>;
420 };
421
422 crypto: crypto-engine@30000 {
423 compatible = "marvell,orion-crypto";
424 reg = <0x30000 0x10000>,
425 <0xc8000000 0x800>;
426 reg-names = "regs", "sram";
427 interrupts = <31>;
428 clocks = <&gate_clk 15>;
429 status = "okay";
430 };
431
432 xor0: dma-engine@60800 {
433 compatible = "marvell,orion-xor";
434 reg = <0x60800 0x100
435 0x60a00 0x100>;
436 clocks = <&gate_clk 23>;
437 status = "okay";
438
439 channel0 {
440 interrupts = <39>;
441 dmacap,memcpy;
442 dmacap,xor;
443 };
444
445 channel1 {
446 interrupts = <40>;
447 dmacap,memset;
448 dmacap,memcpy;
449 dmacap,xor;
450 };
451 };
452
453 xor1: dma-engine@60900 {
454 compatible = "marvell,orion-xor";
455 reg = <0x60900 0x100
456 0x60b00 0x100>;
457 clocks = <&gate_clk 24>;
458 status = "okay";
459
460 channel0 {
461 interrupts = <42>;
462 dmacap,memcpy;
463 dmacap,xor;
464 };
465
466 channel1 {
467 interrupts = <43>;
468 dmacap,memset;
469 dmacap,memcpy;
470 dmacap,xor;
471 };
472 };
473
474 mdio: mdio-bus@72004 {
475 compatible = "marvell,orion-mdio";
476 #address-cells = <1>; 103 #address-cells = <1>;
477 #size-cells = <0>; 104 #size-cells = <1>;
478 reg = <0x72004 0x84>; 105 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
479 interrupts = <30>; 106 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
480 clocks = <&gate_clk 2>; 107 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
481 status = "disabled"; 108 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
482 109
483 ethphy: ethernet-phy { 110 mbusc: mbus-ctrl@20000 {
484 device-type = "ethernet-phy"; 111 compatible = "marvell,mbus-controller";
485 /* set phy address in board file */ 112 reg = <0x20000 0x80>, <0x800100 0x8>;
486 }; 113 };
487 }; 114
488 115 timer: timer@20300 {
489 eth: ethernet-controller@72000 { 116 compatible = "marvell,orion-timer";
490 compatible = "marvell,orion-eth"; 117 reg = <0x20300 0x20>;
491 #address-cells = <1>; 118 interrupt-parent = <&bridge_intc>;
492 #size-cells = <0>; 119 interrupts = <1>, <2>;
493 reg = <0x72000 0x4000>; 120 clocks = <&core_clk 0>;
494 clocks = <&gate_clk 2>; 121 };
495 marvell,tx-checksum-limit = <1600>; 122
496 status = "disabled"; 123 intc: main-interrupt-ctrl@20200 {
497 124 compatible = "marvell,orion-intc";
498 ethernet-port@0 { 125 interrupt-controller;
499 device_type = "network"; 126 #interrupt-cells = <1>;
500 compatible = "marvell,orion-eth-port"; 127 reg = <0x20200 0x10>, <0x20210 0x10>;
501 reg = <0>; 128 };
502 interrupts = <29>; 129
503 /* overwrite MAC address in bootloader */ 130 bridge_intc: bridge-interrupt-ctrl@20110 {
504 local-mac-address = [00 00 00 00 00 00]; 131 compatible = "marvell,orion-bridge-intc";
505 phy-handle = <&ethphy>; 132 interrupt-controller;
133 #interrupt-cells = <1>;
134 reg = <0x20110 0x8>;
135 interrupts = <0>;
136 marvell,#interrupts = <5>;
137 };
138
139 core_clk: core-clocks@d0214 {
140 compatible = "marvell,dove-core-clock";
141 reg = <0xd0214 0x4>;
142 #clock-cells = <1>;
143 };
144
145 gate_clk: clock-gating-ctrl@d0038 {
146 compatible = "marvell,dove-gating-clock";
147 reg = <0xd0038 0x4>;
148 clocks = <&core_clk 0>;
149 #clock-cells = <1>;
150 };
151
152 thermal: thermal-diode@d001c {
153 compatible = "marvell,dove-thermal";
154 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
155 };
156
157 uart0: serial@12000 {
158 compatible = "ns16550a";
159 reg = <0x12000 0x100>;
160 reg-shift = <2>;
161 interrupts = <7>;
162 clocks = <&core_clk 0>;
163 status = "disabled";
164 };
165
166 uart1: serial@12100 {
167 compatible = "ns16550a";
168 reg = <0x12100 0x100>;
169 reg-shift = <2>;
170 interrupts = <8>;
171 clocks = <&core_clk 0>;
172 pinctrl-0 = <&pmx_uart1>;
173 pinctrl-names = "default";
174 status = "disabled";
175 };
176
177 uart2: serial@12200 {
178 compatible = "ns16550a";
179 reg = <0x12000 0x100>;
180 reg-shift = <2>;
181 interrupts = <9>;
182 clocks = <&core_clk 0>;
183 status = "disabled";
184 };
185
186 uart3: serial@12300 {
187 compatible = "ns16550a";
188 reg = <0x12100 0x100>;
189 reg-shift = <2>;
190 interrupts = <10>;
191 clocks = <&core_clk 0>;
192 status = "disabled";
193 };
194
195 gpio0: gpio-ctrl@d0400 {
196 compatible = "marvell,orion-gpio";
197 #gpio-cells = <2>;
198 gpio-controller;
199 reg = <0xd0400 0x20>;
200 ngpios = <32>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 interrupts = <12>, <13>, <14>, <60>;
204 };
205
206 gpio1: gpio-ctrl@d0420 {
207 compatible = "marvell,orion-gpio";
208 #gpio-cells = <2>;
209 gpio-controller;
210 reg = <0xd0420 0x20>;
211 ngpios = <32>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 interrupts = <61>;
215 };
216
217 gpio2: gpio-ctrl@e8400 {
218 compatible = "marvell,orion-gpio";
219 #gpio-cells = <2>;
220 gpio-controller;
221 reg = <0xe8400 0x0c>;
222 ngpios = <8>;
223 };
224
225 pinctrl: pin-ctrl@d0200 {
226 compatible = "marvell,dove-pinctrl";
227 reg = <0xd0200 0x10>;
228 clocks = <&gate_clk 22>;
229
230 pmx_gpio_0: pmx-gpio-0 {
231 marvell,pins = "mpp0";
232 marvell,function = "gpio";
233 };
234
235 pmx_gpio_1: pmx-gpio-1 {
236 marvell,pins = "mpp1";
237 marvell,function = "gpio";
238 };
239
240 pmx_gpio_2: pmx-gpio-2 {
241 marvell,pins = "mpp2";
242 marvell,function = "gpio";
243 };
244
245 pmx_gpio_3: pmx-gpio-3 {
246 marvell,pins = "mpp3";
247 marvell,function = "gpio";
248 };
249
250 pmx_gpio_4: pmx-gpio-4 {
251 marvell,pins = "mpp4";
252 marvell,function = "gpio";
253 };
254
255 pmx_gpio_5: pmx-gpio-5 {
256 marvell,pins = "mpp5";
257 marvell,function = "gpio";
258 };
259
260 pmx_gpio_6: pmx-gpio-6 {
261 marvell,pins = "mpp6";
262 marvell,function = "gpio";
263 };
264
265 pmx_gpio_7: pmx-gpio-7 {
266 marvell,pins = "mpp7";
267 marvell,function = "gpio";
268 };
269
270 pmx_gpio_8: pmx-gpio-8 {
271 marvell,pins = "mpp8";
272 marvell,function = "gpio";
273 };
274
275 pmx_gpio_9: pmx-gpio-9 {
276 marvell,pins = "mpp9";
277 marvell,function = "gpio";
278 };
279
280 pmx_gpio_10: pmx-gpio-10 {
281 marvell,pins = "mpp10";
282 marvell,function = "gpio";
283 };
284
285 pmx_gpio_11: pmx-gpio-11 {
286 marvell,pins = "mpp11";
287 marvell,function = "gpio";
288 };
289
290 pmx_gpio_12: pmx-gpio-12 {
291 marvell,pins = "mpp12";
292 marvell,function = "gpio";
293 };
294
295 pmx_gpio_13: pmx-gpio-13 {
296 marvell,pins = "mpp13";
297 marvell,function = "gpio";
298 };
299
300 pmx_audio1_extclk: pmx-audio1-extclk {
301 marvell,pins = "mpp13";
302 marvell,function = "audio1";
303 };
304
305 pmx_gpio_14: pmx-gpio-14 {
306 marvell,pins = "mpp14";
307 marvell,function = "gpio";
308 };
309
310 pmx_gpio_15: pmx-gpio-15 {
311 marvell,pins = "mpp15";
312 marvell,function = "gpio";
313 };
314
315 pmx_gpio_16: pmx-gpio-16 {
316 marvell,pins = "mpp16";
317 marvell,function = "gpio";
318 };
319
320 pmx_gpio_17: pmx-gpio-17 {
321 marvell,pins = "mpp17";
322 marvell,function = "gpio";
323 };
324
325 pmx_gpio_18: pmx-gpio-18 {
326 marvell,pins = "mpp18";
327 marvell,function = "gpio";
328 };
329
330 pmx_gpio_19: pmx-gpio-19 {
331 marvell,pins = "mpp19";
332 marvell,function = "gpio";
333 };
334
335 pmx_gpio_20: pmx-gpio-20 {
336 marvell,pins = "mpp20";
337 marvell,function = "gpio";
338 };
339
340 pmx_gpio_21: pmx-gpio-21 {
341 marvell,pins = "mpp21";
342 marvell,function = "gpio";
343 };
344
345 pmx_camera: pmx-camera {
346 marvell,pins = "mpp_camera";
347 marvell,function = "camera";
348 };
349
350 pmx_camera_gpio: pmx-camera-gpio {
351 marvell,pins = "mpp_camera";
352 marvell,function = "gpio";
353 };
354
355 pmx_sdio0: pmx-sdio0 {
356 marvell,pins = "mpp_sdio0";
357 marvell,function = "sdio0";
358 };
359
360 pmx_sdio0_gpio: pmx-sdio0-gpio {
361 marvell,pins = "mpp_sdio0";
362 marvell,function = "gpio";
363 };
364
365 pmx_sdio1: pmx-sdio1 {
366 marvell,pins = "mpp_sdio1";
367 marvell,function = "sdio1";
368 };
369
370 pmx_sdio1_gpio: pmx-sdio1-gpio {
371 marvell,pins = "mpp_sdio1";
372 marvell,function = "gpio";
373 };
374
375 pmx_audio1_gpio: pmx-audio1-gpio {
376 marvell,pins = "mpp_audio1";
377 marvell,function = "gpio";
378 };
379
380 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
381 marvell,pins = "mpp_audio1";
382 marvell,function = "i2s1/spdifo";
383 };
384
385 pmx_spi0: pmx-spi0 {
386 marvell,pins = "mpp_spi0";
387 marvell,function = "spi0";
388 };
389
390 pmx_spi0_gpio: pmx-spi0-gpio {
391 marvell,pins = "mpp_spi0";
392 marvell,function = "gpio";
393 };
394
395 pmx_uart1: pmx-uart1 {
396 marvell,pins = "mpp_uart1";
397 marvell,function = "uart1";
398 };
399
400 pmx_uart1_gpio: pmx-uart1-gpio {
401 marvell,pins = "mpp_uart1";
402 marvell,function = "gpio";
403 };
404
405 pmx_nand: pmx-nand {
406 marvell,pins = "mpp_nand";
407 marvell,function = "nand";
408 };
409
410 pmx_nand_gpo: pmx-nand-gpo {
411 marvell,pins = "mpp_nand";
412 marvell,function = "gpo";
413 };
414 };
415
416 spi0: spi-ctrl@10600 {
417 compatible = "marvell,orion-spi";
418 #address-cells = <1>;
419 #size-cells = <0>;
420 cell-index = <0>;
421 interrupts = <6>;
422 reg = <0x10600 0x28>;
423 clocks = <&core_clk 0>;
424 pinctrl-0 = <&pmx_spi0>;
425 pinctrl-names = "default";
426 status = "disabled";
427 };
428
429 spi1: spi-ctrl@14600 {
430 compatible = "marvell,orion-spi";
431 #address-cells = <1>;
432 #size-cells = <0>;
433 cell-index = <1>;
434 interrupts = <5>;
435 reg = <0x14600 0x28>;
436 clocks = <&core_clk 0>;
437 status = "disabled";
438 };
439
440 i2c0: i2c-ctrl@11000 {
441 compatible = "marvell,mv64xxx-i2c";
442 reg = <0x11000 0x20>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 interrupts = <11>;
446 clock-frequency = <400000>;
447 timeout-ms = <1000>;
448 clocks = <&core_clk 0>;
449 status = "disabled";
450 };
451
452 ehci0: usb-host@50000 {
453 compatible = "marvell,orion-ehci";
454 reg = <0x50000 0x1000>;
455 interrupts = <24>;
456 clocks = <&gate_clk 0>;
457 status = "okay";
458 };
459
460 ehci1: usb-host@51000 {
461 compatible = "marvell,orion-ehci";
462 reg = <0x51000 0x1000>;
463 interrupts = <25>;
464 clocks = <&gate_clk 1>;
465 status = "okay";
466 };
467
468 sdio0: sdio-host@92000 {
469 compatible = "marvell,dove-sdhci";
470 reg = <0x92000 0x100>;
471 interrupts = <35>, <37>;
472 clocks = <&gate_clk 8>;
473 pinctrl-0 = <&pmx_sdio0>;
474 pinctrl-names = "default";
475 status = "disabled";
476 };
477
478 sdio1: sdio-host@90000 {
479 compatible = "marvell,dove-sdhci";
480 reg = <0x90000 0x100>;
481 interrupts = <36>, <38>;
482 clocks = <&gate_clk 9>;
483 pinctrl-0 = <&pmx_sdio1>;
484 pinctrl-names = "default";
485 status = "disabled";
486 };
487
488 sata0: sata-host@a0000 {
489 compatible = "marvell,orion-sata";
490 reg = <0xa0000 0x2400>;
491 interrupts = <62>;
492 clocks = <&gate_clk 3>;
493 nr-ports = <1>;
494 status = "disabled";
495 };
496
497 rtc: real-time-clock@d8500 {
498 compatible = "marvell,orion-rtc";
499 reg = <0xd8500 0x20>;
500 };
501
502 crypto: crypto-engine@30000 {
503 compatible = "marvell,orion-crypto";
504 reg = <0x30000 0x10000>,
505 <0xffffe000 0x800>;
506 reg-names = "regs", "sram";
507 interrupts = <31>;
508 clocks = <&gate_clk 15>;
509 status = "okay";
510 };
511
512 xor0: dma-engine@60800 {
513 compatible = "marvell,orion-xor";
514 reg = <0x60800 0x100
515 0x60a00 0x100>;
516 clocks = <&gate_clk 23>;
517 status = "okay";
518
519 channel0 {
520 interrupts = <39>;
521 dmacap,memcpy;
522 dmacap,xor;
523 };
524
525 channel1 {
526 interrupts = <40>;
527 dmacap,memcpy;
528 dmacap,xor;
529 };
530 };
531
532 xor1: dma-engine@60900 {
533 compatible = "marvell,orion-xor";
534 reg = <0x60900 0x100
535 0x60b00 0x100>;
536 clocks = <&gate_clk 24>;
537 status = "okay";
538
539 channel0 {
540 interrupts = <42>;
541 dmacap,memcpy;
542 dmacap,xor;
543 };
544
545 channel1 {
546 interrupts = <43>;
547 dmacap,memcpy;
548 dmacap,xor;
549 };
550 };
551
552 mdio: mdio-bus@72004 {
553 compatible = "marvell,orion-mdio";
554 #address-cells = <1>;
555 #size-cells = <0>;
556 reg = <0x72004 0x84>;
557 interrupts = <30>;
558 clocks = <&gate_clk 2>;
559 status = "disabled";
560
561 ethphy: ethernet-phy {
562 device-type = "ethernet-phy";
563 /* set phy address in board file */
564 };
565 };
566
567 eth: ethernet-ctrl@72000 {
568 compatible = "marvell,orion-eth";
569 #address-cells = <1>;
570 #size-cells = <0>;
571 reg = <0x72000 0x4000>;
572 clocks = <&gate_clk 2>;
573 marvell,tx-checksum-limit = <1600>;
574 status = "disabled";
575
576 ethernet-port@0 {
577 device_type = "network";
578 compatible = "marvell,orion-eth-port";
579 reg = <0>;
580 interrupts = <29>;
581 /* overwrite MAC address in bootloader */
582 local-mac-address = [00 00 00 00 00 00];
583 phy-handle = <&ethphy>;
584 };
585 };
586
587 audio0: audio-controller@b0000 {
588 compatible = "marvell,dove-audio";
589 reg = <0xb0000 0x2210>;
590 interrupts = <19>, <20>;
591 clocks = <&gate_clk 12>;
592 clock-names = "internal";
593 status = "disabled";
594 };
595
596 audio1: audio-controller@b4000 {
597 compatible = "marvell,dove-audio";
598 reg = <0xb4000 0x2210>;
599 interrupts = <21>, <22>;
600 clocks = <&gate_clk 13>;
601 clock-names = "internal";
602 status = "disabled";
506 }; 603 };
507 }; 604 };
508 }; 605 };
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
new file mode 100644
index 000000000000..5babba0a3a75
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -0,0 +1,275 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra7.dtsi"
11
12/ {
13 model = "TI DRA7";
14 compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x60000000>; /* 1536 MB */
19 };
20
21 mmc2_3v3: fixedregulator-mmc2 {
22 compatible = "regulator-fixed";
23 regulator-name = "mmc2_3v3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 };
27};
28
29&dra7_pmx_core {
30 i2c1_pins: pinmux_i2c1_pins {
31 pinctrl-single,pins = <
32 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
33 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
34 >;
35 };
36
37 i2c2_pins: pinmux_i2c2_pins {
38 pinctrl-single,pins = <
39 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
40 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
41 >;
42 };
43
44 i2c3_pins: pinmux_i2c3_pins {
45 pinctrl-single,pins = <
46 0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
47 0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
48 >;
49 };
50
51 mcspi1_pins: pinmux_mcspi1_pins {
52 pinctrl-single,pins = <
53 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
54 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
55 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
56 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
57 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
58 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
59 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
60 >;
61 };
62
63 mcspi2_pins: pinmux_mcspi2_pins {
64 pinctrl-single,pins = <
65 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
66 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
67 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
68 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
69 >;
70 };
71
72 uart1_pins: pinmux_uart1_pins {
73 pinctrl-single,pins = <
74 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
75 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
76 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
77 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
78 >;
79 };
80
81 uart2_pins: pinmux_uart2_pins {
82 pinctrl-single,pins = <
83 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
84 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
85 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
86 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
87 >;
88 };
89
90 uart3_pins: pinmux_uart3_pins {
91 pinctrl-single,pins = <
92 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
93 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
94 >;
95 };
96};
97
98&i2c1 {
99 status = "okay";
100 pinctrl-names = "default";
101 pinctrl-0 = <&i2c1_pins>;
102 clock-frequency = <400000>;
103
104 tps659038: tps659038@58 {
105 compatible = "ti,tps659038";
106 reg = <0x58>;
107
108 tps659038_pmic {
109 compatible = "ti,tps659038-pmic";
110
111 regulators {
112 smps123_reg: smps123 {
113 /* VDD_MPU */
114 regulator-name = "smps123";
115 regulator-min-microvolt = < 850000>;
116 regulator-max-microvolt = <1250000>;
117 regulator-always-on;
118 regulator-boot-on;
119 };
120
121 smps45_reg: smps45 {
122 /* VDD_DSPEVE */
123 regulator-name = "smps45";
124 regulator-min-microvolt = < 850000>;
125 regulator-max-microvolt = <1150000>;
126 regulator-boot-on;
127 };
128
129 smps6_reg: smps6 {
130 /* VDD_GPU - over VDD_SMPS6 */
131 regulator-name = "smps6";
132 regulator-min-microvolt = <850000>;
133 regulator-max-microvolt = <12500000>;
134 regulator-boot-on;
135 };
136
137 smps7_reg: smps7 {
138 /* CORE_VDD */
139 regulator-name = "smps7";
140 regulator-min-microvolt = <850000>;
141 regulator-max-microvolt = <1030000>;
142 regulator-always-on;
143 regulator-boot-on;
144 };
145
146 smps8_reg: smps8 {
147 /* VDD_IVAHD */
148 regulator-name = "smps8";
149 regulator-min-microvolt = < 850000>;
150 regulator-max-microvolt = <1250000>;
151 regulator-boot-on;
152 };
153
154 smps9_reg: smps9 {
155 /* VDDS1V8 */
156 regulator-name = "smps9";
157 regulator-min-microvolt = <1800000>;
158 regulator-max-microvolt = <1800000>;
159 regulator-always-on;
160 regulator-boot-on;
161 };
162
163 ldo1_reg: ldo1 {
164 /* LDO1_OUT --> SDIO */
165 regulator-name = "ldo1";
166 regulator-min-microvolt = <1800000>;
167 regulator-max-microvolt = <3300000>;
168 regulator-boot-on;
169 };
170
171 ldo2_reg: ldo2 {
172 /* VDD_RTCIO */
173 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
174 regulator-name = "ldo2";
175 regulator-min-microvolt = <3300000>;
176 regulator-max-microvolt = <3300000>;
177 regulator-boot-on;
178 };
179
180 ldo3_reg: ldo3 {
181 /* VDDA_1V8_PHY */
182 regulator-name = "ldo3";
183 regulator-min-microvolt = <1800000>;
184 regulator-max-microvolt = <1800000>;
185 regulator-boot-on;
186 };
187
188 ldo9_reg: ldo9 {
189 /* VDD_RTC */
190 regulator-name = "ldo9";
191 regulator-min-microvolt = <1050000>;
192 regulator-max-microvolt = <1050000>;
193 regulator-boot-on;
194 };
195
196 ldoln_reg: ldoln {
197 /* VDDA_1V8_PLL */
198 regulator-name = "ldoln";
199 regulator-min-microvolt = <1800000>;
200 regulator-max-microvolt = <1800000>;
201 regulator-always-on;
202 regulator-boot-on;
203 };
204
205 ldousb_reg: ldousb {
206 /* VDDA_3V_USB: VDDA_USBHS33 */
207 regulator-name = "ldousb";
208 regulator-min-microvolt = <3300000>;
209 regulator-max-microvolt = <3300000>;
210 regulator-boot-on;
211 };
212 };
213 };
214 };
215};
216
217&i2c2 {
218 status = "okay";
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c2_pins>;
221 clock-frequency = <400000>;
222};
223
224&i2c3 {
225 status = "okay";
226 pinctrl-names = "default";
227 pinctrl-0 = <&i2c3_pins>;
228 clock-frequency = <3400000>;
229};
230
231&mcspi1 {
232 status = "okay";
233 pinctrl-names = "default";
234 pinctrl-0 = <&mcspi1_pins>;
235};
236
237&mcspi2 {
238 status = "okay";
239 pinctrl-names = "default";
240 pinctrl-0 = <&mcspi2_pins>;
241};
242
243&uart1 {
244 status = "okay";
245 pinctrl-names = "default";
246 pinctrl-0 = <&uart1_pins>;
247};
248
249&uart2 {
250 status = "okay";
251 pinctrl-names = "default";
252 pinctrl-0 = <&uart2_pins>;
253};
254
255&uart3 {
256 status = "okay";
257 pinctrl-names = "default";
258 pinctrl-0 = <&uart3_pins>;
259};
260
261&mmc1 {
262 status = "okay";
263 vmmc-supply = <&ldo1_reg>;
264 bus-width = <4>;
265};
266
267&mmc2 {
268 status = "okay";
269 vmmc-supply = <&mmc2_3v3>;
270 bus-width = <8>;
271};
272
273&cpu0 {
274 cpu0-supply = <&smps123_reg>;
275};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
new file mode 100644
index 000000000000..d0df4c4e8b0a
--- /dev/null
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -0,0 +1,586 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0>;
44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1176000 1160000
49 >;
50 };
51 cpu@1 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a15";
54 reg = <1>;
55 };
56 };
57
58 timer {
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
64 };
65
66 gic: interrupt-controller@48211000 {
67 compatible = "arm,cortex-a15-gic";
68 interrupt-controller;
69 #interrupt-cells = <3>;
70 reg = <0x48211000 0x1000>,
71 <0x48212000 0x1000>,
72 <0x48214000 0x2000>,
73 <0x48216000 0x2000>;
74 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
75 };
76
77 /*
78 * The soc node represents the soc top level view. It is uses for IPs
79 * that are not memory mapped in the MPU view or for the MPU itself.
80 */
81 soc {
82 compatible = "ti,omap-infra";
83 mpu {
84 compatible = "ti,omap5-mpu";
85 ti,hwmods = "mpu";
86 };
87 };
88
89 /*
90 * XXX: Use a flat representation of the SOC interconnect.
91 * The real OMAP interconnect network is quite complex.
92 * Since that will not bring real advantage to represent that in DT for
93 * the moment, just use a fake OCP bus entry to represent the whole bus
94 * hierarchy.
95 */
96 ocp {
97 compatible = "ti,omap4-l3-noc", "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges;
101 ti,hwmods = "l3_main_1", "l3_main_2";
102 reg = <0x44000000 0x2000>,
103 <0x44800000 0x3000>;
104 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
106
107 counter32k: counter@4ae04000 {
108 compatible = "ti,omap-counter32k";
109 reg = <0x4ae04000 0x40>;
110 ti,hwmods = "counter_32k";
111 };
112
113 dra7_pmx_core: pinmux@4a003400 {
114 compatible = "pinctrl-single";
115 reg = <0x4a003400 0x0464>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 pinctrl-single,register-width = <32>;
119 pinctrl-single,function-mask = <0x3fffffff>;
120 };
121
122 sdma: dma-controller@4a056000 {
123 compatible = "ti,omap4430-sdma";
124 reg = <0x4a056000 0x1000>;
125 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
129 #dma-cells = <1>;
130 #dma-channels = <32>;
131 #dma-requests = <127>;
132 };
133
134 gpio1: gpio@4ae10000 {
135 compatible = "ti,omap4-gpio";
136 reg = <0x4ae10000 0x200>;
137 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
138 ti,hwmods = "gpio1";
139 gpio-controller;
140 #gpio-cells = <2>;
141 interrupt-controller;
142 #interrupt-cells = <1>;
143 };
144
145 gpio2: gpio@48055000 {
146 compatible = "ti,omap4-gpio";
147 reg = <0x48055000 0x200>;
148 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
149 ti,hwmods = "gpio2";
150 gpio-controller;
151 #gpio-cells = <2>;
152 interrupt-controller;
153 #interrupt-cells = <1>;
154 };
155
156 gpio3: gpio@48057000 {
157 compatible = "ti,omap4-gpio";
158 reg = <0x48057000 0x200>;
159 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
160 ti,hwmods = "gpio3";
161 gpio-controller;
162 #gpio-cells = <2>;
163 interrupt-controller;
164 #interrupt-cells = <1>;
165 };
166
167 gpio4: gpio@48059000 {
168 compatible = "ti,omap4-gpio";
169 reg = <0x48059000 0x200>;
170 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
171 ti,hwmods = "gpio4";
172 gpio-controller;
173 #gpio-cells = <2>;
174 interrupt-controller;
175 #interrupt-cells = <1>;
176 };
177
178 gpio5: gpio@4805b000 {
179 compatible = "ti,omap4-gpio";
180 reg = <0x4805b000 0x200>;
181 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
182 ti,hwmods = "gpio5";
183 gpio-controller;
184 #gpio-cells = <2>;
185 interrupt-controller;
186 #interrupt-cells = <1>;
187 };
188
189 gpio6: gpio@4805d000 {
190 compatible = "ti,omap4-gpio";
191 reg = <0x4805d000 0x200>;
192 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "gpio6";
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
197 #interrupt-cells = <1>;
198 };
199
200 gpio7: gpio@48051000 {
201 compatible = "ti,omap4-gpio";
202 reg = <0x48051000 0x200>;
203 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
204 ti,hwmods = "gpio7";
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <1>;
209 };
210
211 gpio8: gpio@48053000 {
212 compatible = "ti,omap4-gpio";
213 reg = <0x48053000 0x200>;
214 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
215 ti,hwmods = "gpio8";
216 gpio-controller;
217 #gpio-cells = <2>;
218 interrupt-controller;
219 #interrupt-cells = <1>;
220 };
221
222 uart1: serial@4806a000 {
223 compatible = "ti,omap4-uart";
224 reg = <0x4806a000 0x100>;
225 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
226 ti,hwmods = "uart1";
227 clock-frequency = <48000000>;
228 status = "disabled";
229 };
230
231 uart2: serial@4806c000 {
232 compatible = "ti,omap4-uart";
233 reg = <0x4806c000 0x100>;
234 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
235 ti,hwmods = "uart2";
236 clock-frequency = <48000000>;
237 status = "disabled";
238 };
239
240 uart3: serial@48020000 {
241 compatible = "ti,omap4-uart";
242 reg = <0x48020000 0x100>;
243 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
244 ti,hwmods = "uart3";
245 clock-frequency = <48000000>;
246 status = "disabled";
247 };
248
249 uart4: serial@4806e000 {
250 compatible = "ti,omap4-uart";
251 reg = <0x4806e000 0x100>;
252 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
253 ti,hwmods = "uart4";
254 clock-frequency = <48000000>;
255 status = "disabled";
256 };
257
258 uart5: serial@48066000 {
259 compatible = "ti,omap4-uart";
260 reg = <0x48066000 0x100>;
261 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
262 ti,hwmods = "uart5";
263 clock-frequency = <48000000>;
264 status = "disabled";
265 };
266
267 uart6: serial@48068000 {
268 compatible = "ti,omap4-uart";
269 reg = <0x48068000 0x100>;
270 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
271 ti,hwmods = "uart6";
272 clock-frequency = <48000000>;
273 status = "disabled";
274 };
275
276 uart7: serial@48420000 {
277 compatible = "ti,omap4-uart";
278 reg = <0x48420000 0x100>;
279 ti,hwmods = "uart7";
280 clock-frequency = <48000000>;
281 status = "disabled";
282 };
283
284 uart8: serial@48422000 {
285 compatible = "ti,omap4-uart";
286 reg = <0x48422000 0x100>;
287 ti,hwmods = "uart8";
288 clock-frequency = <48000000>;
289 status = "disabled";
290 };
291
292 uart9: serial@48424000 {
293 compatible = "ti,omap4-uart";
294 reg = <0x48424000 0x100>;
295 ti,hwmods = "uart9";
296 clock-frequency = <48000000>;
297 status = "disabled";
298 };
299
300 uart10: serial@4ae2b000 {
301 compatible = "ti,omap4-uart";
302 reg = <0x4ae2b000 0x100>;
303 ti,hwmods = "uart10";
304 clock-frequency = <48000000>;
305 status = "disabled";
306 };
307
308 timer1: timer@4ae18000 {
309 compatible = "ti,omap5430-timer";
310 reg = <0x4ae18000 0x80>;
311 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
312 ti,hwmods = "timer1";
313 ti,timer-alwon;
314 };
315
316 timer2: timer@48032000 {
317 compatible = "ti,omap5430-timer";
318 reg = <0x48032000 0x80>;
319 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
320 ti,hwmods = "timer2";
321 };
322
323 timer3: timer@48034000 {
324 compatible = "ti,omap5430-timer";
325 reg = <0x48034000 0x80>;
326 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
327 ti,hwmods = "timer3";
328 };
329
330 timer4: timer@48036000 {
331 compatible = "ti,omap5430-timer";
332 reg = <0x48036000 0x80>;
333 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
334 ti,hwmods = "timer4";
335 };
336
337 timer5: timer@48820000 {
338 compatible = "ti,omap5430-timer";
339 reg = <0x48820000 0x80>;
340 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
341 ti,hwmods = "timer5";
342 ti,timer-dsp;
343 };
344
345 timer6: timer@48822000 {
346 compatible = "ti,omap5430-timer";
347 reg = <0x48822000 0x80>;
348 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
349 ti,hwmods = "timer6";
350 ti,timer-dsp;
351 ti,timer-pwm;
352 };
353
354 timer7: timer@48824000 {
355 compatible = "ti,omap5430-timer";
356 reg = <0x48824000 0x80>;
357 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
358 ti,hwmods = "timer7";
359 ti,timer-dsp;
360 };
361
362 timer8: timer@48826000 {
363 compatible = "ti,omap5430-timer";
364 reg = <0x48826000 0x80>;
365 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
366 ti,hwmods = "timer8";
367 ti,timer-dsp;
368 ti,timer-pwm;
369 };
370
371 timer9: timer@4803e000 {
372 compatible = "ti,omap5430-timer";
373 reg = <0x4803e000 0x80>;
374 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
375 ti,hwmods = "timer9";
376 };
377
378 timer10: timer@48086000 {
379 compatible = "ti,omap5430-timer";
380 reg = <0x48086000 0x80>;
381 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
382 ti,hwmods = "timer10";
383 };
384
385 timer11: timer@48088000 {
386 compatible = "ti,omap5430-timer";
387 reg = <0x48088000 0x80>;
388 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
389 ti,hwmods = "timer11";
390 ti,timer-pwm;
391 };
392
393 timer13: timer@48828000 {
394 compatible = "ti,omap5430-timer";
395 reg = <0x48828000 0x80>;
396 ti,hwmods = "timer13";
397 status = "disabled";
398 };
399
400 timer14: timer@4882a000 {
401 compatible = "ti,omap5430-timer";
402 reg = <0x4882a000 0x80>;
403 ti,hwmods = "timer14";
404 status = "disabled";
405 };
406
407 timer15: timer@4882c000 {
408 compatible = "ti,omap5430-timer";
409 reg = <0x4882c000 0x80>;
410 ti,hwmods = "timer15";
411 status = "disabled";
412 };
413
414 timer16: timer@4882e000 {
415 compatible = "ti,omap5430-timer";
416 reg = <0x4882e000 0x80>;
417 ti,hwmods = "timer16";
418 status = "disabled";
419 };
420
421 wdt2: wdt@4ae14000 {
422 compatible = "ti,omap4-wdt";
423 reg = <0x4ae14000 0x80>;
424 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
425 ti,hwmods = "wd_timer2";
426 };
427
428 i2c1: i2c@48070000 {
429 compatible = "ti,omap4-i2c";
430 reg = <0x48070000 0x100>;
431 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
432 #address-cells = <1>;
433 #size-cells = <0>;
434 ti,hwmods = "i2c1";
435 status = "disabled";
436 };
437
438 i2c2: i2c@48072000 {
439 compatible = "ti,omap4-i2c";
440 reg = <0x48072000 0x100>;
441 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>;
443 #size-cells = <0>;
444 ti,hwmods = "i2c2";
445 status = "disabled";
446 };
447
448 i2c3: i2c@48060000 {
449 compatible = "ti,omap4-i2c";
450 reg = <0x48060000 0x100>;
451 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 ti,hwmods = "i2c3";
455 status = "disabled";
456 };
457
458 i2c4: i2c@4807a000 {
459 compatible = "ti,omap4-i2c";
460 reg = <0x4807a000 0x100>;
461 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
463 #size-cells = <0>;
464 ti,hwmods = "i2c4";
465 status = "disabled";
466 };
467
468 i2c5: i2c@4807c000 {
469 compatible = "ti,omap4-i2c";
470 reg = <0x4807c000 0x100>;
471 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 ti,hwmods = "i2c5";
475 status = "disabled";
476 };
477
478 mmc1: mmc@4809c000 {
479 compatible = "ti,omap4-hsmmc";
480 reg = <0x4809c000 0x400>;
481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
482 ti,hwmods = "mmc1";
483 ti,dual-volt;
484 ti,needs-special-reset;
485 dmas = <&sdma 61>, <&sdma 62>;
486 dma-names = "tx", "rx";
487 status = "disabled";
488 };
489
490 mmc2: mmc@480b4000 {
491 compatible = "ti,omap4-hsmmc";
492 reg = <0x480b4000 0x400>;
493 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
494 ti,hwmods = "mmc2";
495 ti,needs-special-reset;
496 dmas = <&sdma 47>, <&sdma 48>;
497 dma-names = "tx", "rx";
498 status = "disabled";
499 };
500
501 mmc3: mmc@480ad000 {
502 compatible = "ti,omap4-hsmmc";
503 reg = <0x480ad000 0x400>;
504 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
505 ti,hwmods = "mmc3";
506 ti,needs-special-reset;
507 dmas = <&sdma 77>, <&sdma 78>;
508 dma-names = "tx", "rx";
509 status = "disabled";
510 };
511
512 mmc4: mmc@480d1000 {
513 compatible = "ti,omap4-hsmmc";
514 reg = <0x480d1000 0x400>;
515 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
516 ti,hwmods = "mmc4";
517 ti,needs-special-reset;
518 dmas = <&sdma 57>, <&sdma 58>;
519 dma-names = "tx", "rx";
520 status = "disabled";
521 };
522
523 mcspi1: spi@48098000 {
524 compatible = "ti,omap4-mcspi";
525 reg = <0x48098000 0x200>;
526 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 ti,hwmods = "mcspi1";
530 ti,spi-num-cs = <4>;
531 dmas = <&sdma 35>,
532 <&sdma 36>,
533 <&sdma 37>,
534 <&sdma 38>,
535 <&sdma 39>,
536 <&sdma 40>,
537 <&sdma 41>,
538 <&sdma 42>;
539 dma-names = "tx0", "rx0", "tx1", "rx1",
540 "tx2", "rx2", "tx3", "rx3";
541 status = "disabled";
542 };
543
544 mcspi2: spi@4809a000 {
545 compatible = "ti,omap4-mcspi";
546 reg = <0x4809a000 0x200>;
547 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
548 #address-cells = <1>;
549 #size-cells = <0>;
550 ti,hwmods = "mcspi2";
551 ti,spi-num-cs = <2>;
552 dmas = <&sdma 43>,
553 <&sdma 44>,
554 <&sdma 45>,
555 <&sdma 46>;
556 dma-names = "tx0", "rx0", "tx1", "rx1";
557 status = "disabled";
558 };
559
560 mcspi3: spi@480b8000 {
561 compatible = "ti,omap4-mcspi";
562 reg = <0x480b8000 0x200>;
563 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>;
565 #size-cells = <0>;
566 ti,hwmods = "mcspi3";
567 ti,spi-num-cs = <2>;
568 dmas = <&sdma 15>, <&sdma 16>;
569 dma-names = "tx0", "rx0";
570 status = "disabled";
571 };
572
573 mcspi4: spi@480ba000 {
574 compatible = "ti,omap4-mcspi";
575 reg = <0x480ba000 0x200>;
576 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
578 #size-cells = <0>;
579 ti,hwmods = "mcspi4";
580 ti,spi-num-cs = <1>;
581 dmas = <&sdma 70>, <&sdma 71>;
582 dma-names = "tx0", "rx0";
583 status = "disabled";
584 };
585 };
586};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index caadc0257342..a73eeb5f258f 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -49,6 +49,12 @@
49 reg = <0x10000000 0x100>; 49 reg = <0x10000000 0x100>;
50 }; 50 };
51 51
52 mipi_phy: video-phy@10020710 {
53 compatible = "samsung,s5pv210-mipi-video-phy";
54 reg = <0x10020710 8>;
55 #phy-cells = <1>;
56 };
57
52 pd_mfc: mfc-power-domain@10023C40 { 58 pd_mfc: mfc-power-domain@10023C40 {
53 compatible = "samsung,exynos4210-pd"; 59 compatible = "samsung,exynos4210-pd";
54 reg = <0x10023C40 0x20>; 60 reg = <0x10023C40 0x20>;
@@ -161,6 +167,8 @@
161 clock-names = "csis", "sclk_csis"; 167 clock-names = "csis", "sclk_csis";
162 bus-width = <4>; 168 bus-width = <4>;
163 samsung,power-domain = <&pd_cam>; 169 samsung,power-domain = <&pd_cam>;
170 phys = <&mipi_phy 0>;
171 phy-names = "csis";
164 status = "disabled"; 172 status = "disabled";
165 #address-cells = <1>; 173 #address-cells = <1>;
166 #size-cells = <0>; 174 #size-cells = <0>;
@@ -174,6 +182,8 @@
174 clock-names = "csis", "sclk_csis"; 182 clock-names = "csis", "sclk_csis";
175 bus-width = <2>; 183 bus-width = <2>;
176 samsung,power-domain = <&pd_cam>; 184 samsung,power-domain = <&pd_cam>;
185 phys = <&mipi_phy 2>;
186 phy-names = "csis";
177 status = "disabled"; 187 status = "disabled";
178 #address-cells = <1>; 188 #address-cells = <1>;
179 #size-cells = <0>; 189 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 46378fee2a13..1a12fb23767c 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -32,13 +32,20 @@
32 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; 32 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
33 }; 33 };
34 34
35 mmc_reg: voltage-regulator { 35 regulators {
36 compatible = "regulator-fixed"; 36 compatible = "simple-bus";
37 regulator-name = "VMEM_VDD_2.8V"; 37 #address-cells = <1>;
38 regulator-min-microvolt = <2800000>; 38 #size-cells = <0>;
39 regulator-max-microvolt = <2800000>; 39
40 gpio = <&gpx1 1 0>; 40 mmc_reg: regulator@0 {
41 enable-active-high; 41 compatible = "regulator-fixed";
42 reg = <0>;
43 regulator-name = "VMEM_VDD_2.8V";
44 regulator-min-microvolt = <2800000>;
45 regulator-max-microvolt = <2800000>;
46 gpio = <&gpx1 1 0>;
47 enable-active-high;
48 };
42 }; 49 };
43 50
44 tmu@100C0000 { 51 tmu@100C0000 {
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 8768b03702e5..d65984c440f6 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -32,13 +32,20 @@
32 reg = <0x0203F000 0x1000>; 32 reg = <0x0203F000 0x1000>;
33 }; 33 };
34 34
35 mmc_reg: voltage-regulator { 35 regulators {
36 compatible = "regulator-fixed"; 36 compatible = "simple-bus";
37 regulator-name = "VMEM_VDD_2.8V"; 37 #address-cells = <1>;
38 regulator-min-microvolt = <2800000>; 38 #size-cells = <0>;
39 regulator-max-microvolt = <2800000>; 39
40 gpio = <&gpx1 1 0>; 40 mmc_reg: regulator@0 {
41 enable-active-high; 41 compatible = "regulator-fixed";
42 reg = <0>;
43 regulator-name = "VMEM_VDD_2.8V";
44 regulator-min-microvolt = <2800000>;
45 regulator-max-microvolt = <2800000>;
46 gpio = <&gpx1 1 0>;
47 enable-active-high;
48 };
42 }; 49 };
43 50
44 pinctrl@11000000 { 51 pinctrl@11000000 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa33731..684527087aa4 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -324,7 +324,14 @@
324 }; 324 };
325 325
326 i2c@12C80000 { 326 i2c@12C80000 {
327 status = "disabled"; 327 samsung,i2c-sda-delay = <100>;
328 samsung,i2c-max-bus-freq = <66000>;
329 samsung,i2c-slave-addr = <0x50>;
330
331 hdmiddc@50 {
332 compatible = "samsung,exynos4210-hdmiddc";
333 reg = <0x50>;
334 };
328 }; 335 };
329 336
330 i2c@12C90000 { 337 i2c@12C90000 {
@@ -362,6 +369,17 @@
362 status = "disabled"; 369 status = "disabled";
363 }; 370 };
364 371
372 i2c@12CE0000 {
373 samsung,i2c-sda-delay = <100>;
374 samsung,i2c-max-bus-freq = <66000>;
375 samsung,i2c-slave-addr = <0x38>;
376
377 hdmiphy@38 {
378 compatible = "samsung,exynos4212-hdmiphy";
379 reg = <0x38>;
380 };
381 };
382
365 i2c@121D0000 { 383 i2c@121D0000 {
366 status = "disabled"; 384 status = "disabled";
367 }; 385 };
@@ -412,6 +430,10 @@
412 status = "disabled"; 430 status = "disabled";
413 }; 431 };
414 432
433 i2s0: i2s@03830000 {
434 status = "okay";
435 };
436
415 spi_0: spi@12d20000 { 437 spi_0: spi@12d20000 {
416 status = "disabled"; 438 status = "disabled";
417 }; 439 };
@@ -482,13 +504,15 @@
482 #address-cells = <1>; 504 #address-cells = <1>;
483 #size-cells = <0>; 505 #size-cells = <0>;
484 506
485 main_dc_reg: fixedregulator@1 { 507 main_dc_reg: regulator@0 {
486 compatible = "regulator-fixed"; 508 compatible = "regulator-fixed";
509 reg = <0>;
487 regulator-name = "MAIN_DC"; 510 regulator-name = "MAIN_DC";
488 }; 511 };
489 512
490 mmc_reg: voltage-regulator { 513 mmc_reg: regulator@1 {
491 compatible = "regulator-fixed"; 514 compatible = "regulator-fixed";
515 reg = <1>;
492 regulator-name = "VDD_33ON_2.8V"; 516 regulator-name = "VDD_33ON_2.8V";
493 regulator-min-microvolt = <2800000>; 517 regulator-min-microvolt = <2800000>;
494 regulator-max-microvolt = <2800000>; 518 regulator-max-microvolt = <2800000>;
@@ -496,8 +520,9 @@
496 enable-active-high; 520 enable-active-high;
497 }; 521 };
498 522
499 reg_hdmi_en: fixedregulator@0 { 523 reg_hdmi_en: regulator@2 {
500 compatible = "regulator-fixed"; 524 compatible = "regulator-fixed";
525 reg = <2>;
501 regulator-name = "hdmi-en"; 526 regulator-name = "hdmi-en";
502 }; 527 };
503 }; 528 };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b329f2ce..f86d56760a45 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -231,14 +231,6 @@
231 status = "okay"; 231 status = "okay";
232 }; 232 };
233 233
234 i2s1: i2s@12D60000 {
235 status = "disabled";
236 };
237
238 i2s2: i2s@12D70000 {
239 status = "disabled";
240 };
241
242 sound { 234 sound {
243 compatible = "samsung,smdk-wm8994"; 235 compatible = "samsung,smdk-wm8994";
244 236
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index bbac42a78ce5..9db5047812f3 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -422,6 +422,7 @@
422 422
423 i2s0: i2s@03830000 { 423 i2s0: i2s@03830000 {
424 compatible = "samsung,s5pv210-i2s"; 424 compatible = "samsung,s5pv210-i2s";
425 status = "disabled";
425 reg = <0x03830000 0x100>; 426 reg = <0x03830000 0x100>;
426 dmas = <&pdma0 10 427 dmas = <&pdma0 10
427 &pdma0 9 428 &pdma0 9
@@ -438,6 +439,7 @@
438 439
439 i2s1: i2s@12D60000 { 440 i2s1: i2s@12D60000 {
440 compatible = "samsung,s3c6410-i2s"; 441 compatible = "samsung,s3c6410-i2s";
442 status = "disabled";
441 reg = <0x12D60000 0x100>; 443 reg = <0x12D60000 0x100>;
442 dmas = <&pdma1 12 444 dmas = <&pdma1 12
443 &pdma1 11>; 445 &pdma1 11>;
@@ -450,6 +452,7 @@
450 452
451 i2s2: i2s@12D70000 { 453 i2s2: i2s@12D70000 {
452 compatible = "samsung,s3c6410-i2s"; 454 compatible = "samsung,s3c6410-i2s";
455 status = "disabled";
453 reg = <0x12D70000 0x100>; 456 reg = <0x12D70000 0x100>;
454 dmas = <&pdma0 12 457 dmas = <&pdma0 12
455 &pdma0 11>; 458 &pdma0 11>;
@@ -615,16 +618,18 @@
615 compatible = "samsung,exynos4212-hdmi"; 618 compatible = "samsung,exynos4212-hdmi";
616 reg = <0x14530000 0x70000>; 619 reg = <0x14530000 0x70000>;
617 interrupts = <0 95 0>; 620 interrupts = <0 95 0>;
618 clocks = <&clock 333>, <&clock 136>, <&clock 137>, 621 clocks = <&clock 344>, <&clock 136>, <&clock 137>,
619 <&clock 333>, <&clock 333>; 622 <&clock 159>, <&clock 1024>;
620 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 623 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
621 "sclk_hdmiphy", "hdmiphy"; 624 "sclk_hdmiphy", "mout_hdmi";
622 }; 625 };
623 626
624 mixer { 627 mixer {
625 compatible = "samsung,exynos5250-mixer"; 628 compatible = "samsung,exynos5250-mixer";
626 reg = <0x14450000 0x10000>; 629 reg = <0x14450000 0x10000>;
627 interrupts = <0 94 0>; 630 interrupts = <0 94 0>;
631 clocks = <&clock 343>, <&clock 136>;
632 clock-names = "mixer", "sclk_hdmi";
628 }; 633 };
629 634
630 dp_phy: video-phy@10040720 { 635 dp_phy: video-phy@10040720 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25ba7c2..79524c74c603 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -61,4 +61,30 @@
61 }; 61 };
62 }; 62 };
63 63
64 pinctrl@13400000 {
65 hdmi_hpd_irq: hdmi-hpd-irq {
66 samsung,pins = "gpx3-7";
67 samsung,pin-function = <0>;
68 samsung,pin-pud = <1>;
69 samsung,pin-drv = <0>;
70 };
71 };
72
73 hdmi@14530000 {
74 status = "okay";
75 hpd-gpio = <&gpx3 7 0>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&hdmi_hpd_irq>;
78 };
79
80 i2c_2: i2c@12C80000 {
81 samsung,i2c-sda-delay = <100>;
82 samsung,i2c-max-bus-freq = <66000>;
83 status = "okay";
84
85 hdmiddc@50 {
86 compatible = "samsung,exynos4210-hdmiddc";
87 reg = <0x50>;
88 };
89 };
64}; 90};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd704e19..09aa06cb3d3a 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -27,6 +27,10 @@
27 pinctrl2 = &pinctrl_2; 27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3; 28 pinctrl3 = &pinctrl_3;
29 pinctrl4 = &pinctrl_4; 29 pinctrl4 = &pinctrl_4;
30 i2c0 = &i2c_0;
31 i2c1 = &i2c_1;
32 i2c2 = &i2c_2;
33 i2c3 = &i2c_3;
30 }; 34 };
31 35
32 cpus { 36 cpus {
@@ -235,4 +239,75 @@
235 io-channel-ranges; 239 io-channel-ranges;
236 status = "disabled"; 240 status = "disabled";
237 }; 241 };
242
243 i2c_0: i2c@12C60000 {
244 compatible = "samsung,s3c2440-i2c";
245 reg = <0x12C60000 0x100>;
246 interrupts = <0 56 0>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 clocks = <&clock 261>;
250 clock-names = "i2c";
251 pinctrl-names = "default";
252 pinctrl-0 = <&i2c0_bus>;
253 status = "disabled";
254 };
255
256 i2c_1: i2c@12C70000 {
257 compatible = "samsung,s3c2440-i2c";
258 reg = <0x12C70000 0x100>;
259 interrupts = <0 57 0>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 clocks = <&clock 262>;
263 clock-names = "i2c";
264 pinctrl-names = "default";
265 pinctrl-0 = <&i2c1_bus>;
266 status = "disabled";
267 };
268
269 i2c_2: i2c@12C80000 {
270 compatible = "samsung,s3c2440-i2c";
271 reg = <0x12C80000 0x100>;
272 interrupts = <0 58 0>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 clocks = <&clock 263>;
276 clock-names = "i2c";
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c2_bus>;
279 status = "disabled";
280 };
281
282 i2c_3: i2c@12C90000 {
283 compatible = "samsung,s3c2440-i2c";
284 reg = <0x12C90000 0x100>;
285 interrupts = <0 59 0>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 clocks = <&clock 264>;
289 clock-names = "i2c";
290 pinctrl-names = "default";
291 pinctrl-0 = <&i2c3_bus>;
292 status = "disabled";
293 };
294
295 hdmi@14530000 {
296 compatible = "samsung,exynos4212-hdmi";
297 reg = <0x14530000 0x70000>;
298 interrupts = <0 95 0>;
299 clocks = <&clock 413>, <&clock 143>, <&clock 768>,
300 <&clock 158>, <&clock 640>;
301 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
302 "sclk_hdmiphy", "mout_hdmi";
303 status = "disabled";
304 };
305
306 mixer@14450000 {
307 compatible = "samsung,exynos5420-mixer";
308 reg = <0x14450000 0x10000>;
309 interrupts = <0 94 0>;
310 clocks = <&clock 431>, <&clock 143>;
311 clock-names = "mixer", "sclk_hdmi";
312 };
238}; 313};
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index a7cb84884cfb..d58cb787061a 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -68,9 +68,11 @@
68 68
69 pcie@290000 { 69 pcie@290000 {
70 reset-gpio = <&pin_ctrl 5 0>; 70 reset-gpio = <&pin_ctrl 5 0>;
71 status = "okay";
71 }; 72 };
72 73
73 pcie@2a0000 { 74 pcie@2a0000 {
74 reset-gpio = <&pin_ctrl 22 0>; 75 reset-gpio = <&pin_ctrl 22 0>;
76 status = "okay";
75 }; 77 };
76}; 78};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 5d6cf4965d6e..8da107088ce4 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -276,6 +276,7 @@
276 interrupt-map-mask = <0 0 0 0>; 276 interrupt-map-mask = <0 0 0 0>;
277 interrupt-map = <0x0 0 &gic 53>; 277 interrupt-map = <0x0 0 &gic 53>;
278 num-lanes = <4>; 278 num-lanes = <4>;
279 status = "disabled";
279 }; 280 };
280 281
281 pcie@2a0000 { 282 pcie@2a0000 {
@@ -296,5 +297,6 @@
296 interrupt-map-mask = <0 0 0 0>; 297 interrupt-map-mask = <0 0 0 0>;
297 interrupt-map = <0x0 0 &gic 56>; 298 interrupt-map = <0x0 0 &gic 56>;
298 num-lanes = <4>; 299 num-lanes = <4>;
300 status = "disabled";
299 }; 301 };
300}; 302};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 185c7c01102a..1f026adefd45 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx23.dtsi" 13#include "imx23.dtsi"
14 14
15/ { 15/ {
16 model = "Freescale i.MX23 Evaluation Kit"; 16 model = "Freescale i.MX23 Evaluation Kit";
@@ -45,14 +45,14 @@
45 hog_pins_a: hog@0 { 45 hog_pins_a: hog@0 {
46 reg = <0>; 46 reg = <0>;
47 fsl,pinmux-ids = < 47 fsl,pinmux-ids = <
48 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ 48 MX23_PAD_LCD_RESET__GPIO_1_18
49 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ 49 MX23_PAD_PWM3__GPIO_1_29
50 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ 50 MX23_PAD_PWM4__GPIO_1_30
51 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ 51 MX23_PAD_SSP1_DETECT__SSP1_DETECT
52 >; 52 >;
53 fsl,drive-strength = <0>; 53 fsl,drive-strength = <MXS_DRIVE_4mA>;
54 fsl,voltage = <1>; 54 fsl,voltage = <MXS_VOLTAGE_HIGH>;
55 fsl,pull-up = <0>; 55 fsl,pull-up = <MXS_PULL_DISABLE>;
56 }; 56 };
57 }; 57 };
58 58
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index fc766ae12e24..526bfdbd87f9 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -12,7 +12,7 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "imx23.dtsi" 15#include "imx23.dtsi"
16 16
17/ { 17/ {
18 model = "i.MX23 Olinuxino Low Cost Board"; 18 model = "i.MX23 Olinuxino Low Cost Board";
@@ -40,21 +40,21 @@
40 hog_pins_a: hog@0 { 40 hog_pins_a: hog@0 {
41 reg = <0>; 41 reg = <0>;
42 fsl,pinmux-ids = < 42 fsl,pinmux-ids = <
43 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ 43 MX23_PAD_GPMI_ALE__GPIO_0_17
44 >; 44 >;
45 fsl,drive-strength = <0>; 45 fsl,drive-strength = <MXS_DRIVE_4mA>;
46 fsl,voltage = <1>; 46 fsl,voltage = <MXS_VOLTAGE_HIGH>;
47 fsl,pull-up = <0>; 47 fsl,pull-up = <MXS_PULL_DISABLE>;
48 }; 48 };
49 49
50 led_pin_gpio2_1: led_gpio2_1@0 { 50 led_pin_gpio2_1: led_gpio2_1@0 {
51 reg = <0>; 51 reg = <0>;
52 fsl,pinmux-ids = < 52 fsl,pinmux-ids = <
53 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ 53 MX23_PAD_SSP1_DETECT__GPIO_2_1
54 >; 54 >;
55 fsl,drive-strength = <0>; 55 fsl,drive-strength = <MXS_DRIVE_4mA>;
56 fsl,voltage = <1>; 56 fsl,voltage = <MXS_VOLTAGE_HIGH>;
57 fsl,pull-up = <0>; 57 fsl,pull-up = <MXS_PULL_DISABLE>;
58 }; 58 };
59 }; 59 };
60 60
diff --git a/arch/arm/boot/dts/imx23-pinfunc.h b/arch/arm/boot/dts/imx23-pinfunc.h
new file mode 100644
index 000000000000..5c0f32ca3a93
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-pinfunc.h
@@ -0,0 +1,333 @@
1/*
2 * Header providing constants for i.MX23 pinctrl bindings.
3 *
4 * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
15#define __DT_BINDINGS_MX23_PINCTRL_H__
16
17#include "mxs-pinfunc.h"
18
19#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
20#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
21#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
22#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
23#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
24#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
25#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
26#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
27#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
28#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
29#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
30#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
31#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
32#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
33#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
34#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
35#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
36#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
37#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
38#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
39#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
40#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
41#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
42#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
43#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
44#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
45#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
46#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
47#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
48#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
49#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
50#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
51#define MX23_PAD_LCD_D00__LCD_D00 0x1000
52#define MX23_PAD_LCD_D01__LCD_D01 0x1010
53#define MX23_PAD_LCD_D02__LCD_D02 0x1020
54#define MX23_PAD_LCD_D03__LCD_D03 0x1030
55#define MX23_PAD_LCD_D04__LCD_D04 0x1040
56#define MX23_PAD_LCD_D05__LCD_D05 0x1050
57#define MX23_PAD_LCD_D06__LCD_D06 0x1060
58#define MX23_PAD_LCD_D07__LCD_D07 0x1070
59#define MX23_PAD_LCD_D08__LCD_D08 0x1080
60#define MX23_PAD_LCD_D09__LCD_D09 0x1090
61#define MX23_PAD_LCD_D10__LCD_D10 0x10a0
62#define MX23_PAD_LCD_D11__LCD_D11 0x10b0
63#define MX23_PAD_LCD_D12__LCD_D12 0x10c0
64#define MX23_PAD_LCD_D13__LCD_D13 0x10d0
65#define MX23_PAD_LCD_D14__LCD_D14 0x10e0
66#define MX23_PAD_LCD_D15__LCD_D15 0x10f0
67#define MX23_PAD_LCD_D16__LCD_D16 0x1100
68#define MX23_PAD_LCD_D17__LCD_D17 0x1110
69#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120
70#define MX23_PAD_LCD_RS__LCD_RS 0x1130
71#define MX23_PAD_LCD_WR__LCD_WR 0x1140
72#define MX23_PAD_LCD_CS__LCD_CS 0x1150
73#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
74#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
75#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
76#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
77#define MX23_PAD_PWM0__PWM0 0x11a0
78#define MX23_PAD_PWM1__PWM1 0x11b0
79#define MX23_PAD_PWM2__PWM2 0x11c0
80#define MX23_PAD_PWM3__PWM3 0x11d0
81#define MX23_PAD_PWM4__PWM4 0x11e0
82#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
83#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
84#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
85#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
86#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
87#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
88#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
89#define MX23_PAD_ROTARYA__ROTARYA 0x2070
90#define MX23_PAD_ROTARYB__ROTARYB 0x2080
91#define MX23_PAD_EMI_A00__EMI_A00 0x2090
92#define MX23_PAD_EMI_A01__EMI_A01 0x20a0
93#define MX23_PAD_EMI_A02__EMI_A02 0x20b0
94#define MX23_PAD_EMI_A03__EMI_A03 0x20c0
95#define MX23_PAD_EMI_A04__EMI_A04 0x20d0
96#define MX23_PAD_EMI_A05__EMI_A05 0x20e0
97#define MX23_PAD_EMI_A06__EMI_A06 0x20f0
98#define MX23_PAD_EMI_A07__EMI_A07 0x2100
99#define MX23_PAD_EMI_A08__EMI_A08 0x2110
100#define MX23_PAD_EMI_A09__EMI_A09 0x2120
101#define MX23_PAD_EMI_A10__EMI_A10 0x2130
102#define MX23_PAD_EMI_A11__EMI_A11 0x2140
103#define MX23_PAD_EMI_A12__EMI_A12 0x2150
104#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160
105#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170
106#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180
107#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
108#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
109#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
110#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
111#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
112#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
113#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
114#define MX23_PAD_EMI_D00__EMI_D00 0x3000
115#define MX23_PAD_EMI_D01__EMI_D01 0x3010
116#define MX23_PAD_EMI_D02__EMI_D02 0x3020
117#define MX23_PAD_EMI_D03__EMI_D03 0x3030
118#define MX23_PAD_EMI_D04__EMI_D04 0x3040
119#define MX23_PAD_EMI_D05__EMI_D05 0x3050
120#define MX23_PAD_EMI_D06__EMI_D06 0x3060
121#define MX23_PAD_EMI_D07__EMI_D07 0x3070
122#define MX23_PAD_EMI_D08__EMI_D08 0x3080
123#define MX23_PAD_EMI_D09__EMI_D09 0x3090
124#define MX23_PAD_EMI_D10__EMI_D10 0x30a0
125#define MX23_PAD_EMI_D11__EMI_D11 0x30b0
126#define MX23_PAD_EMI_D12__EMI_D12 0x30c0
127#define MX23_PAD_EMI_D13__EMI_D13 0x30d0
128#define MX23_PAD_EMI_D14__EMI_D14 0x30e0
129#define MX23_PAD_EMI_D15__EMI_D15 0x30f0
130#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
131#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
132#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
133#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
134#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140
135#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
136#define MX23_PAD_GPMI_D00__LCD_D8 0x0001
137#define MX23_PAD_GPMI_D01__LCD_D9 0x0011
138#define MX23_PAD_GPMI_D02__LCD_D10 0x0021
139#define MX23_PAD_GPMI_D03__LCD_D11 0x0031
140#define MX23_PAD_GPMI_D04__LCD_D12 0x0041
141#define MX23_PAD_GPMI_D05__LCD_D13 0x0051
142#define MX23_PAD_GPMI_D06__LCD_D14 0x0061
143#define MX23_PAD_GPMI_D07__LCD_D15 0x0071
144#define MX23_PAD_GPMI_D08__LCD_D18 0x0081
145#define MX23_PAD_GPMI_D09__LCD_D19 0x0091
146#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1
147#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1
148#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1
149#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1
150#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
151#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
152#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101
153#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111
154#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
155#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
156#define MX23_PAD_AUART1_RX__IR_RX 0x01c1
157#define MX23_PAD_AUART1_TX__IR_TX 0x01d1
158#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
159#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
160#define MX23_PAD_LCD_D00__ETM_DA8 0x1001
161#define MX23_PAD_LCD_D01__ETM_DA9 0x1011
162#define MX23_PAD_LCD_D02__ETM_DA10 0x1021
163#define MX23_PAD_LCD_D03__ETM_DA11 0x1031
164#define MX23_PAD_LCD_D04__ETM_DA12 0x1041
165#define MX23_PAD_LCD_D05__ETM_DA13 0x1051
166#define MX23_PAD_LCD_D06__ETM_DA14 0x1061
167#define MX23_PAD_LCD_D07__ETM_DA15 0x1071
168#define MX23_PAD_LCD_D08__ETM_DA0 0x1081
169#define MX23_PAD_LCD_D09__ETM_DA1 0x1091
170#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1
171#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1
172#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1
173#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1
174#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1
175#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1
176#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
177#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131
178#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
179#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
180#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
181#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
182#define MX23_PAD_PWM0__ROTARYA 0x11a1
183#define MX23_PAD_PWM1__ROTARYB 0x11b1
184#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1
185#define MX23_PAD_PWM3__ETM_TCTL 0x11d1
186#define MX23_PAD_PWM4__ETM_TCLK 0x11e1
187#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
188#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
189#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
190#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071
191#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081
192#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
193#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
194#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
195#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
196#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
197#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
198#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
199#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
200#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
201#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
202#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
203#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
204#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
205#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
206#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
207#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
208#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
209#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
210#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
211#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
212#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
213#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
214#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
215#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
216#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
217#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
218#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
219#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
220#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
221#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
222#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
223#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
224#define MX23_PAD_PWM0__DUART_RX 0x11a2
225#define MX23_PAD_PWM1__DUART_TX 0x11b2
226#define MX23_PAD_PWM3__AUART1_CTS 0x11d2
227#define MX23_PAD_PWM4__AUART1_RTS 0x11e2
228#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
229#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
230#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
231#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
232#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
233#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
234#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
235#define MX23_PAD_ROTARYA__SPDIF 0x2072
236#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
237#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
238#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
239#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
240#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
241#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
242#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
243#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
244#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
245#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
246#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
247#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
248#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
249#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
250#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
251#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
252#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
253#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
254#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
255#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
256#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
257#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
258#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
259#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
260#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
261#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
262#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
263#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
264#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
265#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
266#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
267#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
268#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
269#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003
270#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013
271#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023
272#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033
273#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043
274#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053
275#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063
276#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073
277#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083
278#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093
279#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
280#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
281#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
282#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
283#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
284#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
285#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103
286#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113
287#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
288#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133
289#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143
290#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153
291#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
292#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
293#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
294#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
295#define MX23_PAD_PWM0__GPIO_1_26 0x11a3
296#define MX23_PAD_PWM1__GPIO_1_27 0x11b3
297#define MX23_PAD_PWM2__GPIO_1_28 0x11c3
298#define MX23_PAD_PWM3__GPIO_1_29 0x11d3
299#define MX23_PAD_PWM4__GPIO_1_30 0x11e3
300#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
301#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
302#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
303#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
304#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
305#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
306#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
307#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073
308#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083
309#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093
310#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
311#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
312#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
313#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
314#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
315#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
316#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103
317#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113
318#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123
319#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133
320#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143
321#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153
322#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
323#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
324#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
325#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
326#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
327#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
328#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
329#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
330#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
331#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
332
333#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 85c3864b6a56..cb64e2b191ea 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx23.dtsi" 13#include "imx23.dtsi"
14 14
15/ { 15/ {
16 model = "Freescale STMP378x Development Board"; 16 model = "Freescale STMP378x Development Board";
@@ -39,12 +39,12 @@
39 hog_pins_a: hog@0 { 39 hog_pins_a: hog@0 {
40 reg = <0>; 40 reg = <0>;
41 fsl,pinmux-ids = < 41 fsl,pinmux-ids = <
42 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ 42 MX23_PAD_PWM3__GPIO_1_29
43 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ 43 MX23_PAD_PWM4__GPIO_1_30
44 >; 44 >;
45 fsl,drive-strength = <0>; 45 fsl,drive-strength = <MXS_DRIVE_4mA>;
46 fsl,voltage = <1>; 46 fsl,voltage = <MXS_VOLTAGE_HIGH>;
47 fsl,pull-up = <0>; 47 fsl,pull-up = <MXS_PULL_DISABLE>;
48 }; 48 };
49 }; 49 };
50 }; 50 };
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 07caf767d428..c96ceaef7ddf 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -9,7 +9,8 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12/include/ "skeleton.dtsi" 12#include "skeleton.dtsi"
13#include "imx23-pinfunc.h"
13 14
14/ { 15/ {
15 interrupt-parent = <&icoll>; 16 interrupt-parent = <&icoll>;
@@ -137,174 +138,174 @@
137 duart_pins_a: duart@0 { 138 duart_pins_a: duart@0 {
138 reg = <0>; 139 reg = <0>;
139 fsl,pinmux-ids = < 140 fsl,pinmux-ids = <
140 0x11a2 /* MX23_PAD_PWM0__DUART_RX */ 141 MX23_PAD_PWM0__DUART_RX
141 0x11b2 /* MX23_PAD_PWM1__DUART_TX */ 142 MX23_PAD_PWM1__DUART_TX
142 >; 143 >;
143 fsl,drive-strength = <0>; 144 fsl,drive-strength = <MXS_DRIVE_4mA>;
144 fsl,voltage = <1>; 145 fsl,voltage = <MXS_VOLTAGE_HIGH>;
145 fsl,pull-up = <0>; 146 fsl,pull-up = <MXS_PULL_DISABLE>;
146 }; 147 };
147 148
148 auart0_pins_a: auart0@0 { 149 auart0_pins_a: auart0@0 {
149 reg = <0>; 150 reg = <0>;
150 fsl,pinmux-ids = < 151 fsl,pinmux-ids = <
151 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */ 152 MX23_PAD_AUART1_RX__AUART1_RX
152 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */ 153 MX23_PAD_AUART1_TX__AUART1_TX
153 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */ 154 MX23_PAD_AUART1_CTS__AUART1_CTS
154 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */ 155 MX23_PAD_AUART1_RTS__AUART1_RTS
155 >; 156 >;
156 fsl,drive-strength = <0>; 157 fsl,drive-strength = <MXS_DRIVE_4mA>;
157 fsl,voltage = <1>; 158 fsl,voltage = <MXS_VOLTAGE_HIGH>;
158 fsl,pull-up = <0>; 159 fsl,pull-up = <MXS_PULL_DISABLE>;
159 }; 160 };
160 161
161 auart0_2pins_a: auart0-2pins@0 { 162 auart0_2pins_a: auart0-2pins@0 {
162 reg = <0>; 163 reg = <0>;
163 fsl,pinmux-ids = < 164 fsl,pinmux-ids = <
164 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */ 165 MX23_PAD_I2C_SCL__AUART1_TX
165 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */ 166 MX23_PAD_I2C_SDA__AUART1_RX
166 >; 167 >;
167 fsl,drive-strength = <0>; 168 fsl,drive-strength = <MXS_DRIVE_4mA>;
168 fsl,voltage = <1>; 169 fsl,voltage = <MXS_VOLTAGE_HIGH>;
169 fsl,pull-up = <0>; 170 fsl,pull-up = <MXS_PULL_DISABLE>;
170 }; 171 };
171 172
172 gpmi_pins_a: gpmi-nand@0 { 173 gpmi_pins_a: gpmi-nand@0 {
173 reg = <0>; 174 reg = <0>;
174 fsl,pinmux-ids = < 175 fsl,pinmux-ids = <
175 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */ 176 MX23_PAD_GPMI_D00__GPMI_D00
176 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */ 177 MX23_PAD_GPMI_D01__GPMI_D01
177 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */ 178 MX23_PAD_GPMI_D02__GPMI_D02
178 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */ 179 MX23_PAD_GPMI_D03__GPMI_D03
179 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */ 180 MX23_PAD_GPMI_D04__GPMI_D04
180 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */ 181 MX23_PAD_GPMI_D05__GPMI_D05
181 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */ 182 MX23_PAD_GPMI_D06__GPMI_D06
182 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */ 183 MX23_PAD_GPMI_D07__GPMI_D07
183 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */ 184 MX23_PAD_GPMI_CLE__GPMI_CLE
184 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */ 185 MX23_PAD_GPMI_ALE__GPMI_ALE
185 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */ 186 MX23_PAD_GPMI_RDY0__GPMI_RDY0
186 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */ 187 MX23_PAD_GPMI_RDY1__GPMI_RDY1
187 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ 188 MX23_PAD_GPMI_WPN__GPMI_WPN
188 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ 189 MX23_PAD_GPMI_WRN__GPMI_WRN
189 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ 190 MX23_PAD_GPMI_RDN__GPMI_RDN
190 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */ 191 MX23_PAD_GPMI_CE1N__GPMI_CE1N
191 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */ 192 MX23_PAD_GPMI_CE0N__GPMI_CE0N
192 >; 193 >;
193 fsl,drive-strength = <0>; 194 fsl,drive-strength = <MXS_DRIVE_4mA>;
194 fsl,voltage = <1>; 195 fsl,voltage = <MXS_VOLTAGE_HIGH>;
195 fsl,pull-up = <0>; 196 fsl,pull-up = <MXS_PULL_DISABLE>;
196 }; 197 };
197 198
198 gpmi_pins_fixup: gpmi-pins-fixup { 199 gpmi_pins_fixup: gpmi-pins-fixup {
199 fsl,pinmux-ids = < 200 fsl,pinmux-ids = <
200 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ 201 MX23_PAD_GPMI_WPN__GPMI_WPN
201 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ 202 MX23_PAD_GPMI_WRN__GPMI_WRN
202 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ 203 MX23_PAD_GPMI_RDN__GPMI_RDN
203 >; 204 >;
204 fsl,drive-strength = <2>; 205 fsl,drive-strength = <MXS_DRIVE_12mA>;
205 }; 206 };
206 207
207 mmc0_4bit_pins_a: mmc0-4bit@0 { 208 mmc0_4bit_pins_a: mmc0-4bit@0 {
208 reg = <0>; 209 reg = <0>;
209 fsl,pinmux-ids = < 210 fsl,pinmux-ids = <
210 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ 211 MX23_PAD_SSP1_DATA0__SSP1_DATA0
211 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ 212 MX23_PAD_SSP1_DATA1__SSP1_DATA1
212 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ 213 MX23_PAD_SSP1_DATA2__SSP1_DATA2
213 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ 214 MX23_PAD_SSP1_DATA3__SSP1_DATA3
214 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ 215 MX23_PAD_SSP1_CMD__SSP1_CMD
215 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ 216 MX23_PAD_SSP1_SCK__SSP1_SCK
216 >; 217 >;
217 fsl,drive-strength = <1>; 218 fsl,drive-strength = <MXS_DRIVE_8mA>;
218 fsl,voltage = <1>; 219 fsl,voltage = <MXS_VOLTAGE_HIGH>;
219 fsl,pull-up = <1>; 220 fsl,pull-up = <MXS_PULL_ENABLE>;
220 }; 221 };
221 222
222 mmc0_8bit_pins_a: mmc0-8bit@0 { 223 mmc0_8bit_pins_a: mmc0-8bit@0 {
223 reg = <0>; 224 reg = <0>;
224 fsl,pinmux-ids = < 225 fsl,pinmux-ids = <
225 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ 226 MX23_PAD_SSP1_DATA0__SSP1_DATA0
226 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ 227 MX23_PAD_SSP1_DATA1__SSP1_DATA1
227 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ 228 MX23_PAD_SSP1_DATA2__SSP1_DATA2
228 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ 229 MX23_PAD_SSP1_DATA3__SSP1_DATA3
229 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */ 230 MX23_PAD_GPMI_D08__SSP1_DATA4
230 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */ 231 MX23_PAD_GPMI_D09__SSP1_DATA5
231 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */ 232 MX23_PAD_GPMI_D10__SSP1_DATA6
232 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */ 233 MX23_PAD_GPMI_D11__SSP1_DATA7
233 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ 234 MX23_PAD_SSP1_CMD__SSP1_CMD
234 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ 235 MX23_PAD_SSP1_DETECT__SSP1_DETECT
235 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ 236 MX23_PAD_SSP1_SCK__SSP1_SCK
236 >; 237 >;
237 fsl,drive-strength = <1>; 238 fsl,drive-strength = <MXS_DRIVE_8mA>;
238 fsl,voltage = <1>; 239 fsl,voltage = <MXS_VOLTAGE_HIGH>;
239 fsl,pull-up = <1>; 240 fsl,pull-up = <MXS_PULL_ENABLE>;
240 }; 241 };
241 242
242 mmc0_pins_fixup: mmc0-pins-fixup { 243 mmc0_pins_fixup: mmc0-pins-fixup {
243 fsl,pinmux-ids = < 244 fsl,pinmux-ids = <
244 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ 245 MX23_PAD_SSP1_DETECT__SSP1_DETECT
245 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ 246 MX23_PAD_SSP1_SCK__SSP1_SCK
246 >; 247 >;
247 fsl,pull-up = <0>; 248 fsl,pull-up = <MXS_PULL_DISABLE>;
248 }; 249 };
249 250
250 pwm2_pins_a: pwm2@0 { 251 pwm2_pins_a: pwm2@0 {
251 reg = <0>; 252 reg = <0>;
252 fsl,pinmux-ids = < 253 fsl,pinmux-ids = <
253 0x11c0 /* MX23_PAD_PWM2__PWM2 */ 254 MX23_PAD_PWM2__PWM2
254 >; 255 >;
255 fsl,drive-strength = <0>; 256 fsl,drive-strength = <MXS_DRIVE_4mA>;
256 fsl,voltage = <1>; 257 fsl,voltage = <MXS_VOLTAGE_HIGH>;
257 fsl,pull-up = <0>; 258 fsl,pull-up = <MXS_PULL_DISABLE>;
258 }; 259 };
259 260
260 lcdif_24bit_pins_a: lcdif-24bit@0 { 261 lcdif_24bit_pins_a: lcdif-24bit@0 {
261 reg = <0>; 262 reg = <0>;
262 fsl,pinmux-ids = < 263 fsl,pinmux-ids = <
263 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */ 264 MX23_PAD_LCD_D00__LCD_D00
264 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */ 265 MX23_PAD_LCD_D01__LCD_D01
265 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */ 266 MX23_PAD_LCD_D02__LCD_D02
266 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */ 267 MX23_PAD_LCD_D03__LCD_D03
267 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */ 268 MX23_PAD_LCD_D04__LCD_D04
268 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */ 269 MX23_PAD_LCD_D05__LCD_D05
269 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */ 270 MX23_PAD_LCD_D06__LCD_D06
270 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */ 271 MX23_PAD_LCD_D07__LCD_D07
271 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */ 272 MX23_PAD_LCD_D08__LCD_D08
272 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */ 273 MX23_PAD_LCD_D09__LCD_D09
273 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */ 274 MX23_PAD_LCD_D10__LCD_D10
274 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */ 275 MX23_PAD_LCD_D11__LCD_D11
275 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */ 276 MX23_PAD_LCD_D12__LCD_D12
276 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */ 277 MX23_PAD_LCD_D13__LCD_D13
277 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */ 278 MX23_PAD_LCD_D14__LCD_D14
278 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */ 279 MX23_PAD_LCD_D15__LCD_D15
279 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */ 280 MX23_PAD_LCD_D16__LCD_D16
280 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */ 281 MX23_PAD_LCD_D17__LCD_D17
281 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */ 282 MX23_PAD_GPMI_D08__LCD_D18
282 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */ 283 MX23_PAD_GPMI_D09__LCD_D19
283 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */ 284 MX23_PAD_GPMI_D10__LCD_D20
284 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */ 285 MX23_PAD_GPMI_D11__LCD_D21
285 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */ 286 MX23_PAD_GPMI_D12__LCD_D22
286 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */ 287 MX23_PAD_GPMI_D13__LCD_D23
287 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */ 288 MX23_PAD_LCD_DOTCK__LCD_DOTCK
288 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */ 289 MX23_PAD_LCD_ENABLE__LCD_ENABLE
289 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */ 290 MX23_PAD_LCD_HSYNC__LCD_HSYNC
290 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */ 291 MX23_PAD_LCD_VSYNC__LCD_VSYNC
291 >; 292 >;
292 fsl,drive-strength = <0>; 293 fsl,drive-strength = <MXS_DRIVE_4mA>;
293 fsl,voltage = <1>; 294 fsl,voltage = <MXS_VOLTAGE_HIGH>;
294 fsl,pull-up = <0>; 295 fsl,pull-up = <MXS_PULL_DISABLE>;
295 }; 296 };
296 297
297 spi2_pins_a: spi2@0 { 298 spi2_pins_a: spi2@0 {
298 reg = <0>; 299 reg = <0>;
299 fsl,pinmux-ids = < 300 fsl,pinmux-ids = <
300 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */ 301 MX23_PAD_GPMI_WRN__SSP2_SCK
301 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */ 302 MX23_PAD_GPMI_RDY1__SSP2_CMD
302 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */ 303 MX23_PAD_GPMI_D00__SSP2_DATA0
303 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */ 304 MX23_PAD_GPMI_D03__SSP2_DATA3
304 >; 305 >;
305 fsl,drive-strength = <1>; 306 fsl,drive-strength = <MXS_DRIVE_8mA>;
306 fsl,voltage = <1>; 307 fsl,voltage = <MXS_VOLTAGE_HIGH>;
307 fsl,pull-up = <1>; 308 fsl,pull-up = <MXS_PULL_ENABLE>;
308 }; 309 };
309 }; 310 };
310 311
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 2a377ca1881a..47c8c26012e4 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -16,6 +16,26 @@
16 model = "Armadeus Systems APF27Dev docking/development board"; 16 model = "Armadeus Systems APF27Dev docking/development board";
17 compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27"; 17 compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27";
18 18
19 display: display {
20 model = "Chimei-LW700AT9003";
21 native-mode = <&timing0>;
22 bits-per-pixel = <16>; /* non-standard but required */
23 fsl,pcr = <0xfae80083>; /* non-standard but required */
24 display-timings {
25 timing0: 640x480 {
26 clock-frequency = <33000033>;
27 hactive = <800>;
28 vactive = <640>;
29 hback-porch = <96>;
30 hfront-porch = <96>;
31 vback-porch = <20>;
32 vfront-porch = <21>;
33 hsync-len = <64>;
34 vsync-len = <4>;
35 };
36 };
37 };
38
19 gpio-keys { 39 gpio-keys {
20 compatible = "gpio-keys"; 40 compatible = "gpio-keys";
21 41
@@ -50,6 +70,12 @@
50 status = "okay"; 70 status = "okay";
51}; 71};
52 72
73&fb {
74 display = <&display>;
75 fsl,dmacr = <0x00020010>;
76 status = "okay";
77};
78
53&i2c1 { 79&i2c1 {
54 clock-frequency = <400000>; 80 clock-frequency = <400000>;
55 status = "okay"; 81 status = "okay";
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index b7a1c6d950b9..826231eb4446 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -123,6 +123,7 @@
123 }; 123 };
124 124
125 pwm: pwm@10006000 { 125 pwm: pwm@10006000 {
126 #pwm-cells = <2>;
126 compatible = "fsl,imx27-pwm"; 127 compatible = "fsl,imx27-pwm";
127 reg = <0x10006000 0x1000>; 128 reg = <0x10006000 0x1000>;
128 interrupts = <23>; 129 interrupts = <23>;
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 7eb075876c4c..7198fe3798c6 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx28.dtsi" 13#include "imx28.dtsi"
14 14
15/ { 15/ {
16 model = "Armadeus Systems APF28 module"; 16 model = "Armadeus Systems APF28 module";
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index b602494c152b..e2efd8d89c4f 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/* APF28Dev is a docking board for the APF28 SOM */ 12/* APF28Dev is a docking board for the APF28 SOM */
13/include/ "imx28-apf28.dts" 13#include "imx28-apf28.dts"
14 14
15/ { 15/ {
16 model = "Armadeus Systems APF28Dev docking/development board"; 16 model = "Armadeus Systems APF28Dev docking/development board";
@@ -41,30 +41,30 @@
41 hog_pins_apf28dev: hog@0 { 41 hog_pins_apf28dev: hog@0 {
42 reg = <0>; 42 reg = <0>;
43 fsl,pinmux-ids = < 43 fsl,pinmux-ids = <
44 0x1103 /* MX28_PAD_LCD_D16__GPIO_1_16 */ 44 MX28_PAD_LCD_D16__GPIO_1_16
45 0x1113 /* MX28_PAD_LCD_D17__GPIO_1_17 */ 45 MX28_PAD_LCD_D17__GPIO_1_17
46 0x1123 /* MX28_PAD_LCD_D18__GPIO_1_18 */ 46 MX28_PAD_LCD_D18__GPIO_1_18
47 0x1133 /* MX28_PAD_LCD_D19__GPIO_1_19 */ 47 MX28_PAD_LCD_D19__GPIO_1_19
48 0x1143 /* MX28_PAD_LCD_D20__GPIO_1_20 */ 48 MX28_PAD_LCD_D20__GPIO_1_20
49 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */ 49 MX28_PAD_LCD_D21__GPIO_1_21
50 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ 50 MX28_PAD_LCD_D22__GPIO_1_22
51 >; 51 >;
52 fsl,drive-strength = <0>; 52 fsl,drive-strength = <MXS_DRIVE_4mA>;
53 fsl,voltage = <1>; 53 fsl,voltage = <MXS_VOLTAGE_HIGH>;
54 fsl,pull-up = <0>; 54 fsl,pull-up = <MXS_PULL_DISABLE>;
55 }; 55 };
56 56
57 lcdif_pins_apf28dev: lcdif-apf28dev@0 { 57 lcdif_pins_apf28dev: lcdif-apf28dev@0 {
58 reg = <0>; 58 reg = <0>;
59 fsl,pinmux-ids = < 59 fsl,pinmux-ids = <
60 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ 60 MX28_PAD_LCD_RD_E__LCD_VSYNC
61 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ 61 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
62 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ 62 MX28_PAD_LCD_RS__LCD_DOTCLK
63 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ 63 MX28_PAD_LCD_CS__LCD_ENABLE
64 >; 64 >;
65 fsl,drive-strength = <0>; 65 fsl,drive-strength = <MXS_DRIVE_4mA>;
66 fsl,voltage = <1>; 66 fsl,voltage = <MXS_VOLTAGE_HIGH>;
67 fsl,pull-up = <0>; 67 fsl,pull-up = <MXS_PULL_DISABLE>;
68 }; 68 };
69 }; 69 };
70 70
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index 0e7fed47bd8d..6f254ca816cb 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -1,5 +1,5 @@
1/dts-v1/; 1/dts-v1/;
2/include/ "imx28.dtsi" 2#include "imx28.dtsi"
3 3
4/ { 4/ {
5 model = "Bluegiga APX4 Development Kit"; 5 model = "Bluegiga APX4 Development Kit";
@@ -40,53 +40,53 @@
40 hog_pins_a: hog@0 { 40 hog_pins_a: hog@0 {
41 reg = <0>; 41 reg = <0>;
42 fsl,pinmux-ids = < 42 fsl,pinmux-ids = <
43 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ 43 MX28_PAD_GPMI_CE1N__GPIO_0_17
44 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */ 44 MX28_PAD_GPMI_RDY1__GPIO_0_21
45 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */ 45 MX28_PAD_SSP2_MISO__GPIO_2_18
46 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */ 46 MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */
47 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 47 MX28_PAD_PWM3__GPIO_3_28
48 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ 48 MX28_PAD_LCD_RESET__GPIO_3_30
49 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */ 49 MX28_PAD_JTAG_RTCK__GPIO_4_20
50 >; 50 >;
51 fsl,drive-strength = <0>; 51 fsl,drive-strength = <MXS_DRIVE_4mA>;
52 fsl,voltage = <1>; 52 fsl,voltage = <MXS_VOLTAGE_HIGH>;
53 fsl,pull-up = <0>; 53 fsl,pull-up = <MXS_PULL_DISABLE>;
54 }; 54 };
55 55
56 lcdif_pins_apx4: lcdif-apx4@0 { 56 lcdif_pins_apx4: lcdif-apx4@0 {
57 reg = <0>; 57 reg = <0>;
58 fsl,pinmux-ids = < 58 fsl,pinmux-ids = <
59 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ 59 MX28_PAD_LCD_RD_E__LCD_VSYNC
60 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ 60 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
61 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ 61 MX28_PAD_LCD_RS__LCD_DOTCLK
62 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ 62 MX28_PAD_LCD_CS__LCD_ENABLE
63 >; 63 >;
64 fsl,drive-strength = <0>; 64 fsl,drive-strength = <MXS_DRIVE_4mA>;
65 fsl,voltage = <1>; 65 fsl,voltage = <MXS_VOLTAGE_HIGH>;
66 fsl,pull-up = <0>; 66 fsl,pull-up = <MXS_PULL_DISABLE>;
67 }; 67 };
68 68
69 mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { 69 mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 {
70 reg = <0>; 70 reg = <0>;
71 fsl,pinmux-ids = < 71 fsl,pinmux-ids = <
72 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */ 72 MX28_PAD_SSP0_DATA4__SSP2_D0
73 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */ 73 MX28_PAD_SSP0_DATA5__SSP2_D3
74 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */ 74 MX28_PAD_SSP0_DATA6__SSP2_CMD
75 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ 75 MX28_PAD_SSP0_DATA7__SSP2_SCK
76 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */ 76 MX28_PAD_SSP2_SS1__SSP2_D1
77 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */ 77 MX28_PAD_SSP2_SS2__SSP2_D2
78 >; 78 >;
79 fsl,drive-strength = <1>; 79 fsl,drive-strength = <MXS_DRIVE_8mA>;
80 fsl,voltage = <1>; 80 fsl,voltage = <MXS_VOLTAGE_HIGH>;
81 fsl,pull-up = <1>; 81 fsl,pull-up = <MXS_PULL_ENABLE>;
82 }; 82 };
83 83
84 mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { 84 mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
85 fsl,pinmux-ids = < 85 fsl,pinmux-ids = <
86 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ 86 MX28_PAD_SSP0_DATA7__SSP2_SCK
87 >; 87 >;
88 fsl,drive-strength = <2>; 88 fsl,drive-strength = <MXS_DRIVE_12mA>;
89 fsl,pull-up = <0>; 89 fsl,pull-up = <MXS_PULL_DISABLE>;
90 }; 90 };
91 }; 91 };
92 92
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 1ec8c94bbac9..cabb6171a19d 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx28.dtsi" 13#include "imx28.dtsi"
14 14
15/ { 15/ {
16 model = "Crystalfontz CFA-10036 Board"; 16 model = "Crystalfontz CFA-10036 Board";
@@ -26,31 +26,31 @@
26 ssd1306_cfa10036: ssd1306-10036@0 { 26 ssd1306_cfa10036: ssd1306-10036@0 {
27 reg = <0>; 27 reg = <0>;
28 fsl,pinmux-ids = < 28 fsl,pinmux-ids = <
29 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */ 29 MX28_PAD_SSP0_DATA7__GPIO_2_7
30 >; 30 >;
31 fsl,drive-strength = <0>; 31 fsl,drive-strength = <MXS_DRIVE_4mA>;
32 fsl,voltage = <1>; 32 fsl,voltage = <MXS_VOLTAGE_HIGH>;
33 fsl,pull-up = <0>; 33 fsl,pull-up = <MXS_PULL_DISABLE>;
34 }; 34 };
35 35
36 led_pins_cfa10036: leds-10036@0 { 36 led_pins_cfa10036: leds-10036@0 {
37 reg = <0>; 37 reg = <0>;
38 fsl,pinmux-ids = < 38 fsl,pinmux-ids = <
39 0x3043 /* MX28_PAD_AUART1_RX__GPIO_3_4 */ 39 MX28_PAD_AUART1_RX__GPIO_3_4
40 >; 40 >;
41 fsl,drive-strength = <0>; 41 fsl,drive-strength = <MXS_DRIVE_4mA>;
42 fsl,voltage = <1>; 42 fsl,voltage = <MXS_VOLTAGE_HIGH>;
43 fsl,pull-up = <0>; 43 fsl,pull-up = <MXS_PULL_DISABLE>;
44 }; 44 };
45 45
46 usb0_otg_cfa10036: otg-10036@0 { 46 usb0_otg_cfa10036: otg-10036@0 {
47 reg = <0>; 47 reg = <0>;
48 fsl,pinmux-ids = < 48 fsl,pinmux-ids = <
49 0x0142 /* MX28_PAD_GPMI_READY0__USB0_ID */ 49 MX28_PAD_GPMI_RDY0__USB0_ID
50 >; 50 >;
51 fsl,drive-strength = <0>; 51 fsl,drive-strength = <MXS_DRIVE_4mA>;
52 fsl,voltage = <1>; 52 fsl,voltage = <MXS_VOLTAGE_HIGH>;
53 fsl,pull-up = <0>; 53 fsl,pull-up = <MXS_PULL_DISABLE>;
54 }; 54 };
55 55
56 }; 56 };
diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts
index 182b99fe35f3..f93e9a700e52 100644
--- a/arch/arm/boot/dts/imx28-cfa10037.dts
+++ b/arch/arm/boot/dts/imx28-cfa10037.dts
@@ -13,7 +13,7 @@
13 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we 13 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
14 * need to include the CFA-10036 DTS. 14 * need to include the CFA-10036 DTS.
15 */ 15 */
16/include/ "imx28-cfa10036.dts" 16#include "imx28-cfa10036.dts"
17 17
18/ { 18/ {
19 model = "Crystalfontz CFA-10037 Board"; 19 model = "Crystalfontz CFA-10037 Board";
@@ -25,21 +25,21 @@
25 usb_pins_cfa10037: usb-10037@0 { 25 usb_pins_cfa10037: usb-10037@0 {
26 reg = <0>; 26 reg = <0>;
27 fsl,pinmux-ids = < 27 fsl,pinmux-ids = <
28 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ 28 MX28_PAD_GPMI_D07__GPIO_0_7
29 >; 29 >;
30 fsl,drive-strength = <0>; 30 fsl,drive-strength = <MXS_DRIVE_4mA>;
31 fsl,voltage = <1>; 31 fsl,voltage = <MXS_VOLTAGE_HIGH>;
32 fsl,pull-up = <0>; 32 fsl,pull-up = <MXS_PULL_DISABLE>;
33 }; 33 };
34 34
35 mac0_pins_cfa10037: mac0-10037@0 { 35 mac0_pins_cfa10037: mac0-10037@0 {
36 reg = <0>; 36 reg = <0>;
37 fsl,pinmux-ids = < 37 fsl,pinmux-ids = <
38 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ 38 MX28_PAD_SSP2_SS2__GPIO_2_21
39 >; 39 >;
40 fsl,drive-strength = <0>; 40 fsl,drive-strength = <MXS_DRIVE_4mA>;
41 fsl,voltage = <1>; 41 fsl,voltage = <MXS_VOLTAGE_HIGH>;
42 fsl,pull-up = <0>; 42 fsl,pull-up = <MXS_PULL_DISABLE>;
43 }; 43 };
44 }; 44 };
45 }; 45 };
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 06e4cfaf7dd2..7087b4bf6a8f 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -13,7 +13,7 @@
13 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we 13 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
14 * need to include the CFA-10036 DTS. 14 * need to include the CFA-10036 DTS.
15 */ 15 */
16/include/ "imx28-cfa10036.dts" 16#include "imx28-cfa10036.dts"
17 17
18/ { 18/ {
19 model = "Crystalfontz CFA-10049 Board"; 19 model = "Crystalfontz CFA-10049 Board";
@@ -25,150 +25,150 @@
25 usb_pins_cfa10049: usb-10049@0 { 25 usb_pins_cfa10049: usb-10049@0 {
26 reg = <0>; 26 reg = <0>;
27 fsl,pinmux-ids = < 27 fsl,pinmux-ids = <
28 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ 28 MX28_PAD_GPMI_D07__GPIO_0_7
29 >; 29 >;
30 fsl,drive-strength = <0>; 30 fsl,drive-strength = <MXS_DRIVE_4mA>;
31 fsl,voltage = <1>; 31 fsl,voltage = <MXS_VOLTAGE_HIGH>;
32 fsl,pull-up = <0>; 32 fsl,pull-up = <MXS_PULL_DISABLE>;
33 }; 33 };
34 34
35 i2cmux_pins_cfa10049: i2cmux-10049@0 { 35 i2cmux_pins_cfa10049: i2cmux-10049@0 {
36 reg = <0>; 36 reg = <0>;
37 fsl,pinmux-ids = < 37 fsl,pinmux-ids = <
38 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ 38 MX28_PAD_LCD_D22__GPIO_1_22
39 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ 39 MX28_PAD_LCD_D23__GPIO_1_23
40 >; 40 >;
41 fsl,drive-strength = <0>; 41 fsl,drive-strength = <MXS_DRIVE_4mA>;
42 fsl,voltage = <1>; 42 fsl,voltage = <MXS_VOLTAGE_HIGH>;
43 fsl,pull-up = <0>; 43 fsl,pull-up = <MXS_PULL_DISABLE>;
44 }; 44 };
45 45
46 mac0_pins_cfa10049: mac0-10049@0 { 46 mac0_pins_cfa10049: mac0-10049@0 {
47 reg = <0>; 47 reg = <0>;
48 fsl,pinmux-ids = < 48 fsl,pinmux-ids = <
49 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ 49 MX28_PAD_SSP2_SS2__GPIO_2_21
50 >; 50 >;
51 fsl,drive-strength = <0>; 51 fsl,drive-strength = <MXS_DRIVE_4mA>;
52 fsl,voltage = <1>; 52 fsl,voltage = <MXS_VOLTAGE_HIGH>;
53 fsl,pull-up = <0>; 53 fsl,pull-up = <MXS_PULL_DISABLE>;
54 }; 54 };
55 55
56 pca_pins_cfa10049: pca-10049@0 { 56 pca_pins_cfa10049: pca-10049@0 {
57 reg = <0>; 57 reg = <0>;
58 fsl,pinmux-ids = < 58 fsl,pinmux-ids = <
59 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */ 59 MX28_PAD_SSP2_SS0__GPIO_2_19
60 >; 60 >;
61 fsl,drive-strength = <0>; 61 fsl,drive-strength = <MXS_DRIVE_4mA>;
62 fsl,voltage = <1>; 62 fsl,voltage = <MXS_VOLTAGE_HIGH>;
63 fsl,pull-up = <1>; 63 fsl,pull-up = <MXS_PULL_ENABLE>;
64 }; 64 };
65 65
66 rotary_pins_cfa10049: rotary-10049@0 { 66 rotary_pins_cfa10049: rotary-10049@0 {
67 reg = <0>; 67 reg = <0>;
68 fsl,pinmux-ids = < 68 fsl,pinmux-ids = <
69 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */ 69 MX28_PAD_I2C0_SCL__GPIO_3_24
70 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */ 70 MX28_PAD_I2C0_SDA__GPIO_3_25
71 >; 71 >;
72 fsl,drive-strength = <0>; 72 fsl,drive-strength = <MXS_DRIVE_4mA>;
73 fsl,voltage = <1>; 73 fsl,voltage = <MXS_VOLTAGE_HIGH>;
74 fsl,pull-up = <1>; 74 fsl,pull-up = <MXS_PULL_ENABLE>;
75 }; 75 };
76 76
77 rotary_btn_pins_cfa10049: rotary-btn-10049@0 { 77 rotary_btn_pins_cfa10049: rotary-btn-10049@0 {
78 reg = <0>; 78 reg = <0>;
79 fsl,pinmux-ids = < 79 fsl,pinmux-ids = <
80 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */ 80 MX28_PAD_SAIF1_SDATA0__GPIO_3_26
81 >; 81 >;
82 fsl,drive-strength = <0>; 82 fsl,drive-strength = <MXS_DRIVE_4mA>;
83 fsl,voltage = <1>; 83 fsl,voltage = <MXS_VOLTAGE_HIGH>;
84 fsl,pull-up = <1>; 84 fsl,pull-up = <MXS_PULL_ENABLE>;
85 }; 85 };
86 86
87 spi2_pins_cfa10049: spi2-cfa10049@0 { 87 spi2_pins_cfa10049: spi2-cfa10049@0 {
88 reg = <0>; 88 reg = <0>;
89 fsl,pinmux-ids = < 89 fsl,pinmux-ids = <
90 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ 90 MX28_PAD_SSP2_SCK__GPIO_2_16
91 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ 91 MX28_PAD_SSP2_MOSI__GPIO_2_17
92 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ 92 MX28_PAD_SSP2_MISO__GPIO_2_18
93 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ 93 MX28_PAD_AUART1_TX__GPIO_3_5
94 >; 94 >;
95 fsl,drive-strength = <1>; 95 fsl,drive-strength = <MXS_DRIVE_8mA>;
96 fsl,voltage = <1>; 96 fsl,voltage = <MXS_VOLTAGE_HIGH>;
97 fsl,pull-up = <1>; 97 fsl,pull-up = <MXS_PULL_ENABLE>;
98 }; 98 };
99 99
100 spi3_pins_cfa10049: spi3-cfa10049@0 { 100 spi3_pins_cfa10049: spi3-cfa10049@0 {
101 reg = <0>; 101 reg = <0>;
102 fsl,pinmux-ids = < 102 fsl,pinmux-ids = <
103 0x0183 /* MX28_PAD_GPMI_RDN__GPIO_0_24 */ 103 MX28_PAD_GPMI_RDN__GPIO_0_24
104 0x01c3 /* MX28_PAD_GPMI_RESETN__GPIO_0_28 */ 104 MX28_PAD_GPMI_RESETN__GPIO_0_28
105 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ 105 MX28_PAD_GPMI_CE1N__GPIO_0_17
106 0x01a3 /* MX28_PAD_GPMI_ALE__GPIO_0_26 */ 106 MX28_PAD_GPMI_ALE__GPIO_0_26
107 0x01b3 /* MX28_PAD_GPMI_CLE__GPIO_0_27 */ 107 MX28_PAD_GPMI_CLE__GPIO_0_27
108 >; 108 >;
109 fsl,drive-strength = <1>; 109 fsl,drive-strength = <MXS_DRIVE_8mA>;
110 fsl,voltage = <1>; 110 fsl,voltage = <MXS_VOLTAGE_HIGH>;
111 fsl,pull-up = <1>; 111 fsl,pull-up = <MXS_PULL_ENABLE>;
112 }; 112 };
113 113
114 lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { 114 lcdif_18bit_pins_cfa10049: lcdif-18bit@0 {
115 reg = <0>; 115 reg = <0>;
116 fsl,pinmux-ids = < 116 fsl,pinmux-ids = <
117 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ 117 MX28_PAD_LCD_D00__LCD_D0
118 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ 118 MX28_PAD_LCD_D01__LCD_D1
119 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ 119 MX28_PAD_LCD_D02__LCD_D2
120 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ 120 MX28_PAD_LCD_D03__LCD_D3
121 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ 121 MX28_PAD_LCD_D04__LCD_D4
122 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ 122 MX28_PAD_LCD_D05__LCD_D5
123 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ 123 MX28_PAD_LCD_D06__LCD_D6
124 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ 124 MX28_PAD_LCD_D07__LCD_D7
125 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ 125 MX28_PAD_LCD_D08__LCD_D8
126 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ 126 MX28_PAD_LCD_D09__LCD_D9
127 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ 127 MX28_PAD_LCD_D10__LCD_D10
128 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ 128 MX28_PAD_LCD_D11__LCD_D11
129 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ 129 MX28_PAD_LCD_D12__LCD_D12
130 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ 130 MX28_PAD_LCD_D13__LCD_D13
131 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ 131 MX28_PAD_LCD_D14__LCD_D14
132 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ 132 MX28_PAD_LCD_D15__LCD_D15
133 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ 133 MX28_PAD_LCD_D16__LCD_D16
134 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ 134 MX28_PAD_LCD_D17__LCD_D17
135 >; 135 >;
136 fsl,drive-strength = <0>; 136 fsl,drive-strength = <MXS_DRIVE_4mA>;
137 fsl,voltage = <1>; 137 fsl,voltage = <MXS_VOLTAGE_HIGH>;
138 fsl,pull-up = <0>; 138 fsl,pull-up = <MXS_PULL_DISABLE>;
139 }; 139 };
140 140
141 lcdif_pins_cfa10049: lcdif-evk@0 { 141 lcdif_pins_cfa10049: lcdif-evk@0 {
142 reg = <0>; 142 reg = <0>;
143 fsl,pinmux-ids = < 143 fsl,pinmux-ids = <
144 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ 144 MX28_PAD_LCD_RD_E__LCD_VSYNC
145 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ 145 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
146 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ 146 MX28_PAD_LCD_RS__LCD_DOTCLK
147 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ 147 MX28_PAD_LCD_CS__LCD_ENABLE
148 >; 148 >;
149 fsl,drive-strength = <0>; 149 fsl,drive-strength = <MXS_DRIVE_4mA>;
150 fsl,voltage = <1>; 150 fsl,voltage = <MXS_VOLTAGE_HIGH>;
151 fsl,pull-up = <0>; 151 fsl,pull-up = <MXS_PULL_DISABLE>;
152 }; 152 };
153 153
154 lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { 154 lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 {
155 reg = <0>; 155 reg = <0>;
156 fsl,pinmux-ids = < 156 fsl,pinmux-ids = <
157 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ 157 MX28_PAD_LCD_RESET__GPIO_3_30
158 >; 158 >;
159 fsl,drive-strength = <0>; 159 fsl,drive-strength = <MXS_DRIVE_4mA>;
160 fsl,voltage = <1>; 160 fsl,voltage = <MXS_VOLTAGE_HIGH>;
161 fsl,pull-up = <1>; 161 fsl,pull-up = <MXS_PULL_ENABLE>;
162 }; 162 };
163 163
164 w1_gpio_pins: w1-gpio@0 { 164 w1_gpio_pins: w1-gpio@0 {
165 reg = <0>; 165 reg = <0>;
166 fsl,pinmux-ids = < 166 fsl,pinmux-ids = <
167 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */ 167 MX28_PAD_LCD_D21__GPIO_1_21
168 >; 168 >;
169 fsl,drive-strength = <1>; 169 fsl,drive-strength = <MXS_DRIVE_8mA>;
170 fsl,voltage = <1>; 170 fsl,voltage = <MXS_VOLTAGE_HIGH>;
171 fsl,pull-up = <0>; /* 0 will enable the keeper */ 171 fsl,pull-up = <MXS_PULL_DISABLE>; /* 0 will enable the keeper */
172 }; 172 };
173 }; 173 };
174 174
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
index 171bcbe1ec4b..c3900e7ba331 100644
--- a/arch/arm/boot/dts/imx28-cfa10055.dts
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -14,7 +14,7 @@
14 * The CFA-10055 is an expansion board for the CFA-10036 module and 14 * The CFA-10055 is an expansion board for the CFA-10036 module and
15 * CFA-10037, thus we need to include the CFA-10037 DTS. 15 * CFA-10037, thus we need to include the CFA-10037 DTS.
16 */ 16 */
17/include/ "imx28-cfa10037.dts" 17#include "imx28-cfa10037.dts"
18 18
19/ { 19/ {
20 model = "Crystalfontz CFA-10055 Board"; 20 model = "Crystalfontz CFA-10055 Board";
@@ -26,64 +26,64 @@
26 spi2_pins_cfa10055: spi2-cfa10055@0 { 26 spi2_pins_cfa10055: spi2-cfa10055@0 {
27 reg = <0>; 27 reg = <0>;
28 fsl,pinmux-ids = < 28 fsl,pinmux-ids = <
29 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ 29 MX28_PAD_SSP2_SCK__GPIO_2_16
30 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ 30 MX28_PAD_SSP2_MOSI__GPIO_2_17
31 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ 31 MX28_PAD_SSP2_MISO__GPIO_2_18
32 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ 32 MX28_PAD_AUART1_TX__GPIO_3_5
33 >; 33 >;
34 fsl,drive-strength = <1>; 34 fsl,drive-strength = <MXS_DRIVE_8mA>;
35 fsl,voltage = <1>; 35 fsl,voltage = <MXS_VOLTAGE_HIGH>;
36 fsl,pull-up = <1>; 36 fsl,pull-up = <MXS_PULL_ENABLE>;
37 }; 37 };
38 38
39 lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { 39 lcdif_18bit_pins_cfa10055: lcdif-18bit@0 {
40 reg = <0>; 40 reg = <0>;
41 fsl,pinmux-ids = < 41 fsl,pinmux-ids = <
42 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ 42 MX28_PAD_LCD_D00__LCD_D0
43 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ 43 MX28_PAD_LCD_D01__LCD_D1
44 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ 44 MX28_PAD_LCD_D02__LCD_D2
45 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ 45 MX28_PAD_LCD_D03__LCD_D3
46 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ 46 MX28_PAD_LCD_D04__LCD_D4
47 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ 47 MX28_PAD_LCD_D05__LCD_D5
48 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ 48 MX28_PAD_LCD_D06__LCD_D6
49 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ 49 MX28_PAD_LCD_D07__LCD_D7
50 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ 50 MX28_PAD_LCD_D08__LCD_D8
51 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ 51 MX28_PAD_LCD_D09__LCD_D9
52 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ 52 MX28_PAD_LCD_D10__LCD_D10
53 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ 53 MX28_PAD_LCD_D11__LCD_D11
54 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ 54 MX28_PAD_LCD_D12__LCD_D12
55 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ 55 MX28_PAD_LCD_D13__LCD_D13
56 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ 56 MX28_PAD_LCD_D14__LCD_D14
57 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ 57 MX28_PAD_LCD_D15__LCD_D15
58 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ 58 MX28_PAD_LCD_D16__LCD_D16
59 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ 59 MX28_PAD_LCD_D17__LCD_D17
60 >; 60 >;
61 fsl,drive-strength = <0>; 61 fsl,drive-strength = <MXS_DRIVE_4mA>;
62 fsl,voltage = <1>; 62 fsl,voltage = <MXS_VOLTAGE_HIGH>;
63 fsl,pull-up = <0>; 63 fsl,pull-up = <MXS_PULL_DISABLE>;
64 }; 64 };
65 65
66 lcdif_pins_cfa10055: lcdif-evk@0 { 66 lcdif_pins_cfa10055: lcdif-evk@0 {
67 reg = <0>; 67 reg = <0>;
68 fsl,pinmux-ids = < 68 fsl,pinmux-ids = <
69 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ 69 MX28_PAD_LCD_RD_E__LCD_VSYNC
70 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ 70 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
71 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ 71 MX28_PAD_LCD_RS__LCD_DOTCLK
72 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ 72 MX28_PAD_LCD_CS__LCD_ENABLE
73 >; 73 >;
74 fsl,drive-strength = <0>; 74 fsl,drive-strength = <MXS_DRIVE_4mA>;
75 fsl,voltage = <1>; 75 fsl,voltage = <MXS_VOLTAGE_HIGH>;
76 fsl,pull-up = <0>; 76 fsl,pull-up = <MXS_PULL_DISABLE>;
77 }; 77 };
78 78
79 lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { 79 lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 {
80 reg = <0>; 80 reg = <0>;
81 fsl,pinmux-ids = < 81 fsl,pinmux-ids = <
82 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ 82 MX28_PAD_LCD_RESET__GPIO_3_30
83 >; 83 >;
84 fsl,drive-strength = <0>; 84 fsl,drive-strength = <MXS_DRIVE_4mA>;
85 fsl,voltage = <1>; 85 fsl,voltage = <MXS_VOLTAGE_HIGH>;
86 fsl,pull-up = <1>; 86 fsl,pull-up = <MXS_PULL_ENABLE>;
87 }; 87 };
88 }; 88 };
89 89
diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts
index b45dd0e4ee57..cef959a97219 100644
--- a/arch/arm/boot/dts/imx28-cfa10056.dts
+++ b/arch/arm/boot/dts/imx28-cfa10056.dts
@@ -13,7 +13,7 @@
13 * The CFA-10055 is an expansion board for the CFA-10036 module and 13 * The CFA-10055 is an expansion board for the CFA-10036 module and
14 * CFA-10037, thus we need to include the CFA-10037 DTS. 14 * CFA-10037, thus we need to include the CFA-10037 DTS.
15 */ 15 */
16/include/ "imx28-cfa10037.dts" 16#include "imx28-cfa10037.dts"
17 17
18/ { 18/ {
19 model = "Crystalfontz CFA-10056 Board"; 19 model = "Crystalfontz CFA-10056 Board";
@@ -25,37 +25,37 @@
25 spi2_pins_cfa10056: spi2-cfa10056@0 { 25 spi2_pins_cfa10056: spi2-cfa10056@0 {
26 reg = <0>; 26 reg = <0>;
27 fsl,pinmux-ids = < 27 fsl,pinmux-ids = <
28 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ 28 MX28_PAD_SSP2_SCK__GPIO_2_16
29 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ 29 MX28_PAD_SSP2_MOSI__GPIO_2_17
30 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ 30 MX28_PAD_SSP2_MISO__GPIO_2_18
31 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ 31 MX28_PAD_AUART1_TX__GPIO_3_5
32 >; 32 >;
33 fsl,drive-strength = <1>; 33 fsl,drive-strength = <MXS_DRIVE_8mA>;
34 fsl,voltage = <1>; 34 fsl,voltage = <MXS_VOLTAGE_HIGH>;
35 fsl,pull-up = <1>; 35 fsl,pull-up = <MXS_PULL_ENABLE>;
36 }; 36 };
37 37
38 lcdif_pins_cfa10056: lcdif-10056@0 { 38 lcdif_pins_cfa10056: lcdif-10056@0 {
39 reg = <0>; 39 reg = <0>;
40 fsl,pinmux-ids = < 40 fsl,pinmux-ids = <
41 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ 41 MX28_PAD_LCD_RD_E__LCD_VSYNC
42 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ 42 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
43 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ 43 MX28_PAD_LCD_RS__LCD_DOTCLK
44 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ 44 MX28_PAD_LCD_CS__LCD_ENABLE
45 >; 45 >;
46 fsl,drive-strength = <0>; 46 fsl,drive-strength = <MXS_DRIVE_4mA>;
47 fsl,voltage = <1>; 47 fsl,voltage = <MXS_VOLTAGE_HIGH>;
48 fsl,pull-up = <0>; 48 fsl,pull-up = <MXS_PULL_DISABLE>;
49 }; 49 };
50 50
51 lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { 51 lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 {
52 reg = <0>; 52 reg = <0>;
53 fsl,pinmux-ids = < 53 fsl,pinmux-ids = <
54 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ 54 MX28_PAD_LCD_RESET__GPIO_3_30
55 >; 55 >;
56 fsl,drive-strength = <0>; 56 fsl,drive-strength = <MXS_DRIVE_4mA>;
57 fsl,voltage = <1>; 57 fsl,voltage = <MXS_VOLTAGE_HIGH>;
58 fsl,pull-up = <1>; 58 fsl,pull-up = <MXS_PULL_ENABLE>;
59 }; 59 };
60 }; 60 };
61 61
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
index 0333c0532f28..3c1312885ae0 100644
--- a/arch/arm/boot/dts/imx28-cfa10057.dts
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -14,7 +14,7 @@
14 * The CFA-10057 is an expansion board for the CFA-10036 module, thus we 14 * The CFA-10057 is an expansion board for the CFA-10036 module, thus we
15 * need to include the CFA-10036 DTS. 15 * need to include the CFA-10036 DTS.
16 */ 16 */
17/include/ "imx28-cfa10036.dts" 17#include "imx28-cfa10036.dts"
18 18
19/ { 19/ {
20 model = "Crystalfontz CFA-10057 Board"; 20 model = "Crystalfontz CFA-10057 Board";
@@ -26,51 +26,51 @@
26 usb_pins_cfa10057: usb-10057@0 { 26 usb_pins_cfa10057: usb-10057@0 {
27 reg = <0>; 27 reg = <0>;
28 fsl,pinmux-ids = < 28 fsl,pinmux-ids = <
29 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ 29 MX28_PAD_GPMI_D07__GPIO_0_7
30 >; 30 >;
31 fsl,drive-strength = <0>; 31 fsl,drive-strength = <MXS_DRIVE_4mA>;
32 fsl,voltage = <1>; 32 fsl,voltage = <MXS_VOLTAGE_HIGH>;
33 fsl,pull-up = <0>; 33 fsl,pull-up = <MXS_PULL_DISABLE>;
34 }; 34 };
35 35
36 lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { 36 lcdif_18bit_pins_cfa10057: lcdif-18bit@0 {
37 reg = <0>; 37 reg = <0>;
38 fsl,pinmux-ids = < 38 fsl,pinmux-ids = <
39 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ 39 MX28_PAD_LCD_D00__LCD_D0
40 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ 40 MX28_PAD_LCD_D01__LCD_D1
41 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ 41 MX28_PAD_LCD_D02__LCD_D2
42 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ 42 MX28_PAD_LCD_D03__LCD_D3
43 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ 43 MX28_PAD_LCD_D04__LCD_D4
44 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ 44 MX28_PAD_LCD_D05__LCD_D5
45 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ 45 MX28_PAD_LCD_D06__LCD_D6
46 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ 46 MX28_PAD_LCD_D07__LCD_D7
47 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ 47 MX28_PAD_LCD_D08__LCD_D8
48 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ 48 MX28_PAD_LCD_D09__LCD_D9
49 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ 49 MX28_PAD_LCD_D10__LCD_D10
50 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ 50 MX28_PAD_LCD_D11__LCD_D11
51 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ 51 MX28_PAD_LCD_D12__LCD_D12
52 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ 52 MX28_PAD_LCD_D13__LCD_D13
53 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ 53 MX28_PAD_LCD_D14__LCD_D14
54 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ 54 MX28_PAD_LCD_D15__LCD_D15
55 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ 55 MX28_PAD_LCD_D16__LCD_D16
56 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ 56 MX28_PAD_LCD_D17__LCD_D17
57 >; 57 >;
58 fsl,drive-strength = <0>; 58 fsl,drive-strength = <MXS_DRIVE_4mA>;
59 fsl,voltage = <1>; 59 fsl,voltage = <MXS_VOLTAGE_HIGH>;
60 fsl,pull-up = <0>; 60 fsl,pull-up = <MXS_PULL_DISABLE>;
61 }; 61 };
62 62
63 lcdif_pins_cfa10057: lcdif-evk@0 { 63 lcdif_pins_cfa10057: lcdif-evk@0 {
64 reg = <0>; 64 reg = <0>;
65 fsl,pinmux-ids = < 65 fsl,pinmux-ids = <
66 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ 66 MX28_PAD_LCD_RD_E__LCD_VSYNC
67 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ 67 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
68 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ 68 MX28_PAD_LCD_RS__LCD_DOTCLK
69 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ 69 MX28_PAD_LCD_CS__LCD_ENABLE
70 >; 70 >;
71 fsl,drive-strength = <0>; 71 fsl,drive-strength = <MXS_DRIVE_4mA>;
72 fsl,voltage = <1>; 72 fsl,voltage = <MXS_VOLTAGE_HIGH>;
73 fsl,pull-up = <0>; 73 fsl,pull-up = <MXS_PULL_DISABLE>;
74 }; 74 };
75 }; 75 };
76 76
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts
index 64c64c55a82a..2469d34df0ae 100644
--- a/arch/arm/boot/dts/imx28-cfa10058.dts
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -14,7 +14,7 @@
14 * The CFA-10058 is an expansion board for the CFA-10036 module, thus we 14 * The CFA-10058 is an expansion board for the CFA-10036 module, thus we
15 * need to include the CFA-10036 DTS. 15 * need to include the CFA-10036 DTS.
16 */ 16 */
17/include/ "imx28-cfa10036.dts" 17#include "imx28-cfa10036.dts"
18 18
19/ { 19/ {
20 model = "Crystalfontz CFA-10058 Board"; 20 model = "Crystalfontz CFA-10058 Board";
@@ -26,24 +26,24 @@
26 usb_pins_cfa10058: usb-10058@0 { 26 usb_pins_cfa10058: usb-10058@0 {
27 reg = <0>; 27 reg = <0>;
28 fsl,pinmux-ids = < 28 fsl,pinmux-ids = <
29 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ 29 MX28_PAD_GPMI_D07__GPIO_0_7
30 >; 30 >;
31 fsl,drive-strength = <0>; 31 fsl,drive-strength = <MXS_DRIVE_4mA>;
32 fsl,voltage = <1>; 32 fsl,voltage = <MXS_VOLTAGE_HIGH>;
33 fsl,pull-up = <0>; 33 fsl,pull-up = <MXS_PULL_DISABLE>;
34 }; 34 };
35 35
36 lcdif_pins_cfa10058: lcdif-10058@0 { 36 lcdif_pins_cfa10058: lcdif-10058@0 {
37 reg = <0>; 37 reg = <0>;
38 fsl,pinmux-ids = < 38 fsl,pinmux-ids = <
39 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ 39 MX28_PAD_LCD_RD_E__LCD_VSYNC
40 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ 40 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
41 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ 41 MX28_PAD_LCD_RS__LCD_DOTCLK
42 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ 42 MX28_PAD_LCD_CS__LCD_ENABLE
43 >; 43 >;
44 fsl,drive-strength = <0>; 44 fsl,drive-strength = <MXS_DRIVE_4mA>;
45 fsl,voltage = <1>; 45 fsl,voltage = <MXS_VOLTAGE_HIGH>;
46 fsl,pull-up = <0>; 46 fsl,pull-up = <MXS_PULL_DISABLE>;
47 }; 47 };
48 }; 48 };
49 49
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index aa33393903a8..4267c2b05d60 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx28.dtsi" 13#include "imx28.dtsi"
14 14
15/ { 15/ {
16 model = "Freescale i.MX28 Evaluation Kit"; 16 model = "Freescale i.MX28 Evaluation Kit";
@@ -70,52 +70,52 @@
70 hog_pins_a: hog@0 { 70 hog_pins_a: hog@0 {
71 reg = <0>; 71 reg = <0>;
72 fsl,pinmux-ids = < 72 fsl,pinmux-ids = <
73 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ 73 MX28_PAD_SSP1_CMD__GPIO_2_13
74 0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */ 74 MX28_PAD_SSP1_DATA3__GPIO_2_15
75 0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */ 75 MX28_PAD_ENET0_RX_CLK__GPIO_4_13
76 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */ 76 MX28_PAD_SSP1_SCK__GPIO_2_12
77 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 77 MX28_PAD_PWM3__GPIO_3_28
78 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ 78 MX28_PAD_LCD_RESET__GPIO_3_30
79 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */ 79 MX28_PAD_AUART2_RX__GPIO_3_8
80 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */ 80 MX28_PAD_AUART2_TX__GPIO_3_9
81 >; 81 >;
82 fsl,drive-strength = <0>; 82 fsl,drive-strength = <MXS_DRIVE_4mA>;
83 fsl,voltage = <1>; 83 fsl,voltage = <MXS_VOLTAGE_HIGH>;
84 fsl,pull-up = <0>; 84 fsl,pull-up = <MXS_PULL_DISABLE>;
85 }; 85 };
86 86
87 led_pin_gpio3_5: led_gpio3_5@0 { 87 led_pin_gpio3_5: led_gpio3_5@0 {
88 reg = <0>; 88 reg = <0>;
89 fsl,pinmux-ids = < 89 fsl,pinmux-ids = <
90 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ 90 MX28_PAD_AUART1_TX__GPIO_3_5
91 >; 91 >;
92 fsl,drive-strength = <0>; 92 fsl,drive-strength = <MXS_DRIVE_4mA>;
93 fsl,voltage = <1>; 93 fsl,voltage = <MXS_VOLTAGE_HIGH>;
94 fsl,pull-up = <0>; 94 fsl,pull-up = <MXS_PULL_DISABLE>;
95 }; 95 };
96 96
97 gpmi_pins_evk: gpmi-nand-evk@0 { 97 gpmi_pins_evk: gpmi-nand-evk@0 {
98 reg = <0>; 98 reg = <0>;
99 fsl,pinmux-ids = < 99 fsl,pinmux-ids = <
100 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */ 100 MX28_PAD_GPMI_CE1N__GPMI_CE1N
101 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */ 101 MX28_PAD_GPMI_RDY1__GPMI_READY1
102 >; 102 >;
103 fsl,drive-strength = <0>; 103 fsl,drive-strength = <MXS_DRIVE_4mA>;
104 fsl,voltage = <1>; 104 fsl,voltage = <MXS_VOLTAGE_HIGH>;
105 fsl,pull-up = <0>; 105 fsl,pull-up = <MXS_PULL_DISABLE>;
106 }; 106 };
107 107
108 lcdif_pins_evk: lcdif-evk@0 { 108 lcdif_pins_evk: lcdif-evk@0 {
109 reg = <0>; 109 reg = <0>;
110 fsl,pinmux-ids = < 110 fsl,pinmux-ids = <
111 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ 111 MX28_PAD_LCD_RD_E__LCD_VSYNC
112 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ 112 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
113 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ 113 MX28_PAD_LCD_RS__LCD_DOTCLK
114 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ 114 MX28_PAD_LCD_CS__LCD_ENABLE
115 >; 115 >;
116 fsl,drive-strength = <0>; 116 fsl,drive-strength = <MXS_DRIVE_4mA>;
117 fsl,voltage = <1>; 117 fsl,voltage = <MXS_VOLTAGE_HIGH>;
118 fsl,pull-up = <0>; 118 fsl,pull-up = <MXS_PULL_DISABLE>;
119 }; 119 };
120 }; 120 };
121 121
@@ -182,6 +182,7 @@
182 }; 182 };
183 183
184 lradc@80050000 { 184 lradc@80050000 {
185 fsl,lradc-touchscreen-wires = <4>;
185 status = "okay"; 186 status = "okay";
186 fsl,lradc-touchscreen-wires = <4>; 187 fsl,lradc-touchscreen-wires = <4>;
187 fsl,ave-ctrl = <4>; 188 fsl,ave-ctrl = <4>;
@@ -246,6 +247,8 @@
246 247
247 ahb@80080000 { 248 ahb@80080000 {
248 usb0: usb@80080000 { 249 usb0: usb@80080000 {
250 pinctrl-names = "default";
251 pinctrl-0 = <&usb0_id_pins_a>;
249 vbus-supply = <&reg_usb0_vbus>; 252 vbus-supply = <&reg_usb0_vbus>;
250 status = "okay"; 253 status = "okay";
251 }; 254 };
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
new file mode 100644
index 000000000000..d3958da60bd7
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -0,0 +1,266 @@
1/*
2 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx28.dtsi"
14
15/ {
16 model = "MSR M28CU3";
17 compatible = "msr,m28cu3", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 #address-cells = <1>;
27 #size-cells = <1>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
30 status = "okay";
31
32 partition@0 {
33 label = "gpmi-nfc-0-boot";
34 reg = <0x00000000 0x01400000>;
35 read-only;
36 };
37
38 partition@1 {
39 label = "gpmi-nfc-general-use";
40 reg = <0x01400000 0x0ec00000>;
41 };
42 };
43
44 ssp0: ssp@80010000 {
45 compatible = "fsl,imx28-mmc";
46 pinctrl-names = "default";
47 pinctrl-0 = <&mmc0_4bit_pins_a
48 &mmc0_cd_cfg
49 &mmc0_sck_cfg>;
50 bus-width = <4>;
51 vmmc-supply = <&reg_vddio_sd0>;
52 status = "okay";
53 };
54
55 ssp2: ssp@80014000 {
56 compatible = "fsl,imx28-mmc";
57 pinctrl-names = "default";
58 pinctrl-0 = <&mmc2_4bit_pins_a
59 &mmc2_cd_cfg
60 &mmc2_sck_cfg>;
61 bus-width = <4>;
62 vmmc-supply = <&reg_vddio_sd1>;
63 status = "okay";
64 };
65
66 pinctrl@80018000 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&hog_pins_a>;
69
70 hog_pins_a: hog@0 {
71 reg = <0>;
72 fsl,pinmux-ids = <
73 MX28_PAD_SSP2_SS0__GPIO_2_19
74 MX28_PAD_PWM4__GPIO_3_29
75 MX28_PAD_AUART2_RX__GPIO_3_8
76 MX28_PAD_ENET0_RX_CLK__GPIO_4_13
77 >;
78 fsl,drive-strength = <MXS_DRIVE_4mA>;
79 fsl,voltage = <MXS_VOLTAGE_HIGH>;
80 fsl,pull-up = <MXS_PULL_DISABLE>;
81 };
82
83 lcdif_pins_m28: lcdif-m28@0 {
84 reg = <0>;
85 fsl,pinmux-ids = <
86 MX28_PAD_LCD_VSYNC__LCD_VSYNC
87 MX28_PAD_LCD_HSYNC__LCD_HSYNC
88 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
89 MX28_PAD_LCD_RESET__LCD_RESET
90 MX28_PAD_LCD_CS__LCD_ENABLE
91 MX28_PAD_AUART1_TX__GPIO_3_5
92 >;
93 fsl,drive-strength = <MXS_DRIVE_4mA>;
94 fsl,voltage = <MXS_VOLTAGE_HIGH>;
95 fsl,pull-up = <MXS_PULL_DISABLE>;
96 };
97
98 led_pins_gpio: leds-m28@0 {
99 reg = <0>;
100 fsl,pinmux-ids = <
101 MX28_PAD_SSP3_MISO__GPIO_2_26
102 MX28_PAD_SSP3_SCK__GPIO_2_24
103 >;
104 fsl,drive-strength = <MXS_DRIVE_4mA>;
105 fsl,voltage = <MXS_VOLTAGE_HIGH>;
106 fsl,pull-up = <MXS_PULL_DISABLE>;
107 };
108 };
109
110 ocotp@8002c000 {
111 status = "okay";
112 };
113
114 lcdif@80030000 {
115 pinctrl-names = "default";
116 pinctrl-0 = <&lcdif_24bit_pins_a
117 &lcdif_pins_m28>;
118 display = <&display>;
119 reset-active-high;
120 status = "okay";
121
122 display: display0 {
123 bits-per-pixel = <32>;
124 bus-width = <24>;
125
126 display-timings {
127 native-mode = <&timing0>;
128 timing0: timing0 {
129 clock-frequency = <6410256>;
130 hactive = <320>;
131 vactive = <240>;
132 hback-porch = <38>;
133 hfront-porch = <20>;
134 vback-porch = <15>;
135 vfront-porch = <5>;
136 hsync-len = <30>;
137 vsync-len = <3>;
138 hsync-active = <0>;
139 vsync-active = <0>;
140 de-active = <1>;
141 pixelclk-active = <1>;
142 };
143 };
144 };
145 };
146 };
147
148 apbx@80040000 {
149 duart: serial@80074000 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&duart_pins_b>;
152 status = "okay";
153 };
154
155 usbphy1: usbphy@8007e000 {
156 status = "okay";
157 };
158
159 auart0: serial@8006a000 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&auart0_2pins_a>;
162 status = "okay";
163 };
164
165 auart3: serial@80070000 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&auart3_2pins_b>;
168 status = "okay";
169 };
170
171 pwm: pwm@80064000 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pwm3_pins_a>;
174 status = "okay";
175 };
176 };
177 };
178
179 ahb@80080000 {
180 usb1: usb@80090000 {
181 vbus-supply = <&reg_usb1_vbus>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&usbphy1_pins_a>;
184 disable-over-current;
185 status = "okay";
186 };
187
188 mac0: ethernet@800f0000 {
189 phy-mode = "rmii";
190 pinctrl-names = "default";
191 pinctrl-0 = <&mac0_pins_a>;
192 phy-reset-gpios = <&gpio4 13 0>;
193 phy-reset-duration = <100>;
194 status = "okay";
195 };
196
197 mac1: ethernet@800f4000 {
198 phy-mode = "rmii";
199 pinctrl-names = "default";
200 pinctrl-0 = <&mac1_pins_a>;
201 status = "okay";
202 };
203 };
204
205 backlight {
206 compatible = "pwm-backlight";
207 pwms = <&pwm 3 5000000>;
208 brightness-levels = <0 4 8 16 32 64 128 255>;
209 default-brightness-level = <6>;
210 };
211
212 leds {
213 compatible = "gpio-leds";
214 pinctrl-names = "default";
215 pinctrl-0 = <&led_pins_gpio>;
216
217 user1 {
218 label = "sd0-led";
219 gpios = <&gpio2 26 0>;
220 linux,default-trigger = "mmc0";
221 };
222
223 user2 {
224 label = "sd1-led";
225 gpios = <&gpio2 24 0>;
226 linux,default-trigger = "mmc2";
227 };
228 };
229
230 regulators {
231 compatible = "simple-bus";
232
233 reg_3p3v: 3p3v {
234 compatible = "regulator-fixed";
235 regulator-name = "3P3V";
236 regulator-min-microvolt = <3300000>;
237 regulator-max-microvolt = <3300000>;
238 regulator-always-on;
239 };
240
241 reg_vddio_sd0: vddio-sd0 {
242 compatible = "regulator-fixed";
243 regulator-name = "vddio-sd0";
244 regulator-min-microvolt = <3300000>;
245 regulator-max-microvolt = <3300000>;
246 gpio = <&gpio3 29 0>;
247 };
248
249 reg_vddio_sd1: vddio-sd1 {
250 compatible = "regulator-fixed";
251 regulator-name = "vddio-sd1";
252 regulator-min-microvolt = <3300000>;
253 regulator-max-microvolt = <3300000>;
254 gpio = <&gpio2 19 0>;
255 };
256
257 reg_usb1_vbus: usb1_vbus {
258 compatible = "regulator-fixed";
259 regulator-name = "usb1_vbus";
260 regulator-min-microvolt = <5000000>;
261 regulator-max-microvolt = <5000000>;
262 gpio = <&gpio3 8 0>;
263 enable-active-high;
264 };
265 };
266};
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 0d322a2bebaf..8e2477fbe1d7 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx28.dtsi" 13#include "imx28.dtsi"
14 14
15/ { 15/ {
16 model = "DENX M28EVK"; 16 model = "DENX M28EVK";
@@ -92,26 +92,26 @@
92 hog_pins_a: hog@0 { 92 hog_pins_a: hog@0 {
93 reg = <0>; 93 reg = <0>;
94 fsl,pinmux-ids = < 94 fsl,pinmux-ids = <
95 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ 95 MX28_PAD_PWM3__GPIO_3_28
96 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ 96 MX28_PAD_AUART2_CTS__GPIO_3_10
97 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ 97 MX28_PAD_AUART2_RTS__GPIO_3_11
98 0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */ 98 MX28_PAD_AUART3_RX__GPIO_3_12
99 0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */ 99 MX28_PAD_AUART3_TX__GPIO_3_13
100 >; 100 >;
101 fsl,drive-strength = <0>; 101 fsl,drive-strength = <MXS_DRIVE_4mA>;
102 fsl,voltage = <1>; 102 fsl,voltage = <MXS_VOLTAGE_HIGH>;
103 fsl,pull-up = <0>; 103 fsl,pull-up = <MXS_PULL_DISABLE>;
104 }; 104 };
105 105
106 lcdif_pins_m28: lcdif-m28@0 { 106 lcdif_pins_m28: lcdif-m28@0 {
107 reg = <0>; 107 reg = <0>;
108 fsl,pinmux-ids = < 108 fsl,pinmux-ids = <
109 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */ 109 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
110 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */ 110 MX28_PAD_LCD_ENABLE__LCD_ENABLE
111 >; 111 >;
112 fsl,drive-strength = <0>; 112 fsl,drive-strength = <MXS_DRIVE_4mA>;
113 fsl,voltage = <1>; 113 fsl,voltage = <MXS_VOLTAGE_HIGH>;
114 fsl,pull-up = <0>; 114 fsl,pull-up = <MXS_PULL_DISABLE>;
115 }; 115 };
116 }; 116 };
117 117
diff --git a/arch/arm/boot/dts/imx28-pinfunc.h b/arch/arm/boot/dts/imx28-pinfunc.h
new file mode 100644
index 000000000000..e11f69ba0fe4
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-pinfunc.h
@@ -0,0 +1,506 @@
1/*
2 * Header providing constants for i.MX28 pinctrl bindings.
3 *
4 * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __DT_BINDINGS_MX28_PINCTRL_H__
15#define __DT_BINDINGS_MX28_PINCTRL_H__
16
17#include "mxs-pinfunc.h"
18
19#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
20#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
21#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
22#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
23#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
24#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
25#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
26#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
27#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
28#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
29#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
30#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
31#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
32#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
33#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
34#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
35#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
36#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
37#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
38#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
39#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
40#define MX28_PAD_LCD_D00__LCD_D0 0x1000
41#define MX28_PAD_LCD_D01__LCD_D1 0x1010
42#define MX28_PAD_LCD_D02__LCD_D2 0x1020
43#define MX28_PAD_LCD_D03__LCD_D3 0x1030
44#define MX28_PAD_LCD_D04__LCD_D4 0x1040
45#define MX28_PAD_LCD_D05__LCD_D5 0x1050
46#define MX28_PAD_LCD_D06__LCD_D6 0x1060
47#define MX28_PAD_LCD_D07__LCD_D7 0x1070
48#define MX28_PAD_LCD_D08__LCD_D8 0x1080
49#define MX28_PAD_LCD_D09__LCD_D9 0x1090
50#define MX28_PAD_LCD_D10__LCD_D10 0x10a0
51#define MX28_PAD_LCD_D11__LCD_D11 0x10b0
52#define MX28_PAD_LCD_D12__LCD_D12 0x10c0
53#define MX28_PAD_LCD_D13__LCD_D13 0x10d0
54#define MX28_PAD_LCD_D14__LCD_D14 0x10e0
55#define MX28_PAD_LCD_D15__LCD_D15 0x10f0
56#define MX28_PAD_LCD_D16__LCD_D16 0x1100
57#define MX28_PAD_LCD_D17__LCD_D17 0x1110
58#define MX28_PAD_LCD_D18__LCD_D18 0x1120
59#define MX28_PAD_LCD_D19__LCD_D19 0x1130
60#define MX28_PAD_LCD_D20__LCD_D20 0x1140
61#define MX28_PAD_LCD_D21__LCD_D21 0x1150
62#define MX28_PAD_LCD_D22__LCD_D22 0x1160
63#define MX28_PAD_LCD_D23__LCD_D23 0x1170
64#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
65#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
66#define MX28_PAD_LCD_RS__LCD_RS 0x11a0
67#define MX28_PAD_LCD_CS__LCD_CS 0x11b0
68#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
69#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
70#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
71#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
72#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
73#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
74#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
75#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
76#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
77#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
78#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
79#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
80#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
81#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
82#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
83#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
84#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
85#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
86#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
87#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
88#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
89#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
90#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
91#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
92#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
93#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
94#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
95#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
96#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
97#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000
98#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010
99#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
100#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
101#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040
102#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050
103#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
104#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
105#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080
106#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090
107#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
108#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
109#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
110#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
111#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
112#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
113#define MX28_PAD_PWM0__PWM_0 0x3100
114#define MX28_PAD_PWM1__PWM_1 0x3110
115#define MX28_PAD_PWM2__PWM_2 0x3120
116#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
117#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
118#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
119#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
120#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
121#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
122#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
123#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0
124#define MX28_PAD_PWM3__PWM_3 0x31c0
125#define MX28_PAD_PWM4__PWM_4 0x31d0
126#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
127#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
128#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
129#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
130#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
131#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
132#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
133#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
134#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
135#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
136#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
137#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
138#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
139#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
140#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
141#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
142#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
143#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
144#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
145#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000
146#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010
147#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020
148#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030
149#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040
150#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050
151#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060
152#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070
153#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080
154#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090
155#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
156#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
157#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
158#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
159#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
160#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
161#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
162#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
163#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
164#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
165#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
166#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150
167#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
168#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
169#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
170#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
171#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
172#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
173#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
174#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
175#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
176#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
177#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
178#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
179#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
180#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
181#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
182#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
183#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
184#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
185#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100
186#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110
187#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120
188#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130
189#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140
190#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150
191#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
192#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
193#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180
194#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001
195#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011
196#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021
197#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031
198#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041
199#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051
200#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061
201#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071
202#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
203#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
204#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
205#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
206#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
207#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
208#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
209#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
210#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
211#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
212#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
213#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
214#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
215#define MX28_PAD_LCD_D03__ETM_DA8 0x1031
216#define MX28_PAD_LCD_D04__ETM_DA9 0x1041
217#define MX28_PAD_LCD_D08__ETM_DA3 0x1081
218#define MX28_PAD_LCD_D09__ETM_DA4 0x1091
219#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
220#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
221#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
222#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
223#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
224#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
225#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
226#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
227#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
228#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
229#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
230#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
231#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
232#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
233#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
234#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
235#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
236#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
237#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
238#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
239#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
240#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
241#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
242#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
243#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
244#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
245#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
246#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
247#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
248#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
249#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
250#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
251#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
252#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
253#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
254#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
255#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071
256#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081
257#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091
258#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
259#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
260#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
261#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
262#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
263#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
264#define MX28_PAD_PWM0__I2C1_SCL 0x3101
265#define MX28_PAD_PWM1__I2C1_SDA 0x3111
266#define MX28_PAD_PWM2__USB0_ID 0x3121
267#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
268#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
269#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
270#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
271#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
272#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
273#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
274#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
275#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
276#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
277#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
278#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
279#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
280#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
281#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
282#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
283#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
284#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
285#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
286#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
287#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
288#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
289#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
290#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
291#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
292#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
293#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
294#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
295#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
296#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
297#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
298#define MX28_PAD_LCD_D00__ETM_DA0 0x1002
299#define MX28_PAD_LCD_D01__ETM_DA1 0x1012
300#define MX28_PAD_LCD_D02__ETM_DA2 0x1022
301#define MX28_PAD_LCD_D03__ETM_DA3 0x1032
302#define MX28_PAD_LCD_D04__ETM_DA4 0x1042
303#define MX28_PAD_LCD_D05__ETM_DA5 0x1052
304#define MX28_PAD_LCD_D06__ETM_DA6 0x1062
305#define MX28_PAD_LCD_D07__ETM_DA7 0x1072
306#define MX28_PAD_LCD_D08__ETM_DA8 0x1082
307#define MX28_PAD_LCD_D09__ETM_DA9 0x1092
308#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2
309#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2
310#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2
311#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2
312#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2
313#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2
314#define MX28_PAD_LCD_D16__ETM_DA7 0x1102
315#define MX28_PAD_LCD_D17__ETM_DA6 0x1112
316#define MX28_PAD_LCD_D18__ETM_DA5 0x1122
317#define MX28_PAD_LCD_D19__ETM_DA4 0x1132
318#define MX28_PAD_LCD_D20__ETM_DA3 0x1142
319#define MX28_PAD_LCD_D21__ETM_DA2 0x1152
320#define MX28_PAD_LCD_D22__ETM_DA1 0x1162
321#define MX28_PAD_LCD_D23__ETM_DA0 0x1172
322#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
323#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
324#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
325#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
326#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
327#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
328#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
329#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
330#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
331#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
332#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
333#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
334#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
335#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
336#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
337#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
338#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
339#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
340#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002
341#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012
342#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022
343#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032
344#define MX28_PAD_AUART1_RX__PWM_0 0x3042
345#define MX28_PAD_AUART1_TX__PWM_1 0x3052
346#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
347#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
348#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082
349#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092
350#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
351#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
352#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
353#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
354#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
355#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
356#define MX28_PAD_PWM0__DUART_RX 0x3102
357#define MX28_PAD_PWM1__DUART_TX 0x3112
358#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
359#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
360#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
361#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
362#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
363#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182
364#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192
365#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
366#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
367#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
368#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
369#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
370#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
371#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
372#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
373#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
374#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
375#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
376#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
377#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
378#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
379#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
380#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
381#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
382#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
383#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
384#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
385#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
386#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
387#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
388#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
389#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
390#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
391#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
392#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
393#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
394#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
395#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
396#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
397#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
398#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
399#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
400#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003
401#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013
402#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023
403#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033
404#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043
405#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053
406#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063
407#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073
408#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083
409#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093
410#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
411#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
412#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
413#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
414#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
415#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
416#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103
417#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113
418#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123
419#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133
420#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143
421#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153
422#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163
423#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173
424#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
425#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
426#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
427#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
428#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
429#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
430#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
431#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
432#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
433#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
434#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
435#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
436#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
437#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
438#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
439#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
440#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
441#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
442#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
443#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
444#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
445#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
446#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
447#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
448#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
449#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
450#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
451#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
452#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
453#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
454#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
455#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
456#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
457#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
458#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
459#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
460#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
461#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
462#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
463#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
464#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
465#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
466#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
467#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
468#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
469#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
470#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
471#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
472#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
473#define MX28_PAD_PWM0__GPIO_3_16 0x3103
474#define MX28_PAD_PWM1__GPIO_3_17 0x3113
475#define MX28_PAD_PWM2__GPIO_3_18 0x3123
476#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
477#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
478#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
479#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
480#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
481#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
482#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
483#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3
484#define MX28_PAD_PWM3__GPIO_3_28 0x31c3
485#define MX28_PAD_PWM4__GPIO_3_29 0x31d3
486#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
487#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
488#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
489#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
490#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
491#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
492#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
493#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
494#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
495#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
496#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
497#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
498#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
499#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
500#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
501#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
502#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
503#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
504#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
505
506#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 6c6a5442800a..4870f07bf56a 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "imx28.dtsi" 13#include "imx28.dtsi"
14 14
15/ { 15/ {
16 model = "SchulerControl GmbH, SC SPS 1"; 16 model = "SchulerControl GmbH, SC SPS 1";
@@ -29,13 +29,13 @@
29 hog_pins_a: hog-gpios@0 { 29 hog_pins_a: hog-gpios@0 {
30 reg = <0>; 30 reg = <0>;
31 fsl,pinmux-ids = < 31 fsl,pinmux-ids = <
32 0x0003 /* MX28_PAD_GPMI_D00__GPIO_0_0 */ 32 MX28_PAD_GPMI_D00__GPIO_0_0
33 0x0033 /* MX28_PAD_GPMI_D03__GPIO_0_3 */ 33 MX28_PAD_GPMI_D03__GPIO_0_3
34 0x0063 /* MX28_PAD_GPMI_D06__GPIO_0_6 */ 34 MX28_PAD_GPMI_D06__GPIO_0_6
35 >; 35 >;
36 fsl,drive-strength = <0>; 36 fsl,drive-strength = <MXS_DRIVE_4mA>;
37 fsl,voltage = <1>; 37 fsl,voltage = <MXS_VOLTAGE_HIGH>;
38 fsl,pull-up = <0>; 38 fsl,pull-up = <MXS_PULL_DISABLE>;
39 }; 39 };
40 40
41 }; 41 };
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 37be532f0055..be5a0550d58c 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -1,106 +1,139 @@
1/*
2 * Copyright 2012 Shawn Guo <shawn.guo@linaro.org>
3 * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
1/dts-v1/; 13/dts-v1/;
2/include/ "imx28.dtsi" 14#include "imx28.dtsi"
15#include <dt-bindings/gpio/gpio.h>
3 16
4/ { 17/ {
5 model = "Ka-Ro electronics TX28 module"; 18 model = "Ka-Ro electronics TX28 module";
6 compatible = "karo,tx28", "fsl,imx28"; 19 compatible = "karo,tx28", "fsl,imx28";
7 20
21 aliases {
22 can0 = &can0;
23 can1 = &can1;
24 display = &display;
25 ds1339 = &ds1339;
26 gpio5 = &gpio5;
27 lcdif = &lcdif;
28 lcdif_23bit_pins = &tx28_lcdif_23bit_pins;
29 lcdif_24bit_pins = &lcdif_24bit_pins_a;
30 stk5led = &user_led;
31 usbotg = &usb0;
32 };
33
8 memory { 34 memory {
9 reg = <0x40000000 0x08000000>; 35 reg = <0 0>; /* will be filled in by U-Boot */
10 }; 36 };
11
12 apb@80000000 {
13 apbh@80000000 {
14 ssp0: ssp@80010000 {
15 compatible = "fsl,imx28-mmc";
16 pinctrl-names = "default";
17 pinctrl-0 = <&mmc0_4bit_pins_a
18 &mmc0_cd_cfg
19 &mmc0_sck_cfg>;
20 bus-width = <4>;
21 status = "okay";
22 };
23 37
24 pinctrl@80018000 { 38 onewire {
25 pinctrl-names = "default"; 39 compatible = "w1-gpio";
26 pinctrl-0 = <&hog_pins_a>; 40 gpios = <&gpio2 7 0>;
27 41 status = "disabled";
28 hog_pins_a: hog@0 { 42 };
29 reg = <0>; 43
30 fsl,pinmux-ids = < 44 regulators {
31 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ 45 compatible = "simple-bus";
32 >; 46
33 fsl,drive-strength = <0>; 47 reg_usb0_vbus: usb0_vbus {
34 fsl,voltage = <1>; 48 compatible = "regulator-fixed";
35 fsl,pull-up = <0>; 49 regulator-name = "usb0_vbus";
36 }; 50 regulator-min-microvolt = <5000000>;
37 51 regulator-max-microvolt = <5000000>;
38 mac0_pins_gpio: mac0-gpio-mode@0 { 52 gpio = <&gpio0 18 0>;
39 reg = <0>; 53 enable-active-high;
40 fsl,pinmux-ids = <
41 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
42 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
43 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
44 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
45 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
46 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
47 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
48 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
49 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
50 >;
51 fsl,drive-strength = <0>;
52 fsl,voltage = <1>;
53 fsl,pull-up = <0>;
54 };
55 };
56 }; 54 };
57 55
58 apbx@80040000 { 56 reg_usb1_vbus: usb1_vbus {
59 i2c0: i2c@80058000 { 57 compatible = "regulator-fixed";
60 pinctrl-names = "default"; 58 regulator-name = "usb1_vbus";
61 pinctrl-0 = <&i2c0_pins_a>; 59 regulator-min-microvolt = <5000000>;
62 status = "okay"; 60 regulator-max-microvolt = <5000000>;
61 gpio = <&gpio3 27 0>;
62 enable-active-high;
63 };
63 64
64 ds1339: rtc@68 { 65 reg_2p5v: 2p5v {
65 compatible = "mxim,ds1339"; 66 compatible = "regulator-fixed";
66 reg = <0x68>; 67 regulator-name = "2P5V";
67 }; 68 regulator-min-microvolt = <2500000>;
68 }; 69 regulator-max-microvolt = <2500000>;
70 regulator-always-on;
71 };
69 72
70 pwm: pwm@80064000 { 73 reg_3p3v: 3p3v {
71 pinctrl-names = "default"; 74 compatible = "regulator-fixed";
72 pinctrl-0 = <&pwm0_pins_a>; 75 regulator-name = "3P3V";
73 status = "okay"; 76 regulator-min-microvolt = <3300000>;
74 }; 77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 };
75 80
76 duart: serial@80074000 { 81 reg_can_xcvr: can-xcvr {
77 pinctrl-names = "default"; 82 compatible = "regulator-fixed";
78 pinctrl-0 = <&duart_4pins_a>; 83 regulator-name = "CAN XCVR";
79 status = "okay"; 84 regulator-min-microvolt = <3300000>;
80 }; 85 regulator-max-microvolt = <3300000>;
86 gpio = <&gpio1 0 0>;
87 enable-active-low;
88 pinctrl-names = "default";
89 pinctrl-0 = <&tx28_flexcan_xcvr_pins>;
90 };
81 91
82 auart1: serial@8006c000 { 92 reg_lcd: lcd-power {
83 pinctrl-names = "default"; 93 compatible = "regulator-fixed";
84 pinctrl-0 = <&auart1_pins_a>; 94 regulator-name = "LCD POWER";
85 status = "okay"; 95 regulator-min-microvolt = <3300000>;
86 }; 96 regulator-max-microvolt = <3300000>;
97 gpio = <&gpio1 31 0>;
98 enable-active-high;
99 };
100
101 reg_lcd_reset: lcd-reset {
102 compatible = "regulator-fixed";
103 regulator-name = "LCD RESET";
104 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <3300000>;
106 gpio = <&gpio3 30 0>;
107 startup-delay-us = <300000>;
108 enable-active-high;
109 regulator-always-on;
110 regulator-boot-on;
87 }; 111 };
88 }; 112 };
89 113
90 ahb@80080000 { 114 clocks {
91 mac0: ethernet@800f0000 { 115 #address-cells = <1>;
92 phy-mode = "rmii"; 116 #size-cells = <0>;
93 pinctrl-names = "default", "gpio_mode"; 117 mclk: clock@0 {
94 pinctrl-0 = <&mac0_pins_a>; 118 compatible = "fixed-clock";
95 pinctrl-1 = <&mac0_pins_gpio>; 119 reg = <0>;
96 status = "okay"; 120 #clock-cells = <0>;
121 clock-frequency = <27000000>;
97 }; 122 };
98 }; 123 };
99 124
125 sound {
126 compatible = "fsl,imx28-tx28-sgtl5000",
127 "fsl,mxs-audio-sgtl5000";
128 model = "imx28-tx28-sgtl5000";
129 saif-controllers = <&saif0 &saif1>;
130 audio-codec = <&sgtl5000>;
131 };
132
100 leds { 133 leds {
101 compatible = "gpio-leds"; 134 compatible = "gpio-leds";
102 135
103 user { 136 user_led: user {
104 label = "Heartbeat"; 137 label = "Heartbeat";
105 gpios = <&gpio4 10 0>; 138 gpios = <&gpio4 10 0>;
106 linux,default-trigger = "heartbeat"; 139 linux,default-trigger = "heartbeat";
@@ -109,8 +142,512 @@
109 142
110 backlight { 143 backlight {
111 compatible = "pwm-backlight"; 144 compatible = "pwm-backlight";
112 pwms = <&pwm 0 5000000>; 145 pwms = <&pwm 0 500000>;
113 brightness-levels = <0 4 8 16 32 64 128 255>; 146 /*
114 default-brightness-level = <6>; 147 * a silly way to create a 1:1 relationship between the
148 * PWM value and the actual duty cycle
149 */
150 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
151 10 11 12 13 14 15 16 17 18 19
152 20 21 22 23 24 25 26 27 28 29
153 30 31 32 33 34 35 36 37 38 39
154 40 41 42 43 44 45 46 47 48 49
155 50 51 52 53 54 55 56 57 58 59
156 60 61 62 63 64 65 66 67 68 69
157 70 71 72 73 74 75 76 77 78 79
158 80 81 82 83 84 85 86 87 88 89
159 90 91 92 93 94 95 96 97 98 99
160 100>;
161 default-brightness-level = <50>;
162 };
163
164 matrix_keypad: matrix-keypad@0 {
165 compatible = "gpio-matrix-keypad";
166 col-gpios = <
167 &gpio5 0 0
168 &gpio5 1 0
169 &gpio5 2 0
170 &gpio5 3 0
171 >;
172 row-gpios = <
173 &gpio5 4 0
174 &gpio5 5 0
175 &gpio5 6 0
176 &gpio5 7 0
177 >;
178 /* sample keymap */
179 linux,keymap = <
180 0x00000074 /* row 0, col 0, KEY_POWER */
181 0x00010052 /* row 0, col 1, KEY_KP0 */
182 0x0002004f /* row 0, col 2, KEY_KP1 */
183 0x00030050 /* row 0, col 3, KEY_KP2 */
184 0x01000051 /* row 1, col 0, KEY_KP3 */
185 0x0101004b /* row 1, col 1, KEY_KP4 */
186 0x0102004c /* row 1, col 2, KEY_KP5 */
187 0x0103004d /* row 1, col 3, KEY_KP6 */
188 0x02000047 /* row 2, col 0, KEY_KP7 */
189 0x02010048 /* row 2, col 1, KEY_KP8 */
190 0x02020049 /* row 2, col 2, KEY_KP9 */
191 >;
192 gpio-activelow;
193 linux,wakeup;
194 debounce-delay-ms = <100>;
195 col-scan-delay-us = <5000>;
196 linux,no-autorepeat;
197 };
198};
199
200/* 2nd TX-Std UART - (A)UART1 */
201&auart1 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&auart1_pins_a>;
204 status = "okay";
205};
206
207/* 3rd TX-Std UART - (A)UART3 */
208&auart3 {
209 pinctrl-names = "default";
210 pinctrl-0 = <&auart3_pins_a>;
211 status = "okay";
212};
213
214&can0 {
215 pinctrl-names = "default";
216 pinctrl-0 = <&can0_pins_a>;
217 xceiver-supply = <&reg_can_xcvr>;
218 status = "okay";
219};
220
221&can1 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&can1_pins_a>;
224 xceiver-supply = <&reg_can_xcvr>;
225 status = "okay";
226};
227
228&digctl {
229 status = "okay";
230};
231
232/* 1st TX-Std UART - (D)UART */
233&duart {
234 pinctrl-names = "default";
235 pinctrl-0 = <&duart_4pins_a>;
236 status = "okay";
237};
238
239&gpmi {
240 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
241 nand-on-flash-bbt;
242 status = "okay";
243};
244
245&i2c0 {
246 pinctrl-names = "default";
247 pinctrl-0 = <&i2c0_pins_a>;
248 clock-frequency = <400000>;
249 status = "okay";
250
251 sgtl5000: sgtl5000@0a {
252 compatible = "fsl,sgtl5000";
253 reg = <0x0a>;
254 VDDA-supply = <&reg_2p5v>;
255 VDDIO-supply = <&reg_3p3v>;
256 clocks = <&mclk>;
257 };
258
259 gpio5: pca953x@20 {
260 compatible = "nxp,pca9554";
261 reg = <0x20>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&tx28_pca9554_pins>;
264 interrupt-parent = <&gpio3>;
265 interrupts = <28 0>;
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 };
271
272 polytouch: edt-ft5x06@38 {
273 compatible = "edt,edt-ft5x06";
274 reg = <0x38>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&tx28_edt_ft5x06_pins>;
277 interrupt-parent = <&gpio2>;
278 interrupts = <5 0>;
279 reset-gpios = <&gpio2 6 1>;
280 wake-gpios = <&gpio4 9 0>;
281 };
282
283 touchscreen: tsc2007@48 {
284 compatible = "ti,tsc2007";
285 reg = <0x48>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&tx28_tsc2007_pins>;
288 interrupt-parent = <&gpio3>;
289 interrupts = <20 0>;
290 pendown-gpio = <&gpio3 20 1>;
291 ti,x-plate-ohms = /bits/ 16 <660>;
292 };
293
294 ds1339: rtc@68 {
295 compatible = "mxim,ds1339";
296 reg = <0x68>;
297 };
298};
299
300&lcdif {
301 pinctrl-names = "default";
302 pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>;
303 lcd-supply = <&reg_lcd>;
304 display = <&display>;
305 status = "okay";
306
307 display: display@0 {
308 bits-per-pixel = <32>;
309 bus-width = <24>;
310 display-timings {
311 native-mode = <&timing5>;
312 timing0: timing0 {
313 panel-name = "VGA";
314 clock-frequency = <25175000>;
315 hactive = <640>;
316 vactive = <480>;
317 hback-porch = <48>;
318 hsync-len = <96>;
319 hfront-porch = <16>;
320 vback-porch = <33>;
321 vsync-len = <2>;
322 vfront-porch = <10>;
323 hsync-active = <0>;
324 vsync-active = <0>;
325 de-active = <1>;
326 pixelclk-active = <1>;
327 };
328
329 timing1: timing1 {
330 panel-name = "ETV570";
331 clock-frequency = <25175000>;
332 hactive = <640>;
333 vactive = <480>;
334 hback-porch = <114>;
335 hsync-len = <30>;
336 hfront-porch = <16>;
337 vback-porch = <32>;
338 vsync-len = <3>;
339 vfront-porch = <10>;
340 hsync-active = <0>;
341 vsync-active = <0>;
342 de-active = <1>;
343 pixelclk-active = <1>;
344 };
345
346 timing2: timing2 {
347 panel-name = "ET0350";
348 clock-frequency = <6500000>;
349 hactive = <320>;
350 vactive = <240>;
351 hback-porch = <34>;
352 hsync-len = <34>;
353 hfront-porch = <20>;
354 vback-porch = <15>;
355 vsync-len = <3>;
356 vfront-porch = <4>;
357 hsync-active = <0>;
358 vsync-active = <0>;
359 de-active = <1>;
360 pixelclk-active = <1>;
361 };
362
363 timing3: timing3 {
364 panel-name = "ET0430";
365 clock-frequency = <9000000>;
366 hactive = <480>;
367 vactive = <272>;
368 hback-porch = <2>;
369 hsync-len = <41>;
370 hfront-porch = <2>;
371 vback-porch = <2>;
372 vsync-len = <10>;
373 vfront-porch = <2>;
374 hsync-active = <0>;
375 vsync-active = <0>;
376 de-active = <1>;
377 pixelclk-active = <1>;
378 };
379
380 timing4: timing4 {
381 panel-name = "ET0500", "ET0700";
382 clock-frequency = <33260000>;
383 hactive = <800>;
384 vactive = <480>;
385 hback-porch = <88>;
386 hsync-len = <128>;
387 hfront-porch = <40>;
388 vback-porch = <33>;
389 vsync-len = <2>;
390 vfront-porch = <10>;
391 hsync-active = <0>;
392 vsync-active = <0>;
393 de-active = <1>;
394 pixelclk-active = <1>;
395 };
396
397 timing5: timing5 {
398 panel-name = "ETQ570";
399 clock-frequency = <6400000>;
400 hactive = <320>;
401 vactive = <240>;
402 hback-porch = <38>;
403 hsync-len = <30>;
404 hfront-porch = <30>;
405 vback-porch = <16>;
406 vsync-len = <3>;
407 vfront-porch = <4>;
408 hsync-active = <0>;
409 vsync-active = <0>;
410 de-active = <1>;
411 pixelclk-active = <1>;
412 };
413 };
414 };
415};
416
417&lradc {
418 fsl,lradc-touchscreen-wires = <4>;
419 status = "okay";
420};
421
422&mac0 {
423 phy-mode = "rmii";
424 pinctrl-names = "default", "gpio_mode";
425 pinctrl-0 = <&mac0_pins_a>;
426 pinctrl-1 = <&tx28_mac0_pins_gpio>;
427 status = "okay";
428};
429
430&mac1 {
431 phy-mode = "rmii";
432 pinctrl-names = "default";
433 pinctrl-0 = <&mac1_pins_a>;
434 /* not enabled by default */
435};
436
437&mxs_rtc {
438 status = "okay";
439};
440
441&ocotp {
442 status = "okay";
443};
444
445&pwm {
446 pinctrl-names = "default";
447 pinctrl-0 = <&pwm0_pins_a>;
448 status = "okay";
449};
450
451&pinctrl {
452 pinctrl-names = "default";
453 pinctrl-0 = <&hog_pins_a>;
454
455 hog_pins_a: hog@0 {
456 reg = <0>;
457 fsl,pinmux-ids = <
458 MX28_PAD_ENET0_RXD3__GPIO_4_10 /* module LED */
459 >;
460 fsl,drive-strength = <MXS_DRIVE_4mA>;
461 fsl,voltage = <MXS_VOLTAGE_HIGH>;
462 fsl,pull-up = <MXS_PULL_DISABLE>;
463 };
464
465 tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins {
466 fsl,pinmux-ids = <
467 MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */
468 MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */
469 MX28_PAD_ENET0_RXD2__GPIO_4_9 /* WAKE */
470 >;
471 fsl,drive-strength = <MXS_DRIVE_4mA>;
472 fsl,voltage = <MXS_VOLTAGE_HIGH>;
473 fsl,pull-up = <MXS_PULL_DISABLE>;
474 };
475
476 tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins {
477 fsl,pinmux-ids = <
478 MX28_PAD_LCD_D00__GPIO_1_0
479 >;
480 fsl,drive-strength = <MXS_DRIVE_4mA>;
481 fsl,voltage = <MXS_VOLTAGE_HIGH>;
482 fsl,pull-up = <MXS_PULL_DISABLE>;
483 };
484
485 tx28_lcdif_23bit_pins: tx28-lcdif-23bit {
486 fsl,pinmux-ids = <
487 /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */
488 MX28_PAD_LCD_D01__LCD_D1
489 MX28_PAD_LCD_D02__LCD_D2
490 MX28_PAD_LCD_D03__LCD_D3
491 MX28_PAD_LCD_D04__LCD_D4
492 MX28_PAD_LCD_D05__LCD_D5
493 MX28_PAD_LCD_D06__LCD_D6
494 MX28_PAD_LCD_D07__LCD_D7
495 MX28_PAD_LCD_D08__LCD_D8
496 MX28_PAD_LCD_D09__LCD_D9
497 MX28_PAD_LCD_D10__LCD_D10
498 MX28_PAD_LCD_D11__LCD_D11
499 MX28_PAD_LCD_D12__LCD_D12
500 MX28_PAD_LCD_D13__LCD_D13
501 MX28_PAD_LCD_D14__LCD_D14
502 MX28_PAD_LCD_D15__LCD_D15
503 MX28_PAD_LCD_D16__LCD_D16
504 MX28_PAD_LCD_D17__LCD_D17
505 MX28_PAD_LCD_D18__LCD_D18
506 MX28_PAD_LCD_D19__LCD_D19
507 MX28_PAD_LCD_D20__LCD_D20
508 MX28_PAD_LCD_D21__LCD_D21
509 MX28_PAD_LCD_D22__LCD_D22
510 MX28_PAD_LCD_D23__LCD_D23
511 >;
512 fsl,drive-strength = <MXS_DRIVE_4mA>;
513 fsl,voltage = <MXS_VOLTAGE_HIGH>;
514 fsl,pull-up = <MXS_PULL_DISABLE>;
515 };
516
517 tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl {
518 fsl,pinmux-ids = <
519 MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */
520 MX28_PAD_LCD_RESET__GPIO_3_30 /* Reset */
521 >;
522 fsl,drive-strength = <MXS_DRIVE_4mA>;
523 fsl,voltage = <MXS_VOLTAGE_HIGH>;
524 fsl,pull-up = <MXS_PULL_DISABLE>;
525 };
526
527 tx28_mac0_pins_gpio: tx28-mac0-gpio-pins {
528 fsl,pinmux-ids = <
529 MX28_PAD_ENET0_MDC__GPIO_4_0
530 MX28_PAD_ENET0_MDIO__GPIO_4_1
531 MX28_PAD_ENET0_RX_EN__GPIO_4_2
532 MX28_PAD_ENET0_RXD0__GPIO_4_3
533 MX28_PAD_ENET0_RXD1__GPIO_4_4
534 MX28_PAD_ENET0_TX_EN__GPIO_4_6
535 MX28_PAD_ENET0_TXD0__GPIO_4_7
536 MX28_PAD_ENET0_TXD1__GPIO_4_8
537 MX28_PAD_ENET_CLK__GPIO_4_16
538 >;
539 fsl,drive-strength = <MXS_DRIVE_4mA>;
540 fsl,voltage = <MXS_VOLTAGE_HIGH>;
541 fsl,pull-up = <MXS_PULL_DISABLE>;
542 };
543
544 tx28_pca9554_pins: tx28-pca9554-pins {
545 fsl,pinmux-ids = <
546 MX28_PAD_PWM3__GPIO_3_28
547 >;
548 fsl,drive-strength = <MXS_DRIVE_4mA>;
549 fsl,voltage = <MXS_VOLTAGE_HIGH>;
550 fsl,pull-up = <MXS_PULL_DISABLE>;
551 };
552
553 tx28_tsc2007_pins: tx28-tsc2007-pins {
554 fsl,pinmux-ids = <
555 MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
556 >;
557 fsl,drive-strength = <MXS_DRIVE_4mA>;
558 fsl,voltage = <MXS_VOLTAGE_HIGH>;
559 fsl,pull-up = <MXS_PULL_DISABLE>;
560 };
561
562
563 tx28_usbphy0_pins: tx28-usbphy0-pins {
564 fsl,pinmux-ids = <
565 MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */
566 MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */
567 >;
568 fsl,drive-strength = <MXS_DRIVE_12mA>;
569 fsl,voltage = <MXS_VOLTAGE_HIGH>;
570 fsl,pull-up = <MXS_PULL_DISABLE>;
571 };
572
573 tx28_usbphy1_pins: tx28-usbphy1-pins {
574 fsl,pinmux-ids = <
575 MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */
576 MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */
577 >;
578 fsl,drive-strength = <MXS_DRIVE_12mA>;
579 fsl,voltage = <MXS_VOLTAGE_HIGH>;
580 fsl,pull-up = <MXS_PULL_DISABLE>;
581 };
582};
583
584&saif0 {
585 pinctrl-names = "default";
586 pinctrl-0 = <&saif0_pins_b>;
587 fsl,saif-master;
588 status = "okay";
589};
590
591&saif1 {
592 pinctrl-names = "default";
593 pinctrl-0 = <&saif1_pins_a>;
594 status = "okay";
595};
596
597&ssp0 {
598 compatible = "fsl,imx28-mmc";
599 pinctrl-names = "default", "special";
600 pinctrl-0 = <&mmc0_4bit_pins_a
601 &mmc0_cd_cfg
602 &mmc0_sck_cfg>;
603 bus-width = <4>;
604 status = "okay";
605};
606
607&ssp3 {
608 compatible = "fsl,imx28-spi";
609 pinctrl-names = "default";
610 pinctrl-0 = <&spi3_pins_a>;
611 clock-frequency = <57600000>;
612 status = "okay";
613
614 spidev0: spi@0 {
615 compatible = "spidev";
616 reg = <0>;
617 spi-max-frequency = <57600000>;
618 };
619
620 spidev1: spi@1 {
621 compatible = "spidev";
622 reg = <1>;
623 spi-max-frequency = <57600000>;
115 }; 624 };
116}; 625};
626
627&usb0 {
628 vbus-supply = <&reg_usb0_vbus>;
629 disable-over-current;
630 dr_mode = "peripheral";
631 status = "okay";
632};
633
634&usb1 {
635 vbus-supply = <&reg_usb1_vbus>;
636 disable-over-current;
637 dr_mode = "host";
638 status = "okay";
639};
640
641&usbphy0 {
642 pinctrl-names = "default";
643 pinctrl-0 = <&tx28_usbphy0_pins>;
644 phy_type = "utmi";
645 status = "okay";
646};
647
648&usbphy1 {
649 pinctrl-names = "default";
650 pinctrl-0 = <&tx28_usbphy1_pins>;
651 phy_type = "utmi";
652 status = "okay";
653};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 175deefb048b..cda19c8b0a47 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -9,7 +9,8 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12/include/ "skeleton.dtsi" 12#include "skeleton.dtsi"
13#include "imx28-pinfunc.h"
13 14
14/ { 15/ {
15 interrupt-parent = <&icoll>; 16 interrupt-parent = <&icoll>;
@@ -207,538 +208,579 @@
207 duart_pins_a: duart@0 { 208 duart_pins_a: duart@0 {
208 reg = <0>; 209 reg = <0>;
209 fsl,pinmux-ids = < 210 fsl,pinmux-ids = <
210 0x3102 /* MX28_PAD_PWM0__DUART_RX */ 211 MX28_PAD_PWM0__DUART_RX
211 0x3112 /* MX28_PAD_PWM1__DUART_TX */ 212 MX28_PAD_PWM1__DUART_TX
212 >; 213 >;
213 fsl,drive-strength = <0>; 214 fsl,drive-strength = <MXS_DRIVE_4mA>;
214 fsl,voltage = <1>; 215 fsl,voltage = <MXS_VOLTAGE_HIGH>;
215 fsl,pull-up = <0>; 216 fsl,pull-up = <MXS_PULL_DISABLE>;
216 }; 217 };
217 218
218 duart_pins_b: duart@1 { 219 duart_pins_b: duart@1 {
219 reg = <1>; 220 reg = <1>;
220 fsl,pinmux-ids = < 221 fsl,pinmux-ids = <
221 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ 222 MX28_PAD_AUART0_CTS__DUART_RX
222 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ 223 MX28_PAD_AUART0_RTS__DUART_TX
223 >; 224 >;
224 fsl,drive-strength = <0>; 225 fsl,drive-strength = <MXS_DRIVE_4mA>;
225 fsl,voltage = <1>; 226 fsl,voltage = <MXS_VOLTAGE_HIGH>;
226 fsl,pull-up = <0>; 227 fsl,pull-up = <MXS_PULL_DISABLE>;
227 }; 228 };
228 229
229 duart_4pins_a: duart-4pins@0 { 230 duart_4pins_a: duart-4pins@0 {
230 reg = <0>; 231 reg = <0>;
231 fsl,pinmux-ids = < 232 fsl,pinmux-ids = <
232 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ 233 MX28_PAD_AUART0_CTS__DUART_RX
233 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ 234 MX28_PAD_AUART0_RTS__DUART_TX
234 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */ 235 MX28_PAD_AUART0_RX__DUART_CTS
235 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */ 236 MX28_PAD_AUART0_TX__DUART_RTS
236 >; 237 >;
237 fsl,drive-strength = <0>; 238 fsl,drive-strength = <MXS_DRIVE_4mA>;
238 fsl,voltage = <1>; 239 fsl,voltage = <MXS_VOLTAGE_HIGH>;
239 fsl,pull-up = <0>; 240 fsl,pull-up = <MXS_PULL_DISABLE>;
240 }; 241 };
241 242
242 gpmi_pins_a: gpmi-nand@0 { 243 gpmi_pins_a: gpmi-nand@0 {
243 reg = <0>; 244 reg = <0>;
244 fsl,pinmux-ids = < 245 fsl,pinmux-ids = <
245 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ 246 MX28_PAD_GPMI_D00__GPMI_D0
246 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ 247 MX28_PAD_GPMI_D01__GPMI_D1
247 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ 248 MX28_PAD_GPMI_D02__GPMI_D2
248 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ 249 MX28_PAD_GPMI_D03__GPMI_D3
249 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ 250 MX28_PAD_GPMI_D04__GPMI_D4
250 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ 251 MX28_PAD_GPMI_D05__GPMI_D5
251 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ 252 MX28_PAD_GPMI_D06__GPMI_D6
252 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ 253 MX28_PAD_GPMI_D07__GPMI_D7
253 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ 254 MX28_PAD_GPMI_CE0N__GPMI_CE0N
254 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ 255 MX28_PAD_GPMI_RDY0__GPMI_READY0
255 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ 256 MX28_PAD_GPMI_RDN__GPMI_RDN
256 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ 257 MX28_PAD_GPMI_WRN__GPMI_WRN
257 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ 258 MX28_PAD_GPMI_ALE__GPMI_ALE
258 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ 259 MX28_PAD_GPMI_CLE__GPMI_CLE
259 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ 260 MX28_PAD_GPMI_RESETN__GPMI_RESETN
260 >; 261 >;
261 fsl,drive-strength = <0>; 262 fsl,drive-strength = <MXS_DRIVE_4mA>;
262 fsl,voltage = <1>; 263 fsl,voltage = <MXS_VOLTAGE_HIGH>;
263 fsl,pull-up = <0>; 264 fsl,pull-up = <MXS_PULL_DISABLE>;
264 }; 265 };
265 266
266 gpmi_status_cfg: gpmi-status-cfg { 267 gpmi_status_cfg: gpmi-status-cfg {
267 fsl,pinmux-ids = < 268 fsl,pinmux-ids = <
268 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ 269 MX28_PAD_GPMI_RDN__GPMI_RDN
269 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ 270 MX28_PAD_GPMI_WRN__GPMI_WRN
270 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ 271 MX28_PAD_GPMI_RESETN__GPMI_RESETN
271 >; 272 >;
272 fsl,drive-strength = <2>; 273 fsl,drive-strength = <MXS_DRIVE_12mA>;
273 }; 274 };
274 275
275 auart0_pins_a: auart0@0 { 276 auart0_pins_a: auart0@0 {
276 reg = <0>; 277 reg = <0>;
277 fsl,pinmux-ids = < 278 fsl,pinmux-ids = <
278 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ 279 MX28_PAD_AUART0_RX__AUART0_RX
279 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ 280 MX28_PAD_AUART0_TX__AUART0_TX
280 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ 281 MX28_PAD_AUART0_CTS__AUART0_CTS
281 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ 282 MX28_PAD_AUART0_RTS__AUART0_RTS
282 >; 283 >;
283 fsl,drive-strength = <0>; 284 fsl,drive-strength = <MXS_DRIVE_4mA>;
284 fsl,voltage = <1>; 285 fsl,voltage = <MXS_VOLTAGE_HIGH>;
285 fsl,pull-up = <0>; 286 fsl,pull-up = <MXS_PULL_DISABLE>;
286 }; 287 };
287 288
288 auart0_2pins_a: auart0-2pins@0 { 289 auart0_2pins_a: auart0-2pins@0 {
289 reg = <0>; 290 reg = <0>;
290 fsl,pinmux-ids = < 291 fsl,pinmux-ids = <
291 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ 292 MX28_PAD_AUART0_RX__AUART0_RX
292 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ 293 MX28_PAD_AUART0_TX__AUART0_TX
293 >; 294 >;
294 fsl,drive-strength = <0>; 295 fsl,drive-strength = <MXS_DRIVE_4mA>;
295 fsl,voltage = <1>; 296 fsl,voltage = <MXS_VOLTAGE_HIGH>;
296 fsl,pull-up = <0>; 297 fsl,pull-up = <MXS_PULL_DISABLE>;
297 }; 298 };
298 299
299 auart1_pins_a: auart1@0 { 300 auart1_pins_a: auart1@0 {
300 reg = <0>; 301 reg = <0>;
301 fsl,pinmux-ids = < 302 fsl,pinmux-ids = <
302 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ 303 MX28_PAD_AUART1_RX__AUART1_RX
303 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ 304 MX28_PAD_AUART1_TX__AUART1_TX
304 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */ 305 MX28_PAD_AUART1_CTS__AUART1_CTS
305 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */ 306 MX28_PAD_AUART1_RTS__AUART1_RTS
306 >; 307 >;
307 fsl,drive-strength = <0>; 308 fsl,drive-strength = <MXS_DRIVE_4mA>;
308 fsl,voltage = <1>; 309 fsl,voltage = <MXS_VOLTAGE_HIGH>;
309 fsl,pull-up = <0>; 310 fsl,pull-up = <MXS_PULL_DISABLE>;
310 }; 311 };
311 312
312 auart1_2pins_a: auart1-2pins@0 { 313 auart1_2pins_a: auart1-2pins@0 {
313 reg = <0>; 314 reg = <0>;
314 fsl,pinmux-ids = < 315 fsl,pinmux-ids = <
315 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ 316 MX28_PAD_AUART1_RX__AUART1_RX
316 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ 317 MX28_PAD_AUART1_TX__AUART1_TX
317 >; 318 >;
318 fsl,drive-strength = <0>; 319 fsl,drive-strength = <MXS_DRIVE_4mA>;
319 fsl,voltage = <1>; 320 fsl,voltage = <MXS_VOLTAGE_HIGH>;
320 fsl,pull-up = <0>; 321 fsl,pull-up = <MXS_PULL_DISABLE>;
321 }; 322 };
322 323
323 auart2_2pins_a: auart2-2pins@0 { 324 auart2_2pins_a: auart2-2pins@0 {
324 reg = <0>; 325 reg = <0>;
325 fsl,pinmux-ids = < 326 fsl,pinmux-ids = <
326 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */ 327 MX28_PAD_SSP2_SCK__AUART2_RX
327 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */ 328 MX28_PAD_SSP2_MOSI__AUART2_TX
328 >; 329 >;
329 fsl,drive-strength = <0>; 330 fsl,drive-strength = <MXS_DRIVE_4mA>;
330 fsl,voltage = <1>; 331 fsl,voltage = <MXS_VOLTAGE_HIGH>;
331 fsl,pull-up = <0>; 332 fsl,pull-up = <MXS_PULL_DISABLE>;
332 }; 333 };
333 334
334 auart2_2pins_b: auart2-2pins@1 { 335 auart2_2pins_b: auart2-2pins@1 {
335 reg = <1>; 336 reg = <1>;
336 fsl,pinmux-ids = < 337 fsl,pinmux-ids = <
337 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */ 338 MX28_PAD_AUART2_RX__AUART2_RX
338 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */ 339 MX28_PAD_AUART2_TX__AUART2_TX
339 >; 340 >;
340 fsl,drive-strength = <0>; 341 fsl,drive-strength = <MXS_DRIVE_4mA>;
341 fsl,voltage = <1>; 342 fsl,voltage = <MXS_VOLTAGE_HIGH>;
342 fsl,pull-up = <0>; 343 fsl,pull-up = <MXS_PULL_DISABLE>;
343 }; 344 };
344 345
345 auart3_pins_a: auart3@0 { 346 auart3_pins_a: auart3@0 {
346 reg = <0>; 347 reg = <0>;
347 fsl,pinmux-ids = < 348 fsl,pinmux-ids = <
348 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ 349 MX28_PAD_AUART3_RX__AUART3_RX
349 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ 350 MX28_PAD_AUART3_TX__AUART3_TX
350 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ 351 MX28_PAD_AUART3_CTS__AUART3_CTS
351 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ 352 MX28_PAD_AUART3_RTS__AUART3_RTS
352 >; 353 >;
353 fsl,drive-strength = <0>; 354 fsl,drive-strength = <MXS_DRIVE_4mA>;
354 fsl,voltage = <1>; 355 fsl,voltage = <MXS_VOLTAGE_HIGH>;
355 fsl,pull-up = <0>; 356 fsl,pull-up = <MXS_PULL_DISABLE>;
356 }; 357 };
357 358
358 auart3_2pins_a: auart3-2pins@0 { 359 auart3_2pins_a: auart3-2pins@0 {
359 reg = <0>; 360 reg = <0>;
360 fsl,pinmux-ids = < 361 fsl,pinmux-ids = <
361 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */ 362 MX28_PAD_SSP2_MISO__AUART3_RX
362 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */ 363 MX28_PAD_SSP2_SS0__AUART3_TX
363 >; 364 >;
364 fsl,drive-strength = <0>; 365 fsl,drive-strength = <MXS_DRIVE_4mA>;
365 fsl,voltage = <1>; 366 fsl,voltage = <MXS_VOLTAGE_HIGH>;
366 fsl,pull-up = <0>; 367 fsl,pull-up = <MXS_PULL_DISABLE>;
367 }; 368 };
368 369
369 auart3_2pins_b: auart3-2pins@1 { 370 auart3_2pins_b: auart3-2pins@1 {
370 reg = <1>; 371 reg = <1>;
371 fsl,pinmux-ids = < 372 fsl,pinmux-ids = <
372 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ 373 MX28_PAD_AUART3_RX__AUART3_RX
373 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ 374 MX28_PAD_AUART3_TX__AUART3_TX
374 >; 375 >;
375 fsl,drive-strength = <0>; 376 fsl,drive-strength = <MXS_DRIVE_4mA>;
376 fsl,voltage = <1>; 377 fsl,voltage = <MXS_VOLTAGE_HIGH>;
377 fsl,pull-up = <0>; 378 fsl,pull-up = <MXS_PULL_DISABLE>;
378 }; 379 };
379 380
380 auart4_2pins_a: auart4@0 { 381 auart4_2pins_a: auart4@0 {
381 reg = <0>; 382 reg = <0>;
382 fsl,pinmux-ids = < 383 fsl,pinmux-ids = <
383 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */ 384 MX28_PAD_SSP3_SCK__AUART4_TX
384 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */ 385 MX28_PAD_SSP3_MOSI__AUART4_RX
385 >; 386 >;
386 fsl,drive-strength = <0>; 387 fsl,drive-strength = <MXS_DRIVE_4mA>;
387 fsl,voltage = <1>; 388 fsl,voltage = <MXS_VOLTAGE_HIGH>;
388 fsl,pull-up = <0>; 389 fsl,pull-up = <MXS_PULL_DISABLE>;
389 }; 390 };
390 391
391 mac0_pins_a: mac0@0 { 392 mac0_pins_a: mac0@0 {
392 reg = <0>; 393 reg = <0>;
393 fsl,pinmux-ids = < 394 fsl,pinmux-ids = <
394 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ 395 MX28_PAD_ENET0_MDC__ENET0_MDC
395 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ 396 MX28_PAD_ENET0_MDIO__ENET0_MDIO
396 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ 397 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
397 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ 398 MX28_PAD_ENET0_RXD0__ENET0_RXD0
398 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ 399 MX28_PAD_ENET0_RXD1__ENET0_RXD1
399 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ 400 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
400 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ 401 MX28_PAD_ENET0_TXD0__ENET0_TXD0
401 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ 402 MX28_PAD_ENET0_TXD1__ENET0_TXD1
402 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ 403 MX28_PAD_ENET_CLK__CLKCTRL_ENET
403 >; 404 >;
404 fsl,drive-strength = <1>; 405 fsl,drive-strength = <MXS_DRIVE_8mA>;
405 fsl,voltage = <1>; 406 fsl,voltage = <MXS_VOLTAGE_HIGH>;
406 fsl,pull-up = <1>; 407 fsl,pull-up = <MXS_PULL_ENABLE>;
407 }; 408 };
408 409
409 mac1_pins_a: mac1@0 { 410 mac1_pins_a: mac1@0 {
410 reg = <0>; 411 reg = <0>;
411 fsl,pinmux-ids = < 412 fsl,pinmux-ids = <
412 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ 413 MX28_PAD_ENET0_CRS__ENET1_RX_EN
413 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ 414 MX28_PAD_ENET0_RXD2__ENET1_RXD0
414 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ 415 MX28_PAD_ENET0_RXD3__ENET1_RXD1
415 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ 416 MX28_PAD_ENET0_COL__ENET1_TX_EN
416 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ 417 MX28_PAD_ENET0_TXD2__ENET1_TXD0
417 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ 418 MX28_PAD_ENET0_TXD3__ENET1_TXD1
418 >; 419 >;
419 fsl,drive-strength = <1>; 420 fsl,drive-strength = <MXS_DRIVE_8mA>;
420 fsl,voltage = <1>; 421 fsl,voltage = <MXS_VOLTAGE_HIGH>;
421 fsl,pull-up = <1>; 422 fsl,pull-up = <MXS_PULL_ENABLE>;
422 }; 423 };
423 424
424 mmc0_8bit_pins_a: mmc0-8bit@0 { 425 mmc0_8bit_pins_a: mmc0-8bit@0 {
425 reg = <0>; 426 reg = <0>;
426 fsl,pinmux-ids = < 427 fsl,pinmux-ids = <
427 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ 428 MX28_PAD_SSP0_DATA0__SSP0_D0
428 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ 429 MX28_PAD_SSP0_DATA1__SSP0_D1
429 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ 430 MX28_PAD_SSP0_DATA2__SSP0_D2
430 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ 431 MX28_PAD_SSP0_DATA3__SSP0_D3
431 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ 432 MX28_PAD_SSP0_DATA4__SSP0_D4
432 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ 433 MX28_PAD_SSP0_DATA5__SSP0_D5
433 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ 434 MX28_PAD_SSP0_DATA6__SSP0_D6
434 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ 435 MX28_PAD_SSP0_DATA7__SSP0_D7
435 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ 436 MX28_PAD_SSP0_CMD__SSP0_CMD
436 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ 437 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
437 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ 438 MX28_PAD_SSP0_SCK__SSP0_SCK
438 >; 439 >;
439 fsl,drive-strength = <1>; 440 fsl,drive-strength = <MXS_DRIVE_8mA>;
440 fsl,voltage = <1>; 441 fsl,voltage = <MXS_VOLTAGE_HIGH>;
441 fsl,pull-up = <1>; 442 fsl,pull-up = <MXS_PULL_ENABLE>;
442 }; 443 };
443 444
444 mmc0_4bit_pins_a: mmc0-4bit@0 { 445 mmc0_4bit_pins_a: mmc0-4bit@0 {
445 reg = <0>; 446 reg = <0>;
446 fsl,pinmux-ids = < 447 fsl,pinmux-ids = <
447 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ 448 MX28_PAD_SSP0_DATA0__SSP0_D0
448 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ 449 MX28_PAD_SSP0_DATA1__SSP0_D1
449 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ 450 MX28_PAD_SSP0_DATA2__SSP0_D2
450 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ 451 MX28_PAD_SSP0_DATA3__SSP0_D3
451 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ 452 MX28_PAD_SSP0_CMD__SSP0_CMD
452 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ 453 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
453 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ 454 MX28_PAD_SSP0_SCK__SSP0_SCK
454 >; 455 >;
455 fsl,drive-strength = <1>; 456 fsl,drive-strength = <MXS_DRIVE_8mA>;
456 fsl,voltage = <1>; 457 fsl,voltage = <MXS_VOLTAGE_HIGH>;
457 fsl,pull-up = <1>; 458 fsl,pull-up = <MXS_PULL_ENABLE>;
458 }; 459 };
459 460
460 mmc0_cd_cfg: mmc0-cd-cfg { 461 mmc0_cd_cfg: mmc0-cd-cfg {
461 fsl,pinmux-ids = < 462 fsl,pinmux-ids = <
462 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ 463 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
463 >; 464 >;
464 fsl,pull-up = <0>; 465 fsl,pull-up = <MXS_PULL_DISABLE>;
465 }; 466 };
466 467
467 mmc0_sck_cfg: mmc0-sck-cfg { 468 mmc0_sck_cfg: mmc0-sck-cfg {
468 fsl,pinmux-ids = < 469 fsl,pinmux-ids = <
469 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ 470 MX28_PAD_SSP0_SCK__SSP0_SCK
470 >; 471 >;
471 fsl,drive-strength = <2>; 472 fsl,drive-strength = <MXS_DRIVE_12mA>;
472 fsl,pull-up = <0>; 473 fsl,pull-up = <MXS_PULL_DISABLE>;
474 };
475
476 mmc2_4bit_pins_a: mmc2-4bit@0 {
477 reg = <0>;
478 fsl,pinmux-ids = <
479 MX28_PAD_SSP0_DATA4__SSP2_D0
480 MX28_PAD_SSP1_SCK__SSP2_D1
481 MX28_PAD_SSP1_CMD__SSP2_D2
482 MX28_PAD_SSP0_DATA5__SSP2_D3
483 MX28_PAD_SSP0_DATA6__SSP2_CMD
484 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
485 MX28_PAD_SSP0_DATA7__SSP2_SCK
486 >;
487 fsl,drive-strength = <MXS_DRIVE_8mA>;
488 fsl,voltage = <MXS_VOLTAGE_HIGH>;
489 fsl,pull-up = <MXS_PULL_ENABLE>;
490 };
491
492 mmc2_cd_cfg: mmc2-cd-cfg {
493 fsl,pinmux-ids = <
494 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
495 >;
496 fsl,pull-up = <MXS_PULL_DISABLE>;
497 };
498
499 mmc2_sck_cfg: mmc2-sck-cfg {
500 fsl,pinmux-ids = <
501 MX28_PAD_SSP0_DATA7__SSP2_SCK
502 >;
503 fsl,drive-strength = <MXS_DRIVE_12mA>;
504 fsl,pull-up = <MXS_PULL_DISABLE>;
473 }; 505 };
474 506
475 i2c0_pins_a: i2c0@0 { 507 i2c0_pins_a: i2c0@0 {
476 reg = <0>; 508 reg = <0>;
477 fsl,pinmux-ids = < 509 fsl,pinmux-ids = <
478 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ 510 MX28_PAD_I2C0_SCL__I2C0_SCL
479 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ 511 MX28_PAD_I2C0_SDA__I2C0_SDA
480 >; 512 >;
481 fsl,drive-strength = <1>; 513 fsl,drive-strength = <MXS_DRIVE_8mA>;
482 fsl,voltage = <1>; 514 fsl,voltage = <MXS_VOLTAGE_HIGH>;
483 fsl,pull-up = <1>; 515 fsl,pull-up = <MXS_PULL_ENABLE>;
484 }; 516 };
485 517
486 i2c0_pins_b: i2c0@1 { 518 i2c0_pins_b: i2c0@1 {
487 reg = <1>; 519 reg = <1>;
488 fsl,pinmux-ids = < 520 fsl,pinmux-ids = <
489 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ 521 MX28_PAD_AUART0_RX__I2C0_SCL
490 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ 522 MX28_PAD_AUART0_TX__I2C0_SDA
491 >; 523 >;
492 fsl,drive-strength = <1>; 524 fsl,drive-strength = <MXS_DRIVE_8mA>;
493 fsl,voltage = <1>; 525 fsl,voltage = <MXS_VOLTAGE_HIGH>;
494 fsl,pull-up = <1>; 526 fsl,pull-up = <MXS_PULL_ENABLE>;
495 }; 527 };
496 528
497 i2c1_pins_a: i2c1@0 { 529 i2c1_pins_a: i2c1@0 {
498 reg = <0>; 530 reg = <0>;
499 fsl,pinmux-ids = < 531 fsl,pinmux-ids = <
500 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ 532 MX28_PAD_PWM0__I2C1_SCL
501 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ 533 MX28_PAD_PWM1__I2C1_SDA
502 >; 534 >;
503 fsl,drive-strength = <1>; 535 fsl,drive-strength = <MXS_DRIVE_8mA>;
504 fsl,voltage = <1>; 536 fsl,voltage = <MXS_VOLTAGE_HIGH>;
505 fsl,pull-up = <1>; 537 fsl,pull-up = <MXS_PULL_ENABLE>;
506 }; 538 };
507 539
508 saif0_pins_a: saif0@0 { 540 saif0_pins_a: saif0@0 {
509 reg = <0>; 541 reg = <0>;
510 fsl,pinmux-ids = < 542 fsl,pinmux-ids = <
511 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ 543 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
512 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ 544 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
513 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ 545 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
514 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ 546 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
515 >; 547 >;
516 fsl,drive-strength = <2>; 548 fsl,drive-strength = <MXS_DRIVE_12mA>;
517 fsl,voltage = <1>; 549 fsl,voltage = <MXS_VOLTAGE_HIGH>;
518 fsl,pull-up = <1>; 550 fsl,pull-up = <MXS_PULL_ENABLE>;
519 }; 551 };
520 552
521 saif0_pins_b: saif0@1 { 553 saif0_pins_b: saif0@1 {
522 reg = <1>; 554 reg = <1>;
523 fsl,pinmux-ids = < 555 fsl,pinmux-ids = <
524 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ 556 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
525 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ 557 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
526 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ 558 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
527 >; 559 >;
528 fsl,drive-strength = <2>; 560 fsl,drive-strength = <MXS_DRIVE_12mA>;
529 fsl,voltage = <1>; 561 fsl,voltage = <MXS_VOLTAGE_HIGH>;
530 fsl,pull-up = <1>; 562 fsl,pull-up = <MXS_PULL_ENABLE>;
531 }; 563 };
532 564
533 saif1_pins_a: saif1@0 { 565 saif1_pins_a: saif1@0 {
534 reg = <0>; 566 reg = <0>;
535 fsl,pinmux-ids = < 567 fsl,pinmux-ids = <
536 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ 568 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
537 >; 569 >;
538 fsl,drive-strength = <2>; 570 fsl,drive-strength = <MXS_DRIVE_12mA>;
539 fsl,voltage = <1>; 571 fsl,voltage = <MXS_VOLTAGE_HIGH>;
540 fsl,pull-up = <1>; 572 fsl,pull-up = <MXS_PULL_ENABLE>;
541 }; 573 };
542 574
543 pwm0_pins_a: pwm0@0 { 575 pwm0_pins_a: pwm0@0 {
544 reg = <0>; 576 reg = <0>;
545 fsl,pinmux-ids = < 577 fsl,pinmux-ids = <
546 0x3100 /* MX28_PAD_PWM0__PWM_0 */ 578 MX28_PAD_PWM0__PWM_0
547 >; 579 >;
548 fsl,drive-strength = <0>; 580 fsl,drive-strength = <MXS_DRIVE_4mA>;
549 fsl,voltage = <1>; 581 fsl,voltage = <MXS_VOLTAGE_HIGH>;
550 fsl,pull-up = <0>; 582 fsl,pull-up = <MXS_PULL_DISABLE>;
551 }; 583 };
552 584
553 pwm2_pins_a: pwm2@0 { 585 pwm2_pins_a: pwm2@0 {
554 reg = <0>; 586 reg = <0>;
555 fsl,pinmux-ids = < 587 fsl,pinmux-ids = <
556 0x3120 /* MX28_PAD_PWM2__PWM_2 */ 588 MX28_PAD_PWM2__PWM_2
557 >; 589 >;
558 fsl,drive-strength = <0>; 590 fsl,drive-strength = <MXS_DRIVE_4mA>;
559 fsl,voltage = <1>; 591 fsl,voltage = <MXS_VOLTAGE_HIGH>;
560 fsl,pull-up = <0>; 592 fsl,pull-up = <MXS_PULL_DISABLE>;
561 }; 593 };
562 594
563 pwm3_pins_a: pwm3@0 { 595 pwm3_pins_a: pwm3@0 {
564 reg = <0>; 596 reg = <0>;
565 fsl,pinmux-ids = < 597 fsl,pinmux-ids = <
566 0x31c0 /* MX28_PAD_PWM3__PWM_3 */ 598 MX28_PAD_PWM3__PWM_3
567 >; 599 >;
568 fsl,drive-strength = <0>; 600 fsl,drive-strength = <MXS_DRIVE_4mA>;
569 fsl,voltage = <1>; 601 fsl,voltage = <MXS_VOLTAGE_HIGH>;
570 fsl,pull-up = <0>; 602 fsl,pull-up = <MXS_PULL_DISABLE>;
571 }; 603 };
572 604
573 pwm3_pins_b: pwm3@1 { 605 pwm3_pins_b: pwm3@1 {
574 reg = <1>; 606 reg = <1>;
575 fsl,pinmux-ids = < 607 fsl,pinmux-ids = <
576 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */ 608 MX28_PAD_SAIF0_MCLK__PWM_3
577 >; 609 >;
578 fsl,drive-strength = <0>; 610 fsl,drive-strength = <MXS_DRIVE_4mA>;
579 fsl,voltage = <1>; 611 fsl,voltage = <MXS_VOLTAGE_HIGH>;
580 fsl,pull-up = <0>; 612 fsl,pull-up = <MXS_PULL_DISABLE>;
581 }; 613 };
582 614
583 pwm4_pins_a: pwm4@0 { 615 pwm4_pins_a: pwm4@0 {
584 reg = <0>; 616 reg = <0>;
585 fsl,pinmux-ids = < 617 fsl,pinmux-ids = <
586 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ 618 MX28_PAD_PWM4__PWM_4
587 >; 619 >;
588 fsl,drive-strength = <0>; 620 fsl,drive-strength = <MXS_DRIVE_4mA>;
589 fsl,voltage = <1>; 621 fsl,voltage = <MXS_VOLTAGE_HIGH>;
590 fsl,pull-up = <0>; 622 fsl,pull-up = <MXS_PULL_DISABLE>;
591 }; 623 };
592 624
593 lcdif_24bit_pins_a: lcdif-24bit@0 { 625 lcdif_24bit_pins_a: lcdif-24bit@0 {
594 reg = <0>; 626 reg = <0>;
595 fsl,pinmux-ids = < 627 fsl,pinmux-ids = <
596 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ 628 MX28_PAD_LCD_D00__LCD_D0
597 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ 629 MX28_PAD_LCD_D01__LCD_D1
598 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ 630 MX28_PAD_LCD_D02__LCD_D2
599 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ 631 MX28_PAD_LCD_D03__LCD_D3
600 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ 632 MX28_PAD_LCD_D04__LCD_D4
601 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ 633 MX28_PAD_LCD_D05__LCD_D5
602 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ 634 MX28_PAD_LCD_D06__LCD_D6
603 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ 635 MX28_PAD_LCD_D07__LCD_D7
604 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ 636 MX28_PAD_LCD_D08__LCD_D8
605 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ 637 MX28_PAD_LCD_D09__LCD_D9
606 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ 638 MX28_PAD_LCD_D10__LCD_D10
607 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ 639 MX28_PAD_LCD_D11__LCD_D11
608 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ 640 MX28_PAD_LCD_D12__LCD_D12
609 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ 641 MX28_PAD_LCD_D13__LCD_D13
610 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ 642 MX28_PAD_LCD_D14__LCD_D14
611 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ 643 MX28_PAD_LCD_D15__LCD_D15
612 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ 644 MX28_PAD_LCD_D16__LCD_D16
613 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ 645 MX28_PAD_LCD_D17__LCD_D17
614 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ 646 MX28_PAD_LCD_D18__LCD_D18
615 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ 647 MX28_PAD_LCD_D19__LCD_D19
616 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ 648 MX28_PAD_LCD_D20__LCD_D20
617 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ 649 MX28_PAD_LCD_D21__LCD_D21
618 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ 650 MX28_PAD_LCD_D22__LCD_D22
619 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ 651 MX28_PAD_LCD_D23__LCD_D23
620 >; 652 >;
621 fsl,drive-strength = <0>; 653 fsl,drive-strength = <MXS_DRIVE_4mA>;
622 fsl,voltage = <1>; 654 fsl,voltage = <MXS_VOLTAGE_HIGH>;
623 fsl,pull-up = <0>; 655 fsl,pull-up = <MXS_PULL_DISABLE>;
624 }; 656 };
625 657
626 lcdif_16bit_pins_a: lcdif-16bit@0 { 658 lcdif_16bit_pins_a: lcdif-16bit@0 {
627 reg = <0>; 659 reg = <0>;
628 fsl,pinmux-ids = < 660 fsl,pinmux-ids = <
629 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ 661 MX28_PAD_LCD_D00__LCD_D0
630 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ 662 MX28_PAD_LCD_D01__LCD_D1
631 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ 663 MX28_PAD_LCD_D02__LCD_D2
632 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ 664 MX28_PAD_LCD_D03__LCD_D3
633 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ 665 MX28_PAD_LCD_D04__LCD_D4
634 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ 666 MX28_PAD_LCD_D05__LCD_D5
635 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ 667 MX28_PAD_LCD_D06__LCD_D6
636 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ 668 MX28_PAD_LCD_D07__LCD_D7
637 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ 669 MX28_PAD_LCD_D08__LCD_D8
638 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ 670 MX28_PAD_LCD_D09__LCD_D9
639 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ 671 MX28_PAD_LCD_D10__LCD_D10
640 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ 672 MX28_PAD_LCD_D11__LCD_D11
641 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ 673 MX28_PAD_LCD_D12__LCD_D12
642 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ 674 MX28_PAD_LCD_D13__LCD_D13
643 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ 675 MX28_PAD_LCD_D14__LCD_D14
644 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ 676 MX28_PAD_LCD_D15__LCD_D15
645 >; 677 >;
646 fsl,drive-strength = <0>; 678 fsl,drive-strength = <MXS_DRIVE_4mA>;
647 fsl,voltage = <1>; 679 fsl,voltage = <MXS_VOLTAGE_HIGH>;
648 fsl,pull-up = <0>; 680 fsl,pull-up = <MXS_PULL_DISABLE>;
649 }; 681 };
650 682
651 lcdif_sync_pins_a: lcdif-sync@0 { 683 lcdif_sync_pins_a: lcdif-sync@0 {
652 reg = <0>; 684 reg = <0>;
653 fsl,pinmux-ids = < 685 fsl,pinmux-ids = <
654 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ 686 MX28_PAD_LCD_RS__LCD_DOTCLK
655 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ 687 MX28_PAD_LCD_CS__LCD_ENABLE
656 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ 688 MX28_PAD_LCD_RD_E__LCD_VSYNC
657 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ 689 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
658 >; 690 >;
659 fsl,drive-strength = <0>; 691 fsl,drive-strength = <MXS_DRIVE_4mA>;
660 fsl,voltage = <1>; 692 fsl,voltage = <MXS_VOLTAGE_HIGH>;
661 fsl,pull-up = <0>; 693 fsl,pull-up = <MXS_PULL_DISABLE>;
662 }; 694 };
663 695
664 can0_pins_a: can0@0 { 696 can0_pins_a: can0@0 {
665 reg = <0>; 697 reg = <0>;
666 fsl,pinmux-ids = < 698 fsl,pinmux-ids = <
667 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ 699 MX28_PAD_GPMI_RDY2__CAN0_TX
668 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ 700 MX28_PAD_GPMI_RDY3__CAN0_RX
669 >; 701 >;
670 fsl,drive-strength = <0>; 702 fsl,drive-strength = <MXS_DRIVE_4mA>;
671 fsl,voltage = <1>; 703 fsl,voltage = <MXS_VOLTAGE_HIGH>;
672 fsl,pull-up = <0>; 704 fsl,pull-up = <MXS_PULL_DISABLE>;
673 }; 705 };
674 706
675 can1_pins_a: can1@0 { 707 can1_pins_a: can1@0 {
676 reg = <0>; 708 reg = <0>;
677 fsl,pinmux-ids = < 709 fsl,pinmux-ids = <
678 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ 710 MX28_PAD_GPMI_CE2N__CAN1_TX
679 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ 711 MX28_PAD_GPMI_CE3N__CAN1_RX
680 >; 712 >;
681 fsl,drive-strength = <0>; 713 fsl,drive-strength = <MXS_DRIVE_4mA>;
682 fsl,voltage = <1>; 714 fsl,voltage = <MXS_VOLTAGE_HIGH>;
683 fsl,pull-up = <0>; 715 fsl,pull-up = <MXS_PULL_DISABLE>;
684 }; 716 };
685 717
686 spi2_pins_a: spi2@0 { 718 spi2_pins_a: spi2@0 {
687 reg = <0>; 719 reg = <0>;
688 fsl,pinmux-ids = < 720 fsl,pinmux-ids = <
689 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ 721 MX28_PAD_SSP2_SCK__SSP2_SCK
690 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ 722 MX28_PAD_SSP2_MOSI__SSP2_CMD
691 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ 723 MX28_PAD_SSP2_MISO__SSP2_D0
692 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ 724 MX28_PAD_SSP2_SS0__SSP2_D3
693 >; 725 >;
694 fsl,drive-strength = <1>; 726 fsl,drive-strength = <MXS_DRIVE_8mA>;
695 fsl,voltage = <1>; 727 fsl,voltage = <MXS_VOLTAGE_HIGH>;
696 fsl,pull-up = <1>; 728 fsl,pull-up = <MXS_PULL_ENABLE>;
697 }; 729 };
698 730
699 spi3_pins_a: spi3@0 { 731 spi3_pins_a: spi3@0 {
700 reg = <0>; 732 reg = <0>;
701 fsl,pinmux-ids = < 733 fsl,pinmux-ids = <
702 0x3082 /* MX28_PAD_AUART2_RX__SSP3_D4 */ 734 MX28_PAD_AUART2_RX__SSP3_D4
703 0x3092 /* MX28_PAD_AUART2_TX__SSP3_D5 */ 735 MX28_PAD_AUART2_TX__SSP3_D5
704 0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */ 736 MX28_PAD_SSP3_SCK__SSP3_SCK
705 0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */ 737 MX28_PAD_SSP3_MOSI__SSP3_CMD
706 0x21A0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */ 738 MX28_PAD_SSP3_MISO__SSP3_D0
707 0x21B0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */ 739 MX28_PAD_SSP3_SS0__SSP3_D3
708 >; 740 >;
709 fsl,drive-strength = <1>; 741 fsl,drive-strength = <MXS_DRIVE_8mA>;
710 fsl,voltage = <1>; 742 fsl,voltage = <MXS_VOLTAGE_HIGH>;
711 fsl,pull-up = <0>; 743 fsl,pull-up = <MXS_PULL_DISABLE>;
712 }; 744 };
713 745
714 usbphy0_pins_a: usbphy0@0 { 746 usbphy0_pins_a: usbphy0@0 {
715 reg = <0>; 747 reg = <0>;
716 fsl,pinmux-ids = < 748 fsl,pinmux-ids = <
717 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ 749 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
718 >; 750 >;
719 fsl,drive-strength = <2>; 751 fsl,drive-strength = <MXS_DRIVE_12mA>;
720 fsl,voltage = <1>; 752 fsl,voltage = <MXS_VOLTAGE_HIGH>;
721 fsl,pull-up = <0>; 753 fsl,pull-up = <MXS_PULL_DISABLE>;
722 }; 754 };
723 755
724 usbphy0_pins_b: usbphy0@1 { 756 usbphy0_pins_b: usbphy0@1 {
725 reg = <1>; 757 reg = <1>;
726 fsl,pinmux-ids = < 758 fsl,pinmux-ids = <
727 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ 759 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
728 >; 760 >;
729 fsl,drive-strength = <2>; 761 fsl,drive-strength = <MXS_DRIVE_12mA>;
730 fsl,voltage = <1>; 762 fsl,voltage = <MXS_VOLTAGE_HIGH>;
731 fsl,pull-up = <0>; 763 fsl,pull-up = <MXS_PULL_DISABLE>;
732 }; 764 };
733 765
734 usbphy1_pins_a: usbphy1@0 { 766 usbphy1_pins_a: usbphy1@0 {
735 reg = <0>; 767 reg = <0>;
736 fsl,pinmux-ids = < 768 fsl,pinmux-ids = <
737 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ 769 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
770 >;
771 fsl,drive-strength = <MXS_DRIVE_12mA>;
772 fsl,voltage = <MXS_VOLTAGE_HIGH>;
773 fsl,pull-up = <MXS_PULL_DISABLE>;
774 };
775
776 usb0_id_pins_a: usb0id@0 {
777 reg = <0>;
778 fsl,pinmux-ids = <
779 MX28_PAD_AUART1_RTS__USB0_ID
738 >; 780 >;
739 fsl,drive-strength = <2>; 781 fsl,drive-strength = <MXS_DRIVE_12mA>;
740 fsl,voltage = <1>; 782 fsl,voltage = <MXS_VOLTAGE_HIGH>;
741 fsl,pull-up = <0>; 783 fsl,pull-up = <MXS_PULL_ENABLE>;
742 }; 784 };
743 }; 785 };
744 786
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index 123fe84e0e8c..5a7f552786a1 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -16,6 +16,33 @@
16 model = "Armadeus Systems APF51Dev docking/development board"; 16 model = "Armadeus Systems APF51Dev docking/development board";
17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51"; 17 compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
18 18
19 display@di1 {
20 compatible = "fsl,imx-parallel-display";
21 crtcs = <&ipu 0>;
22 interface-pix-fmt = "bgr666";
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_ipu_disp1_1>;
25
26 display-timings {
27 lw700 {
28 native-mode;
29 clock-frequency = <33000033>;
30 hactive = <800>;
31 vactive = <480>;
32 hback-porch = <96>;
33 hfront-porch = <96>;
34 vback-porch = <20>;
35 vfront-porch = <21>;
36 hsync-len = <64>;
37 vsync-len = <4>;
38 hsync-active = <1>;
39 vsync-active = <1>;
40 de-active = <1>;
41 pixelclk-active = <0>;
42 };
43 };
44 };
45
19 gpio-keys { 46 gpio-keys {
20 compatible = "gpio-keys"; 47 compatible = "gpio-keys";
21 48
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 1d337d99ecd5..be1407cf5abd 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -27,6 +27,20 @@
27 interface-pix-fmt = "rgb24"; 27 interface-pix-fmt = "rgb24";
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp1_1>; 29 pinctrl-0 = <&pinctrl_ipu_disp1_1>;
30 display-timings {
31 native-mode = <&timing0>;
32 timing0: dvi {
33 clock-frequency = <65000000>;
34 hactive = <1024>;
35 vactive = <768>;
36 hback-porch = <220>;
37 hfront-porch = <40>;
38 vback-porch = <21>;
39 vfront-porch = <7>;
40 hsync-len = <60>;
41 vsync-len = <10>;
42 };
43 };
30 }; 44 };
31 45
32 display@di1 { 46 display@di1 {
@@ -35,6 +49,25 @@
35 interface-pix-fmt = "rgb565"; 49 interface-pix-fmt = "rgb565";
36 pinctrl-names = "default"; 50 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_ipu_disp2_1>; 51 pinctrl-0 = <&pinctrl_ipu_disp2_1>;
52 status = "disabled";
53 display-timings {
54 native-mode = <&timing1>;
55 timing1: claawvga {
56 clock-frequency = <27000000>;
57 hactive = <800>;
58 vactive = <480>;
59 hback-porch = <40>;
60 hfront-porch = <60>;
61 vback-porch = <10>;
62 vfront-porch = <10>;
63 hsync-len = <20>;
64 vsync-len = <10>;
65 hsync-active = <0>;
66 vsync-active = <0>;
67 de-active = <1>;
68 pixelclk-active = <0>;
69 };
70 };
38 }; 71 };
39 72
40 gpio-keys { 73 gpio-keys {
@@ -95,7 +128,7 @@
95 128
96&uart3 { 129&uart3 {
97 pinctrl-names = "default"; 130 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_uart3_1>; 131 pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>;
99 fsl,uart-has-rtscts; 132 fsl,uart-has-rtscts;
100 status = "okay"; 133 status = "okay";
101}; 134};
@@ -252,7 +285,7 @@
252 285
253&uart1 { 286&uart1 {
254 pinctrl-names = "default"; 287 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart1_1>; 288 pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
256 fsl,uart-has-rtscts; 289 fsl,uart-has-rtscts;
257 status = "okay"; 290 status = "okay";
258}; 291};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 54cee6517902..f4dcff3a9969 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -86,6 +86,11 @@
86 interrupt-parent = <&tzic>; 86 interrupt-parent = <&tzic>;
87 ranges; 87 ranges;
88 88
89 iram: iram@1ffe0000 {
90 compatible = "mmio-sram";
91 reg = <0x1ffe0000 0x20000>;
92 };
93
89 ipu: ipu@40000000 { 94 ipu: ipu@40000000 {
90 #crtc-cells = <1>; 95 #crtc-cells = <1>;
91 compatible = "fsl,imx51-ipu"; 96 compatible = "fsl,imx51-ipu";
@@ -374,6 +379,14 @@
374 clocks = <&clks 107>; 379 clocks = <&clks 107>;
375 }; 380 };
376 381
382 owire: owire@83fa4000 {
383 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
384 reg = <0x83fa4000 0x4000>;
385 interrupts = <88>;
386 clocks = <&clks 159>;
387 status = "disabled";
388 };
389
377 ecspi2: ecspi@83fac000 { 390 ecspi2: ecspi@83fac000 {
378 #address-cells = <1>; 391 #address-cells = <1>;
379 #size-cells = <0>; 392 #size-cells = <0>;
@@ -747,6 +760,11 @@
747 fsl,pins = < 760 fsl,pins = <
748 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 761 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
749 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 762 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
763 >;
764 };
765
766 pinctrl_uart1_rtscts_1: uart1rtscts-1 {
767 fsl,pins = <
750 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 768 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
751 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 769 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
752 >; 770 >;
@@ -767,6 +785,11 @@
767 fsl,pins = < 785 fsl,pins = <
768 MX51_PAD_EIM_D25__UART3_RXD 0x1c5 786 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
769 MX51_PAD_EIM_D26__UART3_TXD 0x1c5 787 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
788 >;
789 };
790
791 pinctrl_uart3_rtscts_1: uart3rtscts-1 {
792 fsl,pins = <
770 MX51_PAD_EIM_D27__UART3_RTS 0x1c5 793 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
771 MX51_PAD_EIM_D24__UART3_CTS 0x1c5 794 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
772 >; 795 >;
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index e97ddae09d74..91a5935a4aac 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -55,19 +55,20 @@
55 label = "Power Button"; 55 label = "Power Button";
56 gpios = <&gpio1 8 0>; 56 gpios = <&gpio1 8 0>;
57 linux,code = <116>; /* KEY_POWER */ 57 linux,code = <116>; /* KEY_POWER */
58 gpio-key,wakeup;
59 }; 58 };
60 59
61 volume-up { 60 volume-up {
62 label = "Volume Up"; 61 label = "Volume Up";
63 gpios = <&gpio2 14 0>; 62 gpios = <&gpio2 14 0>;
64 linux,code = <115>; /* KEY_VOLUMEUP */ 63 linux,code = <115>; /* KEY_VOLUMEUP */
64 gpio-key,wakeup;
65 }; 65 };
66 66
67 volume-down { 67 volume-down {
68 label = "Volume Down"; 68 label = "Volume Down";
69 gpios = <&gpio2 15 0>; 69 gpios = <&gpio2 15 0>;
70 linux,code = <114>; /* KEY_VOLUMEDOWN */ 70 linux,code = <114>; /* KEY_VOLUMEDOWN */
71 gpio-key,wakeup;
71 }; 72 };
72 }; 73 };
73 74
@@ -122,7 +123,6 @@
122&esdhc1 { 123&esdhc1 {
123 pinctrl-names = "default"; 124 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_esdhc1_1>; 125 pinctrl-0 = <&pinctrl_esdhc1_1>;
125 cd-gpios = <&gpio3 13 0>;
126 status = "okay"; 126 status = "okay";
127}; 127};
128 128
@@ -136,6 +136,7 @@
136 pinctrl-0 = <&pinctrl_esdhc3_1>; 136 pinctrl-0 = <&pinctrl_esdhc3_1>;
137 cd-gpios = <&gpio3 11 0>; 137 cd-gpios = <&gpio3 11 0>;
138 wp-gpios = <&gpio3 12 0>; 138 wp-gpios = <&gpio3 12 0>;
139 bus-width = <8>;
139 status = "okay"; 140 status = "okay";
140}; 141};
141 142
@@ -152,7 +153,6 @@
152 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 153 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
153 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 154 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
154 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 155 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
155 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
156 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 156 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
157 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 157 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
158 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 158 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
@@ -318,5 +318,6 @@
318}; 318};
319 319
320&usbotg { 320&usbotg {
321 status = "okay"; 321 dr_mode = "peripheral";
322 status = "okay";
322}; 323};
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
index 9bbe82bdee41..97ed0816a6e0 100644
--- a/arch/arm/boot/dts/imx6q-pinfunc.h
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -536,7 +536,7 @@
536#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 536#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
537#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 537#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
538#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 538#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
539#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 539#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100
540#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 540#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
541#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 541#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
542#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 542#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
@@ -654,7 +654,7 @@
654#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 654#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
655#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 655#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
656#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 656#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
657#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 657#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101
658#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 658#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
659#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 659#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
660#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 660#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 3530280f5150..f004913f7d80 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -65,8 +65,10 @@
65 }; 65 };
66}; 66};
67 67
68&sata { 68&audmux {
69 status = "okay"; 69 status = "okay";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_audmux_1>;
70}; 72};
71 73
72&ecspi1 { 74&ecspi1 {
@@ -83,11 +85,29 @@
83 }; 85 };
84}; 86};
85 87
86&ssi1 { 88&fec {
87 fsl,mode = "i2s-slave"; 89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_enet_1>;
91 phy-mode = "rgmii";
92 phy-reset-gpios = <&gpio3 23 0>;
88 status = "okay"; 93 status = "okay";
89}; 94};
90 95
96&i2c1 {
97 status = "okay";
98 clock-frequency = <100000>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_i2c1_1>;
101
102 codec: sgtl5000@0a {
103 compatible = "fsl,sgtl5000";
104 reg = <0x0a>;
105 clocks = <&clks 201>;
106 VDDA-supply = <&reg_2p5v>;
107 VDDIO-supply = <&reg_3p3v>;
108 };
109};
110
91&iomuxc { 111&iomuxc {
92 pinctrl-names = "default"; 112 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_hog>; 113 pinctrl-0 = <&pinctrl_hog>;
@@ -103,28 +123,61 @@
103 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 123 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
104 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 124 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
105 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000 125 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
126 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
106 >; 127 >;
107 }; 128 };
108 }; 129 };
109}; 130};
110 131
111&usbotg { 132&ldb {
112 vbus-supply = <&reg_usb_otg_vbus>; 133 status = "okay";
113 pinctrl-names = "default"; 134
114 pinctrl-0 = <&pinctrl_usbotg_1>; 135 lvds-channel@0 {
115 disable-over-current; 136 fsl,data-mapping = "spwg";
137 fsl,data-width = <18>;
138 status = "okay";
139
140 display-timings {
141 native-mode = <&timing0>;
142 timing0: hsd100pxn1 {
143 clock-frequency = <65000000>;
144 hactive = <1024>;
145 vactive = <768>;
146 hback-porch = <220>;
147 hfront-porch = <40>;
148 vback-porch = <21>;
149 vfront-porch = <7>;
150 hsync-len = <60>;
151 vsync-len = <10>;
152 };
153 };
154 };
155};
156
157&sata {
158 status = "okay";
159};
160
161&ssi1 {
162 fsl,mode = "i2s-slave";
116 status = "okay"; 163 status = "okay";
117}; 164};
118 165
166&uart2 {
167 status = "okay";
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2_1>;
170};
171
119&usbh1 { 172&usbh1 {
120 status = "okay"; 173 status = "okay";
121}; 174};
122 175
123&fec { 176&usbotg {
177 vbus-supply = <&reg_usb_otg_vbus>;
124 pinctrl-names = "default"; 178 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_enet_1>; 179 pinctrl-0 = <&pinctrl_usbotg_1>;
126 phy-mode = "rgmii"; 180 disable-over-current;
127 phy-reset-gpios = <&gpio3 23 0>;
128 status = "okay"; 181 status = "okay";
129}; 182};
130 183
@@ -145,30 +198,3 @@
145 vmmc-supply = <&reg_3p3v>; 198 vmmc-supply = <&reg_3p3v>;
146 status = "okay"; 199 status = "okay";
147}; 200};
148
149&audmux {
150 status = "okay";
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_audmux_1>;
153};
154
155&uart2 {
156 status = "okay";
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart2_1>;
159};
160
161&i2c1 {
162 status = "okay";
163 clock-frequency = <100000>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_i2c1_1>;
166
167 codec: sgtl5000@0a {
168 compatible = "fsl,sgtl5000";
169 reg = <0x0a>;
170 clocks = <&clks 201>;
171 VDDA-supply = <&reg_2p5v>;
172 VDDIO-supply = <&reg_3p3v>;
173 };
174};
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
new file mode 100644
index 000000000000..6e1ccdc019a7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -0,0 +1,39 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14
15/ {
16 model = "Udoo i.MX6 Quad Board";
17 compatible = "udoo,imx6q-udoo", "fsl,imx6q";
18
19 memory {
20 reg = <0x10000000 0x40000000>;
21 };
22};
23
24&sata {
25 status = "okay";
26};
27
28&uart2 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_uart2_1>;
31 status = "okay";
32};
33
34&usdhc3 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_usdhc3_2>;
37 non-removable;
38 status = "okay";
39};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 1cbbc5160d27..ff6f1e8f2dd9 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -54,6 +54,7 @@
54 fsl,pins = < 54 fsl,pins = <
55 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 55 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
56 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 56 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
57 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
57 >; 58 >;
58 }; 59 };
59 }; 60 };
@@ -74,8 +75,10 @@
74}; 75};
75 76
76&usdhc3 { 77&usdhc3 {
77 pinctrl-names = "default"; 78 pinctrl-names = "default", "state_100mhz", "state_200mhz";
78 pinctrl-0 = <&pinctrl_usdhc3_1>; 79 pinctrl-0 = <&pinctrl_usdhc3_1>;
80 pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
81 pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
79 cd-gpios = <&gpio6 15 0>; 82 cd-gpios = <&gpio6 15 0>;
80 wp-gpios = <&gpio1 13 0>; 83 wp-gpios = <&gpio1 13 0>;
81 status = "okay"; 84 status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 39eafc222a2e..e75e11b36dff 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -80,6 +80,14 @@
80 mux-int-port = <2>; 80 mux-int-port = <2>;
81 mux-ext-port = <3>; 81 mux-ext-port = <3>;
82 }; 82 };
83
84 backlight {
85 compatible = "pwm-backlight";
86 pwms = <&pwm1 0 5000000>;
87 brightness-levels = <0 4 8 16 32 64 128 255>;
88 default-brightness-level = <7>;
89 status = "okay";
90 };
83}; 91};
84 92
85&audmux { 93&audmux {
@@ -108,6 +116,7 @@
108 pinctrl-names = "default"; 116 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_enet_1>; 117 pinctrl-0 = <&pinctrl_enet_1>;
110 phy-mode = "rgmii"; 118 phy-mode = "rgmii";
119 phy-reset-gpios = <&gpio1 25 0>;
111 status = "okay"; 120 status = "okay";
112}; 121};
113 122
@@ -172,6 +181,7 @@
172 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 181 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
173 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 182 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
174 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 183 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
184 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
175 >; 185 >;
176 }; 186 };
177 }; 187 };
@@ -202,6 +212,12 @@
202 }; 212 };
203}; 213};
204 214
215&pwm1 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_pwm0_1>;
218 status = "okay";
219};
220
205&ssi2 { 221&ssi2 {
206 fsl,mode = "i2s-slave"; 222 fsl,mode = "i2s-slave";
207 status = "okay"; 223 status = "okay";
@@ -229,6 +245,7 @@
229&usdhc2 { 245&usdhc2 {
230 pinctrl-names = "default"; 246 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_usdhc2_1>; 247 pinctrl-0 = <&pinctrl_usdhc2_1>;
248 bus-width = <8>;
232 cd-gpios = <&gpio2 2 0>; 249 cd-gpios = <&gpio2 2 0>;
233 wp-gpios = <&gpio2 3 0>; 250 wp-gpios = <&gpio2 3 0>;
234 status = "okay"; 251 status = "okay";
@@ -237,6 +254,7 @@
237&usdhc3 { 254&usdhc3 {
238 pinctrl-names = "default"; 255 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_usdhc3_1>; 256 pinctrl-0 = <&pinctrl_usdhc3_1>;
257 bus-width = <8>;
240 cd-gpios = <&gpio2 0 0>; 258 cd-gpios = <&gpio2 0 0>;
241 wp-gpios = <&gpio2 1 0>; 259 wp-gpios = <&gpio2 1 0>;
242 status = "okay"; 260 status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index a55113e65bcb..35f547929167 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -43,6 +43,13 @@
43 mux-int-port = <1>; 43 mux-int-port = <1>;
44 mux-ext-port = <3>; 44 mux-ext-port = <3>;
45 }; 45 };
46
47 sound-spdif {
48 compatible = "fsl,imx-audio-spdif";
49 model = "imx-spdif";
50 spdif-controller = <&spdif>;
51 spdif-out;
52 };
46}; 53};
47 54
48&audmux { 55&audmux {
@@ -81,6 +88,7 @@
81 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */ 88 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
82 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */ 89 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
83 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */ 90 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
91 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
84 >; 92 >;
85 }; 93 };
86 }; 94 };
@@ -90,6 +98,13 @@
90 pinctrl-names = "default"; 98 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet_1>; 99 pinctrl-0 = <&pinctrl_enet_1>;
92 phy-mode = "rgmii"; 100 phy-mode = "rgmii";
101 phy-reset-gpios = <&gpio3 29 0>;
102 status = "okay";
103};
104
105&spdif {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_spdif_3>;
93 status = "okay"; 108 status = "okay";
94}; 109};
95 110
@@ -115,6 +130,14 @@
115 status = "okay"; 130 status = "okay";
116}; 131};
117 132
133&usbotg {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_usbotg_1>;
136 disable-over-current;
137 dr_mode = "peripheral";
138 status = "okay";
139};
140
118&usdhc1 { 141&usdhc1 {
119 pinctrl-names = "default"; 142 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_usdhc1_2>; 143 pinctrl-0 = <&pinctrl_usdhc1_2>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index ccd55c2fdb67..59154dc15fe4 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -116,6 +116,22 @@
116 arm,data-latency = <4 2 3>; 116 arm,data-latency = <4 2 3>;
117 }; 117 };
118 118
119 pcie: pcie@0x01000000 {
120 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
121 reg = <0x01ffc000 0x4000>; /* DBI */
122 #address-cells = <3>;
123 #size-cells = <2>;
124 device_type = "pci";
125 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
126 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
127 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
128 num-lanes = <1>;
129 interrupts = <0 123 0x04>;
130 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
131 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
132 status = "disabled";
133 };
134
119 pmu { 135 pmu {
120 compatible = "arm,cortex-a9-pmu"; 136 compatible = "arm,cortex-a9-pmu";
121 interrupts = <0 94 0x04>; 137 interrupts = <0 94 0x04>;
@@ -136,8 +152,23 @@
136 ranges; 152 ranges;
137 153
138 spdif: spdif@02004000 { 154 spdif: spdif@02004000 {
155 compatible = "fsl,imx35-spdif";
139 reg = <0x02004000 0x4000>; 156 reg = <0x02004000 0x4000>;
140 interrupts = <0 52 0x04>; 157 interrupts = <0 52 0x04>;
158 dmas = <&sdma 14 18 0>,
159 <&sdma 15 18 0>;
160 dma-names = "rx", "tx";
161 clocks = <&clks 197>, <&clks 3>,
162 <&clks 197>, <&clks 107>,
163 <&clks 0>, <&clks 118>,
164 <&clks 62>, <&clks 139>,
165 <&clks 0>;
166 clock-names = "core", "rxtx0",
167 "rxtx1", "rxtx2",
168 "rxtx3", "rxtx4",
169 "rxtx5", "rxtx6",
170 "rxtx7";
171 status = "disabled";
141 }; 172 };
142 173
143 ecspi1: ecspi@02008000 { 174 ecspi1: ecspi@02008000 {
@@ -1010,6 +1041,12 @@
1010 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1041 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1011 >; 1042 >;
1012 }; 1043 };
1044
1045 pinctrl_spdif_3: spdifgrp-3 {
1046 fsl,pins = <
1047 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
1048 >;
1049 };
1013 }; 1050 };
1014 1051
1015 uart1 { 1052 uart1 {
@@ -1184,6 +1221,36 @@
1184 >; 1221 >;
1185 }; 1222 };
1186 1223
1224 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
1225 fsl,pins = <
1226 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
1227 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
1228 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
1229 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
1230 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
1231 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
1232 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
1233 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
1234 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
1235 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
1236 >;
1237 };
1238
1239 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
1240 fsl,pins = <
1241 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
1242 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
1243 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
1244 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
1245 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
1246 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
1247 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
1248 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
1249 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
1250 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
1251 >;
1252 };
1253
1187 pinctrl_usdhc3_2: usdhc3grp-2 { 1254 pinctrl_usdhc3_2: usdhc3grp-2 {
1188 fsl,pins = < 1255 fsl,pins = <
1189 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1256 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 2886a590823d..cc68e19c5163 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -17,6 +17,44 @@
17 memory { 17 memory {
18 reg = <0x80000000 0x40000000>; 18 reg = <0x80000000 0x40000000>;
19 }; 19 };
20
21 regulators {
22 compatible = "simple-bus";
23
24 reg_usb_otg1_vbus: usb_otg1_vbus {
25 compatible = "regulator-fixed";
26 regulator-name = "usb_otg1_vbus";
27 regulator-min-microvolt = <5000000>;
28 regulator-max-microvolt = <5000000>;
29 gpio = <&gpio4 0 0>;
30 enable-active-high;
31 };
32
33 reg_usb_otg2_vbus: usb_otg2_vbus {
34 compatible = "regulator-fixed";
35 regulator-name = "usb_otg2_vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 gpio = <&gpio4 2 0>;
39 enable-active-high;
40 };
41 };
42};
43
44&ecspi1 {
45 fsl,spi-num-chipselects = <1>;
46 cs-gpios = <&gpio4 11 0>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_ecspi1_1>;
49 status = "okay";
50
51 flash: m25p80@0 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 compatible = "st,m25p32";
55 spi-max-frequency = <20000000>;
56 reg = <0>;
57 };
20}; 58};
21 59
22&fec { 60&fec {
@@ -38,6 +76,8 @@
38 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 76 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
39 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 77 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
40 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 78 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
79 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
80 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
41 >; 81 >;
42 }; 82 };
43 }; 83 };
@@ -49,9 +89,26 @@
49 status = "okay"; 89 status = "okay";
50}; 90};
51 91
52&usdhc1 { 92&usbotg1 {
93 vbus-supply = <&reg_usb_otg1_vbus>;
53 pinctrl-names = "default"; 94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_usbotg1_1>;
96 disable-over-current;
97 status = "okay";
98};
99
100&usbotg2 {
101 vbus-supply = <&reg_usb_otg2_vbus>;
102 dr_mode = "host";
103 disable-over-current;
104 status = "okay";
105};
106
107&usdhc1 {
108 pinctrl-names = "default", "state_100mhz", "state_200mhz";
54 pinctrl-0 = <&pinctrl_usdhc1_1>; 109 pinctrl-0 = <&pinctrl_usdhc1_1>;
110 pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>;
111 pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>;
55 bus-width = <8>; 112 bus-width = <8>;
56 cd-gpios = <&gpio4 7 0>; 113 cd-gpios = <&gpio4 7 0>;
57 wp-gpios = <&gpio4 6 0>; 114 wp-gpios = <&gpio4 6 0>;
@@ -59,16 +116,20 @@
59}; 116};
60 117
61&usdhc2 { 118&usdhc2 {
62 pinctrl-names = "default"; 119 pinctrl-names = "default", "state_100mhz", "state_200mhz";
63 pinctrl-0 = <&pinctrl_usdhc2_1>; 120 pinctrl-0 = <&pinctrl_usdhc2_1>;
121 pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
122 pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
64 cd-gpios = <&gpio5 0 0>; 123 cd-gpios = <&gpio5 0 0>;
65 wp-gpios = <&gpio4 29 0>; 124 wp-gpios = <&gpio4 29 0>;
66 status = "okay"; 125 status = "okay";
67}; 126};
68 127
69&usdhc3 { 128&usdhc3 {
70 pinctrl-names = "default"; 129 pinctrl-names = "default", "state_100mhz", "state_200mhz";
71 pinctrl-0 = <&pinctrl_usdhc3_1>; 130 pinctrl-0 = <&pinctrl_usdhc3_1>;
131 pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
132 pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
72 cd-gpios = <&gpio3 22 0>; 133 cd-gpios = <&gpio3 22 0>;
73 status = "okay"; 134 status = "okay";
74}; 135};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 177d9e791a01..28558f1aaf2d 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -13,16 +13,20 @@
13 13
14/ { 14/ {
15 aliases { 15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 gpio0 = &gpio1; 16 gpio0 = &gpio1;
22 gpio1 = &gpio2; 17 gpio1 = &gpio2;
23 gpio2 = &gpio3; 18 gpio2 = &gpio3;
24 gpio3 = &gpio4; 19 gpio3 = &gpio4;
25 gpio4 = &gpio5; 20 gpio4 = &gpio5;
21 serial0 = &uart1;
22 serial1 = &uart2;
23 serial2 = &uart3;
24 serial3 = &uart4;
25 serial4 = &uart5;
26 spi0 = &ecspi1;
27 spi1 = &ecspi2;
28 spi2 = &ecspi3;
29 spi3 = &ecspi4;
26 }; 30 };
27 31
28 cpus { 32 cpus {
@@ -530,10 +534,26 @@
530 interrupts = <0 89 0x04>; 534 interrupts = <0 89 0x04>;
531 }; 535 };
532 536
537 gpr: iomuxc-gpr@020e0000 {
538 compatible = "fsl,imx6sl-iomuxc-gpr",
539 "fsl,imx6q-iomuxc-gpr", "syscon";
540 reg = <0x020e0000 0x38>;
541 };
542
533 iomuxc: iomuxc@020e0000 { 543 iomuxc: iomuxc@020e0000 {
534 compatible = "fsl,imx6sl-iomuxc"; 544 compatible = "fsl,imx6sl-iomuxc";
535 reg = <0x020e0000 0x4000>; 545 reg = <0x020e0000 0x4000>;
536 546
547 ecspi1 {
548 pinctrl_ecspi1_1: ecspi1grp-1 {
549 fsl,pins = <
550 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
551 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
552 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
553 >;
554 };
555 };
556
537 fec { 557 fec {
538 pinctrl_fec_1: fecgrp-1 { 558 pinctrl_fec_1: fecgrp-1 {
539 fsl,pins = < 559 fsl,pins = <
@@ -559,6 +579,64 @@
559 }; 579 };
560 }; 580 };
561 581
582 usbotg1 {
583 pinctrl_usbotg1_1: usbotg1grp-1 {
584 fsl,pins = <
585 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
586 >;
587 };
588
589 pinctrl_usbotg1_2: usbotg1grp-2 {
590 fsl,pins = <
591 MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
592 >;
593 };
594
595 pinctrl_usbotg1_3: usbotg1grp-3 {
596 fsl,pins = <
597 MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
598 >;
599 };
600
601 pinctrl_usbotg1_4: usbotg1grp-4 {
602 fsl,pins = <
603 MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
604 >;
605 };
606
607 pinctrl_usbotg1_5: usbotg1grp-5 {
608 fsl,pins = <
609 MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
610 >;
611 };
612 };
613
614 usbotg2 {
615 pinctrl_usbotg2_1: usbotg2grp-1 {
616 fsl,pins = <
617 MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
618 >;
619 };
620
621 pinctrl_usbotg2_2: usbotg2grp-2 {
622 fsl,pins = <
623 MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
624 >;
625 };
626
627 pinctrl_usbotg2_3: usbotg2grp-3 {
628 fsl,pins = <
629 MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
630 >;
631 };
632
633 pinctrl_usbotg2_4: usbotg2grp-4 {
634 fsl,pins = <
635 MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
636 >;
637 };
638 };
639
562 usdhc1 { 640 usdhc1 {
563 pinctrl_usdhc1_1: usdhc1grp-1 { 641 pinctrl_usdhc1_1: usdhc1grp-1 {
564 fsl,pins = < 642 fsl,pins = <
@@ -574,6 +652,38 @@
574 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 652 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
575 >; 653 >;
576 }; 654 };
655
656 pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
657 fsl,pins = <
658 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
659 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
660 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
661 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
662 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
663 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
664 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
665 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
666 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
667 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
668 >;
669 };
670
671 pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
672 fsl,pins = <
673 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
674 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
675 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
676 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
677 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
678 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
679 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
680 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
681 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
682 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
683 >;
684 };
685
686
577 }; 687 };
578 688
579 usdhc2 { 689 usdhc2 {
@@ -587,6 +697,29 @@
587 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 697 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
588 >; 698 >;
589 }; 699 };
700
701 pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
702 fsl,pins = <
703 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
704 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
705 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
706 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
707 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
708 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
709 >;
710 };
711
712 pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
713 fsl,pins = <
714 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
715 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
716 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
717 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
718 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
719 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
720 >;
721 };
722
590 }; 723 };
591 724
592 usdhc3 { 725 usdhc3 {
@@ -600,6 +733,28 @@
600 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 733 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
601 >; 734 >;
602 }; 735 };
736
737 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
738 fsl,pins = <
739 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
740 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
741 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
742 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
743 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
744 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
745 >;
746 };
747
748 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
749 fsl,pins = <
750 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
751 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
752 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
753 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
754 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
755 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
756 >;
757 };
603 }; 758 };
604 }; 759 };
605 760
@@ -621,7 +776,8 @@
621 <&clks IMX6SL_CLK_SDMA>; 776 <&clks IMX6SL_CLK_SDMA>;
622 clock-names = "ipg", "ahb"; 777 clock-names = "ipg", "ahb";
623 #dma-cells = <3>; 778 #dma-cells = <3>;
624 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; 779 /* imx6sl reuses imx6q sdma firmware */
780 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
625 }; 781 };
626 782
627 pxp: pxp@020f0000 { 783 pxp: pxp@020f0000 {
@@ -665,7 +821,7 @@
665 usbotg2: usb@02184200 { 821 usbotg2: usb@02184200 {
666 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 822 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
667 reg = <0x02184200 0x200>; 823 reg = <0x02184200 0x200>;
668 interrupts = <0 40 0x04>; 824 interrupts = <0 42 0x04>;
669 clocks = <&clks IMX6SL_CLK_USBOH3>; 825 clocks = <&clks IMX6SL_CLK_USBOH3>;
670 fsl,usbphy = <&usbphy2>; 826 fsl,usbphy = <&usbphy2>;
671 fsl,usbmisc = <&usbmisc 1>; 827 fsl,usbmisc = <&usbmisc 1>;
@@ -675,7 +831,7 @@
675 usbh: usb@02184400 { 831 usbh: usb@02184400 {
676 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 832 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
677 reg = <0x02184400 0x200>; 833 reg = <0x02184400 0x200>;
678 interrupts = <0 42 0x04>; 834 interrupts = <0 40 0x04>;
679 clocks = <&clks IMX6SL_CLK_USBOH3>; 835 clocks = <&clks IMX6SL_CLK_USBOH3>;
680 fsl,usbmisc = <&usbmisc 2>; 836 fsl,usbmisc = <&usbmisc 2>;
681 status = "disabled"; 837 status = "disabled";
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
index 72c4b0a0366f..c39dd766c75a 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -19,7 +19,6 @@
19 compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 19 compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
20 20
21 mbus { 21 mbus {
22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
23 pcie-controller { 22 pcie-controller {
24 status = "okay"; 23 status = "okay";
25 24
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
index 36c411d34926..701c6b6cdaa2 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -19,7 +19,6 @@
19 compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; 19 compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
20 20
21 mbus { 21 mbus {
22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
23 pcie-controller { 22 pcie-controller {
24 status = "okay"; 23 status = "okay";
25 24
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
index c0e2a5879174..053aa20fb30f 100644
--- a/arch/arm/boot/dts/kirkwood-db.dtsi
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -39,28 +39,6 @@
39 status = "ok"; 39 status = "ok";
40 }; 40 };
41 41
42 nand@3000000 {
43 pinctrl-0 = <&pmx_nand>;
44 pinctrl-names = "default";
45 chip-delay = <25>;
46 status = "okay";
47
48 partition@0 {
49 label = "uboot";
50 reg = <0x0 0x100000>;
51 };
52
53 partition@100000 {
54 label = "uImage";
55 reg = <0x100000 0x400000>;
56 };
57
58 partition@500000 {
59 label = "root";
60 reg = <0x500000 0x1fb00000>;
61 };
62 };
63
64 sata@80000 { 42 sata@80000 {
65 nr-ports = <2>; 43 nr-ports = <2>;
66 status = "okay"; 44 status = "okay";
@@ -80,6 +58,28 @@
80 }; 58 };
81}; 59};
82 60
61&nand {
62 pinctrl-0 = <&pmx_nand>;
63 pinctrl-names = "default";
64 chip-delay = <25>;
65 status = "okay";
66
67 partition@0 {
68 label = "uboot";
69 reg = <0x0 0x100000>;
70 };
71
72 partition@100000 {
73 label = "uImage";
74 reg = <0x100000 0x400000>;
75 };
76
77 partition@500000 {
78 label = "root";
79 reg = <0x500000 0x1fb00000>;
80 };
81};
82
83&mdio { 83&mdio {
84 status = "okay"; 84 status = "okay";
85 85
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index d544f77a4ca4..aefa375a550d 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -148,44 +148,6 @@
148 status = "okay"; 148 status = "okay";
149 nr-ports = <2>; 149 nr-ports = <2>;
150 }; 150 };
151
152 nand@3000000 {
153 pinctrl-0 = <&pmx_nand>;
154 pinctrl-names = "default";
155 status = "okay";
156 chip-delay = <35>;
157
158 partition@0 {
159 label = "u-boot";
160 reg = <0x0000000 0x100000>;
161 read-only;
162 };
163
164 partition@100000 {
165 label = "uImage";
166 reg = <0x0100000 0x500000>;
167 };
168
169 partition@600000 {
170 label = "ramdisk";
171 reg = <0x0600000 0x500000>;
172 };
173
174 partition@b00000 {
175 label = "image";
176 reg = <0x0b00000 0x6600000>;
177 };
178
179 partition@7100000 {
180 label = "mini firmware";
181 reg = <0x7100000 0xa00000>;
182 };
183
184 partition@7b00000 {
185 label = "config";
186 reg = <0x7b00000 0x500000>;
187 };
188 };
189 }; 151 };
190 152
191 regulators { 153 regulators {
@@ -220,6 +182,44 @@
220 }; 182 };
221}; 183};
222 184
185&nand {
186 pinctrl-0 = <&pmx_nand>;
187 pinctrl-names = "default";
188 status = "okay";
189 chip-delay = <35>;
190
191 partition@0 {
192 label = "u-boot";
193 reg = <0x0000000 0x100000>;
194 read-only;
195 };
196
197 partition@100000 {
198 label = "uImage";
199 reg = <0x0100000 0x500000>;
200 };
201
202 partition@600000 {
203 label = "ramdisk";
204 reg = <0x0600000 0x500000>;
205 };
206
207 partition@b00000 {
208 label = "image";
209 reg = <0x0b00000 0x6600000>;
210 };
211
212 partition@7100000 {
213 label = "mini firmware";
214 reg = <0x7100000 0xa00000>;
215 };
216
217 partition@7b00000 {
218 label = "config";
219 reg = <0x7b00000 0x500000>;
220 };
221};
222
223&mdio { 223&mdio {
224 status = "okay"; 224 status = "okay";
225 225
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 59a2117c35a7..33ff368fbfa5 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -34,26 +34,6 @@
34 serial@12000 { 34 serial@12000 {
35 status = "ok"; 35 status = "ok";
36 }; 36 };
37
38 nand@3000000 {
39 status = "okay";
40
41 partition@0 {
42 label = "u-boot";
43 reg = <0x0000000 0x100000>;
44 read-only;
45 };
46
47 partition@100000 {
48 label = "uImage";
49 reg = <0x0100000 0x400000>;
50 };
51
52 partition@500000 {
53 label = "data";
54 reg = <0x0500000 0xfb00000>;
55 };
56 };
57 }; 37 };
58 gpio-leds { 38 gpio-leds {
59 compatible = "gpio-leds"; 39 compatible = "gpio-leds";
@@ -91,6 +71,26 @@
91 }; 71 };
92}; 72};
93 73
74&nand {
75 status = "okay";
76
77 partition@0 {
78 label = "u-boot";
79 reg = <0x0000000 0x100000>;
80 read-only;
81 };
82
83 partition@100000 {
84 label = "uImage";
85 reg = <0x0100000 0x400000>;
86 };
87
88 partition@500000 {
89 label = "data";
90 reg = <0x0500000 0xfb00000>;
91 };
92};
93
94&mdio { 94&mdio {
95 status = "okay"; 95 status = "okay";
96 96
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 6f7c7d7ecf2a..a43bebb25110 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -67,31 +67,6 @@
67 status = "ok"; 67 status = "ok";
68 }; 68 };
69 69
70 nand@3000000 {
71 chip-delay = <40>;
72 status = "okay";
73
74 partition@0 {
75 label = "u-boot";
76 reg = <0x0000000 0x100000>;
77 read-only;
78 };
79
80 partition@100000 {
81 label = "uImage";
82 reg = <0x0100000 0x400000>;
83 };
84
85 partition@500000 {
86 label = "pogoplug";
87 reg = <0x0500000 0x2000000>;
88 };
89
90 partition@2500000 {
91 label = "root";
92 reg = <0x02500000 0xd800000>;
93 };
94 };
95 sata@80000 { 70 sata@80000 {
96 status = "okay"; 71 status = "okay";
97 nr-ports = <2>; 72 nr-ports = <2>;
@@ -171,6 +146,32 @@
171 }; 146 };
172}; 147};
173 148
149&nand {
150 chip-delay = <40>;
151 status = "okay";
152
153 partition@0 {
154 label = "u-boot";
155 reg = <0x0000000 0x100000>;
156 read-only;
157 };
158
159 partition@100000 {
160 label = "uImage";
161 reg = <0x0100000 0x400000>;
162 };
163
164 partition@500000 {
165 label = "pogoplug";
166 reg = <0x0500000 0x2000000>;
167 };
168
169 partition@2500000 {
170 label = "root";
171 reg = <0x02500000 0xd800000>;
172 };
173};
174
174&mdio { 175&mdio {
175 status = "okay"; 176 status = "okay";
176 177
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 6548b9dc6855..d30a91a5047d 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -40,26 +40,6 @@
40 status = "ok"; 40 status = "ok";
41 }; 41 };
42 42
43 nand@3000000 {
44 status = "okay";
45
46 partition@0 {
47 label = "u-boot";
48 reg = <0x00000000 0x00100000>;
49 read-only;
50 };
51
52 partition@100000 {
53 label = "uImage";
54 reg = <0x00100000 0x00400000>;
55 };
56
57 partition@500000 {
58 label = "data";
59 reg = <0x00500000 0x1fb00000>;
60 };
61 };
62
63 sata@80000 { 43 sata@80000 {
64 status = "okay"; 44 status = "okay";
65 nr-ports = <1>; 45 nr-ports = <1>;
@@ -97,6 +77,26 @@
97 }; 77 };
98}; 78};
99 79
80&nand {
81 status = "okay";
82
83 partition@0 {
84 label = "u-boot";
85 reg = <0x00000000 0x00100000>;
86 read-only;
87 };
88
89 partition@100000 {
90 label = "uImage";
91 reg = <0x00100000 0x00400000>;
92 };
93
94 partition@500000 {
95 label = "data";
96 reg = <0x00500000 0x1fb00000>;
97 };
98};
99
100&mdio { 100&mdio {
101 status = "okay"; 101 status = "okay";
102 102
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index cb711a3bd983..c5fb02f7ebc3 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -5,7 +5,7 @@
5 5
6/ { 6/ {
7 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; 7 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
8 compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 8 compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9 9
10 memory { 10 memory {
11 device_type = "memory"; 11 device_type = "memory";
@@ -43,6 +43,7 @@
43 marvell,function = "gpio"; 43 marvell,function = "gpio";
44 }; 44 };
45 }; 45 };
46
46 serial@12000 { 47 serial@12000 {
47 status = "okay"; 48 status = "okay";
48 }; 49 };
@@ -51,28 +52,6 @@
51 status = "okay"; 52 status = "okay";
52 nr-ports = <2>; 53 nr-ports = <2>;
53 }; 54 };
54
55 nand@3000000 {
56 status = "okay";
57 pinctrl-0 = <&pmx_nand>;
58 pinctrl-names = "default";
59
60 partition@0 {
61 label = "u-boot";
62 reg = <0x0000000 0x100000>;
63 };
64
65 partition@100000 {
66 label = "uImage";
67 reg = <0x0100000 0x600000>;
68 };
69
70 partition@700000 {
71 label = "root";
72 reg = <0x0700000 0xf900000>;
73 };
74
75 };
76 }; 55 };
77 56
78 gpio_keys { 57 gpio_keys {
@@ -93,6 +72,7 @@
93 gpios = <&gpio0 28 1>; 72 gpios = <&gpio0 28 1>;
94 }; 73 };
95 }; 74 };
75
96 gpio-leds { 76 gpio-leds {
97 compatible = "gpio-leds"; 77 compatible = "gpio-leds";
98 pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green 78 pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green
@@ -113,13 +93,39 @@
113 gpios = <&gpio0 27 0>; 93 gpios = <&gpio0 27 0>;
114 }; 94 };
115 }; 95 };
96
116 gpio_poweroff { 97 gpio_poweroff {
117 compatible = "gpio-poweroff"; 98 compatible = "gpio-poweroff";
118 pinctrl-0 = <&pmx_power_off>; 99 pinctrl-0 = <&pmx_power_off>;
119 pinctrl-names = "default"; 100 pinctrl-names = "default";
120 gpios = <&gpio0 24 0>; 101 gpios = <&gpio0 24 0>;
121 }; 102 };
103};
104
105&nand {
106 status = "okay";
107 pinctrl-0 = <&pmx_nand>;
108 pinctrl-names = "default";
109
110 partition@0 {
111 label = "u-boot";
112 reg = <0x0000000 0xe0000>;
113 };
122 114
115 partition@e0000 {
116 label = "u-boot environment";
117 reg = <0xe0000 0x100000>;
118 };
119
120 partition@100000 {
121 label = "uImage";
122 reg = <0x0100000 0x600000>;
123 };
124
125 partition@700000 {
126 label = "root";
127 reg = <0x0700000 0xf900000>;
128 };
123 129
124}; 130};
125 131
@@ -134,6 +140,7 @@
134 140
135&eth0 { 141&eth0 {
136 status = "okay"; 142 status = "okay";
143
137 ethernet0-port@0 { 144 ethernet0-port@0 {
138 phy-handle = <&ethphy0>; 145 phy-handle = <&ethphy0>;
139 }; 146 };
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 0323f017eeed..4a62b206f680 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -19,7 +19,6 @@
19 }; 19 };
20 20
21 mbus { 21 mbus {
22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
23 pcie-controller { 22 pcie-controller {
24 status = "okay"; 23 status = "okay";
25 24
@@ -83,35 +82,6 @@
83 serial@12000 { 82 serial@12000 {
84 status = "ok"; 83 status = "ok";
85 }; 84 };
86
87 nand@3000000 {
88 status = "okay";
89
90 partition@0 {
91 label = "uboot";
92 reg = <0x0000000 0xc0000>;
93 };
94
95 partition@a0000 {
96 label = "env";
97 reg = <0xa0000 0x20000>;
98 };
99
100 partition@100000 {
101 label = "zImage";
102 reg = <0x100000 0x300000>;
103 };
104
105 partition@540000 {
106 label = "initrd";
107 reg = <0x540000 0x300000>;
108 };
109
110 partition@980000 {
111 label = "boot";
112 reg = <0x980000 0x1f400000>;
113 };
114 };
115 }; 85 };
116 86
117 gpio-leds { 87 gpio-leds {
@@ -180,6 +150,35 @@
180 }; 150 };
181}; 151};
182 152
153&nand {
154 status = "okay";
155
156 partition@0 {
157 label = "uboot";
158 reg = <0x0000000 0xc0000>;
159 };
160
161 partition@a0000 {
162 label = "env";
163 reg = <0xa0000 0x20000>;
164 };
165
166 partition@100000 {
167 label = "zImage";
168 reg = <0x100000 0x300000>;
169 };
170
171 partition@540000 {
172 label = "initrd";
173 reg = <0x540000 0x300000>;
174 };
175
176 partition@980000 {
177 label = "boot";
178 reg = <0x980000 0x1f400000>;
179 };
180};
181
183&mdio { 182&mdio {
184 status = "okay"; 183 status = "okay";
185 184
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index df8447442b37..d15395d671ed 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -113,31 +113,6 @@
113 status = "ok"; 113 status = "ok";
114 }; 114 };
115 115
116 nand@3000000 {
117 status = "okay";
118
119 partition@0 {
120 label = "u-boot";
121 reg = <0x0000000 0x100000>;
122 read-only;
123 };
124
125 partition@a0000 {
126 label = "env";
127 reg = <0xa0000 0x20000>;
128 read-only;
129 };
130
131 partition@100000 {
132 label = "uImage";
133 reg = <0x100000 0x300000>;
134 };
135
136 partition@400000 {
137 label = "uInitrd";
138 reg = <0x540000 0x1000000>;
139 };
140 };
141 sata@80000 { 116 sata@80000 {
142 status = "okay"; 117 status = "okay";
143 nr-ports = <2>; 118 nr-ports = <2>;
@@ -195,6 +170,32 @@
195 }; 170 };
196}; 171};
197 172
173&nand {
174 status = "okay";
175
176 partition@0 {
177 label = "u-boot";
178 reg = <0x0000000 0x100000>;
179 read-only;
180 };
181
182 partition@a0000 {
183 label = "env";
184 reg = <0xa0000 0x20000>;
185 read-only;
186 };
187
188 partition@100000 {
189 label = "uImage";
190 reg = <0x100000 0x300000>;
191 };
192
193 partition@400000 {
194 label = "uInitrd";
195 reg = <0x540000 0x1000000>;
196 };
197};
198
198&mdio { 199&mdio {
199 status = "okay"; 200 status = "okay";
200 201
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 6899408482d2..cd44f37e54b5 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -34,13 +34,6 @@
34 serial@12000 { 34 serial@12000 {
35 status = "ok"; 35 status = "ok";
36 }; 36 };
37
38 nand@3000000 {
39 pinctrl-0 = <&pmx_nand>;
40 pinctrl-names = "default";
41 status = "ok";
42 chip-delay = <25>;
43 };
44 }; 37 };
45 38
46 i2c@0 { 39 i2c@0 {
@@ -51,6 +44,13 @@
51 }; 44 };
52}; 45};
53 46
47&nand {
48 pinctrl-0 = <&pmx_nand>;
49 pinctrl-names = "default";
50 status = "ok";
51 chip-delay = <25>;
52};
53
54&mdio { 54&mdio {
55 status = "okay"; 55 status = "okay";
56 56
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index ce2b94b513db..6c1ec2786e6e 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -17,7 +17,6 @@
17 }; 17 };
18 18
19 mbus { 19 mbus {
20 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
21 pcie-controller { 20 pcie-controller {
22 status = "okay"; 21 status = "okay";
23 22
@@ -96,37 +95,6 @@
96 pinctrl-names = "default"; 95 pinctrl-names = "default";
97 }; 96 };
98 97
99 nand@3000000 {
100 pinctrl-0 = <&pmx_nand>;
101 pinctrl-names = "default";
102 status = "okay";
103
104 partition@0 {
105 label = "uboot";
106 reg = <0x0000000 0x100000>;
107 };
108
109 partition@100000 {
110 label = "env";
111 reg = <0x100000 0x80000>;
112 };
113
114 partition@180000 {
115 label = "fdt";
116 reg = <0x180000 0x80000>;
117 };
118
119 partition@200000 {
120 label = "kernel";
121 reg = <0x200000 0x400000>;
122 };
123
124 partition@600000 {
125 label = "rootfs";
126 reg = <0x600000 0x1fa00000>;
127 };
128 };
129
130 rtc@10300 { 98 rtc@10300 {
131 status = "disabled"; 99 status = "disabled";
132 }; 100 };
@@ -194,6 +162,37 @@
194 }; 162 };
195}; 163};
196 164
165&nand {
166 pinctrl-0 = <&pmx_nand>;
167 pinctrl-names = "default";
168 status = "okay";
169
170 partition@0 {
171 label = "uboot";
172 reg = <0x0000000 0x100000>;
173 };
174
175 partition@100000 {
176 label = "env";
177 reg = <0x100000 0x80000>;
178 };
179
180 partition@180000 {
181 label = "fdt";
182 reg = <0x180000 0x80000>;
183 };
184
185 partition@200000 {
186 label = "kernel";
187 reg = <0x200000 0x400000>;
188 };
189
190 partition@600000 {
191 label = "rootfs";
192 reg = <0x600000 0x1fa00000>;
193 };
194};
195
197&mdio { 196&mdio {
198 status = "okay"; 197 status = "okay";
199 198
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 874857ea9cb8..e6a102cf424c 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -17,7 +17,6 @@
17 }; 17 };
18 18
19 mbus { 19 mbus {
20 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
21 pcie-controller { 20 pcie-controller {
22 status = "okay"; 21 status = "okay";
23 22
@@ -98,36 +97,6 @@
98 status = "okay"; 97 status = "okay";
99 }; 98 };
100 99
101 nand@3000000 {
102 status = "okay";
103
104 partition@0 {
105 label = "u-boot";
106 reg = <0x0000000 0x180000>;
107 read-only;
108 };
109
110 partition@180000 {
111 label = "u-boot-env";
112 reg = <0x180000 0x20000>;
113 };
114
115 partition@200000 {
116 label = "uImage";
117 reg = <0x0200000 0x600000>;
118 };
119
120 partition@800000 {
121 label = "minirootfs";
122 reg = <0x0800000 0x1000000>;
123 };
124
125 partition@1800000 {
126 label = "jffs2";
127 reg = <0x1800000 0x6800000>;
128 };
129 };
130
131 sata@80000 { 100 sata@80000 {
132 status = "okay"; 101 status = "okay";
133 nr-ports = <2>; 102 nr-ports = <2>;
@@ -208,6 +177,36 @@
208 }; 177 };
209}; 178};
210 179
180&nand {
181 status = "okay";
182
183 partition@0 {
184 label = "u-boot";
185 reg = <0x0000000 0x180000>;
186 read-only;
187 };
188
189 partition@180000 {
190 label = "u-boot-env";
191 reg = <0x180000 0x20000>;
192 };
193
194 partition@200000 {
195 label = "uImage";
196 reg = <0x0200000 0x600000>;
197 };
198
199 partition@800000 {
200 label = "minirootfs";
201 reg = <0x0800000 0x1000000>;
202 };
203
204 partition@1800000 {
205 label = "jffs2";
206 reg = <0x1800000 0x6800000>;
207 };
208};
209
211&mdio { 210&mdio {
212 status = "okay"; 211 status = "okay";
213 212
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
index 06267a91de38..e3f915defd3d 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
@@ -27,49 +27,6 @@
27 nr-ports = <2>; 27 nr-ports = <2>;
28 }; 28 };
29 29
30 nand@3000000 {
31 status = "okay";
32 chip-delay = <35>;
33
34 partition@0 {
35 label = "uboot";
36 reg = <0x0000000 0x0100000>;
37 read-only;
38 };
39 partition@100000 {
40 label = "uboot_env";
41 reg = <0x0100000 0x0080000>;
42 };
43 partition@180000 {
44 label = "key_store";
45 reg = <0x0180000 0x0080000>;
46 };
47 partition@200000 {
48 label = "info";
49 reg = <0x0200000 0x0080000>;
50 };
51 partition@280000 {
52 label = "etc";
53 reg = <0x0280000 0x0a00000>;
54 };
55 partition@c80000 {
56 label = "kernel_1";
57 reg = <0x0c80000 0x0a00000>;
58 };
59 partition@1680000 {
60 label = "rootfs1";
61 reg = <0x1680000 0x2fc0000>;
62 };
63 partition@4640000 {
64 label = "kernel_2";
65 reg = <0x4640000 0x0a00000>;
66 };
67 partition@5040000 {
68 label = "rootfs2";
69 reg = <0x5040000 0x2fc0000>;
70 };
71 };
72
73 pcie-controller { 30 pcie-controller {
74 status = "okay"; 31 status = "okay";
75 32
@@ -105,3 +62,46 @@
105 }; 62 };
106 }; 63 };
107}; 64};
65
66&nand {
67 status = "okay";
68 chip-delay = <35>;
69
70 partition@0 {
71 label = "uboot";
72 reg = <0x0000000 0x0100000>;
73 read-only;
74 };
75 partition@100000 {
76 label = "uboot_env";
77 reg = <0x0100000 0x0080000>;
78 };
79 partition@180000 {
80 label = "key_store";
81 reg = <0x0180000 0x0080000>;
82 };
83 partition@200000 {
84 label = "info";
85 reg = <0x0200000 0x0080000>;
86 };
87 partition@280000 {
88 label = "etc";
89 reg = <0x0280000 0x0a00000>;
90 };
91 partition@c80000 {
92 label = "kernel_1";
93 reg = <0x0c80000 0x0a00000>;
94 };
95 partition@1680000 {
96 label = "rootfs1";
97 reg = <0x1680000 0x2fc0000>;
98 };
99 partition@4640000 {
100 label = "kernel_2";
101 reg = <0x4640000 0x0a00000>;
102 };
103 partition@5040000 {
104 label = "rootfs2";
105 reg = <0x5040000 0x2fc0000>;
106 };
107};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 7aeae0c2c1f4..b5418bcaecce 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -15,7 +15,6 @@
15 }; 15 };
16 16
17 mbus { 17 mbus {
18 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
19 pcie-controller { 18 pcie-controller {
20 status = "okay"; 19 status = "okay";
21 20
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 85ccf8d8abb1..f0e3d213604c 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -29,43 +29,6 @@
29 pinctrl-names = "default"; 29 pinctrl-names = "default";
30 }; 30 };
31 31
32 nand@3000000 {
33 chip-delay = <25>;
34 status = "okay";
35 pinctrl-0 = <&pmx_nand>;
36 pinctrl-names = "default";
37
38 partition@0 {
39 label = "uboot";
40 reg = <0x0 0x90000>;
41 };
42
43 partition@90000 {
44 label = "env";
45 reg = <0x90000 0x44000>;
46 };
47
48 partition@d4000 {
49 label = "test";
50 reg = <0xd4000 0x24000>;
51 };
52
53 partition@f4000 {
54 label = "conf";
55 reg = <0xf4000 0x400000>;
56 };
57
58 partition@4f4000 {
59 label = "linux";
60 reg = <0x4f4000 0x1d20000>;
61 };
62
63 partition@2214000 {
64 label = "user";
65 reg = <0x2214000 0x1dec000>;
66 };
67 };
68
69 sata@80000 { 32 sata@80000 {
70 nr-ports = <1>; 33 nr-ports = <1>;
71 status = "okay"; 34 status = "okay";
@@ -167,6 +130,43 @@
167 }; 130 };
168}; 131};
169 132
133&nand {
134 chip-delay = <25>;
135 status = "okay";
136 pinctrl-0 = <&pmx_nand>;
137 pinctrl-names = "default";
138
139 partition@0 {
140 label = "uboot";
141 reg = <0x0 0x90000>;
142 };
143
144 partition@90000 {
145 label = "env";
146 reg = <0x90000 0x44000>;
147 };
148
149 partition@d4000 {
150 label = "test";
151 reg = <0xd4000 0x24000>;
152 };
153
154 partition@f4000 {
155 label = "conf";
156 reg = <0xf4000 0x400000>;
157 };
158
159 partition@4f4000 {
160 label = "linux";
161 reg = <0x4f4000 0x1d20000>;
162 };
163
164 partition@2214000 {
165 label = "user";
166 reg = <0x2214000 0x1dec000>;
167 };
168};
169
170&mdio { 170&mdio {
171 status = "okay"; 171 status = "okay";
172 172
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
new file mode 100644
index 000000000000..851fb2a60f20
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
@@ -0,0 +1,223 @@
1/*
2 * Device Tree file for OpenBlocks A7 board
3 *
4 * Copyright (C) 2013 Free Electrons
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13/dts-v1/;
14
15#include "kirkwood.dtsi"
16#include "kirkwood-6282.dtsi"
17
18/ {
19 model = "Plat'Home OpenBlocksA7";
20 compatible = "plathome,openblocks-a7", "marvell,kirkwood-88f6283", "marvell,kirkwood";
21
22 memory {
23 device_type = "memory";
24 reg = <0x00000000 0x40000000>; /* 1 GB */
25 };
26
27 chosen {
28 bootargs = "console=ttyS0,115200n8 earlyprintk";
29 };
30
31 ocp@f1000000 {
32 serial@12000 {
33 status = "ok";
34 pinctrl-0 = <&pmx_uart0>;
35 pinctrl-names = "default";
36 };
37
38 serial@12100 {
39 status = "ok";
40 pinctrl-0 = <&pmx_uart1>;
41 pinctrl-names = "default";
42 };
43
44 sata@80000 {
45 nr-ports = <1>;
46 status = "okay";
47 };
48
49 i2c@11100 {
50 status = "okay";
51 pinctrl-0 = <&pmx_twsi1>;
52 pinctrl-names = "default";
53
54 s24c02: s24c02@50 {
55 compatible = "24c02";
56 reg = <0x50>;
57 };
58 };
59
60 pinctrl: pinctrl@10000 {
61 pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
62 pinctrl-names = "default";
63
64 pmx_uart0: pmx-uart0 {
65 marvell,pins = "mpp10", "mpp11", "mpp15",
66 "mpp16";
67 marvell,function = "uart0";
68 };
69
70 pmx_uart1: pmx-uart1 {
71 marvell,pins = "mpp13", "mpp14", "mpp8",
72 "mpp9";
73 marvell,function = "uart1";
74 };
75
76 pmx_sysrst: pmx-sysrst {
77 marvell,pins = "mpp6";
78 marvell,function = "sysrst";
79 };
80
81 pmx_dip_switches: pmx-dip-switches {
82 marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47";
83 marvell,function = "gpio";
84 };
85
86 /*
87 * Accessible on connector J202. The MPP
88 * listed below are pin 1-7, pin 8 is unused,
89 * pin 9 is external reset input and pin 10 is
90 * ground.
91 */
92 pmx_gpio_header: pmx-gpio-header {
93 marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28",
94 "mpp35", "mpp34", "mpp40";
95 marvell,function = "gpio";
96 };
97
98 pmx_gpio_init: pmx-init {
99 marvell,pins = "mpp38";
100 marvell,function = "gpio";
101 };
102
103 pmx_usb_oc: pmx-usb-oc {
104 marvell,pins = "mpp39";
105 marvell,function = "gpio";
106 };
107
108 pmx_leds: pmx-leds {
109 marvell,pins = "mpp41", "mpp42", "mpp43";
110 marvell,function = "gpio";
111 };
112
113 pmx_ge1: pmx-ge1 {
114 marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23",
115 "mpp24", "mpp25", "mpp26", "mpp27",
116 "mpp30", "mpp31", "mpp32", "mpp33";
117 marvell,function = "ge1";
118 };
119 };
120 };
121
122 gpio-leds {
123 compatible = "gpio-leds";
124 pinctrl-0 = <&pmx_leds>;
125 pinctrl-names = "default";
126
127 led-red {
128 label = "obsa7:red:stat";
129 gpios = <&gpio1 9 1>;
130 };
131
132 led-green {
133 label = "obsa7:green:stat";
134 gpios = <&gpio1 10 1>;
135 };
136
137 led-yellow {
138 label = "obsa7:yellow:stat";
139 gpios = <&gpio1 11 1>;
140 };
141 };
142
143 gpio_keys {
144 compatible = "gpio-keys";
145 pinctrl-0 = <&pmx_gpio_init>;
146 pinctrl-names = "default";
147 #address-cells = <1>;
148 #size-cells = <0>;
149
150 button@1 {
151 label = "Init Button";
152 linux,code = <116>;
153 gpios = <&gpio1 6 0>;
154 };
155 };
156};
157
158&nand {
159 chip-delay = <25>;
160 status = "okay";
161 pinctrl-0 = <&pmx_nand>;
162 pinctrl-names = "default";
163
164 partition@0 {
165 label = "uboot";
166 reg = <0x0 0x1c0000>;
167 };
168
169 partition@1c0000 {
170 label = "env";
171 reg = <0x1c0000 0x2c0000>;
172 };
173
174 partition@480000 {
175 label = "test";
176 reg = <0x480000 0x160000>;
177 };
178
179 partition@5e0000 {
180 label = "conf";
181 reg = <0x5e0000 0x540000>;
182 };
183
184 partition@b20000 {
185 label = "linux";
186 reg = <0xb20000 0x3d40000>;
187 };
188
189 partition@4860000 {
190 label = "user";
191 reg = <0x4860000 0xb7a0000>;
192 };
193};
194
195&mdio {
196 status = "okay";
197
198 ethphy0: ethernet-phy@0 {
199 device_type = "ethernet-phy";
200 reg = <0>;
201 };
202
203 ethphy1: ethernet-phy@1 {
204 device_type = "ethernet-phy";
205 reg = <1>;
206 };
207};
208
209&eth0 {
210 status = "okay";
211 ethernet0-port@0 {
212 phy-handle = <&ethphy0>;
213 };
214};
215
216&eth1 {
217 status = "okay";
218 pinctrl-0 = <&pmx_ge1>;
219 pinctrl-names = "default";
220 ethernet1-port@0 {
221 phy-handle = <&ethphy1>;
222 };
223};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
index 5696b630b70b..1173d7fb31b2 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -48,27 +48,6 @@
48 pinctrl-names = "default"; 48 pinctrl-names = "default";
49 status = "okay"; 49 status = "okay";
50 }; 50 };
51
52 nand@3000000 {
53 pinctrl-0 = <&pmx_nand>;
54 pinctrl-names = "default";
55 status = "okay";
56
57 partition@0 {
58 label = "u-boot";
59 reg = <0x0000000 0x100000>;
60 };
61
62 partition@100000 {
63 label = "uImage";
64 reg = <0x0100000 0x400000>;
65 };
66
67 partition@500000 {
68 label = "root";
69 reg = <0x0500000 0x1fb00000>;
70 };
71 };
72 }; 51 };
73 52
74 regulators { 53 regulators {
@@ -92,6 +71,27 @@
92 }; 71 };
93}; 72};
94 73
74&nand {
75 pinctrl-0 = <&pmx_nand>;
76 pinctrl-names = "default";
77 status = "okay";
78
79 partition@0 {
80 label = "u-boot";
81 reg = <0x0000000 0x100000>;
82 };
83
84 partition@100000 {
85 label = "uImage";
86 reg = <0x0100000 0x400000>;
87 };
88
89 partition@500000 {
90 label = "root";
91 reg = <0x0500000 0x1fb00000>;
92 };
93};
94
95&mdio { 95&mdio {
96 status = "okay"; 96 status = "okay";
97 97
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 30842b4ff293..320da677b984 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -90,37 +90,6 @@
90 pinctrl-names = "default"; 90 pinctrl-names = "default";
91 }; 91 };
92 92
93 nand@3000000 {
94 status = "okay";
95 pinctrl-0 = <&pmx_nand>;
96 pinctrl-names = "default";
97
98 partition@0 {
99 label = "u-boot";
100 reg = <0x0000000 0x180000>;
101 };
102
103 partition@180000 {
104 label = "u-boot env";
105 reg = <0x0180000 0x20000>;
106 };
107
108 partition@200000 {
109 label = "uImage";
110 reg = <0x0200000 0x600000>;
111 };
112
113 partition@800000 {
114 label = "uInitrd";
115 reg = <0x0800000 0x1000000>;
116 };
117
118 partition@1800000 {
119 label = "rootfs";
120 reg = <0x1800000 0xe800000>;
121 };
122 };
123
124 sata@80000 { 93 sata@80000 {
125 status = "okay"; 94 status = "okay";
126 nr-ports = <1>; 95 nr-ports = <1>;
@@ -204,6 +173,37 @@
204 }; 173 };
205}; 174};
206 175
176&nand {
177 status = "okay";
178 pinctrl-0 = <&pmx_nand>;
179 pinctrl-names = "default";
180
181 partition@0 {
182 label = "u-boot";
183 reg = <0x0000000 0x180000>;
184 };
185
186 partition@180000 {
187 label = "u-boot env";
188 reg = <0x0180000 0x20000>;
189 };
190
191 partition@200000 {
192 label = "uImage";
193 reg = <0x0200000 0x600000>;
194 };
195
196 partition@800000 {
197 label = "uInitrd";
198 reg = <0x0800000 0x1000000>;
199 };
200
201 partition@1800000 {
202 label = "rootfs";
203 reg = <0x1800000 0xe800000>;
204 };
205};
206
207&mdio { 207&mdio {
208 status = "okay"; 208 status = "okay";
209 209
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index 9efcd2dc79d3..345562f75891 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -6,7 +6,6 @@
6 6
7/ { 7/ {
8 mbus { 8 mbus {
9 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
10 pcie-controller { 9 pcie-controller {
11 status = "okay"; 10 status = "okay";
12 11
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 1335b2e1bed4..8b73c80f1dad 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -28,16 +28,43 @@
28 compatible = "marvell,kirkwood-mbus", "simple-bus"; 28 compatible = "marvell,kirkwood-mbus", "simple-bus";
29 #address-cells = <2>; 29 #address-cells = <2>;
30 #size-cells = <1>; 30 #size-cells = <1>;
31 /* If a board file needs to change this ranges it must replace it completely */
32 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
33 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
34 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
35 >;
31 controller = <&mbusc>; 36 controller = <&mbusc>;
32 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ 37 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
33 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ 38 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
39
40 crypto@0301 {
41 compatible = "marvell,orion-crypto";
42 reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>,
43 <MBUS_ID(0x03, 0x01) 0 0x800>;
44 reg-names = "regs", "sram";
45 interrupts = <22>;
46 clocks = <&gate_clk 17>;
47 status = "okay";
48 };
49
50 nand: nand@012f {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 cle = <0>;
54 ale = <1>;
55 bank-width = <1>;
56 compatible = "marvell,orion-nand";
57 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
58 chip-delay = <25>;
59 /* set partition map and/or chip-delay in board dts */
60 clocks = <&gate_clk 7>;
61 status = "disabled";
62 };
34 }; 63 };
35 64
36 ocp@f1000000 { 65 ocp@f1000000 {
37 compatible = "simple-bus"; 66 compatible = "simple-bus";
38 ranges = <0x00000000 0xf1000000 0x0100000 67 ranges = <0x00000000 0xf1000000 0x0100000>;
39 0xf4000000 0xf4000000 0x0000400
40 0xf5000000 0xf5000000 0x0000400>;
41 #address-cells = <1>; 68 #address-cells = <1>;
42 #size-cells = <1>; 69 #size-cells = <1>;
43 70
@@ -193,20 +220,6 @@
193 status = "okay"; 220 status = "okay";
194 }; 221 };
195 222
196 nand@3000000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 cle = <0>;
200 ale = <1>;
201 bank-width = <1>;
202 compatible = "marvell,orion-nand";
203 reg = <0xf4000000 0x400>;
204 chip-delay = <25>;
205 /* set partition map and/or chip-delay in board dts */
206 clocks = <&gate_clk 7>;
207 status = "disabled";
208 };
209
210 i2c@11000 { 223 i2c@11000 {
211 compatible = "marvell,mv64xxx-i2c"; 224 compatible = "marvell,mv64xxx-i2c";
212 reg = <0x11000 0x20>; 225 reg = <0x11000 0x20>;
@@ -218,16 +231,6 @@
218 status = "disabled"; 231 status = "disabled";
219 }; 232 };
220 233
221 crypto@30000 {
222 compatible = "marvell,orion-crypto";
223 reg = <0x30000 0x10000>,
224 <0xf5000000 0x800>;
225 reg-names = "regs", "sram";
226 interrupts = <22>;
227 clocks = <&gate_clk 17>;
228 status = "okay";
229 };
230
231 mdio: mdio-bus@72004 { 234 mdio: mdio-bus@72004 {
232 compatible = "marvell,orion-mdio"; 235 compatible = "marvell,orion-mdio";
233 #address-cells = <1>; 236 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/mxs-pinfunc.h b/arch/arm/boot/dts/mxs-pinfunc.h
new file mode 100644
index 000000000000..c6da987b20cb
--- /dev/null
+++ b/arch/arm/boot/dts/mxs-pinfunc.h
@@ -0,0 +1,31 @@
1/*
2 * Header providing constants for i.MX28 pinctrl bindings.
3 *
4 * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __DT_BINDINGS_MXS_PINCTRL_H__
15#define __DT_BINDINGS_MXS_PINCTRL_H__
16
17/* fsl,drive-strength property */
18#define MXS_DRIVE_4mA 0
19#define MXS_DRIVE_8mA 1
20#define MXS_DRIVE_12mA 2
21#define MXS_DRIVE_16mA 3
22
23/* fsl,voltage property */
24#define MXS_VOLTAGE_LOW 0
25#define MXS_VOLTAGE_HIGH 1
26
27/* fsl,pull-up property */
28#define MXS_PULL_DISABLE 0
29#define MXS_PULL_ENABLE 1
30
31#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
new file mode 100644
index 000000000000..9c18adf788f7
--- /dev/null
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -0,0 +1,52 @@
1/*
2 * Common file for GPMC connected smsc911x on omaps
3 *
4 * Note that the board specifc DTS file needs to specify
5 * ranges, pinctrl, reg, interrupt parent and interrupts.
6 */
7
8/ {
9 vddvario: regulator-vddvario {
10 compatible = "regulator-fixed";
11 regulator-name = "vddvario";
12 regulator-always-on;
13 };
14
15 vdd33a: regulator-vdd33a {
16 compatible = "regulator-fixed";
17 regulator-name = "vdd33a";
18 regulator-always-on;
19 };
20};
21
22&gpmc {
23 ethernet@gpmc {
24 compatible = "smsc,lan9221", "smsc,lan9115";
25 bank-width = <2>;
26 gpmc,mux-add-data;
27 gpmc,cs-on-ns = <0>;
28 gpmc,cs-rd-off-ns = <186>;
29 gpmc,cs-wr-off-ns = <186>;
30 gpmc,adv-on-ns = <12>;
31 gpmc,adv-rd-off-ns = <48>;
32 gpmc,adv-wr-off-ns = <48>;
33 gpmc,oe-on-ns = <54>;
34 gpmc,oe-off-ns = <168>;
35 gpmc,we-on-ns = <54>;
36 gpmc,we-off-ns = <168>;
37 gpmc,rd-cycle-ns = <186>;
38 gpmc,wr-cycle-ns = <186>;
39 gpmc,access-ns = <114>;
40 gpmc,page-burst-access-ns = <6>;
41 gpmc,bus-turnaround-ns = <12>;
42 gpmc,cycle2cycle-delay-ns = <18>;
43 gpmc,wr-data-mux-bus-ns = <90>;
44 gpmc,wr-access-ns = <186>;
45 gpmc,cycle2cycle-samecsen;
46 gpmc,cycle2cycle-diffcsen;
47 vmmc-supply = <&vddvario>;
48 vmmc_aux-supply = <&vdd33a>;
49 reg-io-width = <4>;
50 smsc,save-mac-address;
51 };
52};
diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi
new file mode 100644
index 000000000000..b0ee342598f0
--- /dev/null
+++ b/arch/arm/boot/dts/omap-zoom-common.dtsi
@@ -0,0 +1,33 @@
1/*
2 * Common features on the Zoom debug board
3 */
4
5#include "omap-gpmc-smsc911x.dtsi"
6
7&gpmc {
8 ranges = <3 0 0x10000000 0x00000400>,
9 <7 0 0x2c000000 0x01000000>;
10
11 /*
12 * Four port TL16CP754C serial port on GPMC,
13 * they probably share the same GPIO IRQ
14 * REVISIT: Add timing support from slls644g.pdf
15 */
16 8250@3,0 {
17 compatible = "ns16550a";
18 reg = <3 0 0x100>;
19 bank-width = <2>;
20 reg-shift = <1>;
21 reg-io-width = <1>;
22 interrupt-parent = <&gpio4>;
23 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
24 clock-frequency = <1843200>;
25 current-speed = <115200>;
26 };
27
28 ethernet@gpmc {
29 reg = <7 0 0xff>;
30 interrupt-parent = <&gpio5>;
31 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; /* gpio158 */
32 };
33};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 224c08f472f4..34cdecb4fdda 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -50,15 +50,15 @@
50 label = "bootloader"; 50 label = "bootloader";
51 reg = <0 0x20000>; 51 reg = <0 0x20000>;
52 }; 52 };
53 partition@0x20000 { 53 partition@20000 {
54 label = "params"; 54 label = "params";
55 reg = <0x20000 0x20000>; 55 reg = <0x20000 0x20000>;
56 }; 56 };
57 partition@0x40000 { 57 partition@40000 {
58 label = "kernel"; 58 label = "kernel";
59 reg = <0x40000 0x200000>; 59 reg = <0x40000 0x200000>;
60 }; 60 };
61 partition@0x240000 { 61 partition@240000 {
62 label = "file-system"; 62 label = "file-system";
63 reg = <0x240000 0x3dc0000>; 63 reg = <0x240000 0x3dc0000>;
64 }; 64 };
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index ba4dcfc6b721..31a632f7effb 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -69,6 +69,23 @@
69 }; 69 };
70 70
71 }; 71 };
72
73 /* HS USB Port 2 Power */
74 hsusb2_power: hsusb2_power_reg {
75 compatible = "regulator-fixed";
76 regulator-name = "hsusb2_vbus";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
80 startup-delay-us = <70000>;
81 };
82
83 /* HS USB Host PHY on PORT 2 */
84 hsusb2_phy: hsusb2_phy {
85 compatible = "usb-nop-xceiv";
86 reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
87 vcc-supply = <&hsusb2_power>;
88 };
72}; 89};
73 90
74&omap3_pmx_wkup { 91&omap3_pmx_wkup {
@@ -79,6 +96,37 @@
79 }; 96 };
80}; 97};
81 98
99&omap3_pmx_core {
100 pinctrl-names = "default";
101 pinctrl-0 = <
102 &hsusbb2_pins
103 >;
104
105 uart3_pins: pinmux_uart3_pins {
106 pinctrl-single,pins = <
107 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
108 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
109 >;
110 };
111
112 hsusbb2_pins: pinmux_hsusbb2_pins {
113 pinctrl-single,pins = <
114 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
115 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
116 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
117 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
118 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
119 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
120 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
121 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
122 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
123 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
124 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
125 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
126 >;
127 };
128};
129
82&i2c1 { 130&i2c1 {
83 clock-frequency = <2600000>; 131 clock-frequency = <2600000>;
84 132
@@ -150,15 +198,6 @@
150 power = <50>; 198 power = <50>;
151}; 199};
152 200
153&omap3_pmx_core {
154 uart3_pins: pinmux_uart3_pins {
155 pinctrl-single,pins = <
156 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
157 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
158 >;
159 };
160};
161
162&uart3 { 201&uart3 {
163 pinctrl-names = "default"; 202 pinctrl-names = "default";
164 pinctrl-0 = <&uart3_pins>; 203 pinctrl-0 = <&uart3_pins>;
@@ -168,3 +207,11 @@
168 pinctrl-names = "default"; 207 pinctrl-names = "default";
169 pinctrl-0 = <&gpio1_pins>; 208 pinctrl-0 = <&gpio1_pins>;
170}; 209};
210
211&usbhshost {
212 port2-mode = "ehci-phy";
213};
214
215&usbhsehci {
216 phys = <0 &hsusb2_phy>;
217};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index dfd83103657a..fa532aaacc68 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -44,17 +44,6 @@
44 }; 44 };
45 }; 45 };
46 46
47 /* HS USB Port 2 RESET */
48 hsusb2_reset: hsusb2_reset_reg {
49 compatible = "regulator-fixed";
50 regulator-name = "hsusb2_reset";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 gpio = <&gpio5 19 0>; /* gpio_147 */
54 startup-delay-us = <70000>;
55 enable-active-high;
56 };
57
58 /* HS USB Port 2 Power */ 47 /* HS USB Port 2 Power */
59 hsusb2_power: hsusb2_power_reg { 48 hsusb2_power: hsusb2_power_reg {
60 compatible = "regulator-fixed"; 49 compatible = "regulator-fixed";
@@ -68,7 +57,7 @@
68 /* HS USB Host PHY on PORT 2 */ 57 /* HS USB Host PHY on PORT 2 */
69 hsusb2_phy: hsusb2_phy { 58 hsusb2_phy: hsusb2_phy {
70 compatible = "usb-nop-xceiv"; 59 compatible = "usb-nop-xceiv";
71 reset-supply = <&hsusb2_reset>; 60 reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
72 vcc-supply = <&hsusb2_power>; 61 vcc-supply = <&hsusb2_power>;
73 }; 62 };
74 63
@@ -101,18 +90,18 @@
101 90
102 hsusbb2_pins: pinmux_hsusbb2_pins { 91 hsusbb2_pins: pinmux_hsusbb2_pins {
103 pinctrl-single,pins = < 92 pinctrl-single,pins = <
104 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */ 93 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
105 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */ 94 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
106 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */ 95 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
107 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */ 96 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
108 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */ 97 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
109 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */ 98 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
110 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */ 99 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
111 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */ 100 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
112 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */ 101 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
113 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */ 102 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
114 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */ 103 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
115 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */ 104 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
116 >; 105 >;
117 }; 106 };
118 107
@@ -180,3 +169,12 @@
180 pinctrl-names = "default"; 169 pinctrl-names = "default";
181 pinctrl-0 = <&gpio1_pins>; 170 pinctrl-0 = <&gpio1_pins>;
182}; 171};
172
173&usb_otg_hs {
174 interface-type = <0>;
175 usb-phy = <&usb2_phy>;
176 phys = <&usb2_phy>;
177 phy-names = "usb2-phy";
178 mode = <3>;
179 power = <50>;
180};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 7ef282795dd4..4665421bb7bc 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -125,7 +125,7 @@
125 nand-bus-width = <16>; 125 nand-bus-width = <16>;
126 126
127 gpmc,device-nand; 127 gpmc,device-nand;
128 gpmc,sync-clki-ps = <0>; 128 gpmc,sync-clk-ps = <0>;
129 gpmc,cs-on-ns = <0>; 129 gpmc,cs-on-ns = <0>;
130 gpmc,cs-rd-off-ns = <44>; 130 gpmc,cs-rd-off-ns = <44>;
131 gpmc,cs-wr-off-ns = <44>; 131 gpmc,cs-wr-off-ns = <44>;
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
new file mode 100644
index 000000000000..4df68ad3736a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -0,0 +1,151 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "omap36xx.dtsi"
11#include "omap3-evm-common.dtsi"
12
13
14/ {
15 model = "TI OMAP37XX EVM (TMDSEVM3730)";
16 compatible = "ti,omap3-evm-37xx", "ti,omap36xx";
17
18 memory {
19 device_type = "memory";
20 reg = <0x80000000 0x10000000>; /* 256 MB */
21 };
22
23 wl12xx_vmmc: wl12xx_vmmc {
24 pinctrl-names = "default";
25 pinctrl-0 = <&wl12xx_gpio>;
26 };
27};
28
29&omap3_pmx_core {
30 mmc1_pins: pinmux_mmc1_pins {
31 pinctrl-single,pins = <
32 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
33 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
34 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
35 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
36 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
37 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
38 0x120 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
39 0x122 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
40 0x124 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
41 0x126 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
42 >;
43 };
44
45 /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */
46 mmc2_pins: pinmux_mmc2_pins {
47 pinctrl-single,pins = <
48 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
49 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
50 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
51 0x12e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
52 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
53 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
54 >;
55 };
56
57 uart3_pins: pinmux_uart3_pins {
58 pinctrl-single,pins = <
59 0x16e (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
60 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
61 >;
62 };
63
64 wl12xx_gpio: pinmux_wl12xx_gpio {
65 pinctrl-single,pins = <
66 0x150 (PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */
67 0x14e (PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */
68 >;
69 };
70
71 smsc911x_pins: pinmux_smsc911x_pins {
72 pinctrl-single,pins = <
73 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
74 >;
75 };
76};
77
78&mmc1 {
79 pinctrl-names = "default";
80 pinctrl-0 = <&mmc1_pins>;
81};
82
83&mmc2 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&mmc2_pins>;
86};
87
88&mmc3 {
89 status = "disabled";
90};
91
92&uart3 {
93 pinctrl-names = "default";
94 pinctrl-0 = <&uart3_pins>;
95};
96
97&gpmc {
98 ranges = <0 0 0x00000000 0x20000000>,
99 <5 0 0x2c000000 0x01000000>;
100
101 nand@0,0 {
102 linux,mtd-name= "hynix,h8kds0un0mer-4em";
103 reg = <0 0 0>;
104 nand-bus-width = <16>;
105 ti,nand-ecc-opt = "bch8";
106
107 gpmc,sync-clk-ps = <0>;
108 gpmc,cs-on-ns = <0>;
109 gpmc,cs-rd-off-ns = <44>;
110 gpmc,cs-wr-off-ns = <44>;
111 gpmc,adv-on-ns = <6>;
112 gpmc,adv-rd-off-ns = <34>;
113 gpmc,adv-wr-off-ns = <44>;
114 gpmc,we-off-ns = <40>;
115 gpmc,oe-off-ns = <54>;
116 gpmc,access-ns = <64>;
117 gpmc,rd-cycle-ns = <82>;
118 gpmc,wr-cycle-ns = <82>;
119 gpmc,wr-access-ns = <40>;
120 gpmc,wr-data-mux-bus-ns = <0>;
121
122 #address-cells = <1>;
123 #size-cells = <1>;
124
125 partition@0 {
126 label = "X-Loader";
127 reg = <0 0x80000>;
128 };
129 partition@0x80000 {
130 label = "U-Boot";
131 reg = <0x80000 0x1c0000>;
132 };
133 partition@0x1c0000 {
134 label = "Environment";
135 reg = <0x240000 0x40000>;
136 };
137 partition@0x280000 {
138 label = "Kernel";
139 reg = <0x280000 0x500000>;
140 };
141 partition@0x780000 {
142 label = "Filesystem";
143 reg = <0x780000 0x1f880000>;
144 };
145 };
146
147 ethernet@gpmc {
148 pinctrl-names = "default";
149 pinctrl-0 = <&smsc911x_pins>;
150 };
151};
diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi
new file mode 100644
index 000000000000..3007e79c9cd6
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-evm-common.dtsi
@@ -0,0 +1,96 @@
1/*
2 * Common support for omap3 EVM boards
3 */
4
5#include "omap-gpmc-smsc911x.dtsi"
6
7/ {
8 cpus {
9 cpu@0 {
10 cpu0-supply = <&vcc>;
11 };
12 };
13
14 leds {
15 compatible = "gpio-leds";
16 ledb {
17 label = "omap3evm::ledb";
18 gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
19 linux,default-trigger = "default-on";
20 };
21 };
22
23 wl12xx_vmmc: wl12xx_vmmc {
24 compatible = "regulator-fixed";
25 regulator-name = "vwl1271";
26 regulator-min-microvolt = <1800000>;
27 regulator-max-microvolt = <1800000>;
28 gpio = <&gpio5 22 0>; /* gpio150 */
29 startup-delay-us = <70000>;
30 enable-active-high;
31 vin-supply = <&vmmc2>;
32 };
33};
34
35&i2c1 {
36 clock-frequency = <2600000>;
37
38 twl: twl@48 {
39 reg = <0x48>;
40 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
41 interrupt-parent = <&intc>;
42 };
43};
44
45#include "twl4030.dtsi"
46#include "twl4030_omap3.dtsi"
47
48&i2c2 {
49 clock-frequency = <400000>;
50};
51
52&i2c3 {
53 clock-frequency = <400000>;
54
55 /*
56 * TVP5146 Video decoder-in for analog input support.
57 */
58 tvp5146@5c {
59 compatible = "ti,tvp5146m2";
60 reg = <0x5c>;
61 };
62};
63
64&mmc1 {
65 vmmc-supply = <&vmmc1>;
66 vmmc_aux-supply = <&vsim>;
67 bus-width = <8>;
68};
69
70&mmc2 {
71 vmmc-supply = <&wl12xx_vmmc>;
72 non-removable;
73 bus-width = <4>;
74 cap-power-off-card;
75};
76
77&twl_gpio {
78 ti,use-leds;
79};
80
81&usb_otg_hs {
82 interface-type = <0>;
83 usb-phy = <&usb2_phy>;
84 phys = <&usb2_phy>;
85 phy-names = "usb2-phy";
86 mode = <3>;
87 power = <50>;
88};
89
90&gpmc {
91 ethernet@gpmc {
92 interrupt-parent = <&gpio6>;
93 interrupts = <16 8>;
94 reg = <5 0 0xff>;
95 };
96};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 4134dd05c3a4..e10dcd0fa539 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -8,70 +8,14 @@
8/dts-v1/; 8/dts-v1/;
9 9
10#include "omap34xx.dtsi" 10#include "omap34xx.dtsi"
11#include "omap3-evm-common.dtsi"
11 12
12/ { 13/ {
13 model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; 14 model = "TI OMAP35XX EVM (TMDSEVM3530)";
14 compatible = "ti,omap3-evm", "ti,omap3"; 15 compatible = "ti,omap3-evm", "ti,omap3";
15 16
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vcc>;
19 };
20 };
21
22 memory { 17 memory {
23 device_type = "memory"; 18 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */ 19 reg = <0x80000000 0x10000000>; /* 256 MB */
25 }; 20 };
26
27 leds {
28 compatible = "gpio-leds";
29 ledb {
30 label = "omap3evm::ledb";
31 gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
32 linux,default-trigger = "default-on";
33 };
34 };
35};
36
37&i2c1 {
38 clock-frequency = <2600000>;
39
40 twl: twl@48 {
41 reg = <0x48>;
42 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
43 interrupt-parent = <&intc>;
44 };
45};
46
47#include "twl4030.dtsi"
48#include "twl4030_omap3.dtsi"
49
50&i2c2 {
51 clock-frequency = <400000>;
52};
53
54&i2c3 {
55 clock-frequency = <400000>;
56
57 /*
58 * TVP5146 Video decoder-in for analog input support.
59 */
60 tvp5146@5c {
61 compatible = "ti,tvp5146m2";
62 reg = <0x5c>;
63 };
64};
65
66&twl_gpio {
67 ti,use-leds;
68};
69
70&usb_otg_hs {
71 interface-type = <0>;
72 usb-phy = <&usb2_phy>;
73 phys = <&usb2_phy>;
74 phy-names = "usb2-phy";
75 mode = <3>;
76 power = <50>;
77}; 21};
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts
new file mode 100644
index 000000000000..b9b55c95a566
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04.dts
@@ -0,0 +1,170 @@
1/*
2 * Copyright (C) 2013 Marek Belisko <marek@goldelico.com>
3 *
4 * Based on omap3-beagle-xm.dts
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10/dts-v1/;
11
12#include "omap36xx.dtsi"
13
14/ {
15 model = "OMAP3 GTA04";
16 compatible = "ti,omap3-gta04", "ti,omap3";
17
18 cpus {
19 cpu@0 {
20 cpu0-supply = <&vcc>;
21 };
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x20000000>; /* 512 MB */
27 };
28
29 gpio-keys {
30 compatible = "gpio-keys";
31
32 aux-button {
33 label = "aux";
34 linux,code = <169>;
35 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
36 gpio-key,wakeup;
37 };
38 };
39};
40
41&omap3_pmx_core {
42 uart1_pins: pinmux_uart1_pins {
43 pinctrl-single,pins = <
44 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
45 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */
46 >;
47 };
48
49 uart2_pins: pinmux_uart2_pins {
50 pinctrl-single,pins = <
51 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
52 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
53 >;
54 };
55
56 uart3_pins: pinmux_uart3_pins {
57 pinctrl-single,pins = <
58 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
59 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
60 >;
61 };
62
63 mmc1_pins: pinmux_mmc1_pins {
64 pinctrl-single,pins = <
65 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
66 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
67 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
68 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
69 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
70 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
71 >;
72 };
73};
74
75&i2c1 {
76 clock-frequency = <2600000>;
77
78 twl: twl@48 {
79 reg = <0x48>;
80 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
81 interrupt-parent = <&intc>;
82 };
83};
84
85#include "twl4030.dtsi"
86#include "twl4030_omap3.dtsi"
87
88&i2c2 {
89 clock-frequency = <400000>;
90
91 /* pressure sensor */
92 bmp085@77 {
93 compatible = "bosch,bmp085";
94 reg = <0x77>;
95 };
96
97 /* leds */
98 tca6507@45 {
99 compatible = "ti,tca6507";
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0x45>;
103
104 gta04_led0: red_aux@0 {
105 label = "gta04:red:aux";
106 reg = <0x0>;
107 };
108
109 gta04_led1: green_aux@1 {
110 label = "gta04:green:aux";
111 reg = <0x1>;
112 };
113
114 gta04_led3: red_power@3 {
115 label = "gta04:red:power";
116 reg = <0x3>;
117 linux,default-trigger = "default-on";
118 };
119
120 gta04_led4: green_power@4 {
121 label = "gta04:green:power";
122 reg = <0x4>;
123 };
124 };
125};
126
127&i2c3 {
128 clock-frequency = <100000>;
129};
130
131&usb_otg_hs {
132 interface-type = <0>;
133 usb-phy = <&usb2_phy>;
134 phys = <&usb2_phy>;
135 phy-names = "usb2-phy";
136 mode = <3>;
137 power = <50>;
138};
139
140&mmc1 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&mmc1_pins>;
143 vmmc-supply = <&vmmc1>;
144 vmmc_aux-supply = <&vsim>;
145 bus-width = <4>;
146};
147
148&mmc2 {
149 status = "disabled";
150};
151
152&mmc3 {
153 status = "disabled";
154};
155
156&uart1 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&uart1_pins>;
159};
160
161&uart2 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&uart2_pins>;
164};
165
166&uart3 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&uart3_pins>;
169};
170
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 2326d11462a5..ba1e58b7b7e3 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -77,6 +77,8 @@
77 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 77 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
78 >; 78 >;
79 }; 79 };
80
81 leds_pins: pinmux_leds_pins { };
80}; 82};
81 83
82&i2c1 { 84&i2c1 {
@@ -141,3 +143,12 @@
141&twl_gpio { 143&twl_gpio {
142 ti,use-leds; 144 ti,use-leds;
143}; 145};
146
147&usb_otg_hs {
148 interface-type = <0>;
149 usb-phy = <&usb2_phy>;
150 phys = <&usb2_phy>;
151 phy-names = "usb2-phy";
152 mode = <3>;
153 power = <50>;
154};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index e8c48284587c..d5cc79267250 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -10,13 +10,17 @@
10 */ 10 */
11 11
12#include "omap3-igep.dtsi" 12#include "omap3-igep.dtsi"
13#include "omap-gpmc-smsc911x.dtsi"
13 14
14/ { 15/ {
15 model = "IGEPv2"; 16 model = "IGEPv2";
16 compatible = "isee,omap3-igep0020", "ti,omap3"; 17 compatible = "isee,omap3-igep0020", "ti,omap3";
17 18
18 leds { 19 leds {
20 pinctrl-names = "default";
21 pinctrl-0 = <&leds_pins>;
19 compatible = "gpio-leds"; 22 compatible = "gpio-leds";
23
20 boot { 24 boot {
21 label = "omap3:green:boot"; 25 label = "omap3:green:boot";
22 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 26 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
@@ -41,19 +45,56 @@
41 }; 45 };
42 }; 46 };
43 47
44 vddvario: regulator-vddvario { 48 /* HS USB Port 1 Power */
45 compatible = "regulator-fixed"; 49 hsusb1_power: hsusb1_power_reg {
46 regulator-name = "vddvario"; 50 compatible = "regulator-fixed";
47 regulator-always-on; 51 regulator-name = "hsusb1_vbus";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
54 gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
55 startup-delay-us = <70000>;
56 };
57
58 /* HS USB Host PHY on PORT 1 */
59 hsusb1_phy: hsusb1_phy {
60 compatible = "usb-nop-xceiv";
61 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
62 vcc-supply = <&hsusb1_power>;
48 }; 63 };
64};
49 65
50 vdd33a: regulator-vdd33a { 66&omap3_pmx_core {
51 compatible = "regulator-fixed"; 67 pinctrl-names = "default";
52 regulator-name = "vdd33a"; 68 pinctrl-0 = <
53 regulator-always-on; 69 &hsusbb1_pins
70 >;
71
72 hsusbb1_pins: pinmux_hsusbb1_pins {
73 pinctrl-single,pins = <
74 0x5aa (PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
75 0x5a8 (PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
76 0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
77 0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
78 0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
79 0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
80 0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
81 0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
82 0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
83 0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
84 0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
85 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
86 >;
54 }; 87 };
55}; 88};
56 89
90&leds_pins {
91 pinctrl-single,pins = <
92 0x5c4 (PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
93 0x5c6 (PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
94 0x5c8 (PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
95 >;
96};
97
57&i2c3 { 98&i2c3 {
58 clock-frequency = <100000>; 99 clock-frequency = <100000>;
59 100
@@ -99,59 +140,37 @@
99 label = "SPL"; 140 label = "SPL";
100 reg = <0 0x100000>; 141 reg = <0 0x100000>;
101 }; 142 };
102 partition@0x80000 { 143 partition@80000 {
103 label = "U-Boot"; 144 label = "U-Boot";
104 reg = <0x100000 0x180000>; 145 reg = <0x100000 0x180000>;
105 }; 146 };
106 partition@0x1c0000 { 147 partition@1c0000 {
107 label = "Environment"; 148 label = "Environment";
108 reg = <0x280000 0x100000>; 149 reg = <0x280000 0x100000>;
109 }; 150 };
110 partition@0x280000 { 151 partition@280000 {
111 label = "Kernel"; 152 label = "Kernel";
112 reg = <0x380000 0x300000>; 153 reg = <0x380000 0x300000>;
113 }; 154 };
114 partition@0x780000 { 155 partition@780000 {
115 label = "Filesystem"; 156 label = "Filesystem";
116 reg = <0x680000 0x1f980000>; 157 reg = <0x680000 0x1f980000>;
117 }; 158 };
118 }; 159 };
119 160
120 ethernet@5,0 { 161 ethernet@gpmc {
121 pinctrl-names = "default"; 162 pinctrl-names = "default";
122 pinctrl-0 = <&smsc911x_pins>; 163 pinctrl-0 = <&smsc911x_pins>;
123 compatible = "smsc,lan9221", "smsc,lan9115";
124 reg = <5 0 0xff>; 164 reg = <5 0 0xff>;
125 bank-width = <2>;
126
127 gpmc,mux-add-data;
128 gpmc,cs-on-ns = <0>;
129 gpmc,cs-rd-off-ns = <186>;
130 gpmc,cs-wr-off-ns = <186>;
131 gpmc,adv-on-ns = <12>;
132 gpmc,adv-rd-off-ns = <48>;
133 gpmc,adv-wr-off-ns = <48>;
134 gpmc,oe-on-ns = <54>;
135 gpmc,oe-off-ns = <168>;
136 gpmc,we-on-ns = <54>;
137 gpmc,we-off-ns = <168>;
138 gpmc,rd-cycle-ns = <186>;
139 gpmc,wr-cycle-ns = <186>;
140 gpmc,access-ns = <114>;
141 gpmc,page-burst-access-ns = <6>;
142 gpmc,bus-turnaround-ns = <12>;
143 gpmc,cycle2cycle-delay-ns = <18>;
144 gpmc,wr-data-mux-bus-ns = <90>;
145 gpmc,wr-access-ns = <186>;
146 gpmc,cycle2cycle-samecsen;
147 gpmc,cycle2cycle-diffcsen;
148
149 interrupt-parent = <&gpio6>; 165 interrupt-parent = <&gpio6>;
150 interrupts = <16 8>; 166 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
151 vmmc-supply = <&vddvario>;
152 vmmc_aux-supply = <&vdd33a>;
153 reg-io-width = <4>;
154
155 smsc,save-mac-address;
156 }; 167 };
157}; 168};
169
170&usbhshost {
171 port1-mode = "ehci-phy";
172};
173
174&usbhsehci {
175 phys = <&hsusb1_phy>;
176};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 644d05383836..525e6d9b0978 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -16,7 +16,10 @@
16 compatible = "isee,omap3-igep0030", "ti,omap3"; 16 compatible = "isee,omap3-igep0030", "ti,omap3";
17 17
18 leds { 18 leds {
19 pinctrl-names = "default";
20 pinctrl-0 = <&leds_pins>;
19 compatible = "gpio-leds"; 21 compatible = "gpio-leds";
22
20 boot { 23 boot {
21 label = "omap3:green:boot"; 24 label = "omap3:green:boot";
22 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; 25 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
@@ -43,6 +46,12 @@
43 }; 46 };
44}; 47};
45 48
49&leds_pins {
50 pinctrl-single,pins = <
51 0x5b0 (PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
52 >;
53};
54
46&gpmc { 55&gpmc {
47 ranges = <0 0 0x00000000 0x20000000>; 56 ranges = <0 0 0x00000000 0x20000000>;
48 57
@@ -74,19 +83,19 @@
74 label = "SPL"; 83 label = "SPL";
75 reg = <0 0x100000>; 84 reg = <0 0x100000>;
76 }; 85 };
77 partition@0x80000 { 86 partition@80000 {
78 label = "U-Boot"; 87 label = "U-Boot";
79 reg = <0x100000 0x180000>; 88 reg = <0x100000 0x180000>;
80 }; 89 };
81 partition@0x1c0000 { 90 partition@1c0000 {
82 label = "Environment"; 91 label = "Environment";
83 reg = <0x280000 0x100000>; 92 reg = <0x280000 0x100000>;
84 }; 93 };
85 partition@0x280000 { 94 partition@280000 {
86 label = "Kernel"; 95 label = "Kernel";
87 reg = <0x380000 0x300000>; 96 reg = <0x380000 0x300000>;
88 }; 97 };
89 partition@0x780000 { 98 partition@780000 {
90 label = "Filesystem"; 99 label = "Filesystem";
91 reg = <0x680000 0x1f980000>; 100 reg = <0x680000 0x1f980000>;
92 }; 101 };
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
new file mode 100644
index 000000000000..39828ce464ee
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -0,0 +1,18 @@
1/*
2 * omap3-n9.dts - Device Tree file for Nokia N9
3 *
4 * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/dts-v1/;
12
13#include "omap3-n950-n9.dtsi"
14
15/ {
16 model = "Nokia N9";
17 compatible = "nokia,omap3-n9", "ti,omap3";
18};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
new file mode 100644
index 000000000000..c4f20bfe4cce
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -0,0 +1,484 @@
1/*
2 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
3 * Copyright 2013 Aaro Koskinen <aaro.koskinen@iki.fi>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 (or later) as
7 * published by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
12#include "omap34xx.dtsi"
13
14/ {
15 model = "Nokia N900";
16 compatible = "nokia,omap3-n900", "ti,omap3";
17
18 cpus {
19 cpu@0 {
20 cpu0-supply = <&vcc>;
21 };
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x10000000>; /* 256 MB */
27 };
28
29 gpio_keys {
30 compatible = "gpio-keys";
31
32 camera_lens_cover {
33 label = "Camera Lens Cover";
34 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
35 linux,input-type = <5>; /* EV_SW */
36 linux,code = <0x09>; /* SW_CAMERA_LENS_COVER */
37 gpio-key,wakeup;
38 };
39
40 camera_focus {
41 label = "Camera Focus";
42 gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
43 linux,code = <0x210>; /* KEY_CAMERA_FOCUS */
44 gpio-key,wakeup;
45 };
46
47 camera_capture {
48 label = "Camera Capture";
49 gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
50 linux,code = <0xd4>; /* KEY_CAMERA */
51 gpio-key,wakeup;
52 };
53
54 lock_button {
55 label = "Lock Button";
56 gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
57 linux,code = <0x98>; /* KEY_SCREENLOCK */
58 gpio-key,wakeup;
59 };
60
61 keypad_slide {
62 label = "Keypad Slide";
63 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
64 linux,input-type = <5>; /* EV_SW */
65 linux,code = <0x0a>; /* SW_KEYPAD_SLIDE */
66 gpio-key,wakeup;
67 };
68
69 proximity_sensor {
70 label = "Proximity Sensor";
71 gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
72 linux,input-type = <5>; /* EV_SW */
73 linux,code = <0x0b>; /* SW_FRONT_PROXIMITY */
74 };
75 };
76
77};
78
79&omap3_pmx_core {
80 pinctrl-names = "default";
81
82 uart2_pins: pinmux_uart2_pins {
83 pinctrl-single,pins = <
84 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx */
85 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
86 >;
87 };
88
89 uart3_pins: pinmux_uart3_pins {
90 pinctrl-single,pins = <
91 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx */
92 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
93 >;
94 };
95
96 i2c1_pins: pinmux_i2c1_pins {
97 pinctrl-single,pins = <
98 0x18a (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
99 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
100 >;
101 };
102
103 i2c2_pins: pinmux_i2c2_pins {
104 pinctrl-single,pins = <
105 0x18e (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
106 0x190 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
107 >;
108 };
109
110 i2c3_pins: pinmux_i2c3_pins {
111 pinctrl-single,pins = <
112 0x192 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
113 0x194 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
114 >;
115 };
116
117 mmc1_pins: pinmux_mmc1_pins {
118 pinctrl-single,pins = <
119 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
120 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
121 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
122 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
123 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
124 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
125 >;
126 };
127
128 display_pins: pinmux_display_pins {
129 pinctrl-single,pins = <
130 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
131 >;
132 };
133};
134
135&i2c1 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&i2c1_pins>;
138
139 clock-frequency = <2200000>;
140
141 twl: twl@48 {
142 reg = <0x48>;
143 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
144 interrupt-parent = <&intc>;
145 };
146};
147
148#include "twl4030.dtsi"
149#include "twl4030_omap3.dtsi"
150
151&vaux1 {
152 regulator-name = "V28";
153 regulator-min-microvolt = <2800000>;
154 regulator-max-microvolt = <2800000>;
155 regulator-always-on; /* due battery cover sensor */
156};
157
158&vaux2 {
159 regulator-name = "VCSI";
160 regulator-min-microvolt = <1800000>;
161 regulator-max-microvolt = <1800000>;
162};
163
164&vaux3 {
165 regulator-name = "VMMC2_30";
166 regulator-min-microvolt = <2800000>;
167 regulator-max-microvolt = <3000000>;
168};
169
170&vaux4 {
171 regulator-name = "VCAM_ANA_28";
172 regulator-min-microvolt = <2800000>;
173 regulator-max-microvolt = <2800000>;
174};
175
176&vmmc1 {
177 regulator-name = "VMMC1";
178 regulator-min-microvolt = <1850000>;
179 regulator-max-microvolt = <3150000>;
180};
181
182&vmmc2 {
183 regulator-name = "V28_A";
184 regulator-min-microvolt = <2800000>;
185 regulator-max-microvolt = <3000000>;
186 regulator-always-on; /* due VIO leak to AIC34 VDDs */
187};
188
189&vpll1 {
190 regulator-name = "VPLL";
191 regulator-min-microvolt = <1800000>;
192 regulator-max-microvolt = <1800000>;
193 regulator-always-on;
194};
195
196&vpll2 {
197 regulator-name = "VSDI_CSI";
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <1800000>;
200 regulator-always-on;
201};
202
203&vsim {
204 regulator-name = "VMMC2_IO_18";
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <1800000>;
207};
208
209&vio {
210 regulator-name = "VIO";
211 regulator-min-microvolt = <1800000>;
212 regulator-max-microvolt = <1800000>;
213
214};
215
216&vintana1 {
217 regulator-name = "VINTANA1";
218 /* fixed to 1500000 */
219 regulator-always-on;
220};
221
222&vintana2 {
223 regulator-name = "VINTANA2";
224 regulator-min-microvolt = <2750000>;
225 regulator-max-microvolt = <2750000>;
226 regulator-always-on;
227};
228
229&vintdig {
230 regulator-name = "VINTDIG";
231 /* fixed to 1500000 */
232 regulator-always-on;
233};
234
235&twl {
236 twl_audio: audio {
237 compatible = "ti,twl4030-audio";
238 ti,enable-vibra = <1>;
239 };
240};
241
242&twl_gpio {
243 ti,pullups = <0x0>;
244 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
245};
246
247&i2c2 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&i2c2_pins>;
250
251 clock-frequency = <100000>;
252
253 tlv320aic3x: tlv320aic3x@18 {
254 compatible = "ti,tlv320aic3x";
255 reg = <0x18>;
256 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
257 ai3x-gpio-func = <
258 0 /* AIC3X_GPIO1_FUNC_DISABLED */
259 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
260 >;
261
262 AVDD-supply = <&vmmc2>;
263 DRVDD-supply = <&vmmc2>;
264 IOVDD-supply = <&vio>;
265 DVDD-supply = <&vio>;
266 };
267
268 tlv320aic3x_aux: tlv320aic3x@19 {
269 compatible = "ti,tlv320aic3x";
270 reg = <0x19>;
271 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
272
273 AVDD-supply = <&vmmc2>;
274 DRVDD-supply = <&vmmc2>;
275 IOVDD-supply = <&vio>;
276 DVDD-supply = <&vio>;
277 };
278
279 lp5523: lp5523@32 {
280 compatible = "national,lp5523";
281 reg = <0x32>;
282 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
283 enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
284
285 chan0 {
286 chan-name = "lp5523:kb1";
287 led-cur = /bits/ 8 <50>;
288 max-cur = /bits/ 8 <100>;
289 };
290
291 chan1 {
292 chan-name = "lp5523:kb2";
293 led-cur = /bits/ 8 <50>;
294 max-cur = /bits/ 8 <100>;
295 };
296
297 chan2 {
298 chan-name = "lp5523:kb3";
299 led-cur = /bits/ 8 <50>;
300 max-cur = /bits/ 8 <100>;
301 };
302
303 chan3 {
304 chan-name = "lp5523:kb4";
305 led-cur = /bits/ 8 <50>;
306 max-cur = /bits/ 8 <100>;
307 };
308
309 chan4 {
310 chan-name = "lp5523:b";
311 led-cur = /bits/ 8 <50>;
312 max-cur = /bits/ 8 <100>;
313 };
314
315 chan5 {
316 chan-name = "lp5523:g";
317 led-cur = /bits/ 8 <50>;
318 max-cur = /bits/ 8 <100>;
319 };
320
321 chan6 {
322 chan-name = "lp5523:r";
323 led-cur = /bits/ 8 <50>;
324 max-cur = /bits/ 8 <100>;
325 };
326
327 chan7 {
328 chan-name = "lp5523:kb5";
329 led-cur = /bits/ 8 <50>;
330 max-cur = /bits/ 8 <100>;
331 };
332
333 chan8 {
334 chan-name = "lp5523:kb6";
335 led-cur = /bits/ 8 <50>;
336 max-cur = /bits/ 8 <100>;
337 };
338 };
339
340 bq27200: bq27200@55 {
341 compatible = "ti,bq27200";
342 reg = <0x55>;
343 };
344};
345
346&i2c3 {
347 pinctrl-names = "default";
348 pinctrl-0 = <&i2c3_pins>;
349
350 clock-frequency = <400000>;
351};
352
353&mmc1 {
354 pinctrl-names = "default";
355 pinctrl-0 = <&mmc1_pins>;
356 vmmc-supply = <&vmmc1>;
357 bus-width = <4>;
358 cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
359};
360
361&mmc2 {
362 status = "disabled";
363};
364
365&mmc3 {
366 status = "disabled";
367};
368
369&gpmc {
370 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
371
372 /* gpio-irq for dma: 65 */
373
374 onenand@0,0 {
375 #address-cells = <1>;
376 #size-cells = <1>;
377 reg = <0 0 0x10000000>;
378
379 gpmc,sync-read;
380 gpmc,sync-write;
381 gpmc,burst-length = <16>;
382 gpmc,burst-read;
383 gpmc,burst-wrap;
384 gpmc,burst-write;
385 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
386 gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
387 gpmc,cs-on-ns = <0>;
388 gpmc,cs-rd-off-ns = <87>;
389 gpmc,cs-wr-off-ns = <87>;
390 gpmc,adv-on-ns = <0>;
391 gpmc,adv-rd-off-ns = <10>;
392 gpmc,adv-wr-off-ns = <10>;
393 gpmc,oe-on-ns = <15>;
394 gpmc,oe-off-ns = <87>;
395 gpmc,we-on-ns = <0>;
396 gpmc,we-off-ns = <87>;
397 gpmc,rd-cycle-ns = <112>;
398 gpmc,wr-cycle-ns = <112>;
399 gpmc,access-ns = <81>;
400 gpmc,page-burst-access-ns = <15>;
401 gpmc,bus-turnaround-ns = <0>;
402 gpmc,cycle2cycle-delay-ns = <0>;
403 gpmc,wait-monitoring-ns = <0>;
404 gpmc,clk-activation-ns = <5>;
405 gpmc,wr-data-mux-bus-ns = <30>;
406 gpmc,wr-access-ns = <81>;
407 gpmc,sync-clk-ps = <15000>;
408
409 /*
410 * MTD partition table corresponding to Nokia's
411 * Maemo 5 (Fremantle) release.
412 */
413 partition@0 {
414 label = "bootloader";
415 reg = <0x00000000 0x00020000>;
416 read-only;
417 };
418 partition@1 {
419 label = "config";
420 reg = <0x00020000 0x00060000>;
421 };
422 partition@2 {
423 label = "log";
424 reg = <0x00080000 0x00040000>;
425 };
426 partition@3 {
427 label = "kernel";
428 reg = <0x000c0000 0x00200000>;
429 };
430 partition@4 {
431 label = "initfs";
432 reg = <0x002c0000 0x00200000>;
433 };
434 partition@5 {
435 label = "rootfs";
436 reg = <0x004c0000 0x0fb40000>;
437 };
438 };
439};
440
441&mcspi1 {
442 /*
443 * For some reason, touchscreen is necessary for screen to work at
444 * all on real hw. It works well without it on emulator.
445 *
446 * Also... order in the device tree actually matters here.
447 */
448 tsc2005@0 {
449 compatible = "tsc2005";
450 spi-max-frequency = <6000000>;
451 reg = <0>;
452 };
453 mipid@2 {
454 compatible = "acx565akm";
455 spi-max-frequency = <6000000>;
456 reg = <2>;
457
458 pinctrl-names = "default";
459 pinctrl-0 = <&display_pins>;
460 };
461};
462
463&usb_otg_hs {
464 interface-type = <0>;
465 usb-phy = <&usb2_phy>;
466 phys = <&usb2_phy>;
467 phy-names = "usb2-phy";
468 mode = <2>;
469 power = <50>;
470};
471
472&uart1 {
473 status = "disabled";
474};
475
476&uart2 {
477 pinctrl-names = "default";
478 pinctrl-0 = <&uart2_pins>;
479};
480
481&uart3 {
482 pinctrl-names = "default";
483 pinctrl-0 = <&uart3_pins>;
484};
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
new file mode 100644
index 000000000000..94eb77d3b9dd
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -0,0 +1,174 @@
1/*
2 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
3 *
4 * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include "omap36xx.dtsi"
12
13/ {
14 cpus {
15 cpu@0 {
16 cpu0-supply = <&vcc>;
17 };
18 };
19
20 memory {
21 device_type = "memory";
22 reg = <0x80000000 0x40000000>; /* 1 GB */
23 };
24
25 vemmc: fixedregulator@0 {
26 compatible = "regulator-fixed";
27 regulator-name = "VEMMC";
28 regulator-min-microvolt = <2900000>;
29 regulator-max-microvolt = <2900000>;
30 gpio = <&gpio5 29 0>; /* gpio line 157 */
31 startup-delay-us = <150>;
32 enable-active-high;
33 };
34};
35
36&omap3_pmx_core {
37 mmc2_pins: pinmux_mmc2_pins {
38 pinctrl-single,pins = <
39 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
40 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
41 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
42 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
43 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
44 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
45 >;
46 };
47};
48
49&i2c1 {
50 clock-frequency = <2900000>;
51
52 twl: twl@48 {
53 reg = <0x48>;
54 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
55 interrupt-parent = <&intc>;
56 };
57};
58
59/include/ "twl4030.dtsi"
60
61&twl {
62 compatible = "ti,twl5031";
63};
64
65&twl_gpio {
66 ti,pullups = <0x000001>; /* BIT(0) */
67 ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */
68};
69
70&i2c2 {
71 clock-frequency = <400000>;
72};
73
74&i2c3 {
75 clock-frequency = <400000>;
76};
77
78&mmc1 {
79 status = "disabled";
80};
81
82&mmc2 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&mmc2_pins>;
85 vmmc-supply = <&vemmc>;
86 bus-width = <4>;
87 ti,non-removable;
88};
89
90&mmc3 {
91 status = "disabled";
92};
93
94&usb_otg_hs {
95 interface-type = <0>;
96 usb-phy = <&usb2_phy>;
97 phys = <&usb2_phy>;
98 phy-names = "usb2-phy";
99 mode = <3>;
100 power = <50>;
101};
102
103&gpmc {
104 ranges = <0 0 0x04000000 0x20000000>;
105
106 onenand@0,0 {
107 #address-cells = <1>;
108 #size-cells = <1>;
109 reg = <0 0 0x20000000>;
110
111 gpmc,sync-read;
112 gpmc,sync-write;
113 gpmc,burst-length = <16>;
114 gpmc,burst-read;
115 gpmc,burst-wrap;
116 gpmc,burst-write;
117 gpmc,device-width = <2>;
118 gpmc,mux-add-data = <2>;
119 gpmc,cs-on-ns = <0>;
120 gpmc,cs-rd-off-ns = <87>;
121 gpmc,cs-wr-off-ns = <87>;
122 gpmc,adv-on-ns = <0>;
123 gpmc,adv-rd-off-ns = <10>;
124 gpmc,adv-wr-off-ns = <10>;
125 gpmc,oe-on-ns = <15>;
126 gpmc,oe-off-ns = <87>;
127 gpmc,we-on-ns = <0>;
128 gpmc,we-off-ns = <87>;
129 gpmc,rd-cycle-ns = <112>;
130 gpmc,wr-cycle-ns = <112>;
131 gpmc,access-ns = <81>;
132 gpmc,page-burst-access-ns = <15>;
133 gpmc,bus-turnaround-ns = <0>;
134 gpmc,cycle2cycle-delay-ns = <0>;
135 gpmc,wait-monitoring-ns = <0>;
136 gpmc,clk-activation-ns = <5>;
137 gpmc,wr-data-mux-bus-ns = <30>;
138 gpmc,wr-access-ns = <81>;
139 gpmc,sync-clk-ps = <15000>;
140
141 /*
142 * MTD partition table corresponding to Nokia's MeeGo 1.2
143 * Harmattan release.
144 */
145 partition@0 {
146 label = "bootloader";
147 reg = <0x00000000 0x00100000>;
148 };
149 partition@1 {
150 label = "config";
151 reg = <0x00100000 0x002c0000>;
152 };
153 partition@2 {
154 label = "kernel";
155 reg = <0x003c0000 0x01000000>;
156 };
157 partition@3 {
158 label = "log";
159 reg = <0x013c0000 0x00200000>;
160 };
161 partition@4 {
162 label = "var";
163 reg = <0x015c0000 0x1ca40000>;
164 };
165 partition@5 {
166 label = "moslo";
167 reg = <0x1e000000 0x02000000>;
168 };
169 partition@6 {
170 label = "omap2-onenand";
171 reg = <0x00000000 0x20000000>;
172 };
173 };
174};
diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
new file mode 100644
index 000000000000..b076a526b999
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-n950.dts
@@ -0,0 +1,18 @@
1/*
2 * omap3-n950.dts - Device Tree file for Nokia N950
3 *
4 * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/dts-v1/;
12
13#include "omap3-n950-n9.dtsi"
14
15/ {
16 model = "Nokia N950";
17 compatible = "nokia,omap3-n950", "ti,omap3";
18};
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
new file mode 100644
index 000000000000..15eb9fe5169c
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-zoom3.dts
@@ -0,0 +1,217 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "omap36xx.dtsi"
11#include "omap-zoom-common.dtsi"
12
13/ {
14 model = "TI Zoom3";
15 compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3";
16
17 cpus {
18 cpu@0 {
19 cpu0-supply = <&vcc>;
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x80000000 0x20000000>; /* 512 MB */
26 };
27
28 vddvario: regulator-vddvario {
29 compatible = "regulator-fixed";
30 regulator-name = "vddvario";
31 regulator-always-on;
32 };
33
34 vdd33a: regulator-vdd33a {
35 compatible = "regulator-fixed";
36 regulator-name = "vdd33a";
37 regulator-always-on;
38 };
39
40 wl12xx_vmmc: wl12xx_vmmc {
41 pinctrl-names = "default";
42 pinctrl-0 = <&wl12xx_gpio>;
43 compatible = "regulator-fixed";
44 regulator-name = "vwl1271";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 gpio = <&gpio4 5 0>; /* gpio101 */
48 startup-delay-us = <70000>;
49 enable-active-high;
50 };
51};
52
53&omap3_pmx_core {
54 /* REVISIT: twl gpio0 is mmc0_cd */
55 mmc1_pins: pinmux_mmc1_pins {
56 pinctrl-single,pins = <
57 0x114 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
58 0x116 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
59 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
60 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
61 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
62 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
63 >;
64 };
65
66 mmc2_pins: pinmux_mmc2_pins {
67 pinctrl-single,pins = <
68 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
69 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
70 0x12c (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
71 0x12e (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
72 0x130 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
73 0x132 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
74 0x134 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */
75 0x136 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */
76 0x138 (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */
77 0x13a (PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */
78 >;
79 };
80
81 mmc3_pins: pinmux_mmc3_pins {
82 pinctrl-single,pins = <
83 0x168 (PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */
84 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
85 0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
86 0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
87 0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
88 0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
89 0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
90 >;
91 };
92
93 uart1_pins: pinmux_uart1_pins {
94 pinctrl-single,pins = <
95 0x150 (PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */
96 0x14e (PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */
97 0x152 (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
98 0x14c (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
99 >;
100 };
101
102 uart2_pins: pinmux_uart2_pins {
103 pinctrl-single,pins = <
104 0x144 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
105 0x146 (PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
106 0x14a (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
107 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
108 >;
109 };
110
111 uart3_pins: pinmux_uart3_pins {
112 pinctrl-single,pins = <
113 0x16a (PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
114 0x16c (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
115 0x16e (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
116 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
117 >;
118 };
119
120 /* wl12xx GPIO output for WLAN_EN */
121 wl12xx_gpio: pinmux_wl12xx_gpio {
122 pinctrl-single,pins = <
123 0xea (PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */
124 >;
125 };
126};
127
128&omap3_pmx_wkup {
129 wlan_host_wkup: pinmux_wlan_host_wkup_pins {
130 pinctrl-single,pins = <
131 0x1a (PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */
132 >;
133 };
134};
135
136&i2c1 {
137 clock-frequency = <2600000>;
138
139 twl: twl@48 {
140 reg = <0x48>;
141 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
142 interrupt-parent = <&intc>;
143 };
144};
145
146#include "twl4030.dtsi"
147
148&i2c2 {
149 clock-frequency = <400000>;
150};
151
152&i2c3 {
153 clock-frequency = <400000>;
154
155 /*
156 * TVP5146 Video decoder-in for analog input support.
157 */
158 tvp5146@5c {
159 compatible = "ti,tvp5146m2";
160 reg = <0x5c>;
161 };
162};
163
164&twl_gpio {
165 ti,use-leds;
166};
167
168&mmc1 {
169 vmmc-supply = <&vmmc1>;
170 vmmc_aux-supply = <&vsim>;
171 bus-width = <4>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&mmc1_pins>;
174};
175/*
176&mmc2 {
177 vmmc-supply = <&vmmc2>;
178 ti,non-removable;
179 bus-width = <8>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&mmc2_pins>;
182};
183*/
184&mmc3 {
185 vmmc-supply = <&wl12xx_vmmc>;
186 non-removable;
187 bus-width = <4>;
188 cap-power-off-card;
189 pinctrl-names = "default";
190 pinctrl-0 = <&mmc3_pins>;
191};
192
193&uart1 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&uart1_pins>;
196};
197
198&uart2 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&uart2_pins>;
201};
202
203&uart3 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&uart3_pins>;
206};
207
208&uart4 {
209 status = "disabled";
210};
211
212&usb_otg_hs {
213 interface-type = <0>;
214 usb-phy = <&usb2_phy>;
215 mode = <3>;
216 power = <50>;
217};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index b41bd57f4328..f3a0c26ed0c2 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -19,6 +19,9 @@
19 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
20 20
21 aliases { 21 aliases {
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
22 serial0 = &uart1; 25 serial0 = &uart1;
23 serial1 = &uart2; 26 serial1 = &uart2;
24 serial2 = &uart3; 27 serial2 = &uart3;
@@ -37,6 +40,7 @@
37 40
38 pmu { 41 pmu {
39 compatible = "arm,cortex-a8-pmu"; 42 compatible = "arm,cortex-a8-pmu";
43 reg = <0x54000000 0x800000>;
40 interrupts = <3>; 44 interrupts = <3>;
41 ti,hwmods = "debugss"; 45 ti,hwmods = "debugss";
42 }; 46 };
@@ -71,6 +75,8 @@
71 */ 75 */
72 ocp { 76 ocp {
73 compatible = "simple-bus"; 77 compatible = "simple-bus";
78 reg = <0x68000000 0x10000>;
79 interrupts = <9 10>;
74 #address-cells = <1>; 80 #address-cells = <1>;
75 #size-cells = <1>; 81 #size-cells = <1>;
76 ranges; 82 ranges;
@@ -107,15 +113,19 @@
107 reg = <0x48002030 0x05cc>; 113 reg = <0x48002030 0x05cc>;
108 #address-cells = <1>; 114 #address-cells = <1>;
109 #size-cells = <0>; 115 #size-cells = <0>;
116 #interrupt-cells = <1>;
117 interrupt-controller;
110 pinctrl-single,register-width = <16>; 118 pinctrl-single,register-width = <16>;
111 pinctrl-single,function-mask = <0xff1f>; 119 pinctrl-single,function-mask = <0xff1f>;
112 }; 120 };
113 121
114 omap3_pmx_wkup: pinmux@0x48002a00 { 122 omap3_pmx_wkup: pinmux@48002a00 {
115 compatible = "ti,omap3-padconf", "pinctrl-single"; 123 compatible = "ti,omap3-padconf", "pinctrl-single";
116 reg = <0x48002a00 0x5c>; 124 reg = <0x48002a00 0x5c>;
117 #address-cells = <1>; 125 #address-cells = <1>;
118 #size-cells = <0>; 126 #size-cells = <0>;
127 #interrupt-cells = <1>;
128 interrupt-controller;
119 pinctrl-single,register-width = <16>; 129 pinctrl-single,register-width = <16>;
120 pinctrl-single,function-mask = <0xff1f>; 130 pinctrl-single,function-mask = <0xff1f>;
121 }; 131 };
@@ -189,24 +199,40 @@
189 199
190 uart1: serial@4806a000 { 200 uart1: serial@4806a000 {
191 compatible = "ti,omap3-uart"; 201 compatible = "ti,omap3-uart";
202 reg = <0x4806a000 0x2000>;
203 interrupts = <72>;
204 dmas = <&sdma 49 &sdma 50>;
205 dma-names = "tx", "rx";
192 ti,hwmods = "uart1"; 206 ti,hwmods = "uart1";
193 clock-frequency = <48000000>; 207 clock-frequency = <48000000>;
194 }; 208 };
195 209
196 uart2: serial@4806c000 { 210 uart2: serial@4806c000 {
197 compatible = "ti,omap3-uart"; 211 compatible = "ti,omap3-uart";
212 reg = <0x4806c000 0x400>;
213 interrupts = <73>;
214 dmas = <&sdma 51 &sdma 52>;
215 dma-names = "tx", "rx";
198 ti,hwmods = "uart2"; 216 ti,hwmods = "uart2";
199 clock-frequency = <48000000>; 217 clock-frequency = <48000000>;
200 }; 218 };
201 219
202 uart3: serial@49020000 { 220 uart3: serial@49020000 {
203 compatible = "ti,omap3-uart"; 221 compatible = "ti,omap3-uart";
222 reg = <0x49020000 0x400>;
223 interrupts = <74>;
224 dmas = <&sdma 53 &sdma 54>;
225 dma-names = "tx", "rx";
204 ti,hwmods = "uart3"; 226 ti,hwmods = "uart3";
205 clock-frequency = <48000000>; 227 clock-frequency = <48000000>;
206 }; 228 };
207 229
208 i2c1: i2c@48070000 { 230 i2c1: i2c@48070000 {
209 compatible = "ti,omap3-i2c"; 231 compatible = "ti,omap3-i2c";
232 reg = <0x48070000 0x80>;
233 interrupts = <56>;
234 dmas = <&sdma 27 &sdma 28>;
235 dma-names = "tx", "rx";
210 #address-cells = <1>; 236 #address-cells = <1>;
211 #size-cells = <0>; 237 #size-cells = <0>;
212 ti,hwmods = "i2c1"; 238 ti,hwmods = "i2c1";
@@ -214,6 +240,10 @@
214 240
215 i2c2: i2c@48072000 { 241 i2c2: i2c@48072000 {
216 compatible = "ti,omap3-i2c"; 242 compatible = "ti,omap3-i2c";
243 reg = <0x48072000 0x80>;
244 interrupts = <57>;
245 dmas = <&sdma 29 &sdma 30>;
246 dma-names = "tx", "rx";
217 #address-cells = <1>; 247 #address-cells = <1>;
218 #size-cells = <0>; 248 #size-cells = <0>;
219 ti,hwmods = "i2c2"; 249 ti,hwmods = "i2c2";
@@ -221,6 +251,10 @@
221 251
222 i2c3: i2c@48060000 { 252 i2c3: i2c@48060000 {
223 compatible = "ti,omap3-i2c"; 253 compatible = "ti,omap3-i2c";
254 reg = <0x48060000 0x80>;
255 interrupts = <61>;
256 dmas = <&sdma 25 &sdma 26>;
257 dma-names = "tx", "rx";
224 #address-cells = <1>; 258 #address-cells = <1>;
225 #size-cells = <0>; 259 #size-cells = <0>;
226 ti,hwmods = "i2c3"; 260 ti,hwmods = "i2c3";
@@ -228,6 +262,8 @@
228 262
229 mcspi1: spi@48098000 { 263 mcspi1: spi@48098000 {
230 compatible = "ti,omap2-mcspi"; 264 compatible = "ti,omap2-mcspi";
265 reg = <0x48098000 0x100>;
266 interrupts = <65>;
231 #address-cells = <1>; 267 #address-cells = <1>;
232 #size-cells = <0>; 268 #size-cells = <0>;
233 ti,hwmods = "mcspi1"; 269 ti,hwmods = "mcspi1";
@@ -246,6 +282,8 @@
246 282
247 mcspi2: spi@4809a000 { 283 mcspi2: spi@4809a000 {
248 compatible = "ti,omap2-mcspi"; 284 compatible = "ti,omap2-mcspi";
285 reg = <0x4809a000 0x100>;
286 interrupts = <66>;
249 #address-cells = <1>; 287 #address-cells = <1>;
250 #size-cells = <0>; 288 #size-cells = <0>;
251 ti,hwmods = "mcspi2"; 289 ti,hwmods = "mcspi2";
@@ -259,6 +297,8 @@
259 297
260 mcspi3: spi@480b8000 { 298 mcspi3: spi@480b8000 {
261 compatible = "ti,omap2-mcspi"; 299 compatible = "ti,omap2-mcspi";
300 reg = <0x480b8000 0x100>;
301 interrupts = <91>;
262 #address-cells = <1>; 302 #address-cells = <1>;
263 #size-cells = <0>; 303 #size-cells = <0>;
264 ti,hwmods = "mcspi3"; 304 ti,hwmods = "mcspi3";
@@ -272,6 +312,8 @@
272 312
273 mcspi4: spi@480ba000 { 313 mcspi4: spi@480ba000 {
274 compatible = "ti,omap2-mcspi"; 314 compatible = "ti,omap2-mcspi";
315 reg = <0x480ba000 0x100>;
316 interrupts = <48>;
275 #address-cells = <1>; 317 #address-cells = <1>;
276 #size-cells = <0>; 318 #size-cells = <0>;
277 ti,hwmods = "mcspi4"; 319 ti,hwmods = "mcspi4";
@@ -280,8 +322,17 @@
280 dma-names = "tx0", "rx0"; 322 dma-names = "tx0", "rx0";
281 }; 323 };
282 324
325 hdqw1w: 1w@480b2000 {
326 compatible = "ti,omap3-1w";
327 reg = <0x480b2000 0x1000>;
328 interrupts = <58>;
329 ti,hwmods = "hdq1w";
330 };
331
283 mmc1: mmc@4809c000 { 332 mmc1: mmc@4809c000 {
284 compatible = "ti,omap3-hsmmc"; 333 compatible = "ti,omap3-hsmmc";
334 reg = <0x4809c000 0x200>;
335 interrupts = <83>;
285 ti,hwmods = "mmc1"; 336 ti,hwmods = "mmc1";
286 ti,dual-volt; 337 ti,dual-volt;
287 dmas = <&sdma 61>, <&sdma 62>; 338 dmas = <&sdma 61>, <&sdma 62>;
@@ -290,6 +341,8 @@
290 341
291 mmc2: mmc@480b4000 { 342 mmc2: mmc@480b4000 {
292 compatible = "ti,omap3-hsmmc"; 343 compatible = "ti,omap3-hsmmc";
344 reg = <0x480b4000 0x200>;
345 interrupts = <86>;
293 ti,hwmods = "mmc2"; 346 ti,hwmods = "mmc2";
294 dmas = <&sdma 47>, <&sdma 48>; 347 dmas = <&sdma 47>, <&sdma 48>;
295 dma-names = "tx", "rx"; 348 dma-names = "tx", "rx";
@@ -297,6 +350,8 @@
297 350
298 mmc3: mmc@480ad000 { 351 mmc3: mmc@480ad000 {
299 compatible = "ti,omap3-hsmmc"; 352 compatible = "ti,omap3-hsmmc";
353 reg = <0x480ad000 0x200>;
354 interrupts = <94>;
300 ti,hwmods = "mmc3"; 355 ti,hwmods = "mmc3";
301 dmas = <&sdma 77>, <&sdma 78>; 356 dmas = <&sdma 77>, <&sdma 78>;
302 dma-names = "tx", "rx"; 357 dma-names = "tx", "rx";
@@ -304,6 +359,7 @@
304 359
305 wdt2: wdt@48314000 { 360 wdt2: wdt@48314000 {
306 compatible = "ti,omap3-wdt"; 361 compatible = "ti,omap3-wdt";
362 reg = <0x48314000 0x80>;
307 ti,hwmods = "wd_timer2"; 363 ti,hwmods = "wd_timer2";
308 }; 364 };
309 365
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index e2249bcc3e63..281914ed0151 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -84,15 +84,15 @@
84 label = "bootloader-nor"; 84 label = "bootloader-nor";
85 reg = <0 0x40000>; 85 reg = <0 0x40000>;
86 }; 86 };
87 partition@0x40000 { 87 partition@40000 {
88 label = "params-nor"; 88 label = "params-nor";
89 reg = <0x40000 0x40000>; 89 reg = <0x40000 0x40000>;
90 }; 90 };
91 partition@0x80000 { 91 partition@80000 {
92 label = "kernel-nor"; 92 label = "kernel-nor";
93 reg = <0x80000 0x200000>; 93 reg = <0x80000 0x200000>;
94 }; 94 };
95 partition@0x280000 { 95 partition@280000 {
96 label = "filesystem-nor"; 96 label = "filesystem-nor";
97 reg = <0x240000 0x7d80000>; 97 reg = <0x240000 0x7d80000>;
98 }; 98 };
@@ -125,19 +125,19 @@
125 label = "xloader-nand"; 125 label = "xloader-nand";
126 reg = <0 0x80000>; 126 reg = <0 0x80000>;
127 }; 127 };
128 partition@0x80000 { 128 partition@80000 {
129 label = "bootloader-nand"; 129 label = "bootloader-nand";
130 reg = <0x80000 0x140000>; 130 reg = <0x80000 0x140000>;
131 }; 131 };
132 partition@0x1c0000 { 132 partition@1c0000 {
133 label = "params-nand"; 133 label = "params-nand";
134 reg = <0x1c0000 0xc0000>; 134 reg = <0x1c0000 0xc0000>;
135 }; 135 };
136 partition@0x280000 { 136 partition@280000 {
137 label = "kernel-nand"; 137 label = "kernel-nand";
138 reg = <0x280000 0x500000>; 138 reg = <0x280000 0x500000>;
139 }; 139 };
140 partition@0x780000 { 140 partition@780000 {
141 label = "filesystem-nand"; 141 label = "filesystem-nand";
142 reg = <0x780000 0x7880000>; 142 reg = <0x780000 0x7880000>;
143 }; 143 };
@@ -170,19 +170,19 @@
170 label = "xloader-onenand"; 170 label = "xloader-onenand";
171 reg = <0 0x80000>; 171 reg = <0 0x80000>;
172 }; 172 };
173 partition@0x80000 { 173 partition@80000 {
174 label = "bootloader-onenand"; 174 label = "bootloader-onenand";
175 reg = <0x80000 0x40000>; 175 reg = <0x80000 0x40000>;
176 }; 176 };
177 partition@0xc0000 { 177 partition@c0000 {
178 label = "params-onenand"; 178 label = "params-onenand";
179 reg = <0xc0000 0x20000>; 179 reg = <0xc0000 0x20000>;
180 }; 180 };
181 partition@0xe0000 { 181 partition@e0000 {
182 label = "kernel-onenand"; 182 label = "kernel-onenand";
183 reg = <0xe0000 0x200000>; 183 reg = <0xe0000 0x200000>;
184 }; 184 };
185 partition@0x2e0000 { 185 partition@2e0000 {
186 label = "filesystem-onenand"; 186 label = "filesystem-onenand";
187 reg = <0x2e0000 0xfd20000>; 187 reg = <0x2e0000 0xfd20000>;
188 }; 188 };
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f8b3765eb9be..380c22eb468e 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -31,6 +31,10 @@
31 ocp { 31 ocp {
32 uart4: serial@49042000 { 32 uart4: serial@49042000 {
33 compatible = "ti,omap3-uart"; 33 compatible = "ti,omap3-uart";
34 reg = <0x49042000 0x400>;
35 interrupts = <80>;
36 dmas = <&sdma 81 &sdma 82>;
37 dma-names = "tx", "rx";
34 ti,hwmods = "uart4"; 38 ti,hwmods = "uart4";
35 clock-frequency = <48000000>; 39 clock-frequency = <48000000>;
36 }; 40 };
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 814ab67c8c29..298e85020e1b 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -60,22 +60,6 @@
60 "AFMR", "Line In"; 60 "AFMR", "Line In";
61 }; 61 };
62 62
63 /*
64 * Temp hack: Need to be replaced with the proper gpio-controlled
65 * reset driver as soon it will be merged.
66 * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830
67 */
68 /* HS USB Port 1 RESET */
69 hsusb1_reset: hsusb1_reset_reg {
70 compatible = "regulator-fixed";
71 regulator-name = "hsusb1_reset";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 gpio = <&gpio2 30 0>; /* gpio_62 */
75 startup-delay-us = <70000>;
76 enable-active-high;
77 };
78
79 /* HS USB Port 1 Power */ 63 /* HS USB Port 1 Power */
80 hsusb1_power: hsusb1_power_reg { 64 hsusb1_power: hsusb1_power_reg {
81 compatible = "regulator-fixed"; 65 compatible = "regulator-fixed";
@@ -97,7 +81,7 @@
97 /* HS USB Host PHY on PORT 1 */ 81 /* HS USB Host PHY on PORT 1 */
98 hsusb1_phy: hsusb1_phy { 82 hsusb1_phy: hsusb1_phy {
99 compatible = "usb-nop-xceiv"; 83 compatible = "usb-nop-xceiv";
100 reset-supply = <&hsusb1_reset>; 84 reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
101 vcc-supply = <&hsusb1_power>; 85 vcc-supply = <&hsusb1_power>;
102 /** 86 /**
103 * FIXME: 87 * FIXME:
@@ -122,37 +106,19 @@
122 }; 106 };
123}; 107};
124 108
125&omap4_pmx_wkup {
126 pinctrl-names = "default";
127 pinctrl-0 = <
128 &twl6030_wkup_pins
129 >;
130
131 twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
132 pinctrl-single,pins = <
133 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
134 >;
135 };
136};
137
138&omap4_pmx_core { 109&omap4_pmx_core {
139 pinctrl-names = "default"; 110 pinctrl-names = "default";
140 pinctrl-0 = < 111 pinctrl-0 = <
141 &twl6030_pins
142 &twl6040_pins 112 &twl6040_pins
143 &mcpdm_pins 113 &mcpdm_pins
144 &mcbsp1_pins 114 &mcbsp1_pins
115 &dss_dpi_pins
116 &tfp410_pins
145 &dss_hdmi_pins 117 &dss_hdmi_pins
146 &tpd12s015_pins 118 &tpd12s015_pins
147 &hsusbb1_pins 119 &hsusbb1_pins
148 >; 120 >;
149 121
150 twl6030_pins: pinmux_twl6030_pins {
151 pinctrl-single,pins = <
152 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
153 >;
154 };
155
156 twl6040_pins: pinmux_twl6040_pins { 122 twl6040_pins: pinmux_twl6040_pins {
157 pinctrl-single,pins = < 123 pinctrl-single,pins = <
158 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ 124 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
@@ -179,6 +145,47 @@
179 >; 145 >;
180 }; 146 };
181 147
148 dss_dpi_pins: pinmux_dss_dpi_pins {
149 pinctrl-single,pins = <
150 0x122 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */
151 0x124 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */
152 0x126 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */
153 0x128 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */
154 0x12a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */
155 0x12c (PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */
156 0x12e (PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */
157 0x130 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */
158 0x132 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */
159 0x134 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */
160 0x136 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */
161
162 0x174 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */
163 0x176 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */
164 0x178 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */
165 0x17a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */
166 0x17c (PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */
167 0x17e (PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */
168 0x180 (PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */
169 0x182 (PIN_OUTPUT | MUX_MODE5) /* dispc2_de */
170 0x184 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */
171 0x186 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */
172 0x188 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */
173 0x18a (PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */
174 0x18c (PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */
175 0x18e (PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */
176
177 0x190 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */
178 0x192 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */
179 0x194 (PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */
180 >;
181 };
182
183 tfp410_pins: pinmux_tfp410_pins {
184 pinctrl-single,pins = <
185 0x144 (PIN_OUTPUT | MUX_MODE3) /* gpio_0 */
186 >;
187 };
188
182 dss_hdmi_pins: pinmux_dss_hdmi_pins { 189 dss_hdmi_pins: pinmux_dss_hdmi_pins {
183 pinctrl-single,pins = < 190 pinctrl-single,pins = <
184 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ 191 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */
@@ -305,6 +312,7 @@
305}; 312};
306 313
307#include "twl6030.dtsi" 314#include "twl6030.dtsi"
315#include "twl6030_omap4.dtsi"
308 316
309&i2c2 { 317&i2c2 {
310 pinctrl-names = "default"; 318 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 56c435468e94..816d1c95b592 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -62,3 +62,7 @@
62 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 62 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
63 }; 63 };
64}; 64};
65
66&gpio1 {
67 ti,no-reset-on-init;
68};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 4f78380ecdb8..5fc3f43c5a81 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -155,23 +155,9 @@
155 }; 155 };
156}; 156};
157 157
158&omap4_pmx_wkup {
159 pinctrl-names = "default";
160 pinctrl-0 = <
161 &twl6030_wkup_pins
162 >;
163
164 twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
165 pinctrl-single,pins = <
166 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
167 >;
168 };
169};
170
171&omap4_pmx_core { 158&omap4_pmx_core {
172 pinctrl-names = "default"; 159 pinctrl-names = "default";
173 pinctrl-0 = < 160 pinctrl-0 = <
174 &twl6030_pins
175 &twl6040_pins 161 &twl6040_pins
176 &mcpdm_pins 162 &mcpdm_pins
177 &dmic_pins 163 &dmic_pins
@@ -206,12 +192,6 @@
206 >; 192 >;
207 }; 193 };
208 194
209 twl6030_pins: pinmux_twl6030_pins {
210 pinctrl-single,pins = <
211 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
212 >;
213 };
214
215 twl6040_pins: pinmux_twl6040_pins { 195 twl6040_pins: pinmux_twl6040_pins {
216 pinctrl-single,pins = < 196 pinctrl-single,pins = <
217 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ 197 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
@@ -370,6 +350,7 @@
370}; 350};
371 351
372#include "twl6030.dtsi" 352#include "twl6030.dtsi"
353#include "twl6030_omap4.dtsi"
373 354
374&i2c2 { 355&i2c2 {
375 pinctrl-names = "default"; 356 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index ea4054bfdfd4..a1e05853afcd 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -17,6 +17,10 @@
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 aliases { 19 aliases {
20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
23 i2c3 = &i2c4;
20 serial0 = &uart1; 24 serial0 = &uart1;
21 serial1 = &uart2; 25 serial1 = &uart2;
22 serial2 = &uart3; 26 serial2 = &uart3;
@@ -56,7 +60,7 @@
56 cache-level = <2>; 60 cache-level = <2>;
57 }; 61 };
58 62
59 local-timer@0x48240600 { 63 local-timer@48240600 {
60 compatible = "arm,cortex-a9-twd-timer"; 64 compatible = "arm,cortex-a9-twd-timer";
61 reg = <0x48240600 0x20>; 65 reg = <0x48240600 0x20>;
62 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -114,6 +118,8 @@
114 reg = <0x4a100040 0x0196>; 118 reg = <0x4a100040 0x0196>;
115 #address-cells = <1>; 119 #address-cells = <1>;
116 #size-cells = <0>; 120 #size-cells = <0>;
121 #interrupt-cells = <1>;
122 interrupt-controller;
117 pinctrl-single,register-width = <16>; 123 pinctrl-single,register-width = <16>;
118 pinctrl-single,function-mask = <0x7fff>; 124 pinctrl-single,function-mask = <0x7fff>;
119 }; 125 };
@@ -122,6 +128,8 @@
122 reg = <0x4a31e040 0x0038>; 128 reg = <0x4a31e040 0x0038>;
123 #address-cells = <1>; 129 #address-cells = <1>;
124 #size-cells = <0>; 130 #size-cells = <0>;
131 #interrupt-cells = <1>;
132 interrupt-controller;
125 pinctrl-single,register-width = <16>; 133 pinctrl-single,register-width = <16>;
126 pinctrl-single,function-mask = <0x7fff>; 134 pinctrl-single,function-mask = <0x7fff>;
127 }; 135 };
@@ -214,6 +222,7 @@
214 gpmc,num-cs = <8>; 222 gpmc,num-cs = <8>;
215 gpmc,num-waitpins = <4>; 223 gpmc,num-waitpins = <4>;
216 ti,hwmods = "gpmc"; 224 ti,hwmods = "gpmc";
225 ti,no-idle-on-init;
217 }; 226 };
218 227
219 uart1: serial@4806a000 { 228 uart1: serial@4806a000 {
@@ -248,6 +257,12 @@
248 clock-frequency = <48000000>; 257 clock-frequency = <48000000>;
249 }; 258 };
250 259
260 hwspinlock: spinlock@4a0f6000 {
261 compatible = "ti,omap4-hwspinlock";
262 reg = <0x4a0f6000 0x1000>;
263 ti,hwmods = "spinlock";
264 };
265
251 i2c1: i2c@48070000 { 266 i2c1: i2c@48070000 {
252 compatible = "ti,omap4-i2c"; 267 compatible = "ti,omap4-i2c";
253 reg = <0x48070000 0x100>; 268 reg = <0x48070000 0x100>;
@@ -492,6 +507,7 @@
492 reg = <0x4c000000 0x100>; 507 reg = <0x4c000000 0x100>;
493 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 508 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
494 ti,hwmods = "emif1"; 509 ti,hwmods = "emif1";
510 ti,no-idle-on-init;
495 phy-type = <1>; 511 phy-type = <1>;
496 hw-caps-read-idle-ctrl; 512 hw-caps-read-idle-ctrl;
497 hw-caps-ll-interface; 513 hw-caps-ll-interface;
@@ -503,6 +519,7 @@
503 reg = <0x4d000000 0x100>; 519 reg = <0x4d000000 0x100>;
504 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 520 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
505 ti,hwmods = "emif2"; 521 ti,hwmods = "emif2";
522 ti,no-idle-on-init;
506 phy-type = <1>; 523 phy-type = <1>;
507 hw-caps-read-idle-ctrl; 524 hw-caps-read-idle-ctrl;
508 hw-caps-ll-interface; 525 hw-caps-ll-interface;
@@ -670,5 +687,23 @@
670 ram-bits = <12>; 687 ram-bits = <12>;
671 ctrl-module = <&omap_control_usbotg>; 688 ctrl-module = <&omap_control_usbotg>;
672 }; 689 };
690
691 aes: aes@4b501000 {
692 compatible = "ti,omap4-aes";
693 ti,hwmods = "aes";
694 reg = <0x4b501000 0xa0>;
695 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
696 dmas = <&sdma 111>, <&sdma 110>;
697 dma-names = "tx", "rx";
698 };
699
700 des: des@480a5000 {
701 compatible = "ti,omap4-des";
702 ti,hwmods = "des";
703 reg = <0x480a5000 0xa0>;
704 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
705 dmas = <&sdma 117>, <&sdma 116>;
706 dma-names = "tx", "rx";
707 };
673 }; 708 };
674}; 709};
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 65d7b601651c..002fa70180a5 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -27,21 +27,10 @@
27 regulator-max-microvolt = <3000000>; 27 regulator-max-microvolt = <3000000>;
28 }; 28 };
29 29
30 /* HS USB Port 2 RESET */
31 hsusb2_reset: hsusb2_reset_reg {
32 compatible = "regulator-fixed";
33 regulator-name = "hsusb2_reset";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */
37 startup-delay-us = <70000>;
38 enable-active-high;
39 };
40
41 /* HS USB Host PHY on PORT 2 */ 30 /* HS USB Host PHY on PORT 2 */
42 hsusb2_phy: hsusb2_phy { 31 hsusb2_phy: hsusb2_phy {
43 compatible = "usb-nop-xceiv"; 32 compatible = "usb-nop-xceiv";
44 reset-supply = <&hsusb2_reset>; 33 reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
45 /** 34 /**
46 * FIXME 35 * FIXME
47 * Put the right clock phandle here when available 36 * Put the right clock phandle here when available
@@ -51,21 +40,10 @@
51 clock-frequency = <19200000>; 40 clock-frequency = <19200000>;
52 }; 41 };
53 42
54 /* HS USB Port 3 RESET */
55 hsusb3_reset: hsusb3_reset_reg {
56 compatible = "regulator-fixed";
57 regulator-name = "hsusb3_reset";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */
61 startup-delay-us = <70000>;
62 enable-active-high;
63 };
64
65 /* HS USB Host PHY on PORT 3 */ 43 /* HS USB Host PHY on PORT 3 */
66 hsusb3_phy: hsusb3_phy { 44 hsusb3_phy: hsusb3_phy {
67 compatible = "usb-nop-xceiv"; 45 compatible = "usb-nop-xceiv";
68 reset-supply = <&hsusb3_reset>; 46 reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
69 }; 47 };
70 48
71 leds { 49 leds {
@@ -84,7 +62,6 @@
84 pinctrl-0 = < 62 pinctrl-0 = <
85 &twl6040_pins 63 &twl6040_pins
86 &mcpdm_pins 64 &mcpdm_pins
87 &dmic_pins
88 &mcbsp1_pins 65 &mcbsp1_pins
89 &mcbsp2_pins 66 &mcbsp2_pins
90 &usbhost_pins 67 &usbhost_pins
@@ -93,7 +70,7 @@
93 70
94 twl6040_pins: pinmux_twl6040_pins { 71 twl6040_pins: pinmux_twl6040_pins {
95 pinctrl-single,pins = < 72 pinctrl-single,pins = <
96 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ 73 0x17e (PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
97 >; 74 >;
98 }; 75 };
99 76
@@ -107,15 +84,6 @@
107 >; 84 >;
108 }; 85 };
109 86
110 dmic_pins: pinmux_dmic_pins {
111 pinctrl-single,pins = <
112 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */
113 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */
114 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */
115 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */
116 >;
117 };
118
119 mcbsp1_pins: pinmux_mcbsp1_pins { 87 mcbsp1_pins: pinmux_mcbsp1_pins {
120 pinctrl-single,pins = < 88 pinctrl-single,pins = <
121 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ 89 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
@@ -153,25 +121,25 @@
153 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ 121 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
154 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ 122 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
155 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ 123 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
156 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ 124 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */
157 >; 125 >;
158 }; 126 };
159 127
160 mcspi3_pins: pinmux_mcspi3_pins { 128 mcspi3_pins: pinmux_mcspi3_pins {
161 pinctrl-single,pins = < 129 pinctrl-single,pins = <
162 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ 130 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi3_somi */
163 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ 131 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */
164 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ 132 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi3_simo */
165 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ 133 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi3_clk */
166 >; 134 >;
167 }; 135 };
168 136
169 mcspi4_pins: pinmux_mcspi4_pins { 137 mcspi4_pins: pinmux_mcspi4_pins {
170 pinctrl-single,pins = < 138 pinctrl-single,pins = <
171 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ 139 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi4_clk */
172 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ 140 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi4_simo */
173 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ 141 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi4_somi */
174 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ 142 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi4_cs0 */
175 >; 143 >;
176 }; 144 };
177 145
@@ -271,6 +239,14 @@
271 reg = <0x48>; 239 reg = <0x48>;
272 interrupt-controller; 240 interrupt-controller;
273 #interrupt-cells = <2>; 241 #interrupt-cells = <2>;
242 ti,system-power-controller;
243
244 extcon_usb3: palmas_usb {
245 compatible = "ti,palmas-usb-vid";
246 ti,enable-vbus-detection;
247 ti,enable-id-detection;
248 ti,wakeup;
249 };
274 250
275 palmas_pmic { 251 palmas_pmic {
276 compatible = "ti,palmas-pmic"; 252 compatible = "ti,palmas-pmic";
@@ -334,15 +310,22 @@
334 ti,smps-range = <0x80>; 310 ti,smps-range = <0x80>;
335 }; 311 };
336 312
337 smps10_reg: smps10 { 313 smps10_out2_reg: smps10_out2 {
338 /* VBUS_5V_OTG */ 314 /* VBUS_5V_OTG */
339 regulator-name = "smps10"; 315 regulator-name = "smps10_out2";
340 regulator-min-microvolt = <5000000>; 316 regulator-min-microvolt = <5000000>;
341 regulator-max-microvolt = <5000000>; 317 regulator-max-microvolt = <5000000>;
342 regulator-always-on; 318 regulator-always-on;
343 regulator-boot-on; 319 regulator-boot-on;
344 }; 320 };
345 321
322 smps10_out1_reg: smps10_out1 {
323 /* VBUS_5V_OTG */
324 regulator-name = "smps10_out1";
325 regulator-min-microvolt = <5000000>;
326 regulator-max-microvolt = <5000000>;
327 };
328
346 ldo1_reg: ldo1 { 329 ldo1_reg: ldo1 {
347 /* VDDAPHY_CAM: vdda_csiport */ 330 /* VDDAPHY_CAM: vdda_csiport */
348 regulator-name = "ldo1"; 331 regulator-name = "ldo1";
@@ -470,6 +453,11 @@
470 phys = <0 &hsusb2_phy &hsusb3_phy>; 453 phys = <0 &hsusb2_phy &hsusb3_phy>;
471}; 454};
472 455
456&usb3 {
457 extcon = <&extcon_usb3>;
458 vbus-supply = <&smps10_out1_reg>;
459};
460
473&mcspi1 { 461&mcspi1 {
474 462
475}; 463};
@@ -503,3 +491,7 @@
503 pinctrl-names = "default"; 491 pinctrl-names = "default";
504 pinctrl-0 = <&uart5_pins>; 492 pinctrl-0 = <&uart5_pins>;
505}; 493};
494
495&cpu0 {
496 cpu0-supply = <&smps123_reg>;
497};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index c0ec6dce30fe..fc3fad563861 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -21,6 +21,11 @@
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&gic>;
22 22
23 aliases { 23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
24 serial0 = &uart1; 29 serial0 = &uart1;
25 serial1 = &uart2; 30 serial1 = &uart2;
26 serial2 = &uart3; 31 serial2 = &uart3;
@@ -33,10 +38,17 @@
33 #address-cells = <1>; 38 #address-cells = <1>;
34 #size-cells = <0>; 39 #size-cells = <0>;
35 40
36 cpu@0 { 41 cpu0: cpu@0 {
37 device_type = "cpu"; 42 device_type = "cpu";
38 compatible = "arm,cortex-a15"; 43 compatible = "arm,cortex-a15";
39 reg = <0x0>; 44 reg = <0x0>;
45
46 operating-points = <
47 /* kHz uV */
48 500000 880000
49 1000000 1060000
50 1500000 1250000
51 >;
40 }; 52 };
41 cpu@1 { 53 cpu@1 {
42 device_type = "cpu"; 54 device_type = "cpu";
@@ -52,7 +64,6 @@
52 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 64 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
53 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 65 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
54 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; 66 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
55 clock-frequency = <6144000>;
56 }; 67 };
57 68
58 gic: interrupt-controller@48211000 { 69 gic: interrupt-controller@48211000 {
@@ -276,6 +287,12 @@
276 ti,hwmods = "i2c5"; 287 ti,hwmods = "i2c5";
277 }; 288 };
278 289
290 hwspinlock: spinlock@4a0f6000 {
291 compatible = "ti,omap4-hwspinlock";
292 reg = <0x4a0f6000 0x1000>;
293 ti,hwmods = "spinlock";
294 };
295
279 mcspi1: spi@48098000 { 296 mcspi1: spi@48098000 {
280 compatible = "ti,omap4-mcspi"; 297 compatible = "ti,omap4-mcspi";
281 reg = <0x48098000 0x200>; 298 reg = <0x48098000 0x200>;
@@ -604,9 +621,10 @@
604 ti,hwmods = "wd_timer2"; 621 ti,hwmods = "wd_timer2";
605 }; 622 };
606 623
607 emif1: emif@0x4c000000 { 624 emif1: emif@4c000000 {
608 compatible = "ti,emif-4d5"; 625 compatible = "ti,emif-4d5";
609 ti,hwmods = "emif1"; 626 ti,hwmods = "emif1";
627 ti,no-idle-on-init;
610 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 628 phy-type = <2>; /* DDR PHY type: Intelli PHY */
611 reg = <0x4c000000 0x400>; 629 reg = <0x4c000000 0x400>;
612 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 630 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
@@ -615,9 +633,10 @@
615 hw-caps-temp-alert; 633 hw-caps-temp-alert;
616 }; 634 };
617 635
618 emif2: emif@0x4d000000 { 636 emif2: emif@4d000000 {
619 compatible = "ti,emif-4d5"; 637 compatible = "ti,emif-4d5";
620 ti,hwmods = "emif2"; 638 ti,hwmods = "emif2";
639 ti,no-idle-on-init;
621 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 640 phy-type = <2>; /* DDR PHY type: Intelli PHY */
622 reg = <0x4d000000 0x400>; 641 reg = <0x4d000000 0x400>;
623 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 642 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
@@ -638,7 +657,7 @@
638 reg-names = "power"; 657 reg-names = "power";
639 }; 658 };
640 659
641 omap_dwc3@4a020000 { 660 usb3: omap_dwc3@4a020000 {
642 compatible = "ti,dwc3"; 661 compatible = "ti,dwc3";
643 ti,hwmods = "usb_otg_ss"; 662 ti,hwmods = "usb_otg_ss";
644 reg = <0x4a020000 0x10000>; 663 reg = <0x4a020000 0x10000>;
@@ -652,6 +671,7 @@
652 reg = <0x4a030000 0x10000>; 671 reg = <0x4a030000 0x10000>;
653 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 672 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
654 usb-phy = <&usb2_phy>, <&usb3_phy>; 673 usb-phy = <&usb2_phy>, <&usb3_phy>;
674 dr_mode = "peripheral";
655 tx-fifo-resize; 675 tx-fifo-resize;
656 }; 676 };
657 }; 677 };
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 27ed9f5144bc..7cf78afee7b1 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -76,6 +76,11 @@
76 compatible = "sirf,prima2-rsc"; 76 compatible = "sirf,prima2-rsc";
77 reg = <0x88020000 0x1000>; 77 reg = <0x88020000 0x1000>;
78 }; 78 };
79
80 cphifbg@88030000 {
81 compatible = "sirf,prima2-cphifbg";
82 reg = <0x88030000 0x1000>;
83 };
79 }; 84 };
80 85
81 mem-iobg { 86 mem-iobg {
@@ -86,10 +91,17 @@
86 91
87 memory-controller@90000000 { 92 memory-controller@90000000 {
88 compatible = "sirf,prima2-memc"; 93 compatible = "sirf,prima2-memc";
89 reg = <0x90000000 0x10000>; 94 reg = <0x90000000 0x2000>;
90 interrupts = <27>; 95 interrupts = <27>;
91 clocks = <&clks 5>; 96 clocks = <&clks 5>;
92 }; 97 };
98
99 memc-monitor {
100 compatible = "sirf,prima2-memcmon";
101 reg = <0x90002000 0x200>;
102 interrupts = <4>;
103 clocks = <&clks 32>;
104 };
93 }; 105 };
94 106
95 disp-iobg { 107 disp-iobg {
@@ -287,7 +299,13 @@
287 compatible = "sirf,prima2-spi"; 299 compatible = "sirf,prima2-spi";
288 reg = <0xb00d0000 0x10000>; 300 reg = <0xb00d0000 0x10000>;
289 interrupts = <15>; 301 interrupts = <15>;
302 sirf,spi-num-chipselects = <1>;
303 sirf,spi-dma-rx-channel = <25>;
304 sirf,spi-dma-tx-channel = <20>;
305 #address-cells = <1>;
306 #size-cells = <0>;
290 clocks = <&clks 19>; 307 clocks = <&clks 19>;
308 status = "disabled";
291 }; 309 };
292 310
293 spi1: spi@b0170000 { 311 spi1: spi@b0170000 {
@@ -295,7 +313,13 @@
295 compatible = "sirf,prima2-spi"; 313 compatible = "sirf,prima2-spi";
296 reg = <0xb0170000 0x10000>; 314 reg = <0xb0170000 0x10000>;
297 interrupts = <16>; 315 interrupts = <16>;
316 sirf,spi-num-chipselects = <1>;
317 sirf,spi-dma-rx-channel = <12>;
318 sirf,spi-dma-tx-channel = <13>;
319 #address-cells = <1>;
320 #size-cells = <0>;
298 clocks = <&clks 20>; 321 clocks = <&clks 20>;
322 status = "disabled";
299 }; 323 };
300 324
301 i2c0: i2c@b00e0000 { 325 i2c0: i2c@b00e0000 {
@@ -304,6 +328,8 @@
304 reg = <0xb00e0000 0x10000>; 328 reg = <0xb00e0000 0x10000>;
305 interrupts = <24>; 329 interrupts = <24>;
306 clocks = <&clks 17>; 330 clocks = <&clks 17>;
331 #address-cells = <1>;
332 #size-cells = <0>;
307 }; 333 };
308 334
309 i2c1: i2c@b00f0000 { 335 i2c1: i2c@b00f0000 {
@@ -312,6 +338,8 @@
312 reg = <0xb00f0000 0x10000>; 338 reg = <0xb00f0000 0x10000>;
313 interrupts = <25>; 339 interrupts = <25>;
314 clocks = <&clks 18>; 340 clocks = <&clks 18>;
341 #address-cells = <1>;
342 #size-cells = <0>;
315 }; 343 };
316 344
317 tsc@b0110000 { 345 tsc@b0110000 {
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index f444624eb097..9443e93d3cac 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -10,6 +10,7 @@
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r8a73a4.dtsi" 12/include/ "r8a73a4.dtsi"
13#include <dt-bindings/gpio/gpio.h>
13 14
14/ { 15/ {
15 model = "APE6EVM"; 16 model = "APE6EVM";
@@ -24,6 +25,34 @@
24 reg = <0 0x40000000 0 0x40000000>; 25 reg = <0 0x40000000 0 0x40000000>;
25 }; 26 };
26 27
28 vcc_mmc0: regulator@0 {
29 compatible = "regulator-fixed";
30 regulator-name = "MMC0 Vcc";
31 regulator-min-microvolt = <2800000>;
32 regulator-max-microvolt = <2800000>;
33 regulator-always-on;
34 };
35
36 vcc_sdhi0: regulator@1 {
37 compatible = "regulator-fixed";
38
39 regulator-name = "SDHI0 Vcc";
40 regulator-min-microvolt = <3300000>;
41 regulator-max-microvolt = <3300000>;
42
43 gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
44 enable-active-high;
45 };
46
47 /* Common 3.3V rail, used by several devices on APE6EVM */
48 ape6evm_fixed_3v3: regulator@2 {
49 compatible = "regulator-fixed";
50 regulator-name = "3V3";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-always-on;
54 };
55
27 lbsc { 56 lbsc {
28 compatible = "simple-bus"; 57 compatible = "simple-bus";
29 #address-cells = <1>; 58 #address-cells = <1>;
@@ -33,6 +62,7 @@
33}; 62};
34 63
35&i2c5 { 64&i2c5 {
65 status = "okay";
36 vdd_dvfs: max8973@1b { 66 vdd_dvfs: max8973@1b {
37 compatible = "maxim,max8973"; 67 compatible = "maxim,max8973";
38 reg = <0x1b>; 68 reg = <0x1b>;
@@ -62,4 +92,47 @@
62 renesas,groups = "scifa0_data"; 92 renesas,groups = "scifa0_data";
63 renesas,function = "scifa0"; 93 renesas,function = "scifa0";
64 }; 94 };
95
96 mmc0_pins: mmcif {
97 renesas,groups = "mmc0_data8", "mmc0_ctrl";
98 renesas,function = "mmc0";
99 };
100
101 sdhi0_pins: sdhi0 {
102 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
103 renesas,function = "sdhi0";
104 };
105
106 sdhi1_pins: sdhi1 {
107 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
108 renesas,function = "sdhi1";
109 };
110};
111
112&mmcif0 {
113 vmmc-supply = <&vcc_mmc0>;
114 bus-width = <8>;
115 non-removable;
116 pinctrl-names = "default";
117 pinctrl-0 = <&mmc0_pins>;
118 status = "okay";
119};
120
121&sdhi0 {
122 vmmc-supply = <&vcc_sdhi0>;
123 bus-width = <4>;
124 toshiba,mmc-wrprotect-disable;
125 pinctrl-names = "default";
126 pinctrl-0 = <&sdhi0_pins>;
127 status = "okay";
128};
129
130&sdhi1 {
131 vmmc-supply = <&ape6evm_fixed_3v3>;
132 bus-width = <4>;
133 broken-cd;
134 toshiba,mmc-wrprotect-disable;
135 pinctrl-names = "default";
136 pinctrl-0 = <&sdhi1_pins>;
137 status = "okay";
65}; 138};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index 72f867e65791..91436b58016f 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -52,6 +52,7 @@
52}; 52};
53 53
54&i2c5 { 54&i2c5 {
55 status = "okay";
55 vdd_dvfs: max8973@1b { 56 vdd_dvfs: max8973@1b {
56 compatible = "maxim,max8973"; 57 compatible = "maxim,max8973";
57 reg = <0x1b>; 58 reg = <0x1b>;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 658fcc537576..287e047592a0 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -78,6 +78,49 @@
78 <0 56 4>, <0 57 4>; 78 <0 56 4>, <0 57 4>;
79 }; 79 };
80 80
81 dmac: dma-multiplexer@0 {
82 compatible = "renesas,shdma-mux";
83 #dma-cells = <1>;
84 dma-channels = <20>;
85 dma-requests = <256>;
86 #address-cells = <2>;
87 #size-cells = <2>;
88 ranges;
89
90 dma0: dma-controller@e6700020 {
91 compatible = "renesas,shdma-r8a73a4";
92 reg = <0 0xe6700020 0 0x89e0>;
93 interrupt-parent = <&gic>;
94 interrupts = <0 220 4
95 0 200 4
96 0 201 4
97 0 202 4
98 0 203 4
99 0 204 4
100 0 205 4
101 0 206 4
102 0 207 4
103 0 208 4
104 0 209 4
105 0 210 4
106 0 211 4
107 0 212 4
108 0 213 4
109 0 214 4
110 0 215 4
111 0 216 4
112 0 217 4
113 0 218 4
114 0 219 4>;
115 interrupt-names = "error",
116 "ch0", "ch1", "ch2", "ch3",
117 "ch4", "ch5", "ch6", "ch7",
118 "ch8", "ch9", "ch10", "ch11",
119 "ch12", "ch13", "ch14", "ch15",
120 "ch16", "ch17", "ch18", "ch19";
121 };
122 };
123
81 thermal@e61f0000 { 124 thermal@e61f0000 {
82 compatible = "renesas,rcar-thermal"; 125 compatible = "renesas,rcar-thermal";
83 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 126 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
@@ -93,6 +136,7 @@
93 reg = <0 0xe6500000 0 0x428>; 136 reg = <0 0xe6500000 0 0x428>;
94 interrupt-parent = <&gic>; 137 interrupt-parent = <&gic>;
95 interrupts = <0 174 0x4>; 138 interrupts = <0 174 0x4>;
139 status = "disabled";
96 }; 140 };
97 141
98 i2c1: i2c@e6510000 { 142 i2c1: i2c@e6510000 {
@@ -102,6 +146,7 @@
102 reg = <0 0xe6510000 0 0x428>; 146 reg = <0 0xe6510000 0 0x428>;
103 interrupt-parent = <&gic>; 147 interrupt-parent = <&gic>;
104 interrupts = <0 175 0x4>; 148 interrupts = <0 175 0x4>;
149 status = "disabled";
105 }; 150 };
106 151
107 i2c2: i2c@e6520000 { 152 i2c2: i2c@e6520000 {
@@ -111,6 +156,7 @@
111 reg = <0 0xe6520000 0 0x428>; 156 reg = <0 0xe6520000 0 0x428>;
112 interrupt-parent = <&gic>; 157 interrupt-parent = <&gic>;
113 interrupts = <0 176 0x4>; 158 interrupts = <0 176 0x4>;
159 status = "disabled";
114 }; 160 };
115 161
116 i2c3: i2c@e6530000 { 162 i2c3: i2c@e6530000 {
@@ -120,6 +166,7 @@
120 reg = <0 0xe6530000 0 0x428>; 166 reg = <0 0xe6530000 0 0x428>;
121 interrupt-parent = <&gic>; 167 interrupt-parent = <&gic>;
122 interrupts = <0 177 0x4>; 168 interrupts = <0 177 0x4>;
169 status = "disabled";
123 }; 170 };
124 171
125 i2c4: i2c@e6540000 { 172 i2c4: i2c@e6540000 {
@@ -129,6 +176,7 @@
129 reg = <0 0xe6540000 0 0x428>; 176 reg = <0 0xe6540000 0 0x428>;
130 interrupt-parent = <&gic>; 177 interrupt-parent = <&gic>;
131 interrupts = <0 178 0x4>; 178 interrupts = <0 178 0x4>;
179 status = "disabled";
132 }; 180 };
133 181
134 i2c5: i2c@e60b0000 { 182 i2c5: i2c@e60b0000 {
@@ -138,6 +186,7 @@
138 reg = <0 0xe60b0000 0 0x428>; 186 reg = <0 0xe60b0000 0 0x428>;
139 interrupt-parent = <&gic>; 187 interrupt-parent = <&gic>;
140 interrupts = <0 179 0x4>; 188 interrupts = <0 179 0x4>;
189 status = "disabled";
141 }; 190 };
142 191
143 i2c6: i2c@e6550000 { 192 i2c6: i2c@e6550000 {
@@ -147,6 +196,7 @@
147 reg = <0 0xe6550000 0 0x428>; 196 reg = <0 0xe6550000 0 0x428>;
148 interrupt-parent = <&gic>; 197 interrupt-parent = <&gic>;
149 interrupts = <0 184 0x4>; 198 interrupts = <0 184 0x4>;
199 status = "disabled";
150 }; 200 };
151 201
152 i2c7: i2c@e6560000 { 202 i2c7: i2c@e6560000 {
@@ -156,6 +206,7 @@
156 reg = <0 0xe6560000 0 0x428>; 206 reg = <0 0xe6560000 0 0x428>;
157 interrupt-parent = <&gic>; 207 interrupt-parent = <&gic>;
158 interrupts = <0 185 0x4>; 208 interrupts = <0 185 0x4>;
209 status = "disabled";
159 }; 210 };
160 211
161 i2c8: i2c@e6570000 { 212 i2c8: i2c@e6570000 {
@@ -165,6 +216,7 @@
165 reg = <0 0xe6570000 0 0x428>; 216 reg = <0 0xe6570000 0 0x428>;
166 interrupt-parent = <&gic>; 217 interrupt-parent = <&gic>;
167 interrupts = <0 173 0x4>; 218 interrupts = <0 173 0x4>;
219 status = "disabled";
168 }; 220 };
169 221
170 mmcif0: mmcif@ee200000 { 222 mmcif0: mmcif@ee200000 {
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index c638e4ab91b8..1c56c5e56950 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -11,6 +11,7 @@
11/dts-v1/; 11/dts-v1/;
12/include/ "r8a7740.dtsi" 12/include/ "r8a7740.dtsi"
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/pwm/pwm.h>
14 15
15/ { 16/ {
16 model = "armadillo 800 eva reference"; 17 model = "armadillo 800 eva reference";
@@ -34,6 +35,33 @@
34 regulator-boot-on; 35 regulator-boot-on;
35 }; 36 };
36 37
38 vcc_sdhi0: regulator@1 {
39 compatible = "regulator-fixed";
40
41 regulator-name = "SDHI0 Vcc";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44
45 gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
46 enable-active-high;
47 };
48
49 vccq_sdhi0: regulator@2 {
50 compatible = "regulator-gpio";
51
52 regulator-name = "SDHI0 VccQ";
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <3300000>;
55 vin-supply = <&vcc_sdhi0>;
56
57 enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
58 gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
59 states = <3300000 0
60 1800000 1>;
61
62 enable-active-high;
63 };
64
37 leds { 65 leds {
38 compatible = "gpio-leds"; 66 compatible = "gpio-leds";
39 led1 { 67 led1 {
@@ -49,9 +77,19 @@
49 gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; 77 gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
50 }; 78 };
51 }; 79 };
80
81 backlight {
82 compatible = "pwm-backlight";
83 pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
84 brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
85 default-brightness-level = <9>;
86 pinctrl-0 = <&backlight_pins>;
87 pinctrl-names = "default";
88 };
52}; 89};
53 90
54&i2c0 { 91&i2c0 {
92 status = "okay";
55 touchscreen: st1232@55 { 93 touchscreen: st1232@55 {
56 compatible = "sitronix,st1232"; 94 compatible = "sitronix,st1232";
57 reg = <0x55>; 95 reg = <0x55>;
@@ -76,4 +114,44 @@
76 renesas,groups = "intc_irq10"; 114 renesas,groups = "intc_irq10";
77 renesas,function = "intc"; 115 renesas,function = "intc";
78 }; 116 };
117
118 backlight_pins: backlight {
119 renesas,groups = "tpu0_to2_1";
120 renesas,function = "tpu0";
121 };
122
123 mmc0_pins: mmc0 {
124 renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
125 renesas,function = "mmc0";
126 };
127
128 sdhi0_pins: sdhi0 {
129 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
130 renesas,function = "sdhi0";
131 };
132};
133
134&tpu {
135 status = "okay";
136};
137
138&mmcif0 {
139 pinctrl-0 = <&mmc0_pins>;
140 pinctrl-names = "default";
141
142 vmmc-supply = <&reg_3p3v>;
143 bus-width = <8>;
144 non-removable;
145 status = "okay";
146};
147
148&sdhi0 {
149 pinctrl-0 = <&sdhi0_pins>;
150 pinctrl-names = "default";
151
152 vmmc-supply = <&vcc_sdhi0>;
153 vqmmc-supply = <&vccq_sdhi0>;
154 bus-width = <4>;
155 cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
156 status = "okay";
79}; 157};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 44d3d520e01f..ae1e230f711d 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -131,6 +131,7 @@
131 0 202 0x4 131 0 202 0x4
132 0 203 0x4 132 0 203 0x4
133 0 204 0x4>; 133 0 204 0x4>;
134 status = "disabled";
134 }; 135 };
135 136
136 i2c1: i2c@e6c20000 { 137 i2c1: i2c@e6c20000 {
@@ -143,6 +144,7 @@
143 0 71 0x4 144 0 71 0x4
144 0 72 0x4 145 0 72 0x4
145 0 73 0x4>; 146 0 73 0x4>;
147 status = "disabled";
146 }; 148 };
147 149
148 pfc: pfc@e6050000 { 150 pfc: pfc@e6050000 {
@@ -159,4 +161,37 @@
159 status = "disabled"; 161 status = "disabled";
160 #pwm-cells = <3>; 162 #pwm-cells = <3>;
161 }; 163 };
164
165 mmcif0: mmcif@e6bd0000 {
166 compatible = "renesas,sh-mmcif";
167 reg = <0xe6bd0000 0x100>;
168 interrupt-parent = <&gic>;
169 interrupts = <0 56 4
170 0 57 4>;
171 status = "disabled";
172 };
173
174 sdhi0: sdhi@e6850000 {
175 compatible = "renesas,sdhi-r8a7740";
176 reg = <0xe6850000 0x100>;
177 interrupt-parent = <&gic>;
178 interrupts = <0 117 4
179 0 118 4
180 0 119 4>;
181 cap-sd-highspeed;
182 cap-sdio-irq;
183 status = "disabled";
184 };
185
186 sdhi1: sdhi@e6860000 {
187 compatible = "renesas,sdhi-r8a7740";
188 reg = <0xe6860000 0x100>;
189 interrupt-parent = <&gic>;
190 interrupts = <0 121 4
191 0 122 4
192 0 123 4>;
193 cap-sd-highspeed;
194 cap-sdio-irq;
195 status = "disabled";
196 };
162}; 197};
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index 9bb903a3230d..969e386e852c 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -22,11 +22,36 @@
22 compatible = "renesas,bockw-reference", "renesas,r8a7778"; 22 compatible = "renesas,bockw-reference", "renesas,r8a7778";
23 23
24 chosen { 24 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel rw"; 25 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
26 }; 26 };
27 27
28 memory { 28 memory {
29 device_type = "memory"; 29 device_type = "memory";
30 reg = <0x60000000 0x10000000>; 30 reg = <0x60000000 0x10000000>;
31 }; 31 };
32
33 fixedregulator3v3: fixedregulator@0 {
34 compatible = "regulator-fixed";
35 regulator-name = "fixed-3.3V";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 regulator-boot-on;
39 regulator-always-on;
40 };
41
42 ethernet@18300000 {
43 compatible = "smsc,lan9220", "smsc,lan9115";
44 reg = <0x18300000 0x1000>;
45
46 phy-mode = "mii";
47 interrupt-parent = <&irqpin>;
48 interrupts = <0 0>; /* IRQ0: hwirq 0 on irqpin */
49 reg-io-width = <4>;
50 vddvario-supply = <&fixedregulator3v3>;
51 vdd33a-supply = <&fixedregulator3v3>;
52 };
53};
54
55&irqpin {
56 status = "okay";
32}; 57};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 3577aba82583..a6308a399e2d 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -33,6 +33,25 @@
33 <0xfe430000 0x100>; 33 <0xfe430000 0x100>;
34 }; 34 };
35 35
36 /* irqpin: IRQ0 - IRQ3 */
37 irqpin: irqpin@fe78001c {
38 compatible = "renesas,intc-irqpin";
39 #interrupt-cells = <2>;
40 interrupt-controller;
41 status = "disabled"; /* default off */
42 reg = <0xfe78001c 4>,
43 <0xfe780010 4>,
44 <0xfe780024 4>,
45 <0xfe780044 4>,
46 <0xfe780064 4>;
47 interrupt-parent = <&gic>;
48 interrupts = <0 27 0x4
49 0 28 0x4
50 0 29 0x4
51 0 30 0x4>;
52 sense-bitfield-width = <2>;
53 };
54
36 gpio0: gpio@ffc40000 { 55 gpio0: gpio@ffc40000 {
37 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 56 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
38 reg = <0xffc40000 0x2c>; 57 reg = <0xffc40000 0x2c>;
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index 6d5508392252..ab4110aa3c3b 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -42,8 +42,8 @@
42 pinctrl-names = "default"; 42 pinctrl-names = "default";
43 43
44 phy-mode = "mii"; 44 phy-mode = "mii";
45 interrupt-parent = <&gic>; 45 interrupt-parent = <&irqpin0>;
46 interrupts = <0 28 0x4>; 46 interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */
47 reg-io-width = <4>; 47 reg-io-width = <4>;
48 vddvario-supply = <&fixedregulator3v3>; 48 vddvario-supply = <&fixedregulator3v3>;
49 vdd33a-supply = <&fixedregulator3v3>; 49 vdd33a-supply = <&fixedregulator3v3>;
@@ -63,6 +63,10 @@
63 }; 63 };
64}; 64};
65 65
66&irqpin0 {
67 status = "okay";
68};
69
66&pfc { 70&pfc {
67 pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; 71 pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>;
68 pinctrl-names = "default"; 72 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index ebbe507fcbfa..19faeac3fd2e 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -135,6 +135,7 @@
135 irqpin0: irqpin@fe780010 { 135 irqpin0: irqpin@fe780010 {
136 compatible = "renesas,intc-irqpin"; 136 compatible = "renesas,intc-irqpin";
137 #interrupt-cells = <2>; 137 #interrupt-cells = <2>;
138 status = "disabled";
138 interrupt-controller; 139 interrupt-controller;
139 reg = <0xfe78001c 4>, 140 reg = <0xfe78001c 4>,
140 <0xfe780010 4>, 141 <0xfe780010 4>,
@@ -156,6 +157,7 @@
156 reg = <0xffc70000 0x1000>; 157 reg = <0xffc70000 0x1000>;
157 interrupt-parent = <&gic>; 158 interrupt-parent = <&gic>;
158 interrupts = <0 79 0x4>; 159 interrupts = <0 79 0x4>;
160 status = "disabled";
159 }; 161 };
160 162
161 i2c1: i2c@ffc71000 { 163 i2c1: i2c@ffc71000 {
@@ -165,6 +167,7 @@
165 reg = <0xffc71000 0x1000>; 167 reg = <0xffc71000 0x1000>;
166 interrupt-parent = <&gic>; 168 interrupt-parent = <&gic>;
167 interrupts = <0 82 0x4>; 169 interrupts = <0 82 0x4>;
170 status = "disabled";
168 }; 171 };
169 172
170 i2c2: i2c@ffc72000 { 173 i2c2: i2c@ffc72000 {
@@ -174,6 +177,7 @@
174 reg = <0xffc72000 0x1000>; 177 reg = <0xffc72000 0x1000>;
175 interrupt-parent = <&gic>; 178 interrupt-parent = <&gic>;
176 interrupts = <0 80 0x4>; 179 interrupts = <0 80 0x4>;
180 status = "disabled";
177 }; 181 };
178 182
179 i2c3: i2c@ffc73000 { 183 i2c3: i2c@ffc73000 {
@@ -183,6 +187,7 @@
183 reg = <0xffc73000 0x1000>; 187 reg = <0xffc73000 0x1000>;
184 interrupt-parent = <&gic>; 188 interrupt-parent = <&gic>;
185 interrupts = <0 81 0x4>; 189 interrupts = <0 81 0x4>;
190 status = "disabled";
186 }; 191 };
187 192
188 pfc: pfc@fffc0000 { 193 pfc: pfc@fffc0000 {
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 413b4c29e782..ee845fad939b 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -24,6 +24,55 @@
24 reg = <0>; 24 reg = <0>;
25 clock-frequency = <1300000000>; 25 clock-frequency = <1300000000>;
26 }; 26 };
27
28 cpu1: cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a15";
31 reg = <1>;
32 clock-frequency = <1300000000>;
33 };
34
35 cpu2: cpu@2 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a15";
38 reg = <2>;
39 clock-frequency = <1300000000>;
40 };
41
42 cpu3: cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a15";
45 reg = <3>;
46 clock-frequency = <1300000000>;
47 };
48
49 cpu4: cpu@4 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a7";
52 reg = <0x100>;
53 clock-frequency = <780000000>;
54 };
55
56 cpu5: cpu@5 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a7";
59 reg = <0x101>;
60 clock-frequency = <780000000>;
61 };
62
63 cpu6: cpu@6 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a7";
66 reg = <0x102>;
67 clock-frequency = <780000000>;
68 };
69
70 cpu7: cpu@7 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a7";
73 reg = <0x103>;
74 clock-frequency = <780000000>;
75 };
27 }; 76 };
28 77
29 gic: interrupt-controller@f1001000 { 78 gic: interrupt-controller@f1001000 {
@@ -127,6 +176,46 @@
127 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; 176 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
128 }; 177 };
129 178
179 i2c0: i2c@e6508000 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 compatible = "renesas,i2c-r8a7790";
183 reg = <0 0xe6508000 0 0x40>;
184 interrupt-parent = <&gic>;
185 interrupts = <0 287 0x4>;
186 status = "disabled";
187 };
188
189 i2c1: i2c@e6518000 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 compatible = "renesas,i2c-r8a7790";
193 reg = <0 0xe6518000 0 0x40>;
194 interrupt-parent = <&gic>;
195 interrupts = <0 288 0x4>;
196 status = "disabled";
197 };
198
199 i2c2: i2c@e6530000 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "renesas,i2c-r8a7790";
203 reg = <0 0xe6530000 0 0x40>;
204 interrupt-parent = <&gic>;
205 interrupts = <0 286 0x4>;
206 status = "disabled";
207 };
208
209 i2c3: i2c@e6540000 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 compatible = "renesas,i2c-r8a7790";
213 reg = <0 0xe6540000 0 0x40>;
214 interrupt-parent = <&gic>;
215 interrupts = <0 290 0x4>;
216 status = "disabled";
217 };
218
130 mmcif0: mmcif@ee200000 { 219 mmcif0: mmcif@ee200000 {
131 compatible = "renesas,sh-mmcif"; 220 compatible = "renesas,sh-mmcif";
132 reg = <0 0xee200000 0 0x80>; 221 reg = <0 0xee200000 0 0x80>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index bbed43bd9be9..fea5cfef4691 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -25,6 +25,13 @@
25 reg = <0>; 25 reg = <0>;
26 clock-frequency = <1300000000>; 26 clock-frequency = <1300000000>;
27 }; 27 };
28
29 cpu1: cpu@1 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a15";
32 reg = <1>;
33 clock-frequency = <1300000000>;
34 };
28 }; 35 };
29 36
30 gic: interrupt-controller@f1001000 { 37 gic: interrupt-controller@f1001000 {
@@ -38,4 +45,30 @@
38 <0 0xf1006000 0 0x2000>; 45 <0 0xf1006000 0 0x2000>;
39 interrupts = <1 9 0xf04>; 46 interrupts = <1 9 0xf04>;
40 }; 47 };
48
49 timer {
50 compatible = "arm,armv7-timer";
51 interrupts = <1 13 0xf08>,
52 <1 14 0xf08>,
53 <1 11 0xf08>,
54 <1 10 0xf08>;
55 };
56
57 irqc0: interrupt-controller@e61c0000 {
58 compatible = "renesas,irqc";
59 #interrupt-cells = <2>;
60 interrupt-controller;
61 reg = <0 0xe61c0000 0 0x200>;
62 interrupt-parent = <&gic>;
63 interrupts = <0 0 4>,
64 <0 1 4>,
65 <0 2 4>,
66 <0 3 4>,
67 <0 12 4>,
68 <0 13 4>,
69 <0 14 4>,
70 <0 15 4>,
71 <0 16 4>,
72 <0 17 4>;
73 };
41}; 74};
diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi
new file mode 100644
index 000000000000..a7d1c8ec150d
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6400.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Samsung's S3C6400 SoC device tree source
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400
7 * based board files can include this file and provide values for board specfic
8 * bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional
12 * nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17*/
18
19#include "s3c64xx.dtsi"
20
21/ {
22 compatible = "samsung,s3c6400";
23};
24
25&vic0 {
26 valid-mask = <0xfffffe1f>;
27 valid-wakeup-mask = <0x00200004>;
28};
29
30&vic1 {
31 valid-mask = <0xffffffff>;
32 valid-wakeup-mask = <0x53020000>;
33};
34
35&soc {
36 clocks: clock-controller@7e00f000 {
37 compatible = "samsung,s3c6400-clock";
38 reg = <0x7e00f000 0x1000>;
39 #clock-cells = <1>;
40 };
41};
diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts
new file mode 100644
index 000000000000..57e00f9bce99
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -0,0 +1,228 @@
1/*
2 * Samsung's S3C6410 based Mini6410 board device tree source
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Device tree source file for FriendlyARM Mini6410 board which is based on
7 * Samsung's S3C6410 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/dts-v1/;
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19#include "s3c6410.dtsi"
20
21/ {
22 model = "FriendlyARM Mini6410 board based on S3C6410";
23 compatible = "friendlyarm,mini6410", "samsung,s3c6410";
24
25 memory {
26 reg = <0x50000000 0x10000000>;
27 };
28
29 chosen {
30 bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
31 };
32
33 clocks {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 fin_pll: oscillator@0 {
39 compatible = "fixed-clock";
40 reg = <0>;
41 clock-frequency = <12000000>;
42 clock-output-names = "fin_pll";
43 #clock-cells = <0>;
44 };
45
46 xusbxti: oscillator@1 {
47 compatible = "fixed-clock";
48 reg = <1>;
49 clock-output-names = "xusbxti";
50 clock-frequency = <48000000>;
51 #clock-cells = <0>;
52 };
53 };
54
55 srom-cs1@18000000 {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 reg = <0x18000000 0x8000000>;
60 ranges;
61
62 ethernet@18000000 {
63 compatible = "davicom,dm9000";
64 reg = <0x18000000 0x2 0x18000004 0x2>;
65 interrupt-parent = <&gpn>;
66 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
67 davicom,no-eeprom;
68 };
69 };
70
71 gpio-keys {
72 compatible = "gpio-keys";
73 pinctrl-names = "default";
74 pinctrl-0 = <&gpio_keys>;
75 autorepeat;
76
77 button-k1 {
78 label = "K1";
79 gpios = <&gpn 0 GPIO_ACTIVE_LOW>;
80 linux,code = <2>;
81 debounce-interval = <20>;
82 };
83
84 button-k2 {
85 label = "K2";
86 gpios = <&gpn 1 GPIO_ACTIVE_LOW>;
87 linux,code = <3>;
88 debounce-interval = <20>;
89 };
90
91 button-k3 {
92 label = "K3";
93 gpios = <&gpn 2 GPIO_ACTIVE_LOW>;
94 linux,code = <4>;
95 debounce-interval = <20>;
96 };
97
98 button-k4 {
99 label = "K4";
100 gpios = <&gpn 3 GPIO_ACTIVE_LOW>;
101 linux,code = <5>;
102 debounce-interval = <20>;
103 };
104
105 button-k5 {
106 label = "K5";
107 gpios = <&gpn 4 GPIO_ACTIVE_LOW>;
108 linux,code = <6>;
109 debounce-interval = <20>;
110 };
111
112 button-k6 {
113 label = "K6";
114 gpios = <&gpn 5 GPIO_ACTIVE_LOW>;
115 linux,code = <7>;
116 debounce-interval = <20>;
117 };
118
119 button-k7 {
120 label = "K7";
121 gpios = <&gpl 11 GPIO_ACTIVE_LOW>;
122 linux,code = <8>;
123 debounce-interval = <20>;
124 };
125
126 button-k8 {
127 label = "K8";
128 gpios = <&gpl 12 GPIO_ACTIVE_LOW>;
129 linux,code = <9>;
130 debounce-interval = <20>;
131 };
132 };
133
134 leds {
135 compatible = "gpio-leds";
136 pinctrl-names = "default";
137 pinctrl-0 = <&gpio_leds>;
138
139 led-1 {
140 label = "LED1";
141 gpios = <&gpk 4 GPIO_ACTIVE_LOW>;
142 linux,default-trigger = "heartbeat";
143 };
144
145 led-2 {
146 label = "LED2";
147 gpios = <&gpk 5 GPIO_ACTIVE_LOW>;
148 linux,default-trigger = "mmc0";
149 };
150
151 led-3 {
152 label = "LED3";
153 gpios = <&gpk 6 GPIO_ACTIVE_LOW>;
154 };
155
156 led-4 {
157 label = "LED4";
158 gpios = <&gpk 7 GPIO_ACTIVE_LOW>;
159 };
160 };
161
162 buzzer {
163 compatible = "pwm-beeper";
164 pwms = <&pwm 0 1000000 0>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pwm0_out>;
167 };
168};
169
170&sdhci0 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
173 bus-width = <4>;
174 status = "okay";
175};
176
177&uart0 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&uart0_data>;
180 status = "okay";
181};
182
183&uart1 {
184 pinctrl-names = "default";
185 pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
186 status = "okay";
187};
188
189&uart2 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&uart2_data>;
192 status = "okay";
193};
194
195&uart3 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&uart3_data>;
198 status = "okay";
199};
200
201&pwm {
202 status = "okay";
203};
204
205&pinctrl0 {
206 gpio_leds: gpio-leds {
207 samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7";
208 samsung,pin-pud = <PIN_PULL_NONE>;
209 };
210
211 gpio_keys: gpio-keys {
212 samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3",
213 "gpn-4", "gpn-5", "gpl-11", "gpl-12";
214 samsung,pin-pud = <PIN_PULL_NONE>;
215 };
216};
217
218&i2c0 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c0_bus>;
221 status = "okay";
222
223 eeprom@50 {
224 compatible = "atmel,24c08";
225 reg = <0x50>;
226 pagesize = <16>;
227 };
228};
diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts
new file mode 100644
index 000000000000..ecf35ec466f7
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts
@@ -0,0 +1,103 @@
1/*
2 * Samsung S3C6410 based SMDK6410 board device tree source.
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Device tree source file for SAMSUNG SMDK6410 board which is based on
7 * Samsung's S3C6410 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/dts-v1/;
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19#include "s3c6410.dtsi"
20
21/ {
22 model = "SAMSUNG SMDK6410 board based on S3C6410";
23 compatible = "samsung,mini6410", "samsung,s3c6410";
24
25 memory {
26 reg = <0x50000000 0x8000000>;
27 };
28
29 chosen {
30 bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
31 };
32
33 clocks {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 fin_pll: oscillator@0 {
39 compatible = "fixed-clock";
40 reg = <0>;
41 clock-frequency = <12000000>;
42 clock-output-names = "fin_pll";
43 #clock-cells = <0>;
44 };
45
46 xusbxti: oscillator@1 {
47 compatible = "fixed-clock";
48 reg = <1>;
49 clock-output-names = "xusbxti";
50 clock-frequency = <48000000>;
51 #clock-cells = <0>;
52 };
53 };
54
55 srom-cs1@18000000 {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 reg = <0x18000000 0x8000000>;
60 ranges;
61
62 ethernet@18000000 {
63 compatible = "smsc,lan9115";
64 reg = <0x18000000 0x10000>;
65 interrupt-parent = <&gpn>;
66 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
67 phy-mode = "mii";
68 reg-io-width = <4>;
69 smsc,force-internal-phy;
70 };
71 };
72};
73
74&sdhci0 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
77 bus-width = <4>;
78 status = "okay";
79};
80
81&uart0 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
84 status = "okay";
85};
86
87&uart1 {
88 pinctrl-names = "default";
89 pinctrl-0 = <&uart1_data>;
90 status = "okay";
91};
92
93&uart2 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&uart2_data>;
96 status = "okay";
97};
98
99&uart3 {
100 pinctrl-names = "default";
101 pinctrl-0 = <&uart3_data>;
102 status = "okay";
103};
diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi
new file mode 100644
index 000000000000..eb4226b3407c
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410.dtsi
@@ -0,0 +1,57 @@
1/*
2 * Samsung's S3C6410 SoC device tree source
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410
7 * based board files can include this file and provide values for board specfic
8 * bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional
12 * nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17*/
18
19#include "s3c64xx.dtsi"
20
21/ {
22 compatible = "samsung,s3c6410";
23
24 aliases {
25 i2c1 = &i2c1;
26 };
27};
28
29&vic0 {
30 valid-mask = <0xffffff7f>;
31 valid-wakeup-mask = <0x00200004>;
32};
33
34&vic1 {
35 valid-mask = <0xffffffff>;
36 valid-wakeup-mask = <0x53020000>;
37};
38
39&soc {
40 clocks: clock-controller@7e00f000 {
41 compatible = "samsung,s3c6410-clock";
42 reg = <0x7e00f000 0x1000>;
43 #clock-cells = <1>;
44 };
45
46 i2c1: i2c@7f00f000 {
47 compatible = "samsung,s3c2440-i2c";
48 reg = <0x7f00f000 0x1000>;
49 interrupt-parent = <&vic0>;
50 interrupts = <5>;
51 clock-names = "i2c";
52 clocks = <&clocks PCLK_IIC1>;
53 status = "disabled";
54 #address-cells = <1>;
55 #size-cells = <0>;
56 };
57};
diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
new file mode 100644
index 000000000000..b1197d8b04de
--- /dev/null
+++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
@@ -0,0 +1,687 @@
1/*
2 * Samsung's S3C64xx SoC series common device tree source
3 * - pin control-related definitions
4 *
5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
6 *
7 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
8 * listed as device tree nodes in this file.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define PIN_PULL_NONE 0
16#define PIN_PULL_DOWN 1
17#define PIN_PULL_UP 2
18
19&pinctrl0 {
20 /*
21 * Pin banks
22 */
23
24 gpa: gpa {
25 gpio-controller;
26 #gpio-cells = <2>;
27 interrupt-controller;
28 #interrupt-cells = <2>;
29 };
30
31 gpb: gpb {
32 gpio-controller;
33 #gpio-cells = <2>;
34 interrupt-controller;
35 #interrupt-cells = <2>;
36 };
37
38 gpc: gpc {
39 gpio-controller;
40 #gpio-cells = <2>;
41 interrupt-controller;
42 #interrupt-cells = <2>;
43 };
44
45 gpd: gpd {
46 gpio-controller;
47 #gpio-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
50 };
51
52 gpe: gpe {
53 gpio-controller;
54 #gpio-cells = <2>;
55 };
56
57 gpf: gpf {
58 gpio-controller;
59 #gpio-cells = <2>;
60 interrupt-controller;
61 #interrupt-cells = <2>;
62 };
63
64 gpg: gpg {
65 gpio-controller;
66 #gpio-cells = <2>;
67 interrupt-controller;
68 #interrupt-cells = <2>;
69 };
70
71 gph: gph {
72 gpio-controller;
73 #gpio-cells = <2>;
74 interrupt-controller;
75 #interrupt-cells = <2>;
76 };
77
78 gpi: gpi {
79 gpio-controller;
80 #gpio-cells = <2>;
81 };
82
83 gpj: gpj {
84 gpio-controller;
85 #gpio-cells = <2>;
86 };
87
88 gpk: gpk {
89 gpio-controller;
90 #gpio-cells = <2>;
91 };
92
93 gpl: gpl {
94 gpio-controller;
95 #gpio-cells = <2>;
96 interrupt-controller;
97 #interrupt-cells = <2>;
98 };
99
100 gpm: gpm {
101 gpio-controller;
102 #gpio-cells = <2>;
103 interrupt-controller;
104 #interrupt-cells = <2>;
105 };
106
107 gpn: gpn {
108 gpio-controller;
109 #gpio-cells = <2>;
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 };
113
114 gpo: gpo {
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 };
120
121 gpp: gpp {
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
126 };
127
128 gpq: gpq {
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
135 /*
136 * Pin groups
137 */
138
139 uart0_data: uart0-data {
140 samsung,pins = "gpa-0", "gpa-1";
141 samsung,pin-function = <2>;
142 samsung,pin-pud = <PIN_PULL_NONE>;
143 };
144
145 uart0_fctl: uart0-fctl {
146 samsung,pins = "gpa-2", "gpa-3";
147 samsung,pin-function = <2>;
148 samsung,pin-pud = <PIN_PULL_NONE>;
149 };
150
151 uart1_data: uart1-data {
152 samsung,pins = "gpa-4", "gpa-5";
153 samsung,pin-function = <2>;
154 samsung,pin-pud = <PIN_PULL_NONE>;
155 };
156
157 uart1_fctl: uart1-fctl {
158 samsung,pins = "gpa-6", "gpa-7";
159 samsung,pin-function = <2>;
160 samsung,pin-pud = <PIN_PULL_NONE>;
161 };
162
163 uart2_data: uart2-data {
164 samsung,pins = "gpb-0", "gpb-1";
165 samsung,pin-function = <2>;
166 samsung,pin-pud = <PIN_PULL_NONE>;
167 };
168
169 uart3_data: uart3-data {
170 samsung,pins = "gpb-2", "gpb-3";
171 samsung,pin-function = <2>;
172 samsung,pin-pud = <PIN_PULL_NONE>;
173 };
174
175 ext_dma_0: ext-dma-0 {
176 samsung,pins = "gpb-0", "gpb-1";
177 samsung,pin-function = <3>;
178 samsung,pin-pud = <PIN_PULL_NONE>;
179 };
180
181 ext_dma_1: ext-dma-1 {
182 samsung,pins = "gpb-2", "gpb-3";
183 samsung,pin-function = <4>;
184 samsung,pin-pud = <PIN_PULL_NONE>;
185 };
186
187 irda_data_0: irda-data-0 {
188 samsung,pins = "gpb-0", "gpb-1";
189 samsung,pin-function = <4>;
190 samsung,pin-pud = <PIN_PULL_NONE>;
191 };
192
193 irda_data_1: irda-data-1 {
194 samsung,pins = "gpb-2", "gpb-3";
195 samsung,pin-function = <3>;
196 samsung,pin-pud = <PIN_PULL_NONE>;
197 };
198
199 irda_sdbw: irda-sdbw {
200 samsung,pins = "gpb-4";
201 samsung,pin-function = <2>;
202 samsung,pin-pud = <PIN_PULL_NONE>;
203 };
204
205 i2c0_bus: i2c0-bus {
206 samsung,pins = "gpb-5", "gpb-6";
207 samsung,pin-function = <2>;
208 samsung,pin-pud = <PIN_PULL_UP>;
209 };
210
211 i2c1_bus: i2c1-bus {
212 /* S3C6410-only */
213 samsung,pins = "gpb-2", "gpb-3";
214 samsung,pin-function = <6>;
215 samsung,pin-pud = <PIN_PULL_UP>;
216 };
217
218 spi0_bus: spi0-bus {
219 samsung,pins = "gpc-0", "gpc-1", "gpc-2";
220 samsung,pin-function = <2>;
221 samsung,pin-pud = <PIN_PULL_UP>;
222 };
223
224 spi0_cs: spi0-cs {
225 samsung,pins = "gpc-3";
226 samsung,pin-function = <2>;
227 samsung,pin-pud = <PIN_PULL_NONE>;
228 };
229
230 spi1_bus: spi1-bus {
231 samsung,pins = "gpc-4", "gpc-5", "gpc-6";
232 samsung,pin-function = <2>;
233 samsung,pin-pud = <PIN_PULL_UP>;
234 };
235
236 spi1_cs: spi1-cs {
237 samsung,pins = "gpc-7";
238 samsung,pin-function = <2>;
239 samsung,pin-pud = <PIN_PULL_NONE>;
240 };
241
242 sd0_cmd: sd0-cmd {
243 samsung,pins = "gpg-1";
244 samsung,pin-function = <2>;
245 samsung,pin-pud = <PIN_PULL_NONE>;
246 };
247
248 sd0_clk: sd0-clk {
249 samsung,pins = "gpg-0";
250 samsung,pin-function = <2>;
251 samsung,pin-pud = <PIN_PULL_NONE>;
252 };
253
254 sd0_bus1: sd0-bus1 {
255 samsung,pins = "gpg-2";
256 samsung,pin-function = <2>;
257 samsung,pin-pud = <PIN_PULL_NONE>;
258 };
259
260 sd0_bus4: sd0-bus4 {
261 samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5";
262 samsung,pin-function = <2>;
263 samsung,pin-pud = <PIN_PULL_NONE>;
264 };
265
266 sd0_cd: sd0-cd {
267 samsung,pins = "gpg-6";
268 samsung,pin-function = <2>;
269 samsung,pin-pud = <PIN_PULL_UP>;
270 };
271
272 sd1_cmd: sd1-cmd {
273 samsung,pins = "gph-1";
274 samsung,pin-function = <2>;
275 samsung,pin-pud = <PIN_PULL_NONE>;
276 };
277
278 sd1_clk: sd1-clk {
279 samsung,pins = "gph-0";
280 samsung,pin-function = <2>;
281 samsung,pin-pud = <PIN_PULL_NONE>;
282 };
283
284 sd1_bus1: sd1-bus1 {
285 samsung,pins = "gph-2";
286 samsung,pin-function = <2>;
287 samsung,pin-pud = <PIN_PULL_NONE>;
288 };
289
290 sd1_bus4: sd1-bus4 {
291 samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5";
292 samsung,pin-function = <2>;
293 samsung,pin-pud = <PIN_PULL_NONE>;
294 };
295
296 sd1_bus8: sd1-bus8 {
297 samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5",
298 "gph-6", "gph-7", "gph-8", "gph-9";
299 samsung,pin-function = <2>;
300 samsung,pin-pud = <PIN_PULL_NONE>;
301 };
302
303 sd1_cd: sd1-cd {
304 samsung,pins = "gpg-6";
305 samsung,pin-function = <3>;
306 samsung,pin-pud = <PIN_PULL_UP>;
307 };
308
309 sd2_cmd: sd2-cmd {
310 samsung,pins = "gpc-4";
311 samsung,pin-function = <3>;
312 samsung,pin-pud = <PIN_PULL_NONE>;
313 };
314
315 sd2_clk: sd2-clk {
316 samsung,pins = "gpc-5";
317 samsung,pin-function = <3>;
318 samsung,pin-pud = <PIN_PULL_NONE>;
319 };
320
321 sd2_bus1: sd2-bus1 {
322 samsung,pins = "gph-6";
323 samsung,pin-function = <3>;
324 samsung,pin-pud = <PIN_PULL_NONE>;
325 };
326
327 sd2_bus4: sd2-bus4 {
328 samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9";
329 samsung,pin-function = <3>;
330 samsung,pin-pud = <PIN_PULL_NONE>;
331 };
332
333 i2s0_bus: i2s0-bus {
334 samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
335 samsung,pin-function = <3>;
336 samsung,pin-pud = <PIN_PULL_NONE>;
337 };
338
339 i2s0_cdclk: i2s0-cdclk {
340 samsung,pins = "gpd-1";
341 samsung,pin-function = <3>;
342 samsung,pin-pud = <PIN_PULL_NONE>;
343 };
344
345 i2s1_bus: i2s1-bus {
346 samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
347 samsung,pin-function = <3>;
348 samsung,pin-pud = <PIN_PULL_NONE>;
349 };
350
351 i2s1_cdclk: i2s1-cdclk {
352 samsung,pins = "gpe-1";
353 samsung,pin-function = <3>;
354 samsung,pin-pud = <PIN_PULL_NONE>;
355 };
356
357 i2s2_bus: i2s2-bus {
358 /* S3C6410-only */
359 samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",
360 "gph-8", "gph-9";
361 samsung,pin-function = <5>;
362 samsung,pin-pud = <PIN_PULL_NONE>;
363 };
364
365 i2s2_cdclk: i2s2-cdclk {
366 /* S3C6410-only */
367 samsung,pins = "gph-7";
368 samsung,pin-function = <5>;
369 samsung,pin-pud = <PIN_PULL_NONE>;
370 };
371
372 pcm0_bus: pcm0-bus {
373 samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
374 samsung,pin-function = <2>;
375 samsung,pin-pud = <PIN_PULL_NONE>;
376 };
377
378 pcm0_extclk: pcm0-extclk {
379 samsung,pins = "gpd-1";
380 samsung,pin-function = <2>;
381 samsung,pin-pud = <PIN_PULL_NONE>;
382 };
383
384 pcm1_bus: pcm1-bus {
385 samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
386 samsung,pin-function = <2>;
387 samsung,pin-pud = <PIN_PULL_NONE>;
388 };
389
390 pcm1_extclk: pcm1-extclk {
391 samsung,pins = "gpe-1";
392 samsung,pin-function = <2>;
393 samsung,pin-pud = <PIN_PULL_NONE>;
394 };
395
396 ac97_bus_0: ac97-bus-0 {
397 samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4";
398 samsung,pin-function = <4>;
399 samsung,pin-pud = <PIN_PULL_NONE>;
400 };
401
402 ac97_bus_1: ac97-bus-1 {
403 samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4";
404 samsung,pin-function = <4>;
405 samsung,pin-pud = <PIN_PULL_NONE>;
406 };
407
408 cam_port: cam-port {
409 samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4",
410 "gpf-5", "gpf-6", "gpf-7", "gpf-8",
411 "gpf-9", "gpf-10", "gpf-11", "gpf-12";
412 samsung,pin-function = <2>;
413 samsung,pin-pud = <PIN_PULL_NONE>;
414 };
415
416 cam_rst: cam-rst {
417 samsung,pins = "gpf-3";
418 samsung,pin-function = <2>;
419 samsung,pin-pud = <PIN_PULL_NONE>;
420 };
421
422 cam_field: cam-field {
423 /* S3C6410-only */
424 samsung,pins = "gpb-4";
425 samsung,pin-function = <3>;
426 samsung,pin-pud = <PIN_PULL_NONE>;
427 };
428
429 pwm_extclk: pwm-extclk {
430 samsung,pins = "gpf-13";
431 samsung,pin-function = <2>;
432 samsung,pin-pud = <PIN_PULL_NONE>;
433 };
434
435 pwm0_out: pwm0-out {
436 samsung,pins = "gpf-14";
437 samsung,pin-function = <2>;
438 samsung,pin-pud = <PIN_PULL_NONE>;
439 };
440
441 pwm1_out: pwm1-out {
442 samsung,pins = "gpf-15";
443 samsung,pin-function = <2>;
444 samsung,pin-pud = <PIN_PULL_NONE>;
445 };
446
447 clkout0: clkout-0 {
448 samsung,pins = "gpf-14";
449 samsung,pin-function = <3>;
450 samsung,pin-pud = <PIN_PULL_NONE>;
451 };
452
453 keypad_col0_0: keypad-col0-0 {
454 samsung,pins = "gph-0";
455 samsung,pin-function = <4>;
456 samsung,pin-pud = <PIN_PULL_NONE>;
457 };
458
459 keypad_col1_0: keypad-col1-0 {
460 samsung,pins = "gph-1";
461 samsung,pin-function = <4>;
462 samsung,pin-pud = <PIN_PULL_NONE>;
463 };
464
465 keypad_col2_0: keypad-col2-0 {
466 samsung,pins = "gph-2";
467 samsung,pin-function = <4>;
468 samsung,pin-pud = <PIN_PULL_NONE>;
469 };
470
471 keypad_col3_0: keypad-col3-0 {
472 samsung,pins = "gph-3";
473 samsung,pin-function = <4>;
474 samsung,pin-pud = <PIN_PULL_NONE>;
475 };
476
477 keypad_col4_0: keypad-col4-0 {
478 samsung,pins = "gph-4";
479 samsung,pin-function = <4>;
480 samsung,pin-pud = <PIN_PULL_NONE>;
481 };
482
483 keypad_col5_0: keypad-col5-0 {
484 samsung,pins = "gph-5";
485 samsung,pin-function = <4>;
486 samsung,pin-pud = <PIN_PULL_NONE>;
487 };
488
489 keypad_col6_0: keypad-col6-0 {
490 samsung,pins = "gph-6";
491 samsung,pin-function = <4>;
492 samsung,pin-pud = <PIN_PULL_NONE>;
493 };
494
495 keypad_col7_0: keypad-col7-0 {
496 samsung,pins = "gph-7";
497 samsung,pin-function = <4>;
498 samsung,pin-pud = <PIN_PULL_NONE>;
499 };
500
501 keypad_col0_1: keypad-col0-1 {
502 samsung,pins = "gpl-0";
503 samsung,pin-function = <3>;
504 samsung,pin-pud = <PIN_PULL_NONE>;
505 };
506
507 keypad_col1_1: keypad-col1-1 {
508 samsung,pins = "gpl-1";
509 samsung,pin-function = <3>;
510 samsung,pin-pud = <PIN_PULL_NONE>;
511 };
512
513 keypad_col2_1: keypad-col2-1 {
514 samsung,pins = "gpl-2";
515 samsung,pin-function = <3>;
516 samsung,pin-pud = <PIN_PULL_NONE>;
517 };
518
519 keypad_col3_1: keypad-col3-1 {
520 samsung,pins = "gpl-3";
521 samsung,pin-function = <3>;
522 samsung,pin-pud = <PIN_PULL_NONE>;
523 };
524
525 keypad_col4_1: keypad-col4-1 {
526 samsung,pins = "gpl-4";
527 samsung,pin-function = <3>;
528 samsung,pin-pud = <PIN_PULL_NONE>;
529 };
530
531 keypad_col5_1: keypad-col5-1 {
532 samsung,pins = "gpl-5";
533 samsung,pin-function = <3>;
534 samsung,pin-pud = <PIN_PULL_NONE>;
535 };
536
537 keypad_col6_1: keypad-col6-1 {
538 samsung,pins = "gpl-6";
539 samsung,pin-function = <3>;
540 samsung,pin-pud = <PIN_PULL_NONE>;
541 };
542
543 keypad_col7_1: keypad-col7-1 {
544 samsung,pins = "gpl-7";
545 samsung,pin-function = <3>;
546 samsung,pin-pud = <PIN_PULL_NONE>;
547 };
548
549 keypad_row0_0: keypad-row0-0 {
550 samsung,pins = "gpk-8";
551 samsung,pin-function = <3>;
552 samsung,pin-pud = <PIN_PULL_NONE>;
553 };
554
555 keypad_row1_0: keypad-row1-0 {
556 samsung,pins = "gpk-9";
557 samsung,pin-function = <3>;
558 samsung,pin-pud = <PIN_PULL_NONE>;
559 };
560
561 keypad_row2_0: keypad-row2-0 {
562 samsung,pins = "gpk-10";
563 samsung,pin-function = <3>;
564 samsung,pin-pud = <PIN_PULL_NONE>;
565 };
566
567 keypad_row3_0: keypad-row3-0 {
568 samsung,pins = "gpk-11";
569 samsung,pin-function = <3>;
570 samsung,pin-pud = <PIN_PULL_NONE>;
571 };
572
573 keypad_row4_0: keypad-row4-0 {
574 samsung,pins = "gpk-12";
575 samsung,pin-function = <3>;
576 samsung,pin-pud = <PIN_PULL_NONE>;
577 };
578
579 keypad_row5_0: keypad-row5-0 {
580 samsung,pins = "gpk-13";
581 samsung,pin-function = <3>;
582 samsung,pin-pud = <PIN_PULL_NONE>;
583 };
584
585 keypad_row6_0: keypad-row6-0 {
586 samsung,pins = "gpk-14";
587 samsung,pin-function = <3>;
588 samsung,pin-pud = <PIN_PULL_NONE>;
589 };
590
591 keypad_row7_0: keypad-row7-0 {
592 samsung,pins = "gpk-15";
593 samsung,pin-function = <3>;
594 samsung,pin-pud = <PIN_PULL_NONE>;
595 };
596
597 keypad_row0_1: keypad-row0-1 {
598 samsung,pins = "gpn-0";
599 samsung,pin-function = <3>;
600 samsung,pin-pud = <PIN_PULL_NONE>;
601 };
602
603 keypad_row1_1: keypad-row1-1 {
604 samsung,pins = "gpn-1";
605 samsung,pin-function = <3>;
606 samsung,pin-pud = <PIN_PULL_NONE>;
607 };
608
609 keypad_row2_1: keypad-row2-1 {
610 samsung,pins = "gpn-2";
611 samsung,pin-function = <3>;
612 samsung,pin-pud = <PIN_PULL_NONE>;
613 };
614
615 keypad_row3_1: keypad-row3-1 {
616 samsung,pins = "gpn-3";
617 samsung,pin-function = <3>;
618 samsung,pin-pud = <PIN_PULL_NONE>;
619 };
620
621 keypad_row4_1: keypad-row4-1 {
622 samsung,pins = "gpn-4";
623 samsung,pin-function = <3>;
624 samsung,pin-pud = <PIN_PULL_NONE>;
625 };
626
627 keypad_row5_1: keypad-row5-1 {
628 samsung,pins = "gpn-5";
629 samsung,pin-function = <3>;
630 samsung,pin-pud = <PIN_PULL_NONE>;
631 };
632
633 keypad_row6_1: keypad-row6-1 {
634 samsung,pins = "gpn-6";
635 samsung,pin-function = <3>;
636 samsung,pin-pud = <PIN_PULL_NONE>;
637 };
638
639 keypad_row7_1: keypad-row7-1 {
640 samsung,pins = "gpn-7";
641 samsung,pin-function = <3>;
642 samsung,pin-pud = <PIN_PULL_NONE>;
643 };
644
645 lcd_ctrl: lcd-ctrl {
646 samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11";
647 samsung,pin-function = <2>;
648 samsung,pin-pud = <PIN_PULL_NONE>;
649 };
650
651 lcd_data16: lcd-data-width16 {
652 samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6",
653 "gpi-7", "gpi-10", "gpi-11", "gpi-12",
654 "gpi-13", "gpi-14", "gpi-15", "gpj-3",
655 "gpj-4", "gpj-5", "gpj-6", "gpj-7";
656 samsung,pin-function = <2>;
657 samsung,pin-pud = <PIN_PULL_NONE>;
658 };
659
660 lcd_data18: lcd-data-width18 {
661 samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5",
662 "gpi-6", "gpi-7", "gpi-10", "gpi-11",
663 "gpi-12", "gpi-13", "gpi-14", "gpi-15",
664 "gpj-2", "gpj-3", "gpj-4", "gpj-5",
665 "gpj-6", "gpj-7";
666 samsung,pin-function = <2>;
667 samsung,pin-pud = <PIN_PULL_NONE>;
668 };
669
670 lcd_data24: lcd-data-width24 {
671 samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
672 "gpi-4", "gpi-5", "gpi-6", "gpi-7",
673 "gpi-8", "gpi-9", "gpi-10", "gpi-11",
674 "gpi-12", "gpi-13", "gpi-14", "gpi-15",
675 "gpj-0", "gpj-1", "gpj-2", "gpj-3",
676 "gpj-4", "gpj-5", "gpj-6", "gpj-7";
677 samsung,pin-function = <2>;
678 samsung,pin-pud = <PIN_PULL_NONE>;
679 };
680
681 hsi_bus: hsi-bus {
682 samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3",
683 "gpk-4", "gpk-5", "gpk-6", "gpk-7";
684 samsung,pin-function = <3>;
685 samsung,pin-pud = <PIN_PULL_NONE>;
686 };
687};
diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi
new file mode 100644
index 000000000000..4e3be4d3493d
--- /dev/null
+++ b/arch/arm/boot/dts/s3c64xx.dtsi
@@ -0,0 +1,199 @@
1/*
2 * Samsung's S3C64xx SoC series common device tree source
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * Samsung's S3C64xx SoC series device nodes are listed in this file.
7 * Particular SoCs from S3C64xx series can include this file and provide
8 * values for SoCs specfic bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
12 * nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include "skeleton.dtsi"
20#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
21
22/ {
23 aliases {
24 i2c0 = &i2c0;
25 pinctrl0 = &pinctrl0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 device_type = "cpu";
34 compatible = "arm,arm1176jzf-s", "arm,arm1176";
35 reg = <0x0>;
36 };
37 };
38
39 soc: soc {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
44
45 vic0: interrupt-controller@71200000 {
46 compatible = "arm,pl192-vic";
47 interrupt-controller;
48 reg = <0x71200000 0x1000>;
49 #interrupt-cells = <1>;
50 };
51
52 vic1: interrupt-controller@71300000 {
53 compatible = "arm,pl192-vic";
54 interrupt-controller;
55 reg = <0x71300000 0x1000>;
56 #interrupt-cells = <1>;
57 };
58
59 sdhci0: sdhci@7c200000 {
60 compatible = "samsung,s3c6410-sdhci";
61 reg = <0x7c200000 0x100>;
62 interrupt-parent = <&vic1>;
63 interrupts = <24>;
64 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
65 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
66 <&clocks SCLK_MMC0>;
67 status = "disabled";
68 };
69
70 sdhci1: sdhci@7c300000 {
71 compatible = "samsung,s3c6410-sdhci";
72 reg = <0x7c300000 0x100>;
73 interrupt-parent = <&vic1>;
74 interrupts = <25>;
75 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
76 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
77 <&clocks SCLK_MMC1>;
78 status = "disabled";
79 };
80
81 sdhci2: sdhci@7c400000 {
82 compatible = "samsung,s3c6410-sdhci";
83 reg = <0x7c400000 0x100>;
84 interrupt-parent = <&vic1>;
85 interrupts = <17>;
86 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
87 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
88 <&clocks SCLK_MMC2>;
89 status = "disabled";
90 };
91
92 watchdog: watchdog@7e004000 {
93 compatible = "samsung,s3c2410-wdt";
94 reg = <0x7e004000 0x1000>;
95 interrupt-parent = <&vic0>;
96 interrupts = <26>;
97 clock-names = "watchdog";
98 clocks = <&clocks PCLK_WDT>;
99 status = "disabled";
100 };
101
102 i2c0: i2c@7f004000 {
103 compatible = "samsung,s3c2440-i2c";
104 reg = <0x7f004000 0x1000>;
105 interrupt-parent = <&vic1>;
106 interrupts = <18>;
107 clock-names = "i2c";
108 clocks = <&clocks PCLK_IIC0>;
109 status = "disabled";
110 #address-cells = <1>;
111 #size-cells = <0>;
112 };
113
114 uart0: serial@7f005000 {
115 compatible = "samsung,s3c6400-uart";
116 reg = <0x7f005000 0x100>;
117 interrupt-parent = <&vic1>;
118 interrupts = <5>;
119 clock-names = "uart", "clk_uart_baud2",
120 "clk_uart_baud3";
121 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
122 <&clocks SCLK_UART>;
123 status = "disabled";
124 };
125
126 uart1: serial@7f005400 {
127 compatible = "samsung,s3c6400-uart";
128 reg = <0x7f005400 0x100>;
129 interrupt-parent = <&vic1>;
130 interrupts = <6>;
131 clock-names = "uart", "clk_uart_baud2",
132 "clk_uart_baud3";
133 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
134 <&clocks SCLK_UART>;
135 status = "disabled";
136 };
137
138 uart2: serial@7f005800 {
139 compatible = "samsung,s3c6400-uart";
140 reg = <0x7f005800 0x100>;
141 interrupt-parent = <&vic1>;
142 interrupts = <7>;
143 clock-names = "uart", "clk_uart_baud2",
144 "clk_uart_baud3";
145 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
146 <&clocks SCLK_UART>;
147 status = "disabled";
148 };
149
150 uart3: serial@7f005c00 {
151 compatible = "samsung,s3c6400-uart";
152 reg = <0x7f005c00 0x100>;
153 interrupt-parent = <&vic1>;
154 interrupts = <8>;
155 clock-names = "uart", "clk_uart_baud2",
156 "clk_uart_baud3";
157 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
158 <&clocks SCLK_UART>;
159 status = "disabled";
160 };
161
162 pwm: pwm@7f006000 {
163 compatible = "samsung,s3c6400-pwm";
164 reg = <0x7f006000 0x1000>;
165 interrupt-parent = <&vic0>;
166 interrupts = <23>, <24>, <25>, <27>, <28>;
167 clock-names = "timers";
168 clocks = <&clocks PCLK_PWM>;
169 samsung,pwm-outputs = <0>, <1>;
170 #pwm-cells = <3>;
171 status = "disabled";
172 };
173
174 pinctrl0: pinctrl@7f008000 {
175 compatible = "samsung,s3c64xx-pinctrl";
176 reg = <0x7f008000 0x1000>;
177 interrupt-parent = <&vic1>;
178 interrupts = <21>;
179
180 pctrl_int_map: pinctrl-interrupt-map {
181 interrupt-map = <0 &vic0 0>,
182 <1 &vic0 1>,
183 <2 &vic1 0>,
184 <3 &vic1 1>;
185 #address-cells = <0>;
186 #size-cells = <0>;
187 #interrupt-cells = <1>;
188 };
189
190 wakeup-interrupt-controller {
191 compatible = "samsung,s3c64xx-wakeup-eint";
192 interrupts = <0>, <1>, <2>, <3>;
193 interrupt-parent = <&pctrl_int_map>;
194 };
195 };
196 };
197};
198
199#include "s3c64xx-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 212230629f27..8ee06dd81799 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -108,6 +108,7 @@
108}; 108};
109 109
110&i2c0 { 110&i2c0 {
111 status = "okay";
111 as3711@40 { 112 as3711@40 {
112 compatible = "ams,as3711"; 113 compatible = "ams,as3711";
113 reg = <0x40>; 114 reg = <0x40>;
@@ -183,6 +184,7 @@
183&i2c3 { 184&i2c3 {
184 pinctrl-0 = <&i2c3_pins>; 185 pinctrl-0 = <&i2c3_pins>;
185 pinctrl-names = "default"; 186 pinctrl-names = "default";
187 status = "okay";
186}; 188};
187 189
188&mmcif { 190&mmcif {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 3955c7606a6f..fcf26889a8a0 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -135,6 +135,7 @@
135 0 168 0x4 135 0 168 0x4
136 0 169 0x4 136 0 169 0x4
137 0 170 0x4>; 137 0 170 0x4>;
138 status = "disabled";
138 }; 139 };
139 140
140 i2c1: i2c@e6822000 { 141 i2c1: i2c@e6822000 {
@@ -147,6 +148,7 @@
147 0 52 0x4 148 0 52 0x4
148 0 53 0x4 149 0 53 0x4
149 0 54 0x4>; 150 0 54 0x4>;
151 status = "disabled";
150 }; 152 };
151 153
152 i2c2: i2c@e6824000 { 154 i2c2: i2c@e6824000 {
@@ -159,6 +161,7 @@
159 0 172 0x4 161 0 172 0x4
160 0 173 0x4 162 0 173 0x4
161 0 174 0x4>; 163 0 174 0x4>;
164 status = "disabled";
162 }; 165 };
163 166
164 i2c3: i2c@e6826000 { 167 i2c3: i2c@e6826000 {
@@ -171,6 +174,7 @@
171 0 184 0x4 174 0 184 0x4
172 0 185 0x4 175 0 185 0x4
173 0 186 0x4>; 176 0 186 0x4>;
177 status = "disabled";
174 }; 178 };
175 179
176 i2c4: i2c@e6828000 { 180 i2c4: i2c@e6828000 {
@@ -183,6 +187,7 @@
183 0 188 0x4 187 0 188 0x4
184 0 189 0x4 188 0 189 0x4
185 0 190 0x4>; 189 0 190 0x4>;
190 status = "disabled";
186 }; 191 };
187 192
188 mmcif: mmcif@e6bd0000 { 193 mmcif: mmcif@e6bd0000 {
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index e273fa993b8c..6d09b8d42fdd 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -147,7 +147,7 @@
147 reg = <0x58>; 147 reg = <0x58>;
148 }; 148 };
149 149
150 cfg_s2f_usr0_clk: cfg_s2f_usr0_clk { 150 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
151 #clock-cells = <0>; 151 #clock-cells = <0>;
152 compatible = "altr,socfpga-perip-clk"; 152 compatible = "altr,socfpga-perip-clk";
153 clocks = <&main_pll>; 153 clocks = <&main_pll>;
@@ -198,7 +198,7 @@
198 reg = <0x98>; 198 reg = <0x98>;
199 }; 199 };
200 200
201 s2f_usr1_clk: s2f_usr1_clk { 201 h2f_usr1_clk: h2f_usr1_clk {
202 #clock-cells = <0>; 202 #clock-cells = <0>;
203 compatible = "altr,socfpga-perip-clk"; 203 compatible = "altr,socfpga-perip-clk";
204 clocks = <&periph_pll>; 204 clocks = <&periph_pll>;
@@ -235,7 +235,7 @@
235 reg = <0xD0>; 235 reg = <0xD0>;
236 }; 236 };
237 237
238 s2f_usr2_clk: s2f_usr2_clk { 238 h2f_usr2_clk: h2f_usr2_clk {
239 #clock-cells = <0>; 239 #clock-cells = <0>;
240 compatible = "altr,socfpga-perip-clk"; 240 compatible = "altr,socfpga-perip-clk";
241 clocks = <&sdram_pll>; 241 clocks = <&sdram_pll>;
@@ -243,197 +243,197 @@
243 }; 243 };
244 }; 244 };
245 245
246 mpu_periph_clk: mpu_periph_clk { 246 mpu_periph_clk: mpu_periph_clk {
247 #clock-cells = <0>; 247 #clock-cells = <0>;
248 compatible = "altr,socfpga-gate-clk"; 248 compatible = "altr,socfpga-gate-clk";
249 clocks = <&mpuclk>; 249 clocks = <&mpuclk>;
250 fixed-divider = <4>; 250 fixed-divider = <4>;
251 }; 251 };
252 252
253 mpu_l2_ram_clk: mpu_l2_ram_clk { 253 mpu_l2_ram_clk: mpu_l2_ram_clk {
254 #clock-cells = <0>; 254 #clock-cells = <0>;
255 compatible = "altr,socfpga-gate-clk"; 255 compatible = "altr,socfpga-gate-clk";
256 clocks = <&mpuclk>; 256 clocks = <&mpuclk>;
257 fixed-divider = <2>; 257 fixed-divider = <2>;
258 }; 258 };
259 259
260 l4_main_clk: l4_main_clk { 260 l4_main_clk: l4_main_clk {
261 #clock-cells = <0>; 261 #clock-cells = <0>;
262 compatible = "altr,socfpga-gate-clk"; 262 compatible = "altr,socfpga-gate-clk";
263 clocks = <&mainclk>; 263 clocks = <&mainclk>;
264 clk-gate = <0x60 0>; 264 clk-gate = <0x60 0>;
265 }; 265 };
266 266
267 l3_main_clk: l3_main_clk { 267 l3_main_clk: l3_main_clk {
268 #clock-cells = <0>; 268 #clock-cells = <0>;
269 compatible = "altr,socfpga-gate-clk"; 269 compatible = "altr,socfpga-gate-clk";
270 clocks = <&mainclk>; 270 clocks = <&mainclk>;
271 }; 271 };
272 272
273 l3_mp_clk: l3_mp_clk { 273 l3_mp_clk: l3_mp_clk {
274 #clock-cells = <0>; 274 #clock-cells = <0>;
275 compatible = "altr,socfpga-gate-clk"; 275 compatible = "altr,socfpga-gate-clk";
276 clocks = <&mainclk>; 276 clocks = <&mainclk>;
277 div-reg = <0x64 0 2>; 277 div-reg = <0x64 0 2>;
278 clk-gate = <0x60 1>; 278 clk-gate = <0x60 1>;
279 }; 279 };
280 280
281 l3_sp_clk: l3_sp_clk { 281 l3_sp_clk: l3_sp_clk {
282 #clock-cells = <0>; 282 #clock-cells = <0>;
283 compatible = "altr,socfpga-gate-clk"; 283 compatible = "altr,socfpga-gate-clk";
284 clocks = <&mainclk>; 284 clocks = <&mainclk>;
285 div-reg = <0x64 2 2>; 285 div-reg = <0x64 2 2>;
286 }; 286 };
287 287
288 l4_mp_clk: l4_mp_clk { 288 l4_mp_clk: l4_mp_clk {
289 #clock-cells = <0>; 289 #clock-cells = <0>;
290 compatible = "altr,socfpga-gate-clk"; 290 compatible = "altr,socfpga-gate-clk";
291 clocks = <&mainclk>, <&per_base_clk>; 291 clocks = <&mainclk>, <&per_base_clk>;
292 div-reg = <0x64 4 3>; 292 div-reg = <0x64 4 3>;
293 clk-gate = <0x60 2>; 293 clk-gate = <0x60 2>;
294 }; 294 };
295 295
296 l4_sp_clk: l4_sp_clk { 296 l4_sp_clk: l4_sp_clk {
297 #clock-cells = <0>; 297 #clock-cells = <0>;
298 compatible = "altr,socfpga-gate-clk"; 298 compatible = "altr,socfpga-gate-clk";
299 clocks = <&mainclk>, <&per_base_clk>; 299 clocks = <&mainclk>, <&per_base_clk>;
300 div-reg = <0x64 7 3>; 300 div-reg = <0x64 7 3>;
301 clk-gate = <0x60 3>; 301 clk-gate = <0x60 3>;
302 }; 302 };
303 303
304 dbg_at_clk: dbg_at_clk { 304 dbg_at_clk: dbg_at_clk {
305 #clock-cells = <0>; 305 #clock-cells = <0>;
306 compatible = "altr,socfpga-gate-clk"; 306 compatible = "altr,socfpga-gate-clk";
307 clocks = <&dbg_base_clk>; 307 clocks = <&dbg_base_clk>;
308 div-reg = <0x68 0 2>; 308 div-reg = <0x68 0 2>;
309 clk-gate = <0x60 4>; 309 clk-gate = <0x60 4>;
310 }; 310 };
311 311
312 dbg_clk: dbg_clk { 312 dbg_clk: dbg_clk {
313 #clock-cells = <0>; 313 #clock-cells = <0>;
314 compatible = "altr,socfpga-gate-clk"; 314 compatible = "altr,socfpga-gate-clk";
315 clocks = <&dbg_base_clk>; 315 clocks = <&dbg_base_clk>;
316 div-reg = <0x68 2 2>; 316 div-reg = <0x68 2 2>;
317 clk-gate = <0x60 5>; 317 clk-gate = <0x60 5>;
318 }; 318 };
319 319
320 dbg_trace_clk: dbg_trace_clk { 320 dbg_trace_clk: dbg_trace_clk {
321 #clock-cells = <0>; 321 #clock-cells = <0>;
322 compatible = "altr,socfpga-gate-clk"; 322 compatible = "altr,socfpga-gate-clk";
323 clocks = <&dbg_base_clk>; 323 clocks = <&dbg_base_clk>;
324 div-reg = <0x6C 0 3>; 324 div-reg = <0x6C 0 3>;
325 clk-gate = <0x60 6>; 325 clk-gate = <0x60 6>;
326 }; 326 };
327 327
328 dbg_timer_clk: dbg_timer_clk { 328 dbg_timer_clk: dbg_timer_clk {
329 #clock-cells = <0>; 329 #clock-cells = <0>;
330 compatible = "altr,socfpga-gate-clk"; 330 compatible = "altr,socfpga-gate-clk";
331 clocks = <&dbg_base_clk>; 331 clocks = <&dbg_base_clk>;
332 clk-gate = <0x60 7>; 332 clk-gate = <0x60 7>;
333 }; 333 };
334 334
335 cfg_clk: cfg_clk { 335 cfg_clk: cfg_clk {
336 #clock-cells = <0>; 336 #clock-cells = <0>;
337 compatible = "altr,socfpga-gate-clk"; 337 compatible = "altr,socfpga-gate-clk";
338 clocks = <&cfg_s2f_usr0_clk>; 338 clocks = <&cfg_h2f_usr0_clk>;
339 clk-gate = <0x60 8>; 339 clk-gate = <0x60 8>;
340 }; 340 };
341 341
342 s2f_user0_clk: s2f_user0_clk { 342 h2f_user0_clk: h2f_user0_clk {
343 #clock-cells = <0>; 343 #clock-cells = <0>;
344 compatible = "altr,socfpga-gate-clk"; 344 compatible = "altr,socfpga-gate-clk";
345 clocks = <&cfg_s2f_usr0_clk>; 345 clocks = <&cfg_h2f_usr0_clk>;
346 clk-gate = <0x60 9>; 346 clk-gate = <0x60 9>;
347 }; 347 };
348 348
349 emac_0_clk: emac_0_clk { 349 emac_0_clk: emac_0_clk {
350 #clock-cells = <0>; 350 #clock-cells = <0>;
351 compatible = "altr,socfpga-gate-clk"; 351 compatible = "altr,socfpga-gate-clk";
352 clocks = <&emac0_clk>; 352 clocks = <&emac0_clk>;
353 clk-gate = <0xa0 0>; 353 clk-gate = <0xa0 0>;
354 }; 354 };
355 355
356 emac_1_clk: emac_1_clk { 356 emac_1_clk: emac_1_clk {
357 #clock-cells = <0>; 357 #clock-cells = <0>;
358 compatible = "altr,socfpga-gate-clk"; 358 compatible = "altr,socfpga-gate-clk";
359 clocks = <&emac1_clk>; 359 clocks = <&emac1_clk>;
360 clk-gate = <0xa0 1>; 360 clk-gate = <0xa0 1>;
361 }; 361 };
362 362
363 usb_mp_clk: usb_mp_clk { 363 usb_mp_clk: usb_mp_clk {
364 #clock-cells = <0>; 364 #clock-cells = <0>;
365 compatible = "altr,socfpga-gate-clk"; 365 compatible = "altr,socfpga-gate-clk";
366 clocks = <&per_base_clk>; 366 clocks = <&per_base_clk>;
367 clk-gate = <0xa0 2>; 367 clk-gate = <0xa0 2>;
368 div-reg = <0xa4 0 3>; 368 div-reg = <0xa4 0 3>;
369 }; 369 };
370 370
371 spi_m_clk: spi_m_clk { 371 spi_m_clk: spi_m_clk {
372 #clock-cells = <0>; 372 #clock-cells = <0>;
373 compatible = "altr,socfpga-gate-clk"; 373 compatible = "altr,socfpga-gate-clk";
374 clocks = <&per_base_clk>; 374 clocks = <&per_base_clk>;
375 clk-gate = <0xa0 3>; 375 clk-gate = <0xa0 3>;
376 div-reg = <0xa4 3 3>; 376 div-reg = <0xa4 3 3>;
377 }; 377 };
378 378
379 can0_clk: can0_clk { 379 can0_clk: can0_clk {
380 #clock-cells = <0>; 380 #clock-cells = <0>;
381 compatible = "altr,socfpga-gate-clk"; 381 compatible = "altr,socfpga-gate-clk";
382 clocks = <&per_base_clk>; 382 clocks = <&per_base_clk>;
383 clk-gate = <0xa0 4>; 383 clk-gate = <0xa0 4>;
384 div-reg = <0xa4 6 3>; 384 div-reg = <0xa4 6 3>;
385 }; 385 };
386 386
387 can1_clk: can1_clk { 387 can1_clk: can1_clk {
388 #clock-cells = <0>; 388 #clock-cells = <0>;
389 compatible = "altr,socfpga-gate-clk"; 389 compatible = "altr,socfpga-gate-clk";
390 clocks = <&per_base_clk>; 390 clocks = <&per_base_clk>;
391 clk-gate = <0xa0 5>; 391 clk-gate = <0xa0 5>;
392 div-reg = <0xa4 9 3>; 392 div-reg = <0xa4 9 3>;
393 }; 393 };
394 394
395 gpio_db_clk: gpio_db_clk { 395 gpio_db_clk: gpio_db_clk {
396 #clock-cells = <0>; 396 #clock-cells = <0>;
397 compatible = "altr,socfpga-gate-clk"; 397 compatible = "altr,socfpga-gate-clk";
398 clocks = <&per_base_clk>; 398 clocks = <&per_base_clk>;
399 clk-gate = <0xa0 6>; 399 clk-gate = <0xa0 6>;
400 div-reg = <0xa8 0 24>; 400 div-reg = <0xa8 0 24>;
401 }; 401 };
402 402
403 s2f_user1_clk: s2f_user1_clk { 403 h2f_user1_clk: h2f_user1_clk {
404 #clock-cells = <0>; 404 #clock-cells = <0>;
405 compatible = "altr,socfpga-gate-clk"; 405 compatible = "altr,socfpga-gate-clk";
406 clocks = <&s2f_usr1_clk>; 406 clocks = <&h2f_usr1_clk>;
407 clk-gate = <0xa0 7>; 407 clk-gate = <0xa0 7>;
408 }; 408 };
409 409
410 sdmmc_clk: sdmmc_clk { 410 sdmmc_clk: sdmmc_clk {
411 #clock-cells = <0>; 411 #clock-cells = <0>;
412 compatible = "altr,socfpga-gate-clk"; 412 compatible = "altr,socfpga-gate-clk";
413 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 413 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
414 clk-gate = <0xa0 8>; 414 clk-gate = <0xa0 8>;
415 }; 415 };
416 416
417 nand_x_clk: nand_x_clk { 417 nand_x_clk: nand_x_clk {
418 #clock-cells = <0>; 418 #clock-cells = <0>;
419 compatible = "altr,socfpga-gate-clk"; 419 compatible = "altr,socfpga-gate-clk";
420 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 420 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
421 clk-gate = <0xa0 9>; 421 clk-gate = <0xa0 9>;
422 }; 422 };
423 423
424 nand_clk: nand_clk { 424 nand_clk: nand_clk {
425 #clock-cells = <0>; 425 #clock-cells = <0>;
426 compatible = "altr,socfpga-gate-clk"; 426 compatible = "altr,socfpga-gate-clk";
427 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 427 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
428 clk-gate = <0xa0 10>; 428 clk-gate = <0xa0 10>;
429 fixed-divider = <4>; 429 fixed-divider = <4>;
430 }; 430 };
431 431
432 qspi_clk: qspi_clk { 432 qspi_clk: qspi_clk {
433 #clock-cells = <0>; 433 #clock-cells = <0>;
434 compatible = "altr,socfpga-gate-clk"; 434 compatible = "altr,socfpga-gate-clk";
435 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; 435 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
436 clk-gate = <0xa0 11>; 436 clk-gate = <0xa0 11>;
437 }; 437 };
438 }; 438 };
439 }; 439 };
@@ -473,6 +473,7 @@
473 compatible = "arm,cortex-a9-twd-timer"; 473 compatible = "arm,cortex-a9-twd-timer";
474 reg = <0xfffec600 0x100>; 474 reg = <0xfffec600 0x100>;
475 interrupts = <1 13 0xf04>; 475 interrupts = <1 13 0xf04>;
476 clocks = <&mpu_periph_clk>;
476 }; 477 };
477 478
478 timer0: timer0@ffc08000 { 479 timer0: timer0@ffc08000 {
@@ -516,9 +517,9 @@
516 }; 517 };
517 518
518 rstmgr@ffd05000 { 519 rstmgr@ffd05000 {
519 compatible = "altr,rst-mgr"; 520 compatible = "altr,rst-mgr";
520 reg = <0xffd05000 0x1000>; 521 reg = <0xffd05000 0x1000>;
521 }; 522 };
522 523
523 sysmgr@ffd08000 { 524 sysmgr@ffd08000 {
524 compatible = "altr,sys-mgr"; 525 compatible = "altr,sys-mgr";
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
new file mode 100644
index 000000000000..a85b4043f888
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -0,0 +1,58 @@
1/*
2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18/include/ "socfpga.dtsi"
19
20/ {
21 soc {
22 clkmgr@ffd04000 {
23 clocks {
24 osc1 {
25 clock-frequency = <25000000>;
26 };
27 };
28 };
29
30 serial0@ffc02000 {
31 clock-frequency = <100000000>;
32 };
33
34 serial1@ffc03000 {
35 clock-frequency = <100000000>;
36 };
37
38 sysmgr@ffd08000 {
39 cpu1-start-addr = <0xffd080c4>;
40 };
41
42 timer0@ffc08000 {
43 clock-frequency = <100000000>;
44 };
45
46 timer1@ffc09000 {
47 clock-frequency = <100000000>;
48 };
49
50 timer2@ffd00000 {
51 clock-frequency = <25000000>;
52 };
53
54 timer3@ffd01000 {
55 clock-frequency = <25000000>;
56 };
57 };
58};
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
new file mode 100644
index 000000000000..5beffb2265f4
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -0,0 +1,40 @@
1/*
2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/include/ "socfpga_arria5.dtsi"
19
20/ {
21 model = "Altera SOCFPGA Arria V SoC Development Kit";
22 compatible = "altr,socfpga-arria5", "altr,socfpga";
23
24 chosen {
25 bootargs = "console=ttyS0,115200";
26 };
27
28 memory {
29 name = "memory";
30 device_type = "memory";
31 reg = <0x0 0x40000000>; /* 1GB */
32 };
33
34 aliases {
35 /* this allow the ethaddr uboot environmnet variable contents
36 * to be added to the gmac1 device tree blob.
37 */
38 ethernet0 = &gmac1;
39 };
40};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 973999d2c697..a8716f6dbe2e 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -19,26 +19,6 @@
19/include/ "socfpga.dtsi" 19/include/ "socfpga.dtsi"
20 20
21/ { 21/ {
22 model = "Altera SOCFPGA Cyclone V";
23 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
24
25 chosen {
26 bootargs = "console=ttyS0,57600";
27 };
28
29 memory {
30 name = "memory";
31 device_type = "memory";
32 reg = <0x0 0x40000000>; /* 1GB */
33 };
34
35 aliases {
36 /* this allow the ethaddr uboot environmnet variable contents
37 * to be added to the gmac1 device tree blob.
38 */
39 ethernet0 = &gmac1;
40 };
41
42 soc { 22 soc {
43 clkmgr@ffd04000 { 23 clkmgr@ffd04000 {
44 clocks { 24 clocks {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
new file mode 100644
index 000000000000..2ee52ab8cabb
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -0,0 +1,40 @@
1/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/include/ "socfpga_cyclone5.dtsi"
19
20/ {
21 model = "Altera SOCFPGA Cyclone V SoC Development Kit";
22 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
23
24 chosen {
25 bootargs = "console=ttyS0,115200";
26 };
27
28 memory {
29 name = "memory";
30 device_type = "memory";
31 reg = <0x0 0x40000000>; /* 1GB */
32 };
33
34 aliases {
35 /* this allow the ethaddr uboot environmnet variable contents
36 * to be added to the gmac1 device tree blob.
37 */
38 ethernet0 = &gmac1;
39 };
40};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
new file mode 100644
index 000000000000..50b99a2c12ae
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -0,0 +1,37 @@
1/*
2 * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/include/ "socfpga_cyclone5.dtsi"
19
20/ {
21 model = "Terasic SoCkit";
22 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
23
24 chosen {
25 bootargs = "console=ttyS0,115200";
26 };
27
28 memory {
29 name = "memory";
30 device_type = "memory";
31 reg = <0x0 0x40000000>; /* 1GB */
32 };
33};
34
35&gmac1 {
36 status = "okay";
37};
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 1c1091eedade..7da99fe497e1 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/mfd/dbx500-prcmu.h>
13#include "skeleton.dtsi" 14#include "skeleton.dtsi"
14 15
15/ { 16/ {
@@ -42,16 +43,56 @@
42 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 43 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
43 }; 44 };
44 45
46
47 clocks {
48 compatible = "stericsson,u8500-clks";
49
50 prcmu_clk: prcmu-clock {
51 #clock-cells = <1>;
52 };
53
54 prcc_pclk: prcc-periph-clock {
55 #clock-cells = <2>;
56 };
57
58 prcc_kclk: prcc-kernel-clock {
59 #clock-cells = <2>;
60 };
61
62 rtc_clk: rtc32k-clock {
63 #clock-cells = <0>;
64 };
65
66 smp_twd_clk: smp-twd-clock {
67 #clock-cells = <0>;
68 };
69 };
70
71 mtu@a03c6000 {
72 /* Nomadik System Timer */
73 compatible = "st,nomadik-mtu";
74 reg = <0xa03c6000 0x1000>;
75 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
76
77 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
78 clock-names = "timclk", "apb_pclk";
79 };
80
45 timer@a0410600 { 81 timer@a0410600 {
46 compatible = "arm,cortex-a9-twd-timer"; 82 compatible = "arm,cortex-a9-twd-timer";
47 reg = <0xa0410600 0x20>; 83 reg = <0xa0410600 0x20>;
48 interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ 84 interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
85
86 clocks = <&smp_twd_clk>;
49 }; 87 };
50 88
51 rtc@80154000 { 89 rtc@80154000 {
52 compatible = "arm,rtc-pl031", "arm,primecell"; 90 compatible = "arm,rtc-pl031", "arm,primecell";
53 reg = <0x80154000 0x1000>; 91 reg = <0x80154000 0x1000>;
54 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 92 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
93
94 clocks = <&rtc_clk>;
95 clock-names = "apb_pclk";
55 }; 96 };
56 97
57 gpio0: gpio@8012e000 { 98 gpio0: gpio@8012e000 {
@@ -65,6 +106,8 @@
65 gpio-controller; 106 gpio-controller;
66 #gpio-cells = <2>; 107 #gpio-cells = <2>;
67 gpio-bank = <0>; 108 gpio-bank = <0>;
109
110 clocks = <&prcc_pclk 1 9>;
68 }; 111 };
69 112
70 gpio1: gpio@8012e080 { 113 gpio1: gpio@8012e080 {
@@ -78,6 +121,8 @@
78 gpio-controller; 121 gpio-controller;
79 #gpio-cells = <2>; 122 #gpio-cells = <2>;
80 gpio-bank = <1>; 123 gpio-bank = <1>;
124
125 clocks = <&prcc_pclk 1 9>;
81 }; 126 };
82 127
83 gpio2: gpio@8000e000 { 128 gpio2: gpio@8000e000 {
@@ -91,6 +136,8 @@
91 gpio-controller; 136 gpio-controller;
92 #gpio-cells = <2>; 137 #gpio-cells = <2>;
93 gpio-bank = <2>; 138 gpio-bank = <2>;
139
140 clocks = <&prcc_pclk 3 8>;
94 }; 141 };
95 142
96 gpio3: gpio@8000e080 { 143 gpio3: gpio@8000e080 {
@@ -104,6 +151,8 @@
104 gpio-controller; 151 gpio-controller;
105 #gpio-cells = <2>; 152 #gpio-cells = <2>;
106 gpio-bank = <3>; 153 gpio-bank = <3>;
154
155 clocks = <&prcc_pclk 3 8>;
107 }; 156 };
108 157
109 gpio4: gpio@8000e100 { 158 gpio4: gpio@8000e100 {
@@ -117,6 +166,8 @@
117 gpio-controller; 166 gpio-controller;
118 #gpio-cells = <2>; 167 #gpio-cells = <2>;
119 gpio-bank = <4>; 168 gpio-bank = <4>;
169
170 clocks = <&prcc_pclk 3 8>;
120 }; 171 };
121 172
122 gpio5: gpio@8000e180 { 173 gpio5: gpio@8000e180 {
@@ -130,6 +181,8 @@
130 gpio-controller; 181 gpio-controller;
131 #gpio-cells = <2>; 182 #gpio-cells = <2>;
132 gpio-bank = <5>; 183 gpio-bank = <5>;
184
185 clocks = <&prcc_pclk 3 8>;
133 }; 186 };
134 187
135 gpio6: gpio@8011e000 { 188 gpio6: gpio@8011e000 {
@@ -143,6 +196,8 @@
143 gpio-controller; 196 gpio-controller;
144 #gpio-cells = <2>; 197 #gpio-cells = <2>;
145 gpio-bank = <6>; 198 gpio-bank = <6>;
199
200 clocks = <&prcc_pclk 2 11>;
146 }; 201 };
147 202
148 gpio7: gpio@8011e080 { 203 gpio7: gpio@8011e080 {
@@ -156,6 +211,8 @@
156 gpio-controller; 211 gpio-controller;
157 #gpio-cells = <2>; 212 #gpio-cells = <2>;
158 gpio-bank = <7>; 213 gpio-bank = <7>;
214
215 clocks = <&prcc_pclk 2 11>;
159 }; 216 };
160 217
161 gpio8: gpio@a03fe000 { 218 gpio8: gpio@a03fe000 {
@@ -169,6 +226,8 @@
169 gpio-controller; 226 gpio-controller;
170 #gpio-cells = <2>; 227 #gpio-cells = <2>;
171 gpio-bank = <8>; 228 gpio-bank = <8>;
229
230 clocks = <&prcc_pclk 5 1>;
172 }; 231 };
173 232
174 pinctrl { 233 pinctrl {
@@ -177,8 +236,7 @@
177 }; 236 };
178 237
179 usb_per5@a03e0000 { 238 usb_per5@a03e0000 {
180 compatible = "stericsson,db8500-musb", 239 compatible = "stericsson,db8500-musb";
181 "mentor,musb";
182 reg = <0xa03e0000 0x10000>; 240 reg = <0xa03e0000 0x10000>;
183 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 241 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "mc"; 242 interrupt-names = "mc";
@@ -210,6 +268,8 @@
210 "iep_6_14", "oep_6_14", 268 "iep_6_14", "oep_6_14",
211 "iep_7_15", "oep_7_15", 269 "iep_7_15", "oep_7_15",
212 "iep_8", "oep_8"; 270 "iep_8", "oep_8";
271
272 clocks = <&prcc_pclk 5 0>;
213 }; 273 };
214 274
215 dma: dma-controller@801C0000 { 275 dma: dma-controller@801C0000 {
@@ -220,6 +280,8 @@
220 280
221 #dma-cells = <3>; 281 #dma-cells = <3>;
222 memcpy-channels = <56 57 58 59 60>; 282 memcpy-channels = <56 57 58 59 60>;
283
284 clocks = <&prcmu_clk PRCMU_DMACLK>;
223 }; 285 };
224 286
225 prcmu: prcmu@80157000 { 287 prcmu: prcmu@80157000 {
@@ -238,6 +300,13 @@
238 reg = <0x80157450 0xC>; 300 reg = <0x80157450 0xC>;
239 }; 301 };
240 302
303 cpufreq {
304 compatible = "stericsson,cpufreq-ux500";
305 clocks = <&prcmu_clk PRCMU_ARMSS>;
306 clock-names = "armss";
307 status = "disabled";
308 };
309
241 thermal@801573c0 { 310 thermal@801573c0 {
242 compatible = "stericsson,db8500-thermal"; 311 compatible = "stericsson,db8500-thermal";
243 reg = <0x801573c0 0x40>; 312 reg = <0x801573c0 0x40>;
@@ -559,65 +628,74 @@
559 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 628 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
560 reg = <0x80004000 0x1000>; 629 reg = <0x80004000 0x1000>;
561 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 630 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
562 arm,primecell-periphid = <0x180024>;
563 631
564 #address-cells = <1>; 632 #address-cells = <1>;
565 #size-cells = <0>; 633 #size-cells = <0>;
566 v-i2c-supply = <&db8500_vape_reg>; 634 v-i2c-supply = <&db8500_vape_reg>;
567 635
568 clock-frequency = <400000>; 636 clock-frequency = <400000>;
637 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
638 clock-names = "i2cclk", "apb_pclk";
569 }; 639 };
570 640
571 i2c@80122000 { 641 i2c@80122000 {
572 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 642 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
573 reg = <0x80122000 0x1000>; 643 reg = <0x80122000 0x1000>;
574 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 644 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
575 arm,primecell-periphid = <0x180024>;
576 645
577 #address-cells = <1>; 646 #address-cells = <1>;
578 #size-cells = <0>; 647 #size-cells = <0>;
579 v-i2c-supply = <&db8500_vape_reg>; 648 v-i2c-supply = <&db8500_vape_reg>;
580 649
581 clock-frequency = <400000>; 650 clock-frequency = <400000>;
651
652 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
653 clock-names = "i2cclk", "apb_pclk";
582 }; 654 };
583 655
584 i2c@80128000 { 656 i2c@80128000 {
585 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 657 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
586 reg = <0x80128000 0x1000>; 658 reg = <0x80128000 0x1000>;
587 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 659 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
588 arm,primecell-periphid = <0x180024>;
589 660
590 #address-cells = <1>; 661 #address-cells = <1>;
591 #size-cells = <0>; 662 #size-cells = <0>;
592 v-i2c-supply = <&db8500_vape_reg>; 663 v-i2c-supply = <&db8500_vape_reg>;
593 664
594 clock-frequency = <400000>; 665 clock-frequency = <400000>;
666
667 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
668 clock-names = "i2cclk", "apb_pclk";
595 }; 669 };
596 670
597 i2c@80110000 { 671 i2c@80110000 {
598 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 672 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
599 reg = <0x80110000 0x1000>; 673 reg = <0x80110000 0x1000>;
600 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; 674 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
601 arm,primecell-periphid = <0x180024>;
602 675
603 #address-cells = <1>; 676 #address-cells = <1>;
604 #size-cells = <0>; 677 #size-cells = <0>;
605 v-i2c-supply = <&db8500_vape_reg>; 678 v-i2c-supply = <&db8500_vape_reg>;
606 679
607 clock-frequency = <400000>; 680 clock-frequency = <400000>;
681
682 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
683 clock-names = "i2cclk", "apb_pclk";
608 }; 684 };
609 685
610 i2c@8012a000 { 686 i2c@8012a000 {
611 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 687 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
612 reg = <0x8012a000 0x1000>; 688 reg = <0x8012a000 0x1000>;
613 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 689 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
614 arm,primecell-periphid = <0x180024>;
615 690
616 #address-cells = <1>; 691 #address-cells = <1>;
617 #size-cells = <0>; 692 #size-cells = <0>;
618 v-i2c-supply = <&db8500_vape_reg>; 693 v-i2c-supply = <&db8500_vape_reg>;
619 694
620 clock-frequency = <400000>; 695 clock-frequency = <400000>;
696
697 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
698 clock-names = "i2cclk", "apb_pclk";
621 }; 699 };
622 700
623 ssp@80002000 { 701 ssp@80002000 {
@@ -626,7 +704,80 @@
626 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 704 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
627 #address-cells = <1>; 705 #address-cells = <1>;
628 #size-cells = <0>; 706 #size-cells = <0>;
629 status = "disabled"; 707 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
708 clock-names = "ssp0clk", "apb_pclk";
709 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
710 <&dma 8 0 0x0>; /* Logical - MemToDev */
711 dma-names = "rx", "tx";
712 };
713
714 ssp@80003000 {
715 compatible = "arm,pl022", "arm,primecell";
716 reg = <0x80003000 0x1000>;
717 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
721 clock-names = "ssp1clk", "apb_pclk";
722 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
723 <&dma 9 0 0x0>; /* Logical - MemToDev */
724 dma-names = "rx", "tx";
725 };
726
727 spi@8011a000 {
728 compatible = "arm,pl022", "arm,primecell";
729 reg = <0x8011a000 0x1000>;
730 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
731 #address-cells = <1>;
732 #size-cells = <0>;
733 /* Same clock wired to kernel and pclk */
734 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
735 clock-names = "spi0clk", "apb_pclk";
736 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
737 <&dma 0 0 0x0>; /* Logical - MemToDev */
738 dma-names = "rx", "tx";
739 };
740
741 spi@80112000 {
742 compatible = "arm,pl022", "arm,primecell";
743 reg = <0x80112000 0x1000>;
744 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
745 #address-cells = <1>;
746 #size-cells = <0>;
747 /* Same clock wired to kernel and pclk */
748 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
749 clock-names = "spi1clk", "apb_pclk";
750 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
751 <&dma 35 0 0x0>; /* Logical - MemToDev */
752 dma-names = "rx", "tx";
753 };
754
755 spi@80111000 {
756 compatible = "arm,pl022", "arm,primecell";
757 reg = <0x80111000 0x1000>;
758 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
759 #address-cells = <1>;
760 #size-cells = <0>;
761 /* Same clock wired to kernel and pclk */
762 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
763 clock-names = "spi2clk", "apb_pclk";
764 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
765 <&dma 33 0 0x0>; /* Logical - MemToDev */
766 dma-names = "rx", "tx";
767 };
768
769 spi@80129000 {
770 compatible = "arm,pl022", "arm,primecell";
771 reg = <0x80129000 0x1000>;
772 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>;
774 #size-cells = <0>;
775 /* Same clock wired to kernel and pclk */
776 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
777 clock-names = "spi3clk", "apb_pclk";
778 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
779 <&dma 40 0 0x0>; /* Logical - MemToDev */
780 dma-names = "rx", "tx";
630 }; 781 };
631 782
632 uart@80120000 { 783 uart@80120000 {
@@ -638,6 +789,9 @@
638 <&dma 13 0 0x0>; /* Logical - MemToDev */ 789 <&dma 13 0 0x0>; /* Logical - MemToDev */
639 dma-names = "rx", "tx"; 790 dma-names = "rx", "tx";
640 791
792 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
793 clock-names = "uart", "apb_pclk";
794
641 status = "disabled"; 795 status = "disabled";
642 }; 796 };
643 797
@@ -650,6 +804,9 @@
650 <&dma 12 0 0x0>; /* Logical - MemToDev */ 804 <&dma 12 0 0x0>; /* Logical - MemToDev */
651 dma-names = "rx", "tx"; 805 dma-names = "rx", "tx";
652 806
807 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
808 clock-names = "uart", "apb_pclk";
809
653 status = "disabled"; 810 status = "disabled";
654 }; 811 };
655 812
@@ -662,6 +819,9 @@
662 <&dma 11 0 0x0>; /* Logical - MemToDev */ 819 <&dma 11 0 0x0>; /* Logical - MemToDev */
663 dma-names = "rx", "tx"; 820 dma-names = "rx", "tx";
664 821
822 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
823 clock-names = "uart", "apb_pclk";
824
665 status = "disabled"; 825 status = "disabled";
666 }; 826 };
667 827
@@ -674,6 +834,9 @@
674 <&dma 29 0 0x0>; /* Logical - MemToDev */ 834 <&dma 29 0 0x0>; /* Logical - MemToDev */
675 dma-names = "rx", "tx"; 835 dma-names = "rx", "tx";
676 836
837 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
838 clock-names = "sdi", "apb_pclk";
839
677 status = "disabled"; 840 status = "disabled";
678 }; 841 };
679 842
@@ -686,6 +849,9 @@
686 <&dma 32 0 0x0>; /* Logical - MemToDev */ 849 <&dma 32 0 0x0>; /* Logical - MemToDev */
687 dma-names = "rx", "tx"; 850 dma-names = "rx", "tx";
688 851
852 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
853 clock-names = "sdi", "apb_pclk";
854
689 status = "disabled"; 855 status = "disabled";
690 }; 856 };
691 857
@@ -698,6 +864,9 @@
698 <&dma 28 0 0x0>; /* Logical - MemToDev */ 864 <&dma 28 0 0x0>; /* Logical - MemToDev */
699 dma-names = "rx", "tx"; 865 dma-names = "rx", "tx";
700 866
867 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
868 clock-names = "sdi", "apb_pclk";
869
701 status = "disabled"; 870 status = "disabled";
702 }; 871 };
703 872
@@ -705,6 +874,10 @@
705 compatible = "arm,pl18x", "arm,primecell"; 874 compatible = "arm,pl18x", "arm,primecell";
706 reg = <0x80119000 0x1000>; 875 reg = <0x80119000 0x1000>;
707 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; 876 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
877
878 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
879 clock-names = "sdi", "apb_pclk";
880
708 status = "disabled"; 881 status = "disabled";
709 }; 882 };
710 883
@@ -717,6 +890,9 @@
717 <&dma 42 0 0x0>; /* Logical - MemToDev */ 890 <&dma 42 0 0x0>; /* Logical - MemToDev */
718 dma-names = "rx", "tx"; 891 dma-names = "rx", "tx";
719 892
893 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
894 clock-names = "sdi", "apb_pclk";
895
720 status = "disabled"; 896 status = "disabled";
721 }; 897 };
722 898
@@ -724,6 +900,10 @@
724 compatible = "arm,pl18x", "arm,primecell"; 900 compatible = "arm,pl18x", "arm,primecell";
725 reg = <0x80008000 0x1000>; 901 reg = <0x80008000 0x1000>;
726 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 902 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
903
904 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
905 clock-names = "sdi", "apb_pclk";
906
727 status = "disabled"; 907 status = "disabled";
728 }; 908 };
729 909
@@ -732,6 +912,10 @@
732 reg = <0x80123000 0x1000>; 912 reg = <0x80123000 0x1000>;
733 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 913 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
734 v-ape-supply = <&db8500_vape_reg>; 914 v-ape-supply = <&db8500_vape_reg>;
915
916 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
917 clock-names = "msp", "apb_pclk";
918
735 status = "disabled"; 919 status = "disabled";
736 }; 920 };
737 921
@@ -740,6 +924,10 @@
740 reg = <0x80124000 0x1000>; 924 reg = <0x80124000 0x1000>;
741 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; 925 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
742 v-ape-supply = <&db8500_vape_reg>; 926 v-ape-supply = <&db8500_vape_reg>;
927
928 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
929 clock-names = "msp", "apb_pclk";
930
743 status = "disabled"; 931 status = "disabled";
744 }; 932 };
745 933
@@ -749,6 +937,10 @@
749 reg = <0x80117000 0x1000>; 937 reg = <0x80117000 0x1000>;
750 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 938 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
751 v-ape-supply = <&db8500_vape_reg>; 939 v-ape-supply = <&db8500_vape_reg>;
940
941 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
942 clock-names = "msp", "apb_pclk";
943
752 status = "disabled"; 944 status = "disabled";
753 }; 945 };
754 946
@@ -757,6 +949,10 @@
757 reg = <0x80125000 0x1000>; 949 reg = <0x80125000 0x1000>;
758 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; 950 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
759 v-ape-supply = <&db8500_vape_reg>; 951 v-ape-supply = <&db8500_vape_reg>;
952
953 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
954 clock-names = "msp", "apb_pclk";
955
760 status = "disabled"; 956 status = "disabled";
761 }; 957 };
762 958
@@ -772,7 +968,7 @@
772 cpufreq-cooling { 968 cpufreq-cooling {
773 compatible = "stericsson,db8500-cpufreq-cooling"; 969 compatible = "stericsson,db8500-cpufreq-cooling";
774 status = "disabled"; 970 status = "disabled";
775 }; 971 };
776 972
777 vmmci: regulator-gpio { 973 vmmci: regulator-gpio {
778 compatible = "regulator-gpio"; 974 compatible = "regulator-gpio";
@@ -797,6 +993,7 @@
797 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 993 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
798 994
799 v-ape-supply = <&db8500_vape_reg>; 995 v-ape-supply = <&db8500_vape_reg>;
996 clocks = <&prcc_pclk 6 1>;
800 }; 997 };
801 998
802 hash@a03c2000 { 999 hash@a03c2000 {
@@ -804,6 +1001,7 @@
804 reg = <0xa03c2000 0x1000>; 1001 reg = <0xa03c2000 0x1000>;
805 1002
806 v-ape-supply = <&db8500_vape_reg>; 1003 v-ape-supply = <&db8500_vape_reg>;
1004 clocks = <&prcc_pclk 6 2>;
807 }; 1005 };
808 }; 1006 };
809}; 1007};
diff --git a/arch/arm/boot/dts/ste-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi
index 524e33240ad4..76704ec0ffcc 100644
--- a/arch/arm/boot/dts/ste-stuib.dtsi
+++ b/arch/arm/boot/dts/ste-href-stuib.dtsi
@@ -57,7 +57,6 @@
57 bu21013_tp@5c { 57 bu21013_tp@5c {
58 compatible = "rohm,bu21013_tp"; 58 compatible = "rohm,bu21013_tp";
59 reg = <0x5c>; 59 reg = <0x5c>;
60 touch-gpio = <&gpio2 20 0x4>;
61 avdd-supply = <&ab8500_ldo_aux1_reg>; 60 avdd-supply = <&ab8500_ldo_aux1_reg>;
62 61
63 rohm,touch-max-x = <384>; 62 rohm,touch-max-x = <384>;
@@ -68,7 +67,6 @@
68 bu21013_tp@5d { 67 bu21013_tp@5d {
69 compatible = "rohm,bu21013_tp"; 68 compatible = "rohm,bu21013_tp";
70 reg = <0x5d>; 69 reg = <0x5d>;
71 touch-gpio = <&gpio2 20 0x4>;
72 avdd-supply = <&ab8500_ldo_aux1_reg>; 70 avdd-supply = <&ab8500_ldo_aux1_reg>;
73 71
74 rohm,touch-max-x = <384>; 72 rohm,touch-max-x = <384>;
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
new file mode 100644
index 000000000000..76d3ef13175f
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Device Tree for the TVK1281618 UIB
12 */
13
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 soc {
18 /* Add Synaptics touch screen, TC35892 keypad etc here */
19 i2c@80004000 {
20 tc3589x@44 {
21 compatible = "tc3589x";
22 reg = <0x44>;
23 interrupt-parent = <&gpio6>;
24 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
25
26 interrupt-controller;
27 #interrupt-cells = <2>;
28
29 tc3589x_gpio {
30 compatible = "tc3589x-gpio";
31 interrupts = <0 IRQ_TYPE_EDGE_RISING>;
32
33 interrupt-controller;
34 #interrupt-cells = <2>;
35 gpio-controller;
36 #gpio-cells = <2>;
37 };
38 };
39 };
40 };
41};
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 370e03f5e7b2..aa3f02060fdd 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -41,28 +41,6 @@
41 status = "okay"; 41 status = "okay";
42 }; 42 };
43 43
44 i2c@80004000 {
45 tc3589x@42 {
46 compatible = "tc3589x";
47 reg = <0x42>;
48 interrupt-parent = <&gpio6>;
49 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
50
51 interrupt-controller;
52 #interrupt-cells = <2>;
53
54 tc3589x_gpio: tc3589x_gpio {
55 compatible = "tc3589x-gpio";
56 interrupts = <0 IRQ_TYPE_EDGE_RISING>;
57
58 interrupt-controller;
59 #interrupt-cells = <2>;
60 gpio-controller;
61 #gpio-cells = <2>;
62 };
63 };
64 };
65
66 i2c@80128000 { 44 i2c@80128000 {
67 lp5521@33 { 45 lp5521@33 {
68 compatible = "national,lp5521"; 46 compatible = "national,lp5521";
@@ -72,6 +50,7 @@
72 chan0 { 50 chan0 {
73 led-cur = /bits/ 8 <0x2f>; 51 led-cur = /bits/ 8 <0x2f>;
74 max-cur = /bits/ 8 <0x5f>; 52 max-cur = /bits/ 8 <0x5f>;
53 linux,default-trigger = "heartbeat";
75 }; 54 };
76 chan1 { 55 chan1 {
77 led-cur = /bits/ 8 <0x2f>; 56 led-cur = /bits/ 8 <0x2f>;
@@ -102,7 +81,7 @@
102 }; 81 };
103 bh1780@29 { 82 bh1780@29 {
104 compatible = "rohm,bh1780gli"; 83 compatible = "rohm,bh1780gli";
105 reg = <0x33>; 84 reg = <0x29>;
106 }; 85 };
107 }; 86 };
108 87
@@ -167,89 +146,11 @@
167 }; 146 };
168 147
169 prcmu@80157000 { 148 prcmu@80157000 {
170 db8500-prcmu-regulators { 149 ab8500 {
171 db8500_vape_reg: db8500_vape { 150 ab8500-gpio {
172 regulator-name = "db8500-vape"; 151 compatible = "stericsson,ab8500-gpio";
173 };
174
175 db8500_varm_reg: db8500_varm {
176 regulator-name = "db8500-varm";
177 };
178
179 db8500_vmodem_reg: db8500_vmodem {
180 regulator-name = "db8500-vmodem";
181 };
182
183 db8500_vpll_reg: db8500_vpll {
184 regulator-name = "db8500-vpll";
185 };
186
187 db8500_vsmps1_reg: db8500_vsmps1 {
188 regulator-name = "db8500-vsmps1";
189 };
190
191 db8500_vsmps2_reg: db8500_vsmps2 {
192 regulator-name = "db8500-vsmps2";
193 };
194
195 db8500_vsmps3_reg: db8500_vsmps3 {
196 regulator-name = "db8500-vsmps3";
197 };
198
199 db8500_vrf1_reg: db8500_vrf1 {
200 regulator-name = "db8500-vrf1";
201 };
202
203 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
204 regulator-name = "db8500-sva-mmdsp";
205 };
206
207 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
208 regulator-name = "db8500-sva-mmdsp-ret";
209 };
210
211 db8500_sva_pipe_reg: db8500_sva_pipe {
212 regulator-name = "db8500_sva_pipe";
213 };
214
215 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
216 regulator-name = "db8500_sia_mmdsp";
217 };
218
219 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
220 regulator-name = "db8500-sia-mmdsp-ret";
221 };
222
223 db8500_sia_pipe_reg: db8500_sia_pipe {
224 regulator-name = "db8500-sia-pipe";
225 };
226
227 db8500_sga_reg: db8500_sga {
228 regulator-name = "db8500-sga";
229 };
230
231 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
232 regulator-name = "db8500-b2r2-mcde";
233 };
234
235 db8500_esram12_reg: db8500_esram12 {
236 regulator-name = "db8500-esram12";
237 };
238
239 db8500_esram12_ret_reg: db8500_esram12_ret {
240 regulator-name = "db8500-esram12-ret";
241 };
242
243 db8500_esram34_reg: db8500_esram34 {
244 regulator-name = "db8500-esram34";
245 }; 152 };
246 153
247 db8500_esram34_ret_reg: db8500_esram34_ret {
248 regulator-name = "db8500-esram34-ret";
249 };
250 };
251
252 ab8500 {
253 ab8500-regulators { 154 ab8500-regulators {
254 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { 155 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
255 regulator-name = "V-DISPLAY"; 156 regulator-name = "V-DISPLAY";
diff --git a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts
new file mode 100644
index 000000000000..2b1cb5b584b6
--- /dev/null
+++ b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "ste-hrefprev60.dtsi"
14#include "ste-href-stuib.dtsi"
15
16/ {
17 model = "ST-Ericsson HREF (pre-v60) and ST UIB";
18 compatible = "st-ericsson,mop500", "st-ericsson,u8500";
19
20 soc {
21 /* Reset line for the BU21013 touchscreen */
22 i2c@80110000 {
23 /* Only one of these will be used */
24 bu21013_tp@5c {
25 touch-gpio = <&gpio2 12 0x4>;
26 reset-gpio = <&tc3589x_gpio 13 0x4>;
27 };
28 bu21013_tp@5d {
29 touch-gpio = <&gpio2 12 0x4>;
30 reset-gpio = <&tc3589x_gpio 13 0x4>;
31 };
32 };
33 };
34};
diff --git a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts
new file mode 100644
index 000000000000..59523f866812
--- /dev/null
+++ b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts
@@ -0,0 +1,19 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "ste-hrefprev60.dtsi"
14#include "ste-href-tvk1281618.dtsi"
15
16/ {
17 model = "ST-Ericsson HREF (pre-v60) and TVK1281618 UIB";
18 compatible = "st-ericsson,mop500", "st-ericsson,u8500";
19};
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dts b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index d8d3b99ab007..b2cd7bc2752f 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dts
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -7,17 +7,14 @@
7 * 7 *
8 * http://www.opensource.org/licenses/gpl-license.html 8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Device Tree for the HREF+ prior to the v60 variant.
10 */ 12 */
11 13
12/dts-v1/;
13#include "ste-dbx5x0.dtsi" 14#include "ste-dbx5x0.dtsi"
14#include "ste-href.dtsi" 15#include "ste-href.dtsi"
15#include "ste-stuib.dtsi"
16 16
17/ { 17/ {
18 model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
19 compatible = "st-ericsson,mop500", "st-ericsson,u8500";
20
21 gpio_keys { 18 gpio_keys {
22 button@1 { 19 button@1 {
23 gpios = <&tc3589x_gpio 7 0x4>; 20 gpios = <&tc3589x_gpio 7 0x4>;
@@ -25,24 +22,30 @@
25 }; 22 };
26 23
27 soc { 24 soc {
28 prcmu@80157000 {
29 ab8500@5 {
30 ab8500-gpio {
31 compatible = "stericsson,ab8500-gpio";
32 };
33 };
34 };
35
36 i2c@80004000 { 25 i2c@80004000 {
37 tps61052@33 { 26 tps61052@33 {
38 compatible = "tps61052"; 27 compatible = "tps61052";
39 reg = <0x33>; 28 reg = <0x33>;
40 }; 29 };
41 };
42 30
43 i2c@80110000 { 31 tc3589x@42 {
44 bu21013_tp@5c { 32 compatible = "tc3589x";
45 reset-gpio = <&tc3589x_gpio 13 0x4>; 33 reg = <0x42>;
34 interrupt-parent = <&gpio6>;
35 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
36
37 interrupt-controller;
38 #interrupt-cells = <2>;
39
40 tc3589x_gpio: tc3589x_gpio {
41 compatible = "tc3589x-gpio";
42 interrupts = <0 IRQ_TYPE_EDGE_RISING>;
43
44 interrupt-controller;
45 #interrupt-cells = <2>;
46 gpio-controller;
47 #gpio-cells = <2>;
48 };
46 }; 49 };
47 }; 50 };
48 51
diff --git a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts
new file mode 100644
index 000000000000..8c6a2de56cf1
--- /dev/null
+++ b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts
@@ -0,0 +1,36 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Device Tree for the HREF version 60 or later with the ST UIB
12 */
13
14/dts-v1/;
15#include "ste-hrefv60plus.dtsi"
16#include "ste-href-stuib.dtsi"
17
18/ {
19 model = "ST-Ericsson HREF (v60+) and ST UIB";
20 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
21
22 soc {
23 /* Reset line for the BU21013 touchscreen */
24 i2c@80110000 {
25 /* Only one of these will be used */
26 bu21013_tp@5c {
27 touch-gpio = <&gpio2 20 0x4>;
28 reset-gpio = <&gpio4 17 0x4>;
29 };
30 bu21013_tp@5d {
31 touch-gpio = <&gpio2 20 0x4>;
32 reset-gpio = <&gpio4 17 0x4>;
33 };
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts
new file mode 100644
index 000000000000..d53cccdce776
--- /dev/null
+++ b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts
@@ -0,0 +1,21 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Device Tree for the HREF version 60 or later with the TVK1281618 UIB
12 */
13
14/dts-v1/;
15#include "ste-hrefv60plus.dtsi"
16#include "ste-href-tvk1281618.dtsi"
17
18/ {
19 model = "ST-Ericsson HREF (v60+) and TVK1281618 UIB";
20 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
21};
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts
deleted file mode 100644
index 6e52ebbf113f..000000000000
--- a/arch/arm/boot/dts/ste-hrefv60plus.dts
+++ /dev/null
@@ -1,210 +0,0 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "ste-dbx5x0.dtsi"
14#include "ste-href.dtsi"
15#include "ste-stuib.dtsi"
16
17/ {
18 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
19 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
20
21 gpio_keys {
22 button@1 {
23 gpios = <&gpio6 25 0x4>;
24 };
25 };
26
27 soc {
28 i2c@80110000 {
29 bu21013_tp@0x5c {
30 reset-gpio = <&gpio4 15 0x4>;
31 };
32 };
33
34 // External Micro SD slot
35 sdi0_per1@80126000 {
36 arm,primecell-periphid = <0x10480180>;
37 max-frequency = <100000000>;
38 bus-width = <4>;
39 mmc-cap-sd-highspeed;
40 mmc-cap-mmc-highspeed;
41 vmmc-supply = <&ab8500_ldo_aux3_reg>;
42
43 cd-gpios = <&tc3589x_gpio 3 0x4>;
44
45 status = "okay";
46 };
47
48 // WLAN SDIO channel
49 sdi1_per2@80118000 {
50 arm,primecell-periphid = <0x10480180>;
51 max-frequency = <100000000>;
52 bus-width = <4>;
53
54 status = "okay";
55 };
56
57 // PoP:ed eMMC
58 sdi2_per3@80005000 {
59 arm,primecell-periphid = <0x10480180>;
60 max-frequency = <100000000>;
61 bus-width = <8>;
62 mmc-cap-mmc-highspeed;
63
64 status = "okay";
65 };
66
67 // On-board eMMC
68 sdi4_per2@80114000 {
69 arm,primecell-periphid = <0x10480180>;
70 max-frequency = <100000000>;
71 bus-width = <8>;
72 mmc-cap-mmc-highspeed;
73 vmmc-supply = <&ab8500_ldo_aux2_reg>;
74
75 status = "okay";
76 };
77
78 prcmu@80157000 {
79 db8500-prcmu-regulators {
80 db8500_vape_reg: db8500_vape {
81 regulator-name = "db8500-vape";
82 };
83
84 db8500_varm_reg: db8500_varm {
85 regulator-name = "db8500-varm";
86 };
87
88 db8500_vmodem_reg: db8500_vmodem {
89 regulator-name = "db8500-vmodem";
90 };
91
92 db8500_vpll_reg: db8500_vpll {
93 regulator-name = "db8500-vpll";
94 };
95
96 db8500_vsmps1_reg: db8500_vsmps1 {
97 regulator-name = "db8500-vsmps1";
98 };
99
100 db8500_vsmps2_reg: db8500_vsmps2 {
101 regulator-name = "db8500-vsmps2";
102 };
103
104 db8500_vsmps3_reg: db8500_vsmps3 {
105 regulator-name = "db8500-vsmps3";
106 };
107
108 db8500_vrf1_reg: db8500_vrf1 {
109 regulator-name = "db8500-vrf1";
110 };
111
112 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
113 regulator-name = "db8500-sva-mmdsp";
114 };
115
116 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
117 regulator-name = "db8500-sva-mmdsp-ret";
118 };
119
120 db8500_sva_pipe_reg: db8500_sva_pipe {
121 regulator-name = "db8500_sva_pipe";
122 };
123
124 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
125 regulator-name = "db8500_sia_mmdsp";
126 };
127
128 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
129 regulator-name = "db8500-sia-mmdsp-ret";
130 };
131
132 db8500_sia_pipe_reg: db8500_sia_pipe {
133 regulator-name = "db8500-sia-pipe";
134 };
135
136 db8500_sga_reg: db8500_sga {
137 regulator-name = "db8500-sga";
138 };
139
140 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
141 regulator-name = "db8500-b2r2-mcde";
142 };
143
144 db8500_esram12_reg: db8500_esram12 {
145 regulator-name = "db8500-esram12";
146 };
147
148 db8500_esram12_ret_reg: db8500_esram12_ret {
149 regulator-name = "db8500-esram12-ret";
150 };
151
152 db8500_esram34_reg: db8500_esram34 {
153 regulator-name = "db8500-esram34";
154 };
155
156 db8500_esram34_ret_reg: db8500_esram34_ret {
157 regulator-name = "db8500-esram34-ret";
158 };
159 };
160
161 ab8500 {
162 ab8500-regulators {
163 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
164 regulator-name = "V-DISPLAY";
165 };
166
167 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
168 regulator-name = "V-eMMC1";
169 };
170
171 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
172 regulator-name = "V-MMC-SD";
173 };
174
175 ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
176 regulator-name = "V-INTCORE";
177 };
178
179 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
180 regulator-name = "V-TVOUT";
181 };
182
183 ab8500_ldo_usb_reg: ab8500_ldo_usb {
184 regulator-name = "dummy";
185 };
186
187 ab8500_ldo_audio_reg: ab8500_ldo_audio {
188 regulator-name = "V-AUD";
189 };
190
191 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
192 regulator-name = "V-AMIC1";
193 };
194
195 ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
196 regulator-name = "V-AMIC2";
197 };
198
199 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
200 regulator-name = "V-DMIC";
201 };
202
203 ab8500_ldo_ana_reg: ab8500_ldo_ana {
204 regulator-name = "V-CSI/DSI";
205 };
206 };
207 };
208 };
209 };
210};
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
new file mode 100644
index 000000000000..aed511b47a9e
--- /dev/null
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -0,0 +1,70 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "ste-dbx5x0.dtsi"
13#include "ste-href.dtsi"
14
15/ {
16 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
17 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
18
19 gpio_keys {
20 button@1 {
21 gpios = <&gpio5 25 0x4>;
22 };
23 };
24
25 soc {
26 // External Micro SD slot
27 sdi0_per1@80126000 {
28 arm,primecell-periphid = <0x10480180>;
29 max-frequency = <100000000>;
30 bus-width = <4>;
31 mmc-cap-sd-highspeed;
32 mmc-cap-mmc-highspeed;
33 vmmc-supply = <&ab8500_ldo_aux3_reg>;
34
35 cd-gpios = <&gpio2 31 0x4>; // 95
36
37 status = "okay";
38 };
39
40 // WLAN SDIO channel
41 sdi1_per2@80118000 {
42 arm,primecell-periphid = <0x10480180>;
43 max-frequency = <100000000>;
44 bus-width = <4>;
45
46 status = "okay";
47 };
48
49 // PoP:ed eMMC
50 sdi2_per3@80005000 {
51 arm,primecell-periphid = <0x10480180>;
52 max-frequency = <100000000>;
53 bus-width = <8>;
54 mmc-cap-mmc-highspeed;
55
56 status = "okay";
57 };
58
59 // On-board eMMC
60 sdi4_per2@80114000 {
61 arm,primecell-periphid = <0x10480180>;
62 max-frequency = <100000000>;
63 bus-width = <8>;
64 mmc-cap-mmc-highspeed;
65 vmmc-supply = <&ab8500_ldo_aux2_reg>;
66
67 status = "okay";
68 };
69 };
70};
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index f1fc128e249d..f0b39f835914 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -111,12 +111,13 @@
111 vdd33a-supply = <&en_3v3_reg>; 111 vdd33a-supply = <&en_3v3_reg>;
112 vddvario-supply = <&db8500_vape_reg>; 112 vddvario-supply = <&db8500_vape_reg>;
113 113
114
115 reg-shift = <1>; 114 reg-shift = <1>;
116 reg-io-width = <2>; 115 reg-io-width = <2>;
117 smsc,force-internal-phy; 116 smsc,force-internal-phy;
118 smsc,irq-active-high; 117 smsc,irq-active-high;
119 smsc,irq-push-pull; 118 smsc,irq-push-pull;
119
120 clocks = <&prcc_pclk 3 0>;
120 }; 121 };
121 }; 122 };
122 123
@@ -170,86 +171,8 @@
170 }; 171 };
171 172
172 prcmu@80157000 { 173 prcmu@80157000 {
173 db8500-prcmu-regulators { 174 cpufreq {
174 db8500_vape_reg: db8500_vape { 175 status = "okay";
175 regulator-name = "db8500-vape";
176 };
177
178 db8500_varm_reg: db8500_varm {
179 regulator-name = "db8500-varm";
180 };
181
182 db8500_vmodem_reg: db8500_vmodem {
183 regulator-name = "db8500-vmodem";
184 };
185
186 db8500_vpll_reg: db8500_vpll {
187 regulator-name = "db8500-vpll";
188 };
189
190 db8500_vsmps1_reg: db8500_vsmps1 {
191 regulator-name = "db8500-vsmps1";
192 };
193
194 db8500_vsmps2_reg: db8500_vsmps2 {
195 regulator-name = "db8500-vsmps2";
196 };
197
198 db8500_vsmps3_reg: db8500_vsmps3 {
199 regulator-name = "db8500-vsmps3";
200 };
201
202 db8500_vrf1_reg: db8500_vrf1 {
203 regulator-name = "db8500-vrf1";
204 };
205
206 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
207 regulator-name = "db8500-sva-mmdsp";
208 };
209
210 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
211 regulator-name = "db8500-sva-mmdsp-ret";
212 };
213
214 db8500_sva_pipe_reg: db8500_sva_pipe {
215 regulator-name = "db8500_sva_pipe";
216 };
217
218 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
219 regulator-name = "db8500_sia_mmdsp";
220 };
221
222 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
223 regulator-name = "db8500-sia-mmdsp-ret";
224 };
225
226 db8500_sia_pipe_reg: db8500_sia_pipe {
227 regulator-name = "db8500-sia-pipe";
228 };
229
230 db8500_sga_reg: db8500_sga {
231 regulator-name = "db8500-sga";
232 };
233
234 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
235 regulator-name = "db8500-b2r2-mcde";
236 };
237
238 db8500_esram12_reg: db8500_esram12 {
239 regulator-name = "db8500-esram12";
240 };
241
242 db8500_esram12_ret_reg: db8500_esram12_ret {
243 regulator-name = "db8500-esram12-ret";
244 };
245
246 db8500_esram34_reg: db8500_esram34 {
247 regulator-name = "db8500-esram34";
248 };
249
250 db8500_esram34_ret_reg: db8500_esram34_ret {
251 regulator-name = "db8500-esram34-ret";
252 };
253 }; 176 };
254 177
255 thermal@801573c0 { 178 thermal@801573c0 {
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index c32770a28acf..319cc6b509da 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -266,6 +266,11 @@
266 reg = <0x01c20c90 0x10>; 266 reg = <0x01c20c90 0x10>;
267 }; 267 };
268 268
269 sid: eeprom@01c23800 {
270 compatible = "allwinner,sun4i-sid";
271 reg = <0x01c23800 0x10>;
272 };
273
269 uart0: serial@01c28000 { 274 uart0: serial@01c28000 {
270 compatible = "snps,dw-apb-uart"; 275 compatible = "snps,dw-apb-uart";
271 reg = <0x01c28000 0x400>; 276 reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 3b4a0574f068..52476742a104 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -255,6 +255,11 @@
255 reg = <0x01c20c90 0x10>; 255 reg = <0x01c20c90 0x10>;
256 }; 256 };
257 257
258 sid: eeprom@01c23800 {
259 compatible = "allwinner,sun4i-sid";
260 reg = <0x01c23800 0x10>;
261 };
262
258 uart0: serial@01c28000 { 263 uart0: serial@01c28000 {
259 compatible = "snps,dw-apb-uart"; 264 compatible = "snps,dw-apb-uart";
260 reg = <0x01c28000 0x400>; 265 reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index f6091dc0936c..ce8ef2a45be0 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -222,6 +222,11 @@
222 reg = <0x01c20c90 0x10>; 222 reg = <0x01c20c90 0x10>;
223 }; 223 };
224 224
225 sid: eeprom@01c23800 {
226 compatible = "allwinner,sun4i-sid";
227 reg = <0x01c23800 0x10>;
228 };
229
225 uart1: serial@01c28400 { 230 uart1: serial@01c28400 {
226 compatible = "snps,dw-apb-uart"; 231 compatible = "snps,dw-apb-uart";
227 reg = <0x01c28400 0x400>; 232 reg = <0x01c28400 0x400>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index f244f5f02365..c1751a64889a 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -175,7 +175,7 @@
175 apb2_gates: apb2_gates@01c2006c { 175 apb2_gates: apb2_gates@01c2006c {
176 #clock-cells = <1>; 176 #clock-cells = <1>;
177 compatible = "allwinner,sun6i-a31-apb2-gates-clk"; 177 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
178 reg = <0x01c2006c 0x8>; 178 reg = <0x01c2006c 0x4>;
179 clocks = <&apb2>; 179 clocks = <&apb2>;
180 clock-output-names = "apb2_i2c0", "apb2_i2c1", 180 clock-output-names = "apb2_i2c0", "apb2_i2c1",
181 "apb2_i2c2", "apb2_i2c3", "apb2_uart0", 181 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 15e625eca312..5c51cb8a98b0 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -48,6 +48,18 @@
48 pinctrl-0 = <&uart0_pins_a>; 48 pinctrl-0 = <&uart0_pins_a>;
49 status = "okay"; 49 status = "okay";
50 }; 50 };
51
52 i2c0: i2c@01c2ac00 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&i2c0_pins_a>;
55 status = "okay";
56 };
57
58 i2c1: i2c@01c2b000 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c1_pins_a>;
61 status = "okay";
62 };
51 }; 63 };
52 64
53 leds { 65 leds {
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
new file mode 100644
index 000000000000..8a1009d6c829
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2013 Oliver Schinagl
3 *
4 * Oliver Schinagl <oliver@schinagl.nl>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun7i-a20.dtsi"
16
17/ {
18 model = "Cubietech Cubietruck";
19 compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
20
21 soc@01c00000 {
22 pinctrl@01c20800 {
23 led_pins_cubietruck: led_pins@0 {
24 allwinner,pins = "PH7", "PH11", "PH20", "PH21";
25 allwinner,function = "gpio_out";
26 allwinner,drive = <0>;
27 allwinner,pull = <0>;
28 };
29 };
30
31 uart0: serial@01c28000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&uart0_pins_a>;
34 status = "okay";
35 };
36 };
37
38 leds {
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&led_pins_cubietruck>;
42
43 blue {
44 label = "cubietruck:blue:usr";
45 gpios = <&pio 7 21 0>;
46 };
47
48 orange {
49 label = "cubietruck:orange:usr";
50 gpios = <&pio 7 20 0>;
51 };
52
53 white {
54 label = "cubietruck:white:usr";
55 gpios = <&pio 7 11 0>;
56 };
57
58 green {
59 label = "cubietruck:green:usr";
60 gpios = <&pio 7 7 0>;
61 };
62 };
63};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index 9e778557fadb..ead3013f9aca 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -60,6 +60,24 @@
60 pinctrl-0 = <&uart7_pins_a>; 60 pinctrl-0 = <&uart7_pins_a>;
61 status = "okay"; 61 status = "okay";
62 }; 62 };
63
64 i2c0: i2c@01c2ac00 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&i2c0_pins_a>;
67 status = "okay";
68 };
69
70 i2c1: i2c@01c2b000 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&i2c1_pins_a>;
73 status = "okay";
74 };
75
76 i2c2: i2c@01c2b400 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&i2c2_pins_a>;
79 status = "okay";
80 };
63 }; 81 };
64 82
65 leds { 83 leds {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 80559cbdbc87..e46cfedde74c 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -215,6 +215,27 @@
215 allwinner,pull = <0>; 215 allwinner,pull = <0>;
216 }; 216 };
217 217
218 i2c0_pins_a: i2c0@0 {
219 allwinner,pins = "PB0", "PB1";
220 allwinner,function = "i2c0";
221 allwinner,drive = <0>;
222 allwinner,pull = <0>;
223 };
224
225 i2c1_pins_a: i2c1@0 {
226 allwinner,pins = "PB18", "PB19";
227 allwinner,function = "i2c1";
228 allwinner,drive = <0>;
229 allwinner,pull = <0>;
230 };
231
232 i2c2_pins_a: i2c2@0 {
233 allwinner,pins = "PB20", "PB21";
234 allwinner,function = "i2c2";
235 allwinner,drive = <0>;
236 allwinner,pull = <0>;
237 };
238
218 emac_pins_a: emac0@0 { 239 emac_pins_a: emac0@0 {
219 allwinner,pins = "PA0", "PA1", "PA2", 240 allwinner,pins = "PA0", "PA1", "PA2",
220 "PA3", "PA4", "PA5", "PA6", 241 "PA3", "PA4", "PA5", "PA6",
@@ -244,6 +265,11 @@
244 reg = <0x01c20c90 0x10>; 265 reg = <0x01c20c90 0x10>;
245 }; 266 };
246 267
268 sid: eeprom@01c23800 {
269 compatible = "allwinner,sun7i-a20-sid";
270 reg = <0x01c23800 0x200>;
271 };
272
247 uart0: serial@01c28000 { 273 uart0: serial@01c28000 {
248 compatible = "snps,dw-apb-uart"; 274 compatible = "snps,dw-apb-uart";
249 reg = <0x01c28000 0x400>; 275 reg = <0x01c28000 0x400>;
@@ -324,6 +350,51 @@
324 status = "disabled"; 350 status = "disabled";
325 }; 351 };
326 352
353 i2c0: i2c@01c2ac00 {
354 compatible = "allwinner,sun4i-i2c";
355 reg = <0x01c2ac00 0x400>;
356 interrupts = <0 7 1>;
357 clocks = <&apb1_gates 0>;
358 clock-frequency = <100000>;
359 status = "disabled";
360 };
361
362 i2c1: i2c@01c2b000 {
363 compatible = "allwinner,sun4i-i2c";
364 reg = <0x01c2b000 0x400>;
365 interrupts = <0 8 1>;
366 clocks = <&apb1_gates 1>;
367 clock-frequency = <100000>;
368 status = "disabled";
369 };
370
371 i2c2: i2c@01c2b400 {
372 compatible = "allwinner,sun4i-i2c";
373 reg = <0x01c2b400 0x400>;
374 interrupts = <0 9 1>;
375 clocks = <&apb1_gates 2>;
376 clock-frequency = <100000>;
377 status = "disabled";
378 };
379
380 i2c3: i2c@01c2b800 {
381 compatible = "allwinner,sun4i-i2c";
382 reg = <0x01c2b800 0x400>;
383 interrupts = <0 88 1>;
384 clocks = <&apb1_gates 3>;
385 clock-frequency = <100000>;
386 status = "disabled";
387 };
388
389 i2c4: i2c@01c2bc00 {
390 compatible = "allwinner,sun4i-i2c";
391 reg = <0x01c2bc00 0x400>;
392 interrupts = <0 89 1>;
393 clocks = <&apb1_gates 15>;
394 clock-frequency = <100000>;
395 status = "disabled";
396 };
397
327 gic: interrupt-controller@01c81000 { 398 gic: interrupt-controller@01c81000 {
328 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 399 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
329 reg = <0x01c81000 0x1000>, 400 reg = <0x01c81000 0x1000>,
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 60230288884b..cb5ec23b03a7 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,5 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra114.dtsi" 4#include "tegra114.dtsi"
4 5
5/ { 6/ {
@@ -738,6 +739,14 @@
738 realtek,ldo1-en-gpios = 739 realtek,ldo1-en-gpios =
739 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 740 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
740 }; 741 };
742
743 temperature-sensor@4c {
744 compatible = "onnn,nct1008";
745 reg = <0x4c>;
746 vcc-supply = <&palmas_ldo6_reg>;
747 interrupt-parent = <&gpio>;
748 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
749 };
741 }; 750 };
742 751
743 i2c@7000d000 { 752 i2c@7000d000 {
@@ -947,7 +956,7 @@
947 regulator-max-microvolt = <1800000>; 956 regulator-max-microvolt = <1800000>;
948 }; 957 };
949 958
950 ldo6 { 959 palmas_ldo6_reg: ldo6 {
951 regulator-name = "vdd-sensor-2v85"; 960 regulator-name = "vdd-sensor-2v85";
952 regulator-min-microvolt = <2850000>; 961 regulator-min-microvolt = <2850000>;
953 regulator-max-microvolt = <2850000>; 962 regulator-max-microvolt = <2850000>;
@@ -1011,6 +1020,19 @@
1011 interrupt-parent = <&palmas>; 1020 interrupt-parent = <&palmas>;
1012 interrupts = <8 0>; 1021 interrupts = <8 0>;
1013 }; 1022 };
1023
1024 pinmux {
1025 compatible = "ti,tps65913-pinctrl";
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&palmas_default>;
1028
1029 palmas_default: pinmux {
1030 pin_gpio6 {
1031 pins = "gpio6";
1032 function = "gpio";
1033 };
1034 };
1035 };
1014 }; 1036 };
1015 }; 1037 };
1016 1038
@@ -1081,26 +1103,26 @@
1081 home { 1103 home {
1082 label = "Home"; 1104 label = "Home";
1083 gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 1105 gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1084 linux,code = <102>; /* KEY_HOME */ 1106 linux,code = <KEY_HOME>;
1085 }; 1107 };
1086 1108
1087 power { 1109 power {
1088 label = "Power"; 1110 label = "Power";
1089 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1111 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1090 linux,code = <116>; /* KEY_POWER */ 1112 linux,code = <KEY_POWER>;
1091 gpio-key,wakeup; 1113 gpio-key,wakeup;
1092 }; 1114 };
1093 1115
1094 volume_down { 1116 volume_down {
1095 label = "Volume Down"; 1117 label = "Volume Down";
1096 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; 1118 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
1097 linux,code = <114>; /* KEY_VOLUMEDOWN */ 1119 linux,code = <KEY_VOLUMEDOWN>;
1098 }; 1120 };
1099 1121
1100 volume_up { 1122 volume_up {
1101 label = "Volume Up"; 1123 label = "Volume Up";
1102 gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; 1124 gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
1103 linux,code = <115>; /* KEY_VOLUMEUP */ 1125 linux,code = <KEY_VOLUMEUP>;
1104 }; 1126 };
1105 }; 1127 };
1106 1128
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 2905145d8e59..8d42787c8ff1 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -318,9 +318,9 @@
318 318
319 iommu { 319 iommu {
320 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; 320 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
321 reg = <0x7000f010 0x02c 321 reg = <0x70019010 0x02c
322 0x7000f1f0 0x010 322 0x700191f0 0x010
323 0x7000f228 0x074>; 323 0x70019228 0x074>;
324 nvidia,#asids = <4>; 324 nvidia,#asids = <4>;
325 dma-window = <0 0x40000000>; 325 dma-window = <0 0x40000000>;
326 nvidia,swgroups = <0x18659fe>; 326 nvidia,swgroups = <0x18659fe>;
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
new file mode 100644
index 000000000000..431d67a2b413
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -0,0 +1,27 @@
1/dts-v1/;
2
3#include "tegra124.dtsi"
4
5/ {
6 model = "NVIDIA Tegra124 Venice2";
7 compatible = "nvidia,venice2", "nvidia,tegra124";
8
9 memory {
10 reg = <0x80000000 0x80000000>;
11 };
12
13 serial@70006000 {
14 status = "okay";
15 };
16
17 pmc@7000e400 {
18 nvidia,invert-interrupt;
19 nvidia,suspend-mode = <1>;
20 nvidia,cpu-pwr-good-time = <500>;
21 nvidia,cpu-pwr-off-time = <300>;
22 nvidia,core-pwr-good-time = <641 3845>;
23 nvidia,core-pwr-off-time = <61036>;
24 nvidia,core-power-req-active-high;
25 nvidia,sys-clock-req-active-high;
26 };
27};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
new file mode 100644
index 000000000000..b7413004ee77
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -0,0 +1,149 @@
1#include <dt-bindings/gpio/tegra-gpio.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3
4#include "skeleton.dtsi"
5
6/ {
7 compatible = "nvidia,tegra124";
8 interrupt-parent = <&gic>;
9
10 gic: interrupt-controller@50041000 {
11 compatible = "arm,cortex-a15-gic";
12 #interrupt-cells = <3>;
13 interrupt-controller;
14 reg = <0x50041000 0x1000>,
15 <0x50042000 0x1000>,
16 <0x50044000 0x2000>,
17 <0x50046000 0x2000>;
18 interrupts = <GIC_PPI 9
19 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
20 };
21
22 timer@60005000 {
23 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
24 reg = <0x60005000 0x400>;
25 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
26 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
27 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
28 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
31 };
32
33 gpio: gpio@6000d000 {
34 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
35 reg = <0x6000d000 0x1000>;
36 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
44 #gpio-cells = <2>;
45 gpio-controller;
46 #interrupt-cells = <2>;
47 interrupt-controller;
48 };
49
50 /*
51 * There are two serial driver i.e. 8250 based simple serial
52 * driver and APB DMA based serial driver for higher baudrate
53 * and performace. To enable the 8250 based driver, the compatible
54 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
55 * the APB DMA based serial driver, the comptible is
56 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
57 */
58 serial@70006000 {
59 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
60 reg = <0x70006000 0x40>;
61 reg-shift = <2>;
62 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
63 status = "disabled";
64 };
65
66 serial@70006040 {
67 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
68 reg = <0x70006040 0x40>;
69 reg-shift = <2>;
70 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
71 status = "disabled";
72 };
73
74 serial@70006200 {
75 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
76 reg = <0x70006200 0x40>;
77 reg-shift = <2>;
78 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
79 status = "disabled";
80 };
81
82 serial@70006300 {
83 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
84 reg = <0x70006300 0x40>;
85 reg-shift = <2>;
86 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
87 status = "disabled";
88 };
89
90 serial@70006400 {
91 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
92 reg = <0x70006400 0x40>;
93 reg-shift = <2>;
94 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
95 status = "disabled";
96 };
97
98 rtc@7000e000 {
99 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
100 reg = <0x7000e000 0x100>;
101 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
102 };
103
104 pmc@7000e400 {
105 compatible = "nvidia,tegra124-pmc";
106 reg = <0x7000e400 0x400>;
107 };
108
109 cpus {
110 #address-cells = <1>;
111 #size-cells = <0>;
112
113 cpu@0 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a15";
116 reg = <0>;
117 };
118
119 cpu@1 {
120 device_type = "cpu";
121 compatible = "arm,cortex-a15";
122 reg = <1>;
123 };
124
125 cpu@2 {
126 device_type = "cpu";
127 compatible = "arm,cortex-a15";
128 reg = <2>;
129 };
130
131 cpu@3 {
132 device_type = "cpu";
133 compatible = "arm,cortex-a15";
134 reg = <3>;
135 };
136 };
137
138 timer {
139 compatible = "arm,armv7-timer";
140 interrupts = <GIC_PPI 13
141 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
142 <GIC_PPI 14
143 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
144 <GIC_PPI 11
145 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
146 <GIC_PPI 10
147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
148 };
149};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index e19dbf238e5c..5ea7dfa4d9fa 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -294,9 +294,10 @@
294 }; 294 };
295 }; 295 };
296 296
297 nct1008 { 297 temperature-sensor@4c {
298 compatible = "onnn,nct1008"; 298 compatible = "onnn,nct1008";
299 reg = <0x4c>; 299 reg = <0x4c>;
300 vcc-supply = <&sys_3v3_reg>;
300 interrupt-parent = <&gpio>; 301 interrupt-parent = <&gpio>;
301 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>; 302 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
302 }; 303 };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 0022c127e1d9..2bd55cfd88ad 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -136,12 +136,13 @@
136 gr3d { 136 gr3d {
137 compatible = "nvidia,tegra30-gr3d"; 137 compatible = "nvidia,tegra30-gr3d";
138 reg = <0x54180000 0x00040000>; 138 reg = <0x54180000 0x00040000>;
139 clocks = <&tegra_car 24 &tegra_car 98>; 139 clocks = <&tegra_car TEGRA30_CLK_GR3D
140 &tegra_car TEGRA30_CLK_GR3D2>;
140 clock-names = "3d", "3d2"; 141 clock-names = "3d", "3d2";
141 }; 142 };
142 143
143 dc@54200000 { 144 dc@54200000 {
144 compatible = "nvidia,tegra30-dc"; 145 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
145 reg = <0x54200000 0x00040000>; 146 reg = <0x54200000 0x00040000>;
146 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 147 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&tegra_car TEGRA30_CLK_DISP1>, 148 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 5aba238d1f1e..fb1b2ec8eaa9 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -23,6 +23,22 @@
23 compatible = "ti,twl4030-wdt"; 23 compatible = "ti,twl4030-wdt";
24 }; 24 };
25 25
26 vaux1: regulator-vaux1 {
27 compatible = "ti,twl4030-vaux1";
28 };
29
30 vaux2: regulator-vaux2 {
31 compatible = "ti,twl4030-vaux2";
32 };
33
34 vaux3: regulator-vaux3 {
35 compatible = "ti,twl4030-vaux3";
36 };
37
38 vaux4: regulator-vaux4 {
39 compatible = "ti,twl4030-vaux4";
40 };
41
26 vcc: regulator-vdd1 { 42 vcc: regulator-vdd1 {
27 compatible = "ti,twl4030-vdd1"; 43 compatible = "ti,twl4030-vdd1";
28 regulator-min-microvolt = <600000>; 44 regulator-min-microvolt = <600000>;
@@ -35,10 +51,20 @@
35 regulator-max-microvolt = <1800000>; 51 regulator-max-microvolt = <1800000>;
36 }; 52 };
37 53
38 vpll2: regulator-vpll2 { 54 vio: regulator-vio {
39 compatible = "ti,twl4030-vpll2"; 55 compatible = "ti,twl4030-vio";
40 regulator-min-microvolt = <1800000>; 56 };
41 regulator-max-microvolt = <1800000>; 57
58 vintana1: regulator-vintana1 {
59 compatible = "ti,twl4030-vintana1";
60 };
61
62 vintana2: regulator-vintana2 {
63 compatible = "ti,twl4030-vintana2";
64 };
65
66 vintdig: regulator-vintdig {
67 compatible = "ti,twl4030-vintdig";
42 }; 68 };
43 69
44 vmmc1: regulator-vmmc1 { 70 vmmc1: regulator-vmmc1 {
@@ -65,6 +91,16 @@
65 compatible = "ti,twl4030-vusb3v1"; 91 compatible = "ti,twl4030-vusb3v1";
66 }; 92 };
67 93
94 vpll1: regulator-vpll1 {
95 compatible = "ti,twl4030-vpll1";
96 };
97
98 vpll2: regulator-vpll2 {
99 compatible = "ti,twl4030-vpll2";
100 regulator-min-microvolt = <1800000>;
101 regulator-max-microvolt = <1800000>;
102 };
103
68 vsim: regulator-vsim { 104 vsim: regulator-vsim {
69 compatible = "ti,twl4030-vsim"; 105 compatible = "ti,twl4030-vsim";
70 regulator-min-microvolt = <1800000>; 106 regulator-min-microvolt = <1800000>;
@@ -98,4 +134,9 @@
98 compatible = "ti,twl4030-pwmled"; 134 compatible = "ti,twl4030-pwmled";
99 #pwm-cells = <2>; 135 #pwm-cells = <2>;
100 }; 136 };
137
138 twl_pwrbutton: pwrbutton {
139 compatible = "ti,twl4030-pwrbutton";
140 interrupts = <8>;
141 };
101}; 142};
diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/twl6030_omap4.dtsi
new file mode 100644
index 000000000000..a4fa5703c42b
--- /dev/null
+++ b/arch/arm/boot/dts/twl6030_omap4.dtsi
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9&twl {
10 /*
11 * On most OMAP4 platforms, the twl6030 IRQ line is connected
12 * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is
13 * connected to the fref_clk0_out.sys_drm_msecure line.
14 * Therefore, configure the defaults for the SYS_NIRQ1 and
15 * fref_clk0_out.sys_drm_msecure pins here.
16 */
17 pinctrl-names = "default";
18 pinctrl-0 = <
19 &twl6030_pins
20 &twl6030_wkup_pins
21 >;
22};
23
24&omap4_pmx_wkup {
25 twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
26 pinctrl-single,pins = <
27 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
28 >;
29 };
30};
31
32&omap4_pmx_core {
33 twl6030_pins: pinmux_twl6030_pins {
34 pinctrl-single,pins = <
35 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
36 >;
37 };
38};
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
new file mode 100644
index 000000000000..c42e4f938dcd
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -0,0 +1,47 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * Copyright 2013 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11/dts-v1/;
12#include "vf610.dtsi"
13
14/ {
15 model = "PHYTEC Cosmic/Cosmic+ Board";
16 compatible = "phytec,vf610-cosmic", "fsl,vf610";
17
18 chosen {
19 bootargs = "console=ttyLP1,115200";
20 };
21
22 memory {
23 reg = <0x80000000 0x10000000>;
24 };
25
26 clocks {
27 enet_ext {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <50000000>;
31 };
32 };
33
34};
35
36&fec1 {
37 phy-mode = "rmii";
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_fec1_1>;
40 status = "okay";
41};
42
43&uart1 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_uart1_1>;
46 status = "okay";
47};
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 1a58678b93fa..c8047ca16501 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -36,6 +36,23 @@
36 36
37}; 37};
38 38
39&dspi0 {
40 bus-num = <0>;
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_dspi0_1>;
43 status = "okay";
44
45 sflash: at26df081a@0 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "atmel,at26df081a";
49 spi-max-frequency = <16000000>;
50 spi-cpol;
51 spi-cpha;
52 reg = <0>;
53 };
54};
55
39&fec0 { 56&fec0 {
40 phy-mode = "rmii"; 57 phy-mode = "rmii";
41 pinctrl-names = "default"; 58 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 67d929cf9804..d31ce1b4a7b0 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -123,6 +123,18 @@
123 status = "disabled"; 123 status = "disabled";
124 }; 124 };
125 125
126 dspi0: dspi0@4002c000 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 compatible = "fsl,vf610-dspi";
130 reg = <0x4002c000 0x1000>;
131 interrupts = <0 67 0x04>;
132 clocks = <&clks VF610_CLK_DSPI0>;
133 clock-names = "dspi";
134 spi-num-chipselects = <5>;
135 status = "disabled";
136 };
137
126 sai2: sai@40031000 { 138 sai2: sai@40031000 {
127 compatible = "fsl,vf610-sai"; 139 compatible = "fsl,vf610-sai";
128 reg = <0x40031000 0x1000>; 140 reg = <0x40031000 0x1000>;
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 254cf0539439..98a50c309b90 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -1,14 +1,13 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 1CONFIG_SYSVIPC=y
3CONFIG_POSIX_MQUEUE=y 2CONFIG_POSIX_MQUEUE=y
3CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y
4CONFIG_BSD_PROCESS_ACCT=y 5CONFIG_BSD_PROCESS_ACCT=y
5CONFIG_IKCONFIG=y 6CONFIG_IKCONFIG=y
6CONFIG_IKCONFIG_PROC=y 7CONFIG_IKCONFIG_PROC=y
7CONFIG_LOG_BUF_SHIFT=16 8CONFIG_LOG_BUF_SHIFT=16
8CONFIG_BLK_DEV_INITRD=y 9CONFIG_BLK_DEV_INITRD=y
9CONFIG_EXPERT=y 10CONFIG_EXPERT=y
10# CONFIG_SYSCTL_SYSCALL is not set
11CONFIG_KALLSYMS_EXTRA_PASS=y
12CONFIG_SLAB=y 11CONFIG_SLAB=y
13CONFIG_PROFILING=y 12CONFIG_PROFILING=y
14CONFIG_OPROFILE=y 13CONFIG_OPROFILE=y
@@ -20,22 +19,21 @@ CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_MODVERSIONS=y 19CONFIG_MODVERSIONS=y
21CONFIG_MODULE_SRCVERSION_ALL=y 20CONFIG_MODULE_SRCVERSION_ALL=y
22# CONFIG_BLK_DEV_BSG is not set 21# CONFIG_BLK_DEV_BSG is not set
22CONFIG_PARTITION_ADVANCED=y
23CONFIG_ARCH_MULTI_V6=y 23CONFIG_ARCH_MULTI_V6=y
24CONFIG_ARCH_OMAP2PLUS=y 24CONFIG_OMAP_RESET_CLOCKS=y
25CONFIG_OMAP_MUX_DEBUG=y
25CONFIG_ARCH_OMAP2=y 26CONFIG_ARCH_OMAP2=y
26CONFIG_ARCH_OMAP3=y 27CONFIG_ARCH_OMAP3=y
27CONFIG_ARCH_OMAP4=y 28CONFIG_ARCH_OMAP4=y
29CONFIG_SOC_OMAP5=y
28CONFIG_SOC_AM33XX=y 30CONFIG_SOC_AM33XX=y
29CONFIG_OMAP_RESET_CLOCKS=y 31CONFIG_SOC_DRA7XX=y
30CONFIG_OMAP_MUX_DEBUG=y
31CONFIG_ARCH_VEXPRESS_CA9X4=y
32CONFIG_ARM_THUMBEE=y 32CONFIG_ARM_THUMBEE=y
33CONFIG_ARM_ERRATA_411920=y 33CONFIG_ARM_ERRATA_411920=y
34CONFIG_NO_HZ=y
35CONFIG_HIGH_RES_TIMERS=y
36CONFIG_SMP=y 34CONFIG_SMP=y
37CONFIG_NR_CPUS=2 35CONFIG_NR_CPUS=2
38CONFIG_LEDS=y 36CONFIG_CMA=y
39CONFIG_ZBOOT_ROM_TEXT=0x0 37CONFIG_ZBOOT_ROM_TEXT=0x0
40CONFIG_ZBOOT_ROM_BSS=0x0 38CONFIG_ZBOOT_ROM_BSS=0x0
41CONFIG_ARM_APPENDED_DTB=y 39CONFIG_ARM_APPENDED_DTB=y
@@ -61,8 +59,6 @@ CONFIG_IP_PNP_RARP=y
61# CONFIG_IPV6 is not set 59# CONFIG_IPV6 is not set
62CONFIG_NETFILTER=y 60CONFIG_NETFILTER=y
63CONFIG_CAN=m 61CONFIG_CAN=m
64CONFIG_CAN_RAW=m
65CONFIG_CAN_BCM=m
66CONFIG_CAN_C_CAN=m 62CONFIG_CAN_C_CAN=m
67CONFIG_CAN_C_CAN_PLATFORM=m 63CONFIG_CAN_C_CAN_PLATFORM=m
68CONFIG_BT=m 64CONFIG_BT=m
@@ -77,14 +73,13 @@ CONFIG_MAC80211=m
77CONFIG_MAC80211_RC_PID=y 73CONFIG_MAC80211_RC_PID=y
78CONFIG_MAC80211_RC_DEFAULT_PID=y 74CONFIG_MAC80211_RC_DEFAULT_PID=y
79CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 75CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
80CONFIG_CMA=y
81CONFIG_DMA_CMA=y
82CONFIG_CONNECTOR=y
83CONFIG_DEVTMPFS=y 76CONFIG_DEVTMPFS=y
84CONFIG_DEVTMPFS_MOUNT=y 77CONFIG_DEVTMPFS_MOUNT=y
78CONFIG_DMA_CMA=y
79CONFIG_OMAP_OCP2SCP=y
80CONFIG_CONNECTOR=y
85CONFIG_MTD=y 81CONFIG_MTD=y
86CONFIG_MTD_CMDLINE_PARTS=y 82CONFIG_MTD_CMDLINE_PARTS=y
87CONFIG_MTD_CHAR=y
88CONFIG_MTD_BLOCK=y 83CONFIG_MTD_BLOCK=y
89CONFIG_MTD_OOPS=y 84CONFIG_MTD_OOPS=y
90CONFIG_MTD_CFI=y 85CONFIG_MTD_CFI=y
@@ -98,32 +93,40 @@ CONFIG_MTD_UBI=y
98CONFIG_BLK_DEV_LOOP=y 93CONFIG_BLK_DEV_LOOP=y
99CONFIG_BLK_DEV_RAM=y 94CONFIG_BLK_DEV_RAM=y
100CONFIG_BLK_DEV_RAM_SIZE=16384 95CONFIG_BLK_DEV_RAM_SIZE=16384
101CONFIG_SENSORS_LIS3LV02D=m
102CONFIG_SENSORS_TSL2550=m 96CONFIG_SENSORS_TSL2550=m
103CONFIG_SENSORS_LIS3_I2C=m
104CONFIG_BMP085_I2C=m 97CONFIG_BMP085_I2C=m
98CONFIG_SENSORS_LIS3_I2C=m
105CONFIG_SCSI=y 99CONFIG_SCSI=y
106CONFIG_BLK_DEV_SD=y 100CONFIG_BLK_DEV_SD=y
107CONFIG_SCSI_MULTI_LUN=y 101CONFIG_SCSI_MULTI_LUN=y
108CONFIG_SCSI_SCAN_ASYNC=y 102CONFIG_SCSI_SCAN_ASYNC=y
109CONFIG_MD=y 103CONFIG_MD=y
110CONFIG_NETDEVICES=y 104CONFIG_NETDEVICES=y
111CONFIG_SMSC_PHY=y
112CONFIG_NET_ETHERNET=y
113CONFIG_SMC91X=y
114CONFIG_SMSC911X=y
115CONFIG_KS8851=y 105CONFIG_KS8851=y
116CONFIG_KS8851_MLL=y 106CONFIG_KS8851_MLL=y
117CONFIG_LIBERTAS=m 107CONFIG_SMC91X=y
118CONFIG_LIBERTAS_USB=m 108CONFIG_SMSC911X=y
119CONFIG_LIBERTAS_SDIO=m 109CONFIG_TI_CPSW=y
120CONFIG_LIBERTAS_DEBUG=y 110CONFIG_AT803X_PHY=y
111CONFIG_SMSC_PHY=y
121CONFIG_USB_USBNET=y 112CONFIG_USB_USBNET=y
122CONFIG_USB_NET_SMSC95XX=y 113CONFIG_USB_NET_SMSC95XX=y
123CONFIG_USB_ALI_M5632=y 114CONFIG_USB_ALI_M5632=y
124CONFIG_USB_AN2720=y 115CONFIG_USB_AN2720=y
125CONFIG_USB_EPSON2888=y 116CONFIG_USB_EPSON2888=y
126CONFIG_USB_KC2190=y 117CONFIG_USB_KC2190=y
118CONFIG_LIBERTAS=m
119CONFIG_LIBERTAS_USB=m
120CONFIG_LIBERTAS_SDIO=m
121CONFIG_LIBERTAS_DEBUG=y
122CONFIG_WL_TI=y
123CONFIG_WL12XX=m
124CONFIG_WL18XX=m
125CONFIG_WLCORE_SPI=m
126CONFIG_WLCORE_SDIO=m
127CONFIG_MWIFIEX=m
128CONFIG_MWIFIEX_SDIO=m
129CONFIG_MWIFIEX_USB=m
127CONFIG_INPUT_JOYDEV=y 130CONFIG_INPUT_JOYDEV=y
128CONFIG_INPUT_EVDEV=y 131CONFIG_INPUT_EVDEV=y
129CONFIG_KEYBOARD_GPIO=y 132CONFIG_KEYBOARD_GPIO=y
@@ -133,7 +136,6 @@ CONFIG_INPUT_TOUCHSCREEN=y
133CONFIG_TOUCHSCREEN_ADS7846=y 136CONFIG_TOUCHSCREEN_ADS7846=y
134CONFIG_INPUT_MISC=y 137CONFIG_INPUT_MISC=y
135CONFIG_INPUT_TWL4030_PWRBUTTON=y 138CONFIG_INPUT_TWL4030_PWRBUTTON=y
136CONFIG_VT_HW_CONSOLE_BINDING=y
137# CONFIG_LEGACY_PTYS is not set 139# CONFIG_LEGACY_PTYS is not set
138CONFIG_SERIAL_8250=y 140CONFIG_SERIAL_8250=y
139CONFIG_SERIAL_8250_CONSOLE=y 141CONFIG_SERIAL_8250_CONSOLE=y
@@ -143,8 +145,7 @@ CONFIG_SERIAL_8250_MANY_PORTS=y
143CONFIG_SERIAL_8250_SHARE_IRQ=y 145CONFIG_SERIAL_8250_SHARE_IRQ=y
144CONFIG_SERIAL_8250_DETECT_IRQ=y 146CONFIG_SERIAL_8250_DETECT_IRQ=y
145CONFIG_SERIAL_8250_RSA=y 147CONFIG_SERIAL_8250_RSA=y
146CONFIG_SERIAL_AMBA_PL011=y 148CONFIG_SERIAL_OF_PLATFORM=y
147CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
148CONFIG_SERIAL_OMAP=y 149CONFIG_SERIAL_OMAP=y
149CONFIG_SERIAL_OMAP_CONSOLE=y 150CONFIG_SERIAL_OMAP_CONSOLE=y
150CONFIG_HW_RANDOM=y 151CONFIG_HW_RANDOM=y
@@ -158,31 +159,31 @@ CONFIG_GPIO_TWL4030=y
158CONFIG_W1=y 159CONFIG_W1=y
159CONFIG_POWER_SUPPLY=y 160CONFIG_POWER_SUPPLY=y
160CONFIG_SENSORS_LM75=m 161CONFIG_SENSORS_LM75=m
161CONFIG_WATCHDOG=y
162CONFIG_THERMAL=y 162CONFIG_THERMAL=y
163CONFIG_THERMAL_HWMON=y
164CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
165CONFIG_THERMAL_GOV_FAIR_SHARE=y 163CONFIG_THERMAL_GOV_FAIR_SHARE=y
166CONFIG_THERMAL_GOV_STEP_WISE=y
167CONFIG_THERMAL_GOV_USER_SPACE=y 164CONFIG_THERMAL_GOV_USER_SPACE=y
168CONFIG_CPU_THERMAL=y 165CONFIG_TI_SOC_THERMAL=y
166CONFIG_OMAP4_THERMAL=y
167CONFIG_OMAP5_THERMAL=y
168CONFIG_DRA752_THERMAL=y
169CONFIG_WATCHDOG=y
169CONFIG_OMAP_WATCHDOG=y 170CONFIG_OMAP_WATCHDOG=y
170CONFIG_TWL4030_WATCHDOG=y 171CONFIG_TWL4030_WATCHDOG=y
172CONFIG_MFD_PALMAS=y
171CONFIG_MFD_TPS65217=y 173CONFIG_MFD_TPS65217=y
172CONFIG_MFD_TPS65910=y 174CONFIG_MFD_TPS65910=y
173CONFIG_TWL6040_CORE=y 175CONFIG_TWL6040_CORE=y
174CONFIG_REGULATOR_TWL4030=y 176CONFIG_REGULATOR_PALMAS=y
175CONFIG_REGULATOR_TPS65023=y 177CONFIG_REGULATOR_TPS65023=y
176CONFIG_REGULATOR_TPS6507X=y 178CONFIG_REGULATOR_TPS6507X=y
177CONFIG_REGULATOR_TPS65217=y 179CONFIG_REGULATOR_TPS65217=y
178CONFIG_REGULATOR_TPS65910=y 180CONFIG_REGULATOR_TPS65910=y
181CONFIG_REGULATOR_TWL4030=y
179CONFIG_FB=y 182CONFIG_FB=y
180CONFIG_FIRMWARE_EDID=y 183CONFIG_FIRMWARE_EDID=y
181CONFIG_FB_MODE_HELPERS=y 184CONFIG_FB_MODE_HELPERS=y
182CONFIG_FB_TILEBLITTING=y 185CONFIG_FB_TILEBLITTING=y
183CONFIG_FB_OMAP_LCD_VGA=y
184CONFIG_OMAP2_DSS=m 186CONFIG_OMAP2_DSS=m
185CONFIG_OMAP2_DSS_RFBI=y
186CONFIG_OMAP2_DSS_SDI=y 187CONFIG_OMAP2_DSS_SDI=y
187CONFIG_OMAP2_DSS_DSI=y 188CONFIG_OMAP2_DSS_DSI=y
188CONFIG_FB_OMAP2=m 189CONFIG_FB_OMAP2=m
@@ -194,12 +195,8 @@ CONFIG_DISPLAY_PANEL_DPI=m
194CONFIG_BACKLIGHT_LCD_SUPPORT=y 195CONFIG_BACKLIGHT_LCD_SUPPORT=y
195CONFIG_LCD_CLASS_DEVICE=y 196CONFIG_LCD_CLASS_DEVICE=y
196CONFIG_LCD_PLATFORM=y 197CONFIG_LCD_PLATFORM=y
197CONFIG_DISPLAY_SUPPORT=y
198CONFIG_FRAMEBUFFER_CONSOLE=y 198CONFIG_FRAMEBUFFER_CONSOLE=y
199CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y 199CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
200CONFIG_FONTS=y
201CONFIG_FONT_8x8=y
202CONFIG_FONT_8x16=y
203CONFIG_LOGO=y 200CONFIG_LOGO=y
204CONFIG_SOUND=m 201CONFIG_SOUND=m
205CONFIG_SND=m 202CONFIG_SND=m
@@ -216,14 +213,14 @@ CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
216CONFIG_USB=y 213CONFIG_USB=y
217CONFIG_USB_DEBUG=y 214CONFIG_USB_DEBUG=y
218CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 215CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
219CONFIG_USB_DEVICEFS=y
220CONFIG_USB_MON=y 216CONFIG_USB_MON=y
221CONFIG_USB_WDM=y 217CONFIG_USB_WDM=y
222CONFIG_USB_STORAGE=y 218CONFIG_USB_STORAGE=y
223CONFIG_USB_LIBUSUAL=y 219CONFIG_USB_DWC3=m
224CONFIG_USB_TEST=y 220CONFIG_USB_TEST=y
225CONFIG_USB_PHY=y
226CONFIG_NOP_USB_XCEIV=y 221CONFIG_NOP_USB_XCEIV=y
222CONFIG_OMAP_USB2=y
223CONFIG_OMAP_USB3=y
227CONFIG_USB_GADGET=y 224CONFIG_USB_GADGET=y
228CONFIG_USB_GADGET_DEBUG=y 225CONFIG_USB_GADGET_DEBUG=y
229CONFIG_USB_GADGET_DEBUG_FILES=y 226CONFIG_USB_GADGET_DEBUG_FILES=y
@@ -232,7 +229,6 @@ CONFIG_USB_ZERO=m
232CONFIG_MMC=y 229CONFIG_MMC=y
233CONFIG_MMC_UNSAFE_RESUME=y 230CONFIG_MMC_UNSAFE_RESUME=y
234CONFIG_SDIO_UART=y 231CONFIG_SDIO_UART=y
235CONFIG_MMC_ARMMMCI=y
236CONFIG_MMC_OMAP=y 232CONFIG_MMC_OMAP=y
237CONFIG_MMC_OMAP_HS=y 233CONFIG_MMC_OMAP_HS=y
238CONFIG_NEW_LEDS=y 234CONFIG_NEW_LEDS=y
@@ -252,11 +248,8 @@ CONFIG_RTC_DRV_OMAP=y
252CONFIG_DMADEVICES=y 248CONFIG_DMADEVICES=y
253CONFIG_TI_EDMA=y 249CONFIG_TI_EDMA=y
254CONFIG_DMA_OMAP=y 250CONFIG_DMA_OMAP=y
255CONFIG_TI_SOC_THERMAL=y 251CONFIG_EXTCON=y
256CONFIG_TI_THERMAL=y 252CONFIG_EXTCON_PALMAS=y
257CONFIG_OMAP4_THERMAL=y
258CONFIG_OMAP5_THERMAL=y
259CONFIG_DRA752_THERMAL=y
260CONFIG_EXT2_FS=y 253CONFIG_EXT2_FS=y
261CONFIG_EXT3_FS=y 254CONFIG_EXT3_FS=y
262# CONFIG_EXT3_FS_XATTR is not set 255# CONFIG_EXT3_FS_XATTR is not set
@@ -275,23 +268,18 @@ CONFIG_JFFS2_RUBIN=y
275CONFIG_UBIFS_FS=y 268CONFIG_UBIFS_FS=y
276CONFIG_CRAMFS=y 269CONFIG_CRAMFS=y
277CONFIG_NFS_FS=y 270CONFIG_NFS_FS=y
278CONFIG_NFS_V3=y
279CONFIG_NFS_V3_ACL=y 271CONFIG_NFS_V3_ACL=y
280CONFIG_NFS_V4=y 272CONFIG_NFS_V4=y
281CONFIG_ROOT_NFS=y 273CONFIG_ROOT_NFS=y
282CONFIG_PARTITION_ADVANCED=y
283CONFIG_NLS_CODEPAGE_437=y 274CONFIG_NLS_CODEPAGE_437=y
284CONFIG_NLS_ISO8859_1=y 275CONFIG_NLS_ISO8859_1=y
285CONFIG_PRINTK_TIME=y 276CONFIG_PRINTK_TIME=y
277CONFIG_DEBUG_INFO=y
286CONFIG_MAGIC_SYSRQ=y 278CONFIG_MAGIC_SYSRQ=y
287CONFIG_DEBUG_KERNEL=y
288CONFIG_SCHEDSTATS=y 279CONFIG_SCHEDSTATS=y
289CONFIG_TIMER_STATS=y 280CONFIG_TIMER_STATS=y
290CONFIG_PROVE_LOCKING=y 281CONFIG_PROVE_LOCKING=y
291CONFIG_DEBUG_SPINLOCK_SLEEP=y
292# CONFIG_DEBUG_BUGVERBOSE is not set 282# CONFIG_DEBUG_BUGVERBOSE is not set
293CONFIG_DEBUG_INFO=y
294# CONFIG_RCU_CPU_STALL_DETECTOR is not set
295CONFIG_SECURITY=y 283CONFIG_SECURITY=y
296CONFIG_CRYPTO_MICHAEL_MIC=y 284CONFIG_CRYPTO_MICHAEL_MIC=y
297# CONFIG_CRYPTO_ANSI_CPRNG is not set 285# CONFIG_CRYPTO_ANSI_CPRNG is not set
@@ -300,9 +288,6 @@ CONFIG_CRC_T10DIF=y
300CONFIG_CRC_ITU_T=y 288CONFIG_CRC_ITU_T=y
301CONFIG_CRC7=y 289CONFIG_CRC7=y
302CONFIG_LIBCRC32C=y 290CONFIG_LIBCRC32C=y
303CONFIG_SOC_OMAP5=y 291CONFIG_FONTS=y
304CONFIG_TI_DAVINCI_MDIO=y 292CONFIG_FONT_8x8=y
305CONFIG_TI_DAVINCI_CPDMA=y 293CONFIG_FONT_8x16=y
306CONFIG_TI_CPSW=y
307CONFIG_AT803X_PHY=y
308CONFIG_SOC_DRA7XX=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index a0025dc13021..ac632cc38f24 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -1,4 +1,3 @@
1CONFIG_HIGHMEM=y
2# CONFIG_SWAP is not set 1# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
4CONFIG_NO_HZ=y 3CONFIG_NO_HZ=y
@@ -16,6 +15,9 @@ CONFIG_SMP=y
16CONFIG_NR_CPUS=2 15CONFIG_NR_CPUS=2
17CONFIG_PREEMPT=y 16CONFIG_PREEMPT=y
18CONFIG_AEABI=y 17CONFIG_AEABI=y
18CONFIG_HIGHMEM=y
19CONFIG_ARM_APPENDED_DTB=y
20CONFIG_ARM_ATAG_DTB_COMPAT=y
19CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8" 21CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
20CONFIG_CPU_FREQ=y 22CONFIG_CPU_FREQ=y
21CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y 23CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
@@ -68,8 +70,8 @@ CONFIG_CPU_THERMAL=y
68CONFIG_WATCHDOG=y 70CONFIG_WATCHDOG=y
69CONFIG_MFD_STMPE=y 71CONFIG_MFD_STMPE=y
70CONFIG_MFD_TC3589X=y 72CONFIG_MFD_TC3589X=y
71CONFIG_REGULATOR_GPIO=y
72CONFIG_REGULATOR_AB8500=y 73CONFIG_REGULATOR_AB8500=y
74CONFIG_REGULATOR_GPIO=y
73CONFIG_SOUND=y 75CONFIG_SOUND=y
74CONFIG_SND=y 76CONFIG_SND=y
75CONFIG_SND_SOC=y 77CONFIG_SND_SOC=y
@@ -78,10 +80,8 @@ CONFIG_SND_SOC_UX500_MACH_MOP500=y
78CONFIG_USB=y 80CONFIG_USB=y
79CONFIG_USB_MUSB_HDRC=y 81CONFIG_USB_MUSB_HDRC=y
80CONFIG_USB_MUSB_UX500=y 82CONFIG_USB_MUSB_UX500=y
81CONFIG_USB_PHY=y
82CONFIG_AB8500_USB=y 83CONFIG_AB8500_USB=y
83CONFIG_USB_GADGET=y 84CONFIG_USB_GADGET=y
84CONFIG_USB_GADGET_MUSB_HDRC=y
85CONFIG_USB_ETH=m 85CONFIG_USB_ETH=m
86CONFIG_MMC=y 86CONFIG_MMC=y
87CONFIG_MMC_UNSAFE_RESUME=y 87CONFIG_MMC_UNSAFE_RESUME=y
@@ -116,12 +116,12 @@ CONFIG_NFS_FS=y
116CONFIG_ROOT_NFS=y 116CONFIG_ROOT_NFS=y
117CONFIG_NLS_CODEPAGE_437=y 117CONFIG_NLS_CODEPAGE_437=y
118CONFIG_NLS_ISO8859_1=y 118CONFIG_NLS_ISO8859_1=y
119CONFIG_MAGIC_SYSRQ=y 119CONFIG_DEBUG_INFO=y
120CONFIG_DEBUG_FS=y 120CONFIG_DEBUG_FS=y
121CONFIG_MAGIC_SYSRQ=y
121CONFIG_DEBUG_KERNEL=y 122CONFIG_DEBUG_KERNEL=y
122# CONFIG_SCHED_DEBUG is not set 123# CONFIG_SCHED_DEBUG is not set
123# CONFIG_DEBUG_PREEMPT is not set 124# CONFIG_DEBUG_PREEMPT is not set
124CONFIG_DEBUG_INFO=y
125# CONFIG_FTRACE is not set 125# CONFIG_FTRACE is not set
126CONFIG_DEBUG_USER=y 126CONFIG_DEBUG_USER=y
127CONFIG_CRYPTO_DEV_UX500=y 127CONFIG_CRYPTO_DEV_UX500=y
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index c7d670d11802..2d895a297739 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -169,6 +169,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
169 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk), 169 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
170 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk), 170 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
171 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk), 171 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
172 CLKDEV_CON_DEV_ID(NULL, "f0010000.ssc", &ssc_clk),
172 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk), 173 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
173 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), 174 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
174 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), 175 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index c9f6fd2d90f5..9caa4fe95913 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -151,7 +151,6 @@ static void __init kirkwood_dt_init(void)
151 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); 151 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
152 152
153 BUG_ON(mvebu_mbus_dt_init()); 153 BUG_ON(mvebu_mbus_dt_init());
154 kirkwood_setup_wins();
155 154
156 kirkwood_l2_init(); 155 kirkwood_l2_init();
157 156
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index cc511a4890a3..1dc5acd4fc99 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -330,6 +330,11 @@ static void __init crystalfontz_init(void)
330 update_fec_mac_prop(OUI_CRYSTALFONTZ); 330 update_fec_mac_prop(OUI_CRYSTALFONTZ);
331} 331}
332 332
333static void __init m28cu3_init(void)
334{
335 update_fec_mac_prop(OUI_DENX);
336}
337
333static const char __init *mxs_get_soc_id(void) 338static const char __init *mxs_get_soc_id(void)
334{ 339{
335 struct device_node *np; 340 struct device_node *np;
@@ -457,6 +462,8 @@ static void __init mxs_machine_init(void)
457 apx4devkit_init(); 462 apx4devkit_init();
458 else if (of_machine_is_compatible("crystalfontz,cfa10036")) 463 else if (of_machine_is_compatible("crystalfontz,cfa10036"))
459 crystalfontz_init(); 464 crystalfontz_init();
465 else if (of_machine_is_compatible("msr,m28cu3"))
466 m28cu3_init();
460 467
461 of_platform_populate(NULL, of_default_bus_match_table, 468 of_platform_populate(NULL, of_default_bus_match_table,
462 NULL, parent); 469 NULL, parent);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index c94624429680..dc21df166161 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -87,6 +87,7 @@ config ARCH_OMAP2PLUS
87 select COMMON_CLK 87 select COMMON_CLK
88 select GENERIC_CLOCKEVENTS 88 select GENERIC_CLOCKEVENTS
89 select GENERIC_IRQ_CHIP 89 select GENERIC_IRQ_CHIP
90 select MACH_OMAP_GENERIC
90 select OMAP_DM_TIMER 91 select OMAP_DM_TIMER
91 select PINCTRL 92 select PINCTRL
92 select PROC_DEVICETREE if PROC_FS 93 select PROC_DEVICETREE if PROC_FS
@@ -180,16 +181,11 @@ config OMAP_PACKAGE_CUS
180config OMAP_PACKAGE_CBP 181config OMAP_PACKAGE_CBP
181 bool 182 bool
182 183
183comment "OMAP Board Type" 184comment "OMAP Legacy Platform Data Board Type"
184 depends on ARCH_OMAP2PLUS 185 depends on ARCH_OMAP2PLUS
185 186
186config MACH_OMAP_GENERIC 187config MACH_OMAP_GENERIC
187 bool "Generic OMAP2+ board" 188 bool
188 depends on ARCH_OMAP2PLUS
189 default y
190 help
191 Support for generic TI OMAP2+ boards using Flattened Device Tree.
192 More information at Documentation/devicetree
193 189
194config MACH_OMAP2_TUSB6010 190config MACH_OMAP2_TUSB6010
195 bool 191 bool
@@ -253,12 +249,6 @@ config MACH_OVERO
253 default y 249 default y
254 select OMAP_PACKAGE_CBB 250 select OMAP_PACKAGE_CBB
255 251
256config MACH_OMAP3EVM
257 bool "OMAP 3530 EVM board"
258 depends on ARCH_OMAP3
259 default y
260 select OMAP_PACKAGE_CBB
261
262config MACH_OMAP3517EVM 252config MACH_OMAP3517EVM
263 bool "OMAP3517/ AM3517 EVM board" 253 bool "OMAP3517/ AM3517 EVM board"
264 depends on ARCH_OMAP3 254 depends on ARCH_OMAP3
@@ -307,33 +297,12 @@ config MACH_NOKIA_N8X0
307 select MACH_NOKIA_N810_WIMAX 297 select MACH_NOKIA_N810_WIMAX
308 select OMAP_PACKAGE_ZAC 298 select OMAP_PACKAGE_ZAC
309 299
310config MACH_NOKIA_RM680
311 bool "Nokia N950 (RM-680) / N9 (RM-696) phones"
312 depends on ARCH_OMAP3
313 default y
314 select MACH_NOKIA_RM696
315 select OMAP_PACKAGE_CBB
316
317config MACH_NOKIA_RX51 300config MACH_NOKIA_RX51
318 bool "Nokia N900 (RX-51) phone" 301 bool "Nokia N900 (RX-51) phone"
319 depends on ARCH_OMAP3 302 depends on ARCH_OMAP3
320 default y 303 default y
321 select OMAP_PACKAGE_CBB 304 select OMAP_PACKAGE_CBB
322 305
323config MACH_OMAP_ZOOM2
324 bool "OMAP3 Zoom2 board"
325 depends on ARCH_OMAP3
326 default y
327 select OMAP_PACKAGE_CBB
328 select REGULATOR_FIXED_VOLTAGE if REGULATOR
329
330config MACH_OMAP_ZOOM3
331 bool "OMAP3630 Zoom3 board"
332 depends on ARCH_OMAP3
333 default y
334 select OMAP_PACKAGE_CBP
335 select REGULATOR_FIXED_VOLTAGE if REGULATOR
336
337config MACH_CM_T35 306config MACH_CM_T35
338 bool "CompuLab CM-T35/CM-T3730 modules" 307 bool "CompuLab CM-T35/CM-T3730 modules"
339 depends on ARCH_OMAP3 308 depends on ARCH_OMAP3
@@ -350,31 +319,12 @@ config MACH_CM_T3517
350config MACH_CM_T3730 319config MACH_CM_T3730
351 bool 320 bool
352 321
353config MACH_IGEP0020
354 bool "IGEP v2 board"
355 depends on ARCH_OMAP3
356 default y
357 select OMAP_PACKAGE_CBB
358
359config MACH_IGEP0030
360 bool "IGEP OMAP3 module"
361 depends on ARCH_OMAP3
362 default y
363 select MACH_IGEP0020
364 select OMAP_PACKAGE_CBB
365
366config MACH_SBC3530 322config MACH_SBC3530
367 bool "OMAP3 SBC STALKER board" 323 bool "OMAP3 SBC STALKER board"
368 depends on ARCH_OMAP3 324 depends on ARCH_OMAP3
369 default y 325 default y
370 select OMAP_PACKAGE_CUS 326 select OMAP_PACKAGE_CUS
371 327
372config MACH_OMAP_3630SDP
373 bool "OMAP3630 SDP board"
374 depends on ARCH_OMAP3
375 default y
376 select OMAP_PACKAGE_CBP
377
378config MACH_TI8168EVM 328config MACH_TI8168EVM
379 bool "TI8168 Evaluation Module" 329 bool "TI8168 Evaluation Module"
380 depends on SOC_TI81XX 330 depends on SOC_TI81XX
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9b7619f2c1ac..e15ac005ef17 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -236,7 +236,7 @@ endif
236obj-$(CONFIG_SOC_OMAP2420) += msdi.o 236obj-$(CONFIG_SOC_OMAP2420) += msdi.o
237 237
238# Specific board support 238# Specific board support
239obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 239obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
240obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o 240obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
241obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o 241obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
242obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o 242obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
@@ -245,26 +245,14 @@ obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
245obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o 245obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
246obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o 246obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
247obj-$(CONFIG_MACH_OVERO) += board-overo.o 247obj-$(CONFIG_MACH_OVERO) += board-overo.o
248obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o
249obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o 248obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
250obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o 249obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o
251obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o 250obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
252obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o sdram-nokia.o
253obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o 251obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
254obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o 252obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
255obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o 253obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o
256obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o board-zoom-peripherals.o
257obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom-display.o
258obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom-debugboard.o
259obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o board-zoom-peripherals.o
260obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom-display.o
261obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom-debugboard.o
262obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o
263obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-peripherals.o
264obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-display.o
265obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o 254obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
266obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o 255obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
267obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o
268obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o 256obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o
269 257
270obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o 258obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
deleted file mode 100644
index 20d6d8189240..000000000000
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ /dev/null
@@ -1,225 +0,0 @@
1/*
2 * Copyright (C) 2009 Texas Instruments Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/input.h>
13#include <linux/gpio.h>
14#include <linux/mtd/nand.h>
15
16#include <asm/mach-types.h>
17#include <asm/mach/arch.h>
18
19#include "common.h"
20#include "gpmc-smc91x.h"
21
22#include "board-zoom.h"
23
24#include "board-flash.h"
25#include "mux.h"
26#include "sdram-hynix-h8mbx00u0mer-0em.h"
27
28#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
29
30static struct omap_smc91x_platform_data board_smc91x_data = {
31 .cs = 3,
32 .flags = GPMC_MUX_ADD_DATA | IORESOURCE_IRQ_LOWLEVEL,
33};
34
35static void __init board_smc91x_init(void)
36{
37 board_smc91x_data.gpio_irq = 158;
38 gpmc_smc91x_init(&board_smc91x_data);
39}
40
41#else
42
43static inline void board_smc91x_init(void)
44{
45}
46
47#endif /* defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) */
48
49static void enable_board_wakeup_source(void)
50{
51 /* T2 interrupt line (keypad) */
52 omap_mux_init_signal("sys_nirq",
53 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
54}
55
56static struct usbhs_phy_data phy_data[] __initdata = {
57 {
58 .port = 1,
59 .reset_gpio = 126,
60 .vcc_gpio = -EINVAL,
61 },
62 {
63 .port = 2,
64 .reset_gpio = 61,
65 .vcc_gpio = -EINVAL,
66 },
67};
68
69static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
70
71 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
72 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
73};
74
75#ifdef CONFIG_OMAP_MUX
76static struct omap_board_mux board_mux[] __initdata = {
77 { .reg_offset = OMAP_MUX_TERMINATOR },
78};
79#endif
80
81/*
82 * SDP3630 CS organization
83 * See also the Switch S8 settings in the comments.
84 */
85static char chip_sel_sdp[][GPMC_CS_NUM] = {
86 {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
87 {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
88 {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
89};
90
91static struct mtd_partition sdp_nor_partitions[] = {
92 /* bootloader (U-Boot, etc) in first sector */
93 {
94 .name = "Bootloader-NOR",
95 .offset = 0,
96 .size = SZ_256K,
97 .mask_flags = MTD_WRITEABLE, /* force read-only */
98 },
99 /* bootloader params in the next sector */
100 {
101 .name = "Params-NOR",
102 .offset = MTDPART_OFS_APPEND,
103 .size = SZ_256K,
104 .mask_flags = 0,
105 },
106 /* kernel */
107 {
108 .name = "Kernel-NOR",
109 .offset = MTDPART_OFS_APPEND,
110 .size = SZ_2M,
111 .mask_flags = 0
112 },
113 /* file system */
114 {
115 .name = "Filesystem-NOR",
116 .offset = MTDPART_OFS_APPEND,
117 .size = MTDPART_SIZ_FULL,
118 .mask_flags = 0
119 }
120};
121
122static struct mtd_partition sdp_onenand_partitions[] = {
123 {
124 .name = "X-Loader-OneNAND",
125 .offset = 0,
126 .size = 4 * (64 * 2048),
127 .mask_flags = MTD_WRITEABLE /* force read-only */
128 },
129 {
130 .name = "U-Boot-OneNAND",
131 .offset = MTDPART_OFS_APPEND,
132 .size = 2 * (64 * 2048),
133 .mask_flags = MTD_WRITEABLE /* force read-only */
134 },
135 {
136 .name = "U-Boot Environment-OneNAND",
137 .offset = MTDPART_OFS_APPEND,
138 .size = 1 * (64 * 2048),
139 },
140 {
141 .name = "Kernel-OneNAND",
142 .offset = MTDPART_OFS_APPEND,
143 .size = 16 * (64 * 2048),
144 },
145 {
146 .name = "File System-OneNAND",
147 .offset = MTDPART_OFS_APPEND,
148 .size = MTDPART_SIZ_FULL,
149 },
150};
151
152static struct mtd_partition sdp_nand_partitions[] = {
153 /* All the partition sizes are listed in terms of NAND block size */
154 {
155 .name = "X-Loader-NAND",
156 .offset = 0,
157 .size = 4 * (64 * 2048),
158 .mask_flags = MTD_WRITEABLE, /* force read-only */
159 },
160 {
161 .name = "U-Boot-NAND",
162 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
163 .size = 10 * (64 * 2048),
164 .mask_flags = MTD_WRITEABLE, /* force read-only */
165 },
166 {
167 .name = "Boot Env-NAND",
168
169 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
170 .size = 6 * (64 * 2048),
171 },
172 {
173 .name = "Kernel-NAND",
174 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
175 .size = 40 * (64 * 2048),
176 },
177 {
178 .name = "File System - NAND",
179 .size = MTDPART_SIZ_FULL,
180 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
181 },
182};
183
184static struct flash_partitions sdp_flash_partitions[] = {
185 {
186 .parts = sdp_nor_partitions,
187 .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
188 },
189 {
190 .parts = sdp_onenand_partitions,
191 .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
192 },
193 {
194 .parts = sdp_nand_partitions,
195 .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
196 },
197};
198
199static void __init omap_sdp_init(void)
200{
201 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
202 zoom_peripherals_init();
203 omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
204 h8mbx00u0mer0em_sdrc_params);
205 zoom_display_init();
206 board_smc91x_init();
207 board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
208 enable_board_wakeup_source();
209
210 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
211 usbhs_init(&usbhs_bdata);
212}
213
214MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
215 .atag_offset = 0x100,
216 .reserve = omap_reserve,
217 .map_io = omap3_map_io,
218 .init_early = omap3630_init_early,
219 .init_irq = omap3_init_irq,
220 .handle_irq = omap3_intc_handle_irq,
221 .init_machine = omap_sdp_init,
222 .init_late = omap3630_init_late,
223 .init_time = omap3_sync32k_timer_init,
224 .restart = omap3xxx_restart,
225MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 87162e1b94a5..19f1652e94cf 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -15,13 +15,10 @@
15#include <linux/of_irq.h> 15#include <linux/of_irq.h>
16#include <linux/of_platform.h> 16#include <linux/of_platform.h>
17#include <linux/irqdomain.h> 17#include <linux/irqdomain.h>
18#include <linux/clk.h>
19 18
20#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
21 20
22#include "common.h" 21#include "common.h"
23#include "common-board-devices.h"
24#include "dss-common.h"
25 22
26#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) 23#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
27#define intc_of_init NULL 24#define intc_of_init NULL
@@ -36,40 +33,9 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
36 { } 33 { }
37}; 34};
38 35
39/*
40 * Create alias for USB host PHY clock.
41 * Remove this when clock phandle can be provided via DT
42 */
43static void __init legacy_init_ehci_clk(char *clkname)
44{
45 int ret;
46
47 ret = clk_add_alias("main_clk", NULL, clkname, NULL);
48 if (ret) {
49 pr_err("%s:Failed to add main_clk alias to %s :%d\n",
50 __func__, clkname, ret);
51 }
52}
53
54static void __init omap_generic_init(void) 36static void __init omap_generic_init(void)
55{ 37{
56 omap_sdrc_init(NULL, NULL); 38 pdata_quirks_init(omap_dt_match_table);
57
58 of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
59
60 /*
61 * HACK: call display setup code for selected boards to enable omapdss.
62 * This will be removed when omapdss supports DT.
63 */
64 if (of_machine_is_compatible("ti,omap4-panda")) {
65 omap4_panda_display_init_of();
66 legacy_init_ehci_clk("auxclk3_ck");
67
68 }
69 else if (of_machine_is_compatible("ti,omap4-sdp"))
70 omap_4430sdp_display_init_of();
71 else if (of_machine_is_compatible("ti,omap5-uevm"))
72 legacy_init_ehci_clk("auxclk1_ck");
73} 39}
74 40
75#ifdef CONFIG_SOC_OMAP2420 41#ifdef CONFIG_SOC_OMAP2420
@@ -180,6 +146,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
180 .init_irq = omap_intc_of_init, 146 .init_irq = omap_intc_of_init,
181 .handle_irq = omap3_intc_handle_irq, 147 .handle_irq = omap3_intc_handle_irq,
182 .init_machine = omap_generic_init, 148 .init_machine = omap_generic_init,
149 .init_late = am33xx_init_late,
183 .init_time = omap3_gptimer_timer_init, 150 .init_time = omap3_gptimer_timer_init,
184 .dt_compat = am33xx_boards_compat, 151 .dt_compat = am33xx_boards_compat,
185 .restart = am33xx_restart, 152 .restart = am33xx_restart,
@@ -219,6 +186,7 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
219 .init_early = omap5_init_early, 186 .init_early = omap5_init_early,
220 .init_irq = omap_gic_of_init, 187 .init_irq = omap_gic_of_init,
221 .init_machine = omap_generic_init, 188 .init_machine = omap_generic_init,
189 .init_late = omap5_init_late,
222 .init_time = omap5_realtime_timer_init, 190 .init_time = omap5_realtime_timer_init,
223 .dt_compat = omap5_boards_compat, 191 .dt_compat = omap5_boards_compat,
224 .restart = omap44xx_restart, 192 .restart = omap44xx_restart,
@@ -234,6 +202,7 @@ static const char *am43_boards_compat[] __initdata = {
234DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") 202DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
235 .map_io = am33xx_map_io, 203 .map_io = am33xx_map_io,
236 .init_early = am43xx_init_early, 204 .init_early = am43xx_init_early,
205 .init_late = am43xx_init_late,
237 .init_irq = omap_gic_of_init, 206 .init_irq = omap_gic_of_init,
238 .init_machine = omap_generic_init, 207 .init_machine = omap_generic_init,
239 .init_time = omap3_sync32k_timer_init, 208 .init_time = omap3_sync32k_timer_init,
@@ -252,6 +221,7 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
252 .smp = smp_ops(omap4_smp_ops), 221 .smp = smp_ops(omap4_smp_ops),
253 .map_io = omap5_map_io, 222 .map_io = omap5_map_io,
254 .init_early = dra7xx_init_early, 223 .init_early = dra7xx_init_early,
224 .init_late = dra7xx_init_late,
255 .init_irq = omap_gic_of_init, 225 .init_irq = omap_gic_of_init,
256 .init_machine = omap_generic_init, 226 .init_machine = omap_generic_init,
257 .init_time = omap5_realtime_timer_init, 227 .init_time = omap5_realtime_timer_init,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
deleted file mode 100644
index 06dbb2d3d38b..000000000000
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ /dev/null
@@ -1,718 +0,0 @@
1/*
2 * Copyright (C) 2009 Integration Software and Electronic Engineering.
3 *
4 * Modified from mach-omap2/board-generic.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/interrupt.h>
20#include <linux/input.h>
21#include <linux/usb/phy.h>
22
23#include <linux/regulator/machine.h>
24#include <linux/regulator/fixed.h>
25#include <linux/i2c/twl.h>
26#include <linux/mmc/host.h>
27
28#include <linux/mtd/nand.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#include <video/omapdss.h>
34#include <video/omap-panel-data.h>
35#include <linux/platform_data/mtd-onenand-omap2.h>
36
37#include "common.h"
38#include "gpmc.h"
39#include "mux.h"
40#include "hsmmc.h"
41#include "sdram-numonyx-m65kxxxxam.h"
42#include "common-board-devices.h"
43#include "board-flash.h"
44#include "control.h"
45#include "gpmc-onenand.h"
46
47#define IGEP2_SMSC911X_CS 5
48#define IGEP2_SMSC911X_GPIO 176
49#define IGEP2_GPIO_USBH_NRESET 24
50#define IGEP2_GPIO_LED0_GREEN 26
51#define IGEP2_GPIO_LED0_RED 27
52#define IGEP2_GPIO_LED1_RED 28
53#define IGEP2_GPIO_DVI_PUP 170
54
55#define IGEP2_RB_GPIO_WIFI_NPD 94
56#define IGEP2_RB_GPIO_WIFI_NRESET 95
57#define IGEP2_RB_GPIO_BT_NRESET 137
58#define IGEP2_RC_GPIO_WIFI_NPD 138
59#define IGEP2_RC_GPIO_WIFI_NRESET 139
60#define IGEP2_RC_GPIO_BT_NRESET 137
61
62#define IGEP3_GPIO_LED0_GREEN 54
63#define IGEP3_GPIO_LED0_RED 53
64#define IGEP3_GPIO_LED1_RED 16
65#define IGEP3_GPIO_USBH_NRESET 183
66
67#define IGEP_SYSBOOT_MASK 0x1f
68#define IGEP_SYSBOOT_NAND 0x0f
69#define IGEP_SYSBOOT_ONENAND 0x10
70
71/*
72 * IGEP2 Hardware Revision Table
73 *
74 * --------------------------------------------------------------------------
75 * | Id. | Hw Rev. | HW0 (28) | WIFI_NPD | WIFI_NRESET | BT_NRESET |
76 * --------------------------------------------------------------------------
77 * | 0 | B | high | gpio94 | gpio95 | - |
78 * | 0 | B/C (B-compatible) | high | gpio94 | gpio95 | gpio137 |
79 * | 1 | C | low | gpio138 | gpio139 | gpio137 |
80 * --------------------------------------------------------------------------
81 */
82
83#define IGEP2_BOARD_HWREV_B 0
84#define IGEP2_BOARD_HWREV_C 1
85#define IGEP3_BOARD_HWREV 2
86
87static u8 hwrev;
88
89static void __init igep2_get_revision(void)
90{
91 u8 ret;
92
93 if (machine_is_igep0030()) {
94 hwrev = IGEP3_BOARD_HWREV;
95 return;
96 }
97
98 omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT);
99
100 if (gpio_request_one(IGEP2_GPIO_LED1_RED, GPIOF_IN, "GPIO_HW0_REV")) {
101 pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n");
102 pr_err("IGEP2: Unknown Hardware Revision\n");
103 return;
104 }
105
106 ret = gpio_get_value(IGEP2_GPIO_LED1_RED);
107 if (ret == 0) {
108 pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n");
109 hwrev = IGEP2_BOARD_HWREV_C;
110 } else if (ret == 1) {
111 pr_info("IGEP2: Hardware Revision B/C (B compatible)\n");
112 hwrev = IGEP2_BOARD_HWREV_B;
113 } else {
114 pr_err("IGEP2: Unknown Hardware Revision\n");
115 hwrev = -1;
116 }
117
118 gpio_free(IGEP2_GPIO_LED1_RED);
119}
120
121#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
122 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) || \
123 defined(CONFIG_MTD_NAND_OMAP2) || \
124 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
125
126#define ONENAND_MAP 0x20000000
127
128/* NAND04GR4E1A ( x2 Flash built-in COMBO POP MEMORY )
129 * Since the device is equipped with two DataRAMs, and two-plane NAND
130 * Flash memory array, these two component enables simultaneous program
131 * of 4KiB. Plane1 has only even blocks such as block0, block2, block4
132 * while Plane2 has only odd blocks such as block1, block3, block5.
133 * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
134 */
135
136static struct mtd_partition igep_flash_partitions[] = {
137 {
138 .name = "X-Loader",
139 .offset = 0,
140 .size = 2 * (64*(2*2048))
141 },
142 {
143 .name = "U-Boot",
144 .offset = MTDPART_OFS_APPEND,
145 .size = 6 * (64*(2*2048)),
146 },
147 {
148 .name = "Environment",
149 .offset = MTDPART_OFS_APPEND,
150 .size = 2 * (64*(2*2048)),
151 },
152 {
153 .name = "Kernel",
154 .offset = MTDPART_OFS_APPEND,
155 .size = 12 * (64*(2*2048)),
156 },
157 {
158 .name = "File System",
159 .offset = MTDPART_OFS_APPEND,
160 .size = MTDPART_SIZ_FULL,
161 },
162};
163
164static inline u32 igep_get_sysboot_value(void)
165{
166 return omap_ctrl_readl(OMAP343X_CONTROL_STATUS) & IGEP_SYSBOOT_MASK;
167}
168
169static void __init igep_flash_init(void)
170{
171 u32 mux;
172 mux = igep_get_sysboot_value();
173
174 if (mux == IGEP_SYSBOOT_NAND) {
175 pr_info("IGEP: initializing NAND memory device\n");
176 board_nand_init(igep_flash_partitions,
177 ARRAY_SIZE(igep_flash_partitions),
178 0, NAND_BUSWIDTH_16, nand_default_timings);
179 } else if (mux == IGEP_SYSBOOT_ONENAND) {
180 pr_info("IGEP: initializing OneNAND memory device\n");
181 board_onenand_init(igep_flash_partitions,
182 ARRAY_SIZE(igep_flash_partitions), 0);
183 } else {
184 pr_err("IGEP: Flash: unsupported sysboot sequence found\n");
185 }
186}
187
188#else
189static void __init igep_flash_init(void) {}
190#endif
191
192#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
193
194#include <linux/smsc911x.h>
195#include "gpmc-smsc911x.h"
196
197static struct omap_smsc911x_platform_data smsc911x_cfg = {
198 .cs = IGEP2_SMSC911X_CS,
199 .gpio_irq = IGEP2_SMSC911X_GPIO,
200 .gpio_reset = -EINVAL,
201 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
202};
203
204static inline void __init igep2_init_smsc911x(void)
205{
206 gpmc_smsc911x_init(&smsc911x_cfg);
207}
208
209#else
210static inline void __init igep2_init_smsc911x(void) { }
211#endif
212
213static struct regulator_consumer_supply igep_vmmc1_supply[] = {
214 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
215};
216
217/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
218static struct regulator_init_data igep_vmmc1 = {
219 .constraints = {
220 .min_uV = 1850000,
221 .max_uV = 3150000,
222 .valid_modes_mask = REGULATOR_MODE_NORMAL
223 | REGULATOR_MODE_STANDBY,
224 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
225 | REGULATOR_CHANGE_MODE
226 | REGULATOR_CHANGE_STATUS,
227 },
228 .num_consumer_supplies = ARRAY_SIZE(igep_vmmc1_supply),
229 .consumer_supplies = igep_vmmc1_supply,
230};
231
232static struct regulator_consumer_supply igep_vio_supply[] = {
233 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
234};
235
236static struct regulator_init_data igep_vio = {
237 .constraints = {
238 .min_uV = 1800000,
239 .max_uV = 1800000,
240 .apply_uV = 1,
241 .valid_modes_mask = REGULATOR_MODE_NORMAL
242 | REGULATOR_MODE_STANDBY,
243 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
244 | REGULATOR_CHANGE_MODE
245 | REGULATOR_CHANGE_STATUS,
246 },
247 .num_consumer_supplies = ARRAY_SIZE(igep_vio_supply),
248 .consumer_supplies = igep_vio_supply,
249};
250
251static struct regulator_consumer_supply igep_vmmc2_supply[] = {
252 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
253};
254
255static struct regulator_init_data igep_vmmc2 = {
256 .constraints = {
257 .valid_modes_mask = REGULATOR_MODE_NORMAL,
258 .always_on = 1,
259 },
260 .num_consumer_supplies = ARRAY_SIZE(igep_vmmc2_supply),
261 .consumer_supplies = igep_vmmc2_supply,
262};
263
264static struct fixed_voltage_config igep_vwlan = {
265 .supply_name = "vwlan",
266 .microvolts = 3300000,
267 .gpio = -EINVAL,
268 .enabled_at_boot = 1,
269 .init_data = &igep_vmmc2,
270};
271
272static struct platform_device igep_vwlan_device = {
273 .name = "reg-fixed-voltage",
274 .id = 0,
275 .dev = {
276 .platform_data = &igep_vwlan,
277 },
278};
279
280static struct omap2_hsmmc_info mmc[] = {
281 {
282 .mmc = 1,
283 .caps = MMC_CAP_4_BIT_DATA,
284 .gpio_cd = -EINVAL,
285 .gpio_wp = -EINVAL,
286 .deferred = true,
287 },
288#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
289 {
290 .mmc = 2,
291 .caps = MMC_CAP_4_BIT_DATA,
292 .gpio_cd = -EINVAL,
293 .gpio_wp = -EINVAL,
294 },
295#endif
296 {} /* Terminator */
297};
298
299#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
300#include <linux/leds.h>
301
302static struct gpio_led igep_gpio_leds[] = {
303 [0] = {
304 .name = "omap3:red:user0",
305 .default_state = 0,
306 },
307 [1] = {
308 .name = "omap3:green:boot",
309 .default_state = 1,
310 },
311 [2] = {
312 .name = "omap3:red:user1",
313 .default_state = 0,
314 },
315 [3] = {
316 .name = "omap3:green:user1",
317 .default_state = 0,
318 .gpio = -EINVAL, /* gets replaced */
319 .active_low = 1,
320 },
321};
322
323static struct gpio_led_platform_data igep_led_pdata = {
324 .leds = igep_gpio_leds,
325 .num_leds = ARRAY_SIZE(igep_gpio_leds),
326};
327
328static struct platform_device igep_led_device = {
329 .name = "leds-gpio",
330 .id = -1,
331 .dev = {
332 .platform_data = &igep_led_pdata,
333 },
334};
335
336static void __init igep_leds_init(void)
337{
338 if (machine_is_igep0020()) {
339 igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED;
340 igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN;
341 igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED;
342 } else {
343 igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED;
344 igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN;
345 igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED;
346 }
347
348 platform_device_register(&igep_led_device);
349}
350
351#else
352static struct gpio igep_gpio_leds[] __initdata = {
353 { -EINVAL, GPIOF_OUT_INIT_LOW, "gpio-led:red:d0" },
354 { -EINVAL, GPIOF_OUT_INIT_LOW, "gpio-led:green:d0" },
355 { -EINVAL, GPIOF_OUT_INIT_LOW, "gpio-led:red:d1" },
356};
357
358static inline void igep_leds_init(void)
359{
360 int i;
361
362 if (machine_is_igep0020()) {
363 igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED;
364 igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN;
365 igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED;
366 } else {
367 igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED;
368 igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN;
369 igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED;
370 }
371
372 if (gpio_request_array(igep_gpio_leds, ARRAY_SIZE(igep_gpio_leds))) {
373 pr_warning("IGEP v2: Could not obtain leds gpios\n");
374 return;
375 }
376
377 for (i = 0; i < ARRAY_SIZE(igep_gpio_leds); i++)
378 gpio_export(igep_gpio_leds[i].gpio, 0);
379}
380#endif
381
382static struct gpio igep2_twl_gpios[] = {
383 { -EINVAL, GPIOF_IN, "GPIO_EHCI_NOC" },
384 { -EINVAL, GPIOF_OUT_INIT_LOW, "GPIO_USBH_CPEN" },
385};
386
387static int igep_twl_gpio_setup(struct device *dev,
388 unsigned gpio, unsigned ngpio)
389{
390 int ret;
391
392 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
393 mmc[0].gpio_cd = gpio + 0;
394 omap_hsmmc_late_init(mmc);
395
396 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
397#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
398 ret = gpio_request_one(gpio + TWL4030_GPIO_MAX + 1, GPIOF_OUT_INIT_HIGH,
399 "gpio-led:green:d1");
400 if (ret == 0)
401 gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
402 else
403 pr_warning("IGEP: Could not obtain gpio GPIO_LED1_GREEN\n");
404#else
405 igep_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
406#endif
407
408 if (machine_is_igep0030())
409 return 0;
410
411 /*
412 * REVISIT: need ehci-omap hooks for external VBUS
413 * power switch and overcurrent detect
414 */
415 igep2_twl_gpios[0].gpio = gpio + 1;
416
417 /* TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN (out, active low) */
418 igep2_twl_gpios[1].gpio = gpio + TWL4030_GPIO_MAX;
419
420 ret = gpio_request_array(igep2_twl_gpios, ARRAY_SIZE(igep2_twl_gpios));
421 if (ret < 0)
422 pr_err("IGEP2: Could not obtain gpio for USBH_CPEN");
423
424 return 0;
425};
426
427static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
428 .use_leds = true,
429 .setup = igep_twl_gpio_setup,
430};
431
432static struct connector_dvi_platform_data omap3stalker_dvi_connector_pdata = {
433 .name = "dvi",
434 .source = "tfp410.0",
435 .i2c_bus_num = 3,
436};
437
438static struct platform_device omap3stalker_dvi_connector_device = {
439 .name = "connector-dvi",
440 .id = 0,
441 .dev.platform_data = &omap3stalker_dvi_connector_pdata,
442};
443
444static struct encoder_tfp410_platform_data omap3stalker_tfp410_pdata = {
445 .name = "tfp410.0",
446 .source = "dpi.0",
447 .data_lines = 24,
448 .power_down_gpio = IGEP2_GPIO_DVI_PUP,
449};
450
451static struct platform_device omap3stalker_tfp410_device = {
452 .name = "tfp410",
453 .id = 0,
454 .dev.platform_data = &omap3stalker_tfp410_pdata,
455};
456
457static struct omap_dss_board_info igep2_dss_data = {
458 .default_display_name = "dvi",
459};
460
461static struct platform_device *igep_devices[] __initdata = {
462 &igep_vwlan_device,
463 &omap3stalker_tfp410_device,
464 &omap3stalker_dvi_connector_device,
465};
466
467static int igep2_keymap[] = {
468 KEY(0, 0, KEY_LEFT),
469 KEY(0, 1, KEY_RIGHT),
470 KEY(0, 2, KEY_A),
471 KEY(0, 3, KEY_B),
472 KEY(1, 0, KEY_DOWN),
473 KEY(1, 1, KEY_UP),
474 KEY(1, 2, KEY_E),
475 KEY(1, 3, KEY_F),
476 KEY(2, 0, KEY_ENTER),
477 KEY(2, 1, KEY_I),
478 KEY(2, 2, KEY_J),
479 KEY(2, 3, KEY_K),
480 KEY(3, 0, KEY_M),
481 KEY(3, 1, KEY_N),
482 KEY(3, 2, KEY_O),
483 KEY(3, 3, KEY_P)
484};
485
486static struct matrix_keymap_data igep2_keymap_data = {
487 .keymap = igep2_keymap,
488 .keymap_size = ARRAY_SIZE(igep2_keymap),
489};
490
491static struct twl4030_keypad_data igep2_keypad_pdata = {
492 .keymap_data = &igep2_keymap_data,
493 .rows = 4,
494 .cols = 4,
495 .rep = 1,
496};
497
498static struct twl4030_platform_data igep_twldata = {
499 /* platform_data for children goes here */
500 .gpio = &igep_twl4030_gpio_pdata,
501 .vmmc1 = &igep_vmmc1,
502 .vio = &igep_vio,
503};
504
505static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = {
506 {
507 I2C_BOARD_INFO("eeprom", 0x50),
508 },
509};
510
511static void __init igep_i2c_init(void)
512{
513 int ret;
514
515 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB,
516 TWL_COMMON_REGULATOR_VPLL2);
517 igep_twldata.vpll2->constraints.apply_uV = true;
518 igep_twldata.vpll2->constraints.name = "VDVI";
519
520 if (machine_is_igep0020()) {
521 /*
522 * Bus 3 is attached to the DVI port where devices like the
523 * pico DLP projector don't work reliably with 400kHz
524 */
525 ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo,
526 ARRAY_SIZE(igep2_i2c3_boardinfo));
527 if (ret)
528 pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
529
530 igep_twldata.keypad = &igep2_keypad_pdata;
531 /* Get common pmic data */
532 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 0);
533 }
534
535 omap3_pmic_init("twl4030", &igep_twldata);
536}
537
538static struct usbhs_phy_data igep2_phy_data[] __initdata = {
539 {
540 .port = 1,
541 .reset_gpio = IGEP2_GPIO_USBH_NRESET,
542 .vcc_gpio = -EINVAL,
543 },
544};
545
546static struct usbhs_phy_data igep3_phy_data[] __initdata = {
547 {
548 .port = 2,
549 .reset_gpio = IGEP3_GPIO_USBH_NRESET,
550 .vcc_gpio = -EINVAL,
551 },
552};
553
554static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
555 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
556};
557
558static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
559 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
560};
561
562#ifdef CONFIG_OMAP_MUX
563static struct omap_board_mux board_mux[] __initdata = {
564 /* Display Sub System */
565 OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
566 OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
567 OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
568 OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
569 OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
570 OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
571 OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
572 OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
573 OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
574 OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
575 OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
576 OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
577 OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
578 OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
579 OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
580 OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
581 OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
582 OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
583 OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
584 OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
585 OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
586 OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
587 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
588 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
589 OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
590 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
591 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
592 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
593 /* TFP410 PanelBus DVI Transmitte (GPIO_170) */
594 OMAP3_MUX(HDQ_SIO, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
595 /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
596 OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
597 { .reg_offset = OMAP_MUX_TERMINATOR },
598};
599#endif
600
601#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
602static struct gpio igep_wlan_bt_gpios[] __initdata = {
603 { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NPD" },
604 { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NRESET" },
605 { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_BT_NRESET" },
606};
607
608static void __init igep_wlan_bt_init(void)
609{
610 int err;
611
612 /* GPIO's for WLAN-BT combo depends on hardware revision */
613 if (hwrev == IGEP2_BOARD_HWREV_B) {
614 igep_wlan_bt_gpios[0].gpio = IGEP2_RB_GPIO_WIFI_NPD;
615 igep_wlan_bt_gpios[1].gpio = IGEP2_RB_GPIO_WIFI_NRESET;
616 igep_wlan_bt_gpios[2].gpio = IGEP2_RB_GPIO_BT_NRESET;
617 } else if (hwrev == IGEP2_BOARD_HWREV_C || machine_is_igep0030()) {
618 igep_wlan_bt_gpios[0].gpio = IGEP2_RC_GPIO_WIFI_NPD;
619 igep_wlan_bt_gpios[1].gpio = IGEP2_RC_GPIO_WIFI_NRESET;
620 igep_wlan_bt_gpios[2].gpio = IGEP2_RC_GPIO_BT_NRESET;
621 } else
622 return;
623
624 /* Make sure that the GPIO pins are muxed correctly */
625 omap_mux_init_gpio(igep_wlan_bt_gpios[0].gpio, OMAP_PIN_OUTPUT);
626 omap_mux_init_gpio(igep_wlan_bt_gpios[1].gpio, OMAP_PIN_OUTPUT);
627 omap_mux_init_gpio(igep_wlan_bt_gpios[2].gpio, OMAP_PIN_OUTPUT);
628
629 err = gpio_request_array(igep_wlan_bt_gpios,
630 ARRAY_SIZE(igep_wlan_bt_gpios));
631 if (err) {
632 pr_warning("IGEP2: Could not obtain WIFI/BT gpios\n");
633 return;
634 }
635
636 gpio_export(igep_wlan_bt_gpios[0].gpio, 0);
637 gpio_export(igep_wlan_bt_gpios[1].gpio, 0);
638 gpio_export(igep_wlan_bt_gpios[2].gpio, 0);
639
640 gpio_set_value(igep_wlan_bt_gpios[1].gpio, 0);
641 udelay(10);
642 gpio_set_value(igep_wlan_bt_gpios[1].gpio, 1);
643
644}
645#else
646static inline void __init igep_wlan_bt_init(void) { }
647#endif
648
649static struct regulator_consumer_supply dummy_supplies[] = {
650 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
651 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
652};
653
654static void __init igep_init(void)
655{
656 regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
657 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
658
659 /* Get IGEP2 hardware revision */
660 igep2_get_revision();
661
662 omap_hsmmc_init(mmc);
663
664 /* Register I2C busses and drivers */
665 igep_i2c_init();
666 platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
667 omap_serial_init();
668 omap_sdrc_init(m65kxxxxam_sdrc_params,
669 m65kxxxxam_sdrc_params);
670 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
671 usb_musb_init(NULL);
672
673 igep_flash_init();
674 igep_leds_init();
675 omap_twl4030_audio_init("igep2", NULL);
676
677 /*
678 * WLAN-BT combo module from MuRata which has a Marvell WLAN
679 * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
680 */
681 igep_wlan_bt_init();
682
683 if (machine_is_igep0020()) {
684 omap_display_init(&igep2_dss_data);
685 igep2_init_smsc911x();
686 usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data));
687 usbhs_init(&igep2_usbhs_bdata);
688 } else {
689 usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data));
690 usbhs_init(&igep3_usbhs_bdata);
691 }
692}
693
694MACHINE_START(IGEP0020, "IGEP v2 board")
695 .atag_offset = 0x100,
696 .reserve = omap_reserve,
697 .map_io = omap3_map_io,
698 .init_early = omap35xx_init_early,
699 .init_irq = omap3_init_irq,
700 .handle_irq = omap3_intc_handle_irq,
701 .init_machine = igep_init,
702 .init_late = omap35xx_init_late,
703 .init_time = omap3_sync32k_timer_init,
704 .restart = omap3xxx_restart,
705MACHINE_END
706
707MACHINE_START(IGEP0030, "IGEP OMAP3 module")
708 .atag_offset = 0x100,
709 .reserve = omap_reserve,
710 .map_io = omap3_map_io,
711 .init_early = omap35xx_init_early,
712 .init_irq = omap3_init_irq,
713 .handle_irq = omap3_intc_handle_irq,
714 .init_machine = igep_init,
715 .init_late = omap35xx_init_late,
716 .init_time = omap3_sync32k_timer_init,
717 .restart = omap3xxx_restart,
718MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index dd8da2c5399f..4ec8d82b0492 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -36,7 +36,6 @@
36#include <asm/mach/map.h> 36#include <asm/mach/map.h>
37 37
38#include "common.h" 38#include "common.h"
39#include "board-zoom.h"
40#include "gpmc.h" 39#include "gpmc.h"
41#include "gpmc-smsc911x.h" 40#include "gpmc-smsc911x.h"
42 41
@@ -406,7 +405,7 @@ static void __init omap_ldp_init(void)
406 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); 405 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
407 usb_musb_init(NULL); 406 usb_musb_init(NULL);
408 board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions), 407 board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
409 ZOOM_NAND_CS, 0, nand_default_timings); 408 0, 0, nand_default_timings);
410 409
411 omap_hsmmc_init(mmc); 410 omap_hsmmc_init(mmc);
412 ldp_display_init(); 411 ldp_display_init();
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
deleted file mode 100644
index 18143873346c..000000000000
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ /dev/null
@@ -1,756 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-omap3evm.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/gpio.h>
22#include <linux/input.h>
23#include <linux/input/matrix_keypad.h>
24#include <linux/leds.h>
25#include <linux/interrupt.h>
26
27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h>
30
31#include <linux/spi/spi.h>
32#include <linux/spi/ads7846.h>
33#include <linux/i2c/twl.h>
34#include <linux/usb/otg.h>
35#include <linux/usb/musb.h>
36#include <linux/usb/usb_phy_gen_xceiv.h>
37#include <linux/smsc911x.h>
38
39#include <linux/wl12xx.h>
40#include <linux/regulator/fixed.h>
41#include <linux/regulator/machine.h>
42#include <linux/mmc/host.h>
43#include <linux/export.h>
44#include <linux/usb/phy.h>
45
46#include <asm/mach-types.h>
47#include <asm/mach/arch.h>
48#include <asm/mach/map.h>
49
50#include <linux/platform_data/mtd-nand-omap2.h>
51#include "common.h"
52#include <linux/platform_data/spi-omap2-mcspi.h>
53#include <video/omapdss.h>
54#include <video/omap-panel-data.h>
55
56#include "soc.h"
57#include "mux.h"
58#include "sdram-micron-mt46h32m32lf-6.h"
59#include "hsmmc.h"
60#include "common-board-devices.h"
61#include "board-flash.h"
62
63#define NAND_CS 0
64
65#define OMAP3_EVM_TS_GPIO 175
66#define OMAP3_EVM_EHCI_VBUS 22
67#define OMAP3_EVM_EHCI_SELECT 61
68
69#define OMAP3EVM_ETHR_START 0x2c000000
70#define OMAP3EVM_ETHR_SIZE 1024
71#define OMAP3EVM_ETHR_ID_REV 0x50
72#define OMAP3EVM_ETHR_GPIO_IRQ 176
73#define OMAP3EVM_SMSC911X_CS 5
74/*
75 * Eth Reset signal
76 * 64 = Generation 1 (<=RevD)
77 * 7 = Generation 2 (>=RevE)
78 */
79#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
80#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
81
82/*
83 * OMAP35x EVM revision
84 * Run time detection of EVM revision is done by reading Ethernet
85 * PHY ID -
86 * GEN_1 = 0x01150000
87 * GEN_2 = 0x92200000
88 */
89enum {
90 OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
91 OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
92};
93
94static u8 omap3_evm_version;
95
96static u8 get_omap3_evm_rev(void)
97{
98 return omap3_evm_version;
99}
100
101static void __init omap3_evm_get_revision(void)
102{
103 void __iomem *ioaddr;
104 unsigned int smsc_id;
105
106 /* Ethernet PHY ID is stored at ID_REV register */
107 ioaddr = ioremap_nocache(OMAP3EVM_ETHR_START, SZ_1K);
108 if (!ioaddr)
109 return;
110 smsc_id = readl(ioaddr + OMAP3EVM_ETHR_ID_REV) & 0xFFFF0000;
111 iounmap(ioaddr);
112
113 switch (smsc_id) {
114 /*SMSC9115 chipset*/
115 case 0x01150000:
116 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
117 break;
118 /*SMSC 9220 chipset*/
119 case 0x92200000:
120 default:
121 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
122 }
123}
124
125#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
126#include "gpmc-smsc911x.h"
127
128static struct omap_smsc911x_platform_data smsc911x_cfg = {
129 .cs = OMAP3EVM_SMSC911X_CS,
130 .gpio_irq = OMAP3EVM_ETHR_GPIO_IRQ,
131 .gpio_reset = -EINVAL,
132 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
133};
134
135static inline void __init omap3evm_init_smsc911x(void)
136{
137 /* Configure ethernet controller reset gpio */
138 if (cpu_is_omap3430()) {
139 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
140 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
141 else
142 smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
143 }
144
145 gpmc_smsc911x_init(&smsc911x_cfg);
146}
147
148#else
149static inline void __init omap3evm_init_smsc911x(void) { return; }
150#endif
151
152/*
153 * OMAP3EVM LCD Panel control signals
154 */
155#define OMAP3EVM_LCD_PANEL_LR 2
156#define OMAP3EVM_LCD_PANEL_UD 3
157#define OMAP3EVM_LCD_PANEL_INI 152
158#define OMAP3EVM_LCD_PANEL_QVGA 154
159#define OMAP3EVM_LCD_PANEL_RESB 155
160
161#define OMAP3EVM_LCD_PANEL_ENVDD 153
162#define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
163
164/*
165 * OMAP3EVM DVI control signals
166 */
167#define OMAP3EVM_DVI_PANEL_EN_GPIO 199
168
169#ifdef CONFIG_BROKEN
170static void __init omap3_evm_display_init(void)
171{
172 int r;
173
174 r = gpio_request_one(OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW,
175 "lcd_panel_envdd");
176 if (r)
177 pr_err("failed to get lcd_panel_envdd GPIO\n");
178
179 r = gpio_request_one(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO,
180 GPIOF_OUT_INIT_LOW, "lcd_panel_bklight");
181 if (r)
182 pr_err("failed to get lcd_panel_bklight GPIO\n");
183
184 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
185 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
186 else
187 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
188}
189#endif
190
191static struct panel_sharp_ls037v7dw01_platform_data omap3_evm_lcd_pdata = {
192 .name = "lcd",
193 .source = "dpi.0",
194
195 .data_lines = 18,
196
197 .resb_gpio = OMAP3EVM_LCD_PANEL_RESB,
198 .ini_gpio = OMAP3EVM_LCD_PANEL_INI,
199 .mo_gpio = OMAP3EVM_LCD_PANEL_QVGA,
200 .lr_gpio = OMAP3EVM_LCD_PANEL_LR,
201 .ud_gpio = OMAP3EVM_LCD_PANEL_UD,
202};
203
204static struct platform_device omap3_evm_lcd_device = {
205 .name = "panel-sharp-ls037v7dw01",
206 .id = 0,
207 .dev.platform_data = &omap3_evm_lcd_pdata,
208};
209
210static struct connector_dvi_platform_data omap3_evm_dvi_connector_pdata = {
211 .name = "dvi",
212 .source = "tfp410.0",
213 .i2c_bus_num = -1,
214};
215
216static struct platform_device omap3_evm_dvi_connector_device = {
217 .name = "connector-dvi",
218 .id = 0,
219 .dev.platform_data = &omap3_evm_dvi_connector_pdata,
220};
221
222static struct encoder_tfp410_platform_data omap3_evm_tfp410_pdata = {
223 .name = "tfp410.0",
224 .source = "dpi.0",
225 .data_lines = 24,
226 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
227};
228
229static struct platform_device omap3_evm_tfp410_device = {
230 .name = "tfp410",
231 .id = 0,
232 .dev.platform_data = &omap3_evm_tfp410_pdata,
233};
234
235static struct connector_atv_platform_data omap3_evm_tv_pdata = {
236 .name = "tv",
237 .source = "venc.0",
238 .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
239 .invert_polarity = false,
240};
241
242static struct platform_device omap3_evm_tv_connector_device = {
243 .name = "connector-analog-tv",
244 .id = 0,
245 .dev.platform_data = &omap3_evm_tv_pdata,
246};
247
248static struct omap_dss_board_info omap3_evm_dss_data = {
249 .default_display_name = "lcd",
250};
251
252static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
253 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
254};
255
256static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
257 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
258};
259
260/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
261static struct regulator_init_data omap3evm_vmmc1 = {
262 .constraints = {
263 .min_uV = 1850000,
264 .max_uV = 3150000,
265 .valid_modes_mask = REGULATOR_MODE_NORMAL
266 | REGULATOR_MODE_STANDBY,
267 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
268 | REGULATOR_CHANGE_MODE
269 | REGULATOR_CHANGE_STATUS,
270 },
271 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
272 .consumer_supplies = omap3evm_vmmc1_supply,
273};
274
275/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
276static struct regulator_init_data omap3evm_vsim = {
277 .constraints = {
278 .min_uV = 1800000,
279 .max_uV = 3000000,
280 .valid_modes_mask = REGULATOR_MODE_NORMAL
281 | REGULATOR_MODE_STANDBY,
282 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
283 | REGULATOR_CHANGE_MODE
284 | REGULATOR_CHANGE_STATUS,
285 },
286 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
287 .consumer_supplies = omap3evm_vsim_supply,
288};
289
290static struct omap2_hsmmc_info mmc[] = {
291 {
292 .mmc = 1,
293 .caps = MMC_CAP_4_BIT_DATA,
294 .gpio_cd = -EINVAL,
295 .gpio_wp = 63,
296 .deferred = true,
297 },
298#ifdef CONFIG_WILINK_PLATFORM_DATA
299 {
300 .name = "wl1271",
301 .mmc = 2,
302 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
303 .gpio_wp = -EINVAL,
304 .gpio_cd = -EINVAL,
305 .nonremovable = true,
306 },
307#endif
308 {} /* Terminator */
309};
310
311static struct gpio_led gpio_leds[] = {
312 {
313 .name = "omap3evm::ledb",
314 /* normally not visible (board underside) */
315 .default_trigger = "default-on",
316 .gpio = -EINVAL, /* gets replaced */
317 .active_low = true,
318 },
319};
320
321static struct gpio_led_platform_data gpio_led_info = {
322 .leds = gpio_leds,
323 .num_leds = ARRAY_SIZE(gpio_leds),
324};
325
326static struct platform_device leds_gpio = {
327 .name = "leds-gpio",
328 .id = -1,
329 .dev = {
330 .platform_data = &gpio_led_info,
331 },
332};
333
334
335static int omap3evm_twl_gpio_setup(struct device *dev,
336 unsigned gpio, unsigned ngpio)
337{
338 int r, lcd_bl_en;
339
340 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
341 mmc[0].gpio_cd = gpio + 0;
342 omap_hsmmc_late_init(mmc);
343
344 /*
345 * Most GPIOs are for USB OTG. Some are mostly sent to
346 * the P2 connector; notably LEDA for the LCD backlight.
347 */
348
349 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
350 lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ?
351 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
352 r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL");
353 if (r)
354 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
355
356 /* gpio + 7 == DVI Enable */
357 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
358
359 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
360 gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
361
362 platform_device_register(&leds_gpio);
363
364 /* Enable VBUS switch by setting TWL4030.GPIO2DIR as output
365 * for starting USB tranceiver
366 */
367#ifdef CONFIG_TWL4030_CORE
368 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
369 u8 val;
370
371 twl_i2c_read_u8(TWL4030_MODULE_GPIO, &val, REG_GPIODATADIR1);
372 val |= 0x04; /* TWL4030.GPIO2DIR BIT at GPIODATADIR1(0x9B) */
373 twl_i2c_write_u8(TWL4030_MODULE_GPIO, val, REG_GPIODATADIR1);
374 }
375#endif
376
377 return 0;
378}
379
380static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
381 .use_leds = true,
382 .setup = omap3evm_twl_gpio_setup,
383};
384
385static uint32_t board_keymap[] = {
386 KEY(0, 0, KEY_LEFT),
387 KEY(0, 1, KEY_DOWN),
388 KEY(0, 2, KEY_ENTER),
389 KEY(0, 3, KEY_M),
390
391 KEY(1, 0, KEY_RIGHT),
392 KEY(1, 1, KEY_UP),
393 KEY(1, 2, KEY_I),
394 KEY(1, 3, KEY_N),
395
396 KEY(2, 0, KEY_A),
397 KEY(2, 1, KEY_E),
398 KEY(2, 2, KEY_J),
399 KEY(2, 3, KEY_O),
400
401 KEY(3, 0, KEY_B),
402 KEY(3, 1, KEY_F),
403 KEY(3, 2, KEY_K),
404 KEY(3, 3, KEY_P)
405};
406
407static struct matrix_keymap_data board_map_data = {
408 .keymap = board_keymap,
409 .keymap_size = ARRAY_SIZE(board_keymap),
410};
411
412static struct twl4030_keypad_data omap3evm_kp_data = {
413 .keymap_data = &board_map_data,
414 .rows = 4,
415 .cols = 4,
416 .rep = 1,
417};
418
419/* ads7846 on SPI */
420static struct regulator_consumer_supply omap3evm_vio_supply[] = {
421 REGULATOR_SUPPLY("vcc", "spi1.0"),
422};
423
424/* VIO for ads7846 */
425static struct regulator_init_data omap3evm_vio = {
426 .constraints = {
427 .min_uV = 1800000,
428 .max_uV = 1800000,
429 .apply_uV = true,
430 .valid_modes_mask = REGULATOR_MODE_NORMAL
431 | REGULATOR_MODE_STANDBY,
432 .valid_ops_mask = REGULATOR_CHANGE_MODE
433 | REGULATOR_CHANGE_STATUS,
434 },
435 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
436 .consumer_supplies = omap3evm_vio_supply,
437};
438
439#ifdef CONFIG_WILINK_PLATFORM_DATA
440
441#define OMAP3EVM_WLAN_PMENA_GPIO (150)
442#define OMAP3EVM_WLAN_IRQ_GPIO (149)
443
444static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
445 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
446};
447
448/* VMMC2 for driving the WL12xx module */
449static struct regulator_init_data omap3evm_vmmc2 = {
450 .constraints = {
451 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
452 },
453 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
454 .consumer_supplies = omap3evm_vmmc2_supply,
455};
456
457static struct fixed_voltage_config omap3evm_vwlan = {
458 .supply_name = "vwl1271",
459 .microvolts = 1800000, /* 1.80V */
460 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
461 .startup_delay = 70000, /* 70ms */
462 .enable_high = 1,
463 .enabled_at_boot = 0,
464 .init_data = &omap3evm_vmmc2,
465};
466
467static struct platform_device omap3evm_wlan_regulator = {
468 .name = "reg-fixed-voltage",
469 .id = 1,
470 .dev = {
471 .platform_data = &omap3evm_vwlan,
472 },
473};
474
475struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
476 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
477};
478#endif
479
480/* VAUX2 for USB */
481static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
482 REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */
483 REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */
484 REGULATOR_SUPPLY("vcc", "usb_phy_gen_xceiv.2"), /* hsusb port 2 */
485 REGULATOR_SUPPLY("vaux2", NULL),
486};
487
488static struct regulator_init_data omap3evm_vaux2 = {
489 .constraints = {
490 .min_uV = 2800000,
491 .max_uV = 2800000,
492 .apply_uV = true,
493 .valid_modes_mask = REGULATOR_MODE_NORMAL
494 | REGULATOR_MODE_STANDBY,
495 .valid_ops_mask = REGULATOR_CHANGE_MODE
496 | REGULATOR_CHANGE_STATUS,
497 },
498 .num_consumer_supplies = ARRAY_SIZE(omap3evm_vaux2_supplies),
499 .consumer_supplies = omap3evm_vaux2_supplies,
500};
501
502static struct twl4030_platform_data omap3evm_twldata = {
503 /* platform_data for children goes here */
504 .keypad = &omap3evm_kp_data,
505 .gpio = &omap3evm_gpio_data,
506 .vio = &omap3evm_vio,
507 .vmmc1 = &omap3evm_vmmc1,
508 .vsim = &omap3evm_vsim,
509};
510
511static int __init omap3_evm_i2c_init(void)
512{
513 omap3_pmic_get_config(&omap3evm_twldata,
514 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
515 TWL_COMMON_PDATA_AUDIO,
516 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
517
518 omap3evm_twldata.vdac->constraints.apply_uV = true;
519 omap3evm_twldata.vpll2->constraints.apply_uV = true;
520
521 omap3_pmic_init("twl4030", &omap3evm_twldata);
522 omap_register_i2c_bus(2, 400, NULL, 0);
523 omap_register_i2c_bus(3, 400, NULL, 0);
524 return 0;
525}
526
527static struct usbhs_phy_data phy_data[] __initdata = {
528 {
529 .port = 2,
530 .reset_gpio = -1, /* set at runtime */
531 .vcc_gpio = -EINVAL,
532 },
533};
534
535static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
536 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
537};
538
539#ifdef CONFIG_OMAP_MUX
540static struct omap_board_mux omap35x_board_mux[] __initdata = {
541 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
542 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
543 OMAP_PIN_OFF_WAKEUPENABLE),
544 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
545 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
546 OMAP_PIN_OFF_WAKEUPENABLE),
547 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
548 OMAP_PIN_OFF_NONE),
549 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
550 OMAP_PIN_OFF_NONE),
551#ifdef CONFIG_WILINK_PLATFORM_DATA
552 /* WLAN IRQ - GPIO 149 */
553 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
554
555 /* WLAN POWER ENABLE - GPIO 150 */
556 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
557
558 /* MMC2 SDIO pin muxes for WL12xx */
559 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
560 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
561 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
562 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
563 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
564 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
565#endif
566 { .reg_offset = OMAP_MUX_TERMINATOR },
567};
568
569static struct omap_board_mux omap36x_board_mux[] __initdata = {
570 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
571 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
572 OMAP_PIN_OFF_WAKEUPENABLE),
573 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
574 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
575 OMAP_PIN_OFF_WAKEUPENABLE),
576 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
577 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
578 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
579 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
580 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
581 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
582 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
583 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
584 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
585 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
586 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
587 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
588 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
589#ifdef CONFIG_WILINK_PLATFORM_DATA
590 /* WLAN IRQ - GPIO 149 */
591 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
592
593 /* WLAN POWER ENABLE - GPIO 150 */
594 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
595
596 /* MMC2 SDIO pin muxes for WL12xx */
597 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
598 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
599 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
600 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
601 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
602 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
603#endif
604
605 { .reg_offset = OMAP_MUX_TERMINATOR },
606};
607#else
608#define omap35x_board_mux NULL
609#define omap36x_board_mux NULL
610#endif
611
612static struct omap_musb_board_data musb_board_data = {
613 .interface_type = MUSB_INTERFACE_ULPI,
614 .mode = MUSB_OTG,
615 .power = 100,
616};
617
618static struct gpio omap3_evm_ehci_gpios[] __initdata = {
619 { OMAP3_EVM_EHCI_VBUS, GPIOF_OUT_INIT_HIGH, "enable EHCI VBUS" },
620 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
621};
622
623static void __init omap3_evm_wl12xx_init(void)
624{
625#ifdef CONFIG_WILINK_PLATFORM_DATA
626 int ret;
627
628 /* WL12xx WLAN Init */
629 omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
630 ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
631 if (ret)
632 pr_err("error setting wl12xx data: %d\n", ret);
633 ret = platform_device_register(&omap3evm_wlan_regulator);
634 if (ret)
635 pr_err("error registering wl12xx device: %d\n", ret);
636#endif
637}
638
639static struct regulator_consumer_supply dummy_supplies[] = {
640 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
641 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
642};
643
644static struct mtd_partition omap3evm_nand_partitions[] = {
645 /* All the partition sizes are listed in terms of NAND block size */
646 {
647 .name = "X-Loader",
648 .offset = 0,
649 .size = 4*(SZ_128K),
650 .mask_flags = MTD_WRITEABLE
651 },
652 {
653 .name = "U-Boot",
654 .offset = MTDPART_OFS_APPEND,
655 .size = 14*(SZ_128K),
656 .mask_flags = MTD_WRITEABLE
657 },
658 {
659 .name = "U-Boot Env",
660 .offset = MTDPART_OFS_APPEND,
661 .size = 2*(SZ_128K)
662 },
663 {
664 .name = "Kernel",
665 .offset = MTDPART_OFS_APPEND,
666 .size = 40*(SZ_128K)
667 },
668 {
669 .name = "File system",
670 .size = MTDPART_SIZ_FULL,
671 .offset = MTDPART_OFS_APPEND,
672 },
673};
674
675static void __init omap3_evm_init(void)
676{
677 struct omap_board_mux *obm;
678
679 omap3_evm_get_revision();
680 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
681
682 obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
683 omap3_mux_init(obm, OMAP_PACKAGE_CBB);
684
685 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
686 omap_hsmmc_init(mmc);
687
688 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
689 omap3evm_twldata.vaux2 = &omap3evm_vaux2;
690
691 omap3_evm_i2c_init();
692
693 omap_display_init(&omap3_evm_dss_data);
694 platform_device_register(&omap3_evm_lcd_device);
695 platform_device_register(&omap3_evm_tfp410_device);
696 platform_device_register(&omap3_evm_dvi_connector_device);
697 platform_device_register(&omap3_evm_tv_connector_device);
698
699 omap_serial_init();
700 omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
701
702 /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
703 usb_nop_xceiv_register();
704
705 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
706 /* enable EHCI VBUS using GPIO22 */
707 omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
708 /* Select EHCI port on main board */
709 omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
710 OMAP_PIN_INPUT_PULLUP);
711 gpio_request_array(omap3_evm_ehci_gpios,
712 ARRAY_SIZE(omap3_evm_ehci_gpios));
713
714 /* setup EHCI phy reset config */
715 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
716 phy_data[0].reset_gpio = 21;
717
718 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
719 musb_board_data.power = 500;
720 musb_board_data.extvbus = 1;
721 } else {
722 /* setup EHCI phy reset on MDC */
723 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
724 phy_data[0].reset_gpio = 135;
725 }
726 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
727 usb_musb_init(&musb_board_data);
728
729 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
730 usbhs_init(&usbhs_bdata);
731 board_nand_init(omap3evm_nand_partitions,
732 ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
733 NAND_BUSWIDTH_16, NULL);
734
735 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
736 omap3evm_init_smsc911x();
737#ifdef CONFIG_BROKEN
738 omap3_evm_display_init();
739#endif
740 omap3_evm_wl12xx_init();
741 omap_twl4030_audio_init("omap3evm", NULL);
742}
743
744MACHINE_START(OMAP3EVM, "OMAP3 EVM")
745 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
746 .atag_offset = 0x100,
747 .reserve = omap_reserve,
748 .map_io = omap3_map_io,
749 .init_early = omap35xx_init_early,
750 .init_irq = omap3_init_irq,
751 .handle_irq = omap3_intc_handle_irq,
752 .init_machine = omap3_evm_init,
753 .init_late = omap35xx_init_late,
754 .init_time = omap3_sync32k_timer_init,
755 .restart = omap3xxx_restart,
756MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
deleted file mode 100644
index 345e8c4b8731..000000000000
--- a/arch/arm/mach-omap2/board-rm680.c
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * Board support file for Nokia N950 (RM-680) / N9 (RM-696).
3 *
4 * Copyright (C) 2010 Nokia
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/io.h>
12#include <linux/i2c.h>
13#include <linux/gpio.h>
14#include <linux/init.h>
15#include <linux/i2c/twl.h>
16#include <linux/platform_device.h>
17#include <linux/regulator/fixed.h>
18#include <linux/regulator/machine.h>
19#include <linux/regulator/consumer.h>
20#include <linux/platform_data/mtd-onenand-omap2.h>
21#include <linux/usb/phy.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach-types.h>
25
26#include "common.h"
27#include "mux.h"
28#include "gpmc.h"
29#include "mmc.h"
30#include "hsmmc.h"
31#include "sdram-nokia.h"
32#include "common-board-devices.h"
33#include "gpmc-onenand.h"
34
35static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
36 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
37};
38
39/* Fixed regulator for internal eMMC */
40static struct regulator_init_data rm680_vemmc = {
41 .constraints = {
42 .name = "rm680_vemmc",
43 .valid_modes_mask = REGULATOR_MODE_NORMAL
44 | REGULATOR_MODE_STANDBY,
45 .valid_ops_mask = REGULATOR_CHANGE_STATUS
46 | REGULATOR_CHANGE_MODE,
47 },
48 .num_consumer_supplies = ARRAY_SIZE(rm680_vemmc_consumers),
49 .consumer_supplies = rm680_vemmc_consumers,
50};
51
52static struct fixed_voltage_config rm680_vemmc_config = {
53 .supply_name = "VEMMC",
54 .microvolts = 2900000,
55 .gpio = 157,
56 .startup_delay = 150,
57 .enable_high = 1,
58 .init_data = &rm680_vemmc,
59};
60
61static struct platform_device rm680_vemmc_device = {
62 .name = "reg-fixed-voltage",
63 .dev = {
64 .platform_data = &rm680_vemmc_config,
65 },
66};
67
68static struct platform_device *rm680_peripherals_devices[] __initdata = {
69 &rm680_vemmc_device,
70};
71
72/* TWL */
73static struct twl4030_gpio_platform_data rm680_gpio_data = {
74 .pullups = BIT(0),
75 .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15),
76};
77
78static struct twl4030_platform_data rm680_twl_data = {
79 .gpio = &rm680_gpio_data,
80 /* add rest of the children here */
81};
82
83static void __init rm680_i2c_init(void)
84{
85 omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
86 omap_pmic_init(1, 2900, "twl5031", 7 + OMAP_INTC_START, &rm680_twl_data);
87 omap_register_i2c_bus(2, 400, NULL, 0);
88 omap_register_i2c_bus(3, 400, NULL, 0);
89}
90
91#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
92 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
93static struct omap_onenand_platform_data board_onenand_data[] = {
94 {
95 .gpio_irq = 65,
96 .flags = ONENAND_SYNC_READWRITE,
97 }
98};
99#endif
100
101/* eMMC */
102static struct omap2_hsmmc_info mmc[] __initdata = {
103 {
104 .name = "internal",
105 .mmc = 2,
106 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED,
107 .gpio_cd = -EINVAL,
108 .gpio_wp = -EINVAL,
109 },
110 { /* Terminator */ }
111};
112
113static void __init rm680_peripherals_init(void)
114{
115 platform_add_devices(rm680_peripherals_devices,
116 ARRAY_SIZE(rm680_peripherals_devices));
117 rm680_i2c_init();
118 gpmc_onenand_init(board_onenand_data);
119 omap_hsmmc_init(mmc);
120}
121
122#ifdef CONFIG_OMAP_MUX
123static struct omap_board_mux board_mux[] __initdata = {
124 { .reg_offset = OMAP_MUX_TERMINATOR },
125};
126#endif
127
128static void __init rm680_init(void)
129{
130 struct omap_sdrc_params *sdrc_params;
131
132 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
133 omap_serial_init();
134
135 sdrc_params = nokia_get_sdram_timings();
136 omap_sdrc_init(sdrc_params, sdrc_params);
137
138 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
139 usb_musb_init(NULL);
140 rm680_peripherals_init();
141}
142
143MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
144 .atag_offset = 0x100,
145 .reserve = omap_reserve,
146 .map_io = omap3_map_io,
147 .init_early = omap3630_init_early,
148 .init_irq = omap3_init_irq,
149 .handle_irq = omap3_intc_handle_irq,
150 .init_machine = rm680_init,
151 .init_late = omap3630_init_late,
152 .init_time = omap3_sync32k_timer_init,
153 .restart = omap3xxx_restart,
154MACHINE_END
155
156MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
157 .atag_offset = 0x100,
158 .reserve = omap_reserve,
159 .map_io = omap3_map_io,
160 .init_early = omap3630_init_early,
161 .init_irq = omap3_init_irq,
162 .handle_irq = omap3_intc_handle_irq,
163 .init_machine = rm680_init,
164 .init_late = omap3630_init_late,
165 .init_time = omap3_sync32k_timer_init,
166 .restart = omap3xxx_restart,
167MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
deleted file mode 100644
index 42e5f231a799..000000000000
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * Copyright (C) 2009 Texas Instruments Inc.
3 * Mikkel Christensen <mlc@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/gpio.h>
13#include <linux/serial_8250.h>
14#include <linux/smsc911x.h>
15#include <linux/interrupt.h>
16
17#include <linux/regulator/fixed.h>
18#include <linux/regulator/machine.h>
19
20#include "gpmc.h"
21#include "gpmc-smsc911x.h"
22
23#include "board-zoom.h"
24
25#include "soc.h"
26#include "common.h"
27
28#define ZOOM_SMSC911X_CS 7
29#define ZOOM_SMSC911X_GPIO 158
30#define ZOOM_QUADUART_CS 3
31#define ZOOM_QUADUART_GPIO 102
32#define ZOOM_QUADUART_RST_GPIO 152
33#define QUART_CLK 1843200
34#define DEBUG_BASE 0x08000000
35#define ZOOM_ETHR_START DEBUG_BASE
36
37static struct omap_smsc911x_platform_data zoom_smsc911x_cfg = {
38 .cs = ZOOM_SMSC911X_CS,
39 .gpio_irq = ZOOM_SMSC911X_GPIO,
40 .gpio_reset = -EINVAL,
41 .flags = SMSC911X_USE_32BIT,
42};
43
44static inline void __init zoom_init_smsc911x(void)
45{
46 gpmc_smsc911x_init(&zoom_smsc911x_cfg);
47}
48
49static struct plat_serial8250_port serial_platform_data[] = {
50 {
51 .mapbase = ZOOM_UART_BASE,
52 .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
53 .irqflags = IRQF_SHARED | IRQF_TRIGGER_RISING,
54 .iotype = UPIO_MEM,
55 .regshift = 1,
56 .uartclk = QUART_CLK,
57 }, {
58 .flags = 0
59 }
60};
61
62static struct platform_device zoom_debugboard_serial_device = {
63 .name = "serial8250",
64 .id = PLAT8250_DEV_PLATFORM,
65 .dev = {
66 .platform_data = serial_platform_data,
67 },
68};
69
70static inline void __init zoom_init_quaduart(void)
71{
72 int quart_cs;
73 unsigned long cs_mem_base;
74 int quart_gpio = 0;
75
76 if (gpio_request_one(ZOOM_QUADUART_RST_GPIO,
77 GPIOF_OUT_INIT_LOW,
78 "TL16CP754C GPIO") < 0) {
79 pr_err("Failed to request GPIO%d for TL16CP754C\n",
80 ZOOM_QUADUART_RST_GPIO);
81 return;
82 }
83
84 quart_cs = ZOOM_QUADUART_CS;
85
86 if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
87 pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n");
88 return;
89 }
90
91 quart_gpio = ZOOM_QUADUART_GPIO;
92
93 if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0)
94 printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
95 quart_gpio);
96
97 serial_platform_data[0].irq = gpio_to_irq(102);
98}
99
100static inline int omap_zoom_debugboard_detect(void)
101{
102 int debug_board_detect = 0;
103 int ret = 1;
104
105 debug_board_detect = ZOOM_SMSC911X_GPIO;
106
107 if (gpio_request_one(debug_board_detect, GPIOF_IN,
108 "Zoom debug board detect") < 0) {
109 pr_err("Failed to request GPIO%d for Zoom debug board detect\n",
110 debug_board_detect);
111 return 0;
112 }
113
114 if (!gpio_get_value(debug_board_detect)) {
115 ret = 0;
116 }
117 gpio_free(debug_board_detect);
118 return ret;
119}
120
121static struct platform_device *zoom_devices[] __initdata = {
122 &zoom_debugboard_serial_device,
123};
124
125static struct regulator_consumer_supply dummy_supplies[] = {
126 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
127 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
128};
129
130int __init zoom_debugboard_init(void)
131{
132 if (!omap_zoom_debugboard_detect())
133 return 0;
134
135 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
136 zoom_init_smsc911x();
137 zoom_init_quaduart();
138 return platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices));
139}
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
deleted file mode 100644
index 3d8ecc1e05bd..000000000000
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright (C) 2010 Texas Instruments Inc.
3 *
4 * Modified from mach-omap2/board-zoom-peripherals.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/gpio.h>
15#include <linux/spi/spi.h>
16#include <linux/platform_data/spi-omap2-mcspi.h>
17#include <video/omapdss.h>
18#include <video/omap-panel-data.h>
19
20#include "board-zoom.h"
21#include "soc.h"
22#include "common.h"
23
24#define LCD_PANEL_RESET_GPIO_PROD 96
25#define LCD_PANEL_RESET_GPIO_PILOT 55
26#define LCD_PANEL_QVGA_GPIO 56
27
28static struct panel_nec_nl8048hl11_platform_data zoom_lcd_pdata = {
29 .name = "lcd",
30 .source = "dpi.0",
31
32 .data_lines = 24,
33
34 .res_gpio = -1, /* filled in code */
35 .qvga_gpio = LCD_PANEL_QVGA_GPIO,
36};
37
38static struct omap_dss_board_info zoom_dss_data = {
39 .default_display_name = "lcd",
40};
41
42static void __init zoom_lcd_panel_init(void)
43{
44 zoom_lcd_pdata.res_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ?
45 LCD_PANEL_RESET_GPIO_PROD :
46 LCD_PANEL_RESET_GPIO_PILOT;
47}
48
49static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
50 .turbo_mode = 1,
51};
52
53static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
54 [0] = {
55 .modalias = "panel-nec-nl8048hl11",
56 .bus_num = 1,
57 .chip_select = 2,
58 .max_speed_hz = 375000,
59 .controller_data = &dss_lcd_mcspi_config,
60 .platform_data = &zoom_lcd_pdata,
61 },
62};
63
64void __init zoom_display_init(void)
65{
66 omap_display_init(&zoom_dss_data);
67 zoom_lcd_panel_init();
68 spi_register_board_info(nec_8048_spi_board_info,
69 ARRAY_SIZE(nec_8048_spi_board_info));
70}
71
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
deleted file mode 100644
index a90375d5b2b6..000000000000
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ /dev/null
@@ -1,360 +0,0 @@
1/*
2 * Copyright (C) 2009 Texas Instruments Inc.
3 *
4 * Modified from mach-omap2/board-zoom2.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/input.h>
15#include <linux/input/matrix_keypad.h>
16#include <linux/gpio.h>
17#include <linux/i2c/twl.h>
18#include <linux/regulator/machine.h>
19#include <linux/regulator/fixed.h>
20#include <linux/wl12xx.h>
21#include <linux/mmc/host.h>
22#include <linux/platform_data/gpio-omap.h>
23#include <linux/platform_data/omap-twl4030.h>
24#include <linux/usb/phy.h>
25#include <linux/pwm.h>
26#include <linux/leds_pwm.h>
27#include <linux/pwm_backlight.h>
28
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32
33#include "common.h"
34
35#include "board-zoom.h"
36
37#include "mux.h"
38#include "hsmmc.h"
39#include "common-board-devices.h"
40
41#define OMAP_ZOOM_WLAN_PMENA_GPIO (101)
42#define OMAP_ZOOM_TSC2004_IRQ_GPIO (153)
43#define OMAP_ZOOM_WLAN_IRQ_GPIO (162)
44
45/* Zoom2 has Qwerty keyboard*/
46static uint32_t board_keymap[] = {
47 KEY(0, 0, KEY_E),
48 KEY(0, 1, KEY_R),
49 KEY(0, 2, KEY_T),
50 KEY(0, 3, KEY_HOME),
51 KEY(0, 6, KEY_I),
52 KEY(0, 7, KEY_LEFTSHIFT),
53 KEY(1, 0, KEY_D),
54 KEY(1, 1, KEY_F),
55 KEY(1, 2, KEY_G),
56 KEY(1, 3, KEY_SEND),
57 KEY(1, 6, KEY_K),
58 KEY(1, 7, KEY_ENTER),
59 KEY(2, 0, KEY_X),
60 KEY(2, 1, KEY_C),
61 KEY(2, 2, KEY_V),
62 KEY(2, 3, KEY_END),
63 KEY(2, 6, KEY_DOT),
64 KEY(2, 7, KEY_CAPSLOCK),
65 KEY(3, 0, KEY_Z),
66 KEY(3, 1, KEY_KPPLUS),
67 KEY(3, 2, KEY_B),
68 KEY(3, 3, KEY_F1),
69 KEY(3, 6, KEY_O),
70 KEY(3, 7, KEY_SPACE),
71 KEY(4, 0, KEY_W),
72 KEY(4, 1, KEY_Y),
73 KEY(4, 2, KEY_U),
74 KEY(4, 3, KEY_F2),
75 KEY(4, 4, KEY_VOLUMEUP),
76 KEY(4, 6, KEY_L),
77 KEY(4, 7, KEY_LEFT),
78 KEY(5, 0, KEY_S),
79 KEY(5, 1, KEY_H),
80 KEY(5, 2, KEY_J),
81 KEY(5, 3, KEY_F3),
82 KEY(5, 4, KEY_UNKNOWN),
83 KEY(5, 5, KEY_VOLUMEDOWN),
84 KEY(5, 6, KEY_M),
85 KEY(5, 7, KEY_RIGHT),
86 KEY(6, 0, KEY_Q),
87 KEY(6, 1, KEY_A),
88 KEY(6, 2, KEY_N),
89 KEY(6, 3, KEY_BACKSPACE),
90 KEY(6, 6, KEY_P),
91 KEY(6, 7, KEY_UP),
92 KEY(7, 0, KEY_PROG1), /*MACRO 1 <User defined> */
93 KEY(7, 1, KEY_PROG2), /*MACRO 2 <User defined> */
94 KEY(7, 2, KEY_PROG3), /*MACRO 3 <User defined> */
95 KEY(7, 3, KEY_PROG4), /*MACRO 4 <User defined> */
96 KEY(7, 6, KEY_SELECT),
97 KEY(7, 7, KEY_DOWN)
98};
99
100static struct matrix_keymap_data board_map_data = {
101 .keymap = board_keymap,
102 .keymap_size = ARRAY_SIZE(board_keymap),
103};
104
105static struct twl4030_keypad_data zoom_kp_twl4030_data = {
106 .keymap_data = &board_map_data,
107 .rows = 8,
108 .cols = 8,
109 .rep = 1,
110};
111
112static struct regulator_consumer_supply zoom_vmmc1_supply[] = {
113 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
114};
115
116static struct regulator_consumer_supply zoom_vsim_supply[] = {
117 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
118};
119
120static struct regulator_consumer_supply zoom_vmmc2_supply[] = {
121 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
122};
123
124static struct regulator_consumer_supply zoom_vmmc3_supply[] = {
125 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
126};
127
128/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
129static struct regulator_init_data zoom_vmmc1 = {
130 .constraints = {
131 .min_uV = 1850000,
132 .max_uV = 3150000,
133 .valid_modes_mask = REGULATOR_MODE_NORMAL
134 | REGULATOR_MODE_STANDBY,
135 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
136 | REGULATOR_CHANGE_MODE
137 | REGULATOR_CHANGE_STATUS,
138 },
139 .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc1_supply),
140 .consumer_supplies = zoom_vmmc1_supply,
141};
142
143/* VMMC2 for MMC2 card */
144static struct regulator_init_data zoom_vmmc2 = {
145 .constraints = {
146 .min_uV = 1850000,
147 .max_uV = 1850000,
148 .apply_uV = true,
149 .valid_modes_mask = REGULATOR_MODE_NORMAL
150 | REGULATOR_MODE_STANDBY,
151 .valid_ops_mask = REGULATOR_CHANGE_MODE
152 | REGULATOR_CHANGE_STATUS,
153 },
154 .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc2_supply),
155 .consumer_supplies = zoom_vmmc2_supply,
156};
157
158/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
159static struct regulator_init_data zoom_vsim = {
160 .constraints = {
161 .min_uV = 1800000,
162 .max_uV = 3000000,
163 .valid_modes_mask = REGULATOR_MODE_NORMAL
164 | REGULATOR_MODE_STANDBY,
165 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
166 | REGULATOR_CHANGE_MODE
167 | REGULATOR_CHANGE_STATUS,
168 },
169 .num_consumer_supplies = ARRAY_SIZE(zoom_vsim_supply),
170 .consumer_supplies = zoom_vsim_supply,
171};
172
173static struct regulator_init_data zoom_vmmc3 = {
174 .constraints = {
175 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
176 },
177 .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc3_supply),
178 .consumer_supplies = zoom_vmmc3_supply,
179};
180
181static struct fixed_voltage_config zoom_vwlan = {
182 .supply_name = "vwl1271",
183 .microvolts = 1800000, /* 1.8V */
184 .gpio = OMAP_ZOOM_WLAN_PMENA_GPIO,
185 .startup_delay = 70000, /* 70msec */
186 .enable_high = 1,
187 .enabled_at_boot = 0,
188 .init_data = &zoom_vmmc3,
189};
190
191static struct platform_device omap_vwlan_device = {
192 .name = "reg-fixed-voltage",
193 .id = 1,
194 .dev = {
195 .platform_data = &zoom_vwlan,
196 },
197};
198
199static struct pwm_lookup zoom_pwm_lookup[] = {
200 PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "zoom::keypad"),
201 PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", "backlight"),
202};
203
204static struct led_pwm zoom_pwm_leds[] = {
205 {
206 .name = "zoom::keypad",
207 .max_brightness = 127,
208 .pwm_period_ns = 7812500,
209 },
210};
211
212static struct led_pwm_platform_data zoom_pwm_data = {
213 .num_leds = ARRAY_SIZE(zoom_pwm_leds),
214 .leds = zoom_pwm_leds,
215};
216
217static struct platform_device zoom_leds_pwm = {
218 .name = "leds_pwm",
219 .id = -1,
220 .dev = {
221 .platform_data = &zoom_pwm_data,
222 },
223};
224
225static struct platform_pwm_backlight_data zoom_backlight_data = {
226 .pwm_id = 1,
227 .max_brightness = 127,
228 .dft_brightness = 127,
229 .pwm_period_ns = 7812500,
230};
231
232static struct platform_device zoom_backlight_pwm = {
233 .name = "pwm-backlight",
234 .id = -1,
235 .dev = {
236 .platform_data = &zoom_backlight_data,
237 },
238};
239
240static struct platform_device *zoom_devices[] __initdata = {
241 &omap_vwlan_device,
242 &zoom_leds_pwm,
243 &zoom_backlight_pwm,
244};
245
246static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
247 .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
248};
249
250static struct omap2_hsmmc_info mmc[] = {
251 {
252 .name = "external",
253 .mmc = 1,
254 .caps = MMC_CAP_4_BIT_DATA,
255 .gpio_wp = -EINVAL,
256 .power_saving = true,
257 .deferred = true,
258 },
259 {
260 .name = "internal",
261 .mmc = 2,
262 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
263 .gpio_cd = -EINVAL,
264 .gpio_wp = -EINVAL,
265 .nonremovable = true,
266 .power_saving = true,
267 },
268 {
269 .name = "wl1271",
270 .mmc = 3,
271 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
272 .gpio_wp = -EINVAL,
273 .gpio_cd = -EINVAL,
274 .nonremovable = true,
275 },
276 {} /* Terminator */
277};
278
279static struct omap_tw4030_pdata omap_twl4030_audio_data = {
280 .voice_connected = true,
281 .custom_routing = true,
282
283 .has_hs = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
284 .has_hf = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
285
286 .has_mainmic = true,
287 .has_submic = true,
288 .has_hsmic = true,
289 .has_linein = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
290};
291
292static int zoom_twl_gpio_setup(struct device *dev,
293 unsigned gpio, unsigned ngpio)
294{
295 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
296 mmc[0].gpio_cd = gpio + 0;
297 omap_hsmmc_late_init(mmc);
298
299 /* Audio setup */
300 omap_twl4030_audio_data.jack_detect = gpio + 2;
301 omap_twl4030_audio_init("Zoom2", &omap_twl4030_audio_data);
302
303 return 0;
304}
305
306static struct twl4030_gpio_platform_data zoom_gpio_data = {
307 .setup = zoom_twl_gpio_setup,
308};
309
310static struct twl4030_platform_data zoom_twldata = {
311 /* platform_data for children goes here */
312 .gpio = &zoom_gpio_data,
313 .keypad = &zoom_kp_twl4030_data,
314 .vmmc1 = &zoom_vmmc1,
315 .vmmc2 = &zoom_vmmc2,
316 .vsim = &zoom_vsim,
317};
318
319static int __init omap_i2c_init(void)
320{
321 omap3_pmic_get_config(&zoom_twldata,
322 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
323 TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
324 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
325
326 if (machine_is_omap_zoom2())
327 zoom_twldata.audio->codec->ramp_delay_value = 3; /* 161 ms */
328
329 omap_pmic_init(1, 2400, "twl5030", 7 + OMAP_INTC_START, &zoom_twldata);
330 omap_register_i2c_bus(2, 400, NULL, 0);
331 omap_register_i2c_bus(3, 400, NULL, 0);
332 return 0;
333}
334
335static void enable_board_wakeup_source(void)
336{
337 /* T2 interrupt line (keypad) */
338 omap_mux_init_signal("sys_nirq",
339 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
340}
341
342void __init zoom_peripherals_init(void)
343{
344 int ret;
345
346 omap_zoom_wlan_data.irq = gpio_to_irq(OMAP_ZOOM_WLAN_IRQ_GPIO);
347 ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
348
349 if (ret)
350 pr_err("error setting wl12xx data: %d\n", ret);
351
352 omap_hsmmc_init(mmc);
353 omap_i2c_init();
354 pwm_add_table(zoom_pwm_lookup, ARRAY_SIZE(zoom_pwm_lookup));
355 platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices));
356 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
357 usb_musb_init(NULL);
358 enable_board_wakeup_source();
359 omap_serial_init();
360}
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
deleted file mode 100644
index 1a3dd865d8eb..000000000000
--- a/arch/arm/mach-omap2/board-zoom.c
+++ /dev/null
@@ -1,159 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Texas Instruments Inc.
3 * Mikkel Christensen <mlc@ti.com>
4 * Felipe Balbi <balbi@ti.com>
5 *
6 * Modified from mach-omap2/board-ldp.c
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/input.h>
17#include <linux/gpio.h>
18#include <linux/i2c/twl.h>
19#include <linux/mtd/nand.h>
20
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23
24#include "common.h"
25
26#include "board-zoom.h"
27
28#include "board-flash.h"
29#include "mux.h"
30#include "sdram-micron-mt46h32m32lf-6.h"
31#include "sdram-hynix-h8mbx00u0mer-0em.h"
32
33#define ZOOM3_EHCI_RESET_GPIO 64
34
35#ifdef CONFIG_OMAP_MUX
36static struct omap_board_mux board_mux[] __initdata = {
37 /* WLAN IRQ - GPIO 162 */
38 OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
39 /* WLAN POWER ENABLE - GPIO 101 */
40 OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
41 /* WLAN SDIO: MMC3 CMD */
42 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
43 /* WLAN SDIO: MMC3 CLK */
44 OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
45 /* WLAN SDIO: MMC3 DAT[0-3] */
46 OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
47 OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
48 OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
49 OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
50 { .reg_offset = OMAP_MUX_TERMINATOR },
51};
52#endif
53
54static struct mtd_partition zoom_nand_partitions[] = {
55 /* All the partition sizes are listed in terms of NAND block size */
56 {
57 .name = "X-Loader-NAND",
58 .offset = 0,
59 .size = 4 * (64 * 2048), /* 512KB, 0x80000 */
60 .mask_flags = MTD_WRITEABLE, /* force read-only */
61 },
62 {
63 .name = "U-Boot-NAND",
64 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
65 .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */
66 .mask_flags = MTD_WRITEABLE, /* force read-only */
67 },
68 {
69 .name = "Boot Env-NAND",
70 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
71 .size = 2 * (64 * 2048), /* 256KB, 0x40000 */
72 },
73 {
74 .name = "Kernel-NAND",
75 .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/
76 .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */
77 },
78 {
79 .name = "system",
80 .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */
81 .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */
82 },
83 {
84 .name = "userdata",
85 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/
86 .size = 256 * (64 * 2048), /* 32M, 0x2000000 */
87 },
88 {
89 .name = "cache",
90 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/
91 .size = 256 * (64 * 2048), /* 32M, 0x2000000 */
92 },
93};
94
95static struct usbhs_phy_data phy_data[] __initdata = {
96 {
97 .port = 2,
98 .reset_gpio = ZOOM3_EHCI_RESET_GPIO,
99 .vcc_gpio = -EINVAL,
100 },
101};
102
103static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
104 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
105};
106
107static void __init omap_zoom_init(void)
108{
109 if (machine_is_omap_zoom2()) {
110 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
111 } else if (machine_is_omap_zoom3()) {
112 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
113 omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
114
115 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
116 usbhs_init(&usbhs_bdata);
117 }
118
119 board_nand_init(zoom_nand_partitions,
120 ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS,
121 NAND_BUSWIDTH_16, nand_default_timings);
122 zoom_debugboard_init();
123 zoom_peripherals_init();
124
125 if (machine_is_omap_zoom2())
126 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
127 mt46h32m32lf6_sdrc_params);
128 else if (machine_is_omap_zoom3())
129 omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
130 h8mbx00u0mer0em_sdrc_params);
131
132 zoom_display_init();
133}
134
135MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
136 .atag_offset = 0x100,
137 .reserve = omap_reserve,
138 .map_io = omap3_map_io,
139 .init_early = omap3430_init_early,
140 .init_irq = omap3_init_irq,
141 .handle_irq = omap3_intc_handle_irq,
142 .init_machine = omap_zoom_init,
143 .init_late = omap3430_init_late,
144 .init_time = omap3_sync32k_timer_init,
145 .restart = omap3xxx_restart,
146MACHINE_END
147
148MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
149 .atag_offset = 0x100,
150 .reserve = omap_reserve,
151 .map_io = omap3_map_io,
152 .init_early = omap3630_init_early,
153 .init_irq = omap3_init_irq,
154 .handle_irq = omap3_intc_handle_irq,
155 .init_machine = omap_zoom_init,
156 .init_late = omap3630_init_late,
157 .init_time = omap3_sync32k_timer_init,
158 .restart = omap3xxx_restart,
159MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom.h b/arch/arm/mach-omap2/board-zoom.h
deleted file mode 100644
index 2e9486940ead..000000000000
--- a/arch/arm/mach-omap2/board-zoom.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/*
2 * Defines for zoom boards
3 */
4#include <video/omapdss.h>
5
6#define ZOOM_NAND_CS 0
7
8extern int __init zoom_debugboard_init(void);
9extern void __init zoom_peripherals_init(void);
10extern void __init zoom_display_init(void);
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 4a5684b96492..f7644febee81 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -98,6 +98,7 @@ void am35xx_init_early(void);
98void ti81xx_init_early(void); 98void ti81xx_init_early(void);
99void am33xx_init_early(void); 99void am33xx_init_early(void);
100void am43xx_init_early(void); 100void am43xx_init_early(void);
101void am43xx_init_late(void);
101void omap4430_init_early(void); 102void omap4430_init_early(void);
102void omap5_init_early(void); 103void omap5_init_early(void);
103void omap3_init_late(void); /* Do not use this one */ 104void omap3_init_late(void); /* Do not use this one */
@@ -109,8 +110,11 @@ void omap35xx_init_late(void);
109void omap3630_init_late(void); 110void omap3630_init_late(void);
110void am35xx_init_late(void); 111void am35xx_init_late(void);
111void ti81xx_init_late(void); 112void ti81xx_init_late(void);
113void am33xx_init_late(void);
114void omap5_init_late(void);
112int omap2_common_pm_late_init(void); 115int omap2_common_pm_late_init(void);
113void dra7xx_init_early(void); 116void dra7xx_init_early(void);
117void dra7xx_init_late(void);
114 118
115#ifdef CONFIG_SOC_BUS 119#ifdef CONFIG_SOC_BUS
116void omap_soc_device_init(void); 120void omap_soc_device_init(void);
@@ -288,6 +292,9 @@ static inline void omap4_cpu_resume(void)
288 292
289#endif 293#endif
290 294
295void pdata_quirks_init(struct of_device_id *);
296void omap_pcs_legacy_init(int irq, void (*rearm)(void));
297
291struct omap_sdrc_params; 298struct omap_sdrc_params;
292extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 299extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
293 struct omap_sdrc_params *sdrc_cs1); 300 struct omap_sdrc_params *sdrc_cs1);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 89a8698cd6ed..0dd6398bade4 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -19,7 +19,6 @@
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/pinctrl/machine.h> 20#include <linux/pinctrl/machine.h>
21#include <linux/platform_data/omap4-keypad.h> 21#include <linux/platform_data/omap4-keypad.h>
22#include <linux/wl12xx.h>
23#include <linux/platform_data/mailbox-omap.h> 22#include <linux/platform_data/mailbox-omap.h>
24 23
25#include <asm/mach-types.h> 24#include <asm/mach-types.h>
@@ -476,40 +475,6 @@ int __init omap_init_vout(void)
476int __init omap_init_vout(void) { return 0; } 475int __init omap_init_vout(void) { return 0; }
477#endif 476#endif
478 477
479#if IS_ENABLED(CONFIG_WL12XX)
480
481static struct wl12xx_platform_data wl12xx __initdata;
482
483void __init omap_init_wl12xx_of(void)
484{
485 int ret;
486
487 if (!of_have_populated_dt())
488 return;
489
490 if (of_machine_is_compatible("ti,omap4-sdp")) {
491 wl12xx.board_ref_clock = WL12XX_REFCLOCK_26;
492 wl12xx.board_tcxo_clock = WL12XX_TCXOCLOCK_26;
493 wl12xx.irq = gpio_to_irq(53);
494 } else if (of_machine_is_compatible("ti,omap4-panda")) {
495 wl12xx.board_ref_clock = WL12XX_REFCLOCK_38;
496 wl12xx.irq = gpio_to_irq(53);
497 } else {
498 return;
499 }
500
501 ret = wl12xx_set_platform_data(&wl12xx);
502 if (ret) {
503 pr_err("error setting wl12xx data: %d\n", ret);
504 return;
505 }
506}
507#else
508static inline void omap_init_wl12xx_of(void)
509{
510}
511#endif
512
513/*-------------------------------------------------------------------------*/ 478/*-------------------------------------------------------------------------*/
514 479
515static int __init omap2_init_devices(void) 480static int __init omap2_init_devices(void)
@@ -532,9 +497,6 @@ static int __init omap2_init_devices(void)
532 omap_init_sham(); 497 omap_init_sham();
533 omap_init_aes(); 498 omap_init_aes();
534 omap_init_rng(); 499 omap_init_rng();
535 } else {
536 /* These can be removed when bindings are done */
537 omap_init_wl12xx_of();
538 } 500 }
539 omap_init_sti(); 501 omap_init_sti();
540 502
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index bf89effa4c99..365bfd3d9c68 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -213,3 +213,47 @@ void __init omap_4430sdp_display_init_of(void)
213 platform_device_register(&sdp4430_tpd_device); 213 platform_device_register(&sdp4430_tpd_device);
214 platform_device_register(&sdp4430_hdmi_connector_device); 214 platform_device_register(&sdp4430_hdmi_connector_device);
215} 215}
216
217
218/* OMAP3 IGEPv2 data */
219
220#define IGEP2_DVI_TFP410_POWER_DOWN_GPIO 170
221
222/* DVI Connector */
223static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = {
224 .name = "dvi",
225 .source = "tfp410.0",
226 .i2c_bus_num = 3,
227};
228
229static struct platform_device omap3_igep2_dvi_connector_device = {
230 .name = "connector-dvi",
231 .id = 0,
232 .dev.platform_data = &omap3_igep2_dvi_connector_pdata,
233};
234
235/* TFP410 DPI-to-DVI chip */
236static struct encoder_tfp410_platform_data omap3_igep2_tfp410_pdata = {
237 .name = "tfp410.0",
238 .source = "dpi.0",
239 .data_lines = 24,
240 .power_down_gpio = IGEP2_DVI_TFP410_POWER_DOWN_GPIO,
241};
242
243static struct platform_device omap3_igep2_tfp410_device = {
244 .name = "tfp410",
245 .id = 0,
246 .dev.platform_data = &omap3_igep2_tfp410_pdata,
247};
248
249static struct omap_dss_board_info igep2_dss_data = {
250 .default_display_name = "dvi",
251};
252
253void __init omap3_igep2_display_init_of(void)
254{
255 omap_display_init(&igep2_dss_data);
256
257 platform_device_register(&omap3_igep2_tfp410_device);
258 platform_device_register(&omap3_igep2_dvi_connector_device);
259}
diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h
index c28fe3c03588..a9becf0d5be8 100644
--- a/arch/arm/mach-omap2/dss-common.h
+++ b/arch/arm/mach-omap2/dss-common.h
@@ -8,5 +8,6 @@
8 8
9void __init omap4_panda_display_init_of(void); 9void __init omap4_panda_display_init_of(void);
10void __init omap_4430sdp_display_init_of(void); 10void __init omap_4430sdp_display_init_of(void);
11void __init omap3_igep2_display_init_of(void);
11 12
12#endif 13#endif
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 579697adaae7..51525faa0aec 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1521,6 +1521,42 @@ err:
1521 return ret; 1521 return ret;
1522} 1522}
1523 1523
1524/*
1525 * REVISIT: Add timing support from slls644g.pdf
1526 */
1527static int gpmc_probe_8250(struct platform_device *pdev,
1528 struct device_node *child)
1529{
1530 struct resource res;
1531 unsigned long base;
1532 int ret, cs;
1533
1534 if (of_property_read_u32(child, "reg", &cs) < 0) {
1535 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1536 child->full_name);
1537 return -ENODEV;
1538 }
1539
1540 if (of_address_to_resource(child, 0, &res) < 0) {
1541 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1542 child->full_name);
1543 return -ENODEV;
1544 }
1545
1546 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1547 if (ret < 0) {
1548 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1549 return ret;
1550 }
1551
1552 if (of_platform_device_create(child, NULL, &pdev->dev))
1553 return 0;
1554
1555 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
1556
1557 return -ENODEV;
1558}
1559
1524static int gpmc_probe_dt(struct platform_device *pdev) 1560static int gpmc_probe_dt(struct platform_device *pdev)
1525{ 1561{
1526 int ret; 1562 int ret;
@@ -1564,6 +1600,8 @@ static int gpmc_probe_dt(struct platform_device *pdev)
1564 else if (of_node_cmp(child->name, "ethernet") == 0 || 1600 else if (of_node_cmp(child->name, "ethernet") == 0 ||
1565 of_node_cmp(child->name, "nor") == 0) 1601 of_node_cmp(child->name, "nor") == 0)
1566 ret = gpmc_probe_generic_child(pdev, child); 1602 ret = gpmc_probe_generic_child(pdev, child);
1603 else if (of_node_cmp(child->name, "8250") == 0)
1604 ret = gpmc_probe_8250(pdev, child);
1567 1605
1568 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n", 1606 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1569 __func__, child->full_name)) 1607 __func__, child->full_name))
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index c90f64765a3d..cd22262a2cc0 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -583,6 +583,11 @@ void __init am33xx_init_early(void)
583 omap_hwmod_init_postsetup(); 583 omap_hwmod_init_postsetup();
584 omap_clk_init = am33xx_clk_init; 584 omap_clk_init = am33xx_clk_init;
585} 585}
586
587void __init am33xx_init_late(void)
588{
589 omap_common_late_init();
590}
586#endif 591#endif
587 592
588#ifdef CONFIG_SOC_AM43XX 593#ifdef CONFIG_SOC_AM43XX
@@ -602,6 +607,11 @@ void __init am43xx_init_early(void)
602 am43xx_hwmod_init(); 607 am43xx_hwmod_init();
603 omap_hwmod_init_postsetup(); 608 omap_hwmod_init_postsetup();
604} 609}
610
611void __init am43xx_init_late(void)
612{
613 omap_common_late_init();
614}
605#endif 615#endif
606 616
607#ifdef CONFIG_ARCH_OMAP4 617#ifdef CONFIG_ARCH_OMAP4
@@ -657,6 +667,11 @@ void __init omap5_init_early(void)
657 omap54xx_hwmod_init(); 667 omap54xx_hwmod_init();
658 omap_hwmod_init_postsetup(); 668 omap_hwmod_init_postsetup();
659} 669}
670
671void __init omap5_init_late(void)
672{
673 omap_common_late_init();
674}
660#endif 675#endif
661 676
662#ifdef CONFIG_SOC_DRA7XX 677#ifdef CONFIG_SOC_DRA7XX
@@ -677,6 +692,11 @@ void __init dra7xx_init_early(void)
677 dra7xx_hwmod_init(); 692 dra7xx_hwmod_init();
678 omap_hwmod_init_postsetup(); 693 omap_hwmod_init_postsetup();
679} 694}
695
696void __init dra7xx_init_late(void)
697{
698 omap_common_late_init();
699}
680#endif 700#endif
681 701
682 702
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index f82cf878d6af..48094b58c88f 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -811,6 +811,12 @@ int __init omap_mux_late_init(void)
811 } 811 }
812 } 812 }
813 813
814 omap_mux_dbg_init();
815
816 /* see pinctrl-single-omap for the wake-up interrupt handling */
817 if (of_have_populated_dt())
818 return 0;
819
814 ret = request_irq(omap_prcm_event_to_irq("io"), 820 ret = request_irq(omap_prcm_event_to_irq("io"),
815 omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND, 821 omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
816 "hwmod_io", omap_mux_late_init); 822 "hwmod_io", omap_mux_late_init);
@@ -818,8 +824,6 @@ int __init omap_mux_late_init(void)
818 if (ret) 824 if (ret)
819 pr_warning("mux: Failed to setup hwmod io irq %d\n", ret); 825 pr_warning("mux: Failed to setup hwmod io irq %d\n", ret);
820 826
821 omap_mux_dbg_init();
822
823 return 0; 827 return 0;
824} 828}
825 829
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index bd41d59a7cab..82fd8c72f750 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -17,6 +17,7 @@
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 */ 18 */
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/of.h>
20#include <linux/opp.h> 21#include <linux/opp.h>
21#include <linux/cpu.h> 22#include <linux/cpu.h>
22 23
@@ -40,6 +41,9 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
40{ 41{
41 int i, r; 42 int i, r;
42 43
44 if (of_have_populated_dt())
45 return -EINVAL;
46
43 if (!opp_def || !opp_def_size) { 47 if (!opp_def || !opp_def_size) {
44 pr_err("%s: invalid params!\n", __func__); 48 pr_err("%s: invalid params!\n", __func__);
45 return -EINVAL; 49 return -EINVAL;
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
new file mode 100644
index 000000000000..10c71450cf63
--- /dev/null
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -0,0 +1,174 @@
1/*
2 * Legacy platform_data quirks
3 *
4 * Copyright (C) 2013 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/clk.h>
11#include <linux/gpio.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/of_platform.h>
15#include <linux/wl12xx.h>
16
17#include <linux/platform_data/pinctrl-single.h>
18
19#include "common.h"
20#include "common-board-devices.h"
21#include "dss-common.h"
22#include "control.h"
23
24struct pdata_init {
25 const char *compatible;
26 void (*fn)(void);
27};
28
29/*
30 * Create alias for USB host PHY clock.
31 * Remove this when clock phandle can be provided via DT
32 */
33static void __init __used legacy_init_ehci_clk(char *clkname)
34{
35 int ret;
36
37 ret = clk_add_alias("main_clk", NULL, clkname, NULL);
38 if (ret)
39 pr_err("%s:Failed to add main_clk alias to %s :%d\n",
40 __func__, clkname, ret);
41}
42
43#if IS_ENABLED(CONFIG_WL12XX)
44
45static struct wl12xx_platform_data wl12xx __initdata;
46
47static void __init __used legacy_init_wl12xx(unsigned ref_clock,
48 unsigned tcxo_clock,
49 int gpio)
50{
51 int res;
52
53 wl12xx.board_ref_clock = ref_clock;
54 wl12xx.board_tcxo_clock = tcxo_clock;
55 wl12xx.irq = gpio_to_irq(gpio);
56
57 res = wl12xx_set_platform_data(&wl12xx);
58 if (res) {
59 pr_err("error setting wl12xx data: %d\n", res);
60 return;
61 }
62}
63#else
64static inline void legacy_init_wl12xx(unsigned ref_clock,
65 unsigned tcxo_clock,
66 int gpio)
67{
68}
69#endif
70
71#ifdef CONFIG_ARCH_OMAP3
72static void __init hsmmc2_internal_input_clk(void)
73{
74 u32 reg;
75
76 reg = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
77 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
78 omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
79}
80
81static void __init omap3_igep0020_legacy_init(void)
82{
83 omap3_igep2_display_init_of();
84}
85
86static void __init omap3_evm_legacy_init(void)
87{
88 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 149);
89}
90
91static void __init omap3_zoom_legacy_init(void)
92{
93 legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162);
94}
95#endif /* CONFIG_ARCH_OMAP3 */
96
97#ifdef CONFIG_ARCH_OMAP4
98static void __init omap4_sdp_legacy_init(void)
99{
100 omap_4430sdp_display_init_of();
101 legacy_init_wl12xx(WL12XX_REFCLOCK_26,
102 WL12XX_TCXOCLOCK_26, 53);
103}
104
105static void __init omap4_panda_legacy_init(void)
106{
107 omap4_panda_display_init_of();
108 legacy_init_ehci_clk("auxclk3_ck");
109 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53);
110}
111#endif
112
113#ifdef CONFIG_SOC_OMAP5
114static void __init omap5_uevm_legacy_init(void)
115{
116 legacy_init_ehci_clk("auxclk1_ck");
117}
118#endif
119
120static struct pcs_pdata pcs_pdata;
121
122void omap_pcs_legacy_init(int irq, void (*rearm)(void))
123{
124 pcs_pdata.irq = irq;
125 pcs_pdata.rearm = rearm;
126}
127
128struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
129#ifdef CONFIG_ARCH_OMAP3
130 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
131 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata),
132#endif
133#ifdef CONFIG_ARCH_OMAP4
134 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
135 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata),
136#endif
137 { /* sentinel */ },
138};
139
140static struct pdata_init pdata_quirks[] __initdata = {
141#ifdef CONFIG_ARCH_OMAP3
142 { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
143 { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
144 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
145 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
146 { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
147#endif
148#ifdef CONFIG_ARCH_OMAP4
149 { "ti,omap4-sdp", omap4_sdp_legacy_init, },
150 { "ti,omap4-panda", omap4_panda_legacy_init, },
151#endif
152#ifdef CONFIG_SOC_OMAP5
153 { "ti,omap5-uevm", omap5_uevm_legacy_init, },
154#endif
155 { /* sentinel */ },
156};
157
158void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
159{
160 struct pdata_init *quirks = pdata_quirks;
161
162 omap_sdrc_init(NULL, NULL);
163 of_platform_populate(NULL, omap_dt_match_table,
164 omap_auxdata_lookup, NULL);
165
166 while (quirks->compatible) {
167 if (of_machine_is_compatible(quirks->compatible)) {
168 if (quirks->fn)
169 quirks->fn();
170 break;
171 }
172 quirks++;
173 }
174}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index e742118fcfd2..360b2daf54dd 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -266,7 +266,12 @@ static void __init omap4_init_voltages(void)
266 266
267static inline void omap_init_cpufreq(void) 267static inline void omap_init_cpufreq(void)
268{ 268{
269 struct platform_device_info devinfo = { .name = "omap-cpufreq", }; 269 struct platform_device_info devinfo = { };
270
271 if (!of_have_populated_dt())
272 devinfo.name = "omap-cpufreq";
273 else
274 devinfo.name = "cpufreq-cpu0";
270 platform_device_register_full(&devinfo); 275 platform_device_register_full(&devinfo);
271} 276}
272 277
@@ -300,10 +305,11 @@ int __init omap2_common_pm_late_init(void)
300 /* Smartreflex device init */ 305 /* Smartreflex device init */
301 omap_devinit_smartreflex(); 306 omap_devinit_smartreflex();
302 307
303 /* cpufreq dummy device instantiation */
304 omap_init_cpufreq();
305 } 308 }
306 309
310 /* cpufreq dummy device instantiation */
311 omap_init_cpufreq();
312
307#ifdef CONFIG_SUSPEND 313#ifdef CONFIG_SUSPEND
308 suspend_set_ops(&omap_pm_ops); 314 suspend_set_ops(&omap_pm_ops);
309#endif 315#endif
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index 277f71794e61..f8eb83323b1a 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -144,7 +144,13 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
144extern void omap3_prm_vcvp_write(u32 val, u8 offset); 144extern void omap3_prm_vcvp_write(u32 val, u8 offset);
145extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 145extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
146 146
147extern void omap3xxx_prm_reconfigure_io_chain(void); 147#ifdef CONFIG_ARCH_OMAP3
148void omap3xxx_prm_reconfigure_io_chain(void);
149#else
150static inline void omap3xxx_prm_reconfigure_io_chain(void)
151{
152}
153#endif
148 154
149/* PRM interrupt-related functions */ 155/* PRM interrupt-related functions */
150extern void omap3xxx_prm_read_pending_irqs(unsigned long *events); 156extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 7cd22abb8f15..a085d9cc1f5d 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -42,7 +42,13 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
42extern void omap4_prm_vcvp_write(u32 val, u8 offset); 42extern void omap4_prm_vcvp_write(u32 val, u8 offset);
43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
44 44
45extern void omap44xx_prm_reconfigure_io_chain(void); 45#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
46void omap44xx_prm_reconfigure_io_chain(void);
47#else
48static inline void omap44xx_prm_reconfigure_io_chain(void)
49{
50}
51#endif
46 52
47/* PRM interrupt-related functions */ 53/* PRM interrupt-related functions */
48extern void omap44xx_prm_read_pending_irqs(unsigned long *events); 54extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 228b850e632f..a2e1174ad1b6 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -24,6 +24,7 @@
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26 26
27#include "soc.h"
27#include "prm2xxx_3xxx.h" 28#include "prm2xxx_3xxx.h"
28#include "prm2xxx.h" 29#include "prm2xxx.h"
29#include "prm3xxx.h" 30#include "prm3xxx.h"
@@ -322,6 +323,16 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
322 prcm_irq_chips[i] = gc; 323 prcm_irq_chips[i] = gc;
323 } 324 }
324 325
326 if (of_have_populated_dt()) {
327 int irq = omap_prcm_event_to_irq("io");
328 if (cpu_is_omap34xx())
329 omap_pcs_legacy_init(irq,
330 omap3xxx_prm_reconfigure_io_chain);
331 else
332 omap_pcs_legacy_init(irq,
333 omap44xx_prm_reconfigure_io_chain);
334 }
335
325 return 0; 336 return 0;
326 337
327err: 338err:
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index a2d5bb33647d..2cb8dc55b50e 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -298,4 +298,20 @@ config MACH_WLF_CRAGG_6410
298 help 298 help
299 Machine support for the Wolfson Cragganmore S3C6410 variant. 299 Machine support for the Wolfson Cragganmore S3C6410 variant.
300 300
301config MACH_S3C64XX_DT
302 bool "Samsung S3C6400/S3C6410 machine using Device Tree"
303 select CLKSRC_OF
304 select CPU_S3C6400
305 select CPU_S3C6410
306 select PINCTRL
307 select PINCTRL_S3C64XX
308 select USE_OF
309 help
310 Machine support for Samsung S3C6400/S3C6410 machines with Device Tree
311 enabled.
312 Select this if a fdt blob is available for your S3C64XX SoC based
313 board.
314 Note: This is under development and not all peripherals can be
315 supported with this machine file.
316
301endif 317endif
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 645a8fe55f8d..6faedcffce04 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
57obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o 57obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
58obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o 58obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
59obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o 59obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
60obj-$(CONFIG_MACH_S3C64XX_DT) += mach-s3c64xx-dt.o
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 7d3cb58f1856..7a3ce4c39e5f 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -14,6 +14,10 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17/*
18 * NOTE: Code in this file is not used when booting with Device Tree support.
19 */
20
17#include <linux/kernel.h> 21#include <linux/kernel.h>
18#include <linux/init.h> 22#include <linux/init.h>
19#include <linux/module.h> 23#include <linux/module.h>
@@ -203,6 +207,10 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
203 207
204static __init int s3c64xx_dev_init(void) 208static __init int s3c64xx_dev_init(void)
205{ 209{
210 /* Not applicable when using DT. */
211 if (of_have_populated_dt())
212 return 0;
213
206 subsys_system_register(&s3c64xx_subsys, NULL); 214 subsys_system_register(&s3c64xx_subsys, NULL);
207 return device_register(&s3c64xx_dev); 215 return device_register(&s3c64xx_dev);
208} 216}
@@ -404,6 +412,10 @@ static int __init s3c64xx_init_irq_eint(void)
404{ 412{
405 int irq; 413 int irq;
406 414
415 /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
416 if (of_have_populated_dt())
417 return -ENODEV;
418
407 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { 419 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
408 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); 420 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
409 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); 421 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index c511dfaae148..7e22c2113816 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -12,6 +12,10 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15/*
16 * NOTE: Code in this file is not used when booting with Device Tree support.
17 */
18
15#include <linux/kernel.h> 19#include <linux/kernel.h>
16#include <linux/module.h> 20#include <linux/module.h>
17#include <linux/interrupt.h> 21#include <linux/interrupt.h>
@@ -24,6 +28,7 @@
24#include <linux/err.h> 28#include <linux/err.h>
25#include <linux/io.h> 29#include <linux/io.h>
26#include <linux/amba/pl080.h> 30#include <linux/amba/pl080.h>
31#include <linux/of.h>
27 32
28#include <mach/dma.h> 33#include <mach/dma.h>
29#include <mach/map.h> 34#include <mach/map.h>
@@ -726,6 +731,10 @@ static int __init s3c64xx_dma_init(void)
726{ 731{
727 int ret; 732 int ret;
728 733
734 /* This driver is not supported when booting with device tree. */
735 if (of_have_populated_dt())
736 return -ENODEV;
737
729 printk(KERN_INFO "%s: Registering DMA channels\n", __func__); 738 printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
730 739
731 dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0); 740 dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0);
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index c3da1b68d03e..1649c0d1c1b8 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -12,12 +12,17 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14 14
15/*
16 * NOTE: Code in this file is not used when booting with Device Tree support.
17 */
18
15#include <linux/kernel.h> 19#include <linux/kernel.h>
16#include <linux/syscore_ops.h> 20#include <linux/syscore_ops.h>
17#include <linux/interrupt.h> 21#include <linux/interrupt.h>
18#include <linux/serial_core.h> 22#include <linux/serial_core.h>
19#include <linux/irq.h> 23#include <linux/irq.h>
20#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/of.h>
21 26
22#include <mach/map.h> 27#include <mach/map.h>
23 28
@@ -101,6 +106,10 @@ static struct syscore_ops s3c64xx_irq_syscore_ops = {
101 106
102static __init int s3c64xx_syscore_init(void) 107static __init int s3c64xx_syscore_init(void)
103{ 108{
109 /* Appropriate drivers (pinctrl, uart) handle this when using DT. */
110 if (of_have_populated_dt())
111 return 0;
112
104 register_syscore_ops(&s3c64xx_irq_syscore_ops); 113 register_syscore_ops(&s3c64xx_irq_syscore_ops);
105 114
106 return 0; 115 return 0;
diff --git a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
new file mode 100644
index 000000000000..7eb9a10fc1af
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
@@ -0,0 +1,85 @@
1/*
2 * Samsung's S3C64XX flattened device tree enabled machine
3 *
4 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/clk-provider.h>
12#include <linux/irqchip.h>
13#include <linux/of_platform.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <asm/system_misc.h>
18
19#include <plat/cpu.h>
20#include <plat/watchdog-reset.h>
21
22#include <mach/map.h>
23
24#include "common.h"
25
26/*
27 * IO mapping for shared system controller IP.
28 *
29 * FIXME: Make remaining drivers use dynamic mapping.
30 */
31static struct map_desc s3c64xx_dt_iodesc[] __initdata = {
32 {
33 .virtual = (unsigned long)S3C_VA_SYS,
34 .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
35 .length = SZ_4K,
36 .type = MT_DEVICE,
37 },
38};
39
40static void __init s3c64xx_dt_map_io(void)
41{
42 debug_ll_io_init();
43 iotable_init(s3c64xx_dt_iodesc, ARRAY_SIZE(s3c64xx_dt_iodesc));
44
45 s3c64xx_init_cpu();
46
47 if (!soc_is_s3c64xx())
48 panic("SoC is not S3C64xx!");
49}
50
51static void __init s3c64xx_dt_init_irq(void)
52{
53 of_clk_init(NULL);
54 samsung_wdt_reset_of_init();
55 irqchip_init();
56};
57
58static void __init s3c64xx_dt_init_machine(void)
59{
60 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
61}
62
63static void s3c64xx_dt_restart(enum reboot_mode mode, const char *cmd)
64{
65 if (mode != REBOOT_SOFT)
66 samsung_wdt_reset();
67
68 /* if all else fails, or mode was for soft, jump to 0 */
69 soft_restart(0);
70}
71
72static char const *s3c64xx_dt_compat[] __initdata = {
73 "samsung,s3c6400",
74 "samsung,s3c6410",
75 NULL
76};
77
78DT_MACHINE_START(S3C6400_DT, "Samsung S3C64xx (Flattened Device Tree)")
79 /* Maintainer: Tomasz Figa <tomasz.figa@gmail.com> */
80 .dt_compat = s3c64xx_dt_compat,
81 .map_io = s3c64xx_dt_map_io,
82 .init_irq = s3c64xx_dt_init_irq,
83 .init_machine = s3c64xx_dt_init_machine,
84 .restart = s3c64xx_dt_restart,
85MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 331fe8e58145..3db0c98222f7 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -9,6 +9,10 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12/*
13 * NOTE: Code in this file is not used when booting with Device Tree support.
14 */
15
12#include <linux/kernel.h> 16#include <linux/kernel.h>
13#include <linux/types.h> 17#include <linux/types.h>
14#include <linux/interrupt.h> 18#include <linux/interrupt.h>
@@ -20,6 +24,7 @@
20#include <linux/device.h> 24#include <linux/device.h>
21#include <linux/serial_core.h> 25#include <linux/serial_core.h>
22#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/of.h>
23 28
24#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 30#include <asm/mach/map.h>
@@ -76,6 +81,10 @@ static struct device s3c6400_dev = {
76 81
77static int __init s3c6400_core_init(void) 82static int __init s3c6400_core_init(void)
78{ 83{
84 /* Not applicable when using DT. */
85 if (of_have_populated_dt())
86 return 0;
87
79 return subsys_system_register(&s3c6400_subsys, NULL); 88 return subsys_system_register(&s3c6400_subsys, NULL);
80} 89}
81 90
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 7e6fa125584a..72b2278953a8 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -10,6 +10,10 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13/*
14 * NOTE: Code in this file is not used when booting with Device Tree support.
15 */
16
13#include <linux/kernel.h> 17#include <linux/kernel.h>
14#include <linux/types.h> 18#include <linux/types.h>
15#include <linux/interrupt.h> 19#include <linux/interrupt.h>
@@ -21,6 +25,7 @@
21#include <linux/device.h> 25#include <linux/device.h>
22#include <linux/serial_core.h> 26#include <linux/serial_core.h>
23#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/of.h>
24 29
25#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
26#include <asm/mach/map.h> 31#include <asm/mach/map.h>
@@ -79,6 +84,10 @@ static struct device s3c6410_dev = {
79 84
80static int __init s3c6410_core_init(void) 85static int __init s3c6410_core_init(void)
81{ 86{
87 /* Not applicable when using DT. */
88 if (of_have_populated_dt())
89 return 0;
90
82 return subsys_system_register(&s3c6410_subsys, NULL); 91 return subsys_system_register(&s3c6410_subsys, NULL);
83} 92}
84 93
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index fe1f3e26b88b..616b96e86ad4 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,14 +2,11 @@
2# Makefile for the linux kernel, U8500 machine. 2# Makefile for the linux kernel, U8500 machine.
3# 3#
4 4
5obj-y := cpu.o devices.o devices-common.o \ 5obj-y := cpu.o devices.o id.o timer.o pm.o
6 id.o usb.o timer.o pm.o
7obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o 6obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
8obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o 7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
9obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ 8obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
10 board-mop500-regulators.o \ 9 board-mop500-regulators.o \
11 board-mop500-uib.o board-mop500-stuib.o \
12 board-mop500-u8500uib.o \
13 board-mop500-pins.o \ 10 board-mop500-pins.o \
14 board-mop500-audio.o 11 board-mop500-audio.o
15obj-$(CONFIG_SMP) += platsmp.o headsmp.o 12obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index ec0807247e60..154e15f59702 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -68,40 +68,6 @@ static struct stedma40_chan_cfg msp2_dma_tx = {
68 .phy_channel = 1, 68 .phy_channel = 1,
69}; 69};
70 70
71static struct platform_device *db8500_add_msp_i2s(struct device *parent,
72 int id,
73 resource_size_t base, int irq,
74 struct msp_i2s_platform_data *pdata)
75{
76 struct platform_device *pdev;
77 struct resource res[] = {
78 DEFINE_RES_MEM(base, SZ_4K),
79 DEFINE_RES_IRQ(irq),
80 };
81
82 pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
83 id, irq);
84 pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
85 res, ARRAY_SIZE(res),
86 pdata, sizeof(*pdata));
87 if (!pdev) {
88 pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
89 id);
90 return NULL;
91 }
92
93 return pdev;
94}
95
96/* Platform device for ASoC MOP500 machine */
97static struct platform_device snd_soc_mop500 = {
98 .name = "snd-soc-mop500",
99 .id = 0,
100 .dev = {
101 .platform_data = NULL,
102 },
103};
104
105struct msp_i2s_platform_data msp2_platform_data = { 71struct msp_i2s_platform_data msp2_platform_data = {
106 .id = MSP_I2S_2, 72 .id = MSP_I2S_2,
107 .msp_i2s_dma_rx = &msp2_dma_rx, 73 .msp_i2s_dma_rx = &msp2_dma_rx,
@@ -113,19 +79,3 @@ struct msp_i2s_platform_data msp3_platform_data = {
113 .msp_i2s_dma_rx = &msp1_dma_rx, 79 .msp_i2s_dma_rx = &msp1_dma_rx,
114 .msp_i2s_dma_tx = NULL, 80 .msp_i2s_dma_tx = NULL,
115}; 81};
116
117void mop500_audio_init(struct device *parent)
118{
119 pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
120 platform_device_register(&snd_soc_mop500);
121
122 pr_info("Initialize MSP I2S-devices.\n");
123 db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
124 &msp0_platform_data);
125 db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
126 &msp1_platform_data);
127 db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
128 &msp2_platform_data);
129 db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
130 &msp3_platform_data);
131}
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index b3e61a38e5c8..26600a1c5319 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -65,18 +65,6 @@ struct mmci_platform_data mop500_sdi0_data = {
65#endif 65#endif
66}; 66};
67 67
68static void sdi0_configure(struct device *parent)
69{
70 /* Add the device, force v2 to subrevision 1 */
71 db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
72}
73
74void mop500_sdi_tc35892_init(struct device *parent)
75{
76 mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
77 sdi0_configure(parent);
78}
79
80/* 68/*
81 * SDI1 (SDIO WLAN) 69 * SDI1 (SDIO WLAN)
82 */ 70 */
@@ -178,42 +166,3 @@ struct mmci_platform_data mop500_sdi4_data = {
178 .dma_tx_param = &mop500_sdi4_dma_cfg_tx, 166 .dma_tx_param = &mop500_sdi4_dma_cfg_tx,
179#endif 167#endif
180}; 168};
181
182void __init mop500_sdi_init(struct device *parent)
183{
184 /* PoP:ed eMMC */
185 db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
186 /* On-board eMMC */
187 db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
188
189 /*
190 * On boards with the TC35892 GPIO expander, sdi0 will finally
191 * be added when the TC35892 initializes and calls
192 * mop500_sdi_tc35892_init() above.
193 */
194}
195
196void __init snowball_sdi_init(struct device *parent)
197{
198 /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */
199 mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED;
200 /* On-board eMMC */
201 db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
202 /* External Micro SD slot */
203 mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
204 mop500_sdi0_data.cd_invert = true;
205 sdi0_configure(parent);
206}
207
208void __init hrefv60_sdi_init(struct device *parent)
209{
210 /* PoP:ed eMMC */
211 db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
212 /* On-board eMMC */
213 db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
214 /* External Micro SD slot */
215 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
216 sdi0_configure(parent);
217 /* WLAN SDIO channel */
218 db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
219}
diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c
deleted file mode 100644
index 7e1f294f0434..000000000000
--- a/arch/arm/mach-ux500/board-mop500-stuib.c
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/mfd/stmpe.h>
10#include <linux/input/bu21013.h>
11#include <linux/gpio.h>
12#include <linux/interrupt.h>
13#include <linux/i2c.h>
14#include <linux/input/matrix_keypad.h>
15#include <asm/mach-types.h>
16
17#include "board-mop500.h"
18
19/* STMPE/SKE keypad use this key layout */
20static const unsigned int mop500_keymap[] = {
21 KEY(2, 5, KEY_END),
22 KEY(4, 1, KEY_POWER),
23 KEY(3, 5, KEY_VOLUMEDOWN),
24 KEY(1, 3, KEY_3),
25 KEY(5, 2, KEY_RIGHT),
26 KEY(5, 0, KEY_9),
27
28 KEY(0, 5, KEY_MENU),
29 KEY(7, 6, KEY_ENTER),
30 KEY(4, 5, KEY_0),
31 KEY(6, 7, KEY_2),
32 KEY(3, 4, KEY_UP),
33 KEY(3, 3, KEY_DOWN),
34
35 KEY(6, 4, KEY_SEND),
36 KEY(6, 2, KEY_BACK),
37 KEY(4, 2, KEY_VOLUMEUP),
38 KEY(5, 5, KEY_1),
39 KEY(4, 3, KEY_LEFT),
40 KEY(3, 2, KEY_7),
41};
42
43static const struct matrix_keymap_data mop500_keymap_data = {
44 .keymap = mop500_keymap,
45 .keymap_size = ARRAY_SIZE(mop500_keymap),
46};
47/*
48 * STMPE1601
49 */
50static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
51 .debounce_ms = 64,
52 .scan_count = 8,
53 .no_autorepeat = true,
54 .keymap_data = &mop500_keymap_data,
55};
56
57static struct stmpe_platform_data stmpe1601_data = {
58 .id = 1,
59 .blocks = STMPE_BLOCK_KEYPAD,
60 .irq_trigger = IRQF_TRIGGER_FALLING,
61 .irq_base = MOP500_STMPE1601_IRQ(0),
62 .keypad = &stmpe1601_keypad_data,
63 .autosleep = true,
64 .autosleep_timeout = 1024,
65};
66
67static struct i2c_board_info __initdata mop500_i2c0_devices_stuib[] = {
68 {
69 I2C_BOARD_INFO("stmpe1601", 0x40),
70 .irq = NOMADIK_GPIO_TO_IRQ(218),
71 .platform_data = &stmpe1601_data,
72 .flags = I2C_CLIENT_WAKE,
73 },
74};
75
76/*
77 * BU21013 ROHM touchscreen interface on the STUIBs
78 */
79
80#define TOUCH_GPIO_PIN 84
81
82#define TOUCH_XMAX 384
83#define TOUCH_YMAX 704
84
85#define PRCMU_CLOCK_OCR 0x1CC
86#define TSC_EXT_CLOCK_9_6MHZ 0x840000
87
88static struct bu21013_platform_device tsc_plat_device = {
89 .touch_pin = TOUCH_GPIO_PIN,
90 .touch_x_max = TOUCH_XMAX,
91 .touch_y_max = TOUCH_YMAX,
92 .ext_clk = false,
93 .x_flip = false,
94 .y_flip = true,
95};
96
97static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = {
98 {
99 I2C_BOARD_INFO("bu21013_tp", 0x5C),
100 .platform_data = &tsc_plat_device,
101 },
102 {
103 I2C_BOARD_INFO("bu21013_tp", 0x5D),
104 .platform_data = &tsc_plat_device,
105 },
106};
107
108void __init mop500_stuib_init(void)
109{
110 if (machine_is_hrefv60())
111 tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
112 else
113 tsc_plat_device.cs_pin = GPIO_BU21013_CS;
114
115 mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib,
116 ARRAY_SIZE(mop500_i2c0_devices_stuib));
117
118 mop500_uib_i2c_add(3, u8500_i2c3_devices_stuib,
119 ARRAY_SIZE(u8500_i2c3_devices_stuib));
120}
diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c
deleted file mode 100644
index d397c19570af..000000000000
--- a/arch/arm/mach-ux500/board-mop500-u8500uib.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Board data for the U8500 UIB, also known as the New UIB
5 * License terms: GNU General Public License (GPL), version 2
6 */
7#include <linux/gpio.h>
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/i2c.h>
11#include <linux/interrupt.h>
12#include <linux/mfd/tc3589x.h>
13#include <linux/input/matrix_keypad.h>
14
15#include "irqs.h"
16
17#include "board-mop500.h"
18
19static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
20 {
21 I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
22 .irq = NOMADIK_GPIO_TO_IRQ(84),
23 },
24};
25
26/*
27 * TC35893
28 */
29static const unsigned int u8500_keymap[] = {
30 KEY(3, 1, KEY_END),
31 KEY(4, 1, KEY_POWER),
32 KEY(6, 4, KEY_VOLUMEDOWN),
33 KEY(4, 2, KEY_EMAIL),
34 KEY(3, 3, KEY_RIGHT),
35 KEY(2, 5, KEY_BACKSPACE),
36
37 KEY(6, 7, KEY_MENU),
38 KEY(5, 0, KEY_ENTER),
39 KEY(4, 3, KEY_0),
40 KEY(3, 4, KEY_DOT),
41 KEY(5, 2, KEY_UP),
42 KEY(3, 5, KEY_DOWN),
43
44 KEY(4, 5, KEY_SEND),
45 KEY(0, 5, KEY_BACK),
46 KEY(6, 2, KEY_VOLUMEUP),
47 KEY(1, 3, KEY_SPACE),
48 KEY(7, 6, KEY_LEFT),
49 KEY(5, 5, KEY_SEARCH),
50};
51
52static struct matrix_keymap_data u8500_keymap_data = {
53 .keymap = u8500_keymap,
54 .keymap_size = ARRAY_SIZE(u8500_keymap),
55};
56
57static struct tc3589x_keypad_platform_data tc35893_data = {
58 .krow = TC_KPD_ROWS,
59 .kcol = TC_KPD_COLUMNS,
60 .debounce_period = TC_KPD_DEBOUNCE_PERIOD,
61 .settle_time = TC_KPD_SETTLE_TIME,
62 .irqtype = IRQF_TRIGGER_FALLING,
63 .enable_wakeup = true,
64 .keymap_data = &u8500_keymap_data,
65 .no_autorepeat = true,
66};
67
68static struct tc3589x_platform_data tc3589x_keypad_data = {
69 .block = TC3589x_BLOCK_KEYPAD,
70 .keypad = &tc35893_data,
71 .irq_base = MOP500_EGPIO_IRQ_BASE,
72};
73
74static struct i2c_board_info __initdata mop500_i2c0_devices_u8500[] = {
75 {
76 I2C_BOARD_INFO("tc3589x", 0x44),
77 .platform_data = &tc3589x_keypad_data,
78 .irq = NOMADIK_GPIO_TO_IRQ(218),
79 .flags = I2C_CLIENT_WAKE,
80 },
81};
82
83
84void __init mop500_u8500uib_init(void)
85{
86 mop500_uib_i2c_add(3, mop500_i2c3_devices_u8500,
87 ARRAY_SIZE(mop500_i2c3_devices_u8500));
88
89 mop500_uib_i2c_add(0, mop500_i2c0_devices_u8500,
90 ARRAY_SIZE(mop500_i2c0_devices_u8500));
91
92}
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
deleted file mode 100644
index bdaa422da028..000000000000
--- a/arch/arm/mach-ux500/board-mop500-uib.c
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2
6 */
7
8#define pr_fmt(fmt) "mop500-uib: " fmt
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/i2c.h>
13
14#include "board-mop500.h"
15#include "id.h"
16
17enum mop500_uib {
18 STUIB,
19 U8500UIB,
20};
21
22struct uib {
23 const char *name;
24 const char *option;
25 void (*init)(void);
26};
27
28static struct uib __initdata mop500_uibs[] = {
29 [STUIB] = {
30 .name = "ST-UIB",
31 .option = "stuib",
32 .init = mop500_stuib_init,
33 },
34 [U8500UIB] = {
35 .name = "U8500-UIB",
36 .option = "u8500uib",
37 .init = mop500_u8500uib_init,
38 },
39};
40
41static struct uib *mop500_uib;
42
43static int __init mop500_uib_setup(char *str)
44{
45 int i;
46
47 for (i = 0; i < ARRAY_SIZE(mop500_uibs); i++) {
48 struct uib *uib = &mop500_uibs[i];
49
50 if (!strcmp(str, uib->option)) {
51 mop500_uib = uib;
52 break;
53 }
54 }
55
56 if (i == ARRAY_SIZE(mop500_uibs))
57 pr_err("invalid uib= option (%s)\n", str);
58
59 return 1;
60}
61__setup("uib=", mop500_uib_setup);
62
63/*
64 * The UIBs are detected after the I2C host controllers are registered, so
65 * i2c_register_board_info() can't be used.
66 */
67void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
68 unsigned n)
69{
70 struct i2c_adapter *adap;
71 struct i2c_client *client;
72 int i;
73
74 adap = i2c_get_adapter(busnum);
75 if (!adap) {
76 pr_err("failed to get adapter i2c%d\n", busnum);
77 return;
78 }
79
80 for (i = 0; i < n; i++) {
81 client = i2c_new_device(adap, &info[i]);
82 if (!client)
83 pr_err("failed to register %s to i2c%d\n",
84 info[i].type, busnum);
85 }
86
87 i2c_put_adapter(adap);
88}
89
90static void __init __mop500_uib_init(struct uib *uib, const char *why)
91{
92 pr_info("%s (%s)\n", uib->name, why);
93 uib->init();
94}
95
96/*
97 * Detect the UIB attached based on the presence or absence of i2c devices.
98 */
99int __init mop500_uib_init(void)
100{
101 struct uib *uib = mop500_uib;
102 struct i2c_adapter *i2c0;
103 int ret;
104
105 if (!cpu_is_u8500_family())
106 return -ENODEV;
107
108 if (uib) {
109 __mop500_uib_init(uib, "from uib= boot argument");
110 return 0;
111 }
112
113 i2c0 = i2c_get_adapter(0);
114 if (!i2c0) {
115 __mop500_uib_init(&mop500_uibs[STUIB],
116 "fallback, could not get i2c0");
117 return -ENODEV;
118 }
119
120 /* U8500-UIB has the TC35893 at 0x44 on I2C0, the ST-UIB doesn't. */
121 ret = i2c_smbus_xfer(i2c0, 0x44, 0, I2C_SMBUS_WRITE, 0,
122 I2C_SMBUS_QUICK, NULL);
123 i2c_put_adapter(i2c0);
124
125 if (ret == 0)
126 uib = &mop500_uibs[U8500UIB];
127 else
128 uib = &mop500_uibs[STUIB];
129
130 __mop500_uib_init(uib, "detected");
131
132 return 0;
133}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index ad0806eff762..514d40b625a4 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -14,27 +14,16 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/i2c.h>
18#include <linux/platform_data/i2c-nomadik.h>
19#include <linux/platform_data/db8500_thermal.h> 17#include <linux/platform_data/db8500_thermal.h>
20#include <linux/gpio.h>
21#include <linux/amba/bus.h> 18#include <linux/amba/bus.h>
22#include <linux/amba/pl022.h> 19#include <linux/amba/pl022.h>
23#include <linux/amba/serial.h>
24#include <linux/spi/spi.h>
25#include <linux/mfd/abx500/ab8500.h> 20#include <linux/mfd/abx500/ab8500.h>
26#include <linux/regulator/ab8500.h> 21#include <linux/regulator/ab8500.h>
27#include <linux/regulator/fixed.h> 22#include <linux/regulator/fixed.h>
28#include <linux/regulator/driver.h> 23#include <linux/regulator/driver.h>
29#include <linux/regulator/gpio-regulator.h>
30#include <linux/mfd/tc3589x.h>
31#include <linux/mfd/tps6105x.h> 24#include <linux/mfd/tps6105x.h>
32#include <linux/mfd/abx500/ab8500-gpio.h>
33#include <linux/mfd/abx500/ab8500-codec.h>
34#include <linux/platform_data/leds-lp55xx.h> 25#include <linux/platform_data/leds-lp55xx.h>
35#include <linux/input.h> 26#include <linux/input.h>
36#include <linux/smsc911x.h>
37#include <linux/gpio_keys.h>
38#include <linux/delay.h> 27#include <linux/delay.h>
39#include <linux/leds.h> 28#include <linux/leds.h>
40#include <linux/pinctrl/consumer.h> 29#include <linux/pinctrl/consumer.h>
@@ -46,7 +35,6 @@
46#include "setup.h" 35#include "setup.h"
47#include "devices.h" 36#include "devices.h"
48#include "irqs.h" 37#include "irqs.h"
49#include <linux/platform_data/crypto-ux500.h>
50 38
51#include "ste-dma40-db8500.h" 39#include "ste-dma40-db8500.h"
52#include "db8500-regs.h" 40#include "db8500-regs.h"
@@ -54,401 +42,9 @@
54#include "board-mop500.h" 42#include "board-mop500.h"
55#include "board-mop500-regulators.h" 43#include "board-mop500-regulators.h"
56 44
57static struct gpio_led snowball_led_array[] = {
58 {
59 .name = "user_led",
60 .default_trigger = "heartbeat",
61 .gpio = 142,
62 },
63};
64
65static struct gpio_led_platform_data snowball_led_data = {
66 .leds = snowball_led_array,
67 .num_leds = ARRAY_SIZE(snowball_led_array),
68};
69
70static struct platform_device snowball_led_dev = {
71 .name = "leds-gpio",
72 .dev = {
73 .platform_data = &snowball_led_data,
74 },
75};
76
77static struct fixed_voltage_config snowball_gpio_en_3v3_data = {
78 .supply_name = "EN-3V3",
79 .gpio = SNOWBALL_EN_3V3_ETH_GPIO,
80 .microvolts = 3300000,
81 .enable_high = 1,
82 .init_data = &gpio_en_3v3_regulator,
83 .startup_delay = 5000, /* 1200us */
84};
85
86static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
87 .name = "reg-fixed-voltage",
88 .id = 1,
89 .dev = {
90 .platform_data = &snowball_gpio_en_3v3_data,
91 },
92};
93
94/* Dynamically populated. */
95static struct gpio sdi0_reg_gpios[] = {
96 { 0, GPIOF_OUT_INIT_LOW, "mmci_vsel" },
97};
98
99static struct gpio_regulator_state sdi0_reg_states[] = {
100 { .value = 2900000, .gpios = (0 << 0) },
101 { .value = 1800000, .gpios = (1 << 0) },
102};
103
104static struct gpio_regulator_config sdi0_reg_info = {
105 .supply_name = "ext-mmc-level-shifter",
106 .gpios = sdi0_reg_gpios,
107 .nr_gpios = ARRAY_SIZE(sdi0_reg_gpios),
108 .states = sdi0_reg_states,
109 .nr_states = ARRAY_SIZE(sdi0_reg_states),
110 .type = REGULATOR_VOLTAGE,
111 .enable_high = 1,
112 .enabled_at_boot = 0,
113 .init_data = &sdi0_reg_init_data,
114 .startup_delay = 100,
115};
116
117static struct platform_device sdi0_regulator = {
118 .name = "gpio-regulator",
119 .id = -1,
120 .dev = {
121 .platform_data = &sdi0_reg_info,
122 },
123};
124
125static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
126 .gpio_base = MOP500_AB8500_PIN_GPIO(1),
127};
128
129/* ab8500-codec */
130static struct ab8500_codec_platform_data ab8500_codec_pdata = {
131 .amics = {
132 .mic1_type = AMIC_TYPE_DIFFERENTIAL,
133 .mic2_type = AMIC_TYPE_DIFFERENTIAL,
134 .mic1a_micbias = AMIC_MICBIAS_VAMIC1,
135 .mic1b_micbias = AMIC_MICBIAS_VAMIC1,
136 .mic2_micbias = AMIC_MICBIAS_VAMIC2
137 },
138 .ear_cmv = EAR_CMV_0_95V
139};
140
141static struct gpio_keys_button snowball_key_array[] = {
142 {
143 .gpio = 32,
144 .type = EV_KEY,
145 .code = KEY_1,
146 .desc = "userpb",
147 .active_low = 1,
148 .debounce_interval = 50,
149 .wakeup = 1,
150 },
151 {
152 .gpio = 151,
153 .type = EV_KEY,
154 .code = KEY_2,
155 .desc = "extkb1",
156 .active_low = 1,
157 .debounce_interval = 50,
158 .wakeup = 1,
159 },
160 {
161 .gpio = 152,
162 .type = EV_KEY,
163 .code = KEY_3,
164 .desc = "extkb2",
165 .active_low = 1,
166 .debounce_interval = 50,
167 .wakeup = 1,
168 },
169 {
170 .gpio = 161,
171 .type = EV_KEY,
172 .code = KEY_4,
173 .desc = "extkb3",
174 .active_low = 1,
175 .debounce_interval = 50,
176 .wakeup = 1,
177 },
178 {
179 .gpio = 162,
180 .type = EV_KEY,
181 .code = KEY_5,
182 .desc = "extkb4",
183 .active_low = 1,
184 .debounce_interval = 50,
185 .wakeup = 1,
186 },
187};
188
189static struct gpio_keys_platform_data snowball_key_data = {
190 .buttons = snowball_key_array,
191 .nbuttons = ARRAY_SIZE(snowball_key_array),
192};
193
194static struct platform_device snowball_key_dev = {
195 .name = "gpio-keys",
196 .id = -1,
197 .dev = {
198 .platform_data = &snowball_key_data,
199 }
200};
201
202static struct smsc911x_platform_config snowball_sbnet_cfg = {
203 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
204 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
205 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
206 .shift = 1,
207};
208
209static struct resource sbnet_res[] = {
210 {
211 .name = "smsc911x-memory",
212 .start = (0x5000 << 16),
213 .end = (0x5000 << 16) + 0xffff,
214 .flags = IORESOURCE_MEM,
215 },
216 {
217 .start = NOMADIK_GPIO_TO_IRQ(140),
218 .end = NOMADIK_GPIO_TO_IRQ(140),
219 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
220 },
221};
222
223static struct platform_device snowball_sbnet_dev = {
224 .name = "smsc911x",
225 .num_resources = ARRAY_SIZE(sbnet_res),
226 .resource = sbnet_res,
227 .dev = {
228 .platform_data = &snowball_sbnet_cfg,
229 },
230};
231
232struct ab8500_platform_data ab8500_platdata = { 45struct ab8500_platform_data ab8500_platdata = {
233 .irq_base = MOP500_AB8500_IRQ_BASE, 46 .irq_base = MOP500_AB8500_IRQ_BASE,
234 .regulator = &ab8500_regulator_plat_data, 47 .regulator = &ab8500_regulator_plat_data,
235 .gpio = &ab8500_gpio_pdata,
236 .codec = &ab8500_codec_pdata,
237};
238
239static struct platform_device u8500_cpufreq_cooling_device = {
240 .name = "db8500-cpufreq-cooling",
241};
242
243/*
244 * TPS61052
245 */
246
247static struct tps6105x_platform_data mop500_tps61052_data = {
248 .mode = TPS6105X_MODE_VOLTAGE,
249 .regulator_data = &tps61052_regulator,
250};
251
252/*
253 * TC35892
254 */
255
256static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base)
257{
258 struct device *parent = NULL;
259#if 0
260 /* FIXME: Is the sdi actually part of tc3589x? */
261 parent = tc3589x->dev;
262#endif
263 mop500_sdi_tc35892_init(parent);
264}
265
266static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = {
267 .gpio_base = MOP500_EGPIO(0),
268 .setup = mop500_tc35892_init,
269};
270
271static struct tc3589x_platform_data mop500_tc35892_data = {
272 .block = TC3589x_BLOCK_GPIO,
273 .gpio = &mop500_tc35892_gpio_data,
274 .irq_base = MOP500_EGPIO_IRQ_BASE,
275};
276
277static struct lp55xx_led_config lp5521_pri_led[] = {
278 [0] = {
279 .chan_nr = 0,
280 .led_current = 0x2f,
281 .max_current = 0x5f,
282 },
283 [1] = {
284 .chan_nr = 1,
285 .led_current = 0x2f,
286 .max_current = 0x5f,
287 },
288 [2] = {
289 .chan_nr = 2,
290 .led_current = 0x2f,
291 .max_current = 0x5f,
292 },
293};
294
295static struct lp55xx_platform_data __initdata lp5521_pri_data = {
296 .label = "lp5521_pri",
297 .led_config = &lp5521_pri_led[0],
298 .num_channels = 3,
299 .clock_mode = LP55XX_CLOCK_EXT,
300};
301
302static struct lp55xx_led_config lp5521_sec_led[] = {
303 [0] = {
304 .chan_nr = 0,
305 .led_current = 0x2f,
306 .max_current = 0x5f,
307 },
308 [1] = {
309 .chan_nr = 1,
310 .led_current = 0x2f,
311 .max_current = 0x5f,
312 },
313 [2] = {
314 .chan_nr = 2,
315 .led_current = 0x2f,
316 .max_current = 0x5f,
317 },
318};
319
320static struct lp55xx_platform_data __initdata lp5521_sec_data = {
321 .label = "lp5521_sec",
322 .led_config = &lp5521_sec_led[0],
323 .num_channels = 3,
324 .clock_mode = LP55XX_CLOCK_EXT,
325};
326
327/* I2C0 devices only available on the first HREF/MOP500 */
328static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
329 {
330 I2C_BOARD_INFO("tc3589x", 0x42),
331 .irq = NOMADIK_GPIO_TO_IRQ(217),
332 .platform_data = &mop500_tc35892_data,
333 },
334 {
335 I2C_BOARD_INFO("tps61052", 0x33),
336 .platform_data = &mop500_tps61052_data,
337 },
338};
339
340static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
341 {
342 /* lp5521 LED driver, 1st device */
343 I2C_BOARD_INFO("lp5521", 0x33),
344 .platform_data = &lp5521_pri_data,
345 },
346 {
347 /* lp5521 LED driver, 2st device */
348 I2C_BOARD_INFO("lp5521", 0x34),
349 .platform_data = &lp5521_sec_data,
350 },
351 {
352 /* Light sensor Rohm BH1780GLI */
353 I2C_BOARD_INFO("bh1780", 0x29),
354 },
355};
356
357static int __init mop500_i2c_board_init(void)
358{
359 if (machine_is_u8500())
360 mop500_uib_i2c_add(0, mop500_i2c0_devices,
361 ARRAY_SIZE(mop500_i2c0_devices));
362 mop500_uib_i2c_add(2, mop500_i2c2_devices,
363 ARRAY_SIZE(mop500_i2c2_devices));
364 return 0;
365}
366device_initcall(mop500_i2c_board_init);
367
368static void __init mop500_i2c_init(struct device *parent)
369{
370 db8500_add_i2c0(parent, NULL);
371 db8500_add_i2c1(parent, NULL);
372 db8500_add_i2c2(parent, NULL);
373 db8500_add_i2c3(parent, NULL);
374}
375
376static struct gpio_keys_button mop500_gpio_keys[] = {
377 {
378 .desc = "SFH7741 Proximity Sensor",
379 .type = EV_SW,
380 .code = SW_FRONT_PROXIMITY,
381 .active_low = 0,
382 .can_disable = 1,
383 }
384};
385
386static struct regulator *prox_regulator;
387static int mop500_prox_activate(struct device *dev);
388static void mop500_prox_deactivate(struct device *dev);
389
390static struct gpio_keys_platform_data mop500_gpio_keys_data = {
391 .buttons = mop500_gpio_keys,
392 .nbuttons = ARRAY_SIZE(mop500_gpio_keys),
393 .enable = mop500_prox_activate,
394 .disable = mop500_prox_deactivate,
395};
396
397static struct platform_device mop500_gpio_keys_device = {
398 .name = "gpio-keys",
399 .id = 0,
400 .dev = {
401 .platform_data = &mop500_gpio_keys_data,
402 },
403};
404
405static int mop500_prox_activate(struct device *dev)
406{
407 prox_regulator = regulator_get(&mop500_gpio_keys_device.dev,
408 "vcc");
409 if (IS_ERR(prox_regulator)) {
410 dev_err(&mop500_gpio_keys_device.dev,
411 "no regulator\n");
412 return PTR_ERR(prox_regulator);
413 }
414
415 return regulator_enable(prox_regulator);
416}
417
418static void mop500_prox_deactivate(struct device *dev)
419{
420 regulator_disable(prox_regulator);
421 regulator_put(prox_regulator);
422}
423
424static struct cryp_platform_data u8500_cryp1_platform_data = {
425 .mem_to_engine = {
426 .dir = DMA_MEM_TO_DEV,
427 .dev_type = DB8500_DMA_DEV48_CAC1,
428 .mode = STEDMA40_MODE_LOGICAL,
429 },
430 .engine_to_mem = {
431 .dir = DMA_DEV_TO_MEM,
432 .dev_type = DB8500_DMA_DEV48_CAC1,
433 .mode = STEDMA40_MODE_LOGICAL,
434 }
435};
436
437static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
438 .dir = DMA_MEM_TO_DEV,
439 .dev_type = DB8500_DMA_DEV50_HAC1_TX,
440 .mode = STEDMA40_MODE_LOGICAL,
441};
442
443static struct hash_platform_data u8500_hash1_platform_data = {
444 .mem_to_engine = &u8500_hash_dma_cfg_tx,
445 .dma_filter = stedma40_filter,
446};
447
448/* add any platform devices here - TODO */
449static struct platform_device *mop500_platform_devs[] __initdata = {
450 &mop500_gpio_keys_device,
451 &sdi0_regulator,
452}; 48};
453 49
454#ifdef CONFIG_STE_DMA40 50#ifdef CONFIG_STE_DMA40
@@ -480,236 +76,3 @@ struct pl022_ssp_controller ssp0_plat = {
480 */ 76 */
481 .num_chipselect = 5, 77 .num_chipselect = 5,
482}; 78};
483
484static void __init mop500_spi_init(struct device *parent)
485{
486 db8500_add_ssp0(parent, &ssp0_plat);
487}
488
489#ifdef CONFIG_STE_DMA40
490static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
491 .mode = STEDMA40_MODE_LOGICAL,
492 .dir = DMA_DEV_TO_MEM,
493 .dev_type = DB8500_DMA_DEV13_UART0,
494};
495
496static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
497 .mode = STEDMA40_MODE_LOGICAL,
498 .dir = DMA_MEM_TO_DEV,
499 .dev_type = DB8500_DMA_DEV13_UART0,
500};
501
502static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
503 .mode = STEDMA40_MODE_LOGICAL,
504 .dir = DMA_DEV_TO_MEM,
505 .dev_type = DB8500_DMA_DEV12_UART1,
506};
507
508static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
509 .mode = STEDMA40_MODE_LOGICAL,
510 .dir = DMA_MEM_TO_DEV,
511 .dev_type = DB8500_DMA_DEV12_UART1,
512};
513
514static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
515 .mode = STEDMA40_MODE_LOGICAL,
516 .dir = DMA_DEV_TO_MEM,
517 .dev_type = DB8500_DMA_DEV11_UART2,
518};
519
520static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
521 .mode = STEDMA40_MODE_LOGICAL,
522 .dir = DMA_MEM_TO_DEV,
523 .dev_type = DB8500_DMA_DEV11_UART2,
524};
525#endif
526
527struct amba_pl011_data uart0_plat = {
528#ifdef CONFIG_STE_DMA40
529 .dma_filter = stedma40_filter,
530 .dma_rx_param = &uart0_dma_cfg_rx,
531 .dma_tx_param = &uart0_dma_cfg_tx,
532#endif
533};
534
535struct amba_pl011_data uart1_plat = {
536#ifdef CONFIG_STE_DMA40
537 .dma_filter = stedma40_filter,
538 .dma_rx_param = &uart1_dma_cfg_rx,
539 .dma_tx_param = &uart1_dma_cfg_tx,
540#endif
541};
542
543struct amba_pl011_data uart2_plat = {
544#ifdef CONFIG_STE_DMA40
545 .dma_filter = stedma40_filter,
546 .dma_rx_param = &uart2_dma_cfg_rx,
547 .dma_tx_param = &uart2_dma_cfg_tx,
548#endif
549};
550
551static void __init mop500_uart_init(struct device *parent)
552{
553 db8500_add_uart0(parent, &uart0_plat);
554 db8500_add_uart1(parent, &uart1_plat);
555 db8500_add_uart2(parent, &uart2_plat);
556}
557
558static void __init u8500_cryp1_hash1_init(struct device *parent)
559{
560 db8500_add_cryp1(parent, &u8500_cryp1_platform_data);
561 db8500_add_hash1(parent, &u8500_hash1_platform_data);
562}
563
564static struct platform_device *snowball_platform_devs[] __initdata = {
565 &snowball_led_dev,
566 &snowball_key_dev,
567 &snowball_sbnet_dev,
568 &snowball_gpio_en_3v3_regulator_dev,
569 &u8500_cpufreq_cooling_device,
570 &sdi0_regulator,
571};
572
573static void __init mop500_init_machine(void)
574{
575 struct device *parent = NULL;
576 int i;
577
578 platform_device_register(&db8500_prcmu_device);
579 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
580
581 sdi0_reg_info.enable_gpio = GPIO_SDMMC_EN;
582 sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL;
583
584 mop500_pinmaps_init();
585 parent = u8500_init_devices();
586
587 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
588 mop500_platform_devs[i]->dev.parent = parent;
589
590 platform_add_devices(mop500_platform_devs,
591 ARRAY_SIZE(mop500_platform_devs));
592
593 mop500_i2c_init(parent);
594 mop500_sdi_init(parent);
595 mop500_spi_init(parent);
596 mop500_audio_init(parent);
597 mop500_uart_init(parent);
598 u8500_cryp1_hash1_init(parent);
599
600 /* This board has full regulator constraints */
601 regulator_has_full_constraints();
602}
603
604
605static void __init snowball_init_machine(void)
606{
607 struct device *parent = NULL;
608 int i;
609
610 platform_device_register(&db8500_prcmu_device);
611
612 sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO;
613 sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO;
614
615 snowball_pinmaps_init();
616 parent = u8500_init_devices();
617
618 for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
619 snowball_platform_devs[i]->dev.parent = parent;
620
621 platform_add_devices(snowball_platform_devs,
622 ARRAY_SIZE(snowball_platform_devs));
623
624 mop500_i2c_init(parent);
625 snowball_sdi_init(parent);
626 mop500_spi_init(parent);
627 mop500_audio_init(parent);
628 mop500_uart_init(parent);
629
630 u8500_cryp1_hash1_init(parent);
631
632 /* This board has full regulator constraints */
633 regulator_has_full_constraints();
634}
635
636static void __init hrefv60_init_machine(void)
637{
638 struct device *parent = NULL;
639 int i;
640
641 platform_device_register(&db8500_prcmu_device);
642 /*
643 * The HREFv60 board removed a GPIO expander and routed
644 * all these GPIO pins to the internal GPIO controller
645 * instead.
646 */
647 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
648
649 sdi0_reg_info.enable_gpio = HREFV60_SDMMC_EN_GPIO;
650 sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO;
651
652 hrefv60_pinmaps_init();
653 parent = u8500_init_devices();
654
655 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
656 mop500_platform_devs[i]->dev.parent = parent;
657
658 platform_add_devices(mop500_platform_devs,
659 ARRAY_SIZE(mop500_platform_devs));
660
661 mop500_i2c_init(parent);
662 hrefv60_sdi_init(parent);
663 mop500_spi_init(parent);
664 mop500_audio_init(parent);
665 mop500_uart_init(parent);
666
667 /* This board has full regulator constraints */
668 regulator_has_full_constraints();
669}
670
671MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
672 /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
673 .atag_offset = 0x100,
674 .smp = smp_ops(ux500_smp_ops),
675 .map_io = u8500_map_io,
676 .init_irq = ux500_init_irq,
677 /* we re-use nomadik timer here */
678 .init_time = ux500_timer_init,
679 .init_machine = mop500_init_machine,
680 .init_late = ux500_init_late,
681 .restart = ux500_restart,
682MACHINE_END
683
684MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520")
685 .atag_offset = 0x100,
686 .map_io = u8500_map_io,
687 .init_irq = ux500_init_irq,
688 .init_time = ux500_timer_init,
689 .init_machine = mop500_init_machine,
690 .init_late = ux500_init_late,
691 .restart = ux500_restart,
692MACHINE_END
693
694MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
695 .atag_offset = 0x100,
696 .smp = smp_ops(ux500_smp_ops),
697 .map_io = u8500_map_io,
698 .init_irq = ux500_init_irq,
699 .init_time = ux500_timer_init,
700 .init_machine = hrefv60_init_machine,
701 .init_late = ux500_init_late,
702 .restart = ux500_restart,
703MACHINE_END
704
705MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
706 .atag_offset = 0x100,
707 .smp = smp_ops(ux500_smp_ops),
708 .map_io = u8500_map_io,
709 .init_irq = ux500_init_irq,
710 /* we re-use nomadik timer here */
711 .init_time = ux500_timer_init,
712 .init_machine = snowball_init_machine,
713 .init_late = NULL,
714 .restart = ux500_restart,
715MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index d6fab166cbf1..511d6febbe99 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -79,7 +79,6 @@
79#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */ 79#define SNOWBALL_EN_3V3_ETH_GPIO MOP500_AB8500_PIN_GPIO(26) /* GPIO26 */
80 80
81struct device; 81struct device;
82struct i2c_board_info;
83extern struct mmci_platform_data mop500_sdi0_data; 82extern struct mmci_platform_data mop500_sdi0_data;
84extern struct mmci_platform_data mop500_sdi1_data; 83extern struct mmci_platform_data mop500_sdi1_data;
85extern struct mmci_platform_data mop500_sdi2_data; 84extern struct mmci_platform_data mop500_sdi2_data;
@@ -88,25 +87,10 @@ extern struct msp_i2s_platform_data msp0_platform_data;
88extern struct msp_i2s_platform_data msp1_platform_data; 87extern struct msp_i2s_platform_data msp1_platform_data;
89extern struct msp_i2s_platform_data msp2_platform_data; 88extern struct msp_i2s_platform_data msp2_platform_data;
90extern struct msp_i2s_platform_data msp3_platform_data; 89extern struct msp_i2s_platform_data msp3_platform_data;
91extern struct arm_pmu_platdata db8500_pmu_platdata;
92extern struct amba_pl011_data uart0_plat;
93extern struct amba_pl011_data uart1_plat;
94extern struct amba_pl011_data uart2_plat;
95extern struct pl022_ssp_controller ssp0_plat; 90extern struct pl022_ssp_controller ssp0_plat;
96extern struct stedma40_platform_data dma40_plat_data;
97 91
98extern void mop500_sdi_init(struct device *parent);
99extern void snowball_sdi_init(struct device *parent);
100extern void hrefv60_sdi_init(struct device *parent);
101extern void mop500_sdi_tc35892_init(struct device *parent);
102void __init mop500_u8500uib_init(void);
103void __init mop500_stuib_init(void);
104void __init mop500_pinmaps_init(void); 92void __init mop500_pinmaps_init(void);
105void __init snowball_pinmaps_init(void); 93void __init snowball_pinmaps_init(void);
106void __init hrefv60_pinmaps_init(void); 94void __init hrefv60_pinmaps_init(void);
107void mop500_audio_init(struct device *parent);
108 95
109int __init mop500_uib_init(void);
110void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
111 unsigned n);
112#endif 96#endif
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 301c3460d96a..2e85c1e72535 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -32,7 +32,6 @@
32#include "irqs.h" 32#include "irqs.h"
33 33
34#include "devices-db8500.h" 34#include "devices-db8500.h"
35#include "ste-dma40-db8500.h"
36#include "db8500-regs.h" 35#include "db8500-regs.h"
37#include "board-mop500.h" 36#include "board-mop500.h"
38#include "id.h" 37#include "id.h"
@@ -93,14 +92,6 @@ void __init u8500_map_io(void)
93 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 92 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
94} 93}
95 94
96static struct resource db8500_pmu_resources[] = {
97 [0] = {
98 .start = IRQ_DB8500_PMU,
99 .end = IRQ_DB8500_PMU,
100 .flags = IORESOURCE_IRQ,
101 },
102};
103
104/* 95/*
105 * The PMU IRQ lines of two cores are wired together into a single interrupt. 96 * The PMU IRQ lines of two cores are wired together into a single interrupt.
106 * Bounce the interrupt to the other core if it's not ours. 97 * Bounce the interrupt to the other core if it's not ours.
@@ -125,54 +116,6 @@ struct arm_pmu_platdata db8500_pmu_platdata = {
125 .handle_irq = db8500_pmu_handler, 116 .handle_irq = db8500_pmu_handler,
126}; 117};
127 118
128static struct platform_device db8500_pmu_device = {
129 .name = "arm-pmu",
130 .id = -1,
131 .num_resources = ARRAY_SIZE(db8500_pmu_resources),
132 .resource = db8500_pmu_resources,
133 .dev.platform_data = &db8500_pmu_platdata,
134};
135
136static struct platform_device *platform_devs[] __initdata = {
137 &u8500_dma40_device,
138 &db8500_pmu_device,
139};
140
141static resource_size_t __initdata db8500_gpio_base[] = {
142 U8500_GPIOBANK0_BASE,
143 U8500_GPIOBANK1_BASE,
144 U8500_GPIOBANK2_BASE,
145 U8500_GPIOBANK3_BASE,
146 U8500_GPIOBANK4_BASE,
147 U8500_GPIOBANK5_BASE,
148 U8500_GPIOBANK6_BASE,
149 U8500_GPIOBANK7_BASE,
150 U8500_GPIOBANK8_BASE,
151};
152
153static void __init db8500_add_gpios(struct device *parent)
154{
155 struct nmk_gpio_platform_data pdata = {
156 .supports_sleepmode = true,
157 };
158
159 dbx500_add_gpios(parent, db8500_gpio_base,
160 ARRAY_SIZE(db8500_gpio_base),
161 IRQ_DB8500_GPIO0, &pdata);
162 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
163}
164
165static int usb_db8500_dma_cfg[] = {
166 DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
167 DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
168 DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
169 DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
170 DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
171 DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
172 DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
173 DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
174};
175
176static const char *db8500_read_soc_id(void) 119static const char *db8500_read_soc_id(void)
177{ 120{
178 void __iomem *uid = __io_address(U8500_BB_UID_BASE); 121 void __iomem *uid = __io_address(U8500_BB_UID_BASE);
@@ -192,60 +135,22 @@ static struct device * __init db8500_soc_device_init(void)
192 return ux500_soc_device_init(soc_id); 135 return ux500_soc_device_init(soc_id);
193} 136}
194 137
195/*
196 * This function is called from the board init
197 */
198struct device * __init u8500_init_devices(void)
199{
200 struct device *parent;
201 int i;
202
203 parent = db8500_soc_device_init();
204
205 db8500_add_rtc(parent);
206 db8500_add_gpios(parent);
207 db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
208
209 for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
210 platform_devs[i]->dev.parent = parent;
211
212 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
213
214 return parent;
215}
216
217#ifdef CONFIG_MACH_UX500_DT 138#ifdef CONFIG_MACH_UX500_DT
218static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { 139static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
219 /* Requires call-back bindings. */ 140 /* Requires call-back bindings. */
220 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), 141 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
221 /* Requires DMA bindings. */ 142 /* Requires DMA bindings. */
222 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL), 143 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
223 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL), 144 "ux500-msp-i2s.0", &msp0_platform_data),
224 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL), 145 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
225 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 146 "ux500-msp-i2s.1", &msp1_platform_data),
226 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", NULL), 147 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
227 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", NULL), 148 "ux500-msp-i2s.2", &msp2_platform_data),
228 OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", NULL), 149 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
229 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", NULL), 150 "ux500-msp-i2s.3", &msp3_platform_data),
230 /* Requires clock name bindings. */ 151 /* Requires non-DT:able platform data. */
231 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
232 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
233 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
234 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
235 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
236 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
237 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
238 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
239 OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
240 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
241 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
242 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
243 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
244 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
245 OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
246 OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", 152 OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
247 &db8500_prcmu_pdata), 153 &db8500_prcmu_pdata),
248 OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
249 OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL), 154 OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
250 OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL), 155 OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
251 OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0", 156 OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
@@ -253,17 +158,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
253 /* Requires device name bindings. */ 158 /* Requires device name bindings. */
254 OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE, 159 OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
255 "pinctrl-db8500", NULL), 160 "pinctrl-db8500", NULL),
256 /* Requires clock name and DMA bindings. */
257 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
258 "ux500-msp-i2s.0", &msp0_platform_data),
259 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
260 "ux500-msp-i2s.1", &msp1_platform_data),
261 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
262 "ux500-msp-i2s.2", &msp2_platform_data),
263 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
264 "ux500-msp-i2s.3", &msp3_platform_data),
265 /* Requires clock name bindings and channel address lookup table. */
266 OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
267 {}, 161 {},
268}; 162};
269 163
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 5d7eebcabc63..f84d4397896b 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -78,9 +78,17 @@ void __init ux500_init_irq(void)
78 if (cpu_is_u8500_family()) { 78 if (cpu_is_u8500_family()) {
79 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); 79 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
80 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); 80 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
81 u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, 81
82 U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, 82 if (of_have_populated_dt())
83 U8500_CLKRST6_BASE); 83 u8500_of_clk_init(U8500_CLKRST1_BASE,
84 U8500_CLKRST2_BASE,
85 U8500_CLKRST3_BASE,
86 U8500_CLKRST5_BASE,
87 U8500_CLKRST6_BASE);
88 else
89 u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
90 U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
91 U8500_CLKRST6_BASE);
84 } else if (cpu_is_u9540()) { 92 } else if (cpu_is_u9540()) {
85 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); 93 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
86 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); 94 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
@@ -96,11 +104,6 @@ void __init ux500_init_irq(void)
96 } 104 }
97} 105}
98 106
99void __init ux500_init_late(void)
100{
101 mop500_uib_init();
102}
103
104static const char * __init ux500_get_machine(void) 107static const char * __init ux500_get_machine(void)
105{ 108{
106 return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber()); 109 return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber());
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
deleted file mode 100644
index f71b3d7bd4fb..000000000000
--- a/arch/arm/mach-ux500/devices-common.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#include <linux/kernel.h>
9#include <linux/dma-mapping.h>
10#include <linux/err.h>
11#include <linux/irq.h>
12#include <linux/slab.h>
13#include <linux/platform_device.h>
14#include <linux/platform_data/pinctrl-nomadik.h>
15
16#include "irqs.h"
17
18#include "devices-common.h"
19
20static struct platform_device *
21dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq,
22 struct nmk_gpio_platform_data *pdata)
23{
24 struct resource resources[] = {
25 {
26 .start = addr,
27 .end = addr + 127,
28 .flags = IORESOURCE_MEM,
29 },
30 {
31 .start = irq,
32 .end = irq,
33 .flags = IORESOURCE_IRQ,
34 }
35 };
36
37 return platform_device_register_resndata(
38 parent,
39 "gpio",
40 id,
41 resources,
42 ARRAY_SIZE(resources),
43 pdata,
44 sizeof(*pdata));
45}
46
47void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
48 int irq, struct nmk_gpio_platform_data *pdata)
49{
50 int first = 0;
51 int i;
52
53 for (i = 0; i < num; i++, first += 32, irq++) {
54 pdata->first_gpio = first;
55 pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
56 pdata->num_gpio = 32;
57
58 dbx500_add_gpio(parent, i, base[i], irq, pdata);
59 }
60}
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
deleted file mode 100644
index 96fa4ac89e2e..000000000000
--- a/arch/arm/mach-ux500/devices-common.h
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __DEVICES_COMMON_H
9#define __DEVICES_COMMON_H
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/sys_soc.h>
14#include <linux/amba/bus.h>
15#include <linux/platform_data/i2c-nomadik.h>
16#include <linux/platform_data/crypto-ux500.h>
17
18struct spi_master_cntlr;
19
20static inline struct amba_device *
21dbx500_add_msp_spi(struct device *parent, const char *name,
22 resource_size_t base, int irq,
23 struct spi_master_cntlr *pdata)
24{
25 return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
26 pdata, 0);
27}
28
29static inline struct amba_device *
30dbx500_add_spi(struct device *parent, const char *name, resource_size_t base,
31 int irq, struct spi_master_cntlr *pdata,
32 u32 periphid)
33{
34 return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
35 pdata, periphid);
36}
37
38struct mmci_platform_data;
39
40static inline struct amba_device *
41dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base,
42 int irq, struct mmci_platform_data *pdata, u32 periphid)
43{
44 return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
45 pdata, periphid);
46}
47
48struct amba_pl011_data;
49
50static inline struct amba_device *
51dbx500_add_uart(struct device *parent, const char *name, resource_size_t base,
52 int irq, struct amba_pl011_data *pdata)
53{
54 return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
55}
56
57struct nmk_i2c_controller;
58
59static inline struct amba_device *
60dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq,
61 struct nmk_i2c_controller *data)
62{
63 /* Conjure a name similar to what the platform device used to have */
64 char name[16];
65
66 snprintf(name, sizeof(name), "nmk-i2c.%d", id);
67 return amba_apb_device_add(parent, name, base, SZ_4K, irq, 0, data, 0);
68}
69
70static inline struct amba_device *
71dbx500_add_rtc(struct device *parent, resource_size_t base, int irq)
72{
73 return amba_apb_device_add(parent, "rtc-pl031", base, SZ_4K, irq,
74 0, NULL, 0);
75}
76
77struct cryp_platform_data;
78
79static inline struct platform_device *
80dbx500_add_cryp1(struct device *parent, int id, resource_size_t base, int irq,
81 struct cryp_platform_data *pdata)
82{
83 struct resource res[] = {
84 DEFINE_RES_MEM(base, SZ_4K),
85 DEFINE_RES_IRQ(irq),
86 };
87
88 struct platform_device_info pdevinfo = {
89 .parent = parent,
90 .name = "cryp1",
91 .id = id,
92 .res = res,
93 .num_res = ARRAY_SIZE(res),
94 .data = pdata,
95 .size_data = sizeof(*pdata),
96 .dma_mask = DMA_BIT_MASK(32),
97 };
98
99 return platform_device_register_full(&pdevinfo);
100}
101
102struct hash_platform_data;
103
104static inline struct platform_device *
105dbx500_add_hash1(struct device *parent, int id, resource_size_t base,
106 struct hash_platform_data *pdata)
107{
108 struct resource res[] = {
109 DEFINE_RES_MEM(base, SZ_4K),
110 };
111
112 struct platform_device_info pdevinfo = {
113 .parent = parent,
114 .name = "hash1",
115 .id = id,
116 .res = res,
117 .num_res = ARRAY_SIZE(res),
118 .data = pdata,
119 .size_data = sizeof(*pdata),
120 .dma_mask = DMA_BIT_MASK(32),
121 };
122
123 return platform_device_register_full(&pdevinfo);
124}
125
126struct nmk_gpio_platform_data;
127
128void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
129 int irq, struct nmk_gpio_platform_data *pdata);
130
131static inline void
132dbx500_add_pinctrl(struct device *parent, const char *name,
133 resource_size_t base)
134{
135 struct resource res[] = {
136 DEFINE_RES_MEM(base, SZ_8K),
137 };
138 struct platform_device_info pdevinfo = {
139 .parent = parent,
140 .name = name,
141 .id = -1,
142 .res = res,
143 .num_res = ARRAY_SIZE(res),
144 };
145
146 platform_device_register_full(&pdevinfo);
147}
148
149#endif
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index bc316062e0c2..c59f89d058ff 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -9,10 +9,8 @@
9#include <linux/platform_device.h> 9#include <linux/platform_device.h>
10#include <linux/interrupt.h> 10#include <linux/interrupt.h>
11#include <linux/io.h> 11#include <linux/io.h>
12#include <linux/gpio.h>
13#include <linux/amba/bus.h> 12#include <linux/amba/bus.h>
14#include <linux/amba/pl022.h> 13#include <linux/amba/pl022.h>
15#include <linux/platform_data/dma-ste-dma40.h>
16#include <linux/mfd/dbx500-prcmu.h> 14#include <linux/mfd/dbx500-prcmu.h>
17 15
18#include "setup.h" 16#include "setup.h"
@@ -20,62 +18,6 @@
20 18
21#include "db8500-regs.h" 19#include "db8500-regs.h"
22#include "devices-db8500.h" 20#include "devices-db8500.h"
23#include "ste-dma40-db8500.h"
24
25static struct resource dma40_resources[] = {
26 [0] = {
27 .start = U8500_DMA_BASE,
28 .end = U8500_DMA_BASE + SZ_4K - 1,
29 .flags = IORESOURCE_MEM,
30 .name = "base",
31 },
32 [1] = {
33 .start = U8500_DMA_LCPA_BASE,
34 .end = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
35 .flags = IORESOURCE_MEM,
36 .name = "lcpa",
37 },
38 [2] = {
39 .start = IRQ_DB8500_DMA,
40 .end = IRQ_DB8500_DMA,
41 .flags = IORESOURCE_IRQ,
42 }
43};
44
45struct stedma40_platform_data dma40_plat_data = {
46 .disabled_channels = {-1},
47};
48
49struct platform_device u8500_dma40_device = {
50 .dev = {
51 .platform_data = &dma40_plat_data,
52 .coherent_dma_mask = DMA_BIT_MASK(32),
53 },
54 .name = "dma40",
55 .id = 0,
56 .num_resources = ARRAY_SIZE(dma40_resources),
57 .resource = dma40_resources
58};
59
60struct resource keypad_resources[] = {
61 [0] = {
62 .start = U8500_SKE_BASE,
63 .end = U8500_SKE_BASE + SZ_4K - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = IRQ_DB8500_KB,
68 .end = IRQ_DB8500_KB,
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73struct platform_device u8500_ske_keypad_device = {
74 .name = "nmk-ske-keypad",
75 .id = -1,
76 .num_resources = ARRAY_SIZE(keypad_resources),
77 .resource = keypad_resources,
78};
79 21
80struct prcmu_pdata db8500_prcmu_pdata = { 22struct prcmu_pdata db8500_prcmu_pdata = {
81 .ab_platdata = &ab8500_platdata, 23 .ab_platdata = &ab8500_platdata,
@@ -84,39 +26,3 @@ struct prcmu_pdata db8500_prcmu_pdata = {
84 .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, 26 .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
85 .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, 27 .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
86}; 28};
87
88static struct resource db8500_prcmu_res[] = {
89 {
90 .name = "prcmu",
91 .start = U8500_PRCMU_BASE,
92 .end = U8500_PRCMU_BASE + SZ_8K - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .name = "prcmu-tcdm",
97 .start = U8500_PRCMU_TCDM_BASE,
98 .end = U8500_PRCMU_TCDM_BASE + SZ_4K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 {
102 .name = "irq",
103 .start = IRQ_DB8500_PRCMU1,
104 .end = IRQ_DB8500_PRCMU1,
105 .flags = IORESOURCE_IRQ,
106 },
107 {
108 .name = "prcmu-tcpm",
109 .start = U8500_PRCMU_TCPM_BASE,
110 .end = U8500_PRCMU_TCPM_BASE + SZ_32K - 1,
111 .flags = IORESOURCE_MEM,
112 },
113};
114
115struct platform_device db8500_prcmu_device = {
116 .name = "db8500-prcmu",
117 .resource = db8500_prcmu_res,
118 .num_resources = ARRAY_SIZE(db8500_prcmu_res),
119 .dev = {
120 .platform_data = &db8500_prcmu_pdata,
121 },
122};
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 321998320f98..b8ffc9979bb2 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -8,122 +8,12 @@
8#ifndef __DEVICES_DB8500_H 8#ifndef __DEVICES_DB8500_H
9#define __DEVICES_DB8500_H 9#define __DEVICES_DB8500_H
10 10
11#include <linux/platform_data/usb-musb-ux500.h>
12#include "irqs.h" 11#include "irqs.h"
13#include "db8500-regs.h" 12#include "db8500-regs.h"
14#include "devices-common.h"
15 13
16struct ske_keypad_platform_data;
17struct pl022_ssp_controller;
18struct platform_device; 14struct platform_device;
19 15
20extern struct ab8500_platform_data ab8500_platdata; 16extern struct ab8500_platform_data ab8500_platdata;
21extern struct prcmu_pdata db8500_prcmu_pdata; 17extern struct prcmu_pdata db8500_prcmu_pdata;
22extern struct platform_device db8500_prcmu_device;
23 18
24static inline struct platform_device *
25db8500_add_ske_keypad(struct device *parent,
26 struct ske_keypad_platform_data *pdata,
27 size_t size)
28{
29 struct resource resources[] = {
30 DEFINE_RES_MEM(U8500_SKE_BASE, SZ_4K),
31 DEFINE_RES_IRQ(IRQ_DB8500_KB),
32 };
33
34 return platform_device_register_resndata(parent, "nmk-ske-keypad", -1,
35 resources, 2, pdata, size);
36}
37
38static inline struct amba_device *
39db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
40 int irq, struct pl022_ssp_controller *pdata)
41{
42 return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
43}
44
45#define db8500_add_i2c0(parent, pdata) \
46 dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
47#define db8500_add_i2c1(parent, pdata) \
48 dbx500_add_i2c(parent, 1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata)
49#define db8500_add_i2c2(parent, pdata) \
50 dbx500_add_i2c(parent, 2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata)
51#define db8500_add_i2c3(parent, pdata) \
52 dbx500_add_i2c(parent, 3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata)
53#define db8500_add_i2c4(parent, pdata) \
54 dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
55
56#define db8500_add_msp0_spi(parent, pdata) \
57 dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \
58 IRQ_DB8500_MSP0, pdata)
59#define db8500_add_msp1_spi(parent, pdata) \
60 dbx500_add_msp_spi(parent, "msp1", U8500_MSP1_BASE, \
61 IRQ_DB8500_MSP1, pdata)
62#define db8500_add_msp2_spi(parent, pdata) \
63 dbx500_add_msp_spi(parent, "msp2", U8500_MSP2_BASE, \
64 IRQ_DB8500_MSP2, pdata)
65#define db8500_add_msp3_spi(parent, pdata) \
66 dbx500_add_msp_spi(parent, "msp3", U8500_MSP3_BASE, \
67 IRQ_DB8500_MSP1, pdata)
68
69#define db8500_add_rtc(parent) \
70 dbx500_add_rtc(parent, U8500_RTC_BASE, IRQ_DB8500_RTC);
71
72#define db8500_add_usb(parent, rx_cfg, tx_cfg) \
73 ux500_add_usb(parent, U8500_USBOTG_BASE, \
74 IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
75
76#define db8500_add_sdi0(parent, pdata, pid) \
77 dbx500_add_sdi(parent, "sdi0", U8500_SDI0_BASE, \
78 IRQ_DB8500_SDMMC0, pdata, pid)
79#define db8500_add_sdi1(parent, pdata, pid) \
80 dbx500_add_sdi(parent, "sdi1", U8500_SDI1_BASE, \
81 IRQ_DB8500_SDMMC1, pdata, pid)
82#define db8500_add_sdi2(parent, pdata, pid) \
83 dbx500_add_sdi(parent, "sdi2", U8500_SDI2_BASE, \
84 IRQ_DB8500_SDMMC2, pdata, pid)
85#define db8500_add_sdi3(parent, pdata, pid) \
86 dbx500_add_sdi(parent, "sdi3", U8500_SDI3_BASE, \
87 IRQ_DB8500_SDMMC3, pdata, pid)
88#define db8500_add_sdi4(parent, pdata, pid) \
89 dbx500_add_sdi(parent, "sdi4", U8500_SDI4_BASE, \
90 IRQ_DB8500_SDMMC4, pdata, pid)
91#define db8500_add_sdi5(parent, pdata, pid) \
92 dbx500_add_sdi(parent, "sdi5", U8500_SDI5_BASE, \
93 IRQ_DB8500_SDMMC5, pdata, pid)
94
95#define db8500_add_ssp0(parent, pdata) \
96 db8500_add_ssp(parent, "ssp0", U8500_SSP0_BASE, \
97 IRQ_DB8500_SSP0, pdata)
98#define db8500_add_ssp1(parent, pdata) \
99 db8500_add_ssp(parent, "ssp1", U8500_SSP1_BASE, \
100 IRQ_DB8500_SSP1, pdata)
101
102#define db8500_add_spi0(parent, pdata) \
103 dbx500_add_spi(parent, "spi0", U8500_SPI0_BASE, \
104 IRQ_DB8500_SPI0, pdata, 0)
105#define db8500_add_spi1(parent, pdata) \
106 dbx500_add_spi(parent, "spi1", U8500_SPI1_BASE, \
107 IRQ_DB8500_SPI1, pdata, 0)
108#define db8500_add_spi2(parent, pdata) \
109 dbx500_add_spi(parent, "spi2", U8500_SPI2_BASE, \
110 IRQ_DB8500_SPI2, pdata, 0)
111#define db8500_add_spi3(parent, pdata) \
112 dbx500_add_spi(parent, "spi3", U8500_SPI3_BASE, \
113 IRQ_DB8500_SPI3, pdata, 0)
114
115#define db8500_add_uart0(parent, pdata) \
116 dbx500_add_uart(parent, "uart0", U8500_UART0_BASE, \
117 IRQ_DB8500_UART0, pdata)
118#define db8500_add_uart1(parent, pdata) \
119 dbx500_add_uart(parent, "uart1", U8500_UART1_BASE, \
120 IRQ_DB8500_UART1, pdata)
121#define db8500_add_uart2(parent, pdata) \
122 dbx500_add_uart(parent, "uart2", U8500_UART2_BASE, \
123 IRQ_DB8500_UART2, pdata)
124
125#define db8500_add_cryp1(parent, pdata) \
126 dbx500_add_cryp1(parent, -1, U8500_CRYP1_BASE, IRQ_DB8500_CRYP1, pdata)
127#define db8500_add_hash1(parent, pdata) \
128 dbx500_add_hash1(parent, -1, U8500_HASH1_BASE, pdata)
129#endif 19#endif
diff --git a/arch/arm/mach-ux500/devices.h b/arch/arm/mach-ux500/devices.h
index cbc6f1e4104d..5bca7c605cd6 100644
--- a/arch/arm/mach-ux500/devices.h
+++ b/arch/arm/mach-ux500/devices.h
@@ -10,14 +10,6 @@
10struct platform_device; 10struct platform_device;
11struct amba_device; 11struct amba_device;
12 12
13extern struct platform_device u8500_gpio_devs[];
14
15extern struct amba_device ux500_pl031_device; 13extern struct amba_device ux500_pl031_device;
16 14
17extern struct platform_device ux500_hash1_device;
18extern struct platform_device ux500_cryp1_device;
19
20extern struct platform_device u8500_dma40_device;
21extern struct platform_device ux500_ske_keypad_device;
22
23#endif 15#endif
diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h
index 656324aad18e..bdb356498a74 100644
--- a/arch/arm/mach-ux500/setup.h
+++ b/arch/arm/mach-ux500/setup.h
@@ -24,7 +24,6 @@ extern void __init u8500_map_io(void);
24extern struct device * __init u8500_init_devices(void); 24extern struct device * __init u8500_init_devices(void);
25 25
26extern void __init ux500_init_irq(void); 26extern void __init ux500_init_irq(void);
27extern void __init ux500_init_late(void);
28 27
29extern struct device *ux500_soc_device_init(const char *soc_id); 28extern struct device *ux500_soc_device_init(const char *soc_id);
30 29
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index b6bd0efcbe64..05a4ff78b3bd 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -97,8 +97,8 @@ dt_fail:
97 * sched_clock with higher rating then MTU since is always-on. 97 * sched_clock with higher rating then MTU since is always-on.
98 * 98 *
99 */ 99 */
100 100 if (!of_have_populated_dt())
101 nmdk_timer_init(mtu_timer_base, IRQ_MTU0); 101 nmdk_timer_init(mtu_timer_base, IRQ_MTU0);
102 clksrc_dbx500_prcmu_init(prcmu_timer_base); 102 clksrc_dbx500_prcmu_init(prcmu_timer_base);
103 ux500_twd_init(); 103 ux500_twd_init();
104} 104}
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
deleted file mode 100644
index b7bd8d3a5507..000000000000
--- a/arch/arm/mach-ux500/usb.c
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7#include <linux/platform_device.h>
8#include <linux/usb/musb.h>
9#include <linux/dma-mapping.h>
10#include <linux/platform_data/usb-musb-ux500.h>
11#include <linux/platform_data/dma-ste-dma40.h>
12
13#include "db8500-regs.h"
14
15#define MUSB_DMA40_RX_CH { \
16 .mode = STEDMA40_MODE_LOGICAL, \
17 .dir = DMA_DEV_TO_MEM, \
18 }
19
20#define MUSB_DMA40_TX_CH { \
21 .mode = STEDMA40_MODE_LOGICAL, \
22 .dir = DMA_MEM_TO_DEV, \
23 }
24
25static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
26 = {
27 MUSB_DMA40_RX_CH,
28 MUSB_DMA40_RX_CH,
29 MUSB_DMA40_RX_CH,
30 MUSB_DMA40_RX_CH,
31 MUSB_DMA40_RX_CH,
32 MUSB_DMA40_RX_CH,
33 MUSB_DMA40_RX_CH,
34 MUSB_DMA40_RX_CH
35};
36
37static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
38 = {
39 MUSB_DMA40_TX_CH,
40 MUSB_DMA40_TX_CH,
41 MUSB_DMA40_TX_CH,
42 MUSB_DMA40_TX_CH,
43 MUSB_DMA40_TX_CH,
44 MUSB_DMA40_TX_CH,
45 MUSB_DMA40_TX_CH,
46 MUSB_DMA40_TX_CH,
47};
48
49static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
50 &musb_dma_rx_ch[0],
51 &musb_dma_rx_ch[1],
52 &musb_dma_rx_ch[2],
53 &musb_dma_rx_ch[3],
54 &musb_dma_rx_ch[4],
55 &musb_dma_rx_ch[5],
56 &musb_dma_rx_ch[6],
57 &musb_dma_rx_ch[7]
58};
59
60static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
61 &musb_dma_tx_ch[0],
62 &musb_dma_tx_ch[1],
63 &musb_dma_tx_ch[2],
64 &musb_dma_tx_ch[3],
65 &musb_dma_tx_ch[4],
66 &musb_dma_tx_ch[5],
67 &musb_dma_tx_ch[6],
68 &musb_dma_tx_ch[7]
69};
70
71static struct ux500_musb_board_data musb_board_data = {
72 .dma_rx_param_array = ux500_dma_rx_param_array,
73 .dma_tx_param_array = ux500_dma_tx_param_array,
74 .dma_filter = stedma40_filter,
75};
76
77static struct musb_hdrc_platform_data musb_platform_data = {
78 .mode = MUSB_OTG,
79 .board_data = &musb_board_data,
80};
81
82static struct resource usb_resources[] = {
83 [0] = {
84 .name = "usb-mem",
85 .flags = IORESOURCE_MEM,
86 },
87
88 [1] = {
89 .name = "mc", /* hard-coded in musb */
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94struct platform_device ux500_musb_device = {
95 .name = "musb-ux500",
96 .id = 0,
97 .dev = {
98 .platform_data = &musb_platform_data,
99 .coherent_dma_mask = DMA_BIT_MASK(32),
100 },
101 .num_resources = ARRAY_SIZE(usb_resources),
102 .resource = usb_resources,
103};
104
105static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
106{
107 u32 idx;
108
109 for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
110 musb_dma_rx_ch[idx].dev_type = dev_type[idx];
111}
112
113static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
114{
115 u32 idx;
116
117 for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
118 musb_dma_tx_ch[idx].dev_type = dev_type[idx];
119}
120
121void ux500_add_usb(struct device *parent, resource_size_t base, int irq,
122 int *dma_rx_cfg, int *dma_tx_cfg)
123{
124 ux500_musb_device.resource[0].start = base;
125 ux500_musb_device.resource[0].end = base + SZ_64K - 1;
126 ux500_musb_device.resource[1].start = irq;
127 ux500_musb_device.resource[1].end = irq;
128
129 ux500_usb_dma_update_rx_ch_config(dma_rx_cfg);
130 ux500_usb_dma_update_tx_ch_config(dma_tx_cfg);
131
132 ux500_musb_device.dev.parent = parent;
133
134 platform_device_register(&ux500_musb_device);
135}
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index 50a3ea0037db..aa9511b6914a 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -11,12 +11,18 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12*/ 12*/
13 13
14/*
15 * NOTE: Code in this file is not used on S3C64xx when booting with
16 * Device Tree support.
17 */
18
14#include <linux/init.h> 19#include <linux/init.h>
15#include <linux/module.h> 20#include <linux/module.h>
16#include <linux/interrupt.h> 21#include <linux/interrupt.h>
17#include <linux/ioport.h> 22#include <linux/ioport.h>
18#include <linux/serial_core.h> 23#include <linux/serial_core.h>
19#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/of.h>
20 26
21#include <mach/hardware.h> 27#include <mach/hardware.h>
22 28
@@ -148,8 +154,12 @@ static int __init s3c_arch_init(void)
148 154
149 // do the correct init for cpu 155 // do the correct init for cpu
150 156
151 if (cpu == NULL) 157 if (cpu == NULL) {
158 /* Not needed when booting with device tree. */
159 if (of_have_populated_dt())
160 return 0;
152 panic("s3c_arch_init: NULL cpu\n"); 161 panic("s3c_arch_init: NULL cpu\n");
162 }
153 163
154 ret = (cpu->init)(); 164 ret = (cpu->init)();
155 if (ret != 0) 165 if (ret != 0)
diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
index c6a806ed0e8c..521483f0ba33 100644
--- a/drivers/clk/ux500/Makefile
+++ b/drivers/clk/ux500/Makefile
@@ -8,6 +8,7 @@ obj-y += clk-prcmu.o
8obj-y += clk-sysctrl.o 8obj-y += clk-sysctrl.o
9 9
10# Clock definitions 10# Clock definitions
11obj-y += u8500_of_clk.o
11obj-y += u8500_clk.o 12obj-y += u8500_clk.o
12obj-y += u9540_clk.o 13obj-y += u9540_clk.o
13obj-y += u8540_clk.o 14obj-y += u8540_clk.o
diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c
new file mode 100644
index 000000000000..cdeff299de26
--- /dev/null
+++ b/drivers/clk/ux500/u8500_of_clk.c
@@ -0,0 +1,559 @@
1/*
2 * Clock definitions for u8500 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/of.h>
11#include <linux/clk.h>
12#include <linux/clkdev.h>
13#include <linux/clk-provider.h>
14#include <linux/mfd/dbx500-prcmu.h>
15#include <linux/platform_data/clk-ux500.h>
16#include "clk.h"
17
18#define PRCC_NUM_PERIPH_CLUSTERS 6
19#define PRCC_PERIPHS_PER_CLUSTER 32
20
21static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
22static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
23static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
24
25#define PRCC_SHOW(clk, base, bit) \
26 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
27#define PRCC_PCLK_STORE(clk, base, bit) \
28 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
29#define PRCC_KCLK_STORE(clk, base, bit) \
30 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
31
32struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, void *data)
33{
34 struct clk **clk_data = data;
35 unsigned int base, bit;
36
37 if (clkspec->args_count != 2)
38 return ERR_PTR(-EINVAL);
39
40 base = clkspec->args[0];
41 bit = clkspec->args[1];
42
43 if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
44 pr_err("%s: invalid PRCC base %d\n", __func__, base);
45 return ERR_PTR(-EINVAL);
46 }
47
48 return PRCC_SHOW(clk_data, base, bit);
49}
50
51static const struct of_device_id u8500_clk_of_match[] = {
52 { .compatible = "stericsson,u8500-clks", },
53 { },
54};
55
56void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
57 u32 clkrst5_base, u32 clkrst6_base)
58{
59 struct prcmu_fw_version *fw_version;
60 struct device_node *np = NULL;
61 struct device_node *child = NULL;
62 const char *sgaclk_parent = NULL;
63 struct clk *clk, *rtc_clk, *twd_clk;
64
65 if (of_have_populated_dt())
66 np = of_find_matching_node(NULL, u8500_clk_of_match);
67 if (!np) {
68 pr_err("Either DT or U8500 Clock node not found\n");
69 return;
70 }
71
72 /* Clock sources */
73 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
74 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
75 prcmu_clk[PRCMU_PLLSOC0] = clk;
76
77 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
78 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
79 prcmu_clk[PRCMU_PLLSOC1] = clk;
80
81 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
82 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
83 prcmu_clk[PRCMU_PLLDDR] = clk;
84
85 /* FIXME: Add sys, ulp and int clocks here. */
86
87 rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
88 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
89 32768);
90
91 /* PRCMU clocks */
92 fw_version = prcmu_get_fw_version();
93 if (fw_version != NULL) {
94 switch (fw_version->project) {
95 case PRCMU_FW_PROJECT_U8500_C2:
96 case PRCMU_FW_PROJECT_U8520:
97 case PRCMU_FW_PROJECT_U8420:
98 sgaclk_parent = "soc0_pll";
99 break;
100 default:
101 break;
102 }
103 }
104
105 if (sgaclk_parent)
106 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
107 PRCMU_SGACLK, 0);
108 else
109 clk = clk_reg_prcmu_gate("sgclk", NULL,
110 PRCMU_SGACLK, CLK_IS_ROOT);
111 prcmu_clk[PRCMU_SGACLK] = clk;
112
113 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
114 prcmu_clk[PRCMU_UARTCLK] = clk;
115
116 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
117 prcmu_clk[PRCMU_MSP02CLK] = clk;
118
119 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
120 prcmu_clk[PRCMU_MSP1CLK] = clk;
121
122 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
123 prcmu_clk[PRCMU_I2CCLK] = clk;
124
125 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
126 prcmu_clk[PRCMU_SLIMCLK] = clk;
127
128 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
129 prcmu_clk[PRCMU_PER1CLK] = clk;
130
131 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
132 prcmu_clk[PRCMU_PER2CLK] = clk;
133
134 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
135 prcmu_clk[PRCMU_PER3CLK] = clk;
136
137 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
138 prcmu_clk[PRCMU_PER5CLK] = clk;
139
140 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
141 prcmu_clk[PRCMU_PER6CLK] = clk;
142
143 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
144 prcmu_clk[PRCMU_PER7CLK] = clk;
145
146 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
147 CLK_IS_ROOT|CLK_SET_RATE_GATE);
148 prcmu_clk[PRCMU_LCDCLK] = clk;
149
150 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
151 prcmu_clk[PRCMU_BMLCLK] = clk;
152
153 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
154 CLK_IS_ROOT|CLK_SET_RATE_GATE);
155 prcmu_clk[PRCMU_HSITXCLK] = clk;
156
157 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
158 CLK_IS_ROOT|CLK_SET_RATE_GATE);
159 prcmu_clk[PRCMU_HSIRXCLK] = clk;
160
161 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
162 CLK_IS_ROOT|CLK_SET_RATE_GATE);
163 prcmu_clk[PRCMU_HDMICLK] = clk;
164
165 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
166 prcmu_clk[PRCMU_APEATCLK] = clk;
167
168 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
169 CLK_IS_ROOT);
170 prcmu_clk[PRCMU_APETRACECLK] = clk;
171
172 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
173 prcmu_clk[PRCMU_MCDECLK] = clk;
174
175 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
176 CLK_IS_ROOT);
177 prcmu_clk[PRCMU_IPI2CCLK] = clk;
178
179 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
180 CLK_IS_ROOT);
181 prcmu_clk[PRCMU_DSIALTCLK] = clk;
182
183 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
184 prcmu_clk[PRCMU_DMACLK] = clk;
185
186 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
187 prcmu_clk[PRCMU_B2R2CLK] = clk;
188
189 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
190 CLK_IS_ROOT|CLK_SET_RATE_GATE);
191 prcmu_clk[PRCMU_TVCLK] = clk;
192
193 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
194 prcmu_clk[PRCMU_SSPCLK] = clk;
195
196 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
197 prcmu_clk[PRCMU_RNGCLK] = clk;
198
199 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
200 prcmu_clk[PRCMU_UICCCLK] = clk;
201
202 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
203 prcmu_clk[PRCMU_TIMCLK] = clk;
204
205 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
206 100000000,
207 CLK_IS_ROOT|CLK_SET_RATE_GATE);
208 prcmu_clk[PRCMU_SDMMCCLK] = clk;
209
210 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
211 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
212 prcmu_clk[PRCMU_PLLDSI] = clk;
213
214 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
215 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
216 prcmu_clk[PRCMU_DSI0CLK] = clk;
217
218 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
219 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
220 prcmu_clk[PRCMU_DSI1CLK] = clk;
221
222 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
223 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
224 prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
225
226 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
227 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
228 prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
229
230 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
231 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
232 prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
233
234 clk = clk_reg_prcmu_scalable_rate("armss", NULL,
235 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
236 prcmu_clk[PRCMU_ARMSS] = clk;
237
238 twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
239 CLK_IGNORE_UNUSED, 1, 2);
240
241 /*
242 * FIXME: Add special handled PRCMU clocks here:
243 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
244 * 2. ab9540_clkout1yuv, see clkout0yuv
245 */
246
247 /* PRCC P-clocks */
248 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
249 BIT(0), 0);
250 PRCC_PCLK_STORE(clk, 1, 0);
251
252 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
253 BIT(1), 0);
254 PRCC_PCLK_STORE(clk, 1, 1);
255
256 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
257 BIT(2), 0);
258 PRCC_PCLK_STORE(clk, 1, 2);
259
260 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
261 BIT(3), 0);
262 PRCC_PCLK_STORE(clk, 1, 3);
263
264 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
265 BIT(4), 0);
266 PRCC_PCLK_STORE(clk, 1, 4);
267
268 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
269 BIT(5), 0);
270 PRCC_PCLK_STORE(clk, 1, 5);
271
272 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
273 BIT(6), 0);
274 PRCC_PCLK_STORE(clk, 1, 6);
275
276 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
277 BIT(7), 0);
278 PRCC_PCLK_STORE(clk, 1, 7);
279
280 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
281 BIT(8), 0);
282 PRCC_PCLK_STORE(clk, 1, 8);
283
284 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
285 BIT(9), 0);
286 PRCC_PCLK_STORE(clk, 1, 9);
287
288 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
289 BIT(10), 0);
290 PRCC_PCLK_STORE(clk, 1, 10);
291
292 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
293 BIT(11), 0);
294 PRCC_PCLK_STORE(clk, 1, 11);
295
296 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
297 BIT(0), 0);
298 PRCC_PCLK_STORE(clk, 2, 0);
299
300 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
301 BIT(1), 0);
302 PRCC_PCLK_STORE(clk, 2, 1);
303
304 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
305 BIT(2), 0);
306 PRCC_PCLK_STORE(clk, 2, 2);
307
308 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
309 BIT(3), 0);
310 PRCC_PCLK_STORE(clk, 2, 3);
311
312 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
313 BIT(4), 0);
314 PRCC_PCLK_STORE(clk, 2, 4);
315
316 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
317 BIT(5), 0);
318 PRCC_PCLK_STORE(clk, 2, 5);
319
320 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
321 BIT(6), 0);
322 PRCC_PCLK_STORE(clk, 2, 6);
323
324 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
325 BIT(7), 0);
326 PRCC_PCLK_STORE(clk, 2, 7);
327
328 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
329 BIT(8), 0);
330 PRCC_PCLK_STORE(clk, 2, 8);
331
332 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
333 BIT(9), 0);
334 PRCC_PCLK_STORE(clk, 2, 9);
335
336 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
337 BIT(10), 0);
338 PRCC_PCLK_STORE(clk, 2, 10);
339
340 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
341 BIT(11), 0);
342 PRCC_PCLK_STORE(clk, 2, 11);
343
344 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
345 BIT(12), 0);
346 PRCC_PCLK_STORE(clk, 2, 12);
347
348 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
349 BIT(0), 0);
350 PRCC_PCLK_STORE(clk, 3, 0);
351
352 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
353 BIT(1), 0);
354 PRCC_PCLK_STORE(clk, 3, 1);
355
356 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
357 BIT(2), 0);
358 PRCC_PCLK_STORE(clk, 3, 2);
359
360 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
361 BIT(3), 0);
362 PRCC_PCLK_STORE(clk, 3, 3);
363
364 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
365 BIT(4), 0);
366 PRCC_PCLK_STORE(clk, 3, 4);
367
368 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
369 BIT(5), 0);
370 PRCC_PCLK_STORE(clk, 3, 5);
371
372 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
373 BIT(6), 0);
374 PRCC_PCLK_STORE(clk, 3, 6);
375
376 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
377 BIT(7), 0);
378 PRCC_PCLK_STORE(clk, 3, 7);
379
380 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
381 BIT(8), 0);
382 PRCC_PCLK_STORE(clk, 3, 8);
383
384 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
385 BIT(0), 0);
386 PRCC_PCLK_STORE(clk, 5, 0);
387
388 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
389 BIT(1), 0);
390 PRCC_PCLK_STORE(clk, 5, 1);
391
392 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
393 BIT(0), 0);
394 PRCC_PCLK_STORE(clk, 6, 0);
395
396 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
397 BIT(1), 0);
398 PRCC_PCLK_STORE(clk, 6, 1);
399
400 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
401 BIT(2), 0);
402 PRCC_PCLK_STORE(clk, 6, 2);
403
404 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
405 BIT(3), 0);
406 PRCC_PCLK_STORE(clk, 6, 3);
407
408 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
409 BIT(4), 0);
410 PRCC_PCLK_STORE(clk, 6, 4);
411
412 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
413 BIT(5), 0);
414 PRCC_PCLK_STORE(clk, 6, 5);
415
416 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
417 BIT(6), 0);
418 PRCC_PCLK_STORE(clk, 6, 6);
419
420 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
421 BIT(7), 0);
422 PRCC_PCLK_STORE(clk, 6, 7);
423
424 /* PRCC K-clocks
425 *
426 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
427 * by enabling just the K-clock, even if it is not a valid parent to
428 * the K-clock. Until drivers get fixed we might need some kind of
429 * "parent muxed join".
430 */
431
432 /* Periph1 */
433 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
434 clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
435 PRCC_KCLK_STORE(clk, 1, 0);
436
437 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
438 clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
439 PRCC_KCLK_STORE(clk, 1, 1);
440
441 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
442 clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
443 PRCC_KCLK_STORE(clk, 1, 2);
444
445 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
446 clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
447 PRCC_KCLK_STORE(clk, 1, 3);
448
449 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
450 clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
451 PRCC_KCLK_STORE(clk, 1, 4);
452
453 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
454 clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
455 PRCC_KCLK_STORE(clk, 1, 5);
456
457 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
458 clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
459 PRCC_KCLK_STORE(clk, 1, 6);
460
461 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
462 clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
463 PRCC_KCLK_STORE(clk, 1, 8);
464
465 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
466 clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
467 PRCC_KCLK_STORE(clk, 1, 9);
468
469 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
470 clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
471 PRCC_KCLK_STORE(clk, 1, 10);
472
473 /* Periph2 */
474 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
475 clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
476 PRCC_KCLK_STORE(clk, 2, 0);
477
478 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
479 clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
480 PRCC_KCLK_STORE(clk, 2, 2);
481
482 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
483 clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
484 PRCC_KCLK_STORE(clk, 2, 3);
485
486 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
487 clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
488 PRCC_KCLK_STORE(clk, 2, 4);
489
490 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
491 clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
492 PRCC_KCLK_STORE(clk, 2, 5);
493
494 /* Note that rate is received from parent. */
495 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
496 clkrst2_base, BIT(6),
497 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
498 PRCC_KCLK_STORE(clk, 2, 6);
499
500 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
501 clkrst2_base, BIT(7),
502 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
503 PRCC_KCLK_STORE(clk, 2, 7);
504
505 /* Periph3 */
506 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
507 clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
508 PRCC_KCLK_STORE(clk, 3, 1);
509
510 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
511 clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
512 PRCC_KCLK_STORE(clk, 3, 2);
513
514 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
515 clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
516 PRCC_KCLK_STORE(clk, 3, 3);
517
518 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
519 clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
520 PRCC_KCLK_STORE(clk, 3, 4);
521
522 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
523 clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
524 PRCC_KCLK_STORE(clk, 3, 5);
525
526 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
527 clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
528 PRCC_KCLK_STORE(clk, 3, 6);
529
530 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
531 clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
532 PRCC_KCLK_STORE(clk, 3, 7);
533
534 /* Periph6 */
535 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
536 clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
537 PRCC_KCLK_STORE(clk, 6, 0);
538
539 for_each_child_of_node(np, child) {
540 static struct clk_onecell_data clk_data;
541
542 if (!of_node_cmp(child->name, "prcmu-clock")) {
543 clk_data.clks = prcmu_clk;
544 clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
545 of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
546 }
547 if (!of_node_cmp(child->name, "prcc-periph-clock"))
548 of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
549
550 if (!of_node_cmp(child->name, "prcc-kernel-clock"))
551 of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
552
553 if (!of_node_cmp(child->name, "rtc32k-clock"))
554 of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
555
556 if (!of_node_cmp(child->name, "smp-twd-clock"))
557 of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
558 }
559}
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
index f26258869deb..20c8add90d11 100644
--- a/drivers/clk/ux500/u8540_clk.c
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -83,7 +83,7 @@ void u8540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
83 clk_register_clkdev(clk, NULL, "lcd"); 83 clk_register_clkdev(clk, NULL, "lcd");
84 clk_register_clkdev(clk, "lcd", "mcde"); 84 clk_register_clkdev(clk, "lcd", "mcde");
85 85
86 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BML8580CLK, 86 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK,
87 CLK_IS_ROOT); 87 CLK_IS_ROOT);
88 clk_register_clkdev(clk, NULL, "bml"); 88 clk_register_clkdev(clk, NULL, "bml");
89 89
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index f6f1c7d244c4..76e02b9460e6 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2082,34 +2082,14 @@ static __init int samsung_gpiolib_init(void)
2082 int i, nr_chips; 2082 int i, nr_chips;
2083 int group = 0; 2083 int group = 0;
2084 2084
2085#if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
2086 /* 2085 /*
2087 * This gpio driver includes support for device tree support and there 2086 * Currently there are two drivers that can provide GPIO support for
2088 * are platforms using it. In order to maintain compatibility with those 2087 * Samsung SoCs. For device tree enabled platforms, the new
2089 * platforms, and to allow non-dt Exynos4210 platforms to use this 2088 * pinctrl-samsung driver is used, providing both GPIO and pin control
2090 * gpiolib support, a check is added to find out if there is a active 2089 * interfaces. For legacy (non-DT) platforms this driver is used.
2091 * pin-controller driver support available. If it is available, this 2090 */
2092 * gpiolib support is ignored and the gpiolib support available in 2091 if (of_have_populated_dt())
2093 * pin-controller driver is used. This is a temporary check and will go 2092 return -ENODEV;
2094 * away when all of the Exynos4210 platforms have switched to using
2095 * device tree and the pin-ctrl driver.
2096 */
2097 struct device_node *pctrl_np;
2098 static const struct of_device_id exynos_pinctrl_ids[] = {
2099 { .compatible = "samsung,s3c2412-pinctrl", },
2100 { .compatible = "samsung,s3c2416-pinctrl", },
2101 { .compatible = "samsung,s3c2440-pinctrl", },
2102 { .compatible = "samsung,s3c2450-pinctrl", },
2103 { .compatible = "samsung,exynos4210-pinctrl", },
2104 { .compatible = "samsung,exynos4x12-pinctrl", },
2105 { .compatible = "samsung,exynos5250-pinctrl", },
2106 { .compatible = "samsung,exynos5440-pinctrl", },
2107 { }
2108 };
2109 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
2110 if (pctrl_np && of_device_is_available(pctrl_np))
2111 return -ENODEV;
2112#endif
2113 2093
2114 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); 2094 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2115 2095
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 2bbb00404cf5..8e21ae0bab46 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -469,6 +469,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
469int __init vic_of_init(struct device_node *node, struct device_node *parent) 469int __init vic_of_init(struct device_node *node, struct device_node *parent)
470{ 470{
471 void __iomem *regs; 471 void __iomem *regs;
472 u32 interrupt_mask = ~0;
473 u32 wakeup_mask = ~0;
472 474
473 if (WARN(parent, "non-root VICs are not supported")) 475 if (WARN(parent, "non-root VICs are not supported"))
474 return -EINVAL; 476 return -EINVAL;
@@ -477,10 +479,13 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
477 if (WARN_ON(!regs)) 479 if (WARN_ON(!regs))
478 return -EIO; 480 return -EIO;
479 481
482 of_property_read_u32(node, "valid-mask", &interrupt_mask);
483 of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
484
480 /* 485 /*
481 * Passing 0 as first IRQ makes the simple domain allocate descriptors 486 * Passing 0 as first IRQ makes the simple domain allocate descriptors
482 */ 487 */
483 __vic_init(regs, 0, ~0, ~0, node); 488 __vic_init(regs, 0, interrupt_mask, wakeup_mask, node);
484 489
485 return 0; 490 return 0;
486} 491}
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 53f371dcbb6e..b9ce60c301de 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -480,7 +480,6 @@ static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
480 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 480 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 481 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 482 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
483 CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 483 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
485 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 484 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
486 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 485 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 4f6f0fa5d3b7..7cc32a8ff01c 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -32,7 +32,6 @@
32#define PRCM_PER7CLK_MGT (0x040) 32#define PRCM_PER7CLK_MGT (0x040)
33#define PRCM_LCDCLK_MGT (0x044) 33#define PRCM_LCDCLK_MGT (0x044)
34#define PRCM_BMLCLK_MGT (0x04C) 34#define PRCM_BMLCLK_MGT (0x04C)
35#define PRCM_BML8580CLK_MGT (0x108)
36#define PRCM_HSITXCLK_MGT (0x050) 35#define PRCM_HSITXCLK_MGT (0x050)
37#define PRCM_HSIRXCLK_MGT (0x054) 36#define PRCM_HSIRXCLK_MGT (0x054)
38#define PRCM_HDMICLK_MGT (0x058) 37#define PRCM_HDMICLK_MGT (0x058)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index a82ace4d9a20..0846922b2316 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -15,15 +15,21 @@
15#include <linux/slab.h> 15#include <linux/slab.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/list.h> 17#include <linux/list.h>
18#include <linux/interrupt.h>
19
20#include <linux/irqchip/chained_irq.h>
18 21
19#include <linux/of.h> 22#include <linux/of.h>
20#include <linux/of_device.h> 23#include <linux/of_device.h>
21#include <linux/of_address.h> 24#include <linux/of_address.h>
25#include <linux/of_irq.h>
22 26
23#include <linux/pinctrl/pinctrl.h> 27#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h> 28#include <linux/pinctrl/pinmux.h>
25#include <linux/pinctrl/pinconf-generic.h> 29#include <linux/pinctrl/pinconf-generic.h>
26 30
31#include <linux/platform_data/pinctrl-single.h>
32
27#include "core.h" 33#include "core.h"
28#include "pinconf.h" 34#include "pinconf.h"
29 35
@@ -150,19 +156,36 @@ struct pcs_name {
150}; 156};
151 157
152/** 158/**
159 * struct pcs_soc_data - SoC specific settings
160 * @flags: initial SoC specific PCS_FEAT_xxx values
161 * @irq: optional interrupt for the controller
162 * @irq_enable_mask: optional SoC specific interrupt enable mask
163 * @irq_status_mask: optional SoC specific interrupt status mask
164 * @rearm: optional SoC specific wake-up rearm function
165 */
166struct pcs_soc_data {
167 unsigned flags;
168 int irq;
169 unsigned irq_enable_mask;
170 unsigned irq_status_mask;
171 void (*rearm)(void);
172};
173
174/**
153 * struct pcs_device - pinctrl device instance 175 * struct pcs_device - pinctrl device instance
154 * @res: resources 176 * @res: resources
155 * @base: virtual address of the controller 177 * @base: virtual address of the controller
156 * @size: size of the ioremapped area 178 * @size: size of the ioremapped area
157 * @dev: device entry 179 * @dev: device entry
158 * @pctl: pin controller device 180 * @pctl: pin controller device
181 * @flags: mask of PCS_FEAT_xxx values
182 * @lock: spinlock for register access
159 * @mutex: mutex protecting the lists 183 * @mutex: mutex protecting the lists
160 * @width: bits per mux register 184 * @width: bits per mux register
161 * @fmask: function register mask 185 * @fmask: function register mask
162 * @fshift: function register shift 186 * @fshift: function register shift
163 * @foff: value to turn mux off 187 * @foff: value to turn mux off
164 * @fmax: max number of functions in fmask 188 * @fmax: max number of functions in fmask
165 * @is_pinconf: whether supports pinconf
166 * @bits_per_pin:number of bits per pin 189 * @bits_per_pin:number of bits per pin
167 * @names: array of register names for pins 190 * @names: array of register names for pins
168 * @pins: physical pins on the SoC 191 * @pins: physical pins on the SoC
@@ -171,6 +194,9 @@ struct pcs_name {
171 * @pingroups: list of pingroups 194 * @pingroups: list of pingroups
172 * @functions: list of functions 195 * @functions: list of functions
173 * @gpiofuncs: list of gpio functions 196 * @gpiofuncs: list of gpio functions
197 * @irqs: list of interrupt registers
198 * @chip: chip container for this instance
199 * @domain: IRQ domain for this instance
174 * @ngroups: number of pingroups 200 * @ngroups: number of pingroups
175 * @nfuncs: number of functions 201 * @nfuncs: number of functions
176 * @desc: pin controller descriptor 202 * @desc: pin controller descriptor
@@ -183,6 +209,12 @@ struct pcs_device {
183 unsigned size; 209 unsigned size;
184 struct device *dev; 210 struct device *dev;
185 struct pinctrl_dev *pctl; 211 struct pinctrl_dev *pctl;
212 unsigned flags;
213#define PCS_QUIRK_SHARED_IRQ (1 << 2)
214#define PCS_FEAT_IRQ (1 << 1)
215#define PCS_FEAT_PINCONF (1 << 0)
216 struct pcs_soc_data socdata;
217 raw_spinlock_t lock;
186 struct mutex mutex; 218 struct mutex mutex;
187 unsigned width; 219 unsigned width;
188 unsigned fmask; 220 unsigned fmask;
@@ -190,7 +222,6 @@ struct pcs_device {
190 unsigned foff; 222 unsigned foff;
191 unsigned fmax; 223 unsigned fmax;
192 bool bits_per_mux; 224 bool bits_per_mux;
193 bool is_pinconf;
194 unsigned bits_per_pin; 225 unsigned bits_per_pin;
195 struct pcs_name *names; 226 struct pcs_name *names;
196 struct pcs_data pins; 227 struct pcs_data pins;
@@ -199,6 +230,9 @@ struct pcs_device {
199 struct list_head pingroups; 230 struct list_head pingroups;
200 struct list_head functions; 231 struct list_head functions;
201 struct list_head gpiofuncs; 232 struct list_head gpiofuncs;
233 struct list_head irqs;
234 struct irq_chip chip;
235 struct irq_domain *domain;
202 unsigned ngroups; 236 unsigned ngroups;
203 unsigned nfuncs; 237 unsigned nfuncs;
204 struct pinctrl_desc desc; 238 struct pinctrl_desc desc;
@@ -206,6 +240,10 @@ struct pcs_device {
206 void (*write)(unsigned val, void __iomem *reg); 240 void (*write)(unsigned val, void __iomem *reg);
207}; 241};
208 242
243#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
244#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
245#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
246
209static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, 247static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
210 unsigned long *config); 248 unsigned long *config);
211static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, 249static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
@@ -429,9 +467,11 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
429 467
430 for (i = 0; i < func->nvals; i++) { 468 for (i = 0; i < func->nvals; i++) {
431 struct pcs_func_vals *vals; 469 struct pcs_func_vals *vals;
470 unsigned long flags;
432 unsigned val, mask; 471 unsigned val, mask;
433 472
434 vals = &func->vals[i]; 473 vals = &func->vals[i];
474 raw_spin_lock_irqsave(&pcs->lock, flags);
435 val = pcs->read(vals->reg); 475 val = pcs->read(vals->reg);
436 476
437 if (pcs->bits_per_mux) 477 if (pcs->bits_per_mux)
@@ -442,6 +482,7 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
442 val &= ~mask; 482 val &= ~mask;
443 val |= (vals->val & mask); 483 val |= (vals->val & mask);
444 pcs->write(val, vals->reg); 484 pcs->write(val, vals->reg);
485 raw_spin_unlock_irqrestore(&pcs->lock, flags);
445 } 486 }
446 487
447 return 0; 488 return 0;
@@ -483,13 +524,16 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
483 524
484 for (i = 0; i < func->nvals; i++) { 525 for (i = 0; i < func->nvals; i++) {
485 struct pcs_func_vals *vals; 526 struct pcs_func_vals *vals;
527 unsigned long flags;
486 unsigned val; 528 unsigned val;
487 529
488 vals = &func->vals[i]; 530 vals = &func->vals[i];
531 raw_spin_lock_irqsave(&pcs->lock, flags);
489 val = pcs->read(vals->reg); 532 val = pcs->read(vals->reg);
490 val &= ~pcs->fmask; 533 val &= ~pcs->fmask;
491 val |= pcs->foff << pcs->fshift; 534 val |= pcs->foff << pcs->fshift;
492 pcs->write(val, vals->reg); 535 pcs->write(val, vals->reg);
536 raw_spin_unlock_irqrestore(&pcs->lock, flags);
493 } 537 }
494} 538}
495 539
@@ -1060,7 +1104,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1060 }; 1104 };
1061 1105
1062 /* If pinconf isn't supported, don't parse properties in below. */ 1106 /* If pinconf isn't supported, don't parse properties in below. */
1063 if (!pcs->is_pinconf) 1107 if (!PCS_HAS_PINCONF)
1064 return 0; 1108 return 0;
1065 1109
1066 /* cacluate how much properties are supported in current node */ 1110 /* cacluate how much properties are supported in current node */
@@ -1184,7 +1228,7 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1184 (*map)->data.mux.group = np->name; 1228 (*map)->data.mux.group = np->name;
1185 (*map)->data.mux.function = np->name; 1229 (*map)->data.mux.function = np->name;
1186 1230
1187 if (pcs->is_pinconf) { 1231 if (PCS_HAS_PINCONF) {
1188 res = pcs_parse_pinconf(pcs, np, function, map); 1232 res = pcs_parse_pinconf(pcs, np, function, map);
1189 if (res) 1233 if (res)
1190 goto free_pingroups; 1234 goto free_pingroups;
@@ -1305,7 +1349,7 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1305 (*map)->data.mux.group = np->name; 1349 (*map)->data.mux.group = np->name;
1306 (*map)->data.mux.function = np->name; 1350 (*map)->data.mux.function = np->name;
1307 1351
1308 if (pcs->is_pinconf) { 1352 if (PCS_HAS_PINCONF) {
1309 dev_err(pcs->dev, "pinconf not supported\n"); 1353 dev_err(pcs->dev, "pinconf not supported\n");
1310 goto free_pingroups; 1354 goto free_pingroups;
1311 } 1355 }
@@ -1440,11 +1484,33 @@ static void pcs_free_pingroups(struct pcs_device *pcs)
1440} 1484}
1441 1485
1442/** 1486/**
1487 * pcs_irq_free() - free interrupt
1488 * @pcs: pcs driver instance
1489 */
1490static void pcs_irq_free(struct pcs_device *pcs)
1491{
1492 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1493
1494 if (pcs_soc->irq < 0)
1495 return;
1496
1497 if (pcs->domain)
1498 irq_domain_remove(pcs->domain);
1499
1500 if (PCS_QUIRK_HAS_SHARED_IRQ)
1501 free_irq(pcs_soc->irq, pcs_soc);
1502 else
1503 irq_set_chained_handler(pcs_soc->irq, NULL);
1504}
1505
1506/**
1443 * pcs_free_resources() - free memory used by this driver 1507 * pcs_free_resources() - free memory used by this driver
1444 * @pcs: pcs driver instance 1508 * @pcs: pcs driver instance
1445 */ 1509 */
1446static void pcs_free_resources(struct pcs_device *pcs) 1510static void pcs_free_resources(struct pcs_device *pcs)
1447{ 1511{
1512 pcs_irq_free(pcs);
1513
1448 if (pcs->pctl) 1514 if (pcs->pctl)
1449 pinctrl_unregister(pcs->pctl); 1515 pinctrl_unregister(pcs->pctl);
1450 1516
@@ -1493,6 +1559,268 @@ static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1493 } 1559 }
1494 return ret; 1560 return ret;
1495} 1561}
1562/**
1563 * @reg: virtual address of interrupt register
1564 * @hwirq: hardware irq number
1565 * @irq: virtual irq number
1566 * @node: list node
1567 */
1568struct pcs_interrupt {
1569 void __iomem *reg;
1570 irq_hw_number_t hwirq;
1571 unsigned int irq;
1572 struct list_head node;
1573};
1574
1575/**
1576 * pcs_irq_set() - enables or disables an interrupt
1577 *
1578 * Note that this currently assumes one interrupt per pinctrl
1579 * register that is typically used for wake-up events.
1580 */
1581static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1582 int irq, const bool enable)
1583{
1584 struct pcs_device *pcs;
1585 struct list_head *pos;
1586 unsigned mask;
1587
1588 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1589 list_for_each(pos, &pcs->irqs) {
1590 struct pcs_interrupt *pcswi;
1591 unsigned soc_mask;
1592
1593 pcswi = list_entry(pos, struct pcs_interrupt, node);
1594 if (irq != pcswi->irq)
1595 continue;
1596
1597 soc_mask = pcs_soc->irq_enable_mask;
1598 raw_spin_lock(&pcs->lock);
1599 mask = pcs->read(pcswi->reg);
1600 if (enable)
1601 mask |= soc_mask;
1602 else
1603 mask &= ~soc_mask;
1604 pcs->write(mask, pcswi->reg);
1605 raw_spin_unlock(&pcs->lock);
1606 }
1607}
1608
1609/**
1610 * pcs_irq_mask() - mask pinctrl interrupt
1611 * @d: interrupt data
1612 */
1613static void pcs_irq_mask(struct irq_data *d)
1614{
1615 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1616
1617 pcs_irq_set(pcs_soc, d->irq, false);
1618}
1619
1620/**
1621 * pcs_irq_unmask() - unmask pinctrl interrupt
1622 * @d: interrupt data
1623 */
1624static void pcs_irq_unmask(struct irq_data *d)
1625{
1626 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1627
1628 pcs_irq_set(pcs_soc, d->irq, true);
1629 if (pcs_soc->rearm)
1630 pcs_soc->rearm();
1631}
1632
1633/**
1634 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1635 * @d: interrupt data
1636 * @state: wake-up state
1637 *
1638 * Note that this should be called only for suspend and resume.
1639 * For runtime PM, the wake-up events should be enabled by default.
1640 */
1641static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1642{
1643 if (state)
1644 pcs_irq_unmask(d);
1645 else
1646 pcs_irq_mask(d);
1647
1648 return 0;
1649}
1650
1651/**
1652 * pcs_irq_handle() - common interrupt handler
1653 * @pcs_irq: interrupt data
1654 *
1655 * Note that this currently assumes we have one interrupt bit per
1656 * mux register. This interrupt is typically used for wake-up events.
1657 * For more complex interrupts different handlers can be specified.
1658 */
1659static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1660{
1661 struct pcs_device *pcs;
1662 struct list_head *pos;
1663 int count = 0;
1664
1665 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1666 list_for_each(pos, &pcs->irqs) {
1667 struct pcs_interrupt *pcswi;
1668 unsigned mask;
1669
1670 pcswi = list_entry(pos, struct pcs_interrupt, node);
1671 raw_spin_lock(&pcs->lock);
1672 mask = pcs->read(pcswi->reg);
1673 raw_spin_unlock(&pcs->lock);
1674 if (mask & pcs_soc->irq_status_mask) {
1675 generic_handle_irq(irq_find_mapping(pcs->domain,
1676 pcswi->hwirq));
1677 count++;
1678 }
1679 }
1680
1681 /*
1682 * For debugging on omaps, you may want to call pcs_soc->rearm()
1683 * here to see wake-up interrupts during runtime also.
1684 */
1685
1686 return count;
1687}
1688
1689/**
1690 * pcs_irq_handler() - handler for the shared interrupt case
1691 * @irq: interrupt
1692 * @d: data
1693 *
1694 * Use this for cases where multiple instances of
1695 * pinctrl-single share a single interrupt like on omaps.
1696 */
1697static irqreturn_t pcs_irq_handler(int irq, void *d)
1698{
1699 struct pcs_soc_data *pcs_soc = d;
1700
1701 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1702}
1703
1704/**
1705 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1706 * @irq: interrupt
1707 * @desc: interrupt descriptor
1708 *
1709 * Use this if you have a separate interrupt for each
1710 * pinctrl-single instance.
1711 */
1712static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1713{
1714 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1715 struct irq_chip *chip;
1716 int res;
1717
1718 chip = irq_get_chip(irq);
1719 chained_irq_enter(chip, desc);
1720 res = pcs_irq_handle(pcs_soc);
1721 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1722 chained_irq_exit(chip, desc);
1723
1724 return;
1725}
1726
1727static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1728 irq_hw_number_t hwirq)
1729{
1730 struct pcs_soc_data *pcs_soc = d->host_data;
1731 struct pcs_device *pcs;
1732 struct pcs_interrupt *pcswi;
1733
1734 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1735 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1736 if (!pcswi)
1737 return -ENOMEM;
1738
1739 pcswi->reg = pcs->base + hwirq;
1740 pcswi->hwirq = hwirq;
1741 pcswi->irq = irq;
1742
1743 mutex_lock(&pcs->mutex);
1744 list_add_tail(&pcswi->node, &pcs->irqs);
1745 mutex_unlock(&pcs->mutex);
1746
1747 irq_set_chip_data(irq, pcs_soc);
1748 irq_set_chip_and_handler(irq, &pcs->chip,
1749 handle_level_irq);
1750
1751#ifdef CONFIG_ARM
1752 set_irq_flags(irq, IRQF_VALID);
1753#else
1754 irq_set_noprobe(irq);
1755#endif
1756
1757 return 0;
1758}
1759
1760static struct irq_domain_ops pcs_irqdomain_ops = {
1761 .map = pcs_irqdomain_map,
1762 .xlate = irq_domain_xlate_onecell,
1763};
1764
1765/**
1766 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1767 * @pcs: pcs driver instance
1768 * @np: device node pointer
1769 */
1770static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1771 struct device_node *np)
1772{
1773 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1774 const char *name = "pinctrl";
1775 int num_irqs;
1776
1777 if (!pcs_soc->irq_enable_mask ||
1778 !pcs_soc->irq_status_mask) {
1779 pcs_soc->irq = -1;
1780 return -EINVAL;
1781 }
1782
1783 INIT_LIST_HEAD(&pcs->irqs);
1784 pcs->chip.name = name;
1785 pcs->chip.irq_ack = pcs_irq_mask;
1786 pcs->chip.irq_mask = pcs_irq_mask;
1787 pcs->chip.irq_unmask = pcs_irq_unmask;
1788 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1789
1790 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1791 int res;
1792
1793 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1794 IRQF_SHARED | IRQF_NO_SUSPEND,
1795 name, pcs_soc);
1796 if (res) {
1797 pcs_soc->irq = -1;
1798 return res;
1799 }
1800 } else {
1801 irq_set_handler_data(pcs_soc->irq, pcs_soc);
1802 irq_set_chained_handler(pcs_soc->irq,
1803 pcs_irq_chain_handler);
1804 }
1805
1806 /*
1807 * We can use the register offset as the hardirq
1808 * number as irq_domain_add_simple maps them lazily.
1809 * This way we can easily support more than one
1810 * interrupt per function if needed.
1811 */
1812 num_irqs = pcs->size;
1813
1814 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1815 &pcs_irqdomain_ops,
1816 pcs_soc);
1817 if (!pcs->domain) {
1818 irq_set_chained_handler(pcs_soc->irq, NULL);
1819 return -EINVAL;
1820 }
1821
1822 return 0;
1823}
1496 1824
1497#ifdef CONFIG_PM 1825#ifdef CONFIG_PM
1498static int pinctrl_single_suspend(struct platform_device *pdev, 1826static int pinctrl_single_suspend(struct platform_device *pdev,
@@ -1523,8 +1851,10 @@ static int pcs_probe(struct platform_device *pdev)
1523{ 1851{
1524 struct device_node *np = pdev->dev.of_node; 1852 struct device_node *np = pdev->dev.of_node;
1525 const struct of_device_id *match; 1853 const struct of_device_id *match;
1854 struct pcs_pdata *pdata;
1526 struct resource *res; 1855 struct resource *res;
1527 struct pcs_device *pcs; 1856 struct pcs_device *pcs;
1857 const struct pcs_soc_data *soc;
1528 int ret; 1858 int ret;
1529 1859
1530 match = of_match_device(pcs_of_match, &pdev->dev); 1860 match = of_match_device(pcs_of_match, &pdev->dev);
@@ -1537,11 +1867,14 @@ static int pcs_probe(struct platform_device *pdev)
1537 return -ENOMEM; 1867 return -ENOMEM;
1538 } 1868 }
1539 pcs->dev = &pdev->dev; 1869 pcs->dev = &pdev->dev;
1870 raw_spin_lock_init(&pcs->lock);
1540 mutex_init(&pcs->mutex); 1871 mutex_init(&pcs->mutex);
1541 INIT_LIST_HEAD(&pcs->pingroups); 1872 INIT_LIST_HEAD(&pcs->pingroups);
1542 INIT_LIST_HEAD(&pcs->functions); 1873 INIT_LIST_HEAD(&pcs->functions);
1543 INIT_LIST_HEAD(&pcs->gpiofuncs); 1874 INIT_LIST_HEAD(&pcs->gpiofuncs);
1544 pcs->is_pinconf = match->data; 1875 soc = match->data;
1876 pcs->flags = soc->flags;
1877 memcpy(&pcs->socdata, soc, sizeof(*soc));
1545 1878
1546 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, 1879 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
1547 "register width not specified\n"); 1880 "register width not specified\n");
@@ -1610,7 +1943,7 @@ static int pcs_probe(struct platform_device *pdev)
1610 pcs->desc.name = DRIVER_NAME; 1943 pcs->desc.name = DRIVER_NAME;
1611 pcs->desc.pctlops = &pcs_pinctrl_ops; 1944 pcs->desc.pctlops = &pcs_pinctrl_ops;
1612 pcs->desc.pmxops = &pcs_pinmux_ops; 1945 pcs->desc.pmxops = &pcs_pinmux_ops;
1613 if (pcs->is_pinconf) 1946 if (PCS_HAS_PINCONF)
1614 pcs->desc.confops = &pcs_pinconf_ops; 1947 pcs->desc.confops = &pcs_pinconf_ops;
1615 pcs->desc.owner = THIS_MODULE; 1948 pcs->desc.owner = THIS_MODULE;
1616 1949
@@ -1629,6 +1962,27 @@ static int pcs_probe(struct platform_device *pdev)
1629 if (ret < 0) 1962 if (ret < 0)
1630 goto free; 1963 goto free;
1631 1964
1965 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1966 if (pcs->socdata.irq)
1967 pcs->flags |= PCS_FEAT_IRQ;
1968
1969 /* We still need auxdata for some omaps for PRM interrupts */
1970 pdata = dev_get_platdata(&pdev->dev);
1971 if (pdata) {
1972 if (pdata->rearm)
1973 pcs->socdata.rearm = pdata->rearm;
1974 if (pdata->irq) {
1975 pcs->socdata.irq = pdata->irq;
1976 pcs->flags |= PCS_FEAT_IRQ;
1977 }
1978 }
1979
1980 if (PCS_HAS_IRQ) {
1981 ret = pcs_irq_init_chained_handler(pcs, np);
1982 if (ret < 0)
1983 dev_warn(pcs->dev, "initialized with no interrupts\n");
1984 }
1985
1632 dev_info(pcs->dev, "%i pins at pa %p size %u\n", 1986 dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1633 pcs->desc.npins, pcs->base, pcs->size); 1987 pcs->desc.npins, pcs->base, pcs->size);
1634 1988
@@ -1652,9 +2006,25 @@ static int pcs_remove(struct platform_device *pdev)
1652 return 0; 2006 return 0;
1653} 2007}
1654 2008
2009static const struct pcs_soc_data pinctrl_single_omap_wkup = {
2010 .flags = PCS_QUIRK_SHARED_IRQ,
2011 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
2012 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
2013};
2014
2015static const struct pcs_soc_data pinctrl_single = {
2016};
2017
2018static const struct pcs_soc_data pinconf_single = {
2019 .flags = PCS_FEAT_PINCONF,
2020};
2021
1655static struct of_device_id pcs_of_match[] = { 2022static struct of_device_id pcs_of_match[] = {
1656 { .compatible = "pinctrl-single", .data = (void *)false }, 2023 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1657 { .compatible = "pinconf-single", .data = (void *)true }, 2024 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2025 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2026 { .compatible = "pinctrl-single", .data = &pinctrl_single },
2027 { .compatible = "pinconf-single", .data = &pinconf_single },
1658 { }, 2028 { },
1659}; 2029};
1660MODULE_DEVICE_TABLE(of, pcs_of_match); 2030MODULE_DEVICE_TABLE(of, pcs_of_match);
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index f483d1924c28..122446bf1664 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -259,7 +259,7 @@ static int ux500_probe(struct platform_device *pdev)
259 goto err1; 259 goto err1;
260 } 260 }
261 261
262 clk = clk_get(&pdev->dev, "usb"); 262 clk = clk_get(&pdev->dev, NULL);
263 if (IS_ERR(clk)) { 263 if (IS_ERR(clk)) {
264 dev_err(&pdev->dev, "failed to get clock\n"); 264 dev_err(&pdev->dev, "failed to get clock\n");
265 ret = PTR_ERR(clk); 265 ret = PTR_ERR(clk);
diff --git a/include/dt-bindings/mfd/dbx500-prcmu.h b/include/dt-bindings/mfd/dbx500-prcmu.h
new file mode 100644
index 000000000000..552a2d174f01
--- /dev/null
+++ b/include/dt-bindings/mfd/dbx500-prcmu.h
@@ -0,0 +1,83 @@
1/*
2 * This header provides constants for the PRCMU bindings.
3 *
4 */
5
6#ifndef _DT_BINDINGS_MFD_PRCMU_H
7#define _DT_BINDINGS_MFD_PRCMU_H
8
9/*
10 * Clock identifiers.
11 */
12#define ARMCLK 0
13#define PRCMU_ACLK 1
14#define PRCMU_SVAMMCSPCLK 2
15#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
16#define PRCMU_SIACLK 3
17#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
18#define PRCMU_SGACLK 4
19#define PRCMU_UARTCLK 5
20#define PRCMU_MSP02CLK 6
21#define PRCMU_MSP1CLK 7
22#define PRCMU_I2CCLK 8
23#define PRCMU_SDMMCCLK 9
24#define PRCMU_SLIMCLK 10
25#define PRCMU_CAMCLK 10 /* DBx540 only. */
26#define PRCMU_PER1CLK 11
27#define PRCMU_PER2CLK 12
28#define PRCMU_PER3CLK 13
29#define PRCMU_PER5CLK 14
30#define PRCMU_PER6CLK 15
31#define PRCMU_PER7CLK 16
32#define PRCMU_LCDCLK 17
33#define PRCMU_BMLCLK 18
34#define PRCMU_HSITXCLK 19
35#define PRCMU_HSIRXCLK 20
36#define PRCMU_HDMICLK 21
37#define PRCMU_APEATCLK 22
38#define PRCMU_APETRACECLK 23
39#define PRCMU_MCDECLK 24
40#define PRCMU_IPI2CCLK 25
41#define PRCMU_DSIALTCLK 26
42#define PRCMU_DMACLK 27
43#define PRCMU_B2R2CLK 28
44#define PRCMU_TVCLK 29
45#define SPARE_UNIPROCLK 30
46#define PRCMU_SSPCLK 31
47#define PRCMU_RNGCLK 32
48#define PRCMU_UICCCLK 33
49#define PRCMU_G1CLK 34 /* DBx540 only. */
50#define PRCMU_HVACLK 35 /* DBx540 only. */
51#define PRCMU_SPARE1CLK 36
52#define PRCMU_SPARE2CLK 37
53
54#define PRCMU_NUM_REG_CLOCKS 38
55
56#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS
57#define PRCMU_SYSCLK 39
58#define PRCMU_CDCLK 40
59#define PRCMU_TIMCLK 41
60#define PRCMU_PLLSOC0 42
61#define PRCMU_PLLSOC1 43
62#define PRCMU_ARMSS 44
63#define PRCMU_PLLDDR 45
64
65/* DSI Clocks */
66#define PRCMU_PLLDSI 46
67#define PRCMU_DSI0CLK 47
68#define PRCMU_DSI1CLK 48
69#define PRCMU_DSI0ESCCLK 49
70#define PRCMU_DSI1ESCCLK 50
71#define PRCMU_DSI2ESCCLK 51
72
73/* LCD DSI PLL - Ux540 only */
74#define PRCMU_PLLDSI_LCD 52
75#define PRCMU_DSI0CLK_LCD 53
76#define PRCMU_DSI1CLK_LCD 54
77#define PRCMU_DSI0ESCCLK_LCD 55
78#define PRCMU_DSI1ESCCLK_LCD 56
79#define PRCMU_DSI2ESCCLK_LCD 57
80
81#define PRCMU_NUM_CLKS 58
82
83#endif
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h
new file mode 100644
index 000000000000..eb6c366adfba
--- /dev/null
+++ b/include/dt-bindings/pinctrl/am43xx.h
@@ -0,0 +1,31 @@
1/*
2 * This header provides constants specific to AM43XX pinctrl bindings.
3 */
4
5#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H
6#define _DT_BINDINGS_PINCTRL_AM43XX_H
7
8#define MUX_MODE0 0
9#define MUX_MODE1 1
10#define MUX_MODE2 2
11#define MUX_MODE3 3
12#define MUX_MODE4 4
13#define MUX_MODE5 5
14#define MUX_MODE6 6
15#define MUX_MODE7 7
16
17#define PULL_DISABLE (1 << 16)
18#define PULL_UP (1 << 17)
19#define INPUT_EN (1 << 18)
20#define SLEWCTRL_FAST (1 << 19)
21#define DS0_PULL_UP_DOWN_EN (1 << 27)
22
23#define PIN_OUTPUT (PULL_DISABLE)
24#define PIN_OUTPUT_PULLUP (PULL_UP)
25#define PIN_OUTPUT_PULLDOWN 0
26#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
27#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
28#define PIN_INPUT_PULLDOWN (INPUT_EN)
29
30#endif
31
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
new file mode 100644
index 000000000000..002a2855c046
--- /dev/null
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -0,0 +1,50 @@
1/*
2 * This header provides constants for DRA pinctrl bindings.
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 * Author: Rajendra Nayak <rnayak@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _DT_BINDINGS_PINCTRL_DRA_H
13#define _DT_BINDINGS_PINCTRL_DRA_H
14
15/* DRA7 mux mode options for each pin. See TRM for options */
16#define MUX_MODE0 0x0
17#define MUX_MODE1 0x1
18#define MUX_MODE2 0x2
19#define MUX_MODE3 0x3
20#define MUX_MODE4 0x4
21#define MUX_MODE5 0x5
22#define MUX_MODE6 0x6
23#define MUX_MODE7 0x7
24#define MUX_MODE8 0x8
25#define MUX_MODE9 0x9
26#define MUX_MODE10 0xa
27#define MUX_MODE11 0xb
28#define MUX_MODE12 0xc
29#define MUX_MODE13 0xd
30#define MUX_MODE14 0xe
31#define MUX_MODE15 0xf
32
33#define PULL_ENA (1 << 16)
34#define PULL_UP (1 << 17)
35#define INPUT_EN (1 << 18)
36#define SLEWCONTROL (1 << 19)
37#define WAKEUP_EN (1 << 24)
38#define WAKEUP_EVENT (1 << 25)
39
40/* Active pin states */
41#define PIN_OUTPUT 0
42#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
43#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
44#define PIN_INPUT INPUT_EN
45#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
46#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
47#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
48
49#endif
50
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index ca0790fba2f5..060e11256fbc 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -12,6 +12,8 @@
12#include <linux/notifier.h> 12#include <linux/notifier.h>
13#include <linux/err.h> 13#include <linux/err.h>
14 14
15#include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
16
15/* Offset for the firmware version within the TCPM */ 17/* Offset for the firmware version within the TCPM */
16#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4 18#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
17#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8 19#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
@@ -94,74 +96,6 @@ enum prcmu_wakeup_index {
94#define PRCMU_CLKSRC_ARMCLKFIX 0x46 96#define PRCMU_CLKSRC_ARMCLKFIX 0x46
95#define PRCMU_CLKSRC_HDMICLK 0x47 97#define PRCMU_CLKSRC_HDMICLK 0x47
96 98
97/*
98 * Clock identifiers.
99 */
100enum prcmu_clock {
101 PRCMU_SGACLK,
102 PRCMU_UARTCLK,
103 PRCMU_MSP02CLK,
104 PRCMU_MSP1CLK,
105 PRCMU_I2CCLK,
106 PRCMU_SDMMCCLK,
107 PRCMU_SPARE1CLK,
108 PRCMU_SLIMCLK,
109 PRCMU_PER1CLK,
110 PRCMU_PER2CLK,
111 PRCMU_PER3CLK,
112 PRCMU_PER5CLK,
113 PRCMU_PER6CLK,
114 PRCMU_PER7CLK,
115 PRCMU_LCDCLK,
116 PRCMU_BMLCLK,
117 PRCMU_HSITXCLK,
118 PRCMU_HSIRXCLK,
119 PRCMU_HDMICLK,
120 PRCMU_APEATCLK,
121 PRCMU_APETRACECLK,
122 PRCMU_MCDECLK,
123 PRCMU_IPI2CCLK,
124 PRCMU_DSIALTCLK,
125 PRCMU_DMACLK,
126 PRCMU_B2R2CLK,
127 PRCMU_TVCLK,
128 PRCMU_SSPCLK,
129 PRCMU_RNGCLK,
130 PRCMU_UICCCLK,
131 PRCMU_PWMCLK,
132 PRCMU_IRDACLK,
133 PRCMU_IRRCCLK,
134 PRCMU_SIACLK,
135 PRCMU_SVACLK,
136 PRCMU_ACLK,
137 PRCMU_HVACLK, /* Ux540 only */
138 PRCMU_G1CLK, /* Ux540 only */
139 PRCMU_SDMMCHCLK,
140 PRCMU_CAMCLK,
141 PRCMU_BML8580CLK,
142 PRCMU_NUM_REG_CLOCKS,
143 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
144 PRCMU_CDCLK,
145 PRCMU_TIMCLK,
146 PRCMU_PLLSOC0,
147 PRCMU_PLLSOC1,
148 PRCMU_ARMSS,
149 PRCMU_PLLDDR,
150 PRCMU_PLLDSI,
151 PRCMU_DSI0CLK,
152 PRCMU_DSI1CLK,
153 PRCMU_DSI0ESCCLK,
154 PRCMU_DSI1ESCCLK,
155 PRCMU_DSI2ESCCLK,
156 /* LCD DSI PLL - Ux540 only */
157 PRCMU_PLLDSI_LCD,
158 PRCMU_DSI0CLK_LCD,
159 PRCMU_DSI1CLK_LCD,
160 PRCMU_DSI0ESCCLK_LCD,
161 PRCMU_DSI1ESCCLK_LCD,
162 PRCMU_DSI2ESCCLK_LCD,
163};
164
165/** 99/**
166 * enum prcmu_wdog_id - PRCMU watchdog IDs 100 * enum prcmu_wdog_id - PRCMU watchdog IDs
167 * @PRCMU_WDOG_ALL: use all timers 101 * @PRCMU_WDOG_ALL: use all timers
diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h
index 9d98f3aaa16c..97baf831e071 100644
--- a/include/linux/platform_data/clk-ux500.h
+++ b/include/linux/platform_data/clk-ux500.h
@@ -10,6 +10,9 @@
10#ifndef __CLK_UX500_H 10#ifndef __CLK_UX500_H
11#define __CLK_UX500_H 11#define __CLK_UX500_H
12 12
13void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
14 u32 clkrst5_base, u32 clkrst6_base);
15
13void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, 16void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
14 u32 clkrst5_base, u32 clkrst6_base); 17 u32 clkrst5_base, u32 clkrst6_base);
15void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, 18void u9540_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
diff --git a/include/linux/platform_data/pinctrl-single.h b/include/linux/platform_data/pinctrl-single.h
new file mode 100644
index 000000000000..72eacda9b360
--- /dev/null
+++ b/include/linux/platform_data/pinctrl-single.h
@@ -0,0 +1,12 @@
1/**
2 * irq: optional wake-up interrupt
3 * rearm: optional soc specific rearm function
4 *
5 * Note that the irq and rearm setup should come from device
6 * tree except for omap where there are still some dependencies
7 * to the legacy PRM code.
8 */
9struct pcs_pdata {
10 int irq;
11 void (*rearm)(void);
12};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 02:31:49 -0400