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-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c238
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c50
-rw-r--r--arch/arm/mach-omap2/clkt_iclk.c41
-rw-r--r--arch/arm/mach-omap2/clock.c784
-rw-r--r--arch/arm/mach-omap2/clock.h221
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c20
-rw-r--r--arch/arm/mach-omap2/clockdomain.c4
7 files changed, 2 insertions, 1356 deletions
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 03ceb2efd532..0ec9f6fdf046 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -41,11 +41,7 @@
41 41
42#include <linux/kernel.h> 42#include <linux/kernel.h>
43#include <linux/errno.h> 43#include <linux/errno.h>
44#ifdef CONFIG_COMMON_CLK
45#include <linux/clk-provider.h> 44#include <linux/clk-provider.h>
46#else
47#include <linux/clk.h>
48#endif
49#include <linux/io.h> 45#include <linux/io.h>
50#include <linux/bug.h> 46#include <linux/bug.h>
51 47
@@ -62,11 +58,7 @@
62 * the element associated with the supplied parent clock address. 58 * the element associated with the supplied parent clock address.
63 * Returns a pointer to the struct clksel on success or NULL on error. 59 * Returns a pointer to the struct clksel on success or NULL on error.
64 */ 60 */
65#ifdef CONFIG_COMMON_CLK
66static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, 61static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk,
67#else
68static const struct clksel *_get_clksel_by_parent(struct clk *clk,
69#endif
70 struct clk *src_clk) 62 struct clk *src_clk)
71{ 63{
72 const struct clksel *clks; 64 const struct clksel *clks;
@@ -81,11 +73,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
81 if (!clks->parent) { 73 if (!clks->parent) {
82 /* This indicates a data problem */ 74 /* This indicates a data problem */
83 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", 75 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
84#ifdef CONFIG_COMMON_CLK
85 __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); 76 __clk_get_name(clk->hw.clk), __clk_get_name(src_clk));
86#else
87 __clk_get_name(clk), __clk_get_name(src_clk));
88#endif
89 return NULL; 77 return NULL;
90 } 78 }
91 79
@@ -93,66 +81,6 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
93} 81}
94 82
95/** 83/**
96 * _get_div_and_fieldval() - find the new clksel divisor and field value to use
97 * @src_clk: planned new parent struct clk *
98 * @clk: struct clk * that is being reparented
99 * @field_val: pointer to a u32 to contain the register data for the divisor
100 *
101 * Given an intended new parent struct clk * @src_clk, and the struct
102 * clk * @clk to the clock that is being reparented, find the
103 * appropriate rate divisor for the new clock (returned as the return
104 * value), and the corresponding register bitfield data to program to
105 * reach that divisor (returned in the u32 pointed to by @field_val).
106 * Returns 0 on error, or returns the newly-selected divisor upon
107 * success (in this latter case, the corresponding register bitfield
108 * value is passed back in the variable pointed to by @field_val)
109 */
110#ifndef CONFIG_COMMON_CLK
111static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
112 u32 *field_val)
113{
114 const struct clksel *clks;
115 const struct clksel_rate *clkr, *max_clkr = NULL;
116 u8 max_div = 0;
117
118 clks = _get_clksel_by_parent(clk, src_clk);
119 if (!clks)
120 return 0;
121
122 /*
123 * Find the highest divisor (e.g., the one resulting in the
124 * lowest rate) to use as the default. This should avoid
125 * clock rates that are too high for the device. XXX A better
126 * solution here would be to try to determine if there is a
127 * divisor matching the original clock rate before the parent
128 * switch, and if it cannot be found, to fall back to the
129 * highest divisor.
130 */
131 for (clkr = clks->rates; clkr->div; clkr++) {
132 if (!(clkr->flags & cpu_mask))
133 continue;
134
135 if (clkr->div > max_div) {
136 max_div = clkr->div;
137 max_clkr = clkr;
138 }
139 }
140
141 if (max_div == 0) {
142 /* This indicates an error in the clksel data */
143 WARN(1, "clock: %s: could not find divisor for parent %s\n",
144 __clk_get_name(clk),
145 __clk_get_name(__clk_get_parent(src_clk)));
146 return 0;
147 }
148
149 *field_val = max_clkr->val;
150
151 return max_div;
152}
153#endif
154
155/**
156 * _write_clksel_reg() - program a clock's clksel register in hardware 84 * _write_clksel_reg() - program a clock's clksel register in hardware
157 * @clk: struct clk * to program 85 * @clk: struct clk * to program
158 * @v: clksel bitfield value to program (with LSB at bit 0) 86 * @v: clksel bitfield value to program (with LSB at bit 0)
@@ -165,11 +93,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
165 * take into account any time the hardware might take to switch the 93 * take into account any time the hardware might take to switch the
166 * clock source. 94 * clock source.
167 */ 95 */
168#ifdef CONFIG_COMMON_CLK
169static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) 96static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
170#else
171static void _write_clksel_reg(struct clk *clk, u32 field_val)
172#endif
173{ 97{
174 u32 v; 98 u32 v;
175 99
@@ -192,21 +116,13 @@ static void _write_clksel_reg(struct clk *clk, u32 field_val)
192 * before calling. Returns 0 on error or returns the actual integer divisor 116 * before calling. Returns 0 on error or returns the actual integer divisor
193 * upon success. 117 * upon success.
194 */ 118 */
195#ifdef CONFIG_COMMON_CLK
196static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) 119static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val)
197#else
198static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
199#endif
200{ 120{
201 const struct clksel *clks; 121 const struct clksel *clks;
202 const struct clksel_rate *clkr; 122 const struct clksel_rate *clkr;
203 struct clk *parent; 123 struct clk *parent;
204 124
205#ifdef CONFIG_COMMON_CLK
206 parent = __clk_get_parent(clk->hw.clk); 125 parent = __clk_get_parent(clk->hw.clk);
207#else
208 parent = __clk_get_parent(clk);
209#endif
210 126
211 clks = _get_clksel_by_parent(clk, parent); 127 clks = _get_clksel_by_parent(clk, parent);
212 if (!clks) 128 if (!clks)
@@ -223,12 +139,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
223 if (!clkr->div) { 139 if (!clkr->div) {
224 /* This indicates a data error */ 140 /* This indicates a data error */
225 WARN(1, "clock: %s: could not find fieldval %d for parent %s\n", 141 WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
226#ifdef CONFIG_COMMON_CLK
227 __clk_get_name(clk->hw.clk), field_val, 142 __clk_get_name(clk->hw.clk), field_val,
228 __clk_get_name(parent)); 143 __clk_get_name(parent));
229#else
230 __clk_get_name(clk), field_val, __clk_get_name(parent));
231#endif
232 return 0; 144 return 0;
233 } 145 }
234 146
@@ -245,11 +157,7 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
245 * register field value _before_ left-shifting (i.e., LSB is at bit 157 * register field value _before_ left-shifting (i.e., LSB is at bit
246 * 0); or returns 0xFFFFFFFF (~0) upon error. 158 * 0); or returns 0xFFFFFFFF (~0) upon error.
247 */ 159 */
248#ifdef CONFIG_COMMON_CLK
249static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) 160static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div)
250#else
251static u32 _divisor_to_clksel(struct clk *clk, u32 div)
252#endif
253{ 161{
254 const struct clksel *clks; 162 const struct clksel *clks;
255 const struct clksel_rate *clkr; 163 const struct clksel_rate *clkr;
@@ -258,11 +166,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
258 /* should never happen */ 166 /* should never happen */
259 WARN_ON(div == 0); 167 WARN_ON(div == 0);
260 168
261#ifdef CONFIG_COMMON_CLK
262 parent = __clk_get_parent(clk->hw.clk); 169 parent = __clk_get_parent(clk->hw.clk);
263#else
264 parent = __clk_get_parent(clk);
265#endif
266 clks = _get_clksel_by_parent(clk, parent); 170 clks = _get_clksel_by_parent(clk, parent);
267 if (!clks) 171 if (!clks)
268 return ~0; 172 return ~0;
@@ -277,12 +181,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
277 181
278 if (!clkr->div) { 182 if (!clkr->div) {
279 pr_err("clock: %s: could not find divisor %d for parent %s\n", 183 pr_err("clock: %s: could not find divisor %d for parent %s\n",
280#ifdef CONFIG_COMMON_CLK
281 __clk_get_name(clk->hw.clk), div, 184 __clk_get_name(clk->hw.clk), div,
282 __clk_get_name(parent)); 185 __clk_get_name(parent));
283#else
284 __clk_get_name(clk), div, __clk_get_name(parent));
285#endif
286 return ~0; 186 return ~0;
287 } 187 }
288 188
@@ -297,11 +197,7 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
297 * into the hardware, convert it into the actual divisor value, and 197 * into the hardware, convert it into the actual divisor value, and
298 * return it; or return 0 on error. 198 * return it; or return 0 on error.
299 */ 199 */
300#ifdef CONFIG_COMMON_CLK
301static u32 _read_divisor(struct clk_hw_omap *clk) 200static u32 _read_divisor(struct clk_hw_omap *clk)
302#else
303static u32 _read_divisor(struct clk *clk)
304#endif
305{ 201{
306 u32 v; 202 u32 v;
307 203
@@ -329,12 +225,8 @@ static u32 _read_divisor(struct clk *clk)
329 * 225 *
330 * Returns the rounded clock rate or returns 0xffffffff on error. 226 * Returns the rounded clock rate or returns 0xffffffff on error.
331 */ 227 */
332#ifdef CONFIG_COMMON_CLK
333u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, 228u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
334 unsigned long target_rate, 229 unsigned long target_rate,
335#else
336u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
337#endif
338 u32 *new_div) 230 u32 *new_div)
339{ 231{
340 unsigned long test_rate; 232 unsigned long test_rate;
@@ -345,13 +237,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
345 unsigned long parent_rate; 237 unsigned long parent_rate;
346 const char *clk_name; 238 const char *clk_name;
347 239
348#ifdef CONFIG_COMMON_CLK
349 parent = __clk_get_parent(clk->hw.clk); 240 parent = __clk_get_parent(clk->hw.clk);
350 clk_name = __clk_get_name(clk->hw.clk); 241 clk_name = __clk_get_name(clk->hw.clk);
351#else
352 parent = __clk_get_parent(clk);
353 clk_name = __clk_get_name(clk);
354#endif
355 parent_rate = __clk_get_rate(parent); 242 parent_rate = __clk_get_rate(parent);
356 243
357 if (!clk->clksel || !clk->clksel_mask) 244 if (!clk->clksel || !clk->clksel_mask)
@@ -402,7 +289,6 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
402 * (i.e., those used in struct clk field function pointers, etc.) 289 * (i.e., those used in struct clk field function pointers, etc.)
403 */ 290 */
404 291
405#ifdef CONFIG_COMMON_CLK
406/** 292/**
407 * omap2_clksel_find_parent_index() - return the array index of the current 293 * omap2_clksel_find_parent_index() - return the array index of the current
408 * hardware parent of @hw 294 * hardware parent of @hw
@@ -457,62 +343,6 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
457 return ret; 343 return ret;
458} 344}
459 345
460#else
461
462/**
463 * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
464 * @clk: OMAP clock struct ptr to use
465 *
466 * Given a pointer @clk to a source-selectable struct clk, read the
467 * hardware register and determine what its parent is currently set
468 * to. Update @clk's .parent field with the appropriate clk ptr. No
469 * return value.
470 */
471void omap2_init_clksel_parent(struct clk *clk)
472{
473 const struct clksel *clks;
474 const struct clksel_rate *clkr;
475 u32 r, found = 0;
476 struct clk *parent;
477 const char *clk_name;
478
479 if (!clk->clksel || !clk->clksel_mask)
480 return;
481
482 parent = __clk_get_parent(clk);
483 clk_name = __clk_get_name(clk);
484
485 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
486 r >>= __ffs(clk->clksel_mask);
487
488 for (clks = clk->clksel; clks->parent && !found; clks++) {
489 for (clkr = clks->rates; clkr->div && !found; clkr++) {
490 if (!(clkr->flags & cpu_mask))
491 continue;
492
493 if (clkr->val == r) {
494 if (parent != clks->parent) {
495 pr_debug("clock: %s: inited parent to %s (was %s)\n",
496 clk_name,
497 __clk_get_name(clks->parent),
498 ((parent) ?
499 __clk_get_name(parent) :
500 "NULL"));
501 clk_reparent(clk, clks->parent);
502 }
503 found = 1;
504 }
505 }
506 }
507
508 /* This indicates a data error */
509 WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
510 clk_name, r);
511
512 return;
513}
514
515#endif
516 346
517/** 347/**
518 * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field 348 * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
@@ -523,7 +353,6 @@ void omap2_init_clksel_parent(struct clk *clk)
523 * function. Returns the clock's current rate, based on its parent's rate 353 * function. Returns the clock's current rate, based on its parent's rate
524 * and its current divisor setting in the hardware. 354 * and its current divisor setting in the hardware.
525 */ 355 */
526#ifdef CONFIG_COMMON_CLK
527unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate) 356unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
528{ 357{
529 unsigned long rate; 358 unsigned long rate;
@@ -544,26 +373,6 @@ unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate)
544 373
545 return rate; 374 return rate;
546} 375}
547#else
548unsigned long omap2_clksel_recalc(struct clk *clk)
549{
550 unsigned long rate;
551 u32 div = 0;
552 struct clk *parent;
553
554 div = _read_divisor(clk);
555 if (div == 0)
556 return __clk_get_rate(clk);
557
558 parent = __clk_get_parent(clk);
559 rate = __clk_get_rate(parent) / div;
560
561 pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
562 __clk_get_name(clk), rate, div);
563
564 return rate;
565}
566#endif
567 376
568/** 377/**
569 * omap2_clksel_round_rate() - find rounded rate for the given clock and rate 378 * omap2_clksel_round_rate() - find rounded rate for the given clock and rate
@@ -576,15 +385,10 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
576 * 385 *
577 * Returns the rounded clock rate or returns 0xffffffff on error. 386 * Returns the rounded clock rate or returns 0xffffffff on error.
578 */ 387 */
579#ifdef CONFIG_COMMON_CLK
580long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate, 388long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
581 unsigned long *parent_rate) 389 unsigned long *parent_rate)
582{ 390{
583 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 391 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
584#else
585long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
586{
587#endif
588 u32 new_div; 392 u32 new_div;
589 393
590 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 394 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
@@ -605,15 +409,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
605 * is changed, they will all be affected without any notification. 409 * is changed, they will all be affected without any notification.
606 * Returns -EINVAL upon error, or 0 upon success. 410 * Returns -EINVAL upon error, or 0 upon success.
607 */ 411 */
608#ifdef CONFIG_COMMON_CLK
609int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, 412int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
610 unsigned long parent_rate) 413 unsigned long parent_rate)
611{ 414{
612 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 415 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
613#else
614int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
615{
616#endif
617 u32 field_val, validrate, new_div = 0; 416 u32 field_val, validrate, new_div = 0;
618 417
619 if (!clk->clksel || !clk->clksel_mask) 418 if (!clk->clksel || !clk->clksel_mask)
@@ -629,15 +428,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
629 428
630 _write_clksel_reg(clk, field_val); 429 _write_clksel_reg(clk, field_val);
631 430
632#ifdef CONFIG_COMMON_CLK
633 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), 431 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk),
634 __clk_get_rate(hw->clk)); 432 __clk_get_rate(hw->clk));
635#else
636 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
637 __clk_get_rate(clk));
638
639 clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
640#endif
641 433
642 return 0; 434 return 0;
643} 435}
@@ -662,7 +454,6 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
662 * affected without any notification. Returns -EINVAL upon error, or 454 * affected without any notification. Returns -EINVAL upon error, or
663 * 0 upon success. 455 * 0 upon success.
664 */ 456 */
665#ifdef CONFIG_COMMON_CLK
666int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val) 457int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
667{ 458{
668 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 459 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
@@ -673,32 +464,3 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val)
673 _write_clksel_reg(clk, field_val); 464 _write_clksel_reg(clk, field_val);
674 return 0; 465 return 0;
675} 466}
676#else
677int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
678{
679 u32 field_val = 0;
680 u32 parent_div;
681
682 if (!clk->clksel || !clk->clksel_mask)
683 return -EINVAL;
684
685 parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
686 if (!parent_div)
687 return -EINVAL;
688 _write_clksel_reg(clk, field_val);
689
690 clk_reparent(clk, new_parent);
691
692 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
693 clk->rate = __clk_get_rate(new_parent);
694
695 if (parent_div > 0)
696 __clk_get_rate(clk) /= parent_div;
697 pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
698 __clk_get_name(clk),
699 __clk_get_name(__clk_get_parent(clk)),
700 __clk_get_rate(clk));
701
702 return 0;
703}
704#endif
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index f343389fc6e8..924c230f8948 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -16,11 +16,7 @@
16 16
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/errno.h> 18#include <linux/errno.h>
19#ifdef CONFIG_COMMON_CLK
20#include <linux/clk-provider.h> 19#include <linux/clk-provider.h>
21#else
22#include <linux/clk.h>
23#endif
24#include <linux/io.h> 20#include <linux/io.h>
25 21
26#include <asm/div64.h> 22#include <asm/div64.h>
@@ -80,11 +76,7 @@
80 * (assuming that it is counting N upwards), or -2 if the enclosing loop 76 * (assuming that it is counting N upwards), or -2 if the enclosing loop
81 * should skip to the next iteration (again assuming N is increasing). 77 * should skip to the next iteration (again assuming N is increasing).
82 */ 78 */
83#ifdef CONFIG_COMMON_CLK
84static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) 79static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
85#else
86static int _dpll_test_fint(struct clk *clk, u8 n)
87#endif
88{ 80{
89 struct dpll_data *dd; 81 struct dpll_data *dd;
90 long fint, fint_min, fint_max; 82 long fint, fint_min, fint_max;
@@ -93,11 +85,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
93 dd = clk->dpll_data; 85 dd = clk->dpll_data;
94 86
95 /* DPLL divider must result in a valid jitter correction val */ 87 /* DPLL divider must result in a valid jitter correction val */
96#ifdef CONFIG_COMMON_CLK
97 fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; 88 fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
98#else
99 fint = __clk_get_rate(__clk_get_parent(clk)) / n;
100#endif
101 89
102 if (cpu_is_omap24xx()) { 90 if (cpu_is_omap24xx()) {
103 /* Should not be called for OMAP2, so warn if it is called */ 91 /* Should not be called for OMAP2, so warn if it is called */
@@ -198,24 +186,15 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
198} 186}
199 187
200/* Public functions */ 188/* Public functions */
201#ifdef CONFIG_COMMON_CLK
202u8 omap2_init_dpll_parent(struct clk_hw *hw) 189u8 omap2_init_dpll_parent(struct clk_hw *hw)
203{ 190{
204 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 191 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
205#else
206void omap2_init_dpll_parent(struct clk *clk)
207{
208#endif
209 u32 v; 192 u32 v;
210 struct dpll_data *dd; 193 struct dpll_data *dd;
211 194
212 dd = clk->dpll_data; 195 dd = clk->dpll_data;
213 if (!dd) 196 if (!dd)
214#ifdef CONFIG_COMMON_CLK
215 return -EINVAL; 197 return -EINVAL;
216#else
217 return;
218#endif
219 198
220 v = __raw_readl(dd->control_reg); 199 v = __raw_readl(dd->control_reg);
221 v &= dd->enable_mask; 200 v &= dd->enable_mask;
@@ -225,34 +204,18 @@ void omap2_init_dpll_parent(struct clk *clk)
225 if (cpu_is_omap24xx()) { 204 if (cpu_is_omap24xx()) {
226 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 205 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
227 v == OMAP2XXX_EN_DPLL_FRBYPASS) 206 v == OMAP2XXX_EN_DPLL_FRBYPASS)
228#ifdef CONFIG_COMMON_CLK
229 return 1; 207 return 1;
230#else
231 clk_reparent(clk, dd->clk_bypass);
232#endif
233 } else if (cpu_is_omap34xx()) { 208 } else if (cpu_is_omap34xx()) {
234 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 209 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
235 v == OMAP3XXX_EN_DPLL_FRBYPASS) 210 v == OMAP3XXX_EN_DPLL_FRBYPASS)
236#ifdef CONFIG_COMMON_CLK
237 return 1; 211 return 1;
238#else
239 clk_reparent(clk, dd->clk_bypass);
240#endif
241 } else if (soc_is_am33xx() || cpu_is_omap44xx()) { 212 } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
242 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 213 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
243 v == OMAP4XXX_EN_DPLL_FRBYPASS || 214 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
244 v == OMAP4XXX_EN_DPLL_MNBYPASS) 215 v == OMAP4XXX_EN_DPLL_MNBYPASS)
245#ifdef CONFIG_COMMON_CLK
246 return 1; 216 return 1;
247#else
248 clk_reparent(clk, dd->clk_bypass);
249#endif
250 } 217 }
251#ifdef CONFIG_COMMON_CLK
252 return 0; 218 return 0;
253#else
254 return;
255#endif
256} 219}
257 220
258/** 221/**
@@ -269,11 +232,7 @@ void omap2_init_dpll_parent(struct clk *clk)
269 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 232 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
270 * if the clock @clk is not a DPLL. 233 * if the clock @clk is not a DPLL.
271 */ 234 */
272#ifdef CONFIG_COMMON_CLK
273unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) 235unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
274#else
275u32 omap2_get_dpll_rate(struct clk *clk)
276#endif
277{ 236{
278 long long dpll_clk; 237 long long dpll_clk;
279 u32 dpll_mult, dpll_div, v; 238 u32 dpll_mult, dpll_div, v;
@@ -329,15 +288,10 @@ u32 omap2_get_dpll_rate(struct clk *clk)
329 * (expensive) function again. Returns ~0 if the target rate cannot 288 * (expensive) function again. Returns ~0 if the target rate cannot
330 * be rounded, or the rounded rate upon success. 289 * be rounded, or the rounded rate upon success.
331 */ 290 */
332#ifdef CONFIG_COMMON_CLK
333long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 291long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
334 unsigned long *parent_rate) 292 unsigned long *parent_rate)
335{ 293{
336 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 294 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
337#else
338long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
339{
340#endif
341 int m, n, r, scaled_max_m; 295 int m, n, r, scaled_max_m;
342 unsigned long scaled_rt_rp; 296 unsigned long scaled_rt_rp;
343 unsigned long new_rate = 0; 297 unsigned long new_rate = 0;
@@ -351,11 +305,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
351 dd = clk->dpll_data; 305 dd = clk->dpll_data;
352 306
353 ref_rate = __clk_get_rate(dd->clk_ref); 307 ref_rate = __clk_get_rate(dd->clk_ref);
354#ifdef CONFIG_COMMON_CLK
355 clk_name = __clk_get_name(hw->clk); 308 clk_name = __clk_get_name(hw->clk);
356#else
357 clk_name = __clk_get_name(clk);
358#endif
359 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", 309 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
360 clk_name, target_rate); 310 clk_name, target_rate);
361 311
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index 650c8c77a573..f10eb03ce3e2 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -11,11 +11,7 @@
11#undef DEBUG 11#undef DEBUG
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#ifdef CONFIG_COMMON_CLK
15#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
16#else
17#include <linux/clk.h>
18#endif
19#include <linux/io.h> 15#include <linux/io.h>
20 16
21 17
@@ -27,11 +23,7 @@
27/* Private functions */ 23/* Private functions */
28 24
29/* XXX */ 25/* XXX */
30#ifdef CONFIG_COMMON_CLK
31void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) 26void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
32#else
33void omap2_clkt_iclk_allow_idle(struct clk *clk)
34#endif
35{ 27{
36 u32 v, r; 28 u32 v, r;
37 29
@@ -43,11 +35,7 @@ void omap2_clkt_iclk_allow_idle(struct clk *clk)
43} 35}
44 36
45/* XXX */ 37/* XXX */
46#ifdef CONFIG_COMMON_CLK
47void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) 38void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
48#else
49void omap2_clkt_iclk_deny_idle(struct clk *clk)
50#endif
51{ 39{
52 u32 v, r; 40 u32 v, r;
53 41
@@ -60,7 +48,6 @@ void omap2_clkt_iclk_deny_idle(struct clk *clk)
60 48
61/* Public data */ 49/* Public data */
62 50
63#ifdef CONFIG_COMMON_CLK
64const struct clk_hw_omap_ops clkhwops_iclk = { 51const struct clk_hw_omap_ops clkhwops_iclk = {
65 .allow_idle = omap2_clkt_iclk_allow_idle, 52 .allow_idle = omap2_clkt_iclk_allow_idle,
66 .deny_idle = omap2_clkt_iclk_deny_idle, 53 .deny_idle = omap2_clkt_iclk_deny_idle,
@@ -72,34 +59,6 @@ const struct clk_hw_omap_ops clkhwops_iclk_wait = {
72 .find_idlest = omap2_clk_dflt_find_idlest, 59 .find_idlest = omap2_clk_dflt_find_idlest,
73 .find_companion = omap2_clk_dflt_find_companion, 60 .find_companion = omap2_clk_dflt_find_companion,
74}; 61};
75#else
76const struct clkops clkops_omap2_iclk_dflt_wait = {
77 .enable = omap2_dflt_clk_enable,
78 .disable = omap2_dflt_clk_disable,
79 .find_companion = omap2_clk_dflt_find_companion,
80 .find_idlest = omap2_clk_dflt_find_idlest,
81 .allow_idle = omap2_clkt_iclk_allow_idle,
82 .deny_idle = omap2_clkt_iclk_deny_idle,
83};
84 62
85const struct clkops clkops_omap2_iclk_dflt = {
86 .enable = omap2_dflt_clk_enable,
87 .disable = omap2_dflt_clk_disable,
88 .allow_idle = omap2_clkt_iclk_allow_idle,
89 .deny_idle = omap2_clkt_iclk_deny_idle,
90};
91 63
92const struct clkops clkops_omap2_iclk_idle_only = {
93 .allow_idle = omap2_clkt_iclk_allow_idle,
94 .deny_idle = omap2_clkt_iclk_deny_idle,
95};
96 64
97const struct clkops clkops_omap2_mdmclk_dflt_wait = {
98 .enable = omap2_dflt_clk_enable,
99 .disable = omap2_dflt_clk_disable,
100 .find_companion = omap2_clk_dflt_find_companion,
101 .find_idlest = omap2_clk_dflt_find_idlest,
102 .allow_idle = omap2_clkt_iclk_allow_idle,
103 .deny_idle = omap2_clkt_iclk_deny_idle,
104};
105#endif
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 744e6eb17b26..e4ec3a69ee2e 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -20,11 +20,7 @@
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#ifdef CONFIG_COMMON_CLK
24#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
25#else
26#include <linux/clk.h>
27#endif
28#include <linux/io.h> 24#include <linux/io.h>
29#include <linux/bitops.h> 25#include <linux/bitops.h>
30 26
@@ -59,13 +55,6 @@ u16 cpu_mask;
59 */ 55 */
60static bool clkdm_control = true; 56static bool clkdm_control = true;
61 57
62static LIST_HEAD(clocks);
63static DEFINE_MUTEX(clocks_mutex);
64#ifndef CONFIG_COMMON_CLK
65static DEFINE_SPINLOCK(clockfw_lock);
66#endif
67
68#ifdef CONFIG_COMMON_CLK
69static LIST_HEAD(clk_hw_omap_clocks); 58static LIST_HEAD(clk_hw_omap_clocks);
70 59
71/* 60/*
@@ -88,7 +77,6 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
88 77
89 return parent_rate / oclk->fixed_div; 78 return parent_rate / oclk->fixed_div;
90} 79}
91#endif
92 80
93/* 81/*
94 * OMAP2+ specific clock functions 82 * OMAP2+ specific clock functions
@@ -140,11 +128,7 @@ static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
140 * belong in the clock code and will be moved in the medium term to 128 * belong in the clock code and will be moved in the medium term to
141 * module-dependent code. No return value. 129 * module-dependent code. No return value.
142 */ 130 */
143#ifdef CONFIG_COMMON_CLK
144static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 131static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
145#else
146static void _omap2_module_wait_ready(struct clk *clk)
147#endif
148{ 132{
149 void __iomem *companion_reg, *idlest_reg; 133 void __iomem *companion_reg, *idlest_reg;
150 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 134 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
@@ -163,11 +147,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
163 if (r) { 147 if (r) {
164 /* IDLEST register not in the CM module */ 148 /* IDLEST register not in the CM module */
165 _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, 149 _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
166#ifdef CONFIG_COMMON_CLK
167 __clk_get_name(clk->hw.clk)); 150 __clk_get_name(clk->hw.clk));
168#else
169 clk->name);
170#endif
171 } else { 151 } else {
172 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); 152 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
173 }; 153 };
@@ -183,25 +163,16 @@ static void _omap2_module_wait_ready(struct clk *clk)
183 * clockdomain pointer, and save it into the struct clk. Intended to be 163 * clockdomain pointer, and save it into the struct clk. Intended to be
184 * called during clk_register(). No return value. 164 * called during clk_register(). No return value.
185 */ 165 */
186#ifdef CONFIG_COMMON_CLK
187void omap2_init_clk_clkdm(struct clk_hw *hw) 166void omap2_init_clk_clkdm(struct clk_hw *hw)
188{ 167{
189 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 168 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
190#else
191void omap2_init_clk_clkdm(struct clk *clk)
192{
193#endif
194 struct clockdomain *clkdm; 169 struct clockdomain *clkdm;
195 const char *clk_name; 170 const char *clk_name;
196 171
197 if (!clk->clkdm_name) 172 if (!clk->clkdm_name)
198 return; 173 return;
199 174
200#ifdef CONFIG_COMMON_CLK
201 clk_name = __clk_get_name(hw->clk); 175 clk_name = __clk_get_name(hw->clk);
202#else
203 clk_name = __clk_get_name(clk);
204#endif
205 176
206 clkdm = clkdm_lookup(clk->clkdm_name); 177 clkdm = clkdm_lookup(clk->clkdm_name);
207 if (clkdm) { 178 if (clkdm) {
@@ -248,11 +219,7 @@ void __init omap2_clk_disable_clkdm_control(void)
248 * associate this type of code with per-module data structures to 219 * associate this type of code with per-module data structures to
249 * avoid this issue, and remove the casts. No return value. 220 * avoid this issue, and remove the casts. No return value.
250 */ 221 */
251#ifdef CONFIG_COMMON_CLK
252void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 222void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
253#else
254void omap2_clk_dflt_find_companion(struct clk *clk,
255#endif
256 void __iomem **other_reg, u8 *other_bit) 223 void __iomem **other_reg, u8 *other_bit)
257{ 224{
258 u32 r; 225 u32 r;
@@ -281,11 +248,7 @@ void omap2_clk_dflt_find_companion(struct clk *clk,
281 * register address ID (e.g., that CM_FCLKEN2 corresponds to 248 * register address ID (e.g., that CM_FCLKEN2 corresponds to
282 * CM_IDLEST2). This is not true for all modules. No return value. 249 * CM_IDLEST2). This is not true for all modules. No return value.
283 */ 250 */
284#ifdef CONFIG_COMMON_CLK
285void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 251void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
286#else
287void omap2_clk_dflt_find_idlest(struct clk *clk,
288#endif
289 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) 252 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val)
290{ 253{
291 u32 r; 254 u32 r;
@@ -308,7 +271,6 @@ void omap2_clk_dflt_find_idlest(struct clk *clk,
308 271
309} 272}
310 273
311#ifdef CONFIG_COMMON_CLK
312/** 274/**
313 * omap2_dflt_clk_enable - enable a clock in the hardware 275 * omap2_dflt_clk_enable - enable a clock in the hardware
314 * @hw: struct clk_hw * of the clock to enable 276 * @hw: struct clk_hw * of the clock to enable
@@ -605,238 +567,6 @@ const struct clk_hw_omap_ops clkhwops_wait = {
605 .find_idlest = omap2_clk_dflt_find_idlest, 567 .find_idlest = omap2_clk_dflt_find_idlest,
606 .find_companion = omap2_clk_dflt_find_companion, 568 .find_companion = omap2_clk_dflt_find_companion,
607}; 569};
608#else
609int omap2_dflt_clk_enable(struct clk *clk)
610{
611 u32 v;
612
613 if (unlikely(clk->enable_reg == NULL)) {
614 pr_err("clock.c: Enable for %s without enable code\n",
615 clk->name);
616 return 0; /* REVISIT: -EINVAL */
617 }
618
619 v = __raw_readl(clk->enable_reg);
620 if (clk->flags & INVERT_ENABLE)
621 v &= ~(1 << clk->enable_bit);
622 else
623 v |= (1 << clk->enable_bit);
624 __raw_writel(v, clk->enable_reg);
625 v = __raw_readl(clk->enable_reg); /* OCP barrier */
626
627 if (clk->ops->find_idlest)
628 _omap2_module_wait_ready(clk);
629
630 return 0;
631}
632
633void omap2_dflt_clk_disable(struct clk *clk)
634{
635 u32 v;
636
637 if (!clk->enable_reg) {
638 /*
639 * 'Independent' here refers to a clock which is not
640 * controlled by its parent.
641 */
642 pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
643 return;
644 }
645
646 v = __raw_readl(clk->enable_reg);
647 if (clk->flags & INVERT_ENABLE)
648 v |= (1 << clk->enable_bit);
649 else
650 v &= ~(1 << clk->enable_bit);
651 __raw_writel(v, clk->enable_reg);
652 /* No OCP barrier needed here since it is a disable operation */
653}
654
655const struct clkops clkops_omap2_dflt_wait = {
656 .enable = omap2_dflt_clk_enable,
657 .disable = omap2_dflt_clk_disable,
658 .find_companion = omap2_clk_dflt_find_companion,
659 .find_idlest = omap2_clk_dflt_find_idlest,
660};
661
662const struct clkops clkops_omap2_dflt = {
663 .enable = omap2_dflt_clk_enable,
664 .disable = omap2_dflt_clk_disable,
665};
666
667/**
668 * omap2_clk_disable - disable a clock, if the system is not using it
669 * @clk: struct clk * to disable
670 *
671 * Decrements the usecount on struct clk @clk. If there are no users
672 * left, call the clkops-specific clock disable function to disable it
673 * in hardware. If the clock is part of a clockdomain (which they all
674 * should be), request that the clockdomain be disabled. (It too has
675 * a usecount, and so will not be disabled in the hardware until it no
676 * longer has any users.) If the clock has a parent clock (most of
677 * them do), then call ourselves, recursing on the parent clock. This
678 * can cause an entire branch of the clock tree to be powered off by
679 * simply disabling one clock. Intended to be called with the clockfw_lock
680 * spinlock held. No return value.
681 */
682void omap2_clk_disable(struct clk *clk)
683{
684 if (clk->usecount == 0) {
685 WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
686 return;
687 }
688
689 pr_debug("clock: %s: decrementing usecount\n", clk->name);
690
691 clk->usecount--;
692
693 if (clk->usecount > 0)
694 return;
695
696 pr_debug("clock: %s: disabling in hardware\n", clk->name);
697
698 if (clk->ops && clk->ops->disable) {
699 trace_clock_disable(clk->name, 0, smp_processor_id());
700 clk->ops->disable(clk);
701 }
702
703 if (clkdm_control && clk->clkdm)
704 clkdm_clk_disable(clk->clkdm, clk);
705
706 if (clk->parent)
707 omap2_clk_disable(clk->parent);
708}
709
710/**
711 * omap2_clk_enable - request that the system enable a clock
712 * @clk: struct clk * to enable
713 *
714 * Increments the usecount on struct clk @clk. If there were no users
715 * previously, then recurse up the clock tree, enabling all of the
716 * clock's parents and all of the parent clockdomains, and finally,
717 * enabling @clk's clockdomain, and @clk itself. Intended to be
718 * called with the clockfw_lock spinlock held. Returns 0 upon success
719 * or a negative error code upon failure.
720 */
721int omap2_clk_enable(struct clk *clk)
722{
723 int ret;
724
725 pr_debug("clock: %s: incrementing usecount\n", clk->name);
726
727 clk->usecount++;
728
729 if (clk->usecount > 1)
730 return 0;
731
732 pr_debug("clock: %s: enabling in hardware\n", clk->name);
733
734 if (clk->parent) {
735 ret = omap2_clk_enable(clk->parent);
736 if (ret) {
737 WARN(1, "clock: %s: could not enable parent %s: %d\n",
738 clk->name, clk->parent->name, ret);
739 goto oce_err1;
740 }
741 }
742
743 if (clkdm_control && clk->clkdm) {
744 ret = clkdm_clk_enable(clk->clkdm, clk);
745 if (ret) {
746 WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
747 clk->name, clk->clkdm->name, ret);
748 goto oce_err2;
749 }
750 }
751
752 if (clk->ops && clk->ops->enable) {
753 trace_clock_enable(clk->name, 1, smp_processor_id());
754 ret = clk->ops->enable(clk);
755 if (ret) {
756 WARN(1, "clock: %s: could not enable: %d\n",
757 clk->name, ret);
758 goto oce_err3;
759 }
760 }
761
762 return 0;
763
764oce_err3:
765 if (clkdm_control && clk->clkdm)
766 clkdm_clk_disable(clk->clkdm, clk);
767oce_err2:
768 if (clk->parent)
769 omap2_clk_disable(clk->parent);
770oce_err1:
771 clk->usecount--;
772
773 return ret;
774}
775
776/* Given a clock and a rate apply a clock specific rounding function */
777long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
778{
779 if (clk->round_rate)
780 return clk->round_rate(clk, rate);
781
782 return clk->rate;
783}
784
785/* Set the clock rate for a clock source */
786int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
787{
788 int ret = -EINVAL;
789
790 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
791
792 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
793 if (clk->set_rate) {
794 trace_clock_set_rate(clk->name, rate, smp_processor_id());
795 ret = clk->set_rate(clk, rate);
796 }
797
798 return ret;
799}
800
801int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
802{
803 if (!clk->clksel)
804 return -EINVAL;
805
806 if (clk->parent == new_parent)
807 return 0;
808
809 return omap2_clksel_set_parent(clk, new_parent);
810}
811
812/*
813 * OMAP2+ clock reset and init functions
814 */
815
816#ifdef CONFIG_OMAP_RESET_CLOCKS
817void omap2_clk_disable_unused(struct clk *clk)
818{
819 u32 regval32, v;
820
821 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
822
823 regval32 = __raw_readl(clk->enable_reg);
824 if ((regval32 & (1 << clk->enable_bit)) == v)
825 return;
826
827 pr_debug("Disabling unused clock \"%s\"\n", clk->name);
828 if (cpu_is_omap34xx()) {
829 omap2_clk_enable(clk);
830 omap2_clk_disable(clk);
831 } else {
832 clk->ops->disable(clk);
833 }
834 if (clk->clkdm != NULL)
835 pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
836}
837#endif
838
839#endif /* CONFIG_COMMON_CLK */
840 570
841/** 571/**
842 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 572 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
@@ -874,10 +604,6 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
874 } 604 }
875 605
876 calibrate_delay(); 606 calibrate_delay();
877#ifndef CONFIG_COMMON_CLK
878 recalculate_root_clocks();
879#endif
880
881 clk_put(mpurate_ck); 607 clk_put(mpurate_ck);
882 608
883 return 0; 609 return 0;
@@ -921,513 +647,3 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
921 (clk_get_rate(core_ck) / 1000000), 647 (clk_get_rate(core_ck) / 1000000),
922 (clk_get_rate(mpu_ck) / 1000000)); 648 (clk_get_rate(mpu_ck) / 1000000));
923} 649}
924
925#ifndef CONFIG_COMMON_CLK
926/* Common data */
927int clk_enable(struct clk *clk)
928{
929 unsigned long flags;
930 int ret;
931
932 if (clk == NULL || IS_ERR(clk))
933 return -EINVAL;
934
935 spin_lock_irqsave(&clockfw_lock, flags);
936 ret = omap2_clk_enable(clk);
937 spin_unlock_irqrestore(&clockfw_lock, flags);
938
939 return ret;
940}
941EXPORT_SYMBOL(clk_enable);
942
943void clk_disable(struct clk *clk)
944{
945 unsigned long flags;
946
947 if (clk == NULL || IS_ERR(clk))
948 return;
949
950 spin_lock_irqsave(&clockfw_lock, flags);
951 if (clk->usecount == 0) {
952 pr_err("Trying disable clock %s with 0 usecount\n",
953 clk->name);
954 WARN_ON(1);
955 goto out;
956 }
957
958 omap2_clk_disable(clk);
959
960out:
961 spin_unlock_irqrestore(&clockfw_lock, flags);
962}
963EXPORT_SYMBOL(clk_disable);
964
965unsigned long clk_get_rate(struct clk *clk)
966{
967 unsigned long flags;
968 unsigned long ret;
969
970 if (clk == NULL || IS_ERR(clk))
971 return 0;
972
973 spin_lock_irqsave(&clockfw_lock, flags);
974 ret = clk->rate;
975 spin_unlock_irqrestore(&clockfw_lock, flags);
976
977 return ret;
978}
979EXPORT_SYMBOL(clk_get_rate);
980
981/*
982 * Optional clock functions defined in include/linux/clk.h
983 */
984
985long clk_round_rate(struct clk *clk, unsigned long rate)
986{
987 unsigned long flags;
988 long ret;
989
990 if (clk == NULL || IS_ERR(clk))
991 return 0;
992
993 spin_lock_irqsave(&clockfw_lock, flags);
994 ret = omap2_clk_round_rate(clk, rate);
995 spin_unlock_irqrestore(&clockfw_lock, flags);
996
997 return ret;
998}
999EXPORT_SYMBOL(clk_round_rate);
1000
1001int clk_set_rate(struct clk *clk, unsigned long rate)
1002{
1003 unsigned long flags;
1004 int ret = -EINVAL;
1005
1006 if (clk == NULL || IS_ERR(clk))
1007 return ret;
1008
1009 spin_lock_irqsave(&clockfw_lock, flags);
1010 ret = omap2_clk_set_rate(clk, rate);
1011 if (ret == 0)
1012 propagate_rate(clk);
1013 spin_unlock_irqrestore(&clockfw_lock, flags);
1014
1015 return ret;
1016}
1017EXPORT_SYMBOL(clk_set_rate);
1018
1019int clk_set_parent(struct clk *clk, struct clk *parent)
1020{
1021 unsigned long flags;
1022 int ret = -EINVAL;
1023
1024 if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
1025 return ret;
1026
1027 spin_lock_irqsave(&clockfw_lock, flags);
1028 if (clk->usecount == 0) {
1029 ret = omap2_clk_set_parent(clk, parent);
1030 if (ret == 0)
1031 propagate_rate(clk);
1032 } else {
1033 ret = -EBUSY;
1034 }
1035 spin_unlock_irqrestore(&clockfw_lock, flags);
1036
1037 return ret;
1038}
1039EXPORT_SYMBOL(clk_set_parent);
1040
1041struct clk *clk_get_parent(struct clk *clk)
1042{
1043 return clk->parent;
1044}
1045EXPORT_SYMBOL(clk_get_parent);
1046
1047/*
1048 * OMAP specific clock functions shared between omap1 and omap2
1049 */
1050
1051int __initdata mpurate;
1052
1053/*
1054 * By default we use the rate set by the bootloader.
1055 * You can override this with mpurate= cmdline option.
1056 */
1057static int __init omap_clk_setup(char *str)
1058{
1059 get_option(&str, &mpurate);
1060
1061 if (!mpurate)
1062 return 1;
1063
1064 if (mpurate < 1000)
1065 mpurate *= 1000000;
1066
1067 return 1;
1068}
1069__setup("mpurate=", omap_clk_setup);
1070
1071/* Used for clocks that always have same value as the parent clock */
1072unsigned long followparent_recalc(struct clk *clk)
1073{
1074 return clk->parent->rate;
1075}
1076
1077/*
1078 * Used for clocks that have the same value as the parent clock,
1079 * divided by some factor
1080 */
1081unsigned long omap_fixed_divisor_recalc(struct clk *clk)
1082{
1083 WARN_ON(!clk->fixed_div);
1084
1085 return clk->parent->rate / clk->fixed_div;
1086}
1087
1088void clk_reparent(struct clk *child, struct clk *parent)
1089{
1090 list_del_init(&child->sibling);
1091 if (parent)
1092 list_add(&child->sibling, &parent->children);
1093 child->parent = parent;
1094
1095 /* now do the debugfs renaming to reattach the child
1096 to the proper parent */
1097}
1098
1099/* Propagate rate to children */
1100void propagate_rate(struct clk *tclk)
1101{
1102 struct clk *clkp;
1103
1104 list_for_each_entry(clkp, &tclk->children, sibling) {
1105 if (clkp->recalc)
1106 clkp->rate = clkp->recalc(clkp);
1107 propagate_rate(clkp);
1108 }
1109}
1110
1111static LIST_HEAD(root_clks);
1112
1113/**
1114 * recalculate_root_clocks - recalculate and propagate all root clocks
1115 *
1116 * Recalculates all root clocks (clocks with no parent), which if the
1117 * clock's .recalc is set correctly, should also propagate their rates.
1118 * Called at init.
1119 */
1120void recalculate_root_clocks(void)
1121{
1122 struct clk *clkp;
1123
1124 list_for_each_entry(clkp, &root_clks, sibling) {
1125 if (clkp->recalc)
1126 clkp->rate = clkp->recalc(clkp);
1127 propagate_rate(clkp);
1128 }
1129}
1130
1131/**
1132 * clk_preinit - initialize any fields in the struct clk before clk init
1133 * @clk: struct clk * to initialize
1134 *
1135 * Initialize any struct clk fields needed before normal clk initialization
1136 * can run. No return value.
1137 */
1138void clk_preinit(struct clk *clk)
1139{
1140 INIT_LIST_HEAD(&clk->children);
1141}
1142
1143int clk_register(struct clk *clk)
1144{
1145 if (clk == NULL || IS_ERR(clk))
1146 return -EINVAL;
1147
1148 /*
1149 * trap out already registered clocks
1150 */
1151 if (clk->node.next || clk->node.prev)
1152 return 0;
1153
1154 mutex_lock(&clocks_mutex);
1155 if (clk->parent)
1156 list_add(&clk->sibling, &clk->parent->children);
1157 else
1158 list_add(&clk->sibling, &root_clks);
1159
1160 list_add(&clk->node, &clocks);
1161 if (clk->init)
1162 clk->init(clk);
1163 mutex_unlock(&clocks_mutex);
1164
1165 return 0;
1166}
1167EXPORT_SYMBOL(clk_register);
1168
1169void clk_unregister(struct clk *clk)
1170{
1171 if (clk == NULL || IS_ERR(clk))
1172 return;
1173
1174 mutex_lock(&clocks_mutex);
1175 list_del(&clk->sibling);
1176 list_del(&clk->node);
1177 mutex_unlock(&clocks_mutex);
1178}
1179EXPORT_SYMBOL(clk_unregister);
1180
1181void clk_enable_init_clocks(void)
1182{
1183 struct clk *clkp;
1184
1185 list_for_each_entry(clkp, &clocks, node)
1186 if (clkp->flags & ENABLE_ON_INIT)
1187 clk_enable(clkp);
1188}
1189
1190/**
1191 * omap_clk_get_by_name - locate OMAP struct clk by its name
1192 * @name: name of the struct clk to locate
1193 *
1194 * Locate an OMAP struct clk by its name. Assumes that struct clk
1195 * names are unique. Returns NULL if not found or a pointer to the
1196 * struct clk if found.
1197 */
1198struct clk *omap_clk_get_by_name(const char *name)
1199{
1200 struct clk *c;
1201 struct clk *ret = NULL;
1202
1203 mutex_lock(&clocks_mutex);
1204
1205 list_for_each_entry(c, &clocks, node) {
1206 if (!strcmp(c->name, name)) {
1207 ret = c;
1208 break;
1209 }
1210 }
1211
1212 mutex_unlock(&clocks_mutex);
1213
1214 return ret;
1215}
1216
1217int omap_clk_enable_autoidle_all(void)
1218{
1219 struct clk *c;
1220 unsigned long flags;
1221
1222 spin_lock_irqsave(&clockfw_lock, flags);
1223
1224 list_for_each_entry(c, &clocks, node)
1225 if (c->ops->allow_idle)
1226 c->ops->allow_idle(c);
1227
1228 spin_unlock_irqrestore(&clockfw_lock, flags);
1229
1230 return 0;
1231}
1232
1233int omap_clk_disable_autoidle_all(void)
1234{
1235 struct clk *c;
1236 unsigned long flags;
1237
1238 spin_lock_irqsave(&clockfw_lock, flags);
1239
1240 list_for_each_entry(c, &clocks, node)
1241 if (c->ops->deny_idle)
1242 c->ops->deny_idle(c);
1243
1244 spin_unlock_irqrestore(&clockfw_lock, flags);
1245
1246 return 0;
1247}
1248
1249/*
1250 * Low level helpers
1251 */
1252static int clkll_enable_null(struct clk *clk)
1253{
1254 return 0;
1255}
1256
1257static void clkll_disable_null(struct clk *clk)
1258{
1259}
1260
1261const struct clkops clkops_null = {
1262 .enable = clkll_enable_null,
1263 .disable = clkll_disable_null,
1264};
1265
1266/*
1267 * Dummy clock
1268 *
1269 * Used for clock aliases that are needed on some OMAPs, but not others
1270 */
1271struct clk dummy_ck = {
1272 .name = "dummy",
1273 .ops = &clkops_null,
1274};
1275
1276/*
1277 *
1278 */
1279
1280#ifdef CONFIG_OMAP_RESET_CLOCKS
1281/*
1282 * Disable any unused clocks left on by the bootloader
1283 */
1284static int __init clk_disable_unused(void)
1285{
1286 struct clk *ck;
1287 unsigned long flags;
1288
1289 pr_info("clock: disabling unused clocks to save power\n");
1290
1291 spin_lock_irqsave(&clockfw_lock, flags);
1292 list_for_each_entry(ck, &clocks, node) {
1293 if (ck->ops == &clkops_null)
1294 continue;
1295
1296 if (ck->usecount > 0 || !ck->enable_reg)
1297 continue;
1298
1299 omap2_clk_disable_unused(ck);
1300 }
1301 spin_unlock_irqrestore(&clockfw_lock, flags);
1302
1303 return 0;
1304}
1305late_initcall(clk_disable_unused);
1306late_initcall(omap_clk_enable_autoidle_all);
1307#endif
1308
1309#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
1310/*
1311 * debugfs support to trace clock tree hierarchy and attributes
1312 */
1313
1314#include <linux/debugfs.h>
1315#include <linux/seq_file.h>
1316
1317static struct dentry *clk_debugfs_root;
1318
1319static int clk_dbg_show_summary(struct seq_file *s, void *unused)
1320{
1321 struct clk *c;
1322 struct clk *pa;
1323
1324 mutex_lock(&clocks_mutex);
1325 seq_printf(s, "%-30s %-30s %-10s %s\n",
1326 "clock-name", "parent-name", "rate", "use-count");
1327
1328 list_for_each_entry(c, &clocks, node) {
1329 pa = c->parent;
1330 seq_printf(s, "%-30s %-30s %-10lu %d\n",
1331 c->name, pa ? pa->name : "none", c->rate,
1332 c->usecount);
1333 }
1334 mutex_unlock(&clocks_mutex);
1335
1336 return 0;
1337}
1338
1339static int clk_dbg_open(struct inode *inode, struct file *file)
1340{
1341 return single_open(file, clk_dbg_show_summary, inode->i_private);
1342}
1343
1344static const struct file_operations debug_clock_fops = {
1345 .open = clk_dbg_open,
1346 .read = seq_read,
1347 .llseek = seq_lseek,
1348 .release = single_release,
1349};
1350
1351static int clk_debugfs_register_one(struct clk *c)
1352{
1353 int err;
1354 struct dentry *d;
1355 struct clk *pa = c->parent;
1356
1357 d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
1358 if (!d)
1359 return -ENOMEM;
1360 c->dent = d;
1361
1362 d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
1363 if (!d) {
1364 err = -ENOMEM;
1365 goto err_out;
1366 }
1367 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
1368 if (!d) {
1369 err = -ENOMEM;
1370 goto err_out;
1371 }
1372 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
1373 if (!d) {
1374 err = -ENOMEM;
1375 goto err_out;
1376 }
1377 return 0;
1378
1379err_out:
1380 debugfs_remove_recursive(c->dent);
1381 return err;
1382}
1383
1384static int clk_debugfs_register(struct clk *c)
1385{
1386 int err;
1387 struct clk *pa = c->parent;
1388
1389 if (pa && !pa->dent) {
1390 err = clk_debugfs_register(pa);
1391 if (err)
1392 return err;
1393 }
1394
1395 if (!c->dent) {
1396 err = clk_debugfs_register_one(c);
1397 if (err)
1398 return err;
1399 }
1400 return 0;
1401}
1402
1403static int __init clk_debugfs_init(void)
1404{
1405 struct clk *c;
1406 struct dentry *d;
1407 int err;
1408
1409 d = debugfs_create_dir("clock", NULL);
1410 if (!d)
1411 return -ENOMEM;
1412 clk_debugfs_root = d;
1413
1414 list_for_each_entry(c, &clocks, node) {
1415 err = clk_debugfs_register(c);
1416 if (err)
1417 goto err_out;
1418 }
1419
1420 d = debugfs_create_file("summary", S_IRUGO,
1421 d, NULL, &debug_clock_fops);
1422 if (!d)
1423 return -ENOMEM;
1424
1425 return 0;
1426err_out:
1427 debugfs_remove_recursive(clk_debugfs_root);
1428 return err;
1429}
1430late_initcall(clk_debugfs_init);
1431
1432#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
1433#endif /* CONFIG_COMMON_CLK */
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index baeaff229506..9917f793c3b6 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -20,6 +20,7 @@
20#include <linux/list.h> 20#include <linux/list.h>
21 21
22#include <linux/clkdev.h> 22#include <linux/clkdev.h>
23#include <linux/clk-provider.h>
23 24
24struct omap_clk { 25struct omap_clk {
25 u16 cpu; 26 u16 cpu;
@@ -52,9 +53,6 @@ struct omap_clk {
52#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) 53#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
53#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) 54#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
54 55
55#ifdef CONFIG_COMMON_CLK
56#include <linux/clk-provider.h>
57
58struct clockdomain; 56struct clockdomain;
59#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 57#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
60 58
@@ -134,48 +132,6 @@ struct clockdomain;
134 }; \ 132 }; \
135 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); 133 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
136 134
137
138#else
139
140struct module;
141struct clk;
142struct clockdomain;
143
144/* Temporary, needed during the common clock framework conversion */
145#define __clk_get_name(clk) (clk->name)
146#define __clk_get_parent(clk) (clk->parent)
147#define __clk_get_rate(clk) (clk->rate)
148
149/**
150 * struct clkops - some clock function pointers
151 * @enable: fn ptr that enables the current clock in hardware
152 * @disable: fn ptr that enables the current clock in hardware
153 * @find_idlest: function returning the IDLEST register for the clock's IP blk
154 * @find_companion: function returning the "companion" clk reg for the clock
155 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
156 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
157 *
158 * A "companion" clk is an accompanying clock to the one being queried
159 * that must be enabled for the IP module connected to the clock to
160 * become accessible by the hardware. Neither @find_idlest nor
161 * @find_companion should be needed; that information is IP
162 * block-specific; the hwmod code has been created to handle this, but
163 * until hwmod data is ready and drivers have been converted to use PM
164 * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
165 * @find_companion must, unfortunately, remain.
166 */
167struct clkops {
168 int (*enable)(struct clk *);
169 void (*disable)(struct clk *);
170 void (*find_idlest)(struct clk *, void __iomem **,
171 u8 *, u8 *);
172 void (*find_companion)(struct clk *, void __iomem **,
173 u8 *);
174 void (*allow_idle)(struct clk *);
175 void (*deny_idle)(struct clk *);
176};
177#endif
178
179/* struct clksel_rate.flags possibilities */ 135/* struct clksel_rate.flags possibilities */
180#define RATE_IN_242X (1 << 0) 136#define RATE_IN_242X (1 << 0)
181#define RATE_IN_243X (1 << 1) 137#define RATE_IN_243X (1 << 1)
@@ -314,7 +270,6 @@ struct dpll_data {
314#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 270#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
315#define CLOCK_CLKOUTX2 (1 << 5) 271#define CLOCK_CLKOUTX2 (1 << 5)
316 272
317#ifdef CONFIG_COMMON_CLK
318/** 273/**
319 * struct clk_hw_omap - OMAP struct clk 274 * struct clk_hw_omap - OMAP struct clk
320 * @node: list_head connecting this clock into the full clock list 275 * @node: list_head connecting this clock into the full clock list
@@ -367,114 +322,6 @@ struct clk_hw_omap_ops {
367 322
368unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, 323unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
369 unsigned long parent_rate); 324 unsigned long parent_rate);
370#else
371/**
372 * struct clk - OMAP struct clk
373 * @node: list_head connecting this clock into the full clock list
374 * @ops: struct clkops * for this clock
375 * @name: the name of the clock in the hardware (used in hwmod data and debug)
376 * @parent: pointer to this clock's parent struct clk
377 * @children: list_head connecting to the child clks' @sibling list_heads
378 * @sibling: list_head connecting this clk to its parent clk's @children
379 * @rate: current clock rate
380 * @enable_reg: register to write to enable the clock (see @enable_bit)
381 * @recalc: fn ptr that returns the clock's current rate
382 * @set_rate: fn ptr that can change the clock's current rate
383 * @round_rate: fn ptr that can round the clock's current rate
384 * @init: fn ptr to do clock-specific initialization
385 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
386 * @usecount: number of users that have requested this clock to be enabled
387 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
388 * @flags: see "struct clk.flags possibilities" above
389 * @clksel_reg: for clksel clks, register va containing src/divisor select
390 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
391 * @clksel: for clksel clks, pointer to struct clksel for this clock
392 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
393 * @clkdm_name: clockdomain name that this clock is contained in
394 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
395 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
396 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
397 *
398 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
399 * clock code converted to use clksel.
400 *
401 * XXX @usecount is poorly named. It should be "enable_count" or
402 * something similar. "users" in the description refers to kernel
403 * code (core code or drivers) that have called clk_enable() and not
404 * yet called clk_disable(); the usecount of parent clocks is also
405 * incremented by the clock code when clk_enable() is called on child
406 * clocks and decremented by the clock code when clk_disable() is
407 * called on child clocks.
408 *
409 * XXX @clkdm, @usecount, @children, @sibling should be marked for
410 * internal use only.
411 *
412 * @children and @sibling are used to optimize parent-to-child clock
413 * tree traversals. (child-to-parent traversals use @parent.)
414 *
415 * XXX The notion of the clock's current rate probably needs to be
416 * separated from the clock's target rate.
417 */
418struct clk {
419 struct list_head node;
420 const struct clkops *ops;
421 const char *name;
422 struct clk *parent;
423 struct list_head children;
424 struct list_head sibling; /* node for children */
425 unsigned long rate;
426 void __iomem *enable_reg;
427 unsigned long (*recalc)(struct clk *);
428 int (*set_rate)(struct clk *, unsigned long);
429 long (*round_rate)(struct clk *, unsigned long);
430 void (*init)(struct clk *);
431 u8 enable_bit;
432 s8 usecount;
433 u8 fixed_div;
434 u8 flags;
435 void __iomem *clksel_reg;
436 u32 clksel_mask;
437 const struct clksel *clksel;
438 struct dpll_data *dpll_data;
439 const char *clkdm_name;
440 struct clockdomain *clkdm;
441#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
442 struct dentry *dent; /* For visible tree hierarchy */
443#endif
444};
445
446struct clk_functions {
447 int (*clk_enable)(struct clk *clk);
448 void (*clk_disable)(struct clk *clk);
449 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
450 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
451 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
452 void (*clk_allow_idle)(struct clk *clk);
453 void (*clk_deny_idle)(struct clk *clk);
454 void (*clk_disable_unused)(struct clk *clk);
455};
456
457extern int mpurate;
458
459extern int clk_init(struct clk_functions *custom_clocks);
460extern void clk_preinit(struct clk *clk);
461extern int clk_register(struct clk *clk);
462extern void clk_reparent(struct clk *child, struct clk *parent);
463extern void clk_unregister(struct clk *clk);
464extern void propagate_rate(struct clk *clk);
465extern void recalculate_root_clocks(void);
466extern unsigned long followparent_recalc(struct clk *clk);
467extern void clk_enable_init_clocks(void);
468unsigned long omap_fixed_divisor_recalc(struct clk *clk);
469extern struct clk *omap_clk_get_by_name(const char *name);
470extern int omap_clk_enable_autoidle_all(void);
471extern int omap_clk_disable_autoidle_all(void);
472
473extern const struct clkops clkops_null;
474
475extern struct clk dummy_ck;
476
477#endif /* CONFIG_COMMON_CLK */
478 325
479/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 326/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
480#define CORE_CLK_SRC_32K 0x0 327#define CORE_CLK_SRC_32K 0x0
@@ -505,15 +352,6 @@ extern struct clk dummy_ck;
505/* DPLL Type and DCO Selection Flags */ 352/* DPLL Type and DCO Selection Flags */
506#define DPLL_J_TYPE 0x1 353#define DPLL_J_TYPE 0x1
507 354
508#ifndef CONFIG_COMMON_CLK
509int omap2_clk_enable(struct clk *clk);
510void omap2_clk_disable(struct clk *clk);
511long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
512int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
513int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
514#endif /* CONFIG_COMMON_CLK */
515
516#ifdef CONFIG_COMMON_CLK
517long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 355long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
518 unsigned long *parent_rate); 356 unsigned long *parent_rate);
519unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); 357unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
@@ -534,37 +372,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
534long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 372long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
535 unsigned long target_rate, 373 unsigned long target_rate,
536 unsigned long *parent_rate); 374 unsigned long *parent_rate);
537#else
538long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
539unsigned long omap3_dpll_recalc(struct clk *clk);
540unsigned long omap3_clkoutx2_recalc(struct clk *clk);
541void omap3_dpll_allow_idle(struct clk *clk);
542void omap3_dpll_deny_idle(struct clk *clk);
543u32 omap3_dpll_autoidle_read(struct clk *clk);
544int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
545int omap3_noncore_dpll_enable(struct clk *clk);
546void omap3_noncore_dpll_disable(struct clk *clk);
547int omap4_dpllmx_gatectrl_read(struct clk *clk);
548void omap4_dpllmx_allow_gatectrl(struct clk *clk);
549void omap4_dpllmx_deny_gatectrl(struct clk *clk);
550long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
551unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
552#endif
553 375
554#ifdef CONFIG_OMAP_RESET_CLOCKS
555void omap2_clk_disable_unused(struct clk *clk);
556#else
557#define omap2_clk_disable_unused NULL
558#endif
559#ifdef CONFIG_COMMON_CLK
560void omap2_init_clk_clkdm(struct clk_hw *clk); 376void omap2_init_clk_clkdm(struct clk_hw *clk);
561#else
562void omap2_init_clk_clkdm(struct clk *clk);
563#endif
564void __init omap2_clk_disable_clkdm_control(void); 377void __init omap2_clk_disable_clkdm_control(void);
565 378
566/* clkt_clksel.c public functions */ 379/* clkt_clksel.c public functions */
567#ifdef CONFIG_COMMON_CLK
568u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, 380u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
569 unsigned long target_rate, 381 unsigned long target_rate,
570 u32 *new_div); 382 u32 *new_div);
@@ -575,29 +387,14 @@ long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
575int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate, 387int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
576 unsigned long parent_rate); 388 unsigned long parent_rate);
577int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); 389int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
578#else
579u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
580 u32 *new_div);
581void omap2_init_clksel_parent(struct clk *clk);
582unsigned long omap2_clksel_recalc(struct clk *clk);
583long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
584int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
585int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
586#endif
587 390
588/* clkt_iclk.c public functions */ 391/* clkt_iclk.c public functions */
589extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 392extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
590extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); 393extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
591 394
592#ifdef CONFIG_COMMON_CLK
593u8 omap2_init_dpll_parent(struct clk_hw *hw); 395u8 omap2_init_dpll_parent(struct clk_hw *hw);
594unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); 396unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
595#else
596u32 omap2_get_dpll_rate(struct clk *clk);
597void omap2_init_dpll_parent(struct clk *clk);
598#endif
599 397
600#ifdef CONFIG_COMMON_CLK
601int omap2_dflt_clk_enable(struct clk_hw *hw); 398int omap2_dflt_clk_enable(struct clk_hw *hw);
602void omap2_dflt_clk_disable(struct clk_hw *hw); 399void omap2_dflt_clk_disable(struct clk_hw *hw);
603int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 400int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
@@ -611,14 +408,6 @@ void omap2_init_clk_hw_omap_clocks(struct clk *clk);
611int omap2_clk_enable_autoidle_all(void); 408int omap2_clk_enable_autoidle_all(void);
612int omap2_clk_disable_autoidle_all(void); 409int omap2_clk_disable_autoidle_all(void);
613void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); 410void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
614#else
615int omap2_dflt_clk_enable(struct clk *clk);
616void omap2_dflt_clk_disable(struct clk *clk);
617void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
618 u8 *other_bit);
619void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
620 u8 *idlest_bit, u8 *idlest_val);
621#endif
622int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); 411int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
623void omap2_clk_print_new_rates(const char *hfclkin_ck_name, 412void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
624 const char *core_ck_name, 413 const char *core_ck_name,
@@ -665,17 +454,9 @@ extern const struct clksel_rate div_1_3_rates[];
665extern const struct clksel_rate div_1_4_rates[]; 454extern const struct clksel_rate div_1_4_rates[];
666extern const struct clksel_rate div31_1to31_rates[]; 455extern const struct clksel_rate div31_1to31_rates[];
667 456
668#ifndef CONFIG_COMMON_CLK
669/* clocks shared between various OMAP SoCs */
670extern struct clk virt_19200000_ck;
671extern struct clk virt_26000000_ck;
672#endif
673
674extern int am33xx_clk_init(void); 457extern int am33xx_clk_init(void);
675 458
676#ifdef CONFIG_COMMON_CLK
677extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 459extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
678extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 460extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
679#endif
680 461
681#endif 462#endif
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index c0d02a97b768..ef4d21bfb964 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -16,6 +16,7 @@
16 * OMAP3xxx clock definition files. 16 * OMAP3xxx clock definition files.
17 */ 17 */
18 18
19#include <linux/clk-private.h>
19#include "clock.h" 20#include "clock.h"
20 21
21/* clksel_rate data common to 24xx/343x */ 22/* clksel_rate data common to 24xx/343x */
@@ -115,9 +116,6 @@ const struct clksel_rate div31_1to31_rates[] = {
115}; 116};
116 117
117/* Clocks shared between various OMAP SoCs */ 118/* Clocks shared between various OMAP SoCs */
118#ifdef CONFIG_COMMON_CLK
119
120#include <linux/clk-private.h>
121 119
122static struct clk_ops dummy_ck_ops = {}; 120static struct clk_ops dummy_ck_ops = {};
123 121
@@ -126,19 +124,3 @@ struct clk dummy_ck = {
126 .ops = &dummy_ck_ops, 124 .ops = &dummy_ck_ops,
127 .flags = CLK_IS_BASIC, 125 .flags = CLK_IS_BASIC,
128}; 126};
129
130#else
131
132struct clk virt_19200000_ck = {
133 .name = "virt_19200000_ck",
134 .ops = &clkops_null,
135 .rate = 19200000,
136};
137
138struct clk virt_26000000_ck = {
139 .name = "virt_26000000_ck",
140 .ops = &clkops_null,
141 .rate = 26000000,
142};
143
144#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index be6fe356ddba..384873580b23 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -997,11 +997,9 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
997 997
998 spin_lock_irqsave(&clkdm->lock, flags); 998 spin_lock_irqsave(&clkdm->lock, flags);
999 999
1000#ifdef CONFIG_COMMON_CLK
1001 /* corner case: disabling unused clocks */ 1000 /* corner case: disabling unused clocks */
1002 if (__clk_get_enable_count(clk) == 0) 1001 if (__clk_get_enable_count(clk) == 0)
1003 goto ccd_exit; 1002 goto ccd_exit;
1004#endif
1005 1003
1006 if (atomic_read(&clkdm->usecount) == 0) { 1004 if (atomic_read(&clkdm->usecount) == 0) {
1007 spin_unlock_irqrestore(&clkdm->lock, flags); 1005 spin_unlock_irqrestore(&clkdm->lock, flags);
@@ -1019,9 +1017,7 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
1019 1017
1020 pr_debug("clockdomain: %s: disabled\n", clkdm->name); 1018 pr_debug("clockdomain: %s: disabled\n", clkdm->name);
1021 1019
1022#ifdef CONFIG_COMMON_CLK
1023ccd_exit: 1020ccd_exit:
1024#endif
1025 spin_unlock_irqrestore(&clkdm->lock, flags); 1021 spin_unlock_irqrestore(&clkdm->lock, flags);
1026 1022
1027 return 0; 1023 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-04 15:46:22 -0400