1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2bc08a28268e..8066ca5e2719 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3810,6 +3810,17 @@ static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
        return rpn;
 }
+static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
+{
+        u32 val, rp1;
+        val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
+        rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
+        return rp1;
+}
 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
        u32 val, rp0;
@@ -3952,6 +3963,11 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
                         vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
                         dev_priv->rps.efficient_freq);
+        dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
+        DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
+                         vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
+                         dev_priv->rps.rp1_freq);
        dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
        DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
                         vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2bc08a28268e..8066ca5e2719 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3810,6 +3810,17 @@ static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3810	return rpn;	3810	return rpn;
3811	}	3811	}
3812		3812
		3813	static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
		3814	{
		3815	u32 val, rp1;
		3816
		3817	val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
		3818
		3819	rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
		3820
		3821	return rp1;
		3822	}
		3823
3813	static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)	3824	static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3814	{	3825	{
3815	u32 val, rp0;	3826	u32 val, rp0;
@@ -3952,6 +3963,11 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
3952	vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),	3963	vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3953	dev_priv->rps.efficient_freq);	3964	dev_priv->rps.efficient_freq);
3954		3965
		3966	dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
		3967	DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
		3968	vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
		3969	dev_priv->rps.rp1_freq);
		3970
3955	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);	3971	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3956	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",	3972	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3957	vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),	3973	vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),