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-rw-r--r--arch/arm/mach-mx25/clock.c14
-rw-r--r--arch/arm/mach-mx25/devices.c22
-rw-r--r--arch/arm/mach-mx25/devices.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h2
4 files changed, 37 insertions, 2 deletions
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 2bb4f1d73cbb..1a58cae4d5e8 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -139,6 +139,11 @@ static unsigned long get_rate_lcdc(struct clk *clk)
139 return get_rate_per(7); 139 return get_rate_per(7);
140} 140}
141 141
142static unsigned long get_rate_csi(struct clk *clk)
143{
144 return get_rate_per(0);
145}
146
142static unsigned long get_rate_otg(struct clk *clk) 147static unsigned long get_rate_otg(struct clk *clk)
143{ 148{
144 unsigned long cctl = readl(CRM_BASE + CCM_CCTL); 149 unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
@@ -211,6 +216,8 @@ DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
211DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); 216DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
212DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); 217DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
213DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); 218DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
219DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
220DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
214DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); 221DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
215DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); 222DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
216DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); 223DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
@@ -232,6 +239,7 @@ DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL);
232DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); 239DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
233DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); 240DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
234DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); 241DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
242DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk);
235 243
236#define _REGISTER_CLOCK(d, n, c) \ 244#define _REGISTER_CLOCK(d, n, c) \
237 { \ 245 { \
@@ -269,6 +277,7 @@ static struct clk_lookup lookups[] = {
269 _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) 277 _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
270 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) 278 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
271 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) 279 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
280 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
272 _REGISTER_CLOCK(NULL, "audmux", audmux_clk) 281 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
273}; 282};
274 283
@@ -284,8 +293,9 @@ int __init mx25_clocks_init(void)
284 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); 293 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
285 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); 294 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
286 295
287 /* Clock source for lcdc is upll */ 296 /* Clock source for lcdc and csi is upll */
288 __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); 297 __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
298 CRM_BASE + 0x64);
289 299
290 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 300 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
291 301
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index baf0a7913644..82d3e53f01f2 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -571,3 +571,25 @@ struct platform_device imx_ssi_device1 = {
571 .num_resources = ARRAY_SIZE(imx_ssi_resources1), 571 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
572 .resource = imx_ssi_resources1, 572 .resource = imx_ssi_resources1,
573}; 573};
574
575static struct resource mx25_csi_resources[] = {
576 {
577 .start = MX25_CSI_BASE_ADDR,
578 .end = MX25_CSI_BASE_ADDR + 0xfff,
579 .flags = IORESOURCE_MEM,
580 },
581 {
582 .start = MX25_INT_CSI,
583 .flags = IORESOURCE_IRQ
584 },
585};
586
587struct platform_device mx25_csi_device = {
588 .name = "mx2-camera",
589 .id = 0,
590 .num_resources = ARRAY_SIZE(mx25_csi_resources),
591 .resource = mx25_csi_resources,
592 .dev = {
593 .coherent_dma_mask = 0xffffffff,
594 },
595};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index 290843bdddf3..00e29f57a596 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -25,3 +25,4 @@ extern struct platform_device mxc_wdt;
25extern struct platform_device mx25_kpp_device; 25extern struct platform_device mx25_kpp_device;
26extern struct platform_device imx_ssi_device0; 26extern struct platform_device imx_ssi_device0;
27extern struct platform_device imx_ssi_device1; 27extern struct platform_device imx_ssi_device1;
28extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index a1ba9d7c55d7..7516f2949afe 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -39,9 +39,11 @@
39#define MX25_LCDC_BASE_ADDR 0x53fbc000 39#define MX25_LCDC_BASE_ADDR 0x53fbc000
40#define MX25_KPP_BASE_ADDR 0x43fa8000 40#define MX25_KPP_BASE_ADDR 0x43fa8000
41#define MX25_OTG_BASE_ADDR 0x53ff4000 41#define MX25_OTG_BASE_ADDR 0x53ff4000
42#define MX25_CSI_BASE_ADDR 0x53ff8000
42 43
43#define MX25_INT_SSI2 11 44#define MX25_INT_SSI2 11
44#define MX25_INT_SSI1 12 45#define MX25_INT_SSI1 12
46#define MX25_INT_CSI 17
45#define MX25_INT_DRYICE 25 47#define MX25_INT_DRYICE 25
46#define MX25_INT_NANDFC 33 48#define MX25_INT_NANDFC 33
47#define MX25_INT_LCDC 39 49#define MX25_INT_LCDC 39