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-rw-r--r--drivers/gpu/drm/i915/i915_dma.c10
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h2
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c11
4 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ac9dac99b585..197db0993a24 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1490,16 +1490,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1490 spin_lock_init(&dev_priv->uncore.lock); 1490 spin_lock_init(&dev_priv->uncore.lock);
1491 spin_lock_init(&dev_priv->mm.object_stat_lock); 1491 spin_lock_init(&dev_priv->mm.object_stat_lock);
1492 mutex_init(&dev_priv->dpio_lock); 1492 mutex_init(&dev_priv->dpio_lock);
1493 mutex_init(&dev_priv->rps.hw_lock);
1494 mutex_init(&dev_priv->modeset_restore_lock); 1493 mutex_init(&dev_priv->modeset_restore_lock);
1495 1494
1496 mutex_init(&dev_priv->pc8.lock); 1495 intel_pm_setup(dev);
1497 dev_priv->pc8.requirements_met = false;
1498 dev_priv->pc8.gpu_idle = false;
1499 dev_priv->pc8.irqs_disabled = false;
1500 dev_priv->pc8.enabled = false;
1501 dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
1502 INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
1503 1496
1504 intel_display_crc_init(dev); 1497 intel_display_crc_init(dev);
1505 1498
@@ -1603,7 +1596,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1603 } 1596 }
1604 1597
1605 intel_irq_init(dev); 1598 intel_irq_init(dev);
1606 intel_pm_init(dev);
1607 intel_uncore_sanitize(dev); 1599 intel_uncore_sanitize(dev);
1608 1600
1609 /* Try to make sure MCHBAR is enabled before poking at it */ 1601 /* Try to make sure MCHBAR is enabled before poking at it */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ccdbecca070d..6f04fa4b31fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1901,9 +1901,7 @@ void i915_queue_hangcheck(struct drm_device *dev);
1901void i915_handle_error(struct drm_device *dev, bool wedged); 1901void i915_handle_error(struct drm_device *dev, bool wedged);
1902 1902
1903extern void intel_irq_init(struct drm_device *dev); 1903extern void intel_irq_init(struct drm_device *dev);
1904extern void intel_pm_init(struct drm_device *dev);
1905extern void intel_hpd_init(struct drm_device *dev); 1904extern void intel_hpd_init(struct drm_device *dev);
1906extern void intel_pm_init(struct drm_device *dev);
1907 1905
1908extern void intel_uncore_sanitize(struct drm_device *dev); 1906extern void intel_uncore_sanitize(struct drm_device *dev);
1909extern void intel_uncore_early_sanitize(struct drm_device *dev); 1907extern void intel_uncore_early_sanitize(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a18e88b3e425..79f91f26e288 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -821,6 +821,7 @@ void intel_update_sprite_watermarks(struct drm_plane *plane,
821 uint32_t sprite_width, int pixel_size, 821 uint32_t sprite_width, int pixel_size,
822 bool enabled, bool scaled); 822 bool enabled, bool scaled);
823void intel_init_pm(struct drm_device *dev); 823void intel_init_pm(struct drm_device *dev);
824void intel_pm_setup(struct drm_device *dev);
824bool intel_fbc_enabled(struct drm_device *dev); 825bool intel_fbc_enabled(struct drm_device *dev);
825void intel_update_fbc(struct drm_device *dev); 826void intel_update_fbc(struct drm_device *dev);
826void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 827void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e0d5e075b15..e0dec95c764e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6130,10 +6130,19 @@ int vlv_freq_opcode(int ddr_freq, int val)
6130 return val; 6130 return val;
6131} 6131}
6132 6132
6133void intel_pm_init(struct drm_device *dev) 6133void intel_pm_setup(struct drm_device *dev)
6134{ 6134{
6135 struct drm_i915_private *dev_priv = dev->dev_private; 6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136 6136
6137 mutex_init(&dev_priv->rps.hw_lock);
6138
6139 mutex_init(&dev_priv->pc8.lock);
6140 dev_priv->pc8.requirements_met = false;
6141 dev_priv->pc8.gpu_idle = false;
6142 dev_priv->pc8.irqs_disabled = false;
6143 dev_priv->pc8.enabled = false;
6144 dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
6145 INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
6137 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 6146 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6138 intel_gen6_powersave_work); 6147 intel_gen6_powersave_work);
6139} 6148}