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-rw-r--r--arch/arm/mach-tegra/sleep.S8
-rw-r--r--arch/arm/mach-tegra/sleep.h24
2 files changed, 23 insertions, 9 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 364d84523fba..9daaef26b0f6 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu)
106 isb 106 isb
107#ifdef CONFIG_CACHE_L2X0 107#ifdef CONFIG_CACHE_L2X0
108 /* Disable L2 cache */ 108 /* Disable L2 cache */
109 mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000 109 check_cpu_part_num 0xc09, r9, r10
110 mov r5, #0 110 movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
111 str r5, [r4, #L2X0_CTRL] 111 movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
112 moveq r5, #0
113 streq r5, [r4, #L2X0_CTRL]
112#endif 114#endif
113 mov pc, r0 115 mov pc, r0
114ENDPROC(tegra_shut_off_mmu) 116ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index f9f2164a2fc7..2269c0d6fa67 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -70,19 +70,31 @@
70 movt \reg, #:upper16:\val 70 movt \reg, #:upper16:\val
71.endm 71.endm
72 72
73/* Marco to check CPU part num */
74.macro check_cpu_part_num part_num, tmp1, tmp2
75 mrc p15, 0, \tmp1, c0, c0, 0
76 ubfx \tmp1, \tmp1, #4, #12
77 mov32 \tmp2, \part_num
78 cmp \tmp1, \tmp2
79.endm
80
73/* Macro to exit SMP coherency. */ 81/* Macro to exit SMP coherency. */
74.macro exit_smp, tmp1, tmp2 82.macro exit_smp, tmp1, tmp2
75 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR 83 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
76 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW 84 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
77 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR 85 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
78 isb 86 isb
79 cpu_id \tmp1 87#ifdef CONFIG_HAVE_ARM_SCU
80 mov \tmp1, \tmp1, lsl #2 88 check_cpu_part_num 0xc09, \tmp1, \tmp2
81 mov \tmp2, #0xf 89 mrceq p15, 0, \tmp1, c0, c0, 5
82 mov \tmp2, \tmp2, lsl \tmp1 90 andeq \tmp1, \tmp1, #0xF
83 mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC 91 moveq \tmp1, \tmp1, lsl #2
84 str \tmp2, [\tmp1] @ invalidate SCU tags for CPU 92 moveq \tmp2, #0xf
93 moveq \tmp2, \tmp2, lsl \tmp1
94 ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
95 streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
85 dsb 96 dsb
97#endif
86.endm 98.endm
87 99
88/* Macro to check Tegra revision */ 100/* Macro to check Tegra revision */