1 files changed, 21 insertions, 0 deletions

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 1c5e6442dcfb..6a81bc9e54f0 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -652,12 +652,33 @@ CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
 
 static void __init rk3188a_clk_init(struct device_node *np)
 {
+        struct clk *clk1, *clk2;
+        unsigned long rate;
+        int ret;
+
         rk3188_common_clk_init(np);
         rockchip_clk_register_plls(rk3188_pll_clks,
                                    ARRAY_SIZE(rk3188_pll_clks),
                                    RK3188_GRF_SOC_STATUS);
         rockchip_clk_register_branches(rk3188_clk_branches,
                                   ARRAY_SIZE(rk3188_clk_branches));
+
+        /* reparent aclk_cpu_pre from apll */
+        clk1 = __clk_lookup("aclk_cpu_pre");
+        clk2 = __clk_lookup("gpll");
+        if (clk1 && clk2) {
+                rate = clk_get_rate(clk1);
+
+                ret = clk_set_parent(clk1, clk2);
+                if (ret < 0)
+                        pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
+                                __func__);
+
+                clk_set_rate(clk1, rate);
+        } else {
+                pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
+                        __func__);
+        }
 }
 CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);