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-rw-r--r--arch/mips/au1000/Kconfig1
-rw-r--r--arch/mips/au1000/common/irq.c251
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h10
3 files changed, 139 insertions, 123 deletions
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig
index 29c95d97217d..a23d4154da01 100644
--- a/arch/mips/au1000/Kconfig
+++ b/arch/mips/au1000/Kconfig
@@ -137,6 +137,7 @@ config SOC_AU1200
137config SOC_AU1X00 137config SOC_AU1X00
138 bool 138 bool
139 select 64BIT_PHYS_ADDR 139 select 64BIT_PHYS_ADDR
140 select IRQ_CPU
140 select SYS_HAS_CPU_MIPS32_R1 141 select SYS_HAS_CPU_MIPS32_R1
141 select SYS_SUPPORTS_32BIT_KERNEL 142 select SYS_SUPPORTS_32BIT_KERNEL
142 select SYS_SUPPORTS_APM_EMULATION 143 select SYS_SUPPORTS_APM_EMULATION
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index c00f308fd505..59e932a928d2 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -1,11 +1,10 @@
1/* 1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1000 interrupt routines.
4 *
5 * Copyright 2001 MontaVista Software Inc. 2 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. 3 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com 4 * ppopov@mvista.com or source@mvista.com
8 * 5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 *
9 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your 10 * Free Software Foundation; either version 2 of the License, or (at your
@@ -32,6 +31,7 @@
32#include <linux/interrupt.h> 31#include <linux/interrupt.h>
33#include <linux/irq.h> 32#include <linux/irq.h>
34 33
34#include <asm/irq_cpu.h>
35#include <asm/mipsregs.h> 35#include <asm/mipsregs.h>
36#include <asm/mach-au1x00/au1000.h> 36#include <asm/mach-au1x00/au1000.h>
37#ifdef CONFIG_MIPS_PB1000 37#ifdef CONFIG_MIPS_PB1000
@@ -44,7 +44,7 @@
44#define EXT_INTC1_REQ1 5 /* IP 5 */ 44#define EXT_INTC1_REQ1 5 /* IP 5 */
45#define MIPS_TIMER_IP 7 /* IP 7 */ 45#define MIPS_TIMER_IP 7 /* IP 7 */
46 46
47void (*board_init_irq)(void); 47void (*board_init_irq)(void) __initdata = NULL;
48 48
49static DEFINE_SPINLOCK(irq_lock); 49static DEFINE_SPINLOCK(irq_lock);
50 50
@@ -134,12 +134,14 @@ void restore_au1xxx_intctl(void)
134 134
135inline void local_enable_irq(unsigned int irq_nr) 135inline void local_enable_irq(unsigned int irq_nr)
136{ 136{
137 if (irq_nr > AU1000_LAST_INTC0_INT) { 137 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
138 au_writel(1 << (irq_nr - 32), IC1_MASKSET); 138
139 au_writel(1 << (irq_nr - 32), IC1_WAKESET); 139 if (bit >= 32) {
140 au_writel(1 << (bit - 32), IC1_MASKSET);
141 au_writel(1 << (bit - 32), IC1_WAKESET);
140 } else { 142 } else {
141 au_writel(1 << irq_nr, IC0_MASKSET); 143 au_writel(1 << bit, IC0_MASKSET);
142 au_writel(1 << irq_nr, IC0_WAKESET); 144 au_writel(1 << bit, IC0_WAKESET);
143 } 145 }
144 au_sync(); 146 au_sync();
145} 147}
@@ -147,12 +149,14 @@ inline void local_enable_irq(unsigned int irq_nr)
147 149
148inline void local_disable_irq(unsigned int irq_nr) 150inline void local_disable_irq(unsigned int irq_nr)
149{ 151{
150 if (irq_nr > AU1000_LAST_INTC0_INT) { 152 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
151 au_writel(1 << (irq_nr - 32), IC1_MASKCLR); 153
152 au_writel(1 << (irq_nr - 32), IC1_WAKECLR); 154 if (bit >= 32) {
155 au_writel(1 << (bit - 32), IC1_MASKCLR);
156 au_writel(1 << (bit - 32), IC1_WAKECLR);
153 } else { 157 } else {
154 au_writel(1 << irq_nr, IC0_MASKCLR); 158 au_writel(1 << bit, IC0_MASKCLR);
155 au_writel(1 << irq_nr, IC0_WAKECLR); 159 au_writel(1 << bit, IC0_WAKECLR);
156 } 160 }
157 au_sync(); 161 au_sync();
158} 162}
@@ -160,12 +164,14 @@ inline void local_disable_irq(unsigned int irq_nr)
160 164
161static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) 165static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
162{ 166{
163 if (irq_nr > AU1000_LAST_INTC0_INT) { 167 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
164 au_writel(1 << (irq_nr - 32), IC1_RISINGCLR); 168
165 au_writel(1 << (irq_nr - 32), IC1_MASKCLR); 169 if (bit >= 32) {
170 au_writel(1 << (bit - 32), IC1_RISINGCLR);
171 au_writel(1 << (bit - 32), IC1_MASKCLR);
166 } else { 172 } else {
167 au_writel(1 << irq_nr, IC0_RISINGCLR); 173 au_writel(1 << bit, IC0_RISINGCLR);
168 au_writel(1 << irq_nr, IC0_MASKCLR); 174 au_writel(1 << bit, IC0_MASKCLR);
169 } 175 }
170 au_sync(); 176 au_sync();
171} 177}
@@ -173,12 +179,14 @@ static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
173 179
174static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) 180static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
175{ 181{
176 if (irq_nr > AU1000_LAST_INTC0_INT) { 182 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
177 au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR); 183
178 au_writel(1 << (irq_nr - 32), IC1_MASKCLR); 184 if (bit >= 32) {
185 au_writel(1 << (bit - 32), IC1_FALLINGCLR);
186 au_writel(1 << (bit - 32), IC1_MASKCLR);
179 } else { 187 } else {
180 au_writel(1 << irq_nr, IC0_FALLINGCLR); 188 au_writel(1 << bit, IC0_FALLINGCLR);
181 au_writel(1 << irq_nr, IC0_MASKCLR); 189 au_writel(1 << bit, IC0_MASKCLR);
182 } 190 }
183 au_sync(); 191 au_sync();
184} 192}
@@ -186,17 +194,20 @@ static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
186 194
187static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) 195static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
188{ 196{
189 /* This may assume that we don't get interrupts from 197 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
198
199 /*
200 * This may assume that we don't get interrupts from
190 * both edges at once, or if we do, that we don't care. 201 * both edges at once, or if we do, that we don't care.
191 */ 202 */
192 if (irq_nr > AU1000_LAST_INTC0_INT) { 203 if (bit >= 32) {
193 au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR); 204 au_writel(1 << (bit - 32), IC1_FALLINGCLR);
194 au_writel(1 << (irq_nr - 32), IC1_RISINGCLR); 205 au_writel(1 << (bit - 32), IC1_RISINGCLR);
195 au_writel(1 << (irq_nr - 32), IC1_MASKCLR); 206 au_writel(1 << (bit - 32), IC1_MASKCLR);
196 } else { 207 } else {
197 au_writel(1 << irq_nr, IC0_FALLINGCLR); 208 au_writel(1 << bit, IC0_FALLINGCLR);
198 au_writel(1 << irq_nr, IC0_RISINGCLR); 209 au_writel(1 << bit, IC0_RISINGCLR);
199 au_writel(1 << irq_nr, IC0_MASKCLR); 210 au_writel(1 << bit, IC0_MASKCLR);
200 } 211 }
201 au_sync(); 212 au_sync();
202} 213}
@@ -213,10 +224,8 @@ static inline void mask_and_ack_level_irq(unsigned int irq_nr)
213 au_sync(); 224 au_sync();
214 } 225 }
215#endif 226#endif
216 return;
217} 227}
218 228
219
220static void end_irq(unsigned int irq_nr) 229static void end_irq(unsigned int irq_nr)
221{ 230{
222 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 231 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -341,114 +350,118 @@ void startup_match20_interrupt(irq_handler_t handler)
341} 350}
342#endif 351#endif
343 352
344static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 353static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req)
345{ 354{
346 if (irq_nr > AU1000_MAX_INTR) return; 355 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
356
357 if (irq_nr > AU1000_MAX_INTR)
358 return;
359
347 /* Config2[n], Config1[n], Config0[n] */ 360 /* Config2[n], Config1[n], Config0[n] */
348 if (irq_nr > AU1000_LAST_INTC0_INT) { 361 if (bit >= 32) {
349 switch (type) { 362 switch (type) {
350 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 363 case INTC_INT_RISE_EDGE: /* 0:0:1 */
351 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR); 364 au_writel(1 << (bit - 32), IC1_CFG2CLR);
352 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR); 365 au_writel(1 << (bit - 32), IC1_CFG1CLR);
353 au_writel(1 << (irq_nr - 32), IC1_CFG0SET); 366 au_writel(1 << (bit - 32), IC1_CFG0SET);
354 set_irq_chip(irq_nr, &rise_edge_irq_type); 367 set_irq_chip(irq_nr, &rise_edge_irq_type);
355 break; 368 break;
356 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 369 case INTC_INT_FALL_EDGE: /* 0:1:0 */
357 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR); 370 au_writel(1 << (bit - 32), IC1_CFG2CLR);
358 au_writel(1 << (irq_nr - 32), IC1_CFG1SET); 371 au_writel(1 << (bit - 32), IC1_CFG1SET);
359 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR); 372 au_writel(1 << (bit - 32), IC1_CFG0CLR);
360 set_irq_chip(irq_nr, &fall_edge_irq_type); 373 set_irq_chip(irq_nr, &fall_edge_irq_type);
361 break; 374 break;
362 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 375 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
363 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR); 376 au_writel(1 << (bit - 32), IC1_CFG2CLR);
364 au_writel(1 << (irq_nr - 32), IC1_CFG1SET); 377 au_writel(1 << (bit - 32), IC1_CFG1SET);
365 au_writel(1 << (irq_nr - 32), IC1_CFG0SET); 378 au_writel(1 << (bit - 32), IC1_CFG0SET);
366 set_irq_chip(irq_nr, &either_edge_irq_type); 379 set_irq_chip(irq_nr, &either_edge_irq_type);
367 break; 380 break;
368 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 381 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
369 au_writel(1 << (irq_nr - 32), IC1_CFG2SET); 382 au_writel(1 << (bit - 32), IC1_CFG2SET);
370 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR); 383 au_writel(1 << (bit - 32), IC1_CFG1CLR);
371 au_writel(1 << (irq_nr - 32), IC1_CFG0SET); 384 au_writel(1 << (bit - 32), IC1_CFG0SET);
372 set_irq_chip(irq_nr, &level_irq_type); 385 set_irq_chip(irq_nr, &level_irq_type);
373 break; 386 break;
374 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 387 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
375 au_writel(1 << (irq_nr - 32), IC1_CFG2SET); 388 au_writel(1 << (bit - 32), IC1_CFG2SET);
376 au_writel(1 << (irq_nr - 32), IC1_CFG1SET); 389 au_writel(1 << (bit - 32), IC1_CFG1SET);
377 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR); 390 au_writel(1 << (bit - 32), IC1_CFG0CLR);
378 set_irq_chip(irq_nr, &level_irq_type); 391 set_irq_chip(irq_nr, &level_irq_type);
379 break; 392 break;
380 case INTC_INT_DISABLED: /* 0:0:0 */ 393 case INTC_INT_DISABLED: /* 0:0:0 */
381 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR); 394 au_writel(1 << (bit - 32), IC1_CFG0CLR);
382 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR); 395 au_writel(1 << (bit - 32), IC1_CFG1CLR);
383 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR); 396 au_writel(1 << (bit - 32), IC1_CFG2CLR);
384 break; 397 break;
385 default: /* disable the interrupt */ 398 default: /* disable the interrupt */
386 printk(KERN_WARNING "unexpected int type %d (irq %d)\n", 399 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
387 type, irq_nr); 400 type, irq_nr);
388 au_writel(1 << (irq_nr - 32), IC1_CFG0CLR); 401 au_writel(1 << (bit - 32), IC1_CFG0CLR);
389 au_writel(1 << (irq_nr - 32), IC1_CFG1CLR); 402 au_writel(1 << (bit - 32), IC1_CFG1CLR);
390 au_writel(1 << (irq_nr - 32), IC1_CFG2CLR); 403 au_writel(1 << (bit - 32), IC1_CFG2CLR);
391 return; 404 return;
392 } 405 }
393 if (int_req) /* assign to interrupt request 1 */ 406 if (int_req) /* assign to interrupt request 1 */
394 au_writel(1 << (irq_nr - 32), IC1_ASSIGNCLR); 407 au_writel(1 << (bit - 32), IC1_ASSIGNCLR);
395 else /* assign to interrupt request 0 */ 408 else /* assign to interrupt request 0 */
396 au_writel(1 << (irq_nr - 32), IC1_ASSIGNSET); 409 au_writel(1 << (bit - 32), IC1_ASSIGNSET);
397 au_writel(1 << (irq_nr - 32), IC1_SRCSET); 410 au_writel(1 << (bit - 32), IC1_SRCSET);
398 au_writel(1 << (irq_nr - 32), IC1_MASKCLR); 411 au_writel(1 << (bit - 32), IC1_MASKCLR);
399 au_writel(1 << (irq_nr - 32), IC1_WAKECLR); 412 au_writel(1 << (bit - 32), IC1_WAKECLR);
400 } else { 413 } else {
401 switch (type) { 414 switch (type) {
402 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 415 case INTC_INT_RISE_EDGE: /* 0:0:1 */
403 au_writel(1 << irq_nr, IC0_CFG2CLR); 416 au_writel(1 << bit, IC0_CFG2CLR);
404 au_writel(1 << irq_nr, IC0_CFG1CLR); 417 au_writel(1 << bit, IC0_CFG1CLR);
405 au_writel(1 << irq_nr, IC0_CFG0SET); 418 au_writel(1 << bit, IC0_CFG0SET);
406 set_irq_chip(irq_nr, &rise_edge_irq_type); 419 set_irq_chip(irq_nr, &rise_edge_irq_type);
407 break; 420 break;
408 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 421 case INTC_INT_FALL_EDGE: /* 0:1:0 */
409 au_writel(1 << irq_nr, IC0_CFG2CLR); 422 au_writel(1 << bit, IC0_CFG2CLR);
410 au_writel(1 << irq_nr, IC0_CFG1SET); 423 au_writel(1 << bit, IC0_CFG1SET);
411 au_writel(1 << irq_nr, IC0_CFG0CLR); 424 au_writel(1 << bit, IC0_CFG0CLR);
412 set_irq_chip(irq_nr, &fall_edge_irq_type); 425 set_irq_chip(irq_nr, &fall_edge_irq_type);
413 break; 426 break;
414 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 427 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
415 au_writel(1 << irq_nr, IC0_CFG2CLR); 428 au_writel(1 << bit, IC0_CFG2CLR);
416 au_writel(1 << irq_nr, IC0_CFG1SET); 429 au_writel(1 << bit, IC0_CFG1SET);
417 au_writel(1 << irq_nr, IC0_CFG0SET); 430 au_writel(1 << bit, IC0_CFG0SET);
418 set_irq_chip(irq_nr, &either_edge_irq_type); 431 set_irq_chip(irq_nr, &either_edge_irq_type);
419 break; 432 break;
420 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 433 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
421 au_writel(1 << irq_nr, IC0_CFG2SET); 434 au_writel(1 << bit, IC0_CFG2SET);
422 au_writel(1 << irq_nr, IC0_CFG1CLR); 435 au_writel(1 << bit, IC0_CFG1CLR);
423 au_writel(1 << irq_nr, IC0_CFG0SET); 436 au_writel(1 << bit, IC0_CFG0SET);
424 set_irq_chip(irq_nr, &level_irq_type); 437 set_irq_chip(irq_nr, &level_irq_type);
425 break; 438 break;
426 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 439 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
427 au_writel(1 << irq_nr, IC0_CFG2SET); 440 au_writel(1 << bit, IC0_CFG2SET);
428 au_writel(1 << irq_nr, IC0_CFG1SET); 441 au_writel(1 << bit, IC0_CFG1SET);
429 au_writel(1 << irq_nr, IC0_CFG0CLR); 442 au_writel(1 << bit, IC0_CFG0CLR);
430 set_irq_chip(irq_nr, &level_irq_type); 443 set_irq_chip(irq_nr, &level_irq_type);
431 break; 444 break;
432 case INTC_INT_DISABLED: /* 0:0:0 */ 445 case INTC_INT_DISABLED: /* 0:0:0 */
433 au_writel(1 << irq_nr, IC0_CFG0CLR); 446 au_writel(1 << bit, IC0_CFG0CLR);
434 au_writel(1 << irq_nr, IC0_CFG1CLR); 447 au_writel(1 << bit, IC0_CFG1CLR);
435 au_writel(1 << irq_nr, IC0_CFG2CLR); 448 au_writel(1 << bit, IC0_CFG2CLR);
436 break; 449 break;
437 default: /* disable the interrupt */ 450 default: /* disable the interrupt */
438 printk(KERN_WARNING "unexpected int type %d (irq %d)\n", 451 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
439 type, irq_nr); 452 type, irq_nr);
440 au_writel(1 << irq_nr, IC0_CFG0CLR); 453 au_writel(1 << bit, IC0_CFG0CLR);
441 au_writel(1 << irq_nr, IC0_CFG1CLR); 454 au_writel(1 << bit, IC0_CFG1CLR);
442 au_writel(1 << irq_nr, IC0_CFG2CLR); 455 au_writel(1 << bit, IC0_CFG2CLR);
443 return; 456 return;
444 } 457 }
445 if (int_req) /* assign to interrupt request 1 */ 458 if (int_req) /* assign to interrupt request 1 */
446 au_writel(1 << irq_nr, IC0_ASSIGNCLR); 459 au_writel(1 << bit, IC0_ASSIGNCLR);
447 else /* assign to interrupt request 0 */ 460 else /* assign to interrupt request 0 */
448 au_writel(1 << irq_nr, IC0_ASSIGNSET); 461 au_writel(1 << bit, IC0_ASSIGNSET);
449 au_writel(1 << irq_nr, IC0_SRCSET); 462 au_writel(1 << bit, IC0_SRCSET);
450 au_writel(1 << irq_nr, IC0_MASKCLR); 463 au_writel(1 << bit, IC0_MASKCLR);
451 au_writel(1 << irq_nr, IC0_WAKECLR); 464 au_writel(1 << bit, IC0_WAKECLR);
452 } 465 }
453 au_sync(); 466 au_sync();
454} 467}
@@ -461,8 +474,8 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
461 474
462static void intc0_req0_irqdispatch(void) 475static void intc0_req0_irqdispatch(void)
463{ 476{
464 int irq = 0;
465 static unsigned long intc0_req0; 477 static unsigned long intc0_req0;
478 unsigned int bit;
466 479
467 intc0_req0 |= au_readl(IC0_REQ0INT); 480 intc0_req0 |= au_readl(IC0_REQ0INT);
468 481
@@ -481,25 +494,25 @@ static void intc0_req0_irqdispatch(void)
481 return; 494 return;
482 } 495 }
483#endif 496#endif
484 irq = ffs(intc0_req0); 497 bit = ffs(intc0_req0);
485 intc0_req0 &= ~(1 << irq); 498 intc0_req0 &= ~(1 << bit);
486 do_IRQ(irq); 499 do_IRQ(MIPS_CPU_IRQ_BASE + bit);
487} 500}
488 501
489 502
490static void intc0_req1_irqdispatch(void) 503static void intc0_req1_irqdispatch(void)
491{ 504{
492 int irq = 0;
493 static unsigned long intc0_req1; 505 static unsigned long intc0_req1;
506 unsigned int bit;
494 507
495 intc0_req1 |= au_readl(IC0_REQ1INT); 508 intc0_req1 |= au_readl(IC0_REQ1INT);
496 509
497 if (!intc0_req1) 510 if (!intc0_req1)
498 return; 511 return;
499 512
500 irq = ffs(intc0_req1); 513 bit = ffs(intc0_req1);
501 intc0_req1 &= ~(1 << irq); 514 intc0_req1 &= ~(1 << bit);
502 do_IRQ(irq); 515 do_IRQ(bit);
503} 516}
504 517
505 518
@@ -509,43 +522,41 @@ static void intc0_req1_irqdispatch(void)
509 */ 522 */
510static void intc1_req0_irqdispatch(void) 523static void intc1_req0_irqdispatch(void)
511{ 524{
512 int irq = 0;
513 static unsigned long intc1_req0; 525 static unsigned long intc1_req0;
526 unsigned int bit;
514 527
515 intc1_req0 |= au_readl(IC1_REQ0INT); 528 intc1_req0 |= au_readl(IC1_REQ0INT);
516 529
517 if (!intc1_req0) 530 if (!intc1_req0)
518 return; 531 return;
519 532
520 irq = ffs(intc1_req0); 533 bit = ffs(intc1_req0);
521 intc1_req0 &= ~(1 << irq); 534 intc1_req0 &= ~(1 << bit);
522 irq += 32; 535 do_IRQ(MIPS_CPU_IRQ_BASE + 32 + bit);
523 do_IRQ(irq);
524} 536}
525 537
526 538
527static void intc1_req1_irqdispatch(void) 539static void intc1_req1_irqdispatch(void)
528{ 540{
529 int irq = 0;
530 static unsigned long intc1_req1; 541 static unsigned long intc1_req1;
542 unsigned int bit;
531 543
532 intc1_req1 |= au_readl(IC1_REQ1INT); 544 intc1_req1 |= au_readl(IC1_REQ1INT);
533 545
534 if (!intc1_req1) 546 if (!intc1_req1)
535 return; 547 return;
536 548
537 irq = ffs(intc1_req1); 549 bit = ffs(intc1_req1);
538 intc1_req1 &= ~(1 << irq); 550 intc1_req1 &= ~(1 << bit);
539 irq += 32; 551 do_IRQ(MIPS_CPU_IRQ_BASE + 32 + bit);
540 do_IRQ(irq);
541} 552}
542 553
543asmlinkage void plat_irq_dispatch(void) 554asmlinkage void plat_irq_dispatch(void)
544{ 555{
545 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 556 unsigned int pending = read_c0_status() & read_c0_cause();
546 557
547 if (pending & CAUSEF_IP7) 558 if (pending & CAUSEF_IP7)
548 do_IRQ(63); 559 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
549 else if (pending & CAUSEF_IP2) 560 else if (pending & CAUSEF_IP2)
550 intc0_req0_irqdispatch(); 561 intc0_req0_irqdispatch();
551 else if (pending & CAUSEF_IP3) 562 else if (pending & CAUSEF_IP3)
@@ -561,17 +572,15 @@ asmlinkage void plat_irq_dispatch(void)
561void __init arch_init_irq(void) 572void __init arch_init_irq(void)
562{ 573{
563 int i; 574 int i;
564 unsigned long cp0_status;
565 struct au1xxx_irqmap *imp; 575 struct au1xxx_irqmap *imp;
566 extern struct au1xxx_irqmap au1xxx_irq_map[]; 576 extern struct au1xxx_irqmap au1xxx_irq_map[];
567 extern struct au1xxx_irqmap au1xxx_ic0_map[]; 577 extern struct au1xxx_irqmap au1xxx_ic0_map[];
568 extern int au1xxx_nr_irqs; 578 extern int au1xxx_nr_irqs;
569 extern int au1xxx_ic0_nr_irqs; 579 extern int au1xxx_ic0_nr_irqs;
570 580
571 cp0_status = read_c0_status(); 581 /*
572 582 * Initialize interrupt controllers to a safe state.
573 /* Initialize interrupt controllers to a safe state. 583 */
574 */
575 au_writel(0xffffffff, IC0_CFG0CLR); 584 au_writel(0xffffffff, IC0_CFG0CLR);
576 au_writel(0xffffffff, IC0_CFG1CLR); 585 au_writel(0xffffffff, IC0_CFG1CLR);
577 au_writel(0xffffffff, IC0_CFG2CLR); 586 au_writel(0xffffffff, IC0_CFG2CLR);
@@ -594,16 +603,20 @@ void __init arch_init_irq(void)
594 au_writel(0xffffffff, IC1_RISINGCLR); 603 au_writel(0xffffffff, IC1_RISINGCLR);
595 au_writel(0x00000000, IC1_TESTBIT); 604 au_writel(0x00000000, IC1_TESTBIT);
596 605
597 /* Initialize IC0, which is fixed per processor. 606 mips_cpu_irq_init();
598 */ 607
608 /*
609 * Initialize IC0, which is fixed per processor.
610 */
599 imp = au1xxx_ic0_map; 611 imp = au1xxx_ic0_map;
600 for (i = 0; i < au1xxx_ic0_nr_irqs; i++) { 612 for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
601 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); 613 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
602 imp++; 614 imp++;
603 } 615 }
604 616
605 /* Now set up the irq mapping for the board. 617 /*
606 */ 618 * Now set up the irq mapping for the board.
619 */
607 imp = au1xxx_irq_map; 620 imp = au1xxx_irq_map;
608 for (i = 0; i < au1xxx_nr_irqs; i++) { 621 for (i = 0; i < au1xxx_nr_irqs; i++) {
609 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); 622 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
@@ -615,5 +628,5 @@ void __init arch_init_irq(void)
615 /* Board specific IRQ initialization. 628 /* Board specific IRQ initialization.
616 */ 629 */
617 if (board_init_irq) 630 if (board_init_irq)
618 (*board_init_irq)(); 631 board_init_irq();
619} 632}
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index b37baf8cf624..a2a5168a443b 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -926,10 +926,12 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
926 926
927#endif /* CONFIG_SOC_AU1200 */ 927#endif /* CONFIG_SOC_AU1200 */
928 928
929#define AU1000_LAST_INTC0_INT 31 929#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 0)
930#define AU1000_LAST_INTC1_INT 63 930#define AU1000_INTC0_INT_LAST (MIPS_CPU_IRQ_BASE + 31)
931#define AU1000_MAX_INTR 63 931#define AU1000_INTC1_INT_BASE (MIPS_CPU_IRQ_BASE + 32)
932#define INTX 0xFF /* not valid */ 932#define AU1000_INTC1_INT_LAST (MIPS_CPU_IRQ_BASE + 63)
933#define AU1000_MAX_INTR (MIPS_CPU_IRQ_BASE + 63)
934#define INTX 0xFF /* not valid */
933 935
934/* Programmable Counters 0 and 1 */ 936/* Programmable Counters 0 and 1 */
935#define SYS_BASE 0xB1900000 937#define SYS_BASE 0xB1900000
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-29 11:26:51 -0500