2 files changed, 8 insertions, 6 deletions

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index 14a778433522..82f2e963782b 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -10034,8 +10034,12 @@ static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
         id = ((val & 0xffff) << 16);
         val = REG_RD(bp, MISC_REG_CHIP_REV);
         id |= ((val & 0xf) << 12);
-        val = REG_RD(bp, MISC_REG_CHIP_METAL);
-        id |= ((val & 0xff) << 4);
+
+        /* Metal is read from PCI regs, but we can't access >=0x400 from
+         * the configuration space (so we need to reg_rd)
+         */
+        val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
+        id |= (((val >> 24) & 0xf) << 4);
         val = REG_RD(bp, MISC_REG_BOND_ID);
         id |= (val & 0xf);
         bp->common.chip_id = id;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
index 791eb2d53011..d22bc40091ec 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
@@ -1491,10 +1491,6 @@
 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
    Port. */
 #define MISC_REG_BOND_ID                                         0xa400
-/* [R 8] These bits indicate the metal revision of the chip. This value
-   starts at 0x00 for each all-layer tape-out and increments by one for each
-   tape-out. */
-#define MISC_REG_CHIP_METAL                                      0xa404
 /* [R 16] These bits indicate the part number for the chip. */
 #define MISC_REG_CHIP_NUM                                        0xa408
 /* [R 4] These bits indicate the base revision of the chip. This value
@@ -6331,6 +6327,8 @@
 #define PCI_PM_DATA_B                                   0x414
 #define PCI_ID_VAL1                                     0x434
 #define PCI_ID_VAL2                                     0x438
+#define PCI_ID_VAL3                                     0x43c
+
 #define GRC_CONFIG_REG_PF_INIT_VF               0x624
 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK  0xf
 /* First VF_NUM for PF is encoded in this register.