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-rw-r--r--drivers/net/wireless/ath9k/Makefile4
-rw-r--r--drivers/net/wireless/ath9k/ani.c854
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h376
-rw-r--r--drivers/net/wireless/ath9k/calib.c930
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c1605
-rw-r--r--drivers/net/wireless/ath9k/hw.c8492
-rw-r--r--drivers/net/wireless/ath9k/hw.h2
-rw-r--r--drivers/net/wireless/ath9k/mac.c1031
-rw-r--r--drivers/net/wireless/ath9k/phy.c10
9 files changed, 6603 insertions, 6701 deletions
diff --git a/drivers/net/wireless/ath9k/Makefile b/drivers/net/wireless/ath9k/Makefile
index a6411517e5f8..c58cfdeb49c9 100644
--- a/drivers/net/wireless/ath9k/Makefile
+++ b/drivers/net/wireless/ath9k/Makefile
@@ -1,4 +1,8 @@
1ath9k-y += hw.o \ 1ath9k-y += hw.o \
2 eeprom.o \
3 mac.o \
4 calib.o \
5 ani.o \
2 phy.o \ 6 phy.o \
3 regd.o \ 7 regd.o \
4 beacon.o \ 8 beacon.o \
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c
new file mode 100644
index 000000000000..ada12e9aa7f9
--- /dev/null
+++ b/drivers/net/wireless/ath9k/ani.c
@@ -0,0 +1,854 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "core.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21
22static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
23 struct ath9k_channel *chan)
24{
25 struct ath_hal_5416 *ahp = AH5416(ah);
26 int i;
27
28 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
29 if (ahp->ah_ani[i].c.channel == chan->channel)
30 return i;
31 if (ahp->ah_ani[i].c.channel == 0) {
32 ahp->ah_ani[i].c.channel = chan->channel;
33 ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
34 return i;
35 }
36 }
37
38 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
39 "No more channel states left. Using channel 0\n");
40
41 return 0;
42}
43
44static bool ath9k_hw_ani_control(struct ath_hal *ah,
45 enum ath9k_ani_cmd cmd, int param)
46{
47 struct ath_hal_5416 *ahp = AH5416(ah);
48 struct ar5416AniState *aniState = ahp->ah_curani;
49
50 switch (cmd & ahp->ah_ani_function) {
51 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
52 u32 level = param;
53
54 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
55 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
56 "%s: level out of range (%u > %u)\n",
57 __func__, level,
58 (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired));
59 return false;
60 }
61
62 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
63 AR_PHY_DESIRED_SZ_TOT_DES,
64 ahp->ah_totalSizeDesired[level]);
65 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
66 AR_PHY_AGC_CTL1_COARSE_LOW,
67 ahp->ah_coarseLow[level]);
68 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
69 AR_PHY_AGC_CTL1_COARSE_HIGH,
70 ahp->ah_coarseHigh[level]);
71 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
72 AR_PHY_FIND_SIG_FIRPWR,
73 ahp->ah_firpwr[level]);
74
75 if (level > aniState->noiseImmunityLevel)
76 ahp->ah_stats.ast_ani_niup++;
77 else if (level < aniState->noiseImmunityLevel)
78 ahp->ah_stats.ast_ani_nidown++;
79 aniState->noiseImmunityLevel = level;
80 break;
81 }
82 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
83 const int m1ThreshLow[] = { 127, 50 };
84 const int m2ThreshLow[] = { 127, 40 };
85 const int m1Thresh[] = { 127, 0x4d };
86 const int m2Thresh[] = { 127, 0x40 };
87 const int m2CountThr[] = { 31, 16 };
88 const int m2CountThrLow[] = { 63, 48 };
89 u32 on = param ? 1 : 0;
90
91 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
92 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
93 m1ThreshLow[on]);
94 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
95 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
96 m2ThreshLow[on]);
97 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
98 AR_PHY_SFCORR_M1_THRESH,
99 m1Thresh[on]);
100 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
101 AR_PHY_SFCORR_M2_THRESH,
102 m2Thresh[on]);
103 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
104 AR_PHY_SFCORR_M2COUNT_THR,
105 m2CountThr[on]);
106 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
107 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
108 m2CountThrLow[on]);
109
110 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
111 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
112 m1ThreshLow[on]);
113 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
114 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
115 m2ThreshLow[on]);
116 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
117 AR_PHY_SFCORR_EXT_M1_THRESH,
118 m1Thresh[on]);
119 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
120 AR_PHY_SFCORR_EXT_M2_THRESH,
121 m2Thresh[on]);
122
123 if (on)
124 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
125 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
126 else
127 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
128 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
129
130 if (!on != aniState->ofdmWeakSigDetectOff) {
131 if (on)
132 ahp->ah_stats.ast_ani_ofdmon++;
133 else
134 ahp->ah_stats.ast_ani_ofdmoff++;
135 aniState->ofdmWeakSigDetectOff = !on;
136 }
137 break;
138 }
139 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
140 const int weakSigThrCck[] = { 8, 6 };
141 u32 high = param ? 1 : 0;
142
143 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
144 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
145 weakSigThrCck[high]);
146 if (high != aniState->cckWeakSigThreshold) {
147 if (high)
148 ahp->ah_stats.ast_ani_cckhigh++;
149 else
150 ahp->ah_stats.ast_ani_ccklow++;
151 aniState->cckWeakSigThreshold = high;
152 }
153 break;
154 }
155 case ATH9K_ANI_FIRSTEP_LEVEL:{
156 const int firstep[] = { 0, 4, 8 };
157 u32 level = param;
158
159 if (level >= ARRAY_SIZE(firstep)) {
160 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
161 "%s: level out of range (%u > %u)\n",
162 __func__, level,
163 (unsigned) ARRAY_SIZE(firstep));
164 return false;
165 }
166 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
167 AR_PHY_FIND_SIG_FIRSTEP,
168 firstep[level]);
169 if (level > aniState->firstepLevel)
170 ahp->ah_stats.ast_ani_stepup++;
171 else if (level < aniState->firstepLevel)
172 ahp->ah_stats.ast_ani_stepdown++;
173 aniState->firstepLevel = level;
174 break;
175 }
176 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
177 const int cycpwrThr1[] =
178 { 2, 4, 6, 8, 10, 12, 14, 16 };
179 u32 level = param;
180
181 if (level >= ARRAY_SIZE(cycpwrThr1)) {
182 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
183 "%s: level out of range (%u > %u)\n",
184 __func__, level,
185 (unsigned)
186 ARRAY_SIZE(cycpwrThr1));
187 return false;
188 }
189 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
190 AR_PHY_TIMING5_CYCPWR_THR1,
191 cycpwrThr1[level]);
192 if (level > aniState->spurImmunityLevel)
193 ahp->ah_stats.ast_ani_spurup++;
194 else if (level < aniState->spurImmunityLevel)
195 ahp->ah_stats.ast_ani_spurdown++;
196 aniState->spurImmunityLevel = level;
197 break;
198 }
199 case ATH9K_ANI_PRESENT:
200 break;
201 default:
202 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
203 "%s: invalid cmd %u\n", __func__, cmd);
204 return false;
205 }
206
207 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
208 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
209 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
210 "ofdmWeakSigDetectOff=%d\n",
211 aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
212 !aniState->ofdmWeakSigDetectOff);
213 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
214 "cckWeakSigThreshold=%d, "
215 "firstepLevel=%d, listenTime=%d\n",
216 aniState->cckWeakSigThreshold, aniState->firstepLevel,
217 aniState->listenTime);
218 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
219 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
220 aniState->cycleCount, aniState->ofdmPhyErrCount,
221 aniState->cckPhyErrCount);
222
223 return true;
224}
225
226static void ath9k_hw_update_mibstats(struct ath_hal *ah,
227 struct ath9k_mib_stats *stats)
228{
229 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
230 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
231 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
232 stats->rts_good += REG_READ(ah, AR_RTS_OK);
233 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
234}
235
236static void ath9k_ani_restart(struct ath_hal *ah)
237{
238 struct ath_hal_5416 *ahp = AH5416(ah);
239 struct ar5416AniState *aniState;
240
241 if (!DO_ANI(ah))
242 return;
243
244 aniState = ahp->ah_curani;
245
246 aniState->listenTime = 0;
247 if (ahp->ah_hasHwPhyCounters) {
248 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
249 aniState->ofdmPhyErrBase = 0;
250 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
251 "OFDM Trigger is too high for hw counters\n");
252 } else {
253 aniState->ofdmPhyErrBase =
254 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
255 }
256 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
257 aniState->cckPhyErrBase = 0;
258 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
259 "CCK Trigger is too high for hw counters\n");
260 } else {
261 aniState->cckPhyErrBase =
262 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
263 }
264 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
265 "%s: Writing ofdmbase=%u cckbase=%u\n",
266 __func__, aniState->ofdmPhyErrBase,
267 aniState->cckPhyErrBase);
268 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
269 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
270 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
271 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
272
273 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
274 }
275 aniState->ofdmPhyErrCount = 0;
276 aniState->cckPhyErrCount = 0;
277}
278
279static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
280{
281 struct ath_hal_5416 *ahp = AH5416(ah);
282 struct ath9k_channel *chan = ah->ah_curchan;
283 struct ar5416AniState *aniState;
284 enum wireless_mode mode;
285 int32_t rssi;
286
287 if (!DO_ANI(ah))
288 return;
289
290 aniState = ahp->ah_curani;
291
292 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
293 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
294 aniState->noiseImmunityLevel + 1)) {
295 return;
296 }
297 }
298
299 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
300 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
301 aniState->spurImmunityLevel + 1)) {
302 return;
303 }
304 }
305
306 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
307 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
308 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
309 aniState->firstepLevel + 1);
310 }
311 return;
312 }
313 rssi = BEACON_RSSI(ahp);
314 if (rssi > aniState->rssiThrHigh) {
315 if (!aniState->ofdmWeakSigDetectOff) {
316 if (ath9k_hw_ani_control(ah,
317 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
318 false)) {
319 ath9k_hw_ani_control(ah,
320 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
321 return;
322 }
323 }
324 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
325 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
326 aniState->firstepLevel + 1);
327 return;
328 }
329 } else if (rssi > aniState->rssiThrLow) {
330 if (aniState->ofdmWeakSigDetectOff)
331 ath9k_hw_ani_control(ah,
332 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
333 true);
334 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
335 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
336 aniState->firstepLevel + 1);
337 return;
338 } else {
339 mode = ath9k_hw_chan2wmode(ah, chan);
340 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
341 if (!aniState->ofdmWeakSigDetectOff)
342 ath9k_hw_ani_control(ah,
343 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
344 false);
345 if (aniState->firstepLevel > 0)
346 ath9k_hw_ani_control(ah,
347 ATH9K_ANI_FIRSTEP_LEVEL, 0);
348 return;
349 }
350 }
351}
352
353static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
354{
355 struct ath_hal_5416 *ahp = AH5416(ah);
356 struct ath9k_channel *chan = ah->ah_curchan;
357 struct ar5416AniState *aniState;
358 enum wireless_mode mode;
359 int32_t rssi;
360
361 if (!DO_ANI(ah))
362 return;
363
364 aniState = ahp->ah_curani;
365 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
366 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
367 aniState->noiseImmunityLevel + 1)) {
368 return;
369 }
370 }
371 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
372 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
373 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
374 aniState->firstepLevel + 1);
375 }
376 return;
377 }
378 rssi = BEACON_RSSI(ahp);
379 if (rssi > aniState->rssiThrLow) {
380 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
381 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
382 aniState->firstepLevel + 1);
383 } else {
384 mode = ath9k_hw_chan2wmode(ah, chan);
385 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
386 if (aniState->firstepLevel > 0)
387 ath9k_hw_ani_control(ah,
388 ATH9K_ANI_FIRSTEP_LEVEL, 0);
389 }
390 }
391}
392
393static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
394{
395 struct ath_hal_5416 *ahp = AH5416(ah);
396 struct ar5416AniState *aniState;
397 int32_t rssi;
398
399 aniState = ahp->ah_curani;
400
401 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
402 if (aniState->firstepLevel > 0) {
403 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
404 aniState->firstepLevel - 1))
405 return;
406 }
407 } else {
408 rssi = BEACON_RSSI(ahp);
409 if (rssi > aniState->rssiThrHigh) {
410 /* XXX: Handle me */
411 } else if (rssi > aniState->rssiThrLow) {
412 if (aniState->ofdmWeakSigDetectOff) {
413 if (ath9k_hw_ani_control(ah,
414 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
415 true) == true)
416 return;
417 }
418 if (aniState->firstepLevel > 0) {
419 if (ath9k_hw_ani_control(ah,
420 ATH9K_ANI_FIRSTEP_LEVEL,
421 aniState->firstepLevel - 1) == true)
422 return;
423 }
424 } else {
425 if (aniState->firstepLevel > 0) {
426 if (ath9k_hw_ani_control(ah,
427 ATH9K_ANI_FIRSTEP_LEVEL,
428 aniState->firstepLevel - 1) == true)
429 return;
430 }
431 }
432 }
433
434 if (aniState->spurImmunityLevel > 0) {
435 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
436 aniState->spurImmunityLevel - 1))
437 return;
438 }
439
440 if (aniState->noiseImmunityLevel > 0) {
441 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
442 aniState->noiseImmunityLevel - 1);
443 return;
444 }
445}
446
447static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
448{
449 struct ath_hal_5416 *ahp = AH5416(ah);
450 struct ar5416AniState *aniState;
451 u32 txFrameCount, rxFrameCount, cycleCount;
452 int32_t listenTime;
453
454 txFrameCount = REG_READ(ah, AR_TFCNT);
455 rxFrameCount = REG_READ(ah, AR_RFCNT);
456 cycleCount = REG_READ(ah, AR_CCCNT);
457
458 aniState = ahp->ah_curani;
459 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
460
461 listenTime = 0;
462 ahp->ah_stats.ast_ani_lzero++;
463 } else {
464 int32_t ccdelta = cycleCount - aniState->cycleCount;
465 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
466 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
467 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
468 }
469 aniState->cycleCount = cycleCount;
470 aniState->txFrameCount = txFrameCount;
471 aniState->rxFrameCount = rxFrameCount;
472
473 return listenTime;
474}
475
476void ath9k_ani_reset(struct ath_hal *ah)
477{
478 struct ath_hal_5416 *ahp = AH5416(ah);
479 struct ar5416AniState *aniState;
480 struct ath9k_channel *chan = ah->ah_curchan;
481 int index;
482
483 if (!DO_ANI(ah))
484 return;
485
486 index = ath9k_hw_get_ani_channel_idx(ah, chan);
487 aniState = &ahp->ah_ani[index];
488 ahp->ah_curani = aniState;
489
490 if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
491 && ah->ah_opmode != ATH9K_M_IBSS) {
492 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
493 "%s: Reset ANI state opmode %u\n", __func__,
494 ah->ah_opmode);
495 ahp->ah_stats.ast_ani_reset++;
496
497 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
498 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
499 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
500 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
501 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
502 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
503 ATH9K_ANI_CCK_WEAK_SIG_THR);
504
505 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
506 ATH9K_RX_FILTER_PHYERR);
507
508 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
509 ahp->ah_curani->ofdmTrigHigh =
510 ah->ah_config.ofdm_trig_high;
511 ahp->ah_curani->ofdmTrigLow =
512 ah->ah_config.ofdm_trig_low;
513 ahp->ah_curani->cckTrigHigh =
514 ah->ah_config.cck_trig_high;
515 ahp->ah_curani->cckTrigLow =
516 ah->ah_config.cck_trig_low;
517 }
518 ath9k_ani_restart(ah);
519 return;
520 }
521
522 if (aniState->noiseImmunityLevel != 0)
523 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
524 aniState->noiseImmunityLevel);
525 if (aniState->spurImmunityLevel != 0)
526 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
527 aniState->spurImmunityLevel);
528 if (aniState->ofdmWeakSigDetectOff)
529 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
530 !aniState->ofdmWeakSigDetectOff);
531 if (aniState->cckWeakSigThreshold)
532 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
533 aniState->cckWeakSigThreshold);
534 if (aniState->firstepLevel != 0)
535 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
536 aniState->firstepLevel);
537 if (ahp->ah_hasHwPhyCounters) {
538 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
539 ~ATH9K_RX_FILTER_PHYERR);
540 ath9k_ani_restart(ah);
541 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
542 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
543
544 } else {
545 ath9k_ani_restart(ah);
546 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
547 ATH9K_RX_FILTER_PHYERR);
548 }
549}
550
551void ath9k_hw_ani_monitor(struct ath_hal *ah,
552 const struct ath9k_node_stats *stats,
553 struct ath9k_channel *chan)
554{
555 struct ath_hal_5416 *ahp = AH5416(ah);
556 struct ar5416AniState *aniState;
557 int32_t listenTime;
558
559 aniState = ahp->ah_curani;
560 ahp->ah_stats.ast_nodestats = *stats;
561
562 listenTime = ath9k_hw_ani_get_listen_time(ah);
563 if (listenTime < 0) {
564 ahp->ah_stats.ast_ani_lneg++;
565 ath9k_ani_restart(ah);
566 return;
567 }
568
569 aniState->listenTime += listenTime;
570
571 if (ahp->ah_hasHwPhyCounters) {
572 u32 phyCnt1, phyCnt2;
573 u32 ofdmPhyErrCnt, cckPhyErrCnt;
574
575 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
576
577 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
578 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
579
580 if (phyCnt1 < aniState->ofdmPhyErrBase ||
581 phyCnt2 < aniState->cckPhyErrBase) {
582 if (phyCnt1 < aniState->ofdmPhyErrBase) {
583 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
584 "%s: phyCnt1 0x%x, resetting "
585 "counter value to 0x%x\n",
586 __func__, phyCnt1,
587 aniState->ofdmPhyErrBase);
588 REG_WRITE(ah, AR_PHY_ERR_1,
589 aniState->ofdmPhyErrBase);
590 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
591 AR_PHY_ERR_OFDM_TIMING);
592 }
593 if (phyCnt2 < aniState->cckPhyErrBase) {
594 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
595 "%s: phyCnt2 0x%x, resetting "
596 "counter value to 0x%x\n",
597 __func__, phyCnt2,
598 aniState->cckPhyErrBase);
599 REG_WRITE(ah, AR_PHY_ERR_2,
600 aniState->cckPhyErrBase);
601 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
602 AR_PHY_ERR_CCK_TIMING);
603 }
604 return;
605 }
606
607 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
608 ahp->ah_stats.ast_ani_ofdmerrs +=
609 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
610 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
611
612 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
613 ahp->ah_stats.ast_ani_cckerrs +=
614 cckPhyErrCnt - aniState->cckPhyErrCount;
615 aniState->cckPhyErrCount = cckPhyErrCnt;
616 }
617
618 if (!DO_ANI(ah))
619 return;
620
621 if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
622 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
623 aniState->ofdmTrigLow / 1000 &&
624 aniState->cckPhyErrCount <= aniState->listenTime *
625 aniState->cckTrigLow / 1000)
626 ath9k_hw_ani_lower_immunity(ah);
627 ath9k_ani_restart(ah);
628 } else if (aniState->listenTime > ahp->ah_aniPeriod) {
629 if (aniState->ofdmPhyErrCount > aniState->listenTime *
630 aniState->ofdmTrigHigh / 1000) {
631 ath9k_hw_ani_ofdm_err_trigger(ah);
632 ath9k_ani_restart(ah);
633 } else if (aniState->cckPhyErrCount >
634 aniState->listenTime * aniState->cckTrigHigh /
635 1000) {
636 ath9k_hw_ani_cck_err_trigger(ah);
637 ath9k_ani_restart(ah);
638 }
639 }
640}
641
642bool ath9k_hw_phycounters(struct ath_hal *ah)
643{
644 struct ath_hal_5416 *ahp = AH5416(ah);
645
646 return ahp->ah_hasHwPhyCounters ? true : false;
647}
648
649void ath9k_enable_mib_counters(struct ath_hal *ah)
650{
651 struct ath_hal_5416 *ahp = AH5416(ah);
652
653 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n");
654
655 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
656
657 REG_WRITE(ah, AR_FILT_OFDM, 0);
658 REG_WRITE(ah, AR_FILT_CCK, 0);
659 REG_WRITE(ah, AR_MIBC,
660 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
661 & 0x0f);
662 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
663 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
664}
665
666void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
667{
668 struct ath_hal_5416 *ahp = AH5416(ah);
669
670 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n");
671
672 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
673
674 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
675
676 REG_WRITE(ah, AR_FILT_OFDM, 0);
677 REG_WRITE(ah, AR_FILT_CCK, 0);
678}
679
680u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
681 u32 *rxc_pcnt,
682 u32 *rxf_pcnt,
683 u32 *txf_pcnt)
684{
685 static u32 cycles, rx_clear, rx_frame, tx_frame;
686 u32 good = 1;
687
688 u32 rc = REG_READ(ah, AR_RCCNT);
689 u32 rf = REG_READ(ah, AR_RFCNT);
690 u32 tf = REG_READ(ah, AR_TFCNT);
691 u32 cc = REG_READ(ah, AR_CCCNT);
692
693 if (cycles == 0 || cycles > cc) {
694 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
695 "%s: cycle counter wrap. ExtBusy = 0\n",
696 __func__);
697 good = 0;
698 } else {
699 u32 cc_d = cc - cycles;
700 u32 rc_d = rc - rx_clear;
701 u32 rf_d = rf - rx_frame;
702 u32 tf_d = tf - tx_frame;
703
704 if (cc_d != 0) {
705 *rxc_pcnt = rc_d * 100 / cc_d;
706 *rxf_pcnt = rf_d * 100 / cc_d;
707 *txf_pcnt = tf_d * 100 / cc_d;
708 } else {
709 good = 0;
710 }
711 }
712
713 cycles = cc;
714 rx_frame = rf;
715 rx_clear = rc;
716 tx_frame = tf;
717
718 return good;
719}
720
721/*
722 * Process a MIB interrupt. We may potentially be invoked because
723 * any of the MIB counters overflow/trigger so don't assume we're
724 * here because a PHY error counter triggered.
725 */
726void ath9k_hw_procmibevent(struct ath_hal *ah,
727 const struct ath9k_node_stats *stats)
728{
729 struct ath_hal_5416 *ahp = AH5416(ah);
730 u32 phyCnt1, phyCnt2;
731
732 /* Reset these counters regardless */
733 REG_WRITE(ah, AR_FILT_OFDM, 0);
734 REG_WRITE(ah, AR_FILT_CCK, 0);
735 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
736 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
737
738 /* Clear the mib counters and save them in the stats */
739 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
740 ahp->ah_stats.ast_nodestats = *stats;
741
742 if (!DO_ANI(ah))
743 return;
744
745 /* NB: these are not reset-on-read */
746 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
747 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
748 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
749 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
750 struct ar5416AniState *aniState = ahp->ah_curani;
751 u32 ofdmPhyErrCnt, cckPhyErrCnt;
752
753 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
754 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
755 ahp->ah_stats.ast_ani_ofdmerrs +=
756 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
757 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
758
759 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
760 ahp->ah_stats.ast_ani_cckerrs +=
761 cckPhyErrCnt - aniState->cckPhyErrCount;
762 aniState->cckPhyErrCount = cckPhyErrCnt;
763
764 /*
765 * NB: figure out which counter triggered. If both
766 * trigger we'll only deal with one as the processing
767 * clobbers the error counter so the trigger threshold
768 * check will never be true.
769 */
770 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
771 ath9k_hw_ani_ofdm_err_trigger(ah);
772 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
773 ath9k_hw_ani_cck_err_trigger(ah);
774 /* NB: always restart to insure the h/w counters are reset */
775 ath9k_ani_restart(ah);
776 }
777}
778
779void ath9k_hw_ani_setup(struct ath_hal *ah)
780{
781 struct ath_hal_5416 *ahp = AH5416(ah);
782 int i;
783
784 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
785 const int coarseHigh[] = { -14, -14, -14, -14, -12 };
786 const int coarseLow[] = { -64, -64, -64, -64, -70 };
787 const int firpwr[] = { -78, -78, -78, -78, -80 };
788
789 for (i = 0; i < 5; i++) {
790 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
791 ahp->ah_coarseHigh[i] = coarseHigh[i];
792 ahp->ah_coarseLow[i] = coarseLow[i];
793 ahp->ah_firpwr[i] = firpwr[i];
794 }
795}
796
797void ath9k_hw_ani_attach(struct ath_hal *ah)
798{
799 struct ath_hal_5416 *ahp = AH5416(ah);
800 int i;
801
802 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n");
803
804 ahp->ah_hasHwPhyCounters = 1;
805
806 memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
807 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
808 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
809 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
810 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
811 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
812 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
813 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
814 ahp->ah_ani[i].ofdmWeakSigDetectOff =
815 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
816 ahp->ah_ani[i].cckWeakSigThreshold =
817 ATH9K_ANI_CCK_WEAK_SIG_THR;
818 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
819 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
820 if (ahp->ah_hasHwPhyCounters) {
821 ahp->ah_ani[i].ofdmPhyErrBase =
822 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
823 ahp->ah_ani[i].cckPhyErrBase =
824 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
825 }
826 }
827 if (ahp->ah_hasHwPhyCounters) {
828 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
829 "Setting OfdmErrBase = 0x%08x\n",
830 ahp->ah_ani[0].ofdmPhyErrBase);
831 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
832 ahp->ah_ani[0].cckPhyErrBase);
833
834 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
835 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
836 ath9k_enable_mib_counters(ah);
837 }
838 ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
839 if (ah->ah_config.enable_ani)
840 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
841}
842
843void ath9k_hw_ani_detach(struct ath_hal *ah)
844{
845 struct ath_hal_5416 *ahp = AH5416(ah);
846
847 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n");
848
849 if (ahp->ah_hasHwPhyCounters) {
850 ath9k_hw_disable_mib_counters(ah);
851 REG_WRITE(ah, AR_PHY_ERR_1, 0);
852 REG_WRITE(ah, AR_PHY_ERR_2, 0);
853 }
854}
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index a6063dea0fa2..3a180ce1770b 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -828,195 +828,251 @@ struct chan_centers {
828 u16 ext_center; 828 u16 ext_center;
829}; 829};
830 830
831int ath_hal_getcapability(struct ath_hal *ah, 831/* Helpers */
832 enum ath9k_capability_type type, 832
833 u32 capability, 833enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
834 u32 *result); 834 const struct ath9k_channel *chan);
835const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah, 835bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val);
836 u32 mode); 836u32 ath9k_hw_reverse_bits(u32 val, u32 n);
837void ath9k_hw_detach(struct ath_hal *ah); 837bool ath9k_get_channel_edges(struct ath_hal *ah,
838struct ath_hal *ath9k_hw_attach(u16 devid, 838 u16 flags, u16 *low,
839 struct ath_softc *sc, 839 u16 *high);
840 void __iomem *mem, 840u16 ath9k_hw_computetxtime(struct ath_hal *ah,
841 int *error); 841 const struct ath9k_rate_table *rates,
842bool ath9k_regd_init_channels(struct ath_hal *ah, 842 u32 frameLen, u16 rateix,
843 u32 maxchans, u32 *nchans, 843 bool shortPreamble);
844 u8 *regclassids,
845 u32 maxregids, u32 *nregids,
846 u16 cc,
847 bool enableOutdoor,
848 bool enableExtendedChannels);
849u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags); 844u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
850enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, 845void ath9k_hw_get_channel_centers(struct ath_hal *ah,
851 enum ath9k_int ints); 846 struct ath9k_channel *chan,
852bool ath9k_hw_reset(struct ath_hal *ah, 847 struct chan_centers *centers);
853 struct ath9k_channel *chan, 848
849/* Attach, Detach */
850
851const char *ath9k_hw_probe(u16 vendorid, u16 devid);
852void ath9k_hw_detach(struct ath_hal *ah);
853struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
854 void __iomem *mem, int *error);
855void ath9k_hw_rfdetach(struct ath_hal *ah);
856
857
858/* HW Reset */
859
860bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
854 enum ath9k_ht_macmode macmode, 861 enum ath9k_ht_macmode macmode,
855 u8 txchainmask, u8 rxchainmask, 862 u8 txchainmask, u8 rxchainmask,
856 enum ath9k_ht_extprotspacing extprotspacing, 863 enum ath9k_ht_extprotspacing extprotspacing,
857 bool bChannelChange, 864 bool bChannelChange, int *status);
858 int *status); 865
859bool ath9k_hw_phy_disable(struct ath_hal *ah); 866/* Key Cache Management */
860void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan, 867
861 bool *isCalDone);
862void ath9k_hw_ani_monitor(struct ath_hal *ah,
863 const struct ath9k_node_stats *stats,
864 struct ath9k_channel *chan);
865bool ath9k_hw_calibrate(struct ath_hal *ah,
866 struct ath9k_channel *chan,
867 u8 rxchainmask,
868 bool longcal,
869 bool *isCalDone);
870s16 ath9k_hw_getchan_noise(struct ath_hal *ah,
871 struct ath9k_channel *chan);
872void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
873 u16 assocId);
874void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
875void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
876 u16 assocId);
877bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
878void ath9k_hw_reset_tsf(struct ath_hal *ah);
879bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
880bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
881 const u8 *mac);
882bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
883 u16 entry,
884 const struct ath9k_keyval *k,
885 const u8 *mac,
886 int xorKey);
887bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
888 u32 setting);
889void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
890bool ath9k_hw_intrpend(struct ath_hal *ah);
891bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
892bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
893 bool bIncTrigLevel);
894void ath9k_hw_procmibevent(struct ath_hal *ah,
895 const struct ath9k_node_stats *stats);
896bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
897void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
898bool ath9k_hw_phycounters(struct ath_hal *ah);
899bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); 868bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
900bool ath9k_hw_getcapability(struct ath_hal *ah, 869bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac);
901 enum ath9k_capability_type type, 870bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
902 u32 capability, 871 const struct ath9k_keyval *k,
903 u32 *result); 872 const u8 *mac, int xorKey);
904bool ath9k_hw_setcapability(struct ath_hal *ah, 873bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
905 enum ath9k_capability_type type, 874
906 u32 capability, 875/* Power Management */
907 u32 setting, 876
908 int *status);
909u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
910void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
911void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
912bool ath9k_hw_setbssidmask(struct ath_hal *ah,
913 const u8 *mask);
914bool ath9k_hw_setpower(struct ath_hal *ah, 877bool ath9k_hw_setpower(struct ath_hal *ah,
915 enum ath9k_power_mode mode); 878 enum ath9k_power_mode mode);
916enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); 879void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
917u64 ath9k_hw_gettsf64(struct ath_hal *ah); 880
881/* Beacon timers */
882
883void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period);
884void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
885 const struct ath9k_beacon_state *bs);
886
887/* Rate table */
888
889const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
890 u32 mode);
891
892/* HW Capabilities */
893
894bool ath9k_hw_fill_cap_info(struct ath_hal *ah);
895bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
896 u32 capability, u32 *result);
897bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
898 u32 capability, u32 setting, int *status);
899
900/* GPIO / RFKILL / Antennae */
901
902void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio);
903u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
904void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
905 u32 ah_signal_type);
906void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val);
907#ifdef CONFIG_RFKILL
908void ath9k_enable_rfkill(struct ath_hal *ah);
909#endif
910int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg);
918u32 ath9k_hw_getdefantenna(struct ath_hal *ah); 911u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
919bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); 912void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
920bool ath9k_hw_setantennaswitch(struct ath_hal *ah, 913bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
921 enum ath9k_ant_setting settings, 914 enum ath9k_ant_setting settings,
922 struct ath9k_channel *chan, 915 struct ath9k_channel *chan,
923 u8 *tx_chainmask, 916 u8 *tx_chainmask,
924 u8 *rx_chainmask, 917 u8 *rx_chainmask,
925 u8 *antenna_cfgd); 918 u8 *antenna_cfgd);
926void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); 919
927int ath9k_hw_select_antconfig(struct ath_hal *ah, 920/* General Operation */
928 u32 cfg); 921
929bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, 922u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
930 u32 txdp); 923void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
924bool ath9k_hw_phy_disable(struct ath_hal *ah);
925bool ath9k_hw_disable(struct ath_hal *ah);
926bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
927void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
928bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
929void ath9k_hw_setopmode(struct ath_hal *ah);
930void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1);
931void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
932bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask);
933void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId);
934u64 ath9k_hw_gettsf64(struct ath_hal *ah);
935void ath9k_hw_reset_tsf(struct ath_hal *ah);
936bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting);
937bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
938void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
939
940/* Regulatory */
941
942bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
943struct ath9k_channel* ath9k_regd_check_channel(struct ath_hal *ah,
944 const struct ath9k_channel *c);
945u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
946u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
947 struct ath9k_channel *chan);
948bool ath9k_regd_init_channels(struct ath_hal *ah,
949 u32 maxchans, u32 *nchans, u8 *regclassids,
950 u32 maxregids, u32 *nregids, u16 cc,
951 bool enableOutdoor, bool enableExtendedChannels);
952
953/* ANI */
954
955void ath9k_ani_reset(struct ath_hal *ah);
956void ath9k_hw_ani_monitor(struct ath_hal *ah,
957 const struct ath9k_node_stats *stats,
958 struct ath9k_channel *chan);
959bool ath9k_hw_phycounters(struct ath_hal *ah);
960void ath9k_enable_mib_counters(struct ath_hal *ah);
961void ath9k_hw_disable_mib_counters(struct ath_hal *ah);
962u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
963 u32 *rxc_pcnt,
964 u32 *rxf_pcnt,
965 u32 *txf_pcnt);
966void ath9k_hw_procmibevent(struct ath_hal *ah,
967 const struct ath9k_node_stats *stats);
968void ath9k_hw_ani_setup(struct ath_hal *ah);
969void ath9k_hw_ani_attach(struct ath_hal *ah);
970void ath9k_hw_ani_detach(struct ath_hal *ah);
971
972/* Calibration */
973
974void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
975 bool *isCalDone);
976void ath9k_hw_start_nfcal(struct ath_hal *ah);
977void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
978int16_t ath9k_hw_getnf(struct ath_hal *ah,
979 struct ath9k_channel *chan);
980void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah);
981s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan);
982bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
983 u8 rxchainmask, bool longcal,
984 bool *isCalDone);
985bool ath9k_hw_init_cal(struct ath_hal *ah,
986 struct ath9k_channel *chan);
987
988
989/* EEPROM */
990
991int ath9k_hw_set_txpower(struct ath_hal *ah,
992 struct ath9k_channel *chan,
993 u16 cfgCtl,
994 u8 twiceAntennaReduction,
995 u8 twiceMaxRegulatoryPower,
996 u8 powerLimit);
997void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan);
998bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
999 struct ath9k_channel *chan,
1000 int16_t *ratesArray,
1001 u16 cfgCtl,
1002 u8 AntennaReduction,
1003 u8 twiceMaxRegulatoryPower,
1004 u8 powerLimit);
1005bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
1006 struct ath9k_channel *chan,
1007 int16_t *pTxPowerIndexOffset);
1008bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
1009 struct ath9k_channel *chan);
1010int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
1011 struct ath9k_channel *chan,
1012 u8 index, u16 *config);
1013u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
1014 enum ieee80211_band freq_band);
1015u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz);
1016int ath9k_hw_eeprom_attach(struct ath_hal *ah);
1017
1018/* Interrupt Handling */
1019
1020bool ath9k_hw_intrpend(struct ath_hal *ah);
1021bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
1022enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
1023enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints);
1024
1025/* MAC (PCU/QCU) */
1026
1027void ath9k_hw_dmaRegDump(struct ath_hal *ah);
1028u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
1029bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp);
931bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); 1030bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
932u16 ath9k_hw_computetxtime(struct ath_hal *ah, 1031u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
933 const struct ath9k_rate_table *rates, 1032bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel);
934 u32 frameLen, u16 rateix, 1033bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
935 bool shortPreamble); 1034bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1035 u32 segLen, bool firstSeg,
1036 bool lastSeg, const struct ath_desc *ds0);
1037void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1038int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds);
1039void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1040 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
1041 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
936void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, 1042void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
937 struct ath_desc *lastds, 1043 struct ath_desc *lastds,
938 u32 durUpdateEn, u32 rtsctsRate, 1044 u32 durUpdateEn, u32 rtsctsRate,
939 u32 rtsctsDuration, 1045 u32 rtsctsDuration,
940 struct ath9k_11n_rate_series series[], 1046 struct ath9k_11n_rate_series series[],
941 u32 nseries, u32 flags); 1047 u32 nseries, u32 flags);
942void ath9k_hw_set11n_burstduration(struct ath_hal *ah, 1048void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
943 struct ath_desc *ds, 1049 u32 aggrLen);
1050void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1051 u32 numDelims);
1052void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1053void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1054void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
944 u32 burstDuration); 1055 u32 burstDuration);
945void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); 1056void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
946u32 ath9k_hw_reverse_bits(u32 val, u32 n); 1057 u32 vmf);
947bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); 1058void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
948u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
949u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
950 struct ath9k_channel *chan);
951u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
952bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
953 struct ath9k_tx_queue_info *qinfo);
954bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, 1059bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
955 const struct ath9k_tx_queue_info *qinfo); 1060 const struct ath9k_tx_queue_info *qinfo);
956struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah, 1061bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
957 const struct ath9k_channel *c); 1062 struct ath9k_tx_queue_info *qinfo);
958void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, 1063int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
959 u32 pktLen, enum ath9k_pkt_type type, 1064 const struct ath9k_tx_queue_info *qinfo);
960 u32 txPower, u32 keyIx, 1065bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
961 enum ath9k_key_type keyType, u32 flags); 1066bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
962bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, 1067int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
963 u32 segLen, bool firstSeg, 1068 u32 pa, struct ath_desc *nds, u64 tsf);
964 bool lastSeg,
965 const struct ath_desc *ds0);
966u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
967 u32 *rxc_pcnt,
968 u32 *rxf_pcnt,
969 u32 *txf_pcnt);
970void ath9k_hw_dmaRegDump(struct ath_hal *ah);
971void ath9k_hw_beaconinit(struct ath_hal *ah,
972 u32 next_beacon, u32 beacon_period);
973void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
974 const struct ath9k_beacon_state *bs);
975bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, 1069bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
976 u32 size, u32 flags); 1070 u32 size, u32 flags);
1071bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
977void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); 1072void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
978void ath9k_hw_rxena(struct ath_hal *ah); 1073void ath9k_hw_rxena(struct ath_hal *ah);
979void ath9k_hw_setopmode(struct ath_hal *ah);
980bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
981void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
982 u32 filter1);
983u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
984void ath9k_hw_startpcureceive(struct ath_hal *ah); 1074void ath9k_hw_startpcureceive(struct ath_hal *ah);
985void ath9k_hw_stoppcurecv(struct ath_hal *ah); 1075void ath9k_hw_stoppcurecv(struct ath_hal *ah);
986bool ath9k_hw_stopdmarecv(struct ath_hal *ah); 1076bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
987int ath9k_hw_rxprocdesc(struct ath_hal *ah, 1077
988 struct ath_desc *ds, u32 pa,
989 struct ath_desc *nds, u64 tsf);
990u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
991int ath9k_hw_txprocdesc(struct ath_hal *ah,
992 struct ath_desc *ds);
993void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
994 u32 numDelims);
995void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
996 u32 aggrLen);
997void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
998bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
999void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1000void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1001void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
1002 struct ath_desc *ds, u32 vmf);
1003bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
1004bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
1005int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1006 const struct ath9k_tx_queue_info *qinfo);
1007u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
1008const char *ath9k_hw_probe(u16 vendorid, u16 devid);
1009bool ath9k_hw_disable(struct ath_hal *ah);
1010void ath9k_hw_rfdetach(struct ath_hal *ah);
1011void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1012 struct ath9k_channel *chan,
1013 struct chan_centers *centers);
1014bool ath9k_get_channel_edges(struct ath_hal *ah,
1015 u16 flags, u16 *low,
1016 u16 *high);
1017void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
1018 u32 ah_signal_type);
1019void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 value);
1020u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
1021void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio);
1022#endif 1078#endif
diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
new file mode 100644
index 000000000000..1690759fe7b8
--- /dev/null
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -0,0 +1,930 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "core.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21
22static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
23
24/* We can tune this as we go by monitoring really low values */
25#define ATH9K_NF_TOO_LOW -60
26
27/* AR5416 may return very high value (like -31 dBm), in those cases the nf
28 * is incorrect and we should use the static NF value. Later we can try to
29 * find out why they are reporting these values */
30
31static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
32{
33 if (nf > ATH9K_NF_TOO_LOW) {
34 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
35 "%s: noise floor value detected (%d) is "
36 "lower than what we think is a "
37 "reasonable value (%d)\n",
38 __func__, nf, ATH9K_NF_TOO_LOW);
39 return false;
40 }
41 return true;
42}
43
44static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
45{
46 int16_t nfval;
47 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
48 int i, j;
49
50 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
51 sort[i] = nfCalBuffer[i];
52
53 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
54 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
55 if (sort[j] > sort[j - 1]) {
56 nfval = sort[j];
57 sort[j] = sort[j - 1];
58 sort[j - 1] = nfval;
59 }
60 }
61 }
62 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
63
64 return nfval;
65}
66
67static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
68 int16_t *nfarray)
69{
70 int i;
71
72 for (i = 0; i < NUM_NF_READINGS; i++) {
73 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
74
75 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
76 h[i].currIndex = 0;
77
78 if (h[i].invalidNFcount > 0) {
79 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
80 nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
81 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
82 } else {
83 h[i].invalidNFcount--;
84 h[i].privNF = nfarray[i];
85 }
86 } else {
87 h[i].privNF =
88 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
89 }
90 }
91 return;
92}
93
94static void ath9k_hw_do_getnf(struct ath_hal *ah,
95 int16_t nfarray[NUM_NF_READINGS])
96{
97 int16_t nf;
98
99 if (AR_SREV_9280_10_OR_LATER(ah))
100 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
101 else
102 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
103
104 if (nf & 0x100)
105 nf = 0 - ((nf ^ 0x1ff) + 1);
106 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
107 "NF calibrated [ctl] [chain 0] is %d\n", nf);
108 nfarray[0] = nf;
109
110 if (AR_SREV_9280_10_OR_LATER(ah))
111 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
112 AR9280_PHY_CH1_MINCCA_PWR);
113 else
114 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
115 AR_PHY_CH1_MINCCA_PWR);
116
117 if (nf & 0x100)
118 nf = 0 - ((nf ^ 0x1ff) + 1);
119 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
120 "NF calibrated [ctl] [chain 1] is %d\n", nf);
121 nfarray[1] = nf;
122
123 if (!AR_SREV_9280(ah)) {
124 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
125 AR_PHY_CH2_MINCCA_PWR);
126 if (nf & 0x100)
127 nf = 0 - ((nf ^ 0x1ff) + 1);
128 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
129 "NF calibrated [ctl] [chain 2] is %d\n", nf);
130 nfarray[2] = nf;
131 }
132
133 if (AR_SREV_9280_10_OR_LATER(ah))
134 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
135 AR9280_PHY_EXT_MINCCA_PWR);
136 else
137 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
138 AR_PHY_EXT_MINCCA_PWR);
139
140 if (nf & 0x100)
141 nf = 0 - ((nf ^ 0x1ff) + 1);
142 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
143 "NF calibrated [ext] [chain 0] is %d\n", nf);
144 nfarray[3] = nf;
145
146 if (AR_SREV_9280_10_OR_LATER(ah))
147 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
148 AR9280_PHY_CH1_EXT_MINCCA_PWR);
149 else
150 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
151 AR_PHY_CH1_EXT_MINCCA_PWR);
152
153 if (nf & 0x100)
154 nf = 0 - ((nf ^ 0x1ff) + 1);
155 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
156 "NF calibrated [ext] [chain 1] is %d\n", nf);
157 nfarray[4] = nf;
158
159 if (!AR_SREV_9280(ah)) {
160 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
161 AR_PHY_CH2_EXT_MINCCA_PWR);
162 if (nf & 0x100)
163 nf = 0 - ((nf ^ 0x1ff) + 1);
164 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
165 "NF calibrated [ext] [chain 2] is %d\n", nf);
166 nfarray[5] = nf;
167 }
168}
169
170static bool getNoiseFloorThresh(struct ath_hal *ah,
171 const struct ath9k_channel *chan,
172 int16_t *nft)
173{
174 switch (chan->chanmode) {
175 case CHANNEL_A:
176 case CHANNEL_A_HT20:
177 case CHANNEL_A_HT40PLUS:
178 case CHANNEL_A_HT40MINUS:
179 *nft = (int16_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5);
180 break;
181 case CHANNEL_B:
182 case CHANNEL_G:
183 case CHANNEL_G_HT20:
184 case CHANNEL_G_HT40PLUS:
185 case CHANNEL_G_HT40MINUS:
186 *nft = (int16_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2);
187 break;
188 default:
189 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
190 "%s: invalid channel flags 0x%x\n", __func__,
191 chan->channelFlags);
192 return false;
193 }
194
195 return true;
196}
197
198static void ath9k_hw_setup_calibration(struct ath_hal *ah,
199 struct hal_cal_list *currCal)
200{
201 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
202 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
203 currCal->calData->calCountMax);
204
205 switch (currCal->calData->calType) {
206 case IQ_MISMATCH_CAL:
207 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
208 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
209 "%s: starting IQ Mismatch Calibration\n",
210 __func__);
211 break;
212 case ADC_GAIN_CAL:
213 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
214 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
215 "%s: starting ADC Gain Calibration\n", __func__);
216 break;
217 case ADC_DC_CAL:
218 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
219 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
220 "%s: starting ADC DC Calibration\n", __func__);
221 break;
222 case ADC_DC_INIT_CAL:
223 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
224 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
225 "%s: starting Init ADC DC Calibration\n",
226 __func__);
227 break;
228 }
229
230 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
231 AR_PHY_TIMING_CTRL4_DO_CAL);
232}
233
234static void ath9k_hw_reset_calibration(struct ath_hal *ah,
235 struct hal_cal_list *currCal)
236{
237 struct ath_hal_5416 *ahp = AH5416(ah);
238 int i;
239
240 ath9k_hw_setup_calibration(ah, currCal);
241
242 currCal->calState = CAL_RUNNING;
243
244 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
245 ahp->ah_Meas0.sign[i] = 0;
246 ahp->ah_Meas1.sign[i] = 0;
247 ahp->ah_Meas2.sign[i] = 0;
248 ahp->ah_Meas3.sign[i] = 0;
249 }
250
251 ahp->ah_CalSamples = 0;
252}
253
254static void ath9k_hw_per_calibration(struct ath_hal *ah,
255 struct ath9k_channel *ichan,
256 u8 rxchainmask,
257 struct hal_cal_list *currCal,
258 bool *isCalDone)
259{
260 struct ath_hal_5416 *ahp = AH5416(ah);
261
262 *isCalDone = false;
263
264 if (currCal->calState == CAL_RUNNING) {
265 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
266 AR_PHY_TIMING_CTRL4_DO_CAL)) {
267
268 currCal->calData->calCollect(ah);
269 ahp->ah_CalSamples++;
270
271 if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) {
272 int i, numChains = 0;
273 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
274 if (rxchainmask & (1 << i))
275 numChains++;
276 }
277
278 currCal->calData->calPostProc(ah, numChains);
279 ichan->CalValid |= currCal->calData->calType;
280 currCal->calState = CAL_DONE;
281 *isCalDone = true;
282 } else {
283 ath9k_hw_setup_calibration(ah, currCal);
284 }
285 }
286 } else if (!(ichan->CalValid & currCal->calData->calType)) {
287 ath9k_hw_reset_calibration(ah, currCal);
288 }
289}
290
291static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
292 struct ath9k_channel *chan,
293 enum hal_cal_types calType)
294{
295 struct ath_hal_5416 *ahp = AH5416(ah);
296 bool retval = false;
297
298 switch (calType & ahp->ah_suppCals) {
299 case IQ_MISMATCH_CAL:
300 if (!IS_CHAN_B(chan))
301 retval = true;
302 break;
303 case ADC_GAIN_CAL:
304 case ADC_DC_CAL:
305 if (!IS_CHAN_B(chan)
306 && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
307 retval = true;
308 break;
309 }
310
311 return retval;
312}
313
314static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
315{
316 struct ath_hal_5416 *ahp = AH5416(ah);
317 int i;
318
319 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
320 ahp->ah_totalPowerMeasI[i] +=
321 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
322 ahp->ah_totalPowerMeasQ[i] +=
323 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
324 ahp->ah_totalIqCorrMeas[i] +=
325 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
326 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
327 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
328 ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
329 ahp->ah_totalPowerMeasQ[i],
330 ahp->ah_totalIqCorrMeas[i]);
331 }
332}
333
334static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
335{
336 struct ath_hal_5416 *ahp = AH5416(ah);
337 int i;
338
339 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
340 ahp->ah_totalAdcIOddPhase[i] +=
341 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
342 ahp->ah_totalAdcIEvenPhase[i] +=
343 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
344 ahp->ah_totalAdcQOddPhase[i] +=
345 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
346 ahp->ah_totalAdcQEvenPhase[i] +=
347 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
348
349 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
350 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
351 "oddq=0x%08x; evenq=0x%08x;\n",
352 ahp->ah_CalSamples, i,
353 ahp->ah_totalAdcIOddPhase[i],
354 ahp->ah_totalAdcIEvenPhase[i],
355 ahp->ah_totalAdcQOddPhase[i],
356 ahp->ah_totalAdcQEvenPhase[i]);
357 }
358}
359
360static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
361{
362 struct ath_hal_5416 *ahp = AH5416(ah);
363 int i;
364
365 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
366 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
367 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
368 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
369 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
370 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
371 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
372 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
373 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
374
375 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
376 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
377 "oddq=0x%08x; evenq=0x%08x;\n",
378 ahp->ah_CalSamples, i,
379 ahp->ah_totalAdcDcOffsetIOddPhase[i],
380 ahp->ah_totalAdcDcOffsetIEvenPhase[i],
381 ahp->ah_totalAdcDcOffsetQOddPhase[i],
382 ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
383 }
384}
385
386static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
387{
388 struct ath_hal_5416 *ahp = AH5416(ah);
389 u32 powerMeasQ, powerMeasI, iqCorrMeas;
390 u32 qCoffDenom, iCoffDenom;
391 int32_t qCoff, iCoff;
392 int iqCorrNeg, i;
393
394 for (i = 0; i < numChains; i++) {
395 powerMeasI = ahp->ah_totalPowerMeasI[i];
396 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
397 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
398
399 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
400 "Starting IQ Cal and Correction for Chain %d\n",
401 i);
402
403 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
404 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
405 i, ahp->ah_totalIqCorrMeas[i]);
406
407 iqCorrNeg = 0;
408
409 if (iqCorrMeas > 0x80000000) {
410 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
411 iqCorrNeg = 1;
412 }
413
414 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
415 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
416 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
417 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
418 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
419 iqCorrNeg);
420
421 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
422 qCoffDenom = powerMeasQ / 64;
423
424 if (powerMeasQ != 0) {
425 iCoff = iqCorrMeas / iCoffDenom;
426 qCoff = powerMeasI / qCoffDenom - 64;
427 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
428 "Chn %d iCoff = 0x%08x\n", i, iCoff);
429 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
430 "Chn %d qCoff = 0x%08x\n", i, qCoff);
431
432 iCoff = iCoff & 0x3f;
433 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
434 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
435 if (iqCorrNeg == 0x0)
436 iCoff = 0x40 - iCoff;
437
438 if (qCoff > 15)
439 qCoff = 15;
440 else if (qCoff <= -16)
441 qCoff = 16;
442
443 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
444 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
445 i, iCoff, qCoff);
446
447 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
448 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
449 iCoff);
450 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
451 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
452 qCoff);
453 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
454 "IQ Cal and Correction done for Chain %d\n",
455 i);
456 }
457 }
458
459 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
460 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
461}
462
463static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
464{
465 struct ath_hal_5416 *ahp = AH5416(ah);
466 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
467 u32 qGainMismatch, iGainMismatch, val, i;
468
469 for (i = 0; i < numChains; i++) {
470 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
471 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
472 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
473 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
474
475 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
476 "Starting ADC Gain Cal for Chain %d\n", i);
477
478 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
479 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
480 iOddMeasOffset);
481 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
482 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
483 iEvenMeasOffset);
484 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
485 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
486 qOddMeasOffset);
487 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
488 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
489 qEvenMeasOffset);
490
491 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
492 iGainMismatch =
493 ((iEvenMeasOffset * 32) /
494 iOddMeasOffset) & 0x3f;
495 qGainMismatch =
496 ((qOddMeasOffset * 32) /
497 qEvenMeasOffset) & 0x3f;
498
499 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
500 "Chn %d gain_mismatch_i = 0x%08x\n", i,
501 iGainMismatch);
502 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
503 "Chn %d gain_mismatch_q = 0x%08x\n", i,
504 qGainMismatch);
505
506 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
507 val &= 0xfffff000;
508 val |= (qGainMismatch) | (iGainMismatch << 6);
509 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
510
511 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
512 "ADC Gain Cal done for Chain %d\n", i);
513 }
514 }
515
516 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
517 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
518 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
519}
520
521static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
522{
523 struct ath_hal_5416 *ahp = AH5416(ah);
524 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
525 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
526 const struct hal_percal_data *calData =
527 ahp->ah_cal_list_curr->calData;
528 u32 numSamples =
529 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
530
531 for (i = 0; i < numChains; i++) {
532 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
533 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
534 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
535 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
536
537 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
538 "Starting ADC DC Offset Cal for Chain %d\n", i);
539
540 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
541 "Chn %d pwr_meas_odd_i = %d\n", i,
542 iOddMeasOffset);
543 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
544 "Chn %d pwr_meas_even_i = %d\n", i,
545 iEvenMeasOffset);
546 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
547 "Chn %d pwr_meas_odd_q = %d\n", i,
548 qOddMeasOffset);
549 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
550 "Chn %d pwr_meas_even_q = %d\n", i,
551 qEvenMeasOffset);
552
553 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
554 numSamples) & 0x1ff;
555 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
556 numSamples) & 0x1ff;
557
558 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
559 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
560 iDcMismatch);
561 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
562 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
563 qDcMismatch);
564
565 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
566 val &= 0xc0000fff;
567 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
568 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
569
570 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
571 "ADC DC Offset Cal done for Chain %d\n", i);
572 }
573
574 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
575 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
576 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
577}
578
579void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
580 bool *isCalDone)
581{
582 struct ath_hal_5416 *ahp = AH5416(ah);
583 struct ath9k_channel *ichan =
584 ath9k_regd_check_channel(ah, chan);
585 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
586
587 *isCalDone = true;
588
589 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
590 return;
591
592 if (currCal == NULL)
593 return;
594
595 if (ichan == NULL) {
596 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
597 "%s: invalid channel %u/0x%x; no mapping\n",
598 __func__, chan->channel, chan->channelFlags);
599 return;
600 }
601
602
603 if (currCal->calState != CAL_DONE) {
604 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
605 "%s: Calibration state incorrect, %d\n",
606 __func__, currCal->calState);
607 return;
608 }
609
610
611 if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))
612 return;
613
614 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
615 "%s: Resetting Cal %d state for channel %u/0x%x\n",
616 __func__, currCal->calData->calType, chan->channel,
617 chan->channelFlags);
618
619 ichan->CalValid &= ~currCal->calData->calType;
620 currCal->calState = CAL_WAITING;
621
622 *isCalDone = false;
623}
624
625void ath9k_hw_start_nfcal(struct ath_hal *ah)
626{
627 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
628 AR_PHY_AGC_CONTROL_ENABLE_NF);
629 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
630 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
631 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
632}
633
634void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
635{
636 struct ath9k_nfcal_hist *h;
637 int i, j;
638 int32_t val;
639 const u32 ar5416_cca_regs[6] = {
640 AR_PHY_CCA,
641 AR_PHY_CH1_CCA,
642 AR_PHY_CH2_CCA,
643 AR_PHY_EXT_CCA,
644 AR_PHY_CH1_EXT_CCA,
645 AR_PHY_CH2_EXT_CCA
646 };
647 u8 chainmask;
648
649 if (AR_SREV_9280(ah))
650 chainmask = 0x1B;
651 else
652 chainmask = 0x3F;
653
654#ifdef ATH_NF_PER_CHAN
655 h = chan->nfCalHist;
656#else
657 h = ah->nfCalHist;
658#endif
659
660 for (i = 0; i < NUM_NF_READINGS; i++) {
661 if (chainmask & (1 << i)) {
662 val = REG_READ(ah, ar5416_cca_regs[i]);
663 val &= 0xFFFFFE00;
664 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
665 REG_WRITE(ah, ar5416_cca_regs[i], val);
666 }
667 }
668
669 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
670 AR_PHY_AGC_CONTROL_ENABLE_NF);
671 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
672 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
673 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
674
675 for (j = 0; j < 1000; j++) {
676 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
677 AR_PHY_AGC_CONTROL_NF) == 0)
678 break;
679 udelay(10);
680 }
681
682 for (i = 0; i < NUM_NF_READINGS; i++) {
683 if (chainmask & (1 << i)) {
684 val = REG_READ(ah, ar5416_cca_regs[i]);
685 val &= 0xFFFFFE00;
686 val |= (((u32) (-50) << 1) & 0x1ff);
687 REG_WRITE(ah, ar5416_cca_regs[i], val);
688 }
689 }
690}
691
692int16_t ath9k_hw_getnf(struct ath_hal *ah,
693 struct ath9k_channel *chan)
694{
695 int16_t nf, nfThresh;
696 int16_t nfarray[NUM_NF_READINGS] = { 0 };
697 struct ath9k_nfcal_hist *h;
698 u8 chainmask;
699
700 if (AR_SREV_9280(ah))
701 chainmask = 0x1B;
702 else
703 chainmask = 0x3F;
704
705 chan->channelFlags &= (~CHANNEL_CW_INT);
706 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
707 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
708 "%s: NF did not complete in calibration window\n",
709 __func__);
710 nf = 0;
711 chan->rawNoiseFloor = nf;
712 return chan->rawNoiseFloor;
713 } else {
714 ath9k_hw_do_getnf(ah, nfarray);
715 nf = nfarray[0];
716 if (getNoiseFloorThresh(ah, chan, &nfThresh)
717 && nf > nfThresh) {
718 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
719 "%s: noise floor failed detected; "
720 "detected %d, threshold %d\n", __func__,
721 nf, nfThresh);
722 chan->channelFlags |= CHANNEL_CW_INT;
723 }
724 }
725
726#ifdef ATH_NF_PER_CHAN
727 h = chan->nfCalHist;
728#else
729 h = ah->nfCalHist;
730#endif
731
732 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
733 chan->rawNoiseFloor = h[0].privNF;
734
735 return chan->rawNoiseFloor;
736}
737
738void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
739{
740 int i, j;
741
742 for (i = 0; i < NUM_NF_READINGS; i++) {
743 ah->nfCalHist[i].currIndex = 0;
744 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
745 ah->nfCalHist[i].invalidNFcount =
746 AR_PHY_CCA_FILTERWINDOW_LENGTH;
747 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
748 ah->nfCalHist[i].nfCalBuffer[j] =
749 AR_PHY_CCA_MAX_GOOD_VALUE;
750 }
751 }
752 return;
753}
754
755s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
756{
757 struct ath9k_channel *ichan;
758 s16 nf;
759
760 ichan = ath9k_regd_check_channel(ah, chan);
761 if (ichan == NULL) {
762 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
763 "%s: invalid channel %u/0x%x; no mapping\n",
764 __func__, chan->channel, chan->channelFlags);
765 return ATH_DEFAULT_NOISE_FLOOR;
766 }
767 if (ichan->rawNoiseFloor == 0) {
768 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
769 nf = NOISE_FLOOR[mode];
770 } else
771 nf = ichan->rawNoiseFloor;
772
773 if (!ath9k_hw_nf_in_range(ah, nf))
774 nf = ATH_DEFAULT_NOISE_FLOOR;
775
776 return nf;
777}
778
779bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
780 u8 rxchainmask, bool longcal,
781 bool *isCalDone)
782{
783 struct ath_hal_5416 *ahp = AH5416(ah);
784 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
785 struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
786
787 *isCalDone = true;
788
789 if (ichan == NULL) {
790 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
791 "%s: invalid channel %u/0x%x; no mapping\n",
792 __func__, chan->channel, chan->channelFlags);
793 return false;
794 }
795
796 if (currCal &&
797 (currCal->calState == CAL_RUNNING ||
798 currCal->calState == CAL_WAITING)) {
799 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
800 isCalDone);
801 if (*isCalDone) {
802 ahp->ah_cal_list_curr = currCal = currCal->calNext;
803
804 if (currCal->calState == CAL_WAITING) {
805 *isCalDone = false;
806 ath9k_hw_reset_calibration(ah, currCal);
807 }
808 }
809 }
810
811 if (longcal) {
812 ath9k_hw_getnf(ah, ichan);
813 ath9k_hw_loadnf(ah, ah->ah_curchan);
814 ath9k_hw_start_nfcal(ah);
815
816 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
817 chan->channelFlags |= CHANNEL_CW_INT;
818 ichan->channelFlags &= ~CHANNEL_CW_INT;
819 }
820 }
821
822 return true;
823}
824
825bool ath9k_hw_init_cal(struct ath_hal *ah,
826 struct ath9k_channel *chan)
827{
828 struct ath_hal_5416 *ahp = AH5416(ah);
829 struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
830
831 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
832 REG_READ(ah, AR_PHY_AGC_CONTROL) |
833 AR_PHY_AGC_CONTROL_CAL);
834
835 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
836 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
837 "%s: offset calibration failed to complete in 1ms; "
838 "noisy environment?\n", __func__);
839 return false;
840 }
841
842 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
843 REG_READ(ah, AR_PHY_AGC_CONTROL) |
844 AR_PHY_AGC_CONTROL_NF);
845
846 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
847
848 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
849 if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
850 INIT_CAL(&ahp->ah_adcGainCalData);
851 INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
852 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
853 "%s: enabling ADC Gain Calibration.\n",
854 __func__);
855 }
856 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
857 INIT_CAL(&ahp->ah_adcDcCalData);
858 INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
859 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
860 "%s: enabling ADC DC Calibration.\n",
861 __func__);
862 }
863 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
864 INIT_CAL(&ahp->ah_iqCalData);
865 INSERT_CAL(ahp, &ahp->ah_iqCalData);
866 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
867 "%s: enabling IQ Calibration.\n",
868 __func__);
869 }
870
871 ahp->ah_cal_list_curr = ahp->ah_cal_list;
872
873 if (ahp->ah_cal_list_curr)
874 ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr);
875 }
876
877 ichan->CalValid = 0;
878
879 return true;
880}
881
882const struct hal_percal_data iq_cal_multi_sample = {
883 IQ_MISMATCH_CAL,
884 MAX_CAL_SAMPLES,
885 PER_MIN_LOG_COUNT,
886 ath9k_hw_iqcal_collect,
887 ath9k_hw_iqcalibrate
888};
889const struct hal_percal_data iq_cal_single_sample = {
890 IQ_MISMATCH_CAL,
891 MIN_CAL_SAMPLES,
892 PER_MAX_LOG_COUNT,
893 ath9k_hw_iqcal_collect,
894 ath9k_hw_iqcalibrate
895};
896const struct hal_percal_data adc_gain_cal_multi_sample = {
897 ADC_GAIN_CAL,
898 MAX_CAL_SAMPLES,
899 PER_MIN_LOG_COUNT,
900 ath9k_hw_adc_gaincal_collect,
901 ath9k_hw_adc_gaincal_calibrate
902};
903const struct hal_percal_data adc_gain_cal_single_sample = {
904 ADC_GAIN_CAL,
905 MIN_CAL_SAMPLES,
906 PER_MAX_LOG_COUNT,
907 ath9k_hw_adc_gaincal_collect,
908 ath9k_hw_adc_gaincal_calibrate
909};
910const struct hal_percal_data adc_dc_cal_multi_sample = {
911 ADC_DC_CAL,
912 MAX_CAL_SAMPLES,
913 PER_MIN_LOG_COUNT,
914 ath9k_hw_adc_dccal_collect,
915 ath9k_hw_adc_dccal_calibrate
916};
917const struct hal_percal_data adc_dc_cal_single_sample = {
918 ADC_DC_CAL,
919 MIN_CAL_SAMPLES,
920 PER_MAX_LOG_COUNT,
921 ath9k_hw_adc_dccal_collect,
922 ath9k_hw_adc_dccal_calibrate
923};
924const struct hal_percal_data adc_init_dc_cal = {
925 ADC_DC_INIT_CAL,
926 MIN_CAL_SAMPLES,
927 INIT_LOG_COUNT,
928 ath9k_hw_adc_dccal_collect,
929 ath9k_hw_adc_dccal_calibrate
930};
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
new file mode 100644
index 000000000000..f5fd03c0edd7
--- /dev/null
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -0,0 +1,1605 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "core.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21
22static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
23 u32 reg, u32 mask,
24 u32 shift, u32 val)
25{
26 u32 regVal;
27
28 regVal = REG_READ(ah, reg) & ~mask;
29 regVal |= (val << shift) & mask;
30
31 REG_WRITE(ah, reg, regVal);
32
33 if (ah->ah_config.analog_shiftreg)
34 udelay(100);
35
36 return;
37}
38
39static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
40{
41
42 if (fbin == AR5416_BCHAN_UNUSED)
43 return fbin;
44
45 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
46}
47
48static inline int16_t ath9k_hw_interpolate(u16 target,
49 u16 srcLeft, u16 srcRight,
50 int16_t targetLeft,
51 int16_t targetRight)
52{
53 int16_t rv;
54
55 if (srcRight == srcLeft) {
56 rv = targetLeft;
57 } else {
58 rv = (int16_t) (((target - srcLeft) * targetRight +
59 (srcRight - target) * targetLeft) /
60 (srcRight - srcLeft));
61 }
62 return rv;
63}
64
65static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList,
66 u16 listSize, u16 *indexL,
67 u16 *indexR)
68{
69 u16 i;
70
71 if (target <= pList[0]) {
72 *indexL = *indexR = 0;
73 return true;
74 }
75 if (target >= pList[listSize - 1]) {
76 *indexL = *indexR = (u16) (listSize - 1);
77 return true;
78 }
79
80 for (i = 0; i < listSize - 1; i++) {
81 if (pList[i] == target) {
82 *indexL = *indexR = i;
83 return true;
84 }
85 if (target < pList[i + 1]) {
86 *indexL = i;
87 *indexR = (u16) (i + 1);
88 return false;
89 }
90 }
91 return false;
92}
93
94static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off, u16 *data)
95{
96 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
97
98 if (!ath9k_hw_wait(ah,
99 AR_EEPROM_STATUS_DATA,
100 AR_EEPROM_STATUS_DATA_BUSY |
101 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
102 return false;
103 }
104
105 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
106 AR_EEPROM_STATUS_DATA_VAL);
107
108 return true;
109}
110
111static int ath9k_hw_flash_map(struct ath_hal *ah)
112{
113 struct ath_hal_5416 *ahp = AH5416(ah);
114
115 ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
116
117 if (!ahp->ah_cal_mem) {
118 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
119 "%s: cannot remap eeprom region \n", __func__);
120 return -EIO;
121 }
122
123 return 0;
124}
125
126static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off, u16 *data)
127{
128 struct ath_hal_5416 *ahp = AH5416(ah);
129
130 *data = ioread16(ahp->ah_cal_mem + off);
131
132 return true;
133}
134
135static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, u32 off, u16 *data)
136{
137 if (ath9k_hw_use_flash(ah))
138 return ath9k_hw_flash_read(ah, off, data);
139 else
140 return ath9k_hw_eeprom_read(ah, off, data);
141}
142
143static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
144{
145 struct ath_hal_5416 *ahp = AH5416(ah);
146 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
147 u16 *eep_data;
148 int addr, ar5416_eep_start_loc = 0;
149
150 if (!ath9k_hw_use_flash(ah)) {
151 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
152 "%s: Reading from EEPROM, not flash\n", __func__);
153 ar5416_eep_start_loc = 256;
154 }
155
156 if (AR_SREV_9100(ah))
157 ar5416_eep_start_loc = 256;
158
159 eep_data = (u16 *)eep;
160
161 for (addr = 0; addr < sizeof(struct ar5416_eeprom) / sizeof(u16); addr++) {
162 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
163 eep_data)) {
164 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
165 "%s: Unable to read eeprom region \n",
166 __func__);
167 return false;
168 }
169 eep_data++;
170 }
171 return true;
172}
173
174static int ath9k_hw_check_eeprom(struct ath_hal *ah)
175{
176 struct ath_hal_5416 *ahp = AH5416(ah);
177 struct ar5416_eeprom *eep =
178 (struct ar5416_eeprom *) &ahp->ah_eeprom;
179 u16 *eepdata, temp, magic, magic2;
180 u32 sum = 0, el;
181 bool need_swap = false;
182 int i, addr, size;
183
184 if (!ath9k_hw_use_flash(ah)) {
185 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
186 &magic)) {
187 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
188 "%s: Reading Magic # failed\n", __func__);
189 return false;
190 }
191
192 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
193 __func__, magic);
194
195 if (magic != AR5416_EEPROM_MAGIC) {
196 magic2 = swab16(magic);
197
198 if (magic2 == AR5416_EEPROM_MAGIC) {
199 size = sizeof(struct ar5416_eeprom);
200 need_swap = true;
201 eepdata = (u16 *) (&ahp->ah_eeprom);
202
203 for (addr = 0; addr < size / sizeof(u16); addr++) {
204 temp = swab16(*eepdata);
205 *eepdata = temp;
206 eepdata++;
207
208 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
209 "0x%04X ", *eepdata);
210
211 if (((addr + 1) % 6) == 0)
212 DPRINTF(ah->ah_sc,
213 ATH_DBG_EEPROM, "\n");
214 }
215 } else {
216 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
217 "Invalid EEPROM Magic. "
218 "endianness mismatch.\n");
219 return -EINVAL;
220 }
221 }
222 }
223
224 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
225 need_swap ? "True" : "False");
226
227 if (need_swap)
228 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
229 else
230 el = ahp->ah_eeprom.baseEepHeader.length;
231
232 if (el > sizeof(struct ar5416_eeprom))
233 el = sizeof(struct ar5416_eeprom) / sizeof(u16);
234 else
235 el = el / sizeof(u16);
236
237 eepdata = (u16 *)(&ahp->ah_eeprom);
238
239 for (i = 0; i < el; i++)
240 sum ^= *eepdata++;
241
242 if (need_swap) {
243 u32 integer, j;
244 u16 word;
245
246 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
247 "EEPROM Endianness is not native.. Changing \n");
248
249 word = swab16(eep->baseEepHeader.length);
250 eep->baseEepHeader.length = word;
251
252 word = swab16(eep->baseEepHeader.checksum);
253 eep->baseEepHeader.checksum = word;
254
255 word = swab16(eep->baseEepHeader.version);
256 eep->baseEepHeader.version = word;
257
258 word = swab16(eep->baseEepHeader.regDmn[0]);
259 eep->baseEepHeader.regDmn[0] = word;
260
261 word = swab16(eep->baseEepHeader.regDmn[1]);
262 eep->baseEepHeader.regDmn[1] = word;
263
264 word = swab16(eep->baseEepHeader.rfSilent);
265 eep->baseEepHeader.rfSilent = word;
266
267 word = swab16(eep->baseEepHeader.blueToothOptions);
268 eep->baseEepHeader.blueToothOptions = word;
269
270 word = swab16(eep->baseEepHeader.deviceCap);
271 eep->baseEepHeader.deviceCap = word;
272
273 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
274 struct modal_eep_header *pModal =
275 &eep->modalHeader[j];
276 integer = swab32(pModal->antCtrlCommon);
277 pModal->antCtrlCommon = integer;
278
279 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
280 integer = swab32(pModal->antCtrlChain[i]);
281 pModal->antCtrlChain[i] = integer;
282 }
283
284 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
285 word = swab16(pModal->spurChans[i].spurChan);
286 pModal->spurChans[i].spurChan = word;
287 }
288 }
289 }
290
291 if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
292 ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
293 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
294 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
295 sum, ar5416_get_eep_ver(ahp));
296 return -EINVAL;
297 }
298
299 return 0;
300}
301
302static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
303 u8 *pVpdList, u16 numIntercepts,
304 u8 *pRetVpdList)
305{
306 u16 i, k;
307 u8 currPwr = pwrMin;
308 u16 idxL = 0, idxR = 0;
309
310 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
311 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
312 numIntercepts, &(idxL),
313 &(idxR));
314 if (idxR < 1)
315 idxR = 1;
316 if (idxL == numIntercepts - 1)
317 idxL = (u16) (numIntercepts - 2);
318 if (pPwrList[idxL] == pPwrList[idxR])
319 k = pVpdList[idxL];
320 else
321 k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
322 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
323 (pPwrList[idxR] - pPwrList[idxL]));
324 pRetVpdList[i] = (u8) k;
325 currPwr += 2;
326 }
327
328 return true;
329}
330
331static void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
332 struct ath9k_channel *chan,
333 struct cal_data_per_freq *pRawDataSet,
334 u8 *bChans, u16 availPiers,
335 u16 tPdGainOverlap, int16_t *pMinCalPower,
336 u16 *pPdGainBoundaries, u8 *pPDADCValues,
337 u16 numXpdGains)
338{
339 int i, j, k;
340 int16_t ss;
341 u16 idxL = 0, idxR = 0, numPiers;
342 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
343 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
344 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
345 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
346 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
347 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
348
349 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
350 u8 minPwrT4[AR5416_NUM_PD_GAINS];
351 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
352 int16_t vpdStep;
353 int16_t tmpVal;
354 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
355 bool match;
356 int16_t minDelta = 0;
357 struct chan_centers centers;
358
359 ath9k_hw_get_channel_centers(ah, chan, &centers);
360
361 for (numPiers = 0; numPiers < availPiers; numPiers++) {
362 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
363 break;
364 }
365
366 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
367 IS_CHAN_2GHZ(chan)),
368 bChans, numPiers, &idxL, &idxR);
369
370 if (match) {
371 for (i = 0; i < numXpdGains; i++) {
372 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
373 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
374 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
375 pRawDataSet[idxL].pwrPdg[i],
376 pRawDataSet[idxL].vpdPdg[i],
377 AR5416_PD_GAIN_ICEPTS,
378 vpdTableI[i]);
379 }
380 } else {
381 for (i = 0; i < numXpdGains; i++) {
382 pVpdL = pRawDataSet[idxL].vpdPdg[i];
383 pPwrL = pRawDataSet[idxL].pwrPdg[i];
384 pVpdR = pRawDataSet[idxR].vpdPdg[i];
385 pPwrR = pRawDataSet[idxR].pwrPdg[i];
386
387 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
388
389 maxPwrT4[i] =
390 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
391 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
392
393
394 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
395 pPwrL, pVpdL,
396 AR5416_PD_GAIN_ICEPTS,
397 vpdTableL[i]);
398 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
399 pPwrR, pVpdR,
400 AR5416_PD_GAIN_ICEPTS,
401 vpdTableR[i]);
402
403 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
404 vpdTableI[i][j] =
405 (u8)(ath9k_hw_interpolate((u16)
406 FREQ2FBIN(centers.
407 synth_center,
408 IS_CHAN_2GHZ
409 (chan)),
410 bChans[idxL], bChans[idxR],
411 vpdTableL[i][j], vpdTableR[i][j]));
412 }
413 }
414 }
415
416 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
417
418 k = 0;
419
420 for (i = 0; i < numXpdGains; i++) {
421 if (i == (numXpdGains - 1))
422 pPdGainBoundaries[i] =
423 (u16)(maxPwrT4[i] / 2);
424 else
425 pPdGainBoundaries[i] =
426 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
427
428 pPdGainBoundaries[i] =
429 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
430
431 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
432 minDelta = pPdGainBoundaries[0] - 23;
433 pPdGainBoundaries[0] = 23;
434 } else {
435 minDelta = 0;
436 }
437
438 if (i == 0) {
439 if (AR_SREV_9280_10_OR_LATER(ah))
440 ss = (int16_t)(0 - (minPwrT4[i] / 2));
441 else
442 ss = 0;
443 } else {
444 ss = (int16_t)((pPdGainBoundaries[i - 1] -
445 (minPwrT4[i] / 2)) -
446 tPdGainOverlap + 1 + minDelta);
447 }
448 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
449 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
450
451 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
452 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
453 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
454 ss++;
455 }
456
457 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
458 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
459 (minPwrT4[i] / 2));
460 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
461 tgtIndex : sizeCurrVpdTable;
462
463 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
464 pPDADCValues[k++] = vpdTableI[i][ss++];
465 }
466
467 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
468 vpdTableI[i][sizeCurrVpdTable - 2]);
469 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
470
471 if (tgtIndex > maxIndex) {
472 while ((ss <= tgtIndex) &&
473 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
474 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
475 (ss - maxIndex + 1) * vpdStep));
476 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
477 255 : tmpVal);
478 ss++;
479 }
480 }
481 }
482
483 while (i < AR5416_PD_GAINS_IN_MASK) {
484 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
485 i++;
486 }
487
488 while (k < AR5416_NUM_PDADC_VALUES) {
489 pPDADCValues[k] = pPDADCValues[k - 1];
490 k++;
491 }
492
493 return;
494}
495
496static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
497 struct ath9k_channel *chan,
498 struct cal_target_power_leg *powInfo,
499 u16 numChannels,
500 struct cal_target_power_leg *pNewPower,
501 u16 numRates, bool isExtTarget)
502{
503 struct chan_centers centers;
504 u16 clo, chi;
505 int i;
506 int matchIndex = -1, lowIndex = -1;
507 u16 freq;
508
509 ath9k_hw_get_channel_centers(ah, chan, &centers);
510 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
511
512 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
513 IS_CHAN_2GHZ(chan))) {
514 matchIndex = 0;
515 } else {
516 for (i = 0; (i < numChannels) &&
517 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
518 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
519 IS_CHAN_2GHZ(chan))) {
520 matchIndex = i;
521 break;
522 } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
523 IS_CHAN_2GHZ(chan))) &&
524 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
525 IS_CHAN_2GHZ(chan)))) {
526 lowIndex = i - 1;
527 break;
528 }
529 }
530 if ((matchIndex == -1) && (lowIndex == -1))
531 matchIndex = i - 1;
532 }
533
534 if (matchIndex != -1) {
535 *pNewPower = powInfo[matchIndex];
536 } else {
537 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
538 IS_CHAN_2GHZ(chan));
539 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
540 IS_CHAN_2GHZ(chan));
541
542 for (i = 0; i < numRates; i++) {
543 pNewPower->tPow2x[i] =
544 (u8)ath9k_hw_interpolate(freq, clo, chi,
545 powInfo[lowIndex].tPow2x[i],
546 powInfo[lowIndex + 1].tPow2x[i]);
547 }
548 }
549}
550
551static void ath9k_hw_get_target_powers(struct ath_hal *ah,
552 struct ath9k_channel *chan,
553 struct cal_target_power_ht *powInfo,
554 u16 numChannels,
555 struct cal_target_power_ht *pNewPower,
556 u16 numRates, bool isHt40Target)
557{
558 struct chan_centers centers;
559 u16 clo, chi;
560 int i;
561 int matchIndex = -1, lowIndex = -1;
562 u16 freq;
563
564 ath9k_hw_get_channel_centers(ah, chan, &centers);
565 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
566
567 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
568 matchIndex = 0;
569 } else {
570 for (i = 0; (i < numChannels) &&
571 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
572 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
573 IS_CHAN_2GHZ(chan))) {
574 matchIndex = i;
575 break;
576 } else
577 if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
578 IS_CHAN_2GHZ(chan))) &&
579 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
580 IS_CHAN_2GHZ(chan)))) {
581 lowIndex = i - 1;
582 break;
583 }
584 }
585 if ((matchIndex == -1) && (lowIndex == -1))
586 matchIndex = i - 1;
587 }
588
589 if (matchIndex != -1) {
590 *pNewPower = powInfo[matchIndex];
591 } else {
592 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
593 IS_CHAN_2GHZ(chan));
594 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
595 IS_CHAN_2GHZ(chan));
596
597 for (i = 0; i < numRates; i++) {
598 pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
599 clo, chi,
600 powInfo[lowIndex].tPow2x[i],
601 powInfo[lowIndex + 1].tPow2x[i]);
602 }
603 }
604}
605
606static u16 ath9k_hw_get_max_edge_power(u16 freq,
607 struct cal_ctl_edges *pRdEdgesPower,
608 bool is2GHz)
609{
610 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
611 int i;
612
613 for (i = 0; (i < AR5416_NUM_BAND_EDGES) &&
614 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
615 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
616 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
617 break;
618 } else if ((i > 0) &&
619 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
620 is2GHz))) {
621 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
622 is2GHz) < freq &&
623 pRdEdgesPower[i - 1].flag) {
624 twiceMaxEdgePower =
625 pRdEdgesPower[i - 1].tPower;
626 }
627 break;
628 }
629 }
630
631 return twiceMaxEdgePower;
632}
633
634int ath9k_hw_set_txpower(struct ath_hal *ah,
635 struct ath9k_channel *chan,
636 u16 cfgCtl,
637 u8 twiceAntennaReduction,
638 u8 twiceMaxRegulatoryPower,
639 u8 powerLimit)
640{
641 struct ath_hal_5416 *ahp = AH5416(ah);
642 struct ar5416_eeprom *pEepData = &ahp->ah_eeprom;
643 struct modal_eep_header *pModal =
644 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
645 int16_t ratesArray[Ar5416RateSize];
646 int16_t txPowerIndexOffset = 0;
647 u8 ht40PowerIncForPdadc = 2;
648 int i;
649
650 memset(ratesArray, 0, sizeof(ratesArray));
651
652 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
653 AR5416_EEP_MINOR_VER_2) {
654 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
655 }
656
657 if (!ath9k_hw_set_power_per_rate_table(ah, chan,
658 &ratesArray[0], cfgCtl,
659 twiceAntennaReduction,
660 twiceMaxRegulatoryPower,
661 powerLimit)) {
662 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
663 "ath9k_hw_set_txpower: unable to set "
664 "tx power per rate table\n");
665 return -EIO;
666 }
667
668 if (!ath9k_hw_set_power_cal_table(ah, chan, &txPowerIndexOffset)) {
669 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
670 "ath9k_hw_set_txpower: unable to set power table\n");
671 return -EIO;
672 }
673
674 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
675 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
676 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
677 ratesArray[i] = AR5416_MAX_RATE_POWER;
678 }
679
680 if (AR_SREV_9280_10_OR_LATER(ah)) {
681 for (i = 0; i < Ar5416RateSize; i++)
682 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
683 }
684
685 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
686 ATH9K_POW_SM(ratesArray[rate18mb], 24)
687 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
688 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
689 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
690 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
691 ATH9K_POW_SM(ratesArray[rate54mb], 24)
692 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
693 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
694 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
695
696 if (IS_CHAN_2GHZ(chan)) {
697 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
698 ATH9K_POW_SM(ratesArray[rate2s], 24)
699 | ATH9K_POW_SM(ratesArray[rate2l], 16)
700 | ATH9K_POW_SM(ratesArray[rateXr], 8)
701 | ATH9K_POW_SM(ratesArray[rate1l], 0));
702 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
703 ATH9K_POW_SM(ratesArray[rate11s], 24)
704 | ATH9K_POW_SM(ratesArray[rate11l], 16)
705 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
706 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
707 }
708
709 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
710 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
711 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
712 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
713 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
714 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
715 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
716 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
717 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
718 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
719
720 if (IS_CHAN_HT40(chan)) {
721 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
722 ATH9K_POW_SM(ratesArray[rateHt40_3] +
723 ht40PowerIncForPdadc, 24)
724 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
725 ht40PowerIncForPdadc, 16)
726 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
727 ht40PowerIncForPdadc, 8)
728 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
729 ht40PowerIncForPdadc, 0));
730 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
731 ATH9K_POW_SM(ratesArray[rateHt40_7] +
732 ht40PowerIncForPdadc, 24)
733 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
734 ht40PowerIncForPdadc, 16)
735 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
736 ht40PowerIncForPdadc, 8)
737 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
738 ht40PowerIncForPdadc, 0));
739
740 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
741 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
742 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
743 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
744 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
745 }
746
747 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
748 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
749 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
750
751 i = rate6mb;
752
753 if (IS_CHAN_HT40(chan))
754 i = rateHt40_0;
755 else if (IS_CHAN_HT20(chan))
756 i = rateHt20_0;
757
758 if (AR_SREV_9280_10_OR_LATER(ah))
759 ah->ah_maxPowerLevel =
760 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
761 else
762 ah->ah_maxPowerLevel = ratesArray[i];
763
764 return 0;
765}
766
767void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan)
768{
769 struct modal_eep_header *pModal;
770 struct ath_hal_5416 *ahp = AH5416(ah);
771 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
772 u8 biaslevel;
773
774 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
775 return;
776
777 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
778 return;
779
780 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
781
782 if (pModal->xpaBiasLvl != 0xff) {
783 biaslevel = pModal->xpaBiasLvl;
784 } else {
785 u16 resetFreqBin, freqBin, freqCount = 0;
786 struct chan_centers centers;
787
788 ath9k_hw_get_channel_centers(ah, chan, &centers);
789
790 resetFreqBin = FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
791 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
792 biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
793
794 freqCount++;
795
796 while (freqCount < 3) {
797 if (pModal->xpaBiasLvlFreq[freqCount] == 0x0)
798 break;
799
800 freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
801 if (resetFreqBin >= freqBin) {
802 biaslevel = (u8)(pModal->xpaBiasLvlFreq[freqCount] >> 14);
803 } else {
804 break;
805 }
806 freqCount++;
807 }
808 }
809
810 if (IS_CHAN_2GHZ(chan)) {
811 INI_RA(&ahp->ah_iniAddac, 7, 1) =
812 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
813 } else {
814 INI_RA(&ahp->ah_iniAddac, 6, 1) =
815 (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel << 6;
816 }
817}
818
819bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
820 struct ath9k_channel *chan,
821 int16_t *ratesArray,
822 u16 cfgCtl,
823 u8 AntennaReduction,
824 u8 twiceMaxRegulatoryPower,
825 u8 powerLimit)
826{
827 struct ath_hal_5416 *ahp = AH5416(ah);
828 struct ar5416_eeprom *pEepData = &ahp->ah_eeprom;
829 u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
830 static const u16 tpScaleReductionTable[5] =
831 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
832
833 int i;
834 int8_t twiceLargestAntenna;
835 struct cal_ctl_data *rep;
836 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
837 0, { 0, 0, 0, 0}
838 };
839 struct cal_target_power_leg targetPowerOfdmExt = {
840 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
841 0, { 0, 0, 0, 0 }
842 };
843 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
844 0, {0, 0, 0, 0}
845 };
846 u8 scaledPower = 0, minCtlPower, maxRegAllowedPower;
847 u16 ctlModesFor11a[] =
848 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
849 u16 ctlModesFor11g[] =
850 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
851 CTL_2GHT40
852 };
853 u16 numCtlModes, *pCtlMode, ctlMode, freq;
854 struct chan_centers centers;
855 int tx_chainmask;
856 u8 twiceMinEdgePower;
857
858 tx_chainmask = ahp->ah_txchainmask;
859
860 ath9k_hw_get_channel_centers(ah, chan, &centers);
861
862 twiceLargestAntenna = max(
863 pEepData->modalHeader
864 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
865 pEepData->modalHeader
866 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
867
868 twiceLargestAntenna = max((u8)twiceLargestAntenna,
869 pEepData->modalHeader
870 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
871
872 twiceLargestAntenna = (int8_t)min(AntennaReduction - twiceLargestAntenna, 0);
873
874 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
875
876 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
877 maxRegAllowedPower -=
878 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
879 }
880
881 scaledPower = min(powerLimit, maxRegAllowedPower);
882
883 switch (ar5416_get_ntxchains(tx_chainmask)) {
884 case 1:
885 break;
886 case 2:
887 scaledPower -=
888 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
889 break;
890 case 3:
891 scaledPower -=
892 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
893 break;
894 }
895
896 scaledPower = max(0, (int32_t) scaledPower);
897
898 if (IS_CHAN_2GHZ(chan)) {
899 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
900 SUB_NUM_CTL_MODES_AT_2G_40;
901 pCtlMode = ctlModesFor11g;
902
903 ath9k_hw_get_legacy_target_powers(ah, chan,
904 pEepData->calTargetPowerCck,
905 AR5416_NUM_2G_CCK_TARGET_POWERS,
906 &targetPowerCck, 4, false);
907 ath9k_hw_get_legacy_target_powers(ah, chan,
908 pEepData->calTargetPower2G,
909 AR5416_NUM_2G_20_TARGET_POWERS,
910 &targetPowerOfdm, 4, false);
911 ath9k_hw_get_target_powers(ah, chan,
912 pEepData->calTargetPower2GHT20,
913 AR5416_NUM_2G_20_TARGET_POWERS,
914 &targetPowerHt20, 8, false);
915
916 if (IS_CHAN_HT40(chan)) {
917 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
918 ath9k_hw_get_target_powers(ah, chan,
919 pEepData->calTargetPower2GHT40,
920 AR5416_NUM_2G_40_TARGET_POWERS,
921 &targetPowerHt40, 8, true);
922 ath9k_hw_get_legacy_target_powers(ah, chan,
923 pEepData->calTargetPowerCck,
924 AR5416_NUM_2G_CCK_TARGET_POWERS,
925 &targetPowerCckExt, 4, true);
926 ath9k_hw_get_legacy_target_powers(ah, chan,
927 pEepData->calTargetPower2G,
928 AR5416_NUM_2G_20_TARGET_POWERS,
929 &targetPowerOfdmExt, 4, true);
930 }
931 } else {
932 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
933 SUB_NUM_CTL_MODES_AT_5G_40;
934 pCtlMode = ctlModesFor11a;
935
936 ath9k_hw_get_legacy_target_powers(ah, chan,
937 pEepData->calTargetPower5G,
938 AR5416_NUM_5G_20_TARGET_POWERS,
939 &targetPowerOfdm, 4, false);
940 ath9k_hw_get_target_powers(ah, chan,
941 pEepData->calTargetPower5GHT20,
942 AR5416_NUM_5G_20_TARGET_POWERS,
943 &targetPowerHt20, 8, false);
944
945 if (IS_CHAN_HT40(chan)) {
946 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
947 ath9k_hw_get_target_powers(ah, chan,
948 pEepData->calTargetPower5GHT40,
949 AR5416_NUM_5G_40_TARGET_POWERS,
950 &targetPowerHt40, 8, true);
951 ath9k_hw_get_legacy_target_powers(ah, chan,
952 pEepData->calTargetPower5G,
953 AR5416_NUM_5G_20_TARGET_POWERS,
954 &targetPowerOfdmExt, 4, true);
955 }
956 }
957
958 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
959 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
960 (pCtlMode[ctlMode] == CTL_2GHT40);
961 if (isHt40CtlMode)
962 freq = centers.synth_center;
963 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
964 freq = centers.ext_center;
965 else
966 freq = centers.ctl_center;
967
968 if (ar5416_get_eep_ver(ahp) == 14 && ar5416_get_eep_rev(ahp) <= 2)
969 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
970
971 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
972 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
973 "EXT_ADDITIVE %d\n",
974 ctlMode, numCtlModes, isHt40CtlMode,
975 (pCtlMode[ctlMode] & EXT_ADDITIVE));
976
977 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
978 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
979 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
980 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
981 "chan %d\n",
982 i, cfgCtl, pCtlMode[ctlMode],
983 pEepData->ctlIndex[i], chan->channel);
984
985 if ((((cfgCtl & ~CTL_MODE_M) |
986 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
987 pEepData->ctlIndex[i]) ||
988 (((cfgCtl & ~CTL_MODE_M) |
989 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
990 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
991 rep = &(pEepData->ctlData[i]);
992
993 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
994 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
995 IS_CHAN_2GHZ(chan));
996
997 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
998 " MATCH-EE_IDX %d: ch %d is2 %d "
999 "2xMinEdge %d chainmask %d chains %d\n",
1000 i, freq, IS_CHAN_2GHZ(chan),
1001 twiceMinEdgePower, tx_chainmask,
1002 ar5416_get_ntxchains
1003 (tx_chainmask));
1004 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1005 twiceMaxEdgePower = min(twiceMaxEdgePower,
1006 twiceMinEdgePower);
1007 } else {
1008 twiceMaxEdgePower = twiceMinEdgePower;
1009 break;
1010 }
1011 }
1012 }
1013
1014 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1015
1016 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1017 " SEL-Min ctlMode %d pCtlMode %d "
1018 "2xMaxEdge %d sP %d minCtlPwr %d\n",
1019 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
1020 scaledPower, minCtlPower);
1021
1022 switch (pCtlMode[ctlMode]) {
1023 case CTL_11B:
1024 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1025 targetPowerCck.tPow2x[i] =
1026 min(targetPowerCck.tPow2x[i],
1027 minCtlPower);
1028 }
1029 break;
1030 case CTL_11A:
1031 case CTL_11G:
1032 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1033 targetPowerOfdm.tPow2x[i] =
1034 min(targetPowerOfdm.tPow2x[i],
1035 minCtlPower);
1036 }
1037 break;
1038 case CTL_5GHT20:
1039 case CTL_2GHT20:
1040 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1041 targetPowerHt20.tPow2x[i] =
1042 min(targetPowerHt20.tPow2x[i],
1043 minCtlPower);
1044 }
1045 break;
1046 case CTL_11B_EXT:
1047 targetPowerCckExt.tPow2x[0] =
1048 min(targetPowerCckExt.tPow2x[0], minCtlPower);
1049 break;
1050 case CTL_11A_EXT:
1051 case CTL_11G_EXT:
1052 targetPowerOfdmExt.tPow2x[0] =
1053 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
1054 break;
1055 case CTL_5GHT40:
1056 case CTL_2GHT40:
1057 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1058 targetPowerHt40.tPow2x[i] =
1059 min(targetPowerHt40.tPow2x[i],
1060 minCtlPower);
1061 }
1062 break;
1063 default:
1064 break;
1065 }
1066 }
1067
1068 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1069 ratesArray[rate18mb] = ratesArray[rate24mb] =
1070 targetPowerOfdm.tPow2x[0];
1071 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1072 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1073 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1074 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1075
1076 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1077 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1078
1079 if (IS_CHAN_2GHZ(chan)) {
1080 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1081 ratesArray[rate2s] = ratesArray[rate2l] =
1082 targetPowerCck.tPow2x[1];
1083 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1084 targetPowerCck.tPow2x[2];
1085 ;
1086 ratesArray[rate11s] = ratesArray[rate11l] =
1087 targetPowerCck.tPow2x[3];
1088 ;
1089 }
1090 if (IS_CHAN_HT40(chan)) {
1091 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1092 ratesArray[rateHt40_0 + i] =
1093 targetPowerHt40.tPow2x[i];
1094 }
1095 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1096 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1097 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1098 if (IS_CHAN_2GHZ(chan)) {
1099 ratesArray[rateExtCck] =
1100 targetPowerCckExt.tPow2x[0];
1101 }
1102 }
1103 return true;
1104}
1105
1106bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
1107 struct ath9k_channel *chan,
1108 int16_t *pTxPowerIndexOffset)
1109{
1110 struct ath_hal_5416 *ahp = AH5416(ah);
1111 struct ar5416_eeprom *pEepData = &ahp->ah_eeprom;
1112 struct cal_data_per_freq *pRawDataset;
1113 u8 *pCalBChans = NULL;
1114 u16 pdGainOverlap_t2;
1115 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
1116 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
1117 u16 numPiers, i, j;
1118 int16_t tMinCalPower;
1119 u16 numXpdGain, xpdMask;
1120 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
1121 u32 reg32, regOffset, regChainOffset;
1122 int16_t modalIdx;
1123
1124 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
1125 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
1126
1127 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1128 AR5416_EEP_MINOR_VER_2) {
1129 pdGainOverlap_t2 =
1130 pEepData->modalHeader[modalIdx].pdGainOverlap;
1131 } else {
1132 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
1133 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
1134 }
1135
1136 if (IS_CHAN_2GHZ(chan)) {
1137 pCalBChans = pEepData->calFreqPier2G;
1138 numPiers = AR5416_NUM_2G_CAL_PIERS;
1139 } else {
1140 pCalBChans = pEepData->calFreqPier5G;
1141 numPiers = AR5416_NUM_5G_CAL_PIERS;
1142 }
1143
1144 numXpdGain = 0;
1145
1146 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
1147 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
1148 if (numXpdGain >= AR5416_NUM_PD_GAINS)
1149 break;
1150 xpdGainValues[numXpdGain] =
1151 (u16)(AR5416_PD_GAINS_IN_MASK - i);
1152 numXpdGain++;
1153 }
1154 }
1155
1156 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
1157 (numXpdGain - 1) & 0x3);
1158 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
1159 xpdGainValues[0]);
1160 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
1161 xpdGainValues[1]);
1162 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
1163 xpdGainValues[2]);
1164
1165 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1166 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1167 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) &&
1168 (i != 0)) {
1169 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1170 } else
1171 regChainOffset = i * 0x1000;
1172
1173 if (pEepData->baseEepHeader.txMask & (1 << i)) {
1174 if (IS_CHAN_2GHZ(chan))
1175 pRawDataset = pEepData->calPierData2G[i];
1176 else
1177 pRawDataset = pEepData->calPierData5G[i];
1178
1179 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
1180 pRawDataset, pCalBChans,
1181 numPiers, pdGainOverlap_t2,
1182 &tMinCalPower, gainBoundaries,
1183 pdadcValues, numXpdGain);
1184
1185 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
1186 REG_WRITE(ah,
1187 AR_PHY_TPCRG5 + regChainOffset,
1188 SM(pdGainOverlap_t2,
1189 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
1190 | SM(gainBoundaries[0],
1191 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
1192 | SM(gainBoundaries[1],
1193 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
1194 | SM(gainBoundaries[2],
1195 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
1196 | SM(gainBoundaries[3],
1197 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1198 }
1199
1200 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
1201 for (j = 0; j < 32; j++) {
1202 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
1203 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
1204 ((pdadcValues[4 * j + 2] & 0xFF) << 16) |
1205 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
1206 REG_WRITE(ah, regOffset, reg32);
1207
1208 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
1209 "PDADC (%d,%4x): %4.4x %8.8x\n",
1210 i, regChainOffset, regOffset,
1211 reg32);
1212 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
1213 "PDADC: Chain %d | PDADC %3d Value %3d | "
1214 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
1215 "PDADC %3d Value %3d |\n",
1216 i, 4 * j, pdadcValues[4 * j],
1217 4 * j + 1, pdadcValues[4 * j + 1],
1218 4 * j + 2, pdadcValues[4 * j + 2],
1219 4 * j + 3,
1220 pdadcValues[4 * j + 3]);
1221
1222 regOffset += 4;
1223 }
1224 }
1225 }
1226
1227 *pTxPowerIndexOffset = 0;
1228
1229 return true;
1230}
1231
1232/* XXX: Clean me up, make me more legible */
1233bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
1234 struct ath9k_channel *chan)
1235{
1236 struct modal_eep_header *pModal;
1237 struct ath_hal_5416 *ahp = AH5416(ah);
1238 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1239 int i, regChainOffset;
1240 u8 txRxAttenLocal;
1241 u16 ant_config;
1242
1243 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1244
1245 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
1246
1247 ath9k_hw_get_eeprom_antenna_cfg(ah, chan, 1, &ant_config);
1248 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
1249
1250 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1251 if (AR_SREV_9280(ah)) {
1252 if (i >= 2)
1253 break;
1254 }
1255
1256 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1257 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
1258 && (i != 0))
1259 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1260 else
1261 regChainOffset = i * 0x1000;
1262
1263 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1264 pModal->antCtrlChain[i]);
1265
1266 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1267 (REG_READ(ah,
1268 AR_PHY_TIMING_CTRL4(0) +
1269 regChainOffset) &
1270 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1271 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1272 SM(pModal->iqCalICh[i],
1273 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1274 SM(pModal->iqCalQCh[i],
1275 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1276
1277 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
1278 if ((eep->baseEepHeader.version &
1279 AR5416_EEP_VER_MINOR_MASK) >=
1280 AR5416_EEP_MINOR_VER_3) {
1281 txRxAttenLocal = pModal->txRxAttenCh[i];
1282 if (AR_SREV_9280_10_OR_LATER(ah)) {
1283 REG_RMW_FIELD(ah,
1284 AR_PHY_GAIN_2GHZ +
1285 regChainOffset,
1286 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1287 pModal->
1288 bswMargin[i]);
1289 REG_RMW_FIELD(ah,
1290 AR_PHY_GAIN_2GHZ +
1291 regChainOffset,
1292 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1293 pModal->
1294 bswAtten[i]);
1295 REG_RMW_FIELD(ah,
1296 AR_PHY_GAIN_2GHZ +
1297 regChainOffset,
1298 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1299 pModal->
1300 xatten2Margin[i]);
1301 REG_RMW_FIELD(ah,
1302 AR_PHY_GAIN_2GHZ +
1303 regChainOffset,
1304 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1305 pModal->
1306 xatten2Db[i]);
1307 } else {
1308 REG_WRITE(ah,
1309 AR_PHY_GAIN_2GHZ +
1310 regChainOffset,
1311 (REG_READ(ah,
1312 AR_PHY_GAIN_2GHZ +
1313 regChainOffset) &
1314 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1315 | SM(pModal->
1316 bswMargin[i],
1317 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1318 REG_WRITE(ah,
1319 AR_PHY_GAIN_2GHZ +
1320 regChainOffset,
1321 (REG_READ(ah,
1322 AR_PHY_GAIN_2GHZ +
1323 regChainOffset) &
1324 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1325 | SM(pModal->bswAtten[i],
1326 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1327 }
1328 }
1329 if (AR_SREV_9280_10_OR_LATER(ah)) {
1330 REG_RMW_FIELD(ah,
1331 AR_PHY_RXGAIN +
1332 regChainOffset,
1333 AR9280_PHY_RXGAIN_TXRX_ATTEN,
1334 txRxAttenLocal);
1335 REG_RMW_FIELD(ah,
1336 AR_PHY_RXGAIN +
1337 regChainOffset,
1338 AR9280_PHY_RXGAIN_TXRX_MARGIN,
1339 pModal->rxTxMarginCh[i]);
1340 } else {
1341 REG_WRITE(ah,
1342 AR_PHY_RXGAIN + regChainOffset,
1343 (REG_READ(ah,
1344 AR_PHY_RXGAIN +
1345 regChainOffset) &
1346 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
1347 SM(txRxAttenLocal,
1348 AR_PHY_RXGAIN_TXRX_ATTEN));
1349 REG_WRITE(ah,
1350 AR_PHY_GAIN_2GHZ +
1351 regChainOffset,
1352 (REG_READ(ah,
1353 AR_PHY_GAIN_2GHZ +
1354 regChainOffset) &
1355 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1356 SM(pModal->rxTxMarginCh[i],
1357 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1358 }
1359 }
1360 }
1361
1362 if (AR_SREV_9280_10_OR_LATER(ah)) {
1363 if (IS_CHAN_2GHZ(chan)) {
1364 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1365 AR_AN_RF2G1_CH0_OB,
1366 AR_AN_RF2G1_CH0_OB_S,
1367 pModal->ob);
1368 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1369 AR_AN_RF2G1_CH0_DB,
1370 AR_AN_RF2G1_CH0_DB_S,
1371 pModal->db);
1372 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1373 AR_AN_RF2G1_CH1_OB,
1374 AR_AN_RF2G1_CH1_OB_S,
1375 pModal->ob_ch1);
1376 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1377 AR_AN_RF2G1_CH1_DB,
1378 AR_AN_RF2G1_CH1_DB_S,
1379 pModal->db_ch1);
1380 } else {
1381 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1382 AR_AN_RF5G1_CH0_OB5,
1383 AR_AN_RF5G1_CH0_OB5_S,
1384 pModal->ob);
1385 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1386 AR_AN_RF5G1_CH0_DB5,
1387 AR_AN_RF5G1_CH0_DB5_S,
1388 pModal->db);
1389 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1390 AR_AN_RF5G1_CH1_OB5,
1391 AR_AN_RF5G1_CH1_OB5_S,
1392 pModal->ob_ch1);
1393 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1394 AR_AN_RF5G1_CH1_DB5,
1395 AR_AN_RF5G1_CH1_DB5_S,
1396 pModal->db_ch1);
1397 }
1398 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1399 AR_AN_TOP2_XPABIAS_LVL,
1400 AR_AN_TOP2_XPABIAS_LVL_S,
1401 pModal->xpaBiasLvl);
1402 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1403 AR_AN_TOP2_LOCALBIAS,
1404 AR_AN_TOP2_LOCALBIAS_S,
1405 pModal->local_bias);
1406 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n",
1407 pModal->force_xpaon);
1408 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
1409 pModal->force_xpaon);
1410 }
1411
1412 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1413 pModal->switchSettling);
1414 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1415 pModal->adcDesiredSize);
1416
1417 if (!AR_SREV_9280_10_OR_LATER(ah))
1418 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1419 AR_PHY_DESIRED_SZ_PGA,
1420 pModal->pgaDesiredSize);
1421
1422 REG_WRITE(ah, AR_PHY_RF_CTL4,
1423 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1424 | SM(pModal->txEndToXpaOff,
1425 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1426 | SM(pModal->txFrameToXpaOn,
1427 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1428 | SM(pModal->txFrameToXpaOn,
1429 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1430
1431 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1432 pModal->txEndToRxOn);
1433 if (AR_SREV_9280_10_OR_LATER(ah)) {
1434 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1435 pModal->thresh62);
1436 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1437 AR_PHY_EXT_CCA0_THRESH62,
1438 pModal->thresh62);
1439 } else {
1440 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1441 pModal->thresh62);
1442 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1443 AR_PHY_EXT_CCA_THRESH62,
1444 pModal->thresh62);
1445 }
1446
1447 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1448 AR5416_EEP_MINOR_VER_2) {
1449 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1450 AR_PHY_TX_END_DATA_START,
1451 pModal->txFrameToDataStart);
1452 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1453 pModal->txFrameToPaOn);
1454 }
1455
1456 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1457 AR5416_EEP_MINOR_VER_3) {
1458 if (IS_CHAN_HT40(chan))
1459 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1460 AR_PHY_SETTLING_SWITCH,
1461 pModal->swSettleHt40);
1462 }
1463
1464 return true;
1465}
1466
1467int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
1468 struct ath9k_channel *chan,
1469 u8 index, u16 *config)
1470{
1471 struct ath_hal_5416 *ahp = AH5416(ah);
1472 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1473 struct modal_eep_header *pModal =
1474 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1475 struct base_eep_header *pBase = &eep->baseEepHeader;
1476
1477 switch (index) {
1478 case 0:
1479 *config = pModal->antCtrlCommon & 0xFFFF;
1480 return 0;
1481 case 1:
1482 if (pBase->version >= 0x0E0D) {
1483 if (pModal->useAnt1) {
1484 *config =
1485 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
1486 return 0;
1487 }
1488 }
1489 break;
1490 default:
1491 break;
1492 }
1493
1494 return -EINVAL;
1495}
1496
1497u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
1498 enum ieee80211_band freq_band)
1499{
1500 struct ath_hal_5416 *ahp = AH5416(ah);
1501 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1502 struct modal_eep_header *pModal =
1503 &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]);
1504 struct base_eep_header *pBase = &eep->baseEepHeader;
1505 u8 num_ant_config;
1506
1507 num_ant_config = 1;
1508
1509 if (pBase->version >= 0x0E0D)
1510 if (pModal->useAnt1)
1511 num_ant_config += 1;
1512
1513 return num_ant_config;
1514}
1515
1516u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz)
1517{
1518 struct ath_hal_5416 *ahp = AH5416(ah);
1519 struct ar5416_eeprom *eep =
1520 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1521 u16 spur_val = AR_NO_SPUR;
1522
1523 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1524 "Getting spur idx %d is2Ghz. %d val %x\n",
1525 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
1526
1527 switch (ah->ah_config.spurmode) {
1528 case SPUR_DISABLE:
1529 break;
1530 case SPUR_ENABLE_IOCTL:
1531 spur_val = ah->ah_config.spurchans[i][is2GHz];
1532 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1533 "Getting spur val from new loc. %d\n", spur_val);
1534 break;
1535 case SPUR_ENABLE_EEPROM:
1536 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1537 break;
1538
1539 }
1540
1541 return spur_val;
1542}
1543
1544u32 ath9k_hw_get_eeprom(struct ath_hal *ah,
1545 enum eeprom_param param)
1546{
1547 struct ath_hal_5416 *ahp = AH5416(ah);
1548 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1549 struct modal_eep_header *pModal = eep->modalHeader;
1550 struct base_eep_header *pBase = &eep->baseEepHeader;
1551
1552 switch (param) {
1553 case EEP_NFTHRESH_5:
1554 return -pModal[0].noiseFloorThreshCh[0];
1555 case EEP_NFTHRESH_2:
1556 return -pModal[1].noiseFloorThreshCh[0];
1557 case AR_EEPROM_MAC(0):
1558 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1559 case AR_EEPROM_MAC(1):
1560 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1561 case AR_EEPROM_MAC(2):
1562 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1563 case EEP_REG_0:
1564 return pBase->regDmn[0];
1565 case EEP_REG_1:
1566 return pBase->regDmn[1];
1567 case EEP_OP_CAP:
1568 return pBase->deviceCap;
1569 case EEP_OP_MODE:
1570 return pBase->opCapFlags;
1571 case EEP_RF_SILENT:
1572 return pBase->rfSilent;
1573 case EEP_OB_5:
1574 return pModal[0].ob;
1575 case EEP_DB_5:
1576 return pModal[0].db;
1577 case EEP_OB_2:
1578 return pModal[1].ob;
1579 case EEP_DB_2:
1580 return pModal[1].db;
1581 case EEP_MINOR_REV:
1582 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1583 case EEP_TX_MASK:
1584 return pBase->txMask;
1585 case EEP_RX_MASK:
1586 return pBase->rxMask;
1587 default:
1588 return 0;
1589 }
1590}
1591
1592int ath9k_hw_eeprom_attach(struct ath_hal *ah)
1593{
1594 int status;
1595
1596 if (ath9k_hw_use_flash(ah))
1597 ath9k_hw_flash_map(ah);
1598
1599 if (!ath9k_hw_fill_eeprom(ah))
1600 return -EIO;
1601
1602 status = ath9k_hw_check_eeprom(ah);
1603
1604 return status;
1605}
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 1417ba07523d..e05c9ef55e47 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -23,183 +23,68 @@
23#include "phy.h" 23#include "phy.h"
24#include "initvals.h" 24#include "initvals.h"
25 25
26static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
27static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains);
28static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
29static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
30 u8 numChains);
31static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
32static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
33 u8 numChains);
34
35static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 }; 26static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
36static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
37
38static const struct hal_percal_data iq_cal_multi_sample = {
39 IQ_MISMATCH_CAL,
40 MAX_CAL_SAMPLES,
41 PER_MIN_LOG_COUNT,
42 ath9k_hw_iqcal_collect,
43 ath9k_hw_iqcalibrate
44};
45static const struct hal_percal_data iq_cal_single_sample = {
46 IQ_MISMATCH_CAL,
47 MIN_CAL_SAMPLES,
48 PER_MAX_LOG_COUNT,
49 ath9k_hw_iqcal_collect,
50 ath9k_hw_iqcalibrate
51};
52static const struct hal_percal_data adc_gain_cal_multi_sample = {
53 ADC_GAIN_CAL,
54 MAX_CAL_SAMPLES,
55 PER_MIN_LOG_COUNT,
56 ath9k_hw_adc_gaincal_collect,
57 ath9k_hw_adc_gaincal_calibrate
58};
59static const struct hal_percal_data adc_gain_cal_single_sample = {
60 ADC_GAIN_CAL,
61 MIN_CAL_SAMPLES,
62 PER_MAX_LOG_COUNT,
63 ath9k_hw_adc_gaincal_collect,
64 ath9k_hw_adc_gaincal_calibrate
65};
66static const struct hal_percal_data adc_dc_cal_multi_sample = {
67 ADC_DC_CAL,
68 MAX_CAL_SAMPLES,
69 PER_MIN_LOG_COUNT,
70 ath9k_hw_adc_dccal_collect,
71 ath9k_hw_adc_dccal_calibrate
72};
73static const struct hal_percal_data adc_dc_cal_single_sample = {
74 ADC_DC_CAL,
75 MIN_CAL_SAMPLES,
76 PER_MAX_LOG_COUNT,
77 ath9k_hw_adc_dccal_collect,
78 ath9k_hw_adc_dccal_calibrate
79};
80static const struct hal_percal_data adc_init_dc_cal = {
81 ADC_DC_INIT_CAL,
82 MIN_CAL_SAMPLES,
83 INIT_LOG_COUNT,
84 ath9k_hw_adc_dccal_collect,
85 ath9k_hw_adc_dccal_calibrate
86};
87 27
88static struct ath9k_rate_table ar5416_11a_table = { 28extern struct hal_percal_data iq_cal_multi_sample;
89 8, 29extern struct hal_percal_data iq_cal_single_sample;
90 {0}, 30extern struct hal_percal_data adc_gain_cal_multi_sample;
91 { 31extern struct hal_percal_data adc_gain_cal_single_sample;
92 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0}, 32extern struct hal_percal_data adc_dc_cal_multi_sample;
93 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0}, 33extern struct hal_percal_data adc_dc_cal_single_sample;
94 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2}, 34extern struct hal_percal_data adc_init_dc_cal;
95 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
96 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
97 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
98 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
99 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
100 },
101};
102 35
103static struct ath9k_rate_table ar5416_11b_table = { 36static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
104 4, 37static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
105 {0}, 38 enum ath9k_ht_macmode macmode);
106 { 39static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
107 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0}, 40 struct ar5416_eeprom *pEepData,
108 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1}, 41 u32 reg, u32 value);
109 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1}, 42static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
110 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1} 43static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
111 },
112};
113 44
114static struct ath9k_rate_table ar5416_11g_table = { 45/********************/
115 12, 46/* Helper Functions */
116 {0}, 47/********************/
117 {
118 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
119 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
120 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
121 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
122 48
123 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4}, 49static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
124 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4}, 50{
125 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6}, 51 if (ah->ah_curchan != NULL)
126 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6}, 52 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
127 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8}, 53 else
128 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8}, 54 return clks / CLOCK_RATE[ATH9K_MODE_11B];
129 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8}, 55}
130 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
131 },
132};
133 56
134static struct ath9k_rate_table ar5416_11ng_table = { 57static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
135 28, 58{
136 {0}, 59 struct ath9k_channel *chan = ah->ah_curchan;
137 {
138 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
139 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
140 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
141 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
142 60
143 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4}, 61 if (chan && IS_CHAN_HT40(chan))
144 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4}, 62 return ath9k_hw_mac_usec(ah, clks) / 2;
145 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6}, 63 else
146 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6}, 64 return ath9k_hw_mac_usec(ah, clks);
147 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8}, 65}
148 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
149 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
150 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
151 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
152 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
153 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
154 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
155 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
156 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
157 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
158 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
159 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
160 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
161 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
162 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
163 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
164 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
165 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
166 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
167 },
168};
169 66
170static struct ath9k_rate_table ar5416_11na_table = { 67static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
171 24, 68{
172 {0}, 69 if (ah->ah_curchan != NULL)
173 { 70 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
174 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0}, 71 ah->ah_curchan)];
175 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0}, 72 else
176 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2}, 73 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
177 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2}, 74}
178 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4}, 75
179 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4}, 76static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
180 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4}, 77{
181 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}, 78 struct ath9k_channel *chan = ah->ah_curchan;
182 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0}, 79
183 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2}, 80 if (chan && IS_CHAN_HT40(chan))
184 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2}, 81 return ath9k_hw_mac_clks(ah, usecs) * 2;
185 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4}, 82 else
186 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4}, 83 return ath9k_hw_mac_clks(ah, usecs);
187 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4}, 84}
188 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
189 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
190 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
191 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
192 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
193 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
194 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
195 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
196 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
197 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
198 },
199};
200 85
201static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah, 86enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
202 const struct ath9k_channel *chan) 87 const struct ath9k_channel *chan)
203{ 88{
204 if (IS_CHAN_CCK(chan)) 89 if (IS_CHAN_CCK(chan))
205 return ATH9K_MODE_11A; 90 return ATH9K_MODE_11A;
@@ -208,10 +93,7 @@ static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
208 return ATH9K_MODE_11A; 93 return ATH9K_MODE_11A;
209} 94}
210 95
211static bool ath9k_hw_wait(struct ath_hal *ah, 96bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
212 u32 reg,
213 u32 mask,
214 u32 val)
215{ 97{
216 int i; 98 int i;
217 99
@@ -222,78 +104,10 @@ static bool ath9k_hw_wait(struct ath_hal *ah,
222 udelay(AH_TIME_QUANTUM); 104 udelay(AH_TIME_QUANTUM);
223 } 105 }
224 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, 106 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
225 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 107 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
226 __func__, reg, REG_READ(ah, reg), mask, val); 108 __func__, reg, REG_READ(ah, reg), mask, val);
227 return false;
228}
229
230static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off,
231 u16 *data)
232{
233 (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
234
235 if (!ath9k_hw_wait(ah,
236 AR_EEPROM_STATUS_DATA,
237 AR_EEPROM_STATUS_DATA_BUSY |
238 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
239 return false;
240 }
241
242 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
243 AR_EEPROM_STATUS_DATA_VAL);
244
245 return true;
246}
247
248static int ath9k_hw_flash_map(struct ath_hal *ah)
249{
250 struct ath_hal_5416 *ahp = AH5416(ah);
251
252 ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
253
254 if (!ahp->ah_cal_mem) {
255 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
256 "%s: cannot remap eeprom region \n", __func__);
257 return -EIO;
258 }
259
260 return 0;
261}
262
263static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off,
264 u16 *data)
265{
266 struct ath_hal_5416 *ahp = AH5416(ah);
267
268 *data = ioread16(ahp->ah_cal_mem + off);
269 return true;
270}
271
272static void ath9k_hw_read_revisions(struct ath_hal *ah)
273{
274 u32 val;
275
276 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
277
278 if (val == 0xFF) {
279 val = REG_READ(ah, AR_SREV);
280
281 ah->ah_macVersion =
282 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
283
284 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
285 ah->ah_isPciExpress =
286 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
287
288 } else {
289 if (!AR_SREV_9100(ah))
290 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
291
292 ah->ah_macRev = val & AR_SREV_REVISION;
293 109
294 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) 110 return false;
295 ah->ah_isPciExpress = true;
296 }
297} 111}
298 112
299u32 ath9k_hw_reverse_bits(u32 val, u32 n) 113u32 ath9k_hw_reverse_bits(u32 val, u32 n)
@@ -308,596 +122,215 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n)
308 return retval; 122 return retval;
309} 123}
310 124
311static void ath9k_hw_set_defaults(struct ath_hal *ah) 125bool ath9k_get_channel_edges(struct ath_hal *ah,
126 u16 flags, u16 *low,
127 u16 *high)
312{ 128{
313 int i; 129 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
314
315 ah->ah_config.dma_beacon_response_time = 2;
316 ah->ah_config.sw_beacon_response_time = 10;
317 ah->ah_config.additional_swba_backoff = 0;
318 ah->ah_config.ack_6mb = 0x0;
319 ah->ah_config.cwm_ignore_extcca = 0;
320 ah->ah_config.pcie_powersave_enable = 0;
321 ah->ah_config.pcie_l1skp_enable = 0;
322 ah->ah_config.pcie_clock_req = 0;
323 ah->ah_config.pcie_power_reset = 0x100;
324 ah->ah_config.pcie_restore = 0;
325 ah->ah_config.pcie_waen = 0;
326 ah->ah_config.analog_shiftreg = 1;
327 ah->ah_config.ht_enable = 1;
328 ah->ah_config.ofdm_trig_low = 200;
329 ah->ah_config.ofdm_trig_high = 500;
330 ah->ah_config.cck_trig_high = 200;
331 ah->ah_config.cck_trig_low = 100;
332 ah->ah_config.enable_ani = 1;
333 ah->ah_config.noise_immunity_level = 4;
334 ah->ah_config.ofdm_weaksignal_det = 1;
335 ah->ah_config.cck_weaksignal_thr = 0;
336 ah->ah_config.spur_immunity_level = 2;
337 ah->ah_config.firstep_level = 0;
338 ah->ah_config.rssi_thr_high = 40;
339 ah->ah_config.rssi_thr_low = 7;
340 ah->ah_config.diversity_control = 0;
341 ah->ah_config.antenna_switch_swap = 0;
342 130
343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 131 if (flags & CHANNEL_5GHZ) {
344 ah->ah_config.spurchans[i][0] = AR_NO_SPUR; 132 *low = pCap->low_5ghz_chan;
345 ah->ah_config.spurchans[i][1] = AR_NO_SPUR; 133 *high = pCap->high_5ghz_chan;
134 return true;
346 } 135 }
347 136 if ((flags & CHANNEL_2GHZ)) {
348 ah->ah_config.intr_mitigation = 1; 137 *low = pCap->low_2ghz_chan;
349} 138 *high = pCap->high_2ghz_chan;
350 139 return true;
351static void ath9k_hw_override_ini(struct ath_hal *ah,
352 struct ath9k_channel *chan)
353{
354 if (!AR_SREV_5416_V20_OR_LATER(ah)
355 || AR_SREV_9280_10_OR_LATER(ah))
356 return;
357
358 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
359}
360
361static void ath9k_hw_init_bb(struct ath_hal *ah,
362 struct ath9k_channel *chan)
363{
364 u32 synthDelay;
365
366 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
367 if (IS_CHAN_CCK(chan))
368 synthDelay = (4 * synthDelay) / 22;
369 else
370 synthDelay /= 10;
371
372 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
373
374 udelay(synthDelay + BASE_ACTIVATE_DELAY);
375}
376
377static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
378 enum ath9k_opmode opmode)
379{
380 struct ath_hal_5416 *ahp = AH5416(ah);
381
382 ahp->ah_maskReg = AR_IMR_TXERR |
383 AR_IMR_TXURN |
384 AR_IMR_RXERR |
385 AR_IMR_RXORN |
386 AR_IMR_BCNMISC;
387
388 if (ahp->ah_intrMitigation)
389 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
390 else
391 ahp->ah_maskReg |= AR_IMR_RXOK;
392
393 ahp->ah_maskReg |= AR_IMR_TXOK;
394
395 if (opmode == ATH9K_M_HOSTAP)
396 ahp->ah_maskReg |= AR_IMR_MIB;
397
398 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
399 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
400
401 if (!AR_SREV_9100(ah)) {
402 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
403 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
404 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
405 } 140 }
141 return false;
406} 142}
407 143
408static void ath9k_hw_init_qos(struct ath_hal *ah) 144u16 ath9k_hw_computetxtime(struct ath_hal *ah,
409{ 145 const struct ath9k_rate_table *rates,
410 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 146 u32 frameLen, u16 rateix,
411 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 147 bool shortPreamble)
412
413 REG_WRITE(ah, AR_QOS_NO_ACK,
414 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
415 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
416 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
417
418 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
419 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
420 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
421 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
422 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
423}
424
425static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
426 u32 reg,
427 u32 mask,
428 u32 shift,
429 u32 val)
430{
431 u32 regVal;
432
433 regVal = REG_READ(ah, reg) & ~mask;
434 regVal |= (val << shift) & mask;
435
436 REG_WRITE(ah, reg, regVal);
437
438 if (ah->ah_config.analog_shiftreg)
439 udelay(100);
440
441 return;
442}
443
444static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
445 enum ieee80211_band freq_band)
446{ 148{
447 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 149 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
448 struct modal_eep_header *pModal = 150 u32 kbps;
449 &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]);
450 struct base_eep_header *pBase = &eep->baseEepHeader;
451 u8 num_ant_config;
452
453 num_ant_config = 1;
454
455 if (pBase->version >= 0x0E0D)
456 if (pModal->useAnt1)
457 num_ant_config += 1;
458
459 return num_ant_config;
460}
461 151
462static int 152 kbps = rates->info[rateix].rateKbps;
463ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
464 struct ath9k_channel *chan,
465 u8 index,
466 u16 *config)
467{
468 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
469 struct modal_eep_header *pModal =
470 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
471 struct base_eep_header *pBase = &eep->baseEepHeader;
472 153
473 switch (index) { 154 if (kbps == 0)
474 case 0:
475 *config = pModal->antCtrlCommon & 0xFFFF;
476 return 0; 155 return 0;
477 case 1: 156
478 if (pBase->version >= 0x0E0D) { 157 switch (rates->info[rateix].phy) {
479 if (pModal->useAnt1) { 158 case PHY_CCK:
480 *config = 159 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
481 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16); 160 if (shortPreamble && rates->info[rateix].shortPreamble)
482 return 0; 161 phyTime >>= 1;
483 } 162 numBits = frameLen << 3;
163 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
164 break;
165 case PHY_OFDM:
166 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
168 numBits = OFDM_PLCP_BITS + (frameLen << 3);
169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
170 txTime = OFDM_SIFS_TIME_QUARTER
171 + OFDM_PREAMBLE_TIME_QUARTER
172 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
173 } else if (ah->ah_curchan &&
174 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
175 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
176 numBits = OFDM_PLCP_BITS + (frameLen << 3);
177 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
178 txTime = OFDM_SIFS_TIME_HALF +
179 OFDM_PREAMBLE_TIME_HALF
180 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
181 } else {
182 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
183 numBits = OFDM_PLCP_BITS + (frameLen << 3);
184 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
185 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
186 + (numSymbols * OFDM_SYMBOL_TIME);
484 } 187 }
485 break; 188 break;
486 default: 189 default:
190 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
191 "%s: unknown phy %u (rate ix %u)\n", __func__,
192 rates->info[rateix].phy, rateix);
193 txTime = 0;
487 break; 194 break;
488 } 195 }
489 196
490 return -EINVAL; 197 return txTime;
491}
492
493static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
494 u32 off,
495 u16 *data)
496{
497 if (ath9k_hw_use_flash(ah))
498 return ath9k_hw_flash_read(ah, off, data);
499 else
500 return ath9k_hw_eeprom_read(ah, off, data);
501} 198}
502 199
503static bool ath9k_hw_fill_eeprom(struct ath_hal *ah) 200u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
504{ 201{
505 struct ath_hal_5416 *ahp = AH5416(ah); 202 if (flags & CHANNEL_2GHZ) {
506 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 203 if (freq == 2484)
507 u16 *eep_data; 204 return 14;
508 int addr, ar5416_eep_start_loc = 0; 205 if (freq < 2484)
509 206 return (freq - 2407) / 5;
510 if (!ath9k_hw_use_flash(ah)) { 207 else
511 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 208 return 15 + ((freq - 2512) / 20);
512 "%s: Reading from EEPROM, not flash\n", __func__); 209 } else if (flags & CHANNEL_5GHZ) {
513 ar5416_eep_start_loc = 256; 210 if (ath9k_regd_is_public_safety_sku(ah) &&
514 } 211 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
515 if (AR_SREV_9100(ah)) 212 return ((freq * 10) +
516 ar5416_eep_start_loc = 256; 213 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
517 214 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
518 eep_data = (u16 *) eep; 215 return (freq - 4000) / 5;
519 for (addr = 0; 216 } else {
520 addr < sizeof(struct ar5416_eeprom) / sizeof(u16); 217 return (freq - 5000) / 5;
521 addr++) {
522 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
523 eep_data)) {
524 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
525 "%s: Unable to read eeprom region \n",
526 __func__);
527 return false;
528 } 218 }
529 eep_data++; 219 } else {
220 if (freq == 2484)
221 return 14;
222 if (freq < 2484)
223 return (freq - 2407) / 5;
224 if (freq < 5000) {
225 if (ath9k_regd_is_public_safety_sku(ah)
226 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
227 return ((freq * 10) +
228 (((freq % 5) ==
229 2) ? 5 : 0) - 49400) / 5;
230 } else if (freq > 4900) {
231 return (freq - 4000) / 5;
232 } else {
233 return 15 + ((freq - 2512) / 20);
234 }
235 }
236 return (freq - 5000) / 5;
530 } 237 }
531 return true;
532} 238}
533 239
534/* XXX: Clean me up, make me more legible */ 240void ath9k_hw_get_channel_centers(struct ath_hal *ah,
535static bool 241 struct ath9k_channel *chan,
536ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, 242 struct chan_centers *centers)
537 struct ath9k_channel *chan)
538{ 243{
539 struct modal_eep_header *pModal; 244 int8_t extoff;
540 int i, regChainOffset;
541 struct ath_hal_5416 *ahp = AH5416(ah); 245 struct ath_hal_5416 *ahp = AH5416(ah);
542 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
543 u8 txRxAttenLocal;
544 u16 ant_config;
545 246
546 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 247 if (!IS_CHAN_HT40(chan)) {
248 centers->ctl_center = centers->ext_center =
249 centers->synth_center = chan->channel;
250 return;
251 }
547 252
548 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; 253 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
254 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
255 centers->synth_center =
256 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
257 extoff = 1;
258 } else {
259 centers->synth_center =
260 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
261 extoff = -1;
262 }
549 263
550 ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config); 264 centers->ctl_center =
551 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 265 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
266 centers->ext_center =
267 centers->synth_center + (extoff *
268 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
269 HT40_CHANNEL_CENTER_SHIFT : 15));
552 270
553 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 271}
554 if (AR_SREV_9280(ah)) {
555 if (i >= 2)
556 break;
557 }
558 272
559 if (AR_SREV_5416_V20_OR_LATER(ah) && 273/******************/
560 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) 274/* Chip Revisions */
561 && (i != 0)) 275/******************/
562 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
563 else
564 regChainOffset = i * 0x1000;
565
566 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
567 pModal->antCtrlChain[i]);
568
569 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
570 (REG_READ(ah,
571 AR_PHY_TIMING_CTRL4(0) +
572 regChainOffset) &
573 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
574 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
575 SM(pModal->iqCalICh[i],
576 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
577 SM(pModal->iqCalQCh[i],
578 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
579
580 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
581 if ((eep->baseEepHeader.version &
582 AR5416_EEP_VER_MINOR_MASK) >=
583 AR5416_EEP_MINOR_VER_3) {
584 txRxAttenLocal = pModal->txRxAttenCh[i];
585 if (AR_SREV_9280_10_OR_LATER(ah)) {
586 REG_RMW_FIELD(ah,
587 AR_PHY_GAIN_2GHZ +
588 regChainOffset,
589 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
590 pModal->
591 bswMargin[i]);
592 REG_RMW_FIELD(ah,
593 AR_PHY_GAIN_2GHZ +
594 regChainOffset,
595 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
596 pModal->
597 bswAtten[i]);
598 REG_RMW_FIELD(ah,
599 AR_PHY_GAIN_2GHZ +
600 regChainOffset,
601 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
602 pModal->
603 xatten2Margin[i]);
604 REG_RMW_FIELD(ah,
605 AR_PHY_GAIN_2GHZ +
606 regChainOffset,
607 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
608 pModal->
609 xatten2Db[i]);
610 } else {
611 REG_WRITE(ah,
612 AR_PHY_GAIN_2GHZ +
613 regChainOffset,
614 (REG_READ(ah,
615 AR_PHY_GAIN_2GHZ +
616 regChainOffset) &
617 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
618 | SM(pModal->
619 bswMargin[i],
620 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
621 REG_WRITE(ah,
622 AR_PHY_GAIN_2GHZ +
623 regChainOffset,
624 (REG_READ(ah,
625 AR_PHY_GAIN_2GHZ +
626 regChainOffset) &
627 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
628 | SM(pModal->bswAtten[i],
629 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
630 }
631 }
632 if (AR_SREV_9280_10_OR_LATER(ah)) {
633 REG_RMW_FIELD(ah,
634 AR_PHY_RXGAIN +
635 regChainOffset,
636 AR9280_PHY_RXGAIN_TXRX_ATTEN,
637 txRxAttenLocal);
638 REG_RMW_FIELD(ah,
639 AR_PHY_RXGAIN +
640 regChainOffset,
641 AR9280_PHY_RXGAIN_TXRX_MARGIN,
642 pModal->rxTxMarginCh[i]);
643 } else {
644 REG_WRITE(ah,
645 AR_PHY_RXGAIN + regChainOffset,
646 (REG_READ(ah,
647 AR_PHY_RXGAIN +
648 regChainOffset) &
649 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
650 SM(txRxAttenLocal,
651 AR_PHY_RXGAIN_TXRX_ATTEN));
652 REG_WRITE(ah,
653 AR_PHY_GAIN_2GHZ +
654 regChainOffset,
655 (REG_READ(ah,
656 AR_PHY_GAIN_2GHZ +
657 regChainOffset) &
658 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
659 SM(pModal->rxTxMarginCh[i],
660 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
661 }
662 }
663 }
664 276
665 if (AR_SREV_9280_10_OR_LATER(ah)) { 277static void ath9k_hw_read_revisions(struct ath_hal *ah)
666 if (IS_CHAN_2GHZ(chan)) { 278{
667 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, 279 u32 val;
668 AR_AN_RF2G1_CH0_OB,
669 AR_AN_RF2G1_CH0_OB_S,
670 pModal->ob);
671 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
672 AR_AN_RF2G1_CH0_DB,
673 AR_AN_RF2G1_CH0_DB_S,
674 pModal->db);
675 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
676 AR_AN_RF2G1_CH1_OB,
677 AR_AN_RF2G1_CH1_OB_S,
678 pModal->ob_ch1);
679 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
680 AR_AN_RF2G1_CH1_DB,
681 AR_AN_RF2G1_CH1_DB_S,
682 pModal->db_ch1);
683 } else {
684 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
685 AR_AN_RF5G1_CH0_OB5,
686 AR_AN_RF5G1_CH0_OB5_S,
687 pModal->ob);
688 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
689 AR_AN_RF5G1_CH0_DB5,
690 AR_AN_RF5G1_CH0_DB5_S,
691 pModal->db);
692 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
693 AR_AN_RF5G1_CH1_OB5,
694 AR_AN_RF5G1_CH1_OB5_S,
695 pModal->ob_ch1);
696 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
697 AR_AN_RF5G1_CH1_DB5,
698 AR_AN_RF5G1_CH1_DB5_S,
699 pModal->db_ch1);
700 }
701 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
702 AR_AN_TOP2_XPABIAS_LVL,
703 AR_AN_TOP2_XPABIAS_LVL_S,
704 pModal->xpaBiasLvl);
705 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
706 AR_AN_TOP2_LOCALBIAS,
707 AR_AN_TOP2_LOCALBIAS_S,
708 pModal->local_bias);
709 DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n",
710 pModal->force_xpaon);
711 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
712 pModal->force_xpaon);
713 }
714 280
715 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
716 pModal->switchSettling);
717 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
718 pModal->adcDesiredSize);
719 282
720 if (!AR_SREV_9280_10_OR_LATER(ah)) 283 if (val == 0xFF) {
721 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 284 val = REG_READ(ah, AR_SREV);
722 AR_PHY_DESIRED_SZ_PGA, 285 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
723 pModal->pgaDesiredSize); 286 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
724 287 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
725 REG_WRITE(ah, AR_PHY_RF_CTL4,
726 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
727 | SM(pModal->txEndToXpaOff,
728 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
729 | SM(pModal->txFrameToXpaOn,
730 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
731 | SM(pModal->txFrameToXpaOn,
732 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
733
734 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
735 pModal->txEndToRxOn);
736 if (AR_SREV_9280_10_OR_LATER(ah)) {
737 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
738 pModal->thresh62);
739 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
740 AR_PHY_EXT_CCA0_THRESH62,
741 pModal->thresh62);
742 } else { 288 } else {
743 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, 289 if (!AR_SREV_9100(ah))
744 pModal->thresh62); 290 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
745 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
746 AR_PHY_EXT_CCA_THRESH62,
747 pModal->thresh62);
748 }
749 291
750 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 292 ah->ah_macRev = val & AR_SREV_REVISION;
751 AR5416_EEP_MINOR_VER_2) {
752 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
753 AR_PHY_TX_END_DATA_START,
754 pModal->txFrameToDataStart);
755 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
756 pModal->txFrameToPaOn);
757 }
758 293
759 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 294 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
760 AR5416_EEP_MINOR_VER_3) { 295 ah->ah_isPciExpress = true;
761 if (IS_CHAN_HT40(chan))
762 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
763 AR_PHY_SETTLING_SWITCH,
764 pModal->swSettleHt40);
765 } 296 }
766
767 return true;
768} 297}
769 298
770static int ath9k_hw_check_eeprom(struct ath_hal *ah) 299static int ath9k_hw_get_radiorev(struct ath_hal *ah)
771{ 300{
772 u32 sum = 0, el; 301 u32 val;
773 u16 *eepdata;
774 int i; 302 int i;
775 struct ath_hal_5416 *ahp = AH5416(ah);
776 bool need_swap = false;
777 struct ar5416_eeprom *eep =
778 (struct ar5416_eeprom *) &ahp->ah_eeprom;
779
780 if (!ath9k_hw_use_flash(ah)) {
781 u16 magic, magic2;
782 int addr;
783
784 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
785 &magic)) {
786 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
787 "%s: Reading Magic # failed\n", __func__);
788 return false;
789 }
790 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
791 __func__, magic);
792
793 if (magic != AR5416_EEPROM_MAGIC) {
794 magic2 = swab16(magic);
795
796 if (magic2 == AR5416_EEPROM_MAGIC) {
797 need_swap = true;
798 eepdata = (u16 *) (&ahp->ah_eeprom);
799
800 for (addr = 0;
801 addr <
802 sizeof(struct ar5416_eeprom) /
803 sizeof(u16); addr++) {
804 u16 temp;
805
806 temp = swab16(*eepdata);
807 *eepdata = temp;
808 eepdata++;
809
810 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
811 "0x%04X ", *eepdata);
812 if (((addr + 1) % 6) == 0)
813 DPRINTF(ah->ah_sc,
814 ATH_DBG_EEPROM,
815 "\n");
816 }
817 } else {
818 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
819 "Invalid EEPROM Magic. "
820 "endianness missmatch.\n");
821 return -EINVAL;
822 }
823 }
824 }
825 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
826 need_swap ? "True" : "False");
827
828 if (need_swap)
829 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
830 else
831 el = ahp->ah_eeprom.baseEepHeader.length;
832
833 if (el > sizeof(struct ar5416_eeprom))
834 el = sizeof(struct ar5416_eeprom) / sizeof(u16);
835 else
836 el = el / sizeof(u16);
837
838 eepdata = (u16 *) (&ahp->ah_eeprom);
839
840 for (i = 0; i < el; i++)
841 sum ^= *eepdata++;
842
843 if (need_swap) {
844 u32 integer, j;
845 u16 word;
846 303
847 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 304 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
848 "EEPROM Endianness is not native.. Changing \n");
849
850 word = swab16(eep->baseEepHeader.length);
851 eep->baseEepHeader.length = word;
852
853 word = swab16(eep->baseEepHeader.checksum);
854 eep->baseEepHeader.checksum = word;
855
856 word = swab16(eep->baseEepHeader.version);
857 eep->baseEepHeader.version = word;
858
859 word = swab16(eep->baseEepHeader.regDmn[0]);
860 eep->baseEepHeader.regDmn[0] = word;
861
862 word = swab16(eep->baseEepHeader.regDmn[1]);
863 eep->baseEepHeader.regDmn[1] = word;
864
865 word = swab16(eep->baseEepHeader.rfSilent);
866 eep->baseEepHeader.rfSilent = word;
867
868 word = swab16(eep->baseEepHeader.blueToothOptions);
869 eep->baseEepHeader.blueToothOptions = word;
870 305
871 word = swab16(eep->baseEepHeader.deviceCap); 306 for (i = 0; i < 8; i++)
872 eep->baseEepHeader.deviceCap = word; 307 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
308 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
309 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
873 310
874 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { 311 return ath9k_hw_reverse_bits(val, 8);
875 struct modal_eep_header *pModal = 312}
876 &eep->modalHeader[j];
877 integer = swab32(pModal->antCtrlCommon);
878 pModal->antCtrlCommon = integer;
879 313
880 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 314/************************************/
881 integer = swab32(pModal->antCtrlChain[i]); 315/* HW Attach, Detach, Init Routines */
882 pModal->antCtrlChain[i] = integer; 316/************************************/
883 }
884 317
885 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 318static void ath9k_hw_disablepcie(struct ath_hal *ah)
886 word = swab16(pModal->spurChans[i].spurChan); 319{
887 pModal->spurChans[i].spurChan = word; 320 if (!AR_SREV_9100(ah))
888 } 321 return;
889 }
890 }
891 322
892 if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER || 323 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
893 ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) { 324 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
894 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 325 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
895 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 326 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
896 sum, ar5416_get_eep_ver(ahp)); 327 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
897 return -EINVAL; 328 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
898 } 329 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
330 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
899 332
900 return 0; 333 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
901} 334}
902 335
903static bool ath9k_hw_chip_test(struct ath_hal *ah) 336static bool ath9k_hw_chip_test(struct ath_hal *ah)
@@ -905,9 +338,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
905 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 338 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
906 u32 regHold[2]; 339 u32 regHold[2];
907 u32 patternData[4] = { 0x55555555, 340 u32 patternData[4] = { 0x55555555,
908 0xaaaaaaaa, 341 0xaaaaaaaa,
909 0x66666666, 342 0x66666666,
910 0x99999999 }; 343 0x99999999 };
911 int i, j; 344 int i, j;
912 345
913 for (i = 0; i < 2; i++) { 346 for (i = 0; i < 2; i++) {
@@ -921,9 +354,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
921 rdData = REG_READ(ah, addr); 354 rdData = REG_READ(ah, addr);
922 if (rdData != wrData) { 355 if (rdData != wrData) {
923 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 356 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
924 "%s: address test failed " 357 "%s: address test failed "
925 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 358 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
926 __func__, addr, wrData, rdData); 359 __func__, addr, wrData, rdData);
927 return false; 360 return false;
928 } 361 }
929 } 362 }
@@ -933,9 +366,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
933 rdData = REG_READ(ah, addr); 366 rdData = REG_READ(ah, addr);
934 if (wrData != rdData) { 367 if (wrData != rdData) {
935 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 368 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
936 "%s: address test failed " 369 "%s: address test failed "
937 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 370 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
938 __func__, addr, wrData, rdData); 371 __func__, addr, wrData, rdData);
939 return false; 372 return false;
940 } 373 }
941 } 374 }
@@ -945,213 +378,62 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
945 return true; 378 return true;
946} 379}
947 380
948u32 ath9k_hw_getrxfilter(struct ath_hal *ah) 381static const char *ath9k_hw_devname(u16 devid)
949{
950 u32 bits = REG_READ(ah, AR_RX_FILTER);
951 u32 phybits = REG_READ(ah, AR_PHY_ERR);
952
953 if (phybits & AR_PHY_ERR_RADAR)
954 bits |= ATH9K_RX_FILTER_PHYRADAR;
955 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
956 bits |= ATH9K_RX_FILTER_PHYERR;
957 return bits;
958}
959
960void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
961{
962 u32 phybits;
963
964 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
965 phybits = 0;
966 if (bits & ATH9K_RX_FILTER_PHYRADAR)
967 phybits |= AR_PHY_ERR_RADAR;
968 if (bits & ATH9K_RX_FILTER_PHYERR)
969 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
970 REG_WRITE(ah, AR_PHY_ERR, phybits);
971
972 if (phybits)
973 REG_WRITE(ah, AR_RXCFG,
974 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
975 else
976 REG_WRITE(ah, AR_RXCFG,
977 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
978}
979
980bool ath9k_hw_setcapability(struct ath_hal *ah,
981 enum ath9k_capability_type type,
982 u32 capability,
983 u32 setting,
984 int *status)
985{
986 struct ath_hal_5416 *ahp = AH5416(ah);
987 u32 v;
988
989 switch (type) {
990 case ATH9K_CAP_TKIP_MIC:
991 if (setting)
992 ahp->ah_staId1Defaults |=
993 AR_STA_ID1_CRPT_MIC_ENABLE;
994 else
995 ahp->ah_staId1Defaults &=
996 ~AR_STA_ID1_CRPT_MIC_ENABLE;
997 return true;
998 case ATH9K_CAP_DIVERSITY:
999 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1000 if (setting)
1001 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1002 else
1003 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1004 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1005 return true;
1006 case ATH9K_CAP_MCAST_KEYSRCH:
1007 if (setting)
1008 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1009 else
1010 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1011 return true;
1012 case ATH9K_CAP_TSF_ADJUST:
1013 if (setting)
1014 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1015 else
1016 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1017 return true;
1018 default:
1019 return false;
1020 }
1021}
1022
1023void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1024{ 382{
1025 u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; 383 switch (devid) {
1026 int qcuOffset = 0, dcuOffset = 0; 384 case AR5416_DEVID_PCI:
1027 u32 *qcuBase = &val[0], *dcuBase = &val[4]; 385 case AR5416_DEVID_PCIE:
1028 int i; 386 return "Atheros 5416";
1029 387 case AR9160_DEVID_PCI:
1030 REG_WRITE(ah, AR_MACMISC, 388 return "Atheros 9160";
1031 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 389 case AR9280_DEVID_PCI:
1032 (AR_MACMISC_MISC_OBS_BUS_1 << 390 case AR9280_DEVID_PCIE:
1033 AR_MACMISC_MISC_OBS_BUS_MSB_S))); 391 return "Atheros 9280";
1034
1035 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n");
1036 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
1037 if (i % 4 == 0)
1038 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1039
1040 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
1041 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
1042 }
1043
1044 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
1045 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1046 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1047
1048 for (i = 0; i < ATH9K_NUM_QUEUES;
1049 i++, qcuOffset += 4, dcuOffset += 5) {
1050 if (i == 8) {
1051 qcuOffset = 0;
1052 qcuBase++;
1053 }
1054
1055 if (i == 6) {
1056 dcuOffset = 0;
1057 dcuBase++;
1058 }
1059
1060 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1061 "%2d %2x %1x %2x %2x\n",
1062 i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1063 (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1064 3),
1065 val[2] & (0x7 << (i * 3)) >> (i * 3),
1066 (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1067 } 392 }
1068 393
1069 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n"); 394 return NULL;
1070 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1071 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1072 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1073 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1074 "qcu_complete state: %2x dcu_complete state: %2x\n",
1075 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1076 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1077 "dcu_arb state: %2x dcu_fp state: %2x\n",
1078 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1079 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1080 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1081 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1082 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1083 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1084 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1085 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1086 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1087 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1088
1089 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
1090 REG_READ(ah, AR_OBS_BUS_1));
1091 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1092 "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1093} 395}
1094 396
1095u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, 397static void ath9k_hw_set_defaults(struct ath_hal *ah)
1096 u32 *rxc_pcnt,
1097 u32 *rxf_pcnt,
1098 u32 *txf_pcnt)
1099{ 398{
1100 static u32 cycles, rx_clear, rx_frame, tx_frame; 399 int i;
1101 u32 good = 1;
1102 400
1103 u32 rc = REG_READ(ah, AR_RCCNT); 401 ah->ah_config.dma_beacon_response_time = 2;
1104 u32 rf = REG_READ(ah, AR_RFCNT); 402 ah->ah_config.sw_beacon_response_time = 10;
1105 u32 tf = REG_READ(ah, AR_TFCNT); 403 ah->ah_config.additional_swba_backoff = 0;
1106 u32 cc = REG_READ(ah, AR_CCCNT); 404 ah->ah_config.ack_6mb = 0x0;
405 ah->ah_config.cwm_ignore_extcca = 0;
406 ah->ah_config.pcie_powersave_enable = 0;
407 ah->ah_config.pcie_l1skp_enable = 0;
408 ah->ah_config.pcie_clock_req = 0;
409 ah->ah_config.pcie_power_reset = 0x100;
410 ah->ah_config.pcie_restore = 0;
411 ah->ah_config.pcie_waen = 0;
412 ah->ah_config.analog_shiftreg = 1;
413 ah->ah_config.ht_enable = 1;
414 ah->ah_config.ofdm_trig_low = 200;
415 ah->ah_config.ofdm_trig_high = 500;
416 ah->ah_config.cck_trig_high = 200;
417 ah->ah_config.cck_trig_low = 100;
418 ah->ah_config.enable_ani = 1;
419 ah->ah_config.noise_immunity_level = 4;
420 ah->ah_config.ofdm_weaksignal_det = 1;
421 ah->ah_config.cck_weaksignal_thr = 0;
422 ah->ah_config.spur_immunity_level = 2;
423 ah->ah_config.firstep_level = 0;
424 ah->ah_config.rssi_thr_high = 40;
425 ah->ah_config.rssi_thr_low = 7;
426 ah->ah_config.diversity_control = 0;
427 ah->ah_config.antenna_switch_swap = 0;
1107 428
1108 if (cycles == 0 || cycles > cc) { 429 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1109 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 430 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
1110 "%s: cycle counter wrap. ExtBusy = 0\n", 431 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
1111 __func__);
1112 good = 0;
1113 } else {
1114 u32 cc_d = cc - cycles;
1115 u32 rc_d = rc - rx_clear;
1116 u32 rf_d = rf - rx_frame;
1117 u32 tf_d = tf - tx_frame;
1118
1119 if (cc_d != 0) {
1120 *rxc_pcnt = rc_d * 100 / cc_d;
1121 *rxf_pcnt = rf_d * 100 / cc_d;
1122 *txf_pcnt = tf_d * 100 / cc_d;
1123 } else {
1124 good = 0;
1125 }
1126 } 432 }
1127 433
1128 cycles = cc; 434 ah->ah_config.intr_mitigation = 1;
1129 rx_frame = rf;
1130 rx_clear = rc;
1131 tx_frame = tf;
1132
1133 return good;
1134}
1135
1136void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
1137{
1138 u32 macmode;
1139
1140 if (mode == ATH9K_HT_MACMODE_2040 &&
1141 !ah->ah_config.cwm_ignore_extcca)
1142 macmode = AR_2040_JOINED_RX_CLEAR;
1143 else
1144 macmode = 0;
1145
1146 REG_WRITE(ah, AR_2040_MODE, macmode);
1147}
1148
1149static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1150{
1151 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1152} 435}
1153 436
1154
1155static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, 437static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1156 struct ath_softc *sc, 438 struct ath_softc *sc,
1157 void __iomem *mem, 439 void __iomem *mem,
@@ -1165,20 +447,17 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1165 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); 447 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1166 if (ahp == NULL) { 448 if (ahp == NULL) {
1167 DPRINTF(sc, ATH_DBG_FATAL, 449 DPRINTF(sc, ATH_DBG_FATAL,
1168 "%s: cannot allocate memory for state block\n", 450 "%s: cannot allocate memory for state block\n",
1169 __func__); 451 __func__);
1170 *status = -ENOMEM; 452 *status = -ENOMEM;
1171 return NULL; 453 return NULL;
1172 } 454 }
1173 455
1174 ah = &ahp->ah; 456 ah = &ahp->ah;
1175
1176 ah->ah_sc = sc; 457 ah->ah_sc = sc;
1177 ah->ah_sh = mem; 458 ah->ah_sh = mem;
1178
1179 ah->ah_magic = AR5416_MAGIC; 459 ah->ah_magic = AR5416_MAGIC;
1180 ah->ah_countryCode = CTRY_DEFAULT; 460 ah->ah_countryCode = CTRY_DEFAULT;
1181
1182 ah->ah_devid = devid; 461 ah->ah_devid = devid;
1183 ah->ah_subvendorid = 0; 462 ah->ah_subvendorid = 0;
1184 463
@@ -1190,12 +469,10 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1190 469
1191 ah->ah_powerLimit = MAX_RATE_POWER; 470 ah->ah_powerLimit = MAX_RATE_POWER;
1192 ah->ah_tpScale = ATH9K_TP_SCALE_MAX; 471 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
1193
1194 ahp->ah_atimWindow = 0; 472 ahp->ah_atimWindow = 0;
1195 ahp->ah_diversityControl = ah->ah_config.diversity_control; 473 ahp->ah_diversityControl = ah->ah_config.diversity_control;
1196 ahp->ah_antennaSwitchSwap = 474 ahp->ah_antennaSwitchSwap =
1197 ah->ah_config.antenna_switch_swap; 475 ah->ah_config.antenna_switch_swap;
1198
1199 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 476 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1200 ahp->ah_beaconInterval = 100; 477 ahp->ah_beaconInterval = 100;
1201 ahp->ah_enable32kHzClock = DONT_USE_32KHZ; 478 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
@@ -1210,162 +487,6 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1210 return ahp; 487 return ahp;
1211} 488}
1212 489
1213static int ath9k_hw_eeprom_attach(struct ath_hal *ah)
1214{
1215 int status;
1216
1217 if (ath9k_hw_use_flash(ah))
1218 ath9k_hw_flash_map(ah);
1219
1220 if (!ath9k_hw_fill_eeprom(ah))
1221 return -EIO;
1222
1223 status = ath9k_hw_check_eeprom(ah);
1224
1225 return status;
1226}
1227
1228u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1229 enum eeprom_param param)
1230{
1231 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1232 struct modal_eep_header *pModal = eep->modalHeader;
1233 struct base_eep_header *pBase = &eep->baseEepHeader;
1234
1235 switch (param) {
1236 case EEP_NFTHRESH_5:
1237 return -pModal[0].noiseFloorThreshCh[0];
1238 case EEP_NFTHRESH_2:
1239 return -pModal[1].noiseFloorThreshCh[0];
1240 case AR_EEPROM_MAC(0):
1241 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1242 case AR_EEPROM_MAC(1):
1243 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1244 case AR_EEPROM_MAC(2):
1245 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1246 case EEP_REG_0:
1247 return pBase->regDmn[0];
1248 case EEP_REG_1:
1249 return pBase->regDmn[1];
1250 case EEP_OP_CAP:
1251 return pBase->deviceCap;
1252 case EEP_OP_MODE:
1253 return pBase->opCapFlags;
1254 case EEP_RF_SILENT:
1255 return pBase->rfSilent;
1256 case EEP_OB_5:
1257 return pModal[0].ob;
1258 case EEP_DB_5:
1259 return pModal[0].db;
1260 case EEP_OB_2:
1261 return pModal[1].ob;
1262 case EEP_DB_2:
1263 return pModal[1].db;
1264 case EEP_MINOR_REV:
1265 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1266 case EEP_TX_MASK:
1267 return pBase->txMask;
1268 case EEP_RX_MASK:
1269 return pBase->rxMask;
1270 default:
1271 return 0;
1272 }
1273}
1274
1275static int ath9k_hw_get_radiorev(struct ath_hal *ah)
1276{
1277 u32 val;
1278 int i;
1279
1280 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1281 for (i = 0; i < 8; i++)
1282 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1283 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1284 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1285 return ath9k_hw_reverse_bits(val, 8);
1286}
1287
1288static int ath9k_hw_init_macaddr(struct ath_hal *ah)
1289{
1290 u32 sum;
1291 int i;
1292 u16 eeval;
1293 struct ath_hal_5416 *ahp = AH5416(ah);
1294
1295 sum = 0;
1296 for (i = 0; i < 3; i++) {
1297 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1298 sum += eeval;
1299 ahp->ah_macaddr[2 * i] = eeval >> 8;
1300 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1301 }
1302 if (sum == 0 || sum == 0xffff * 3) {
1303 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1304 "%s: mac address read failed: %pM\n", __func__,
1305 ahp->ah_macaddr);
1306 return -EADDRNOTAVAIL;
1307 }
1308
1309 return 0;
1310}
1311
1312static inline int16_t ath9k_hw_interpolate(u16 target,
1313 u16 srcLeft,
1314 u16 srcRight,
1315 int16_t targetLeft,
1316 int16_t targetRight)
1317{
1318 int16_t rv;
1319
1320 if (srcRight == srcLeft) {
1321 rv = targetLeft;
1322 } else {
1323 rv = (int16_t) (((target - srcLeft) * targetRight +
1324 (srcRight - target) * targetLeft) /
1325 (srcRight - srcLeft));
1326 }
1327 return rv;
1328}
1329
1330static inline u16 ath9k_hw_fbin2freq(u8 fbin,
1331 bool is2GHz)
1332{
1333
1334 if (fbin == AR5416_BCHAN_UNUSED)
1335 return fbin;
1336
1337 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1338}
1339
1340static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1341 u16 i,
1342 bool is2GHz)
1343{
1344 struct ath_hal_5416 *ahp = AH5416(ah);
1345 struct ar5416_eeprom *eep =
1346 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1347 u16 spur_val = AR_NO_SPUR;
1348
1349 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1350 "Getting spur idx %d is2Ghz. %d val %x\n",
1351 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
1352
1353 switch (ah->ah_config.spurmode) {
1354 case SPUR_DISABLE:
1355 break;
1356 case SPUR_ENABLE_IOCTL:
1357 spur_val = ah->ah_config.spurchans[i][is2GHz];
1358 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1359 "Getting spur val from new loc. %d\n", spur_val);
1360 break;
1361 case SPUR_ENABLE_EEPROM:
1362 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1363 break;
1364
1365 }
1366 return spur_val;
1367}
1368
1369static int ath9k_hw_rfattach(struct ath_hal *ah) 490static int ath9k_hw_rfattach(struct ath_hal *ah)
1370{ 491{
1371 bool rfStatus = false; 492 bool rfStatus = false;
@@ -1374,8 +495,8 @@ static int ath9k_hw_rfattach(struct ath_hal *ah)
1374 rfStatus = ath9k_hw_init_rf(ah, &ecode); 495 rfStatus = ath9k_hw_init_rf(ah, &ecode);
1375 if (!rfStatus) { 496 if (!rfStatus) {
1376 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 497 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1377 "%s: RF setup failed, status %u\n", __func__, 498 "%s: RF setup failed, status %u\n", __func__,
1378 ecode); 499 ecode);
1379 return ecode; 500 return ecode;
1380 } 501 }
1381 502
@@ -1400,9 +521,9 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah)
1400 break; 521 break;
1401 default: 522 default:
1402 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 523 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1403 "%s: 5G Radio Chip Rev 0x%02X is not " 524 "%s: 5G Radio Chip Rev 0x%02X is not "
1404 "supported by this driver\n", 525 "supported by this driver\n",
1405 __func__, ah->ah_analog5GhzRev); 526 __func__, ah->ah_analog5GhzRev);
1406 return -EOPNOTSUPP; 527 return -EOPNOTSUPP;
1407 } 528 }
1408 529
@@ -1411,1482 +532,37 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah)
1411 return 0; 532 return 0;
1412} 533}
1413 534
1414static void ath9k_hw_init_pll(struct ath_hal *ah, 535static int ath9k_hw_init_macaddr(struct ath_hal *ah)
1415 struct ath9k_channel *chan)
1416{
1417 u32 pll;
1418
1419 if (AR_SREV_9100(ah)) {
1420 if (chan && IS_CHAN_5GHZ(chan))
1421 pll = 0x1450;
1422 else
1423 pll = 0x1458;
1424 } else {
1425 if (AR_SREV_9280_10_OR_LATER(ah)) {
1426 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1427
1428 if (chan && IS_CHAN_HALF_RATE(chan))
1429 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1430 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1431 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1432
1433 if (chan && IS_CHAN_5GHZ(chan)) {
1434 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1435
1436
1437 if (AR_SREV_9280_20(ah)) {
1438 if (((chan->channel % 20) == 0)
1439 || ((chan->channel % 10) == 0))
1440 pll = 0x2850;
1441 else
1442 pll = 0x142c;
1443 }
1444 } else {
1445 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1446 }
1447
1448 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1449
1450 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1451
1452 if (chan && IS_CHAN_HALF_RATE(chan))
1453 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1454 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1455 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1456
1457 if (chan && IS_CHAN_5GHZ(chan))
1458 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1459 else
1460 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1461 } else {
1462 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1463
1464 if (chan && IS_CHAN_HALF_RATE(chan))
1465 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1466 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1467 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1468
1469 if (chan && IS_CHAN_5GHZ(chan))
1470 pll |= SM(0xa, AR_RTC_PLL_DIV);
1471 else
1472 pll |= SM(0xb, AR_RTC_PLL_DIV);
1473 }
1474 }
1475 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1476
1477 udelay(RTC_PLL_SETTLE_DELAY);
1478
1479 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1480}
1481
1482static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1483 enum ath9k_ht_macmode macmode)
1484{
1485 u32 phymode;
1486 struct ath_hal_5416 *ahp = AH5416(ah);
1487
1488 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1489 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1490
1491 if (IS_CHAN_HT40(chan)) {
1492 phymode |= AR_PHY_FC_DYN2040_EN;
1493
1494 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1495 (chan->chanmode == CHANNEL_G_HT40PLUS))
1496 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1497
1498 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1499 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1500 }
1501 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1502
1503 ath9k_hw_set11nmac2040(ah, macmode);
1504
1505 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1506 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1507}
1508
1509static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1510{
1511 u32 val;
1512
1513 val = REG_READ(ah, AR_STA_ID1);
1514 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1515 switch (opmode) {
1516 case ATH9K_M_HOSTAP:
1517 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1518 | AR_STA_ID1_KSRCH_MODE);
1519 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1520 break;
1521 case ATH9K_M_IBSS:
1522 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1523 | AR_STA_ID1_KSRCH_MODE);
1524 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1525 break;
1526 case ATH9K_M_STA:
1527 case ATH9K_M_MONITOR:
1528 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1529 break;
1530 }
1531}
1532
1533static void
1534ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1535{
1536 u32 rfMode = 0;
1537
1538 if (chan == NULL)
1539 return;
1540
1541 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1542 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1543
1544 if (!AR_SREV_9280_10_OR_LATER(ah))
1545 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1546 AR_PHY_MODE_RF2GHZ;
1547
1548 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1549 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1550
1551 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1552}
1553
1554static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1555{
1556 u32 rst_flags;
1557 u32 tmpReg;
1558
1559 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1560 AR_RTC_FORCE_WAKE_ON_INT);
1561
1562 if (AR_SREV_9100(ah)) {
1563 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1564 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1565 } else {
1566 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1567 if (tmpReg &
1568 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1569 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1570 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1571 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1572 } else {
1573 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1574 }
1575
1576 rst_flags = AR_RTC_RC_MAC_WARM;
1577 if (type == ATH9K_RESET_COLD)
1578 rst_flags |= AR_RTC_RC_MAC_COLD;
1579 }
1580
1581 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1582 udelay(50);
1583
1584 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1585 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1586 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1587 "%s: RTC stuck in MAC reset\n",
1588 __func__);
1589 return false;
1590 }
1591
1592 if (!AR_SREV_9100(ah))
1593 REG_WRITE(ah, AR_RC, 0);
1594
1595 ath9k_hw_init_pll(ah, NULL);
1596
1597 if (AR_SREV_9100(ah))
1598 udelay(50);
1599
1600 return true;
1601}
1602
1603static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1604{
1605 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1606 AR_RTC_FORCE_WAKE_ON_INT);
1607
1608 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1609 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1610
1611 if (!ath9k_hw_wait(ah,
1612 AR_RTC_STATUS,
1613 AR_RTC_STATUS_M,
1614 AR_RTC_STATUS_ON)) {
1615 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1616 __func__);
1617 return false;
1618 }
1619
1620 ath9k_hw_read_revisions(ah);
1621
1622 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1623}
1624
1625static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1626 u32 type)
1627{
1628 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1629 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1630
1631 switch (type) {
1632 case ATH9K_RESET_POWER_ON:
1633 return ath9k_hw_set_reset_power_on(ah);
1634 break;
1635 case ATH9K_RESET_WARM:
1636 case ATH9K_RESET_COLD:
1637 return ath9k_hw_set_reset(ah, type);
1638 break;
1639 default:
1640 return false;
1641 }
1642}
1643
1644static
1645struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1646 struct ath9k_channel *chan)
1647{
1648 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1649 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1650 "%s: invalid channel %u/0x%x; not marked as "
1651 "2GHz or 5GHz\n", __func__, chan->channel,
1652 chan->channelFlags);
1653 return NULL;
1654 }
1655
1656 if (!IS_CHAN_OFDM(chan) &&
1657 !IS_CHAN_CCK(chan) &&
1658 !IS_CHAN_HT20(chan) &&
1659 !IS_CHAN_HT40(chan)) {
1660 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1661 "%s: invalid channel %u/0x%x; not marked as "
1662 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1663 __func__, chan->channel, chan->channelFlags);
1664 return NULL;
1665 }
1666
1667 return ath9k_regd_check_channel(ah, chan);
1668}
1669
1670static inline bool
1671ath9k_hw_get_lower_upper_index(u8 target,
1672 u8 *pList,
1673 u16 listSize,
1674 u16 *indexL,
1675 u16 *indexR)
1676{
1677 u16 i;
1678
1679 if (target <= pList[0]) {
1680 *indexL = *indexR = 0;
1681 return true;
1682 }
1683 if (target >= pList[listSize - 1]) {
1684 *indexL = *indexR = (u16) (listSize - 1);
1685 return true;
1686 }
1687
1688 for (i = 0; i < listSize - 1; i++) {
1689 if (pList[i] == target) {
1690 *indexL = *indexR = i;
1691 return true;
1692 }
1693 if (target < pList[i + 1]) {
1694 *indexL = i;
1695 *indexR = (u16) (i + 1);
1696 return false;
1697 }
1698 }
1699 return false;
1700}
1701
1702static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1703{
1704 int16_t nfval;
1705 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
1706 int i, j;
1707
1708 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
1709 sort[i] = nfCalBuffer[i];
1710
1711 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
1712 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
1713 if (sort[j] > sort[j - 1]) {
1714 nfval = sort[j];
1715 sort[j] = sort[j - 1];
1716 sort[j - 1] = nfval;
1717 }
1718 }
1719 }
1720 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
1721
1722 return nfval;
1723}
1724
1725static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
1726 int16_t *nfarray)
1727{ 536{
537 u32 sum;
1728 int i; 538 int i;
1729 539 u16 eeval;
1730 for (i = 0; i < NUM_NF_READINGS; i++) {
1731 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1732
1733 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
1734 h[i].currIndex = 0;
1735
1736 if (h[i].invalidNFcount > 0) {
1737 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1738 || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1739 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
1740 } else {
1741 h[i].invalidNFcount--;
1742 h[i].privNF = nfarray[i];
1743 }
1744 } else {
1745 h[i].privNF =
1746 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1747 }
1748 }
1749 return;
1750}
1751
1752static void ar5416GetNoiseFloor(struct ath_hal *ah,
1753 int16_t nfarray[NUM_NF_READINGS])
1754{
1755 int16_t nf;
1756
1757 if (AR_SREV_9280_10_OR_LATER(ah))
1758 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1759 else
1760 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1761
1762 if (nf & 0x100)
1763 nf = 0 - ((nf ^ 0x1ff) + 1);
1764 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1765 "NF calibrated [ctl] [chain 0] is %d\n", nf);
1766 nfarray[0] = nf;
1767
1768 if (AR_SREV_9280_10_OR_LATER(ah))
1769 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1770 AR9280_PHY_CH1_MINCCA_PWR);
1771 else
1772 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1773 AR_PHY_CH1_MINCCA_PWR);
1774
1775 if (nf & 0x100)
1776 nf = 0 - ((nf ^ 0x1ff) + 1);
1777 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1778 "NF calibrated [ctl] [chain 1] is %d\n", nf);
1779 nfarray[1] = nf;
1780
1781 if (!AR_SREV_9280(ah)) {
1782 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1783 AR_PHY_CH2_MINCCA_PWR);
1784 if (nf & 0x100)
1785 nf = 0 - ((nf ^ 0x1ff) + 1);
1786 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1787 "NF calibrated [ctl] [chain 2] is %d\n", nf);
1788 nfarray[2] = nf;
1789 }
1790
1791 if (AR_SREV_9280_10_OR_LATER(ah))
1792 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1793 AR9280_PHY_EXT_MINCCA_PWR);
1794 else
1795 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1796 AR_PHY_EXT_MINCCA_PWR);
1797
1798 if (nf & 0x100)
1799 nf = 0 - ((nf ^ 0x1ff) + 1);
1800 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1801 "NF calibrated [ext] [chain 0] is %d\n", nf);
1802 nfarray[3] = nf;
1803
1804 if (AR_SREV_9280_10_OR_LATER(ah))
1805 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1806 AR9280_PHY_CH1_EXT_MINCCA_PWR);
1807 else
1808 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1809 AR_PHY_CH1_EXT_MINCCA_PWR);
1810
1811 if (nf & 0x100)
1812 nf = 0 - ((nf ^ 0x1ff) + 1);
1813 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1814 "NF calibrated [ext] [chain 1] is %d\n", nf);
1815 nfarray[4] = nf;
1816
1817 if (!AR_SREV_9280(ah)) {
1818 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1819 AR_PHY_CH2_EXT_MINCCA_PWR);
1820 if (nf & 0x100)
1821 nf = 0 - ((nf ^ 0x1ff) + 1);
1822 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1823 "NF calibrated [ext] [chain 2] is %d\n", nf);
1824 nfarray[5] = nf;
1825 }
1826}
1827
1828static bool
1829getNoiseFloorThresh(struct ath_hal *ah,
1830 const struct ath9k_channel *chan,
1831 int16_t *nft)
1832{
1833 struct ath_hal_5416 *ahp = AH5416(ah); 540 struct ath_hal_5416 *ahp = AH5416(ah);
1834 541
1835 switch (chan->chanmode) { 542 sum = 0;
1836 case CHANNEL_A: 543 for (i = 0; i < 3; i++) {
1837 case CHANNEL_A_HT20: 544 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
1838 case CHANNEL_A_HT40PLUS: 545 sum += eeval;
1839 case CHANNEL_A_HT40MINUS: 546 ahp->ah_macaddr[2 * i] = eeval >> 8;
1840 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5); 547 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1841 break;
1842 case CHANNEL_B:
1843 case CHANNEL_G:
1844 case CHANNEL_G_HT20:
1845 case CHANNEL_G_HT40PLUS:
1846 case CHANNEL_G_HT40MINUS:
1847 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1848 break;
1849 default:
1850 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1851 "%s: invalid channel flags 0x%x\n", __func__,
1852 chan->channelFlags);
1853 return false;
1854 }
1855 return true;
1856}
1857
1858static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1859{
1860 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1861 AR_PHY_AGC_CONTROL_ENABLE_NF);
1862 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1863 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1864 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1865}
1866
1867static void
1868ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
1869{
1870 struct ath9k_nfcal_hist *h;
1871 int i, j;
1872 int32_t val;
1873 const u32 ar5416_cca_regs[6] = {
1874 AR_PHY_CCA,
1875 AR_PHY_CH1_CCA,
1876 AR_PHY_CH2_CCA,
1877 AR_PHY_EXT_CCA,
1878 AR_PHY_CH1_EXT_CCA,
1879 AR_PHY_CH2_EXT_CCA
1880 };
1881 u8 chainmask;
1882
1883 if (AR_SREV_9280(ah))
1884 chainmask = 0x1B;
1885 else
1886 chainmask = 0x3F;
1887
1888#ifdef ATH_NF_PER_CHAN
1889 h = chan->nfCalHist;
1890#else
1891 h = ah->nfCalHist;
1892#endif
1893
1894 for (i = 0; i < NUM_NF_READINGS; i++) {
1895 if (chainmask & (1 << i)) {
1896 val = REG_READ(ah, ar5416_cca_regs[i]);
1897 val &= 0xFFFFFE00;
1898 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1899 REG_WRITE(ah, ar5416_cca_regs[i], val);
1900 }
1901 }
1902
1903 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1904 AR_PHY_AGC_CONTROL_ENABLE_NF);
1905 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1906 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1907 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1908
1909 for (j = 0; j < 1000; j++) {
1910 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1911 AR_PHY_AGC_CONTROL_NF) == 0)
1912 break;
1913 udelay(10);
1914 }
1915
1916 for (i = 0; i < NUM_NF_READINGS; i++) {
1917 if (chainmask & (1 << i)) {
1918 val = REG_READ(ah, ar5416_cca_regs[i]);
1919 val &= 0xFFFFFE00;
1920 val |= (((u32) (-50) << 1) & 0x1ff);
1921 REG_WRITE(ah, ar5416_cca_regs[i], val);
1922 }
1923 }
1924}
1925
1926static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1927 struct ath9k_channel *chan)
1928{
1929 int16_t nf, nfThresh;
1930 int16_t nfarray[NUM_NF_READINGS] = { 0 };
1931 struct ath9k_nfcal_hist *h;
1932 u8 chainmask;
1933
1934 if (AR_SREV_9280(ah))
1935 chainmask = 0x1B;
1936 else
1937 chainmask = 0x3F;
1938
1939 chan->channelFlags &= (~CHANNEL_CW_INT);
1940 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1941 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1942 "%s: NF did not complete in calibration window\n",
1943 __func__);
1944 nf = 0;
1945 chan->rawNoiseFloor = nf;
1946 return chan->rawNoiseFloor;
1947 } else {
1948 ar5416GetNoiseFloor(ah, nfarray);
1949 nf = nfarray[0];
1950 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1951 && nf > nfThresh) {
1952 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1953 "%s: noise floor failed detected; "
1954 "detected %d, threshold %d\n", __func__,
1955 nf, nfThresh);
1956 chan->channelFlags |= CHANNEL_CW_INT;
1957 }
1958 } 548 }
1959 549 if (sum == 0 || sum == 0xffff * 3) {
1960#ifdef ATH_NF_PER_CHAN 550 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1961 h = chan->nfCalHist; 551 "%s: mac address read failed: %pM\n", __func__,
1962#else 552 ahp->ah_macaddr);
1963 h = ah->nfCalHist; 553 return -EADDRNOTAVAIL;
1964#endif
1965
1966 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1967 chan->rawNoiseFloor = h[0].privNF;
1968
1969 return chan->rawNoiseFloor;
1970}
1971
1972static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1973 struct ath9k_mib_stats *stats)
1974{
1975 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1976 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1977 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1978 stats->rts_good += REG_READ(ah, AR_RTS_OK);
1979 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1980}
1981
1982static void ath9k_enable_mib_counters(struct ath_hal *ah)
1983{
1984 struct ath_hal_5416 *ahp = AH5416(ah);
1985
1986 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n");
1987
1988 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
1989
1990 REG_WRITE(ah, AR_FILT_OFDM, 0);
1991 REG_WRITE(ah, AR_FILT_CCK, 0);
1992 REG_WRITE(ah, AR_MIBC,
1993 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
1994 & 0x0f);
1995 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1996 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1997}
1998
1999static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2000{
2001 struct ath_hal_5416 *ahp = AH5416(ah);
2002
2003 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n");
2004
2005 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2006
2007 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2008
2009 REG_WRITE(ah, AR_FILT_OFDM, 0);
2010 REG_WRITE(ah, AR_FILT_CCK, 0);
2011}
2012
2013static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2014 struct ath9k_channel *chan)
2015{
2016 struct ath_hal_5416 *ahp = AH5416(ah);
2017 int i;
2018
2019 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2020 if (ahp->ah_ani[i].c.channel == chan->channel)
2021 return i;
2022 if (ahp->ah_ani[i].c.channel == 0) {
2023 ahp->ah_ani[i].c.channel = chan->channel;
2024 ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2025 return i;
2026 }
2027 } 554 }
2028 555
2029 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2030 "No more channel states left. Using channel 0\n");
2031 return 0; 556 return 0;
2032} 557}
2033 558
2034static void ath9k_hw_ani_attach(struct ath_hal *ah)
2035{
2036 struct ath_hal_5416 *ahp = AH5416(ah);
2037 int i;
2038
2039 ahp->ah_hasHwPhyCounters = 1;
2040
2041 memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2042 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2043 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
2044 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
2045 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
2046 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
2047 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
2048 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
2049 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2050 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
2051 ahp->ah_ani[i].cckWeakSigThreshold =
2052 ATH9K_ANI_CCK_WEAK_SIG_THR;
2053 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
2054 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
2055 if (ahp->ah_hasHwPhyCounters) {
2056 ahp->ah_ani[i].ofdmPhyErrBase =
2057 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
2058 ahp->ah_ani[i].cckPhyErrBase =
2059 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
2060 }
2061 }
2062 if (ahp->ah_hasHwPhyCounters) {
2063 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2064 "Setting OfdmErrBase = 0x%08x\n",
2065 ahp->ah_ani[0].ofdmPhyErrBase);
2066 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2067 ahp->ah_ani[0].cckPhyErrBase);
2068
2069 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2070 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2071 ath9k_enable_mib_counters(ah);
2072 }
2073 ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
2074 if (ah->ah_config.enable_ani)
2075 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2076}
2077
2078static void ath9k_hw_ani_setup(struct ath_hal *ah)
2079{
2080 struct ath_hal_5416 *ahp = AH5416(ah);
2081 int i;
2082
2083 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
2084 const int coarseHigh[] = { -14, -14, -14, -14, -12 };
2085 const int coarseLow[] = { -64, -64, -64, -64, -70 };
2086 const int firpwr[] = { -78, -78, -78, -78, -80 };
2087
2088 for (i = 0; i < 5; i++) {
2089 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
2090 ahp->ah_coarseHigh[i] = coarseHigh[i];
2091 ahp->ah_coarseLow[i] = coarseLow[i];
2092 ahp->ah_firpwr[i] = firpwr[i];
2093 }
2094}
2095
2096static void ath9k_hw_ani_detach(struct ath_hal *ah)
2097{
2098 struct ath_hal_5416 *ahp = AH5416(ah);
2099
2100 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n");
2101 if (ahp->ah_hasHwPhyCounters) {
2102 ath9k_hw_disable_mib_counters(ah);
2103 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2104 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2105 }
2106}
2107
2108
2109static bool ath9k_hw_ani_control(struct ath_hal *ah,
2110 enum ath9k_ani_cmd cmd, int param)
2111{
2112 struct ath_hal_5416 *ahp = AH5416(ah);
2113 struct ar5416AniState *aniState = ahp->ah_curani;
2114
2115 switch (cmd & ahp->ah_ani_function) {
2116 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2117 u32 level = param;
2118
2119 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2120 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2121 "%s: level out of range (%u > %u)\n",
2122 __func__, level,
2123 (unsigned) ARRAY_SIZE(ahp->
2124 ah_totalSizeDesired));
2125 return false;
2126 }
2127
2128 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2129 AR_PHY_DESIRED_SZ_TOT_DES,
2130 ahp->ah_totalSizeDesired[level]);
2131 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2132 AR_PHY_AGC_CTL1_COARSE_LOW,
2133 ahp->ah_coarseLow[level]);
2134 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2135 AR_PHY_AGC_CTL1_COARSE_HIGH,
2136 ahp->ah_coarseHigh[level]);
2137 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2138 AR_PHY_FIND_SIG_FIRPWR,
2139 ahp->ah_firpwr[level]);
2140
2141 if (level > aniState->noiseImmunityLevel)
2142 ahp->ah_stats.ast_ani_niup++;
2143 else if (level < aniState->noiseImmunityLevel)
2144 ahp->ah_stats.ast_ani_nidown++;
2145 aniState->noiseImmunityLevel = level;
2146 break;
2147 }
2148 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2149 const int m1ThreshLow[] = { 127, 50 };
2150 const int m2ThreshLow[] = { 127, 40 };
2151 const int m1Thresh[] = { 127, 0x4d };
2152 const int m2Thresh[] = { 127, 0x40 };
2153 const int m2CountThr[] = { 31, 16 };
2154 const int m2CountThrLow[] = { 63, 48 };
2155 u32 on = param ? 1 : 0;
2156
2157 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2158 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2159 m1ThreshLow[on]);
2160 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2161 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2162 m2ThreshLow[on]);
2163 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2164 AR_PHY_SFCORR_M1_THRESH,
2165 m1Thresh[on]);
2166 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2167 AR_PHY_SFCORR_M2_THRESH,
2168 m2Thresh[on]);
2169 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2170 AR_PHY_SFCORR_M2COUNT_THR,
2171 m2CountThr[on]);
2172 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2173 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2174 m2CountThrLow[on]);
2175
2176 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2177 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2178 m1ThreshLow[on]);
2179 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2180 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2181 m2ThreshLow[on]);
2182 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2183 AR_PHY_SFCORR_EXT_M1_THRESH,
2184 m1Thresh[on]);
2185 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2186 AR_PHY_SFCORR_EXT_M2_THRESH,
2187 m2Thresh[on]);
2188
2189 if (on)
2190 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2191 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2192 else
2193 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2194 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2195
2196 if (!on != aniState->ofdmWeakSigDetectOff) {
2197 if (on)
2198 ahp->ah_stats.ast_ani_ofdmon++;
2199 else
2200 ahp->ah_stats.ast_ani_ofdmoff++;
2201 aniState->ofdmWeakSigDetectOff = !on;
2202 }
2203 break;
2204 }
2205 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2206 const int weakSigThrCck[] = { 8, 6 };
2207 u32 high = param ? 1 : 0;
2208
2209 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2210 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2211 weakSigThrCck[high]);
2212 if (high != aniState->cckWeakSigThreshold) {
2213 if (high)
2214 ahp->ah_stats.ast_ani_cckhigh++;
2215 else
2216 ahp->ah_stats.ast_ani_ccklow++;
2217 aniState->cckWeakSigThreshold = high;
2218 }
2219 break;
2220 }
2221 case ATH9K_ANI_FIRSTEP_LEVEL:{
2222 const int firstep[] = { 0, 4, 8 };
2223 u32 level = param;
2224
2225 if (level >= ARRAY_SIZE(firstep)) {
2226 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2227 "%s: level out of range (%u > %u)\n",
2228 __func__, level,
2229 (unsigned) ARRAY_SIZE(firstep));
2230 return false;
2231 }
2232 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2233 AR_PHY_FIND_SIG_FIRSTEP,
2234 firstep[level]);
2235 if (level > aniState->firstepLevel)
2236 ahp->ah_stats.ast_ani_stepup++;
2237 else if (level < aniState->firstepLevel)
2238 ahp->ah_stats.ast_ani_stepdown++;
2239 aniState->firstepLevel = level;
2240 break;
2241 }
2242 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2243 const int cycpwrThr1[] =
2244 { 2, 4, 6, 8, 10, 12, 14, 16 };
2245 u32 level = param;
2246
2247 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2248 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2249 "%s: level out of range (%u > %u)\n",
2250 __func__, level,
2251 (unsigned)
2252 ARRAY_SIZE(cycpwrThr1));
2253 return false;
2254 }
2255 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2256 AR_PHY_TIMING5_CYCPWR_THR1,
2257 cycpwrThr1[level]);
2258 if (level > aniState->spurImmunityLevel)
2259 ahp->ah_stats.ast_ani_spurup++;
2260 else if (level < aniState->spurImmunityLevel)
2261 ahp->ah_stats.ast_ani_spurdown++;
2262 aniState->spurImmunityLevel = level;
2263 break;
2264 }
2265 case ATH9K_ANI_PRESENT:
2266 break;
2267 default:
2268 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2269 "%s: invalid cmd %u\n", __func__, cmd);
2270 return false;
2271 }
2272
2273 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
2274 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2275 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2276 "ofdmWeakSigDetectOff=%d\n",
2277 aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2278 !aniState->ofdmWeakSigDetectOff);
2279 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2280 "cckWeakSigThreshold=%d, "
2281 "firstepLevel=%d, listenTime=%d\n",
2282 aniState->cckWeakSigThreshold, aniState->firstepLevel,
2283 aniState->listenTime);
2284 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2285 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2286 aniState->cycleCount, aniState->ofdmPhyErrCount,
2287 aniState->cckPhyErrCount);
2288 return true;
2289}
2290
2291static void ath9k_ani_restart(struct ath_hal *ah)
2292{
2293 struct ath_hal_5416 *ahp = AH5416(ah);
2294 struct ar5416AniState *aniState;
2295
2296 if (!DO_ANI(ah))
2297 return;
2298
2299 aniState = ahp->ah_curani;
2300
2301 aniState->listenTime = 0;
2302 if (ahp->ah_hasHwPhyCounters) {
2303 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2304 aniState->ofdmPhyErrBase = 0;
2305 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2306 "OFDM Trigger is too high for hw counters\n");
2307 } else {
2308 aniState->ofdmPhyErrBase =
2309 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2310 }
2311 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2312 aniState->cckPhyErrBase = 0;
2313 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2314 "CCK Trigger is too high for hw counters\n");
2315 } else {
2316 aniState->cckPhyErrBase =
2317 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2318 }
2319 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2320 "%s: Writing ofdmbase=%u cckbase=%u\n",
2321 __func__, aniState->ofdmPhyErrBase,
2322 aniState->cckPhyErrBase);
2323 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2324 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2325 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2326 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2327
2328 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2329 }
2330 aniState->ofdmPhyErrCount = 0;
2331 aniState->cckPhyErrCount = 0;
2332}
2333
2334static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2335{
2336 struct ath_hal_5416 *ahp = AH5416(ah);
2337 struct ath9k_channel *chan = ah->ah_curchan;
2338 struct ar5416AniState *aniState;
2339 enum wireless_mode mode;
2340 int32_t rssi;
2341
2342 if (!DO_ANI(ah))
2343 return;
2344
2345 aniState = ahp->ah_curani;
2346
2347 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2348 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2349 aniState->noiseImmunityLevel + 1)) {
2350 return;
2351 }
2352 }
2353
2354 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2355 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2356 aniState->spurImmunityLevel + 1)) {
2357 return;
2358 }
2359 }
2360
2361 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2362 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2363 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2364 aniState->firstepLevel + 1);
2365 }
2366 return;
2367 }
2368 rssi = BEACON_RSSI(ahp);
2369 if (rssi > aniState->rssiThrHigh) {
2370 if (!aniState->ofdmWeakSigDetectOff) {
2371 if (ath9k_hw_ani_control(ah,
2372 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2373 false)) {
2374 ath9k_hw_ani_control(ah,
2375 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2376 0);
2377 return;
2378 }
2379 }
2380 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2381 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2382 aniState->firstepLevel + 1);
2383 return;
2384 }
2385 } else if (rssi > aniState->rssiThrLow) {
2386 if (aniState->ofdmWeakSigDetectOff)
2387 ath9k_hw_ani_control(ah,
2388 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2389 true);
2390 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2391 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2392 aniState->firstepLevel + 1);
2393 return;
2394 } else {
2395 mode = ath9k_hw_chan2wmode(ah, chan);
2396 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2397 if (!aniState->ofdmWeakSigDetectOff)
2398 ath9k_hw_ani_control(ah,
2399 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2400 false);
2401 if (aniState->firstepLevel > 0)
2402 ath9k_hw_ani_control(ah,
2403 ATH9K_ANI_FIRSTEP_LEVEL,
2404 0);
2405 return;
2406 }
2407 }
2408}
2409
2410static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2411{
2412 struct ath_hal_5416 *ahp = AH5416(ah);
2413 struct ath9k_channel *chan = ah->ah_curchan;
2414 struct ar5416AniState *aniState;
2415 enum wireless_mode mode;
2416 int32_t rssi;
2417
2418 if (!DO_ANI(ah))
2419 return;
2420
2421 aniState = ahp->ah_curani;
2422 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2423 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2424 aniState->noiseImmunityLevel + 1)) {
2425 return;
2426 }
2427 }
2428 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2429 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2430 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2431 aniState->firstepLevel + 1);
2432 }
2433 return;
2434 }
2435 rssi = BEACON_RSSI(ahp);
2436 if (rssi > aniState->rssiThrLow) {
2437 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2438 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2439 aniState->firstepLevel + 1);
2440 } else {
2441 mode = ath9k_hw_chan2wmode(ah, chan);
2442 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2443 if (aniState->firstepLevel > 0)
2444 ath9k_hw_ani_control(ah,
2445 ATH9K_ANI_FIRSTEP_LEVEL,
2446 0);
2447 }
2448 }
2449}
2450
2451static void ath9k_ani_reset(struct ath_hal *ah)
2452{
2453 struct ath_hal_5416 *ahp = AH5416(ah);
2454 struct ar5416AniState *aniState;
2455 struct ath9k_channel *chan = ah->ah_curchan;
2456 int index;
2457
2458 if (!DO_ANI(ah))
2459 return;
2460
2461 index = ath9k_hw_get_ani_channel_idx(ah, chan);
2462 aniState = &ahp->ah_ani[index];
2463 ahp->ah_curani = aniState;
2464
2465 if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
2466 && ah->ah_opmode != ATH9K_M_IBSS) {
2467 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2468 "%s: Reset ANI state opmode %u\n", __func__,
2469 ah->ah_opmode);
2470 ahp->ah_stats.ast_ani_reset++;
2471 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
2472 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
2473 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
2474 ath9k_hw_ani_control(ah,
2475 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2476 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
2477 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2478 ATH9K_ANI_CCK_WEAK_SIG_THR);
2479 ath9k_hw_setrxfilter(ah,
2480 ath9k_hw_getrxfilter(ah) |
2481 ATH9K_RX_FILTER_PHYERR);
2482 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2483 ahp->ah_curani->ofdmTrigHigh =
2484 ah->ah_config.ofdm_trig_high;
2485 ahp->ah_curani->ofdmTrigLow =
2486 ah->ah_config.ofdm_trig_low;
2487 ahp->ah_curani->cckTrigHigh =
2488 ah->ah_config.cck_trig_high;
2489 ahp->ah_curani->cckTrigLow =
2490 ah->ah_config.cck_trig_low;
2491 }
2492 ath9k_ani_restart(ah);
2493 return;
2494 }
2495
2496 if (aniState->noiseImmunityLevel != 0)
2497 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2498 aniState->noiseImmunityLevel);
2499 if (aniState->spurImmunityLevel != 0)
2500 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2501 aniState->spurImmunityLevel);
2502 if (aniState->ofdmWeakSigDetectOff)
2503 ath9k_hw_ani_control(ah,
2504 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2505 !aniState->ofdmWeakSigDetectOff);
2506 if (aniState->cckWeakSigThreshold)
2507 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2508 aniState->cckWeakSigThreshold);
2509 if (aniState->firstepLevel != 0)
2510 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2511 aniState->firstepLevel);
2512 if (ahp->ah_hasHwPhyCounters) {
2513 ath9k_hw_setrxfilter(ah,
2514 ath9k_hw_getrxfilter(ah) &
2515 ~ATH9K_RX_FILTER_PHYERR);
2516 ath9k_ani_restart(ah);
2517 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2518 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2519
2520 } else {
2521 ath9k_ani_restart(ah);
2522 ath9k_hw_setrxfilter(ah,
2523 ath9k_hw_getrxfilter(ah) |
2524 ATH9K_RX_FILTER_PHYERR);
2525 }
2526}
2527
2528/*
2529 * Process a MIB interrupt. We may potentially be invoked because
2530 * any of the MIB counters overflow/trigger so don't assume we're
2531 * here because a PHY error counter triggered.
2532 */
2533void ath9k_hw_procmibevent(struct ath_hal *ah,
2534 const struct ath9k_node_stats *stats)
2535{
2536 struct ath_hal_5416 *ahp = AH5416(ah);
2537 u32 phyCnt1, phyCnt2;
2538
2539 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
2540 /* Reset these counters regardless */
2541 REG_WRITE(ah, AR_FILT_OFDM, 0);
2542 REG_WRITE(ah, AR_FILT_CCK, 0);
2543 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2544 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2545
2546 /* Clear the mib counters and save them in the stats */
2547 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2548 ahp->ah_stats.ast_nodestats = *stats;
2549
2550 if (!DO_ANI(ah))
2551 return;
2552
2553 /* NB: these are not reset-on-read */
2554 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2555 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2556 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2557 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2558 struct ar5416AniState *aniState = ahp->ah_curani;
2559 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2560
2561 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
2562 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2563 ahp->ah_stats.ast_ani_ofdmerrs +=
2564 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2565 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2566
2567 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2568 ahp->ah_stats.ast_ani_cckerrs +=
2569 cckPhyErrCnt - aniState->cckPhyErrCount;
2570 aniState->cckPhyErrCount = cckPhyErrCnt;
2571
2572 /*
2573 * NB: figure out which counter triggered. If both
2574 * trigger we'll only deal with one as the processing
2575 * clobbers the error counter so the trigger threshold
2576 * check will never be true.
2577 */
2578 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2579 ath9k_hw_ani_ofdm_err_trigger(ah);
2580 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2581 ath9k_hw_ani_cck_err_trigger(ah);
2582 /* NB: always restart to insure the h/w counters are reset */
2583 ath9k_ani_restart(ah);
2584 }
2585}
2586
2587static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2588{
2589 struct ath_hal_5416 *ahp = AH5416(ah);
2590 struct ar5416AniState *aniState;
2591 int32_t rssi;
2592
2593 aniState = ahp->ah_curani;
2594
2595 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2596 if (aniState->firstepLevel > 0) {
2597 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2598 aniState->firstepLevel - 1)) {
2599 return;
2600 }
2601 }
2602 } else {
2603 rssi = BEACON_RSSI(ahp);
2604 if (rssi > aniState->rssiThrHigh) {
2605 /* XXX: Handle me */
2606 } else if (rssi > aniState->rssiThrLow) {
2607 if (aniState->ofdmWeakSigDetectOff) {
2608 if (ath9k_hw_ani_control(ah,
2609 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2610 true) ==
2611 true) {
2612 return;
2613 }
2614 }
2615 if (aniState->firstepLevel > 0) {
2616 if (ath9k_hw_ani_control
2617 (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2618 aniState->firstepLevel - 1) ==
2619 true) {
2620 return;
2621 }
2622 }
2623 } else {
2624 if (aniState->firstepLevel > 0) {
2625 if (ath9k_hw_ani_control
2626 (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2627 aniState->firstepLevel - 1) ==
2628 true) {
2629 return;
2630 }
2631 }
2632 }
2633 }
2634
2635 if (aniState->spurImmunityLevel > 0) {
2636 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2637 aniState->spurImmunityLevel - 1)) {
2638 return;
2639 }
2640 }
2641
2642 if (aniState->noiseImmunityLevel > 0) {
2643 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2644 aniState->noiseImmunityLevel - 1);
2645 return;
2646 }
2647}
2648
2649static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2650{
2651 struct ath_hal_5416 *ahp = AH5416(ah);
2652 struct ar5416AniState *aniState;
2653 u32 txFrameCount, rxFrameCount, cycleCount;
2654 int32_t listenTime;
2655
2656 txFrameCount = REG_READ(ah, AR_TFCNT);
2657 rxFrameCount = REG_READ(ah, AR_RFCNT);
2658 cycleCount = REG_READ(ah, AR_CCCNT);
2659
2660 aniState = ahp->ah_curani;
2661 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2662
2663 listenTime = 0;
2664 ahp->ah_stats.ast_ani_lzero++;
2665 } else {
2666 int32_t ccdelta = cycleCount - aniState->cycleCount;
2667 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2668 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2669 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2670 }
2671 aniState->cycleCount = cycleCount;
2672 aniState->txFrameCount = txFrameCount;
2673 aniState->rxFrameCount = rxFrameCount;
2674
2675 return listenTime;
2676}
2677
2678void ath9k_hw_ani_monitor(struct ath_hal *ah,
2679 const struct ath9k_node_stats *stats,
2680 struct ath9k_channel *chan)
2681{
2682 struct ath_hal_5416 *ahp = AH5416(ah);
2683 struct ar5416AniState *aniState;
2684 int32_t listenTime;
2685
2686 aniState = ahp->ah_curani;
2687 ahp->ah_stats.ast_nodestats = *stats;
2688
2689 listenTime = ath9k_hw_ani_get_listen_time(ah);
2690 if (listenTime < 0) {
2691 ahp->ah_stats.ast_ani_lneg++;
2692 ath9k_ani_restart(ah);
2693 return;
2694 }
2695
2696 aniState->listenTime += listenTime;
2697
2698 if (ahp->ah_hasHwPhyCounters) {
2699 u32 phyCnt1, phyCnt2;
2700 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2701
2702 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2703
2704 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2705 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2706
2707 if (phyCnt1 < aniState->ofdmPhyErrBase ||
2708 phyCnt2 < aniState->cckPhyErrBase) {
2709 if (phyCnt1 < aniState->ofdmPhyErrBase) {
2710 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2711 "%s: phyCnt1 0x%x, resetting "
2712 "counter value to 0x%x\n",
2713 __func__, phyCnt1,
2714 aniState->ofdmPhyErrBase);
2715 REG_WRITE(ah, AR_PHY_ERR_1,
2716 aniState->ofdmPhyErrBase);
2717 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
2718 AR_PHY_ERR_OFDM_TIMING);
2719 }
2720 if (phyCnt2 < aniState->cckPhyErrBase) {
2721 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2722 "%s: phyCnt2 0x%x, resetting "
2723 "counter value to 0x%x\n",
2724 __func__, phyCnt2,
2725 aniState->cckPhyErrBase);
2726 REG_WRITE(ah, AR_PHY_ERR_2,
2727 aniState->cckPhyErrBase);
2728 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
2729 AR_PHY_ERR_CCK_TIMING);
2730 }
2731 return;
2732 }
2733
2734 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2735 ahp->ah_stats.ast_ani_ofdmerrs +=
2736 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2737 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2738
2739 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2740 ahp->ah_stats.ast_ani_cckerrs +=
2741 cckPhyErrCnt - aniState->cckPhyErrCount;
2742 aniState->cckPhyErrCount = cckPhyErrCnt;
2743 }
2744
2745 if (!DO_ANI(ah))
2746 return;
2747
2748 if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
2749 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
2750 aniState->ofdmTrigLow / 1000 &&
2751 aniState->cckPhyErrCount <= aniState->listenTime *
2752 aniState->cckTrigLow / 1000)
2753 ath9k_hw_ani_lower_immunity(ah);
2754 ath9k_ani_restart(ah);
2755 } else if (aniState->listenTime > ahp->ah_aniPeriod) {
2756 if (aniState->ofdmPhyErrCount > aniState->listenTime *
2757 aniState->ofdmTrigHigh / 1000) {
2758 ath9k_hw_ani_ofdm_err_trigger(ah);
2759 ath9k_ani_restart(ah);
2760 } else if (aniState->cckPhyErrCount >
2761 aniState->listenTime * aniState->cckTrigHigh /
2762 1000) {
2763 ath9k_hw_ani_cck_err_trigger(ah);
2764 ath9k_ani_restart(ah);
2765 }
2766 }
2767}
2768
2769#ifndef ATH_NF_PER_CHAN
2770static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
2771{
2772 int i, j;
2773
2774 for (i = 0; i < NUM_NF_READINGS; i++) {
2775 ah->nfCalHist[i].currIndex = 0;
2776 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
2777 ah->nfCalHist[i].invalidNFcount =
2778 AR_PHY_CCA_FILTERWINDOW_LENGTH;
2779 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
2780 ah->nfCalHist[i].nfCalBuffer[j] =
2781 AR_PHY_CCA_MAX_GOOD_VALUE;
2782 }
2783 }
2784 return;
2785}
2786#endif
2787
2788static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
2789 u32 gpio, u32 type)
2790{
2791 int addr;
2792 u32 gpio_shift, tmp;
2793
2794 if (gpio > 11)
2795 addr = AR_GPIO_OUTPUT_MUX3;
2796 else if (gpio > 5)
2797 addr = AR_GPIO_OUTPUT_MUX2;
2798 else
2799 addr = AR_GPIO_OUTPUT_MUX1;
2800
2801 gpio_shift = (gpio % 6) * 5;
2802
2803 if (AR_SREV_9280_20_OR_LATER(ah)
2804 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2805 REG_RMW(ah, addr, (type << gpio_shift),
2806 (0x1f << gpio_shift));
2807 } else {
2808 tmp = REG_READ(ah, addr);
2809 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2810 tmp &= ~(0x1f << gpio_shift);
2811 tmp |= (type << gpio_shift);
2812 REG_WRITE(ah, addr, tmp);
2813 }
2814}
2815
2816void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
2817 u32 ah_signal_type)
2818{
2819 u32 gpio_shift;
2820
2821 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2822
2823 gpio_shift = 2 * gpio;
2824
2825 REG_RMW(ah,
2826 AR_GPIO_OE_OUT,
2827 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2828 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2829}
2830
2831void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
2832{
2833 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2834 AR_GPIO_BIT(gpio));
2835}
2836
2837/*
2838 * Configure GPIO Input lines
2839 */
2840void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
2841{
2842 u32 gpio_shift;
2843
2844 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
2845
2846 gpio_shift = gpio << 1;
2847
2848 REG_RMW(ah,
2849 AR_GPIO_OE_OUT,
2850 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2851 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2852}
2853
2854#ifdef CONFIG_RFKILL
2855static void ath9k_enable_rfkill(struct ath_hal *ah)
2856{
2857 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2858 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2859
2860 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2861 AR_GPIO_INPUT_MUX2_RFSILENT);
2862
2863 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
2864 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2865}
2866#endif
2867
2868u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
2869{
2870 if (gpio >= ah->ah_caps.num_gpio_pins)
2871 return 0xffffffff;
2872
2873 if (AR_SREV_9280_10_OR_LATER(ah)) {
2874 return (MS
2875 (REG_READ(ah, AR_GPIO_IN_OUT),
2876 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
2877 } else {
2878 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
2879 AR_GPIO_BIT(gpio)) != 0;
2880 }
2881}
2882
2883static int ath9k_hw_post_attach(struct ath_hal *ah) 559static int ath9k_hw_post_attach(struct ath_hal *ah)
2884{ 560{
2885 int ecode; 561 int ecode;
2886 562
2887 if (!ath9k_hw_chip_test(ah)) { 563 if (!ath9k_hw_chip_test(ah)) {
2888 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 564 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2889 "%s: hardware self-test failed\n", __func__); 565 "%s: hardware self-test failed\n", __func__);
2890 return -ENODEV; 566 return -ENODEV;
2891 } 567 }
2892 568
@@ -2905,357 +581,12 @@ static int ath9k_hw_post_attach(struct ath_hal *ah)
2905 ath9k_hw_ani_setup(ah); 581 ath9k_hw_ani_setup(ah);
2906 ath9k_hw_ani_attach(ah); 582 ath9k_hw_ani_attach(ah);
2907 } 583 }
2908 return 0;
2909}
2910
2911static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
2912 struct ar5416_eeprom *pEepData,
2913 u32 reg, u32 value)
2914{
2915 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
2916
2917 switch (ah->ah_devid) {
2918 case AR9280_DEVID_PCI:
2919 if (reg == 0x7894) {
2920 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2921 "ini VAL: %x EEPROM: %x\n", value,
2922 (pBase->version & 0xff));
2923
2924 if ((pBase->version & 0xff) > 0x0a) {
2925 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2926 "PWDCLKIND: %d\n",
2927 pBase->pwdclkind);
2928 value &= ~AR_AN_TOP2_PWDCLKIND;
2929 value |= AR_AN_TOP2_PWDCLKIND & (pBase->
2930 pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
2931 } else {
2932 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2933 "PWDCLKIND Earlier Rev\n");
2934 }
2935
2936 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2937 "final ini VAL: %x\n", value);
2938 }
2939 break;
2940 }
2941 return value;
2942}
2943
2944static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2945{
2946 struct ath_hal_5416 *ahp = AH5416(ah);
2947 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2948 u16 capField = 0, eeval;
2949
2950 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
2951
2952 ah->ah_currentRD = eeval;
2953
2954 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1);
2955 ah->ah_currentRDExt = eeval;
2956
2957 capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
2958
2959 if (ah->ah_opmode != ATH9K_M_HOSTAP &&
2960 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2961 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
2962 ah->ah_currentRD += 5;
2963 else if (ah->ah_currentRD == 0x41)
2964 ah->ah_currentRD = 0x43;
2965 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
2966 "%s: regdomain mapped to 0x%x\n", __func__,
2967 ah->ah_currentRD);
2968 }
2969
2970 eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2971 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2972 584
2973 if (eeval & AR5416_OPFLAGS_11A) { 585 return 0;
2974 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2975 if (ah->ah_config.ht_enable) {
2976 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2977 set_bit(ATH9K_MODE_11NA_HT20,
2978 pCap->wireless_modes);
2979 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2980 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2981 pCap->wireless_modes);
2982 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2983 pCap->wireless_modes);
2984 }
2985 }
2986 }
2987
2988 if (eeval & AR5416_OPFLAGS_11G) {
2989 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
2990 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2991 if (ah->ah_config.ht_enable) {
2992 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2993 set_bit(ATH9K_MODE_11NG_HT20,
2994 pCap->wireless_modes);
2995 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2996 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2997 pCap->wireless_modes);
2998 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2999 pCap->wireless_modes);
3000 }
3001 }
3002 }
3003
3004 pCap->tx_chainmask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
3005 if ((ah->ah_isPciExpress)
3006 || (eeval & AR5416_OPFLAGS_11A)) {
3007 pCap->rx_chainmask =
3008 ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
3009 } else {
3010 pCap->rx_chainmask =
3011 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3012 }
3013
3014 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3015 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3016
3017 pCap->low_2ghz_chan = 2312;
3018 pCap->high_2ghz_chan = 2732;
3019
3020 pCap->low_5ghz_chan = 4920;
3021 pCap->high_5ghz_chan = 6100;
3022
3023 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3024 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3025 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3026
3027 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3028 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3029 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3030
3031 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3032
3033 if (ah->ah_config.ht_enable)
3034 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3035 else
3036 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3037
3038 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3039 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3040 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3041 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3042
3043 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3044 pCap->total_queues =
3045 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3046 else
3047 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3048
3049 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3050 pCap->keycache_size =
3051 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3052 else
3053 pCap->keycache_size = AR_KEYTABLE_SIZE;
3054
3055 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3056 pCap->num_mr_retries = 4;
3057 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3058
3059 if (AR_SREV_9280_10_OR_LATER(ah))
3060 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3061 else
3062 pCap->num_gpio_pins = AR_NUM_GPIO;
3063
3064 if (AR_SREV_9280_10_OR_LATER(ah)) {
3065 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3066 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3067 } else {
3068 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3069 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3070 }
3071
3072 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3073 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3074 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3075 } else {
3076 pCap->rts_aggr_limit = (8 * 1024);
3077 }
3078
3079 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3080
3081#ifdef CONFIG_RFKILL
3082 ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3083 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3084 ah->ah_rfkill_gpio =
3085 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3086 ah->ah_rfkill_polarity =
3087 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3088
3089 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3090 }
3091#endif
3092
3093 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3094 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3095 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3096 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3097 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3098 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3099 else
3100 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3101
3102 if (AR_SREV_9280(ah))
3103 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3104 else
3105 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3106
3107 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3108 pCap->reg_cap =
3109 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3110 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3111 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3112 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3113 } else {
3114 pCap->reg_cap =
3115 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3116 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3117 }
3118
3119 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3120
3121 pCap->num_antcfg_5ghz =
3122 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_5GHZ);
3123 pCap->num_antcfg_2ghz =
3124 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_2GHZ);
3125
3126 return true;
3127}
3128
3129static void ar5416DisablePciePhy(struct ath_hal *ah)
3130{
3131 if (!AR_SREV_9100(ah))
3132 return;
3133
3134 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3135 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3136 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
3137 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
3138 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
3139 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
3140 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3141 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3142 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
3143
3144 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3145}
3146
3147static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
3148{
3149 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3150 if (setChip) {
3151 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3152 AR_RTC_FORCE_WAKE_EN);
3153 if (!AR_SREV_9100(ah))
3154 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
3155
3156 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
3157 AR_RTC_RESET_EN);
3158 }
3159}
3160
3161static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3162{
3163 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3164 if (setChip) {
3165 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3166
3167 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3168 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3169 AR_RTC_FORCE_WAKE_ON_INT);
3170 } else {
3171 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3172 AR_RTC_FORCE_WAKE_EN);
3173 }
3174 }
3175}
3176
3177static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
3178 int setChip)
3179{
3180 u32 val;
3181 int i;
3182
3183 if (setChip) {
3184 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
3185 AR_RTC_STATUS_SHUTDOWN) {
3186 if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)
3187 != true) {
3188 return false;
3189 }
3190 }
3191 if (AR_SREV_9100(ah))
3192 REG_SET_BIT(ah, AR_RTC_RESET,
3193 AR_RTC_RESET_EN);
3194
3195 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3196 AR_RTC_FORCE_WAKE_EN);
3197 udelay(50);
3198
3199 for (i = POWER_UP_TIME / 50; i > 0; i--) {
3200 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
3201 if (val == AR_RTC_STATUS_ON)
3202 break;
3203 udelay(50);
3204 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3205 AR_RTC_FORCE_WAKE_EN);
3206 }
3207 if (i == 0) {
3208 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3209 "%s: Failed to wakeup in %uus\n",
3210 __func__, POWER_UP_TIME / 20);
3211 return false;
3212 }
3213 }
3214
3215 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3216 return true;
3217}
3218
3219bool ath9k_hw_setpower(struct ath_hal *ah,
3220 enum ath9k_power_mode mode)
3221{
3222 struct ath_hal_5416 *ahp = AH5416(ah);
3223 static const char *modes[] = {
3224 "AWAKE",
3225 "FULL-SLEEP",
3226 "NETWORK SLEEP",
3227 "UNDEFINED"
3228 };
3229 int status = true, setChip = true;
3230
3231 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
3232 modes[ahp->ah_powerMode], modes[mode],
3233 setChip ? "set chip " : "");
3234
3235 switch (mode) {
3236 case ATH9K_PM_AWAKE:
3237 status = ath9k_hw_set_power_awake(ah, setChip);
3238 break;
3239 case ATH9K_PM_FULL_SLEEP:
3240 ath9k_set_power_sleep(ah, setChip);
3241 ahp->ah_chipFullSleep = true;
3242 break;
3243 case ATH9K_PM_NETWORK_SLEEP:
3244 ath9k_set_power_network_sleep(ah, setChip);
3245 break;
3246 default:
3247 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3248 "%s: unknown power mode %u\n", __func__, mode);
3249 return false;
3250 }
3251 ahp->ah_powerMode = mode;
3252 return status;
3253} 586}
3254 587
3255static struct ath_hal *ath9k_hw_do_attach(u16 devid, 588static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
3256 struct ath_softc *sc, 589 void __iomem *mem, int *status)
3257 void __iomem *mem,
3258 int *status)
3259{ 590{
3260 struct ath_hal_5416 *ahp; 591 struct ath_hal_5416 *ahp;
3261 struct ath_hal *ah; 592 struct ath_hal *ah;
@@ -3299,6 +630,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3299 SER_REG_MODE_OFF; 630 SER_REG_MODE_OFF;
3300 } 631 }
3301 } 632 }
633
3302 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 634 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3303 "%s: serialize_regmode is %d\n", 635 "%s: serialize_regmode is %d\n",
3304 __func__, ah->ah_config.serialize_regmode); 636 __func__, ah->ah_config.serialize_regmode);
@@ -3308,9 +640,9 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3308 (ah->ah_macVersion != AR_SREV_VERSION_9160) && 640 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
3309 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) { 641 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
3310 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 642 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3311 "%s: Mac Chip Rev 0x%02x.%x is not supported by " 643 "%s: Mac Chip Rev 0x%02x.%x is not supported by "
3312 "this driver\n", __func__, 644 "this driver\n", __func__,
3313 ah->ah_macVersion, ah->ah_macRev); 645 ah->ah_macVersion, ah->ah_macRev);
3314 ecode = -EOPNOTSUPP; 646 ecode = -EOPNOTSUPP;
3315 goto bad; 647 goto bad;
3316 } 648 }
@@ -3340,8 +672,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3340 ahp->ah_adcDcCalInitData.calData = 672 ahp->ah_adcDcCalInitData.calData =
3341 &adc_init_dc_cal; 673 &adc_init_dc_cal;
3342 } 674 }
3343 ahp->ah_suppCals = 675 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3344 ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3345 } 676 }
3346 677
3347 if (AR_SREV_9160(ah)) { 678 if (AR_SREV_9160(ah)) {
@@ -3351,14 +682,13 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3351 } else { 682 } else {
3352 ahp->ah_ani_function = ATH9K_ANI_ALL; 683 ahp->ah_ani_function = ATH9K_ANI_ALL;
3353 if (AR_SREV_9280_10_OR_LATER(ah)) { 684 if (AR_SREV_9280_10_OR_LATER(ah)) {
3354 ahp->ah_ani_function &= 685 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
3355 ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
3356 } 686 }
3357 } 687 }
3358 688
3359 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 689 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3360 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 690 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
3361 ah->ah_macVersion, ah->ah_macRev); 691 ah->ah_macVersion, ah->ah_macRev);
3362 692
3363 if (AR_SREV_9280_20_OR_LATER(ah)) { 693 if (AR_SREV_9280_20_OR_LATER(ah)) {
3364 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, 694 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
@@ -3368,21 +698,16 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3368 698
3369 if (ah->ah_config.pcie_clock_req) { 699 if (ah->ah_config.pcie_clock_req) {
3370 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 700 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3371 ar9280PciePhy_clkreq_off_L1_9280, 701 ar9280PciePhy_clkreq_off_L1_9280,
3372 ARRAY_SIZE 702 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
3373 (ar9280PciePhy_clkreq_off_L1_9280),
3374 2);
3375 } else { 703 } else {
3376 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 704 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3377 ar9280PciePhy_clkreq_always_on_L1_9280, 705 ar9280PciePhy_clkreq_always_on_L1_9280,
3378 ARRAY_SIZE 706 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
3379 (ar9280PciePhy_clkreq_always_on_L1_9280),
3380 2);
3381 } 707 }
3382 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, 708 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
3383 ar9280Modes_fast_clock_9280_2, 709 ar9280Modes_fast_clock_9280_2,
3384 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 710 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
3385 3);
3386 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 711 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
3387 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, 712 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
3388 ARRAY_SIZE(ar9280Modes_9280), 6); 713 ARRAY_SIZE(ar9280Modes_9280), 6);
@@ -3468,7 +793,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3468 if (ah->ah_isPciExpress) 793 if (ah->ah_isPciExpress)
3469 ath9k_hw_configpcipowersave(ah, 0); 794 ath9k_hw_configpcipowersave(ah, 0);
3470 else 795 else
3471 ar5416DisablePciePhy(ah); 796 ath9k_hw_disablepcie(ah);
3472 797
3473 ecode = ath9k_hw_post_attach(ah); 798 ecode = ath9k_hw_post_attach(ah);
3474 if (ecode != 0) 799 if (ecode != 0)
@@ -3489,10 +814,9 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3489 } 814 }
3490 } 815 }
3491#endif 816#endif
3492
3493 if (!ath9k_hw_fill_cap_info(ah)) { 817 if (!ath9k_hw_fill_cap_info(ah)) {
3494 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 818 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3495 "%s:failed ath9k_hw_fill_cap_info\n", __func__); 819 "%s:failed ath9k_hw_fill_cap_info\n", __func__);
3496 ecode = -EINVAL; 820 ecode = -EINVAL;
3497 goto bad; 821 goto bad;
3498 } 822 }
@@ -3500,8 +824,8 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3500 ecode = ath9k_hw_init_macaddr(ah); 824 ecode = ath9k_hw_init_macaddr(ah);
3501 if (ecode != 0) { 825 if (ecode != 0) {
3502 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 826 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3503 "%s: failed initializing mac address\n", 827 "%s: failed initializing mac address\n",
3504 __func__); 828 __func__);
3505 goto bad; 829 goto bad;
3506 } 830 }
3507 831
@@ -3510,1106 +834,553 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3510 else 834 else
3511 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); 835 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
3512 836
3513#ifndef ATH_NF_PER_CHAN
3514
3515 ath9k_init_nfcal_hist_buffer(ah); 837 ath9k_init_nfcal_hist_buffer(ah);
3516#endif
3517 838
3518 return ah; 839 return ah;
3519
3520bad: 840bad:
3521 if (ahp) 841 if (ahp)
3522 ath9k_hw_detach((struct ath_hal *) ahp); 842 ath9k_hw_detach((struct ath_hal *) ahp);
3523 if (status) 843 if (status)
3524 *status = ecode; 844 *status = ecode;
845
3525 return NULL; 846 return NULL;
3526} 847}
3527 848
3528void ath9k_hw_detach(struct ath_hal *ah) 849static void ath9k_hw_init_bb(struct ath_hal *ah,
850 struct ath9k_channel *chan)
3529{ 851{
3530 if (!AR_SREV_9100(ah)) 852 u32 synthDelay;
3531 ath9k_hw_ani_detach(ah);
3532 ath9k_hw_rfdetach(ah);
3533 853
3534 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 854 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
3535 kfree(ah); 855 if (IS_CHAN_CCK(chan))
856 synthDelay = (4 * synthDelay) / 22;
857 else
858 synthDelay /= 10;
859
860 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
861
862 udelay(synthDelay + BASE_ACTIVATE_DELAY);
3536} 863}
3537 864
3538bool ath9k_get_channel_edges(struct ath_hal *ah, 865static void ath9k_hw_init_qos(struct ath_hal *ah)
3539 u16 flags, u16 *low,
3540 u16 *high)
3541{ 866{
3542 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 867 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
868 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
3543 869
3544 if (flags & CHANNEL_5GHZ) { 870 REG_WRITE(ah, AR_QOS_NO_ACK,
3545 *low = pCap->low_5ghz_chan; 871 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
3546 *high = pCap->high_5ghz_chan; 872 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
3547 return true; 873 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
3548 }
3549 if ((flags & CHANNEL_2GHZ)) {
3550 *low = pCap->low_2ghz_chan;
3551 *high = pCap->high_2ghz_chan;
3552 874
3553 return true; 875 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
3554 } 876 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
3555 return false; 877 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
878 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
879 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
3556} 880}
3557 881
3558static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, 882static void ath9k_hw_init_pll(struct ath_hal *ah,
3559 u8 pwrMax, 883 struct ath9k_channel *chan)
3560 u8 *pPwrList,
3561 u8 *pVpdList,
3562 u16
3563 numIntercepts,
3564 u8 *pRetVpdList)
3565{ 884{
3566 u16 i, k; 885 u32 pll;
3567 u8 currPwr = pwrMin;
3568 u16 idxL = 0, idxR = 0;
3569
3570 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
3571 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
3572 numIntercepts, &(idxL),
3573 &(idxR));
3574 if (idxR < 1)
3575 idxR = 1;
3576 if (idxL == numIntercepts - 1)
3577 idxL = (u16) (numIntercepts - 2);
3578 if (pPwrList[idxL] == pPwrList[idxR])
3579 k = pVpdList[idxL];
3580 else
3581 k = (u16) (((currPwr -
3582 pPwrList[idxL]) *
3583 pVpdList[idxR] +
3584 (pPwrList[idxR] -
3585 currPwr) * pVpdList[idxL]) /
3586 (pPwrList[idxR] -
3587 pPwrList[idxL]));
3588 pRetVpdList[i] = (u8) k;
3589 currPwr += 2;
3590 }
3591 886
3592 return true; 887 if (AR_SREV_9100(ah)) {
3593} 888 if (chan && IS_CHAN_5GHZ(chan))
889 pll = 0x1450;
890 else
891 pll = 0x1458;
892 } else {
893 if (AR_SREV_9280_10_OR_LATER(ah)) {
894 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
3594 895
3595static void 896 if (chan && IS_CHAN_HALF_RATE(chan))
3596ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah, 897 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
3597 struct ath9k_channel *chan, 898 else if (chan && IS_CHAN_QUARTER_RATE(chan))
3598 struct cal_data_per_freq *pRawDataSet, 899 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
3599 u8 *bChans,
3600 u16 availPiers,
3601 u16 tPdGainOverlap,
3602 int16_t *pMinCalPower,
3603 u16 *pPdGainBoundaries,
3604 u8 *pPDADCValues,
3605 u16 numXpdGains)
3606{
3607 int i, j, k;
3608 int16_t ss;
3609 u16 idxL = 0, idxR = 0, numPiers;
3610 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
3611 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3612 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
3613 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3614 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
3615 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3616
3617 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3618 u8 minPwrT4[AR5416_NUM_PD_GAINS];
3619 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
3620 int16_t vpdStep;
3621 int16_t tmpVal;
3622 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
3623 bool match;
3624 int16_t minDelta = 0;
3625 struct chan_centers centers;
3626 900
3627 ath9k_hw_get_channel_centers(ah, chan, &centers); 901 if (chan && IS_CHAN_5GHZ(chan)) {
902 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
3628 903
3629 for (numPiers = 0; numPiers < availPiers; numPiers++) {
3630 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
3631 break;
3632 }
3633 904
3634 match = ath9k_hw_get_lower_upper_index((u8) 905 if (AR_SREV_9280_20(ah)) {
3635 FREQ2FBIN(centers. 906 if (((chan->channel % 20) == 0)
3636 synth_center, 907 || ((chan->channel % 10) == 0))
3637 IS_CHAN_2GHZ 908 pll = 0x2850;
3638 (chan)), bChans, 909 else
3639 numPiers, &idxL, &idxR); 910 pll = 0x142c;
3640 911 }
3641 if (match) { 912 } else {
3642 for (i = 0; i < numXpdGains; i++) { 913 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
3643 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3644 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3645 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3646 pRawDataSet[idxL].
3647 pwrPdg[i],
3648 pRawDataSet[idxL].
3649 vpdPdg[i],
3650 AR5416_PD_GAIN_ICEPTS,
3651 vpdTableI[i]);
3652 }
3653 } else {
3654 for (i = 0; i < numXpdGains; i++) {
3655 pVpdL = pRawDataSet[idxL].vpdPdg[i];
3656 pPwrL = pRawDataSet[idxL].pwrPdg[i];
3657 pVpdR = pRawDataSet[idxR].vpdPdg[i];
3658 pPwrR = pRawDataSet[idxR].pwrPdg[i];
3659
3660 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3661
3662 maxPwrT4[i] =
3663 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
3664 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
3665
3666
3667 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3668 pPwrL, pVpdL,
3669 AR5416_PD_GAIN_ICEPTS,
3670 vpdTableL[i]);
3671 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3672 pPwrR, pVpdR,
3673 AR5416_PD_GAIN_ICEPTS,
3674 vpdTableR[i]);
3675
3676 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3677 vpdTableI[i][j] =
3678 (u8) (ath9k_hw_interpolate
3679 ((u16)
3680 FREQ2FBIN(centers.
3681 synth_center,
3682 IS_CHAN_2GHZ
3683 (chan)),
3684 bChans[idxL],
3685 bChans[idxR], vpdTableL[i]
3686 [j], vpdTableR[i]
3687 [j]));
3688 } 914 }
3689 }
3690 }
3691 915
3692 *pMinCalPower = (int16_t) (minPwrT4[0] / 2); 916 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
3693
3694 k = 0;
3695 for (i = 0; i < numXpdGains; i++) {
3696 if (i == (numXpdGains - 1))
3697 pPdGainBoundaries[i] =
3698 (u16) (maxPwrT4[i] / 2);
3699 else
3700 pPdGainBoundaries[i] =
3701 (u16) ((maxPwrT4[i] +
3702 minPwrT4[i + 1]) / 4);
3703 917
3704 pPdGainBoundaries[i] = 918 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
3705 min((u16) AR5416_MAX_RATE_POWER,
3706 pPdGainBoundaries[i]);
3707 919
3708 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { 920 if (chan && IS_CHAN_HALF_RATE(chan))
3709 minDelta = pPdGainBoundaries[0] - 23; 921 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
3710 pPdGainBoundaries[0] = 23; 922 else if (chan && IS_CHAN_QUARTER_RATE(chan))
3711 } else { 923 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
3712 minDelta = 0;
3713 }
3714 924
3715 if (i == 0) { 925 if (chan && IS_CHAN_5GHZ(chan))
3716 if (AR_SREV_9280_10_OR_LATER(ah)) 926 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
3717 ss = (int16_t) (0 - (minPwrT4[i] / 2));
3718 else 927 else
3719 ss = 0; 928 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
3720 } else { 929 } else {
3721 ss = (int16_t) ((pPdGainBoundaries[i - 1] - 930 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
3722 (minPwrT4[i] / 2)) -
3723 tPdGainOverlap + 1 + minDelta);
3724 }
3725 vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]);
3726 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3727
3728 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3729 tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
3730 pPDADCValues[k++] =
3731 (u8) ((tmpVal < 0) ? 0 : tmpVal);
3732 ss++;
3733 }
3734
3735 sizeCurrVpdTable =
3736 (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3737 tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap -
3738 (minPwrT4[i] / 2));
3739 maxIndex = (tgtIndex <
3740 sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
3741 931
3742 while ((ss < maxIndex) 932 if (chan && IS_CHAN_HALF_RATE(chan))
3743 && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 933 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
3744 pPDADCValues[k++] = vpdTableI[i][ss++]; 934 else if (chan && IS_CHAN_QUARTER_RATE(chan))
3745 } 935 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
3746 936
3747 vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] - 937 if (chan && IS_CHAN_5GHZ(chan))
3748 vpdTableI[i][sizeCurrVpdTable - 2]); 938 pll |= SM(0xa, AR_RTC_PLL_DIV);
3749 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep); 939 else
3750 940 pll |= SM(0xb, AR_RTC_PLL_DIV);
3751 if (tgtIndex > maxIndex) {
3752 while ((ss <= tgtIndex)
3753 && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3754 tmpVal = (int16_t) ((vpdTableI[i]
3755 [sizeCurrVpdTable -
3756 1] + (ss - maxIndex +
3757 1) * vpdStep));
3758 pPDADCValues[k++] = (u8) ((tmpVal >
3759 255) ? 255 : tmpVal);
3760 ss++;
3761 }
3762 } 941 }
3763 } 942 }
943 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
3764 944
3765 while (i < AR5416_PD_GAINS_IN_MASK) { 945 udelay(RTC_PLL_SETTLE_DELAY);
3766 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
3767 i++;
3768 }
3769 946
3770 while (k < AR5416_NUM_PDADC_VALUES) { 947 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
3771 pPDADCValues[k] = pPDADCValues[k - 1];
3772 k++;
3773 }
3774 return;
3775} 948}
3776 949
3777static bool 950static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
3778ath9k_hw_set_power_cal_table(struct ath_hal *ah,
3779 struct ar5416_eeprom *pEepData,
3780 struct ath9k_channel *chan,
3781 int16_t *pTxPowerIndexOffset)
3782{ 951{
3783 struct cal_data_per_freq *pRawDataset;
3784 u8 *pCalBChans = NULL;
3785 u16 pdGainOverlap_t2;
3786 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
3787 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
3788 u16 numPiers, i, j;
3789 int16_t tMinCalPower;
3790 u16 numXpdGain, xpdMask;
3791 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
3792 u32 reg32, regOffset, regChainOffset;
3793 int16_t modalIdx;
3794 struct ath_hal_5416 *ahp = AH5416(ah); 952 struct ath_hal_5416 *ahp = AH5416(ah);
953 int rx_chainmask, tx_chainmask;
3795 954
3796 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; 955 rx_chainmask = ahp->ah_rxchainmask;
3797 xpdMask = pEepData->modalHeader[modalIdx].xpdGain; 956 tx_chainmask = ahp->ah_txchainmask;
3798
3799 if ((pEepData->baseEepHeader.
3800 version & AR5416_EEP_VER_MINOR_MASK) >=
3801 AR5416_EEP_MINOR_VER_2) {
3802 pdGainOverlap_t2 =
3803 pEepData->modalHeader[modalIdx].pdGainOverlap;
3804 } else {
3805 pdGainOverlap_t2 =
3806 (u16) (MS
3807 (REG_READ(ah, AR_PHY_TPCRG5),
3808 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3809 }
3810
3811 if (IS_CHAN_2GHZ(chan)) {
3812 pCalBChans = pEepData->calFreqPier2G;
3813 numPiers = AR5416_NUM_2G_CAL_PIERS;
3814 } else {
3815 pCalBChans = pEepData->calFreqPier5G;
3816 numPiers = AR5416_NUM_5G_CAL_PIERS;
3817 }
3818
3819 numXpdGain = 0;
3820 957
3821 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 958 switch (rx_chainmask) {
3822 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 959 case 0x5:
3823 if (numXpdGain >= AR5416_NUM_PD_GAINS) 960 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
3824 break; 961 AR_PHY_SWAP_ALT_CHAIN);
3825 xpdGainValues[numXpdGain] = 962 case 0x3:
3826 (u16) (AR5416_PD_GAINS_IN_MASK - i); 963 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
3827 numXpdGain++; 964 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
965 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
966 break;
3828 } 967 }
968 case 0x1:
969 case 0x2:
970 if (!AR_SREV_9280(ah))
971 break;
972 case 0x7:
973 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
974 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
975 break;
976 default:
977 break;
3829 } 978 }
3830 979
3831 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 980 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
3832 (numXpdGain - 1) & 0x3); 981 if (tx_chainmask == 0x5) {
3833 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, 982 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
3834 xpdGainValues[0]); 983 AR_PHY_SWAP_ALT_CHAIN);
3835 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3836 xpdGainValues[1]);
3837 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3838 xpdGainValues[2]);
3839
3840 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3841 if (AR_SREV_5416_V20_OR_LATER(ah) &&
3842 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
3843 && (i != 0)) {
3844 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
3845 } else
3846 regChainOffset = i * 0x1000;
3847 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3848 if (IS_CHAN_2GHZ(chan))
3849 pRawDataset = pEepData->calPierData2G[i];
3850 else
3851 pRawDataset = pEepData->calPierData5G[i];
3852
3853 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
3854 pRawDataset,
3855 pCalBChans,
3856 numPiers,
3857 pdGainOverlap_t2,
3858 &tMinCalPower,
3859 gainBoundaries,
3860 pdadcValues,
3861 numXpdGain);
3862
3863 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
3864
3865 REG_WRITE(ah,
3866 AR_PHY_TPCRG5 + regChainOffset,
3867 SM(pdGainOverlap_t2,
3868 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
3869 | SM(gainBoundaries[0],
3870 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3871 | SM(gainBoundaries[1],
3872 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3873 | SM(gainBoundaries[2],
3874 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3875 | SM(gainBoundaries[3],
3876 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3877 }
3878
3879 regOffset =
3880 AR_PHY_BASE + (672 << 2) + regChainOffset;
3881 for (j = 0; j < 32; j++) {
3882 reg32 =
3883 ((pdadcValues[4 * j + 0] & 0xFF) << 0)
3884 | ((pdadcValues[4 * j + 1] & 0xFF) <<
3885 8) | ((pdadcValues[4 * j + 2] &
3886 0xFF) << 16) |
3887 ((pdadcValues[4 * j + 3] & 0xFF) <<
3888 24);
3889 REG_WRITE(ah, regOffset, reg32);
3890
3891 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3892 "PDADC (%d,%4x): %4.4x %8.8x\n",
3893 i, regChainOffset, regOffset,
3894 reg32);
3895 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3896 "PDADC: Chain %d | PDADC %3d Value %3d | "
3897 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
3898 "PDADC %3d Value %3d |\n",
3899 i, 4 * j, pdadcValues[4 * j],
3900 4 * j + 1, pdadcValues[4 * j + 1],
3901 4 * j + 2, pdadcValues[4 * j + 2],
3902 4 * j + 3,
3903 pdadcValues[4 * j + 3]);
3904
3905 regOffset += 4;
3906 }
3907 }
3908 } 984 }
3909 *pTxPowerIndexOffset = 0; 985 if (AR_SREV_9100(ah))
3910 986 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3911 return true; 987 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
3912} 988}
3913 989
3914void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) 990static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode)
3915{ 991{
3916 struct ath_hal_5416 *ahp = AH5416(ah); 992 struct ath_hal_5416 *ahp = AH5416(ah);
3917 u8 i;
3918 993
3919 if (ah->ah_isPciExpress != true) 994 ahp->ah_maskReg = AR_IMR_TXERR |
3920 return; 995 AR_IMR_TXURN |
3921 996 AR_IMR_RXERR |
3922 if (ah->ah_config.pcie_powersave_enable == 2) 997 AR_IMR_RXORN |
3923 return; 998 AR_IMR_BCNMISC;
3924
3925 if (restore)
3926 return;
3927
3928 if (AR_SREV_9280_20_OR_LATER(ah)) {
3929 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
3930 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
3931 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3932 }
3933 udelay(1000);
3934 } else if (AR_SREV_9280(ah)
3935 && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
3936 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3937 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3938 999
3939 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); 1000 if (ahp->ah_intrMitigation)
3940 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); 1001 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
3941 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); 1002 else
1003 ahp->ah_maskReg |= AR_IMR_RXOK;
3942 1004
3943 if (ah->ah_config.pcie_clock_req) 1005 ahp->ah_maskReg |= AR_IMR_TXOK;
3944 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3945 else
3946 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3947 1006
3948 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 1007 if (opmode == ATH9K_M_HOSTAP)
3949 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 1008 ahp->ah_maskReg |= AR_IMR_MIB;
3950 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3951 1009
3952 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 1010 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1011 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
3953 1012
3954 udelay(1000); 1013 if (!AR_SREV_9100(ah)) {
3955 } else { 1014 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
3956 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 1015 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
3957 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 1016 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
3958 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3959 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3960 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3961 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3962 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3963 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3964 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3965 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3966 } 1017 }
1018}
3967 1019
3968 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 1020static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1021{
1022 struct ath_hal_5416 *ahp = AH5416(ah);
3969 1023
3970 if (ah->ah_config.pcie_waen) { 1024 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
3971 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); 1025 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
1026 __func__, us);
1027 ahp->ah_acktimeout = (u32) -1;
1028 return false;
3972 } else { 1029 } else {
3973 if (AR_SREV_9280(ah)) 1030 REG_RMW_FIELD(ah, AR_TIME_OUT,
3974 REG_WRITE(ah, AR_WA, 0x0040073f); 1031 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
3975 else 1032 ahp->ah_acktimeout = us;
3976 REG_WRITE(ah, AR_WA, 0x0000073f); 1033 return true;
3977 } 1034 }
3978} 1035}
3979 1036
3980static void 1037static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
3981ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
3982 struct ath9k_channel *chan,
3983 struct cal_target_power_leg *powInfo,
3984 u16 numChannels,
3985 struct cal_target_power_leg *pNewPower,
3986 u16 numRates,
3987 bool isExtTarget)
3988{ 1038{
3989 u16 clo, chi; 1039 struct ath_hal_5416 *ahp = AH5416(ah);
3990 int i;
3991 int matchIndex = -1, lowIndex = -1;
3992 u16 freq;
3993 struct chan_centers centers;
3994
3995 ath9k_hw_get_channel_centers(ah, chan, &centers);
3996 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
3997 1040
3998 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, 1041 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
3999 IS_CHAN_2GHZ(chan))) { 1042 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
4000 matchIndex = 0; 1043 __func__, us);
1044 ahp->ah_ctstimeout = (u32) -1;
1045 return false;
4001 } else { 1046 } else {
4002 for (i = 0; (i < numChannels) 1047 REG_RMW_FIELD(ah, AR_TIME_OUT,
4003 && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 1048 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
4004 if (freq == 1049 ahp->ah_ctstimeout = us;
4005 ath9k_hw_fbin2freq(powInfo[i].bChannel, 1050 return true;
4006 IS_CHAN_2GHZ(chan))) {
4007 matchIndex = i;
4008 break;
4009 } else if ((freq <
4010 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4011 IS_CHAN_2GHZ(chan)))
4012 && (freq >
4013 ath9k_hw_fbin2freq(powInfo[i - 1].
4014 bChannel,
4015 IS_CHAN_2GHZ
4016 (chan)))) {
4017 lowIndex = i - 1;
4018 break;
4019 }
4020 }
4021 if ((matchIndex == -1) && (lowIndex == -1))
4022 matchIndex = i - 1;
4023 } 1051 }
1052}
4024 1053
4025 if (matchIndex != -1) { 1054static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
4026 *pNewPower = powInfo[matchIndex]; 1055{
1056 struct ath_hal_5416 *ahp = AH5416(ah);
1057
1058 if (tu > 0xFFFF) {
1059 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1060 "%s: bad global tx timeout %u\n", __func__, tu);
1061 ahp->ah_globaltxtimeout = (u32) -1;
1062 return false;
4027 } else { 1063 } else {
4028 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, 1064 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
4029 IS_CHAN_2GHZ(chan)); 1065 ahp->ah_globaltxtimeout = tu;
4030 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, 1066 return true;
4031 IS_CHAN_2GHZ(chan));
4032
4033 for (i = 0; i < numRates; i++) {
4034 pNewPower->tPow2x[i] =
4035 (u8) ath9k_hw_interpolate(freq, clo, chi,
4036 powInfo
4037 [lowIndex].
4038 tPow2x[i],
4039 powInfo
4040 [lowIndex +
4041 1].tPow2x[i]);
4042 }
4043 } 1067 }
4044} 1068}
4045 1069
4046static void 1070static void ath9k_hw_init_user_settings(struct ath_hal *ah)
4047ath9k_hw_get_target_powers(struct ath_hal *ah,
4048 struct ath9k_channel *chan,
4049 struct cal_target_power_ht *powInfo,
4050 u16 numChannels,
4051 struct cal_target_power_ht *pNewPower,
4052 u16 numRates,
4053 bool isHt40Target)
4054{ 1071{
4055 u16 clo, chi; 1072 struct ath_hal_5416 *ahp = AH5416(ah);
4056 int i;
4057 int matchIndex = -1, lowIndex = -1;
4058 u16 freq;
4059 struct chan_centers centers;
4060 1073
4061 ath9k_hw_get_channel_centers(ah, chan, &centers); 1074 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
4062 freq = isHt40Target ? centers.synth_center : centers.ctl_center; 1075 __func__, ahp->ah_miscMode);
4063 1076
4064 if (freq <= 1077 if (ahp->ah_miscMode != 0)
4065 ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { 1078 REG_WRITE(ah, AR_PCU_MISC,
4066 matchIndex = 0; 1079 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
4067 } else { 1080 if (ahp->ah_slottime != (u32) -1)
4068 for (i = 0; (i < numChannels) 1081 ath9k_hw_setslottime(ah, ahp->ah_slottime);
4069 && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 1082 if (ahp->ah_acktimeout != (u32) -1)
4070 if (freq == 1083 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
4071 ath9k_hw_fbin2freq(powInfo[i].bChannel, 1084 if (ahp->ah_ctstimeout != (u32) -1)
4072 IS_CHAN_2GHZ(chan))) { 1085 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
4073 matchIndex = i; 1086 if (ahp->ah_globaltxtimeout != (u32) -1)
4074 break; 1087 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
4075 } else 1088}
4076 if ((freq <
4077 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4078 IS_CHAN_2GHZ(chan)))
4079 && (freq >
4080 ath9k_hw_fbin2freq(powInfo[i - 1].
4081 bChannel,
4082 IS_CHAN_2GHZ
4083 (chan)))) {
4084 lowIndex = i - 1;
4085 break;
4086 }
4087 }
4088 if ((matchIndex == -1) && (lowIndex == -1))
4089 matchIndex = i - 1;
4090 }
4091 1089
4092 if (matchIndex != -1) { 1090const char *ath9k_hw_probe(u16 vendorid, u16 devid)
4093 *pNewPower = powInfo[matchIndex]; 1091{
4094 } else { 1092 return vendorid == ATHEROS_VENDOR_ID ?
4095 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, 1093 ath9k_hw_devname(devid) : NULL;
4096 IS_CHAN_2GHZ(chan));
4097 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4098 IS_CHAN_2GHZ(chan));
4099
4100 for (i = 0; i < numRates; i++) {
4101 pNewPower->tPow2x[i] =
4102 (u8) ath9k_hw_interpolate(freq, clo, chi,
4103 powInfo
4104 [lowIndex].
4105 tPow2x[i],
4106 powInfo
4107 [lowIndex +
4108 1].tPow2x[i]);
4109 }
4110 }
4111} 1094}
4112 1095
4113static u16 1096void ath9k_hw_detach(struct ath_hal *ah)
4114ath9k_hw_get_max_edge_power(u16 freq,
4115 struct cal_ctl_edges *pRdEdgesPower,
4116 bool is2GHz)
4117{ 1097{
4118 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1098 if (!AR_SREV_9100(ah))
4119 int i; 1099 ath9k_hw_ani_detach(ah);
4120 1100
4121 for (i = 0; (i < AR5416_NUM_BAND_EDGES) 1101 ath9k_hw_rfdetach(ah);
4122 && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 1102 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
4123 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, 1103 kfree(ah);
4124 is2GHz)) {
4125 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
4126 break;
4127 } else if ((i > 0)
4128 && (freq <
4129 ath9k_hw_fbin2freq(pRdEdgesPower[i].
4130 bChannel, is2GHz))) {
4131 if (ath9k_hw_fbin2freq
4132 (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq
4133 && pRdEdgesPower[i - 1].flag) {
4134 twiceMaxEdgePower =
4135 pRdEdgesPower[i - 1].tPower;
4136 }
4137 break;
4138 }
4139 }
4140 return twiceMaxEdgePower;
4141} 1104}
4142 1105
4143static bool 1106struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
4144ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, 1107 void __iomem *mem, int *error)
4145 struct ar5416_eeprom *pEepData,
4146 struct ath9k_channel *chan,
4147 int16_t *ratesArray,
4148 u16 cfgCtl,
4149 u8 AntennaReduction,
4150 u8 twiceMaxRegulatoryPower,
4151 u8 powerLimit)
4152{ 1108{
4153 u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1109 struct ath_hal *ah = NULL;
4154 static const u16 tpScaleReductionTable[5] =
4155 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
4156 1110
4157 int i; 1111 switch (devid) {
4158 int8_t twiceLargestAntenna; 1112 case AR5416_DEVID_PCI:
4159 struct cal_ctl_data *rep; 1113 case AR5416_DEVID_PCIE:
4160 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 1114 case AR9160_DEVID_PCI:
4161 0, { 0, 0, 0, 0} 1115 case AR9280_DEVID_PCI:
4162 }; 1116 case AR9280_DEVID_PCIE:
4163 struct cal_target_power_leg targetPowerOfdmExt = { 1117 ah = ath9k_hw_do_attach(devid, sc, mem, error);
4164 0, { 0, 0, 0, 0} }, targetPowerCckExt = { 1118 break;
4165 0, { 0, 0, 0, 0 } 1119 default:
4166 }; 1120 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
4167 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 1121 "devid=0x%x not supported.\n", devid);
4168 0, {0, 0, 0, 0} 1122 ah = NULL;
4169 }; 1123 *error = -ENXIO;
4170 u8 scaledPower = 0, minCtlPower, maxRegAllowedPower; 1124 break;
4171 u16 ctlModesFor11a[] = 1125 }
4172 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
4173 u16 ctlModesFor11g[] =
4174 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
4175 CTL_2GHT40
4176 };
4177 u16 numCtlModes, *pCtlMode, ctlMode, freq;
4178 struct chan_centers centers;
4179 int tx_chainmask;
4180 u8 twiceMinEdgePower;
4181 struct ath_hal_5416 *ahp = AH5416(ah);
4182 1126
4183 tx_chainmask = ahp->ah_txchainmask; 1127 return ah;
1128}
4184 1129
4185 ath9k_hw_get_channel_centers(ah, chan, &centers); 1130/*******/
1131/* INI */
1132/*******/
4186 1133
4187 twiceLargestAntenna = max( 1134static void ath9k_hw_override_ini(struct ath_hal *ah,
4188 pEepData->modalHeader 1135 struct ath9k_channel *chan)
4189 [IS_CHAN_2GHZ(chan)].antennaGainCh[0], 1136{
4190 pEepData->modalHeader 1137 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
4191 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); 1138 AR_SREV_9280_10_OR_LATER(ah))
1139 return;
4192 1140
4193 twiceLargestAntenna = max((u8) twiceLargestAntenna, 1141 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
4194 pEepData->modalHeader 1142}
4195 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1143
1144static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1145 struct ar5416_eeprom *pEepData,
1146 u32 reg, u32 value)
1147{
1148 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
4196 1149
4197 twiceLargestAntenna = 1150 switch (ah->ah_devid) {
4198 (int8_t) min(AntennaReduction - twiceLargestAntenna, 0); 1151 case AR9280_DEVID_PCI:
1152 if (reg == 0x7894) {
1153 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1154 "ini VAL: %x EEPROM: %x\n", value,
1155 (pBase->version & 0xff));
4199 1156
4200 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 1157 if ((pBase->version & 0xff) > 0x0a) {
1158 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1159 "PWDCLKIND: %d\n",
1160 pBase->pwdclkind);
1161 value &= ~AR_AN_TOP2_PWDCLKIND;
1162 value |= AR_AN_TOP2_PWDCLKIND &
1163 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1164 } else {
1165 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1166 "PWDCLKIND Earlier Rev\n");
1167 }
4201 1168
4202 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) { 1169 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
4203 maxRegAllowedPower -= 1170 "final ini VAL: %x\n", value);
4204 (tpScaleReductionTable[(ah->ah_tpScale)] * 2); 1171 }
1172 break;
4205 } 1173 }
4206 1174
4207 scaledPower = min(powerLimit, maxRegAllowedPower); 1175 return value;
1176}
4208 1177
4209 switch (ar5416_get_ntxchains(tx_chainmask)) { 1178static int ath9k_hw_process_ini(struct ath_hal *ah,
4210 case 1: 1179 struct ath9k_channel *chan,
1180 enum ath9k_ht_macmode macmode)
1181{
1182 int i, regWrites = 0;
1183 struct ath_hal_5416 *ahp = AH5416(ah);
1184 u32 modesIndex, freqIndex;
1185 int status;
1186
1187 switch (chan->chanmode) {
1188 case CHANNEL_A:
1189 case CHANNEL_A_HT20:
1190 modesIndex = 1;
1191 freqIndex = 1;
4211 break; 1192 break;
4212 case 2: 1193 case CHANNEL_A_HT40PLUS:
4213 scaledPower -= 1194 case CHANNEL_A_HT40MINUS:
4214 pEepData->modalHeader[IS_CHAN_2GHZ(chan)]. 1195 modesIndex = 2;
4215 pwrDecreaseFor2Chain; 1196 freqIndex = 1;
4216 break; 1197 break;
4217 case 3: 1198 case CHANNEL_G:
4218 scaledPower -= 1199 case CHANNEL_G_HT20:
4219 pEepData->modalHeader[IS_CHAN_2GHZ(chan)]. 1200 case CHANNEL_B:
4220 pwrDecreaseFor3Chain; 1201 modesIndex = 4;
1202 freqIndex = 2;
4221 break; 1203 break;
1204 case CHANNEL_G_HT40PLUS:
1205 case CHANNEL_G_HT40MINUS:
1206 modesIndex = 3;
1207 freqIndex = 2;
1208 break;
1209
1210 default:
1211 return -EINVAL;
4222 } 1212 }
4223 1213
4224 scaledPower = max(0, (int32_t) scaledPower); 1214 REG_WRITE(ah, AR_PHY(0), 0x00000007);
4225
4226 if (IS_CHAN_2GHZ(chan)) {
4227 numCtlModes =
4228 ARRAY_SIZE(ctlModesFor11g) -
4229 SUB_NUM_CTL_MODES_AT_2G_40;
4230 pCtlMode = ctlModesFor11g;
4231
4232 ath9k_hw_get_legacy_target_powers(ah, chan,
4233 pEepData->
4234 calTargetPowerCck,
4235 AR5416_NUM_2G_CCK_TARGET_POWERS,
4236 &targetPowerCck, 4,
4237 false);
4238 ath9k_hw_get_legacy_target_powers(ah, chan,
4239 pEepData->
4240 calTargetPower2G,
4241 AR5416_NUM_2G_20_TARGET_POWERS,
4242 &targetPowerOfdm, 4,
4243 false);
4244 ath9k_hw_get_target_powers(ah, chan,
4245 pEepData->calTargetPower2GHT20,
4246 AR5416_NUM_2G_20_TARGET_POWERS,
4247 &targetPowerHt20, 8, false);
4248 1215
4249 if (IS_CHAN_HT40(chan)) { 1216 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
4250 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 1217
4251 ath9k_hw_get_target_powers(ah, chan, 1218 ath9k_hw_set_addac(ah, chan);
4252 pEepData-> 1219
4253 calTargetPower2GHT40, 1220 if (AR_SREV_5416_V22_OR_LATER(ah)) {
4254 AR5416_NUM_2G_40_TARGET_POWERS, 1221 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
4255 &targetPowerHt40, 8,
4256 true);
4257 ath9k_hw_get_legacy_target_powers(ah, chan,
4258 pEepData->
4259 calTargetPowerCck,
4260 AR5416_NUM_2G_CCK_TARGET_POWERS,
4261 &targetPowerCckExt,
4262 4, true);
4263 ath9k_hw_get_legacy_target_powers(ah, chan,
4264 pEepData->
4265 calTargetPower2G,
4266 AR5416_NUM_2G_20_TARGET_POWERS,
4267 &targetPowerOfdmExt,
4268 4, true);
4269 }
4270 } else { 1222 } else {
1223 struct ar5416IniArray temp;
1224 u32 addacSize =
1225 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1226 ahp->ah_iniAddac.ia_columns;
4271 1227
4272 numCtlModes = 1228 memcpy(ahp->ah_addac5416_21,
4273 ARRAY_SIZE(ctlModesFor11a) - 1229 ahp->ah_iniAddac.ia_array, addacSize);
4274 SUB_NUM_CTL_MODES_AT_5G_40;
4275 pCtlMode = ctlModesFor11a;
4276
4277 ath9k_hw_get_legacy_target_powers(ah, chan,
4278 pEepData->
4279 calTargetPower5G,
4280 AR5416_NUM_5G_20_TARGET_POWERS,
4281 &targetPowerOfdm, 4,
4282 false);
4283 ath9k_hw_get_target_powers(ah, chan,
4284 pEepData->calTargetPower5GHT20,
4285 AR5416_NUM_5G_20_TARGET_POWERS,
4286 &targetPowerHt20, 8, false);
4287 1230
4288 if (IS_CHAN_HT40(chan)) { 1231 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
4289 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4290 ath9k_hw_get_target_powers(ah, chan,
4291 pEepData->
4292 calTargetPower5GHT40,
4293 AR5416_NUM_5G_40_TARGET_POWERS,
4294 &targetPowerHt40, 8,
4295 true);
4296 ath9k_hw_get_legacy_target_powers(ah, chan,
4297 pEepData->
4298 calTargetPower5G,
4299 AR5416_NUM_5G_20_TARGET_POWERS,
4300 &targetPowerOfdmExt,
4301 4, true);
4302 }
4303 }
4304 1232
4305 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 1233 temp.ia_array = ahp->ah_addac5416_21;
4306 bool isHt40CtlMode = 1234 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
4307 (pCtlMode[ctlMode] == CTL_5GHT40) 1235 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
4308 || (pCtlMode[ctlMode] == CTL_2GHT40); 1236 REG_WRITE_ARRAY(&temp, 1, regWrites);
4309 if (isHt40CtlMode) 1237 }
4310 freq = centers.synth_center;
4311 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4312 freq = centers.ext_center;
4313 else
4314 freq = centers.ctl_center;
4315 1238
4316 if (ar5416_get_eep_ver(ahp) == 14 1239 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
4317 && ar5416_get_eep_rev(ahp) <= 2)
4318 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4319 1240
4320 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1241 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
4321 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " 1242 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
4322 "EXT_ADDITIVE %d\n", 1243 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
4323 ctlMode, numCtlModes, isHt40CtlMode,
4324 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4325 1244
4326 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; 1245#ifdef CONFIG_SLOW_ANT_DIV
4327 i++) { 1246 if (ah->ah_devid == AR9280_DEVID_PCI)
4328 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1247 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, val);
4329 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " 1248#endif
4330 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4331 "chan %d\n",
4332 i, cfgCtl, pCtlMode[ctlMode],
4333 pEepData->ctlIndex[i], chan->channel);
4334
4335 if ((((cfgCtl & ~CTL_MODE_M) |
4336 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4337 pEepData->ctlIndex[i])
4338 ||
4339 (((cfgCtl & ~CTL_MODE_M) |
4340 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4341 ((pEepData->
4342 ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
4343 rep = &(pEepData->ctlData[i]);
4344
4345 twiceMinEdgePower =
4346 ath9k_hw_get_max_edge_power(freq,
4347 rep->
4348 ctlEdges
4349 [ar5416_get_ntxchains
4350 (tx_chainmask)
4351 - 1],
4352 IS_CHAN_2GHZ
4353 (chan));
4354
4355 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4356 " MATCH-EE_IDX %d: ch %d is2 %d "
4357 "2xMinEdge %d chainmask %d chains %d\n",
4358 i, freq, IS_CHAN_2GHZ(chan),
4359 twiceMinEdgePower, tx_chainmask,
4360 ar5416_get_ntxchains
4361 (tx_chainmask));
4362 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
4363 twiceMaxEdgePower =
4364 min(twiceMaxEdgePower,
4365 twiceMinEdgePower);
4366 } else {
4367 twiceMaxEdgePower =
4368 twiceMinEdgePower;
4369 break;
4370 }
4371 }
4372 }
4373 1249
4374 minCtlPower = min(twiceMaxEdgePower, scaledPower); 1250 REG_WRITE(ah, reg, val);
4375 1251
4376 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1252 if (reg >= 0x7800 && reg < 0x78a0
4377 " SEL-Min ctlMode %d pCtlMode %d " 1253 && ah->ah_config.analog_shiftreg) {
4378 "2xMaxEdge %d sP %d minCtlPwr %d\n", 1254 udelay(100);
4379 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4380 scaledPower, minCtlPower);
4381
4382 switch (pCtlMode[ctlMode]) {
4383 case CTL_11B:
4384 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
4385 i++) {
4386 targetPowerCck.tPow2x[i] =
4387 min(targetPowerCck.tPow2x[i],
4388 minCtlPower);
4389 }
4390 break;
4391 case CTL_11A:
4392 case CTL_11G:
4393 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
4394 i++) {
4395 targetPowerOfdm.tPow2x[i] =
4396 min(targetPowerOfdm.tPow2x[i],
4397 minCtlPower);
4398 }
4399 break;
4400 case CTL_5GHT20:
4401 case CTL_2GHT20:
4402 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
4403 i++) {
4404 targetPowerHt20.tPow2x[i] =
4405 min(targetPowerHt20.tPow2x[i],
4406 minCtlPower);
4407 }
4408 break;
4409 case CTL_11B_EXT:
4410 targetPowerCckExt.tPow2x[0] =
4411 min(targetPowerCckExt.tPow2x[0], minCtlPower);
4412 break;
4413 case CTL_11A_EXT:
4414 case CTL_11G_EXT:
4415 targetPowerOfdmExt.tPow2x[0] =
4416 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
4417 break;
4418 case CTL_5GHT40:
4419 case CTL_2GHT40:
4420 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
4421 i++) {
4422 targetPowerHt40.tPow2x[i] =
4423 min(targetPowerHt40.tPow2x[i],
4424 minCtlPower);
4425 }
4426 break;
4427 default:
4428 break;
4429 } 1255 }
4430 }
4431 1256
4432 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = 1257 DO_DELAY(regWrites);
4433 ratesArray[rate18mb] = ratesArray[rate24mb] =
4434 targetPowerOfdm.tPow2x[0];
4435 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
4436 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
4437 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
4438 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
4439
4440 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
4441 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
4442
4443 if (IS_CHAN_2GHZ(chan)) {
4444 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
4445 ratesArray[rate2s] = ratesArray[rate2l] =
4446 targetPowerCck.tPow2x[1];
4447 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
4448 targetPowerCck.tPow2x[2];
4449 ;
4450 ratesArray[rate11s] = ratesArray[rate11l] =
4451 targetPowerCck.tPow2x[3];
4452 ;
4453 } 1258 }
4454 if (IS_CHAN_HT40(chan)) { 1259
4455 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 1260 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
4456 ratesArray[rateHt40_0 + i] = 1261 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
4457 targetPowerHt40.tPow2x[i]; 1262 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
4458 } 1263
4459 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 1264 REG_WRITE(ah, reg, val);
4460 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 1265
4461 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 1266 if (reg >= 0x7800 && reg < 0x78a0
4462 if (IS_CHAN_2GHZ(chan)) { 1267 && ah->ah_config.analog_shiftreg) {
4463 ratesArray[rateExtCck] = 1268 udelay(100);
4464 targetPowerCckExt.tPow2x[0];
4465 } 1269 }
4466 }
4467 return true;
4468}
4469 1270
4470static int 1271 DO_DELAY(regWrites);
4471ath9k_hw_set_txpower(struct ath_hal *ah, 1272 }
4472 struct ar5416_eeprom *pEepData,
4473 struct ath9k_channel *chan,
4474 u16 cfgCtl,
4475 u8 twiceAntennaReduction,
4476 u8 twiceMaxRegulatoryPower,
4477 u8 powerLimit)
4478{
4479 struct modal_eep_header *pModal =
4480 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
4481 int16_t ratesArray[Ar5416RateSize];
4482 int16_t txPowerIndexOffset = 0;
4483 u8 ht40PowerIncForPdadc = 2;
4484 int i;
4485 1273
4486 memset(ratesArray, 0, sizeof(ratesArray)); 1274 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
4487 1275
4488 if ((pEepData->baseEepHeader. 1276 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
4489 version & AR5416_EEP_VER_MINOR_MASK) >= 1277 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
4490 AR5416_EEP_MINOR_VER_2) { 1278 regWrites);
4491 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
4492 } 1279 }
4493 1280
4494 if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan, 1281 ath9k_hw_override_ini(ah, chan);
4495 &ratesArray[0], cfgCtl, 1282 ath9k_hw_set_regs(ah, chan, macmode);
4496 twiceAntennaReduction, 1283 ath9k_hw_init_chain_masks(ah);
4497 twiceMaxRegulatoryPower, 1284
4498 powerLimit)) { 1285 status = ath9k_hw_set_txpower(ah, chan,
4499 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1286 ath9k_regd_get_ctl(ah, chan),
4500 "ath9k_hw_set_txpower: unable to set " 1287 ath9k_regd_get_antenna_allowed(ah,
4501 "tx power per rate table\n"); 1288 chan),
1289 chan->maxRegTxPower * 2,
1290 min((u32) MAX_RATE_POWER,
1291 (u32) ah->ah_powerLimit));
1292 if (status != 0) {
1293 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1294 "%s: error init'ing transmit power\n", __func__);
4502 return -EIO; 1295 return -EIO;
4503 } 1296 }
4504 1297
4505 if (!ath9k_hw_set_power_cal_table 1298 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
4506 (ah, pEepData, chan, &txPowerIndexOffset)) { 1299 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
4507 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1300 "%s: ar5416SetRfRegs failed\n", __func__);
4508 "ath9k_hw_set_txpower: unable to set power table\n");
4509 return -EIO; 1301 return -EIO;
4510 } 1302 }
4511 1303
4512 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 1304 return 0;
4513 ratesArray[i] = 1305}
4514 (int16_t) (txPowerIndexOffset + ratesArray[i]);
4515 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
4516 ratesArray[i] = AR5416_MAX_RATE_POWER;
4517 }
4518 1306
4519 if (AR_SREV_9280_10_OR_LATER(ah)) { 1307/****************************************/
4520 for (i = 0; i < Ar5416RateSize; i++) 1308/* Reset and Channel Switching Routines */
4521 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; 1309/****************************************/
4522 }
4523 1310
4524 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1311static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
4525 ATH9K_POW_SM(ratesArray[rate18mb], 24) 1312{
4526 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 1313 u32 rfMode = 0;
4527 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
4528 | ATH9K_POW_SM(ratesArray[rate6mb], 0)
4529 );
4530 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
4531 ATH9K_POW_SM(ratesArray[rate54mb], 24)
4532 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
4533 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
4534 | ATH9K_POW_SM(ratesArray[rate24mb], 0)
4535 );
4536
4537 if (IS_CHAN_2GHZ(chan)) {
4538 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
4539 ATH9K_POW_SM(ratesArray[rate2s], 24)
4540 | ATH9K_POW_SM(ratesArray[rate2l], 16)
4541 | ATH9K_POW_SM(ratesArray[rateXr], 8)
4542 | ATH9K_POW_SM(ratesArray[rate1l], 0)
4543 );
4544 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
4545 ATH9K_POW_SM(ratesArray[rate11s], 24)
4546 | ATH9K_POW_SM(ratesArray[rate11l], 16)
4547 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
4548 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)
4549 );
4550 }
4551 1314
4552 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 1315 if (chan == NULL)
4553 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 1316 return;
4554 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
4555 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
4556 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
4557 );
4558 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
4559 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
4560 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
4561 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
4562 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
4563 );
4564 1317
4565 if (IS_CHAN_HT40(chan)) { 1318 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
4566 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 1319 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
4567 ATH9K_POW_SM(ratesArray[rateHt40_3] +
4568 ht40PowerIncForPdadc, 24)
4569 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
4570 ht40PowerIncForPdadc, 16)
4571 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
4572 ht40PowerIncForPdadc, 8)
4573 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
4574 ht40PowerIncForPdadc, 0)
4575 );
4576 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
4577 ATH9K_POW_SM(ratesArray[rateHt40_7] +
4578 ht40PowerIncForPdadc, 24)
4579 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
4580 ht40PowerIncForPdadc, 16)
4581 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
4582 ht40PowerIncForPdadc, 8)
4583 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
4584 ht40PowerIncForPdadc, 0)
4585 );
4586
4587 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
4588 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
4589 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
4590 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
4591 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)
4592 );
4593 }
4594 1320
4595 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 1321 if (!AR_SREV_9280_10_OR_LATER(ah))
4596 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) 1322 rfMode |= (IS_CHAN_5GHZ(chan)) ?
4597 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0) 1323 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
4598 );
4599 1324
4600 i = rate6mb; 1325 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
4601 if (IS_CHAN_HT40(chan)) 1326 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
4602 i = rateHt40_0;
4603 else if (IS_CHAN_HT20(chan))
4604 i = rateHt20_0;
4605 1327
4606 if (AR_SREV_9280_10_OR_LATER(ah)) 1328 REG_WRITE(ah, AR_PHY_MODE, rfMode);
4607 ah->ah_maxPowerLevel = 1329}
4608 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
4609 else
4610 ah->ah_maxPowerLevel = ratesArray[i];
4611 1330
4612 return 0; 1331static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1332{
1333 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1334}
1335
1336static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1337{
1338 u32 regval;
1339
1340 regval = REG_READ(ah, AR_AHB_MODE);
1341 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1342
1343 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1344 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1345
1346 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1347
1348 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1349 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1350
1351 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1352
1353 if (AR_SREV_9285(ah)) {
1354 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1355 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1356 } else {
1357 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1358 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1359 }
1360}
1361
1362static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1363{
1364 u32 val;
1365
1366 val = REG_READ(ah, AR_STA_ID1);
1367 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1368 switch (opmode) {
1369 case ATH9K_M_HOSTAP:
1370 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1371 | AR_STA_ID1_KSRCH_MODE);
1372 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1373 break;
1374 case ATH9K_M_IBSS:
1375 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1376 | AR_STA_ID1_KSRCH_MODE);
1377 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1378 break;
1379 case ATH9K_M_STA:
1380 case ATH9K_M_MONITOR:
1381 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1382 break;
1383 }
4613} 1384}
4614 1385
4615static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, 1386static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
@@ -4631,9 +1402,8 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
4631 *coef_exponent = coef_exp - 16; 1402 *coef_exponent = coef_exp - 16;
4632} 1403}
4633 1404
4634static void 1405static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
4635ath9k_hw_set_delta_slope(struct ath_hal *ah, 1406 struct ath9k_channel *chan)
4636 struct ath9k_channel *chan)
4637{ 1407{
4638 u32 coef_scaled, ds_coef_exp, ds_coef_man; 1408 u32 coef_scaled, ds_coef_exp, ds_coef_man;
4639 u32 clockMhzScaled = 0x64000000; 1409 u32 clockMhzScaled = 0x64000000;
@@ -4666,8 +1436,242 @@ ath9k_hw_set_delta_slope(struct ath_hal *ah,
4666 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 1436 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
4667} 1437}
4668 1438
4669static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, 1439static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
4670 struct ath9k_channel *chan) 1440{
1441 u32 rst_flags;
1442 u32 tmpReg;
1443
1444 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1445 AR_RTC_FORCE_WAKE_ON_INT);
1446
1447 if (AR_SREV_9100(ah)) {
1448 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1449 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1450 } else {
1451 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1452 if (tmpReg &
1453 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1454 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1455 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1456 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1457 } else {
1458 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1459 }
1460
1461 rst_flags = AR_RTC_RC_MAC_WARM;
1462 if (type == ATH9K_RESET_COLD)
1463 rst_flags |= AR_RTC_RC_MAC_COLD;
1464 }
1465
1466 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1467 udelay(50);
1468
1469 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1470 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1471 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1472 "%s: RTC stuck in MAC reset\n",
1473 __func__);
1474 return false;
1475 }
1476
1477 if (!AR_SREV_9100(ah))
1478 REG_WRITE(ah, AR_RC, 0);
1479
1480 ath9k_hw_init_pll(ah, NULL);
1481
1482 if (AR_SREV_9100(ah))
1483 udelay(50);
1484
1485 return true;
1486}
1487
1488static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1489{
1490 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1491 AR_RTC_FORCE_WAKE_ON_INT);
1492
1493 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1494 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1495
1496 if (!ath9k_hw_wait(ah,
1497 AR_RTC_STATUS,
1498 AR_RTC_STATUS_M,
1499 AR_RTC_STATUS_ON)) {
1500 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1501 __func__);
1502 return false;
1503 }
1504
1505 ath9k_hw_read_revisions(ah);
1506
1507 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1508}
1509
1510static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1511{
1512 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1513 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1514
1515 switch (type) {
1516 case ATH9K_RESET_POWER_ON:
1517 return ath9k_hw_set_reset_power_on(ah);
1518 break;
1519 case ATH9K_RESET_WARM:
1520 case ATH9K_RESET_COLD:
1521 return ath9k_hw_set_reset(ah, type);
1522 break;
1523 default:
1524 return false;
1525 }
1526}
1527
1528static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1529 enum ath9k_ht_macmode macmode)
1530{
1531 u32 phymode;
1532 struct ath_hal_5416 *ahp = AH5416(ah);
1533
1534 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1535 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1536
1537 if (IS_CHAN_HT40(chan)) {
1538 phymode |= AR_PHY_FC_DYN2040_EN;
1539
1540 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1541 (chan->chanmode == CHANNEL_G_HT40PLUS))
1542 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1543
1544 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1545 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1546 }
1547 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1548
1549 ath9k_hw_set11nmac2040(ah, macmode);
1550
1551 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1552 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1553}
1554
1555static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1556 struct ath9k_channel *chan)
1557{
1558 struct ath_hal_5416 *ahp = AH5416(ah);
1559
1560 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1561 return false;
1562
1563 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1564 return false;
1565
1566 ahp->ah_chipFullSleep = false;
1567
1568 ath9k_hw_init_pll(ah, chan);
1569
1570 ath9k_hw_set_rfmode(ah, chan);
1571
1572 return true;
1573}
1574
1575static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1576 struct ath9k_channel *chan)
1577{
1578 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1579 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1580 "%s: invalid channel %u/0x%x; not marked as "
1581 "2GHz or 5GHz\n", __func__, chan->channel,
1582 chan->channelFlags);
1583 return NULL;
1584 }
1585
1586 if (!IS_CHAN_OFDM(chan) &&
1587 !IS_CHAN_CCK(chan) &&
1588 !IS_CHAN_HT20(chan) &&
1589 !IS_CHAN_HT40(chan)) {
1590 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1591 "%s: invalid channel %u/0x%x; not marked as "
1592 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1593 __func__, chan->channel, chan->channelFlags);
1594 return NULL;
1595 }
1596
1597 return ath9k_regd_check_channel(ah, chan);
1598}
1599
1600static bool ath9k_hw_channel_change(struct ath_hal *ah,
1601 struct ath9k_channel *chan,
1602 enum ath9k_ht_macmode macmode)
1603{
1604 u32 synthDelay, qnum;
1605
1606 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1607 if (ath9k_hw_numtxpending(ah, qnum)) {
1608 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1609 "%s: Transmit frames pending on queue %d\n",
1610 __func__, qnum);
1611 return false;
1612 }
1613 }
1614
1615 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1616 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1617 AR_PHY_RFBUS_GRANT_EN)) {
1618 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
1619 "%s: Could not kill baseband RX\n", __func__);
1620 return false;
1621 }
1622
1623 ath9k_hw_set_regs(ah, chan, macmode);
1624
1625 if (AR_SREV_9280_10_OR_LATER(ah)) {
1626 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1627 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1628 "%s: failed to set channel\n", __func__);
1629 return false;
1630 }
1631 } else {
1632 if (!(ath9k_hw_set_channel(ah, chan))) {
1633 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1634 "%s: failed to set channel\n", __func__);
1635 return false;
1636 }
1637 }
1638
1639 if (ath9k_hw_set_txpower(ah, chan,
1640 ath9k_regd_get_ctl(ah, chan),
1641 ath9k_regd_get_antenna_allowed(ah, chan),
1642 chan->maxRegTxPower * 2,
1643 min((u32) MAX_RATE_POWER,
1644 (u32) ah->ah_powerLimit)) != 0) {
1645 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1646 "%s: error init'ing transmit power\n", __func__);
1647 return false;
1648 }
1649
1650 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1651 if (IS_CHAN_CCK(chan))
1652 synthDelay = (4 * synthDelay) / 22;
1653 else
1654 synthDelay /= 10;
1655
1656 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1657
1658 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1659
1660 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1661 ath9k_hw_set_delta_slope(ah, chan);
1662
1663 if (AR_SREV_9280_10_OR_LATER(ah))
1664 ath9k_hw_9280_spur_mitigate(ah, chan);
1665 else
1666 ath9k_hw_spur_mitigate(ah, chan);
1667
1668 if (!chan->oneTimeCalsDone)
1669 chan->oneTimeCalsDone = true;
1670
1671 return true;
1672}
1673
1674static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
4671{ 1675{
4672 int bb_spur = AR_NO_SPUR; 1676 int bb_spur = AR_NO_SPUR;
4673 int freq; 1677 int freq;
@@ -4917,8 +1921,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4917 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 1921 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
4918} 1922}
4919 1923
4920static void ath9k_hw_spur_mitigate(struct ath_hal *ah, 1924static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
4921 struct ath9k_channel *chan)
4922{ 1925{
4923 int bb_spur = AR_NO_SPUR; 1926 int bb_spur = AR_NO_SPUR;
4924 int bin, cur_bin; 1927 int bin, cur_bin;
@@ -5119,752 +2122,11 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
5119 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2122 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
5120} 2123}
5121 2124
5122static void ath9k_hw_init_chain_masks(struct ath_hal *ah) 2125bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
5123{
5124 struct ath_hal_5416 *ahp = AH5416(ah);
5125 int rx_chainmask, tx_chainmask;
5126
5127 rx_chainmask = ahp->ah_rxchainmask;
5128 tx_chainmask = ahp->ah_txchainmask;
5129
5130 switch (rx_chainmask) {
5131 case 0x5:
5132 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5133 AR_PHY_SWAP_ALT_CHAIN);
5134 case 0x3:
5135 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
5136 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
5137 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
5138 break;
5139 }
5140 case 0x1:
5141 case 0x2:
5142 if (!AR_SREV_9280(ah))
5143 break;
5144 case 0x7:
5145 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5146 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5147 break;
5148 default:
5149 break;
5150 }
5151
5152 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
5153 if (tx_chainmask == 0x5) {
5154 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5155 AR_PHY_SWAP_ALT_CHAIN);
5156 }
5157 if (AR_SREV_9100(ah))
5158 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
5159 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
5160}
5161
5162static void ath9k_hw_set_addac(struct ath_hal *ah,
5163 struct ath9k_channel *chan)
5164{
5165 struct modal_eep_header *pModal;
5166 struct ath_hal_5416 *ahp = AH5416(ah);
5167 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
5168 u8 biaslevel;
5169
5170 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
5171 return;
5172
5173 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
5174 return;
5175
5176 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
5177
5178 if (pModal->xpaBiasLvl != 0xff) {
5179 biaslevel = pModal->xpaBiasLvl;
5180 } else {
5181
5182 u16 resetFreqBin, freqBin, freqCount = 0;
5183 struct chan_centers centers;
5184
5185 ath9k_hw_get_channel_centers(ah, chan, &centers);
5186
5187 resetFreqBin =
5188 FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
5189 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
5190 biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
5191
5192 freqCount++;
5193
5194 while (freqCount < 3) {
5195 if (pModal->xpaBiasLvlFreq[freqCount] == 0x0)
5196 break;
5197
5198 freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
5199 if (resetFreqBin >= freqBin) {
5200 biaslevel =
5201 (u8) (pModal->
5202 xpaBiasLvlFreq[freqCount]
5203 >> 14);
5204 } else {
5205 break;
5206 }
5207 freqCount++;
5208 }
5209 }
5210
5211 if (IS_CHAN_2GHZ(chan)) {
5212 INI_RA(&ahp->ah_iniAddac, 7, 1) =
5213 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel
5214 << 3;
5215 } else {
5216 INI_RA(&ahp->ah_iniAddac, 6, 1) =
5217 (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel
5218 << 6;
5219 }
5220}
5221
5222static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
5223{
5224 if (ah->ah_curchan != NULL)
5225 return clks /
5226 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
5227 else
5228 return clks / CLOCK_RATE[ATH9K_MODE_11B];
5229}
5230
5231static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
5232{
5233 struct ath9k_channel *chan = ah->ah_curchan;
5234
5235 if (chan && IS_CHAN_HT40(chan))
5236 return ath9k_hw_mac_usec(ah, clks) / 2;
5237 else
5238 return ath9k_hw_mac_usec(ah, clks);
5239}
5240
5241static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
5242{
5243 if (ah->ah_curchan != NULL)
5244 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
5245 ah->ah_curchan)];
5246 else
5247 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
5248}
5249
5250static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
5251{
5252 struct ath9k_channel *chan = ah->ah_curchan;
5253
5254 if (chan && IS_CHAN_HT40(chan))
5255 return ath9k_hw_mac_clks(ah, usecs) * 2;
5256 else
5257 return ath9k_hw_mac_clks(ah, usecs);
5258}
5259
5260static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
5261{
5262 struct ath_hal_5416 *ahp = AH5416(ah);
5263
5264 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
5265 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
5266 __func__, us);
5267 ahp->ah_acktimeout = (u32) -1;
5268 return false;
5269 } else {
5270 REG_RMW_FIELD(ah, AR_TIME_OUT,
5271 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
5272 ahp->ah_acktimeout = us;
5273 return true;
5274 }
5275}
5276
5277static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
5278{
5279 struct ath_hal_5416 *ahp = AH5416(ah);
5280
5281 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
5282 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
5283 __func__, us);
5284 ahp->ah_ctstimeout = (u32) -1;
5285 return false;
5286 } else {
5287 REG_RMW_FIELD(ah, AR_TIME_OUT,
5288 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
5289 ahp->ah_ctstimeout = us;
5290 return true;
5291 }
5292}
5293static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
5294 u32 tu)
5295{
5296 struct ath_hal_5416 *ahp = AH5416(ah);
5297
5298 if (tu > 0xFFFF) {
5299 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
5300 "%s: bad global tx timeout %u\n", __func__, tu);
5301 ahp->ah_globaltxtimeout = (u32) -1;
5302 return false;
5303 } else {
5304 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
5305 ahp->ah_globaltxtimeout = tu;
5306 return true;
5307 }
5308}
5309
5310bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
5311{
5312 struct ath_hal_5416 *ahp = AH5416(ah);
5313
5314 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
5315 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
5316 __func__, us);
5317 ahp->ah_slottime = (u32) -1;
5318 return false;
5319 } else {
5320 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
5321 ahp->ah_slottime = us;
5322 return true;
5323 }
5324}
5325
5326static void ath9k_hw_init_user_settings(struct ath_hal *ah)
5327{
5328 struct ath_hal_5416 *ahp = AH5416(ah);
5329
5330 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
5331 __func__, ahp->ah_miscMode);
5332 if (ahp->ah_miscMode != 0)
5333 REG_WRITE(ah, AR_PCU_MISC,
5334 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
5335 if (ahp->ah_slottime != (u32) -1)
5336 ath9k_hw_setslottime(ah, ahp->ah_slottime);
5337 if (ahp->ah_acktimeout != (u32) -1)
5338 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
5339 if (ahp->ah_ctstimeout != (u32) -1)
5340 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
5341 if (ahp->ah_globaltxtimeout != (u32) -1)
5342 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
5343}
5344
5345static int
5346ath9k_hw_process_ini(struct ath_hal *ah,
5347 struct ath9k_channel *chan,
5348 enum ath9k_ht_macmode macmode)
5349{
5350 int i, regWrites = 0;
5351 struct ath_hal_5416 *ahp = AH5416(ah);
5352 u32 modesIndex, freqIndex;
5353 int status;
5354
5355 switch (chan->chanmode) {
5356 case CHANNEL_A:
5357 case CHANNEL_A_HT20:
5358 modesIndex = 1;
5359 freqIndex = 1;
5360 break;
5361 case CHANNEL_A_HT40PLUS:
5362 case CHANNEL_A_HT40MINUS:
5363 modesIndex = 2;
5364 freqIndex = 1;
5365 break;
5366 case CHANNEL_G:
5367 case CHANNEL_G_HT20:
5368 case CHANNEL_B:
5369 modesIndex = 4;
5370 freqIndex = 2;
5371 break;
5372 case CHANNEL_G_HT40PLUS:
5373 case CHANNEL_G_HT40MINUS:
5374 modesIndex = 3;
5375 freqIndex = 2;
5376 break;
5377
5378 default:
5379 return -EINVAL;
5380 }
5381
5382 REG_WRITE(ah, AR_PHY(0), 0x00000007);
5383
5384 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
5385
5386 ath9k_hw_set_addac(ah, chan);
5387
5388 if (AR_SREV_5416_V22_OR_LATER(ah)) {
5389 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
5390 } else {
5391 struct ar5416IniArray temp;
5392 u32 addacSize =
5393 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
5394 ahp->ah_iniAddac.ia_columns;
5395
5396 memcpy(ahp->ah_addac5416_21,
5397 ahp->ah_iniAddac.ia_array, addacSize);
5398
5399 (ahp->ah_addac5416_21)[31 *
5400 ahp->ah_iniAddac.ia_columns + 1] = 0;
5401
5402 temp.ia_array = ahp->ah_addac5416_21;
5403 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
5404 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
5405 REG_WRITE_ARRAY(&temp, 1, regWrites);
5406 }
5407 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
5408
5409 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
5410 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
5411 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
5412
5413#ifdef CONFIG_SLOW_ANT_DIV
5414 if (ah->ah_devid == AR9280_DEVID_PCI)
5415 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg,
5416 val);
5417#endif
5418
5419 REG_WRITE(ah, reg, val);
5420
5421 if (reg >= 0x7800 && reg < 0x78a0
5422 && ah->ah_config.analog_shiftreg) {
5423 udelay(100);
5424 }
5425
5426 DO_DELAY(regWrites);
5427 }
5428
5429 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
5430 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
5431 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
5432
5433 REG_WRITE(ah, reg, val);
5434
5435 if (reg >= 0x7800 && reg < 0x78a0
5436 && ah->ah_config.analog_shiftreg) {
5437 udelay(100);
5438 }
5439
5440 DO_DELAY(regWrites);
5441 }
5442
5443 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
5444
5445 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
5446 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
5447 regWrites);
5448 }
5449
5450 ath9k_hw_override_ini(ah, chan);
5451 ath9k_hw_set_regs(ah, chan, macmode);
5452 ath9k_hw_init_chain_masks(ah);
5453
5454 status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5455 ath9k_regd_get_ctl(ah, chan),
5456 ath9k_regd_get_antenna_allowed(ah,
5457 chan),
5458 chan->maxRegTxPower * 2,
5459 min((u32) MAX_RATE_POWER,
5460 (u32) ah->ah_powerLimit));
5461 if (status != 0) {
5462 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
5463 "%s: error init'ing transmit power\n", __func__);
5464 return -EIO;
5465 }
5466
5467 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
5468 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
5469 "%s: ar5416SetRfRegs failed\n", __func__);
5470 return -EIO;
5471 }
5472
5473 return 0;
5474}
5475
5476static void ath9k_hw_setup_calibration(struct ath_hal *ah,
5477 struct hal_cal_list *currCal)
5478{
5479 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
5480 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
5481 currCal->calData->calCountMax);
5482
5483 switch (currCal->calData->calType) {
5484 case IQ_MISMATCH_CAL:
5485 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
5486 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5487 "%s: starting IQ Mismatch Calibration\n",
5488 __func__);
5489 break;
5490 case ADC_GAIN_CAL:
5491 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
5492 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5493 "%s: starting ADC Gain Calibration\n", __func__);
5494 break;
5495 case ADC_DC_CAL:
5496 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
5497 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5498 "%s: starting ADC DC Calibration\n", __func__);
5499 break;
5500 case ADC_DC_INIT_CAL:
5501 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
5502 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5503 "%s: starting Init ADC DC Calibration\n",
5504 __func__);
5505 break;
5506 }
5507
5508 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
5509 AR_PHY_TIMING_CTRL4_DO_CAL);
5510}
5511
5512static void ath9k_hw_reset_calibration(struct ath_hal *ah,
5513 struct hal_cal_list *currCal)
5514{
5515 struct ath_hal_5416 *ahp = AH5416(ah);
5516 int i;
5517
5518 ath9k_hw_setup_calibration(ah, currCal);
5519
5520 currCal->calState = CAL_RUNNING;
5521
5522 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5523 ahp->ah_Meas0.sign[i] = 0;
5524 ahp->ah_Meas1.sign[i] = 0;
5525 ahp->ah_Meas2.sign[i] = 0;
5526 ahp->ah_Meas3.sign[i] = 0;
5527 }
5528
5529 ahp->ah_CalSamples = 0;
5530}
5531
5532static void
5533ath9k_hw_per_calibration(struct ath_hal *ah,
5534 struct ath9k_channel *ichan,
5535 u8 rxchainmask,
5536 struct hal_cal_list *currCal,
5537 bool *isCalDone)
5538{
5539 struct ath_hal_5416 *ahp = AH5416(ah);
5540
5541 *isCalDone = false;
5542
5543 if (currCal->calState == CAL_RUNNING) {
5544 if (!(REG_READ(ah,
5545 AR_PHY_TIMING_CTRL4(0)) &
5546 AR_PHY_TIMING_CTRL4_DO_CAL)) {
5547
5548 currCal->calData->calCollect(ah);
5549
5550 ahp->ah_CalSamples++;
5551
5552 if (ahp->ah_CalSamples >=
5553 currCal->calData->calNumSamples) {
5554 int i, numChains = 0;
5555 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5556 if (rxchainmask & (1 << i))
5557 numChains++;
5558 }
5559
5560 currCal->calData->calPostProc(ah,
5561 numChains);
5562
5563 ichan->CalValid |=
5564 currCal->calData->calType;
5565 currCal->calState = CAL_DONE;
5566 *isCalDone = true;
5567 } else {
5568 ath9k_hw_setup_calibration(ah, currCal);
5569 }
5570 }
5571 } else if (!(ichan->CalValid & currCal->calData->calType)) {
5572 ath9k_hw_reset_calibration(ah, currCal);
5573 }
5574}
5575
5576static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
5577 int init_cal_count)
5578{
5579 struct ath_hal_5416 *ahp = AH5416(ah);
5580 struct ath9k_channel ichan;
5581 bool isCalDone;
5582 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
5583 const struct hal_percal_data *calData = currCal->calData;
5584 int i;
5585
5586 if (currCal == NULL)
5587 return false;
5588
5589 ichan.CalValid = 0;
5590
5591 for (i = 0; i < init_cal_count; i++) {
5592 ath9k_hw_reset_calibration(ah, currCal);
5593
5594 if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
5595 AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
5596 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5597 "%s: Cal %d failed to complete in 100ms.\n",
5598 __func__, calData->calType);
5599
5600 ahp->ah_cal_list = ahp->ah_cal_list_last =
5601 ahp->ah_cal_list_curr = NULL;
5602 return false;
5603 }
5604
5605 ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
5606 currCal, &isCalDone);
5607 if (!isCalDone) {
5608 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5609 "%s: Not able to run Init Cal %d.\n",
5610 __func__, calData->calType);
5611 }
5612 if (currCal->calNext) {
5613 currCal = currCal->calNext;
5614 calData = currCal->calData;
5615 }
5616 }
5617
5618 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
5619 return true;
5620}
5621
5622static bool
5623ath9k_hw_channel_change(struct ath_hal *ah,
5624 struct ath9k_channel *chan,
5625 enum ath9k_ht_macmode macmode)
5626{
5627 u32 synthDelay, qnum;
5628 struct ath_hal_5416 *ahp = AH5416(ah);
5629
5630 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
5631 if (ath9k_hw_numtxpending(ah, qnum)) {
5632 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5633 "%s: Transmit frames pending on queue %d\n",
5634 __func__, qnum);
5635 return false;
5636 }
5637 }
5638
5639 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
5640 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
5641 AR_PHY_RFBUS_GRANT_EN)) {
5642 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
5643 "%s: Could not kill baseband RX\n", __func__);
5644 return false;
5645 }
5646
5647 ath9k_hw_set_regs(ah, chan, macmode);
5648
5649 if (AR_SREV_9280_10_OR_LATER(ah)) {
5650 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
5651 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5652 "%s: failed to set channel\n", __func__);
5653 return false;
5654 }
5655 } else {
5656 if (!(ath9k_hw_set_channel(ah, chan))) {
5657 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5658 "%s: failed to set channel\n", __func__);
5659 return false;
5660 }
5661 }
5662
5663 if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5664 ath9k_regd_get_ctl(ah, chan),
5665 ath9k_regd_get_antenna_allowed(ah, chan),
5666 chan->maxRegTxPower * 2,
5667 min((u32) MAX_RATE_POWER,
5668 (u32) ah->ah_powerLimit)) != 0) {
5669 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5670 "%s: error init'ing transmit power\n", __func__);
5671 return false;
5672 }
5673
5674 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
5675 if (IS_CHAN_CCK(chan))
5676 synthDelay = (4 * synthDelay) / 22;
5677 else
5678 synthDelay /= 10;
5679
5680 udelay(synthDelay + BASE_ACTIVATE_DELAY);
5681
5682 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
5683
5684 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5685 ath9k_hw_set_delta_slope(ah, chan);
5686
5687 if (AR_SREV_9280_10_OR_LATER(ah))
5688 ath9k_hw_9280_spur_mitigate(ah, chan);
5689 else
5690 ath9k_hw_spur_mitigate(ah, chan);
5691
5692 if (!chan->oneTimeCalsDone)
5693 chan->oneTimeCalsDone = true;
5694
5695 return true;
5696}
5697
5698static bool ath9k_hw_chip_reset(struct ath_hal *ah,
5699 struct ath9k_channel *chan)
5700{
5701 struct ath_hal_5416 *ahp = AH5416(ah);
5702
5703 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
5704 return false;
5705
5706 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5707 return false;
5708
5709 ahp->ah_chipFullSleep = false;
5710
5711 ath9k_hw_init_pll(ah, chan);
5712
5713 ath9k_hw_set_rfmode(ah, chan);
5714
5715 return true;
5716}
5717
5718static inline void ath9k_hw_set_dma(struct ath_hal *ah)
5719{
5720 u32 regval;
5721
5722 regval = REG_READ(ah, AR_AHB_MODE);
5723 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
5724
5725 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
5726 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
5727
5728 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
5729
5730 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
5731 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
5732
5733 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
5734
5735 if (AR_SREV_9285(ah)) {
5736 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5737 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
5738 } else {
5739 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5740 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
5741 }
5742}
5743
5744bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
5745{
5746 REG_WRITE(ah, AR_CR, AR_CR_RXD);
5747 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
5748 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5749 "%s: dma failed to stop in 10ms\n"
5750 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
5751 __func__,
5752 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
5753 return false;
5754 } else {
5755 return true;
5756 }
5757}
5758
5759void ath9k_hw_startpcureceive(struct ath_hal *ah)
5760{
5761 REG_CLR_BIT(ah, AR_DIAG_SW,
5762 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
5763
5764 ath9k_enable_mib_counters(ah);
5765
5766 ath9k_ani_reset(ah);
5767}
5768
5769void ath9k_hw_stoppcurecv(struct ath_hal *ah)
5770{
5771 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
5772
5773 ath9k_hw_disable_mib_counters(ah);
5774}
5775
5776static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
5777 struct ath9k_channel *chan,
5778 enum hal_cal_types calType)
5779{
5780 struct ath_hal_5416 *ahp = AH5416(ah);
5781 bool retval = false;
5782
5783 switch (calType & ahp->ah_suppCals) {
5784 case IQ_MISMATCH_CAL:
5785 if (!IS_CHAN_B(chan))
5786 retval = true;
5787 break;
5788 case ADC_GAIN_CAL:
5789 case ADC_DC_CAL:
5790 if (!IS_CHAN_B(chan)
5791 && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
5792 retval = true;
5793 break;
5794 }
5795
5796 return retval;
5797}
5798
5799static bool ath9k_hw_init_cal(struct ath_hal *ah,
5800 struct ath9k_channel *chan)
5801{
5802 struct ath_hal_5416 *ahp = AH5416(ah);
5803 struct ath9k_channel *ichan =
5804 ath9k_regd_check_channel(ah, chan);
5805
5806 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5807 REG_READ(ah, AR_PHY_AGC_CONTROL) |
5808 AR_PHY_AGC_CONTROL_CAL);
5809
5810 if (!ath9k_hw_wait
5811 (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
5812 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5813 "%s: offset calibration failed to complete in 1ms; "
5814 "noisy environment?\n", __func__);
5815 return false;
5816 }
5817
5818 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5819 REG_READ(ah, AR_PHY_AGC_CONTROL) |
5820 AR_PHY_AGC_CONTROL_NF);
5821
5822 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr =
5823 NULL;
5824
5825 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
5826 if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
5827 INIT_CAL(&ahp->ah_adcGainCalData);
5828 INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
5829 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5830 "%s: enabling ADC Gain Calibration.\n",
5831 __func__);
5832 }
5833 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
5834 INIT_CAL(&ahp->ah_adcDcCalData);
5835 INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
5836 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5837 "%s: enabling ADC DC Calibration.\n",
5838 __func__);
5839 }
5840 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
5841 INIT_CAL(&ahp->ah_iqCalData);
5842 INSERT_CAL(ahp, &ahp->ah_iqCalData);
5843 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5844 "%s: enabling IQ Calibration.\n",
5845 __func__);
5846 }
5847
5848 ahp->ah_cal_list_curr = ahp->ah_cal_list;
5849
5850 if (ahp->ah_cal_list_curr)
5851 ath9k_hw_reset_calibration(ah,
5852 ahp->ah_cal_list_curr);
5853 }
5854
5855 ichan->CalValid = 0;
5856
5857 return true;
5858}
5859
5860
5861bool ath9k_hw_reset(struct ath_hal *ah,
5862 struct ath9k_channel *chan,
5863 enum ath9k_ht_macmode macmode, 2126 enum ath9k_ht_macmode macmode,
5864 u8 txchainmask, u8 rxchainmask, 2127 u8 txchainmask, u8 rxchainmask,
5865 enum ath9k_ht_extprotspacing extprotspacing, 2128 enum ath9k_ht_extprotspacing extprotspacing,
5866 bool bChannelChange, 2129 bool bChannelChange, int *status)
5867 int *status)
5868{ 2130{
5869 u32 saveLedState; 2131 u32 saveLedState;
5870 struct ath_hal_5416 *ahp = AH5416(ah); 2132 struct ath_hal_5416 *ahp = AH5416(ah);
@@ -5885,8 +2147,8 @@ bool ath9k_hw_reset(struct ath_hal *ah,
5885 2147
5886 if (ath9k_hw_check_chan(ah, chan) == NULL) { 2148 if (ath9k_hw_check_chan(ah, chan) == NULL) {
5887 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 2149 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5888 "%s: invalid channel %u/0x%x; no mapping\n", 2150 "%s: invalid channel %u/0x%x; no mapping\n",
5889 __func__, chan->channel, chan->channelFlags); 2151 __func__, chan->channel, chan->channelFlags);
5890 ecode = -EINVAL; 2152 ecode = -EINVAL;
5891 goto bad; 2153 goto bad;
5892 } 2154 }
@@ -5964,7 +2226,7 @@ bool ath9k_hw_reset(struct ath_hal *ah,
5964 2226
5965 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { 2227 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
5966 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 2228 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5967 "%s: error setting board options\n", __func__); 2229 "%s: error setting board options\n", __func__);
5968 ecode = -EIO; 2230 ecode = -EIO;
5969 goto bad; 2231 goto bad;
5970 } 2232 }
@@ -6054,15 +2316,15 @@ bool ath9k_hw_reset(struct ath_hal *ah,
6054 mask = REG_READ(ah, AR_CFG); 2316 mask = REG_READ(ah, AR_CFG);
6055 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2317 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
6056 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2318 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6057 "%s CFG Byte Swap Set 0x%x\n", __func__, 2319 "%s CFG Byte Swap Set 0x%x\n", __func__,
6058 mask); 2320 mask);
6059 } else { 2321 } else {
6060 mask = 2322 mask =
6061 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2323 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
6062 REG_WRITE(ah, AR_CFG, mask); 2324 REG_WRITE(ah, AR_CFG, mask);
6063 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2325 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6064 "%s Setting CFG 0x%x\n", __func__, 2326 "%s Setting CFG 0x%x\n", __func__,
6065 REG_READ(ah, AR_CFG)); 2327 REG_READ(ah, AR_CFG));
6066 } 2328 }
6067 } else { 2329 } else {
6068#ifdef __BIG_ENDIAN 2330#ifdef __BIG_ENDIAN
@@ -6077,692 +2339,403 @@ bad:
6077 return false; 2339 return false;
6078} 2340}
6079 2341
6080bool ath9k_hw_phy_disable(struct ath_hal *ah) 2342/************************/
6081{ 2343/* Key Cache Management */
6082 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); 2344/************************/
6083}
6084
6085bool ath9k_hw_disable(struct ath_hal *ah)
6086{
6087 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
6088 return false;
6089
6090 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
6091}
6092 2345
6093bool 2346bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
6094ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
6095 u8 rxchainmask, bool longcal,
6096 bool *isCalDone)
6097{ 2347{
6098 struct ath_hal_5416 *ahp = AH5416(ah); 2348 u32 keyType;
6099 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6100 struct ath9k_channel *ichan =
6101 ath9k_regd_check_channel(ah, chan);
6102
6103 *isCalDone = true;
6104 2349
6105 if (ichan == NULL) { 2350 if (entry >= ah->ah_caps.keycache_size) {
6106 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 2351 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
6107 "%s: invalid channel %u/0x%x; no mapping\n", 2352 "%s: entry %u out of range\n", __func__, entry);
6108 __func__, chan->channel, chan->channelFlags);
6109 return false; 2353 return false;
6110 } 2354 }
6111 2355
6112 if (currCal && 2356 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
6113 (currCal->calState == CAL_RUNNING ||
6114 currCal->calState == CAL_WAITING)) {
6115 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
6116 isCalDone);
6117 if (*isCalDone) {
6118 ahp->ah_cal_list_curr = currCal = currCal->calNext;
6119
6120 if (currCal->calState == CAL_WAITING) {
6121 *isCalDone = false;
6122 ath9k_hw_reset_calibration(ah, currCal);
6123 }
6124 }
6125 }
6126 2357
6127 if (longcal) { 2358 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
6128 ath9k_hw_getnf(ah, ichan); 2359 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
6129 ath9k_hw_loadnf(ah, ah->ah_curchan); 2360 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
6130 ath9k_hw_start_nfcal(ah); 2361 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2362 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2363 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2364 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2365 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2366
2367 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2368 u16 micentry = entry + 64;
6131 2369
6132 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) { 2370 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2371 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2372 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2373 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
6133 2374
6134 chan->channelFlags |= CHANNEL_CW_INT;
6135 ichan->channelFlags &= ~CHANNEL_CW_INT;
6136 }
6137 } 2375 }
6138 2376
2377 if (ah->ah_curchan == NULL)
2378 return true;
2379
6139 return true; 2380 return true;
6140} 2381}
6141 2382
6142static void ath9k_hw_iqcal_collect(struct ath_hal *ah) 2383bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
6143{ 2384{
6144 struct ath_hal_5416 *ahp = AH5416(ah); 2385 u32 macHi, macLo;
6145 int i;
6146 2386
6147 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2387 if (entry >= ah->ah_caps.keycache_size) {
6148 ahp->ah_totalPowerMeasI[i] += 2388 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
6149 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 2389 "%s: entry %u out of range\n", __func__, entry);
6150 ahp->ah_totalPowerMeasQ[i] += 2390 return false;
6151 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6152 ahp->ah_totalIqCorrMeas[i] +=
6153 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6154 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6155 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
6156 ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
6157 ahp->ah_totalPowerMeasQ[i],
6158 ahp->ah_totalIqCorrMeas[i]);
6159 } 2391 }
6160}
6161 2392
6162static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah) 2393 if (mac != NULL) {
6163{ 2394 macHi = (mac[5] << 8) | mac[4];
6164 struct ath_hal_5416 *ahp = AH5416(ah); 2395 macLo = (mac[3] << 24) |
6165 int i; 2396 (mac[2] << 16) |
6166 2397 (mac[1] << 8) |
6167 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2398 mac[0];
6168 ahp->ah_totalAdcIOddPhase[i] += 2399 macLo >>= 1;
6169 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 2400 macLo |= (macHi & 1) << 31;
6170 ahp->ah_totalAdcIEvenPhase[i] += 2401 macHi >>= 1;
6171 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 2402 } else {
6172 ahp->ah_totalAdcQOddPhase[i] += 2403 macLo = macHi = 0;
6173 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6174 ahp->ah_totalAdcQEvenPhase[i] +=
6175 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6176
6177 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6178 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6179 "oddq=0x%08x; evenq=0x%08x;\n",
6180 ahp->ah_CalSamples, i,
6181 ahp->ah_totalAdcIOddPhase[i],
6182 ahp->ah_totalAdcIEvenPhase[i],
6183 ahp->ah_totalAdcQOddPhase[i],
6184 ahp->ah_totalAdcQEvenPhase[i]);
6185 } 2404 }
2405 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2406 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2407
2408 return true;
6186} 2409}
6187 2410
6188static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah) 2411bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2412 const struct ath9k_keyval *k,
2413 const u8 *mac, int xorKey)
6189{ 2414{
2415 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2416 u32 key0, key1, key2, key3, key4;
2417 u32 keyType;
2418 u32 xorMask = xorKey ?
2419 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2420 | ATH9K_KEY_XOR) : 0;
6190 struct ath_hal_5416 *ahp = AH5416(ah); 2421 struct ath_hal_5416 *ahp = AH5416(ah);
6191 int i;
6192 2422
6193 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2423 if (entry >= pCap->keycache_size) {
6194 ahp->ah_totalAdcDcOffsetIOddPhase[i] += 2424 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
6195 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 2425 "%s: entry %u out of range\n", __func__, entry);
6196 ahp->ah_totalAdcDcOffsetIEvenPhase[i] += 2426 return false;
6197 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6198 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
6199 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6200 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
6201 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6202
6203 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6204 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6205 "oddq=0x%08x; evenq=0x%08x;\n",
6206 ahp->ah_CalSamples, i,
6207 ahp->ah_totalAdcDcOffsetIOddPhase[i],
6208 ahp->ah_totalAdcDcOffsetIEvenPhase[i],
6209 ahp->ah_totalAdcDcOffsetQOddPhase[i],
6210 ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
6211 } 2427 }
6212}
6213 2428
6214static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) 2429 switch (k->kv_type) {
6215{ 2430 case ATH9K_CIPHER_AES_OCB:
6216 struct ath_hal_5416 *ahp = AH5416(ah); 2431 keyType = AR_KEYTABLE_TYPE_AES;
6217 u32 powerMeasQ, powerMeasI, iqCorrMeas; 2432 break;
6218 u32 qCoffDenom, iCoffDenom; 2433 case ATH9K_CIPHER_AES_CCM:
6219 int32_t qCoff, iCoff; 2434 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
6220 int iqCorrNeg, i; 2435 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2436 "%s: AES-CCM not supported by "
2437 "mac rev 0x%x\n", __func__,
2438 ah->ah_macRev);
2439 return false;
2440 }
2441 keyType = AR_KEYTABLE_TYPE_CCM;
2442 break;
2443 case ATH9K_CIPHER_TKIP:
2444 keyType = AR_KEYTABLE_TYPE_TKIP;
2445 if (ATH9K_IS_MIC_ENABLED(ah)
2446 && entry + 64 >= pCap->keycache_size) {
2447 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2448 "%s: entry %u inappropriate for TKIP\n",
2449 __func__, entry);
2450 return false;
2451 }
2452 break;
2453 case ATH9K_CIPHER_WEP:
2454 if (k->kv_len < LEN_WEP40) {
2455 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2456 "%s: WEP key length %u too small\n",
2457 __func__, k->kv_len);
2458 return false;
2459 }
2460 if (k->kv_len <= LEN_WEP40)
2461 keyType = AR_KEYTABLE_TYPE_40;
2462 else if (k->kv_len <= LEN_WEP104)
2463 keyType = AR_KEYTABLE_TYPE_104;
2464 else
2465 keyType = AR_KEYTABLE_TYPE_128;
2466 break;
2467 case ATH9K_CIPHER_CLR:
2468 keyType = AR_KEYTABLE_TYPE_CLR;
2469 break;
2470 default:
2471 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2472 "%s: cipher %u not supported\n", __func__,
2473 k->kv_type);
2474 return false;
2475 }
6221 2476
6222 for (i = 0; i < numChains; i++) { 2477 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
6223 powerMeasI = ahp->ah_totalPowerMeasI[i]; 2478 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
6224 powerMeasQ = ahp->ah_totalPowerMeasQ[i]; 2479 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
6225 iqCorrMeas = ahp->ah_totalIqCorrMeas[i]; 2480 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2481 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2482 if (k->kv_len <= LEN_WEP104)
2483 key4 &= 0xff;
6226 2484
6227 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 2485 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
6228 "Starting IQ Cal and Correction for Chain %d\n", 2486 u16 micentry = entry + 64;
6229 i);
6230 2487
6231 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 2488 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
6232 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 2489 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
6233 i, ahp->ah_totalIqCorrMeas[i]); 2490 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2491 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2492 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2493 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2494 (void) ath9k_hw_keysetmac(ah, entry, mac);
6234 2495
6235 iqCorrNeg = 0; 2496 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2497 u32 mic0, mic1, mic2, mic3, mic4;
6236 2498
2499 mic0 = get_unaligned_le32(k->kv_mic + 0);
2500 mic2 = get_unaligned_le32(k->kv_mic + 4);
2501 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2502 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2503 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2504 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2505 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2506 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2507 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2508 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2509 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2510 AR_KEYTABLE_TYPE_CLR);
6237 2511
6238 if (iqCorrMeas > 0x80000000) { 2512 } else {
6239 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1; 2513 u32 mic0, mic2;
6240 iqCorrNeg = 1;
6241 }
6242 2514
6243 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 2515 mic0 = get_unaligned_le32(k->kv_mic + 0);
6244 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 2516 mic2 = get_unaligned_le32(k->kv_mic + 4);
6245 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 2517 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
6246 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 2518 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
6247 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 2519 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
6248 iqCorrNeg); 2520 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
6249 2521 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
6250 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 2522 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
6251 qCoffDenom = powerMeasQ / 64; 2523 AR_KEYTABLE_TYPE_CLR);
6252
6253 if (powerMeasQ != 0) {
6254
6255 iCoff = iqCorrMeas / iCoffDenom;
6256 qCoff = powerMeasI / qCoffDenom - 64;
6257 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6258 "Chn %d iCoff = 0x%08x\n", i, iCoff);
6259 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6260 "Chn %d qCoff = 0x%08x\n", i, qCoff);
6261
6262
6263 iCoff = iCoff & 0x3f;
6264 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6265 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
6266 if (iqCorrNeg == 0x0)
6267 iCoff = 0x40 - iCoff;
6268
6269 if (qCoff > 15)
6270 qCoff = 15;
6271 else if (qCoff <= -16)
6272 qCoff = 16;
6273
6274 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6275 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
6276 i, iCoff, qCoff);
6277
6278 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6279 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
6280 iCoff);
6281 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6282 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
6283 qCoff);
6284 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6285 "IQ Cal and Correction done for Chain %d\n",
6286 i);
6287 } 2524 }
6288 } 2525 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
6289 2526 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
6290 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), 2527 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
6291 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 2528 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
6292} 2529 } else {
2530 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2531 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2532 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2533 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2534 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2535 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
6293 2536
6294static void 2537 (void) ath9k_hw_keysetmac(ah, entry, mac);
6295ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
6296{
6297 struct ath_hal_5416 *ahp = AH5416(ah);
6298 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
6299 qEvenMeasOffset;
6300 u32 qGainMismatch, iGainMismatch, val, i;
6301
6302 for (i = 0; i < numChains; i++) {
6303 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
6304 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
6305 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
6306 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
6307
6308 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6309 "Starting ADC Gain Cal for Chain %d\n", i);
6310
6311 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6312 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
6313 iOddMeasOffset);
6314 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6315 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
6316 iEvenMeasOffset);
6317 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6318 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
6319 qOddMeasOffset);
6320 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6321 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
6322 qEvenMeasOffset);
6323
6324 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
6325 iGainMismatch =
6326 ((iEvenMeasOffset * 32) /
6327 iOddMeasOffset) & 0x3f;
6328 qGainMismatch =
6329 ((qOddMeasOffset * 32) /
6330 qEvenMeasOffset) & 0x3f;
6331
6332 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6333 "Chn %d gain_mismatch_i = 0x%08x\n", i,
6334 iGainMismatch);
6335 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6336 "Chn %d gain_mismatch_q = 0x%08x\n", i,
6337 qGainMismatch);
6338
6339 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6340 val &= 0xfffff000;
6341 val |= (qGainMismatch) | (iGainMismatch << 6);
6342 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6343
6344 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6345 "ADC Gain Cal done for Chain %d\n", i);
6346 }
6347 } 2538 }
6348 2539
6349 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), 2540 if (ah->ah_curchan == NULL)
6350 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | 2541 return true;
6351 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); 2542
2543 return true;
6352} 2544}
6353 2545
6354static void 2546bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
6355ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
6356{ 2547{
6357 struct ath_hal_5416 *ahp = AH5416(ah); 2548 if (entry < ah->ah_caps.keycache_size) {
6358 u32 iOddMeasOffset, iEvenMeasOffset, val, i; 2549 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
6359 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; 2550 if (val & AR_KEYTABLE_VALID)
6360 const struct hal_percal_data *calData = 2551 return true;
6361 ahp->ah_cal_list_curr->calData;
6362 u32 numSamples =
6363 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
6364
6365 for (i = 0; i < numChains; i++) {
6366 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
6367 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
6368 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
6369 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
6370
6371 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6372 "Starting ADC DC Offset Cal for Chain %d\n", i);
6373
6374 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6375 "Chn %d pwr_meas_odd_i = %d\n", i,
6376 iOddMeasOffset);
6377 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6378 "Chn %d pwr_meas_even_i = %d\n", i,
6379 iEvenMeasOffset);
6380 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6381 "Chn %d pwr_meas_odd_q = %d\n", i,
6382 qOddMeasOffset);
6383 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6384 "Chn %d pwr_meas_even_q = %d\n", i,
6385 qEvenMeasOffset);
6386
6387 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
6388 numSamples) & 0x1ff;
6389 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
6390 numSamples) & 0x1ff;
6391
6392 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6393 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
6394 iDcMismatch);
6395 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6396 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
6397 qDcMismatch);
6398
6399 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6400 val &= 0xc0000fff;
6401 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
6402 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6403
6404 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6405 "ADC DC Offset Cal done for Chain %d\n", i);
6406 } 2552 }
6407 2553 return false;
6408 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6409 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6410 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
6411} 2554}
6412 2555
6413bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) 2556/******************************/
6414{ 2557/* Power Management (Chipset) */
6415 struct ath_hal_5416 *ahp = AH5416(ah); 2558/******************************/
6416 struct ath9k_channel *chan = ah->ah_curchan;
6417
6418 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
6419
6420 if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
6421 ath9k_regd_get_ctl(ah, chan),
6422 ath9k_regd_get_antenna_allowed(ah,
6423 chan),
6424 chan->maxRegTxPower * 2,
6425 min((u32) MAX_RATE_POWER,
6426 (u32) ah->ah_powerLimit)) != 0)
6427 return false;
6428 2559
6429 return true; 2560static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
6430}
6431
6432void
6433ath9k_hw_get_channel_centers(struct ath_hal *ah,
6434 struct ath9k_channel *chan,
6435 struct chan_centers *centers)
6436{ 2561{
6437 int8_t extoff; 2562 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
6438 struct ath_hal_5416 *ahp = AH5416(ah); 2563 if (setChip) {
6439 2564 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
6440 if (!IS_CHAN_HT40(chan)) { 2565 AR_RTC_FORCE_WAKE_EN);
6441 centers->ctl_center = centers->ext_center = 2566 if (!AR_SREV_9100(ah))
6442 centers->synth_center = chan->channel; 2567 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
6443 return;
6444 }
6445 2568
6446 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 2569 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
6447 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 2570 AR_RTC_RESET_EN);
6448 centers->synth_center =
6449 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
6450 extoff = 1;
6451 } else {
6452 centers->synth_center =
6453 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
6454 extoff = -1;
6455 } 2571 }
6456
6457 centers->ctl_center = centers->synth_center - (extoff *
6458 HT40_CHANNEL_CENTER_SHIFT);
6459 centers->ext_center = centers->synth_center + (extoff *
6460 ((ahp->
6461 ah_extprotspacing
6462 ==
6463 ATH9K_HT_EXTPROTSPACING_20)
6464 ?
6465 HT40_CHANNEL_CENTER_SHIFT
6466 : 15));
6467
6468} 2572}
6469 2573
6470void 2574static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
6471ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
6472 bool *isCalDone)
6473{ 2575{
6474 struct ath_hal_5416 *ahp = AH5416(ah); 2576 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
6475 struct ath9k_channel *ichan = 2577 if (setChip) {
6476 ath9k_regd_check_channel(ah, chan); 2578 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6477 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6478
6479 *isCalDone = true;
6480
6481 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
6482 return;
6483
6484 if (currCal == NULL)
6485 return;
6486
6487 if (ichan == NULL) {
6488 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6489 "%s: invalid channel %u/0x%x; no mapping\n",
6490 __func__, chan->channel, chan->channelFlags);
6491 return;
6492 }
6493
6494 2579
6495 if (currCal->calState != CAL_DONE) { 2580 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6496 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 2581 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
6497 "%s: Calibration state incorrect, %d\n", 2582 AR_RTC_FORCE_WAKE_ON_INT);
6498 __func__, currCal->calState); 2583 } else {
6499 return; 2584 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2585 AR_RTC_FORCE_WAKE_EN);
2586 }
6500 } 2587 }
6501
6502
6503 if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))
6504 return;
6505
6506 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6507 "%s: Resetting Cal %d state for channel %u/0x%x\n",
6508 __func__, currCal->calData->calType, chan->channel,
6509 chan->channelFlags);
6510
6511 ichan->CalValid &= ~currCal->calData->calType;
6512 currCal->calState = CAL_WAITING;
6513
6514 *isCalDone = false;
6515} 2588}
6516 2589
6517void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac) 2590static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2591 int setChip)
6518{ 2592{
6519 struct ath_hal_5416 *ahp = AH5416(ah); 2593 u32 val;
2594 int i;
6520 2595
6521 memcpy(mac, ahp->ah_macaddr, ETH_ALEN); 2596 if (setChip) {
6522} 2597 if ((REG_READ(ah, AR_RTC_STATUS) &
2598 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2599 if (ath9k_hw_set_reset_reg(ah,
2600 ATH9K_RESET_POWER_ON) != true) {
2601 return false;
2602 }
2603 }
2604 if (AR_SREV_9100(ah))
2605 REG_SET_BIT(ah, AR_RTC_RESET,
2606 AR_RTC_RESET_EN);
6523 2607
6524bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) 2608 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
6525{ 2609 AR_RTC_FORCE_WAKE_EN);
6526 struct ath_hal_5416 *ahp = AH5416(ah); 2610 udelay(50);
6527 2611
6528 memcpy(ahp->ah_macaddr, mac, ETH_ALEN); 2612 for (i = POWER_UP_TIME / 50; i > 0; i--) {
6529 return true; 2613 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
6530} 2614 if (val == AR_RTC_STATUS_ON)
2615 break;
2616 udelay(50);
2617 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2618 AR_RTC_FORCE_WAKE_EN);
2619 }
2620 if (i == 0) {
2621 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2622 "%s: Failed to wakeup in %uus\n",
2623 __func__, POWER_UP_TIME / 20);
2624 return false;
2625 }
2626 }
6531 2627
6532void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask) 2628 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
6533{
6534 struct ath_hal_5416 *ahp = AH5416(ah);
6535 2629
6536 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN); 2630 return true;
6537} 2631}
6538 2632
6539bool 2633bool ath9k_hw_setpower(struct ath_hal *ah,
6540ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask) 2634 enum ath9k_power_mode mode)
6541{ 2635{
6542 struct ath_hal_5416 *ahp = AH5416(ah); 2636 struct ath_hal_5416 *ahp = AH5416(ah);
2637 static const char *modes[] = {
2638 "AWAKE",
2639 "FULL-SLEEP",
2640 "NETWORK SLEEP",
2641 "UNDEFINED"
2642 };
2643 int status = true, setChip = true;
6543 2644
6544 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN); 2645 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
2646 modes[ahp->ah_powerMode], modes[mode],
2647 setChip ? "set chip " : "");
6545 2648
6546 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask)); 2649 switch (mode) {
6547 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4)); 2650 case ATH9K_PM_AWAKE:
2651 status = ath9k_hw_set_power_awake(ah, setChip);
2652 break;
2653 case ATH9K_PM_FULL_SLEEP:
2654 ath9k_set_power_sleep(ah, setChip);
2655 ahp->ah_chipFullSleep = true;
2656 break;
2657 case ATH9K_PM_NETWORK_SLEEP:
2658 ath9k_set_power_network_sleep(ah, setChip);
2659 break;
2660 default:
2661 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2662 "%s: unknown power mode %u\n", __func__, mode);
2663 return false;
2664 }
2665 ahp->ah_powerMode = mode;
6548 2666
6549 return true; 2667 return status;
6550} 2668}
6551 2669
6552void 2670void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
6553ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
6554 u16 assocId)
6555{ 2671{
6556 struct ath_hal_5416 *ahp = AH5416(ah); 2672 struct ath_hal_5416 *ahp = AH5416(ah);
2673 u8 i;
6557 2674
6558 memcpy(ahp->ah_bssid, bssid, ETH_ALEN); 2675 if (ah->ah_isPciExpress != true)
6559 ahp->ah_assocId = assocId; 2676 return;
6560
6561 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
6562 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
6563 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
6564}
6565
6566u64 ath9k_hw_gettsf64(struct ath_hal *ah)
6567{
6568 u64 tsf;
6569 2677
6570 tsf = REG_READ(ah, AR_TSF_U32); 2678 if (ah->ah_config.pcie_powersave_enable == 2)
6571 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); 2679 return;
6572 return tsf;
6573}
6574 2680
6575void ath9k_hw_reset_tsf(struct ath_hal *ah) 2681 if (restore)
6576{ 2682 return;
6577 int count;
6578 2683
6579 count = 0; 2684 if (AR_SREV_9280_20_OR_LATER(ah)) {
6580 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 2685 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
6581 count++; 2686 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
6582 if (count > 10) { 2687 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
6583 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6584 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
6585 __func__);
6586 break;
6587 } 2688 }
6588 udelay(10); 2689 udelay(1000);
6589 } 2690 } else if (AR_SREV_9280(ah) &&
6590 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2691 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
6591} 2692 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
6592 2693 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
6593u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
6594{
6595 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
6596}
6597 2694
6598void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna) 2695 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
6599{ 2696 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
6600 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2697 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
6601}
6602 2698
6603bool 2699 if (ah->ah_config.pcie_clock_req)
6604ath9k_hw_setantennaswitch(struct ath_hal *ah, 2700 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
6605 enum ath9k_ant_setting settings, 2701 else
6606 struct ath9k_channel *chan, 2702 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
6607 u8 *tx_chainmask,
6608 u8 *rx_chainmask,
6609 u8 *antenna_cfgd)
6610{
6611 struct ath_hal_5416 *ahp = AH5416(ah);
6612 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
6613 2703
6614 if (AR_SREV_9280(ah)) { 2704 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
6615 if (!tx_chainmask_cfg) { 2705 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2706 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
6616 2707
6617 tx_chainmask_cfg = *tx_chainmask; 2708 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
6618 rx_chainmask_cfg = *rx_chainmask;
6619 }
6620 2709
6621 switch (settings) { 2710 udelay(1000);
6622 case ATH9K_ANT_FIXED_A:
6623 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6624 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6625 *antenna_cfgd = true;
6626 break;
6627 case ATH9K_ANT_FIXED_B:
6628 if (ah->ah_caps.tx_chainmask >
6629 ATH9K_ANTENNA1_CHAINMASK) {
6630 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6631 }
6632 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6633 *antenna_cfgd = true;
6634 break;
6635 case ATH9K_ANT_VARIABLE:
6636 *tx_chainmask = tx_chainmask_cfg;
6637 *rx_chainmask = rx_chainmask_cfg;
6638 *antenna_cfgd = true;
6639 break;
6640 default:
6641 break;
6642 }
6643 } else { 2711 } else {
6644 ahp->ah_diversityControl = settings; 2712 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2713 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2714 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2715 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2716 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2717 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2718 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2719 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2720 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2721 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
6645 } 2722 }
6646 2723
6647 return true; 2724 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
6648}
6649
6650void ath9k_hw_setopmode(struct ath_hal *ah)
6651{
6652 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
6653}
6654
6655bool
6656ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
6657 u32 capability, u32 *result)
6658{
6659 struct ath_hal_5416 *ahp = AH5416(ah);
6660 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6661 2725
6662 switch (type) { 2726 if (ah->ah_config.pcie_waen) {
6663 case ATH9K_CAP_CIPHER: 2727 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
6664 switch (capability) { 2728 } else {
6665 case ATH9K_CIPHER_AES_CCM: 2729 if (AR_SREV_9280(ah))
6666 case ATH9K_CIPHER_AES_OCB: 2730 REG_WRITE(ah, AR_WA, 0x0040073f);
6667 case ATH9K_CIPHER_TKIP: 2731 else
6668 case ATH9K_CIPHER_WEP: 2732 REG_WRITE(ah, AR_WA, 0x0000073f);
6669 case ATH9K_CIPHER_MIC:
6670 case ATH9K_CIPHER_CLR:
6671 return true;
6672 default:
6673 return false;
6674 }
6675 case ATH9K_CAP_TKIP_MIC:
6676 switch (capability) {
6677 case 0:
6678 return true;
6679 case 1:
6680 return (ahp->ah_staId1Defaults &
6681 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
6682 false;
6683 }
6684 case ATH9K_CAP_TKIP_SPLIT:
6685 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
6686 false : true;
6687 case ATH9K_CAP_WME_TKIPMIC:
6688 return 0;
6689 case ATH9K_CAP_PHYCOUNTERS:
6690 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
6691 case ATH9K_CAP_DIVERSITY:
6692 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
6693 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
6694 true : false;
6695 case ATH9K_CAP_PHYDIAG:
6696 return true;
6697 case ATH9K_CAP_MCAST_KEYSRCH:
6698 switch (capability) {
6699 case 0:
6700 return true;
6701 case 1:
6702 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
6703 return false;
6704 } else {
6705 return (ahp->ah_staId1Defaults &
6706 AR_STA_ID1_MCAST_KSRCH) ? true :
6707 false;
6708 }
6709 }
6710 return false;
6711 case ATH9K_CAP_TSF_ADJUST:
6712 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
6713 true : false;
6714 case ATH9K_CAP_RFSILENT:
6715 if (capability == 3)
6716 return false;
6717 case ATH9K_CAP_ANT_CFG_2GHZ:
6718 *result = pCap->num_antcfg_2ghz;
6719 return true;
6720 case ATH9K_CAP_ANT_CFG_5GHZ:
6721 *result = pCap->num_antcfg_5ghz;
6722 return true;
6723 case ATH9K_CAP_TXPOW:
6724 switch (capability) {
6725 case 0:
6726 return 0;
6727 case 1:
6728 *result = ah->ah_powerLimit;
6729 return 0;
6730 case 2:
6731 *result = ah->ah_maxPowerLevel;
6732 return 0;
6733 case 3:
6734 *result = ah->ah_tpScale;
6735 return 0;
6736 }
6737 return false;
6738 default:
6739 return false;
6740 } 2733 }
6741} 2734}
6742 2735
6743int 2736/**********************/
6744ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg) 2737/* Interrupt Handling */
6745{ 2738/**********************/
6746 struct ath_hal_5416 *ahp = AH5416(ah);
6747 struct ath9k_channel *chan = ah->ah_curchan;
6748 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6749 u16 ant_config;
6750 u32 halNumAntConfig;
6751
6752 halNumAntConfig =
6753 IS_CHAN_2GHZ(chan) ? pCap->num_antcfg_2ghz : pCap->
6754 num_antcfg_5ghz;
6755
6756 if (cfg < halNumAntConfig) {
6757 if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan,
6758 cfg, &ant_config)) {
6759 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
6760 return 0;
6761 }
6762 }
6763
6764 return -EINVAL;
6765}
6766 2739
6767bool ath9k_hw_intrpend(struct ath_hal *ah) 2740bool ath9k_hw_intrpend(struct ath_hal *ah)
6768{ 2741{
@@ -6790,6 +2763,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6790 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2763 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6791 u32 sync_cause = 0; 2764 u32 sync_cause = 0;
6792 bool fatal_int = false; 2765 bool fatal_int = false;
2766 struct ath_hal_5416 *ahp = AH5416(ah);
6793 2767
6794 if (!AR_SREV_9100(ah)) { 2768 if (!AR_SREV_9100(ah)) {
6795 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2769 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -6799,9 +2773,8 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6799 } 2773 }
6800 } 2774 }
6801 2775
6802 sync_cause = 2776 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
6803 REG_READ(ah, 2777 AR_INTR_SYNC_DEFAULT;
6804 AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
6805 2778
6806 *masked = 0; 2779 *masked = 0;
6807 2780
@@ -6813,8 +2786,6 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6813 } 2786 }
6814 2787
6815 if (isr) { 2788 if (isr) {
6816 struct ath_hal_5416 *ahp = AH5416(ah);
6817
6818 if (isr & AR_ISR_BCNMISC) { 2789 if (isr & AR_ISR_BCNMISC) {
6819 u32 isr2; 2790 u32 isr2;
6820 isr2 = REG_READ(ah, AR_ISR_S2); 2791 isr2 = REG_READ(ah, AR_ISR_S2);
@@ -6841,7 +2812,6 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6841 *masked = isr & ATH9K_INT_COMMON; 2812 *masked = isr & ATH9K_INT_COMMON;
6842 2813
6843 if (ahp->ah_intrMitigation) { 2814 if (ahp->ah_intrMitigation) {
6844
6845 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2815 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
6846 *masked |= ATH9K_INT_RX; 2816 *masked |= ATH9K_INT_RX;
6847 } 2817 }
@@ -6866,8 +2836,8 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6866 2836
6867 if (isr & AR_ISR_RXORN) { 2837 if (isr & AR_ISR_RXORN) {
6868 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2838 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6869 "%s: receive FIFO overrun interrupt\n", 2839 "%s: receive FIFO overrun interrupt\n",
6870 __func__); 2840 __func__);
6871 } 2841 }
6872 2842
6873 if (!AR_SREV_9100(ah)) { 2843 if (!AR_SREV_9100(ah)) {
@@ -6880,8 +2850,10 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6880 2850
6881 *masked |= mask2; 2851 *masked |= mask2;
6882 } 2852 }
2853
6883 if (AR_SREV_9100(ah)) 2854 if (AR_SREV_9100(ah))
6884 return true; 2855 return true;
2856
6885 if (sync_cause) { 2857 if (sync_cause) {
6886 fatal_int = 2858 fatal_int =
6887 (sync_cause & 2859 (sync_cause &
@@ -6891,32 +2863,33 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6891 if (fatal_int) { 2863 if (fatal_int) {
6892 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 2864 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
6893 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2865 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6894 "%s: received PCI FATAL interrupt\n", 2866 "%s: received PCI FATAL interrupt\n",
6895 __func__); 2867 __func__);
6896 } 2868 }
6897 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 2869 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
6898 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2870 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6899 "%s: received PCI PERR interrupt\n", 2871 "%s: received PCI PERR interrupt\n",
6900 __func__); 2872 __func__);
6901 } 2873 }
6902 } 2874 }
6903 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 2875 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
6904 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2876 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6905 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n", 2877 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
6906 __func__); 2878 __func__);
6907 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 2879 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
6908 REG_WRITE(ah, AR_RC, 0); 2880 REG_WRITE(ah, AR_RC, 0);
6909 *masked |= ATH9K_INT_FATAL; 2881 *masked |= ATH9K_INT_FATAL;
6910 } 2882 }
6911 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 2883 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
6912 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2884 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6913 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n", 2885 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
6914 __func__); 2886 __func__);
6915 } 2887 }
6916 2888
6917 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 2889 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
6918 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 2890 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
6919 } 2891 }
2892
6920 return true; 2893 return true;
6921} 2894}
6922 2895
@@ -7034,9 +3007,11 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
7034 return omask; 3007 return omask;
7035} 3008}
7036 3009
7037void 3010/*******************/
7038ath9k_hw_beaconinit(struct ath_hal *ah, 3011/* Beacon Handling */
7039 u32 next_beacon, u32 beacon_period) 3012/*******************/
3013
3014void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
7040{ 3015{
7041 struct ath_hal_5416 *ahp = AH5416(ah); 3016 struct ath_hal_5416 *ahp = AH5416(ah);
7042 int flags = 0; 3017 int flags = 0;
@@ -7088,9 +3063,8 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
7088 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3063 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
7089} 3064}
7090 3065
7091void 3066void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7092ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, 3067 const struct ath9k_beacon_state *bs)
7093 const struct ath9k_beacon_state *bs)
7094{ 3068{
7095 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3069 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
7096 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3070 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
@@ -7153,1421 +3127,869 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7153 3127
7154} 3128}
7155 3129
7156bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) 3130/***************/
7157{ 3131/* Rate tables */
7158 if (entry < ah->ah_caps.keycache_size) { 3132/***************/
7159 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
7160 if (val & AR_KEYTABLE_VALID)
7161 return true;
7162 }
7163 return false;
7164}
7165 3133
7166bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) 3134static struct ath9k_rate_table ar5416_11a_table = {
7167{ 3135 8,
7168 u32 keyType; 3136 {0},
3137 {
3138 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
3139 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
3140 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
3141 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
3142 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
3143 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
3144 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
3145 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
3146 },
3147};
7169 3148
7170 if (entry >= ah->ah_caps.keycache_size) { 3149static struct ath9k_rate_table ar5416_11b_table = {
7171 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 3150 4,
7172 "%s: entry %u out of range\n", __func__, entry); 3151 {0},
7173 return false; 3152 {
7174 } 3153 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
7175 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3154 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
3155 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
3156 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
3157 },
3158};
7176 3159
7177 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 3160static struct ath9k_rate_table ar5416_11g_table = {
7178 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 3161 12,
7179 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 3162 {0},
7180 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 3163 {
7181 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 3164 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
7182 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 3165 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
7183 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 3166 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
7184 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 3167 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
7185 3168
7186 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 3169 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
7187 u16 micentry = entry + 64; 3170 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
3171 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
3172 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
3173 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
3174 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
3175 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
3176 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
3177 },
3178};
7188 3179
7189 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 3180static struct ath9k_rate_table ar5416_11ng_table = {
7190 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 3181 28,
7191 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); 3182 {0},
7192 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 3183 {
3184 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
3185 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
3186 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
3187 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
7193 3188
7194 } 3189 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
3190 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
3191 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
3192 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
3193 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
3194 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
3195 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
3196 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
3197 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
3198 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
3199 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
3200 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
3201 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
3202 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
3203 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
3204 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
3205 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
3206 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
3207 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
3208 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
3209 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
3210 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
3211 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
3212 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
3213 },
3214};
7195 3215
7196 return true; 3216static struct ath9k_rate_table ar5416_11na_table = {
7197} 3217 24,
3218 {0},
3219 {
3220 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
3221 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
3222 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
3223 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
3224 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
3225 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
3226 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
3227 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
3228 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
3229 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
3230 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
3231 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
3232 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
3233 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
3234 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
3235 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
3236 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
3237 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
3238 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
3239 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
3240 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
3241 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
3242 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
3243 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
3244 },
3245};
7198 3246
7199bool 3247static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
7200ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, 3248 struct ath9k_rate_table *rt)
7201 const u8 *mac)
7202{ 3249{
7203 u32 macHi, macLo; 3250 int i;
7204 3251
7205 if (entry >= ah->ah_caps.keycache_size) { 3252 if (rt->rateCodeToIndex[0] != 0)
7206 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 3253 return;
7207 "%s: entry %u out of range\n", __func__, entry);
7208 return false;
7209 }
7210 3254
7211 if (mac != NULL) { 3255 for (i = 0; i < 256; i++)
7212 macHi = (mac[5] << 8) | mac[4]; 3256 rt->rateCodeToIndex[i] = (u8) -1;
7213 macLo = (mac[3] << 24) | (mac[2] << 16)
7214 | (mac[1] << 8) | mac[0];
7215 macLo >>= 1;
7216 macLo |= (macHi & 1) << 31;
7217 macHi >>= 1;
7218 } else {
7219 macLo = macHi = 0;
7220 }
7221 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
7222 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
7223 3257
7224 return true; 3258 for (i = 0; i < rt->rateCount; i++) {
3259 u8 code = rt->info[i].rateCode;
3260 u8 cix = rt->info[i].controlRate;
3261
3262 rt->rateCodeToIndex[code] = i;
3263 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
3264
3265 rt->info[i].lpAckDuration =
3266 ath9k_hw_computetxtime(ah, rt,
3267 WLAN_CTRL_FRAME_SIZE,
3268 cix,
3269 false);
3270 rt->info[i].spAckDuration =
3271 ath9k_hw_computetxtime(ah, rt,
3272 WLAN_CTRL_FRAME_SIZE,
3273 cix,
3274 true);
3275 }
7225} 3276}
7226 3277
7227bool 3278const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
7228ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, 3279 u32 mode)
7229 const struct ath9k_keyval *k,
7230 const u8 *mac, int xorKey)
7231{ 3280{
7232 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3281 struct ath9k_rate_table *rt;
7233 u32 key0, key1, key2, key3, key4;
7234 u32 keyType;
7235 u32 xorMask = xorKey ?
7236 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
7237 | ATH9K_KEY_XOR) : 0;
7238 struct ath_hal_5416 *ahp = AH5416(ah);
7239 3282
7240 if (entry >= pCap->keycache_size) { 3283 switch (mode) {
7241 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 3284 case ATH9K_MODE_11A:
7242 "%s: entry %u out of range\n", __func__, entry); 3285 rt = &ar5416_11a_table;
7243 return false;
7244 }
7245 switch (k->kv_type) {
7246 case ATH9K_CIPHER_AES_OCB:
7247 keyType = AR_KEYTABLE_TYPE_AES;
7248 break; 3286 break;
7249 case ATH9K_CIPHER_AES_CCM: 3287 case ATH9K_MODE_11B:
7250 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 3288 rt = &ar5416_11b_table;
7251 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7252 "%s: AES-CCM not supported by "
7253 "mac rev 0x%x\n", __func__,
7254 ah->ah_macRev);
7255 return false;
7256 }
7257 keyType = AR_KEYTABLE_TYPE_CCM;
7258 break; 3289 break;
7259 case ATH9K_CIPHER_TKIP: 3290 case ATH9K_MODE_11G:
7260 keyType = AR_KEYTABLE_TYPE_TKIP; 3291 rt = &ar5416_11g_table;
7261 if (ATH9K_IS_MIC_ENABLED(ah)
7262 && entry + 64 >= pCap->keycache_size) {
7263 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7264 "%s: entry %u inappropriate for TKIP\n",
7265 __func__, entry);
7266 return false;
7267 }
7268 break; 3292 break;
7269 case ATH9K_CIPHER_WEP: 3293 case ATH9K_MODE_11NG_HT20:
7270 if (k->kv_len < LEN_WEP40) { 3294 case ATH9K_MODE_11NG_HT40PLUS:
7271 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 3295 case ATH9K_MODE_11NG_HT40MINUS:
7272 "%s: WEP key length %u too small\n", 3296 rt = &ar5416_11ng_table;
7273 __func__, k->kv_len);
7274 return false;
7275 }
7276 if (k->kv_len <= LEN_WEP40)
7277 keyType = AR_KEYTABLE_TYPE_40;
7278 else if (k->kv_len <= LEN_WEP104)
7279 keyType = AR_KEYTABLE_TYPE_104;
7280 else
7281 keyType = AR_KEYTABLE_TYPE_128;
7282 break; 3297 break;
7283 case ATH9K_CIPHER_CLR: 3298 case ATH9K_MODE_11NA_HT20:
7284 keyType = AR_KEYTABLE_TYPE_CLR; 3299 case ATH9K_MODE_11NA_HT40PLUS:
3300 case ATH9K_MODE_11NA_HT40MINUS:
3301 rt = &ar5416_11na_table;
7285 break; 3302 break;
7286 default: 3303 default:
7287 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 3304 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
7288 "%s: cipher %u not supported\n", __func__, 3305 __func__, mode);
7289 k->kv_type); 3306 return NULL;
7290 return false;
7291 } 3307 }
7292 3308
7293 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask; 3309 ath9k_hw_setup_rate_table(ah, rt);
7294 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
7295 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
7296 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
7297 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
7298 if (k->kv_len <= LEN_WEP104)
7299 key4 &= 0xff;
7300 3310
7301 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 3311 return rt;
7302 u16 micentry = entry + 64; 3312}
7303 3313
7304 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); 3314/*******************/
7305 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); 3315/* HW Capabilities */
7306 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 3316/*******************/
7307 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7308 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7309 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7310 (void) ath9k_hw_keysetmac(ah, entry, mac);
7311 3317
7312 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { 3318bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
7313 u32 mic0, mic1, mic2, mic3, mic4; 3319{
3320 struct ath_hal_5416 *ahp = AH5416(ah);
3321 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3322 u16 capField = 0, eeval;
7314 3323
7315 mic0 = get_unaligned_le32(k->kv_mic + 0); 3324 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
7316 mic2 = get_unaligned_le32(k->kv_mic + 4);
7317 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
7318 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
7319 mic4 = get_unaligned_le32(k->kv_txmic + 4);
7320 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7321 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
7322 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7323 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
7324 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
7325 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7326 AR_KEYTABLE_TYPE_CLR);
7327 3325
7328 } else { 3326 ah->ah_currentRD = eeval;
7329 u32 mic0, mic2;
7330 3327
7331 mic0 = get_unaligned_le32(k->kv_mic + 0); 3328 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
7332 mic2 = get_unaligned_le32(k->kv_mic + 4); 3329 ah->ah_currentRDExt = eeval;
7333 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7334 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7335 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7336 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7337 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
7338 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7339 AR_KEYTABLE_TYPE_CLR);
7340 }
7341 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
7342 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
7343 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7344 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7345 } else {
7346 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7347 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7348 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7349 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7350 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7351 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7352 3330
7353 (void) ath9k_hw_keysetmac(ah, entry, mac); 3331 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
7354 }
7355 3332
7356 if (ah->ah_curchan == NULL) 3333 if (ah->ah_opmode != ATH9K_M_HOSTAP &&
7357 return true; 3334 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3335 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3336 ah->ah_currentRD += 5;
3337 else if (ah->ah_currentRD == 0x41)
3338 ah->ah_currentRD = 0x43;
3339 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3340 "%s: regdomain mapped to 0x%x\n", __func__,
3341 ah->ah_currentRD);
3342 }
7358 3343
7359 return true; 3344 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
7360} 3345 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
7361 3346
7362bool 3347 if (eeval & AR5416_OPFLAGS_11A) {
7363ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel) 3348 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
7364{ 3349 if (ah->ah_config.ht_enable) {
7365 struct ath_hal_5416 *ahp = AH5416(ah); 3350 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
7366 u32 txcfg, curLevel, newLevel; 3351 set_bit(ATH9K_MODE_11NA_HT20,
7367 enum ath9k_int omask; 3352 pCap->wireless_modes);
3353 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3354 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3355 pCap->wireless_modes);
3356 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3357 pCap->wireless_modes);
3358 }
3359 }
3360 }
7368 3361
7369 if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD) 3362 if (eeval & AR5416_OPFLAGS_11G) {
7370 return false; 3363 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3364 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3365 if (ah->ah_config.ht_enable) {
3366 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3367 set_bit(ATH9K_MODE_11NG_HT20,
3368 pCap->wireless_modes);
3369 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3370 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3371 pCap->wireless_modes);
3372 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3373 pCap->wireless_modes);
3374 }
3375 }
3376 }
7371 3377
7372 omask = ath9k_hw_set_interrupts(ah, 3378 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
7373 ahp->ah_maskReg & ~ATH9K_INT_GLOBAL); 3379 if ((ah->ah_isPciExpress)
3380 || (eeval & AR5416_OPFLAGS_11A)) {
3381 pCap->rx_chainmask =
3382 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3383 } else {
3384 pCap->rx_chainmask =
3385 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3386 }
7374 3387
7375 txcfg = REG_READ(ah, AR_TXCFG); 3388 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
7376 curLevel = MS(txcfg, AR_FTRIG); 3389 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
7377 newLevel = curLevel;
7378 if (bIncTrigLevel) {
7379 if (curLevel < MAX_TX_FIFO_THRESHOLD)
7380 newLevel++;
7381 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
7382 newLevel--;
7383 if (newLevel != curLevel)
7384 REG_WRITE(ah, AR_TXCFG,
7385 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
7386 3390
7387 ath9k_hw_set_interrupts(ah, omask); 3391 pCap->low_2ghz_chan = 2312;
3392 pCap->high_2ghz_chan = 2732;
7388 3393
7389 ah->ah_txTrigLevel = newLevel; 3394 pCap->low_5ghz_chan = 4920;
3395 pCap->high_5ghz_chan = 6100;
7390 3396
7391 return newLevel != curLevel; 3397 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
7392} 3398 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3399 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
7393 3400
7394bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, 3401 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
7395 const struct ath9k_tx_queue_info *qinfo) 3402 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
7396{ 3403 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
7397 u32 cw;
7398 struct ath_hal_5416 *ahp = AH5416(ah);
7399 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7400 struct ath9k_tx_queue_info *qi;
7401 3404
7402 if (q >= pCap->total_queues) { 3405 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
7403 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7404 __func__, q);
7405 return false;
7406 }
7407 3406
7408 qi = &ahp->ah_txq[q]; 3407 if (ah->ah_config.ht_enable)
7409 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 3408 pCap->hw_caps |= ATH9K_HW_CAP_HT;
7410 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", 3409 else
7411 __func__); 3410 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
7412 return false;
7413 }
7414 3411
7415 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi); 3412 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3413 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3414 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3415 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
7416 3416
7417 qi->tqi_ver = qinfo->tqi_ver; 3417 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
7418 qi->tqi_subtype = qinfo->tqi_subtype; 3418 pCap->total_queues =
7419 qi->tqi_qflags = qinfo->tqi_qflags; 3419 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
7420 qi->tqi_priority = qinfo->tqi_priority;
7421 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
7422 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
7423 else
7424 qi->tqi_aifs = INIT_AIFS;
7425 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
7426 cw = min(qinfo->tqi_cwmin, 1024U);
7427 qi->tqi_cwmin = 1;
7428 while (qi->tqi_cwmin < cw)
7429 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
7430 } else
7431 qi->tqi_cwmin = qinfo->tqi_cwmin;
7432 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
7433 cw = min(qinfo->tqi_cwmax, 1024U);
7434 qi->tqi_cwmax = 1;
7435 while (qi->tqi_cwmax < cw)
7436 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
7437 } else
7438 qi->tqi_cwmax = INIT_CWMAX;
7439
7440 if (qinfo->tqi_shretry != 0)
7441 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
7442 else 3420 else
7443 qi->tqi_shretry = INIT_SH_RETRY; 3421 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
7444 if (qinfo->tqi_lgretry != 0) 3422
7445 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U); 3423 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3424 pCap->keycache_size =
3425 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
7446 else 3426 else
7447 qi->tqi_lgretry = INIT_LG_RETRY; 3427 pCap->keycache_size = AR_KEYTABLE_SIZE;
7448 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
7449 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
7450 qi->tqi_burstTime = qinfo->tqi_burstTime;
7451 qi->tqi_readyTime = qinfo->tqi_readyTime;
7452
7453 switch (qinfo->tqi_subtype) {
7454 case ATH9K_WME_UPSD:
7455 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
7456 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
7457 break;
7458 default:
7459 break;
7460 }
7461 return true;
7462}
7463 3428
7464bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, 3429 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
7465 struct ath9k_tx_queue_info *qinfo) 3430 pCap->num_mr_retries = 4;
7466{ 3431 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
7467 struct ath_hal_5416 *ahp = AH5416(ah);
7468 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7469 struct ath9k_tx_queue_info *qi;
7470 3432
7471 if (q >= pCap->total_queues) { 3433 if (AR_SREV_9280_10_OR_LATER(ah))
7472 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 3434 pCap->num_gpio_pins = AR928X_NUM_GPIO;
7473 __func__, q); 3435 else
7474 return false; 3436 pCap->num_gpio_pins = AR_NUM_GPIO;
7475 }
7476 3437
7477 qi = &ahp->ah_txq[q]; 3438 if (AR_SREV_9280_10_OR_LATER(ah)) {
7478 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 3439 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
7479 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", 3440 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
7480 __func__); 3441 } else {
7481 return false; 3442 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3443 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
7482 } 3444 }
7483 3445
7484 qinfo->tqi_qflags = qi->tqi_qflags; 3446 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
7485 qinfo->tqi_ver = qi->tqi_ver; 3447 pCap->hw_caps |= ATH9K_HW_CAP_CST;
7486 qinfo->tqi_subtype = qi->tqi_subtype; 3448 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
7487 qinfo->tqi_qflags = qi->tqi_qflags; 3449 } else {
7488 qinfo->tqi_priority = qi->tqi_priority; 3450 pCap->rts_aggr_limit = (8 * 1024);
7489 qinfo->tqi_aifs = qi->tqi_aifs; 3451 }
7490 qinfo->tqi_cwmin = qi->tqi_cwmin;
7491 qinfo->tqi_cwmax = qi->tqi_cwmax;
7492 qinfo->tqi_shretry = qi->tqi_shretry;
7493 qinfo->tqi_lgretry = qi->tqi_lgretry;
7494 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
7495 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
7496 qinfo->tqi_burstTime = qi->tqi_burstTime;
7497 qinfo->tqi_readyTime = qi->tqi_readyTime;
7498 3452
7499 return true; 3453 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
7500}
7501 3454
7502int 3455#ifdef CONFIG_RFKILL
7503ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, 3456 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
7504 const struct ath9k_tx_queue_info *qinfo) 3457 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
7505{ 3458 ah->ah_rfkill_gpio =
7506 struct ath_hal_5416 *ahp = AH5416(ah); 3459 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
7507 struct ath9k_tx_queue_info *qi; 3460 ah->ah_rfkill_polarity =
7508 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3461 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
7509 int q;
7510 3462
7511 switch (type) { 3463 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
7512 case ATH9K_TX_QUEUE_BEACON:
7513 q = pCap->total_queues - 1;
7514 break;
7515 case ATH9K_TX_QUEUE_CAB:
7516 q = pCap->total_queues - 2;
7517 break;
7518 case ATH9K_TX_QUEUE_PSPOLL:
7519 q = 1;
7520 break;
7521 case ATH9K_TX_QUEUE_UAPSD:
7522 q = pCap->total_queues - 3;
7523 break;
7524 case ATH9K_TX_QUEUE_DATA:
7525 for (q = 0; q < pCap->total_queues; q++)
7526 if (ahp->ah_txq[q].tqi_type ==
7527 ATH9K_TX_QUEUE_INACTIVE)
7528 break;
7529 if (q == pCap->total_queues) {
7530 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7531 "%s: no available tx queue\n", __func__);
7532 return -1;
7533 }
7534 break;
7535 default:
7536 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n",
7537 __func__, type);
7538 return -1;
7539 } 3464 }
3465#endif
7540 3466
7541 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); 3467 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3468 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3469 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3470 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3471 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3472 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3473 else
3474 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
7542 3475
7543 qi = &ahp->ah_txq[q]; 3476 if (AR_SREV_9280(ah))
7544 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 3477 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
7545 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 3478 else
7546 "%s: tx queue %u already active\n", __func__, q); 3479 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
7547 return -1; 3480
7548 } 3481 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
7549 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 3482 pCap->reg_cap =
7550 qi->tqi_type = type; 3483 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
7551 if (qinfo == NULL) { 3484 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
7552 qi->tqi_qflags = 3485 AR_EEPROM_EEREGCAP_EN_KK_U2 |
7553 TXQ_FLAG_TXOKINT_ENABLE 3486 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
7554 | TXQ_FLAG_TXERRINT_ENABLE
7555 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
7556 qi->tqi_aifs = INIT_AIFS;
7557 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
7558 qi->tqi_cwmax = INIT_CWMAX;
7559 qi->tqi_shretry = INIT_SH_RETRY;
7560 qi->tqi_lgretry = INIT_LG_RETRY;
7561 qi->tqi_physCompBuf = 0;
7562 } else { 3487 } else {
7563 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf; 3488 pCap->reg_cap =
7564 (void) ath9k_hw_set_txq_props(ah, q, qinfo); 3489 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3490 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
7565 } 3491 }
7566 3492
7567 return q; 3493 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
7568}
7569 3494
7570static void 3495 pCap->num_antcfg_5ghz =
7571ath9k_hw_set_txq_interrupts(struct ath_hal *ah, 3496 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ);
7572 struct ath9k_tx_queue_info *qi) 3497 pCap->num_antcfg_2ghz =
7573{ 3498 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ);
7574 struct ath_hal_5416 *ahp = AH5416(ah);
7575 3499
7576 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 3500 return true;
7577 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
7578 __func__, ahp->ah_txOkInterruptMask,
7579 ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
7580 ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask);
7581
7582 REG_WRITE(ah, AR_IMR_S0,
7583 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
7584 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC));
7585 REG_WRITE(ah, AR_IMR_S1,
7586 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
7587 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL));
7588 REG_RMW_FIELD(ah, AR_IMR_S2,
7589 AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
7590} 3501}
7591 3502
7592bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) 3503bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3504 u32 capability, u32 *result)
7593{ 3505{
7594 struct ath_hal_5416 *ahp = AH5416(ah); 3506 struct ath_hal_5416 *ahp = AH5416(ah);
7595 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3507 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7596 struct ath9k_tx_queue_info *qi;
7597 3508
7598 if (q >= pCap->total_queues) { 3509 switch (type) {
7599 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 3510 case ATH9K_CAP_CIPHER:
7600 __func__, q); 3511 switch (capability) {
3512 case ATH9K_CIPHER_AES_CCM:
3513 case ATH9K_CIPHER_AES_OCB:
3514 case ATH9K_CIPHER_TKIP:
3515 case ATH9K_CIPHER_WEP:
3516 case ATH9K_CIPHER_MIC:
3517 case ATH9K_CIPHER_CLR:
3518 return true;
3519 default:
3520 return false;
3521 }
3522 case ATH9K_CAP_TKIP_MIC:
3523 switch (capability) {
3524 case 0:
3525 return true;
3526 case 1:
3527 return (ahp->ah_staId1Defaults &
3528 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3529 false;
3530 }
3531 case ATH9K_CAP_TKIP_SPLIT:
3532 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3533 false : true;
3534 case ATH9K_CAP_WME_TKIPMIC:
3535 return 0;
3536 case ATH9K_CAP_PHYCOUNTERS:
3537 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3538 case ATH9K_CAP_DIVERSITY:
3539 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3540 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3541 true : false;
3542 case ATH9K_CAP_PHYDIAG:
3543 return true;
3544 case ATH9K_CAP_MCAST_KEYSRCH:
3545 switch (capability) {
3546 case 0:
3547 return true;
3548 case 1:
3549 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3550 return false;
3551 } else {
3552 return (ahp->ah_staId1Defaults &
3553 AR_STA_ID1_MCAST_KSRCH) ? true :
3554 false;
3555 }
3556 }
7601 return false; 3557 return false;
7602 } 3558 case ATH9K_CAP_TSF_ADJUST:
7603 qi = &ahp->ah_txq[q]; 3559 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
7604 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 3560 true : false;
7605 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", 3561 case ATH9K_CAP_RFSILENT:
7606 __func__, q); 3562 if (capability == 3)
3563 return false;
3564 case ATH9K_CAP_ANT_CFG_2GHZ:
3565 *result = pCap->num_antcfg_2ghz;
3566 return true;
3567 case ATH9K_CAP_ANT_CFG_5GHZ:
3568 *result = pCap->num_antcfg_5ghz;
3569 return true;
3570 case ATH9K_CAP_TXPOW:
3571 switch (capability) {
3572 case 0:
3573 return 0;
3574 case 1:
3575 *result = ah->ah_powerLimit;
3576 return 0;
3577 case 2:
3578 *result = ah->ah_maxPowerLevel;
3579 return 0;
3580 case 3:
3581 *result = ah->ah_tpScale;
3582 return 0;
3583 }
3584 return false;
3585 default:
7607 return false; 3586 return false;
7608 } 3587 }
7609
7610 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n",
7611 __func__, q);
7612
7613 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
7614 ahp->ah_txOkInterruptMask &= ~(1 << q);
7615 ahp->ah_txErrInterruptMask &= ~(1 << q);
7616 ahp->ah_txDescInterruptMask &= ~(1 << q);
7617 ahp->ah_txEolInterruptMask &= ~(1 << q);
7618 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7619 ath9k_hw_set_txq_interrupts(ah, qi);
7620
7621 return true;
7622} 3588}
7623 3589
7624bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) 3590bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3591 u32 capability, u32 setting, int *status)
7625{ 3592{
7626 struct ath_hal_5416 *ahp = AH5416(ah); 3593 struct ath_hal_5416 *ahp = AH5416(ah);
7627 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3594 u32 v;
7628 struct ath9k_channel *chan = ah->ah_curchan;
7629 struct ath9k_tx_queue_info *qi;
7630 u32 cwMin, chanCwMin, value;
7631 3595
7632 if (q >= pCap->total_queues) { 3596 switch (type) {
7633 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 3597 case ATH9K_CAP_TKIP_MIC:
7634 __func__, q); 3598 if (setting)
7635 return false; 3599 ahp->ah_staId1Defaults |=
7636 } 3600 AR_STA_ID1_CRPT_MIC_ENABLE;
7637 qi = &ahp->ah_txq[q]; 3601 else
7638 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 3602 ahp->ah_staId1Defaults &=
7639 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", 3603 ~AR_STA_ID1_CRPT_MIC_ENABLE;
7640 __func__, q);
7641 return true; 3604 return true;
7642 } 3605 case ATH9K_CAP_DIVERSITY:
7643 3606 v = REG_READ(ah, AR_PHY_CCK_DETECT);
7644 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q); 3607 if (setting)
7645 3608 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
7646 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
7647 if (chan && IS_CHAN_B(chan))
7648 chanCwMin = INIT_CWMIN_11B;
7649 else 3609 else
7650 chanCwMin = INIT_CWMIN; 3610 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
7651 3611 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
7652 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1); 3612 return true;
7653 } else 3613 case ATH9K_CAP_MCAST_KEYSRCH:
7654 cwMin = qi->tqi_cwmin; 3614 if (setting)
7655 3615 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
7656 REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN) 3616 else
7657 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) 3617 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
7658 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 3618 return true;
7659 3619 case ATH9K_CAP_TSF_ADJUST:
7660 REG_WRITE(ah, AR_DRETRY_LIMIT(q), 3620 if (setting)
7661 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) 3621 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
7662 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) 3622 else
7663 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); 3623 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
7664 3624 return true;
7665 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
7666 REG_WRITE(ah, AR_DMISC(q),
7667 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
7668
7669 if (qi->tqi_cbrPeriod) {
7670 REG_WRITE(ah, AR_QCBRCFG(q),
7671 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL)
7672 | SM(qi->tqi_cbrOverflowLimit,
7673 AR_Q_CBRCFG_OVF_THRESH));
7674 REG_WRITE(ah, AR_QMISC(q),
7675 REG_READ(ah,
7676 AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | (qi->
7677 tqi_cbrOverflowLimit
7678 ?
7679 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
7680 :
7681 0));
7682 }
7683 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
7684 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7685 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
7686 AR_Q_RDYTIMECFG_EN);
7687 }
7688
7689 REG_WRITE(ah, AR_DCHNTIME(q),
7690 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
7691 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
7692
7693 if (qi->tqi_burstTime
7694 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
7695 REG_WRITE(ah, AR_QMISC(q),
7696 REG_READ(ah,
7697 AR_QMISC(q)) |
7698 AR_Q_MISC_RDYTIME_EXP_POLICY);
7699
7700 }
7701
7702 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
7703 REG_WRITE(ah, AR_DMISC(q),
7704 REG_READ(ah, AR_DMISC(q)) |
7705 AR_D_MISC_POST_FR_BKOFF_DIS);
7706 }
7707 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
7708 REG_WRITE(ah, AR_DMISC(q),
7709 REG_READ(ah, AR_DMISC(q)) |
7710 AR_D_MISC_FRAG_BKOFF_EN);
7711 }
7712 switch (qi->tqi_type) {
7713 case ATH9K_TX_QUEUE_BEACON:
7714 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7715 | AR_Q_MISC_FSP_DBA_GATED
7716 | AR_Q_MISC_BEACON_USE
7717 | AR_Q_MISC_CBR_INCR_DIS1);
7718
7719 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7720 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7721 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
7722 | AR_D_MISC_BEACON_USE
7723 | AR_D_MISC_POST_FR_BKOFF_DIS);
7724 break;
7725 case ATH9K_TX_QUEUE_CAB:
7726 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7727 | AR_Q_MISC_FSP_DBA_GATED
7728 | AR_Q_MISC_CBR_INCR_DIS1
7729 | AR_Q_MISC_CBR_INCR_DIS0);
7730 value = (qi->tqi_readyTime
7731 - (ah->ah_config.sw_beacon_response_time -
7732 ah->ah_config.dma_beacon_response_time)
7733 -
7734 ah->ah_config.additional_swba_backoff) *
7735 1024;
7736 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7737 value | AR_Q_RDYTIMECFG_EN);
7738 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7739 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7740 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7741 break;
7742 case ATH9K_TX_QUEUE_PSPOLL:
7743 REG_WRITE(ah, AR_QMISC(q),
7744 REG_READ(ah,
7745 AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
7746 break;
7747 case ATH9K_TX_QUEUE_UAPSD:
7748 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7749 | AR_D_MISC_POST_FR_BKOFF_DIS);
7750 break;
7751 default: 3625 default:
7752 break; 3626 return false;
7753 }
7754
7755 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
7756 REG_WRITE(ah, AR_DMISC(q),
7757 REG_READ(ah, AR_DMISC(q)) |
7758 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
7759 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
7760 AR_D_MISC_POST_FR_BKOFF_DIS);
7761 } 3627 }
7762
7763 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
7764 ahp->ah_txOkInterruptMask |= 1 << q;
7765 else
7766 ahp->ah_txOkInterruptMask &= ~(1 << q);
7767 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
7768 ahp->ah_txErrInterruptMask |= 1 << q;
7769 else
7770 ahp->ah_txErrInterruptMask &= ~(1 << q);
7771 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
7772 ahp->ah_txDescInterruptMask |= 1 << q;
7773 else
7774 ahp->ah_txDescInterruptMask &= ~(1 << q);
7775 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
7776 ahp->ah_txEolInterruptMask |= 1 << q;
7777 else
7778 ahp->ah_txEolInterruptMask &= ~(1 << q);
7779 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
7780 ahp->ah_txUrnInterruptMask |= 1 << q;
7781 else
7782 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7783 ath9k_hw_set_txq_interrupts(ah, qi);
7784
7785 return true;
7786} 3628}
7787 3629
7788void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs) 3630/****************************/
7789{ 3631/* GPIO / RFKILL / Antennae */
7790 struct ath_hal_5416 *ahp = AH5416(ah); 3632/****************************/
7791 *txqs &= ahp->ah_intrTxqs;
7792 ahp->ah_intrTxqs &= ~(*txqs);
7793}
7794
7795bool
7796ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
7797 u32 segLen, bool firstSeg,
7798 bool lastSeg, const struct ath_desc *ds0)
7799{
7800 struct ar5416_desc *ads = AR5416DESC(ds);
7801
7802 if (firstSeg) {
7803 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
7804 } else if (lastSeg) {
7805 ads->ds_ctl0 = 0;
7806 ads->ds_ctl1 = segLen;
7807 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
7808 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
7809 } else {
7810 ads->ds_ctl0 = 0;
7811 ads->ds_ctl1 = segLen | AR_TxMore;
7812 ads->ds_ctl2 = 0;
7813 ads->ds_ctl3 = 0;
7814 }
7815 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7816 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7817 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7818 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7819 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7820 return true;
7821}
7822 3633
7823void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds) 3634static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3635 u32 gpio, u32 type)
7824{ 3636{
7825 struct ar5416_desc *ads = AR5416DESC(ds); 3637 int addr;
3638 u32 gpio_shift, tmp;
7826 3639
7827 ads->ds_txstatus0 = ads->ds_txstatus1 = 0; 3640 if (gpio > 11)
7828 ads->ds_txstatus2 = ads->ds_txstatus3 = 0; 3641 addr = AR_GPIO_OUTPUT_MUX3;
7829 ads->ds_txstatus4 = ads->ds_txstatus5 = 0; 3642 else if (gpio > 5)
7830 ads->ds_txstatus6 = ads->ds_txstatus7 = 0; 3643 addr = AR_GPIO_OUTPUT_MUX2;
7831 ads->ds_txstatus8 = ads->ds_txstatus9 = 0; 3644 else
7832} 3645 addr = AR_GPIO_OUTPUT_MUX1;
7833 3646
7834int 3647 gpio_shift = (gpio % 6) * 5;
7835ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
7836{
7837 struct ar5416_desc *ads = AR5416DESC(ds);
7838
7839 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
7840 return -EINPROGRESS;
7841
7842 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
7843 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
7844 ds->ds_txstat.ts_status = 0;
7845 ds->ds_txstat.ts_flags = 0;
7846
7847 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
7848 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
7849 if (ads->ds_txstatus1 & AR_Filtered)
7850 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
7851 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
7852 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
7853 if (ads->ds_txstatus9 & AR_TxOpExceeded)
7854 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
7855 if (ads->ds_txstatus1 & AR_TxTimerExpired)
7856 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
7857
7858 if (ads->ds_txstatus1 & AR_DescCfgErr)
7859 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
7860 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
7861 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
7862 ath9k_hw_updatetxtriglevel(ah, true);
7863 }
7864 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
7865 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
7866 ath9k_hw_updatetxtriglevel(ah, true);
7867 }
7868 if (ads->ds_txstatus0 & AR_TxBaStatus) {
7869 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
7870 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
7871 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
7872 }
7873 3648
7874 ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx); 3649 if (AR_SREV_9280_20_OR_LATER(ah)
7875 switch (ds->ds_txstat.ts_rateindex) { 3650 || (addr != AR_GPIO_OUTPUT_MUX1)) {
7876 case 0: 3651 REG_RMW(ah, addr, (type << gpio_shift),
7877 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0); 3652 (0x1f << gpio_shift));
7878 break; 3653 } else {
7879 case 1: 3654 tmp = REG_READ(ah, addr);
7880 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1); 3655 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
7881 break; 3656 tmp &= ~(0x1f << gpio_shift);
7882 case 2: 3657 tmp |= (type << gpio_shift);
7883 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2); 3658 REG_WRITE(ah, addr, tmp);
7884 break;
7885 case 3:
7886 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
7887 break;
7888 } 3659 }
7889
7890 ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
7891 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
7892 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
7893 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
7894 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
7895 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
7896 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
7897 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
7898 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
7899 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
7900 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
7901 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
7902 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
7903 ds->ds_txstat.ts_antenna = 1;
7904
7905 return 0;
7906} 3660}
7907 3661
7908void 3662void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
7909ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
7910 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
7911 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
7912{ 3663{
7913 struct ar5416_desc *ads = AR5416DESC(ds); 3664 u32 gpio_shift;
7914 struct ath_hal_5416 *ahp = AH5416(ah);
7915
7916 txPower += ahp->ah_txPowerIndexOffset;
7917 if (txPower > 63)
7918 txPower = 63;
7919
7920 ads->ds_ctl0 = (pktLen & AR_FrameLen)
7921 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
7922 | SM(txPower, AR_XmitPower)
7923 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
7924 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
7925 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
7926 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
7927
7928 ads->ds_ctl1 =
7929 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
7930 | SM(type, AR_FrameType)
7931 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
7932 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
7933 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
7934 3665
7935 ads->ds_ctl6 = SM(keyType, AR_EncrType); 3666 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
7936 3667
7937 if (AR_SREV_9285(ah)) { 3668 gpio_shift = gpio << 1;
7938 3669
7939 ads->ds_ctl8 = 0; 3670 REG_RMW(ah,
7940 ads->ds_ctl9 = 0; 3671 AR_GPIO_OE_OUT,
7941 ads->ds_ctl10 = 0; 3672 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
7942 ads->ds_ctl11 = 0; 3673 (AR_GPIO_OE_OUT_DRV << gpio_shift));
7943 }
7944} 3674}
7945 3675
7946void 3676u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
7947ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
7948 struct ath_desc *lastds,
7949 u32 durUpdateEn, u32 rtsctsRate,
7950 u32 rtsctsDuration,
7951 struct ath9k_11n_rate_series series[],
7952 u32 nseries, u32 flags)
7953{ 3677{
7954 struct ar5416_desc *ads = AR5416DESC(ds); 3678 if (gpio >= ah->ah_caps.num_gpio_pins)
7955 struct ar5416_desc *last_ads = AR5416DESC(lastds); 3679 return 0xffffffff;
7956 u32 ds_ctl0;
7957
7958 (void) nseries;
7959 (void) rtsctsDuration;
7960
7961 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
7962 ds_ctl0 = ads->ds_ctl0;
7963
7964 if (flags & ATH9K_TXDESC_RTSENA) {
7965 ds_ctl0 &= ~AR_CTSEnable;
7966 ds_ctl0 |= AR_RTSEnable;
7967 } else {
7968 ds_ctl0 &= ~AR_RTSEnable;
7969 ds_ctl0 |= AR_CTSEnable;
7970 }
7971 3680
7972 ads->ds_ctl0 = ds_ctl0; 3681 if (AR_SREV_9280_10_OR_LATER(ah)) {
3682 return (MS
3683 (REG_READ(ah, AR_GPIO_IN_OUT),
3684 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
7973 } else { 3685 } else {
7974 ads->ds_ctl0 = 3686 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
7975 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); 3687 AR_GPIO_BIT(gpio)) != 0;
7976 } 3688 }
7977
7978 ads->ds_ctl2 = set11nTries(series, 0)
7979 | set11nTries(series, 1)
7980 | set11nTries(series, 2)
7981 | set11nTries(series, 3)
7982 | (durUpdateEn ? AR_DurUpdateEna : 0)
7983 | SM(0, AR_BurstDur);
7984
7985 ads->ds_ctl3 = set11nRate(series, 0)
7986 | set11nRate(series, 1)
7987 | set11nRate(series, 2)
7988 | set11nRate(series, 3);
7989
7990 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
7991 | set11nPktDurRTSCTS(series, 1);
7992
7993 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
7994 | set11nPktDurRTSCTS(series, 3);
7995
7996 ads->ds_ctl7 = set11nRateFlags(series, 0)
7997 | set11nRateFlags(series, 1)
7998 | set11nRateFlags(series, 2)
7999 | set11nRateFlags(series, 3)
8000 | SM(rtsctsRate, AR_RTSCTSRate);
8001 last_ads->ds_ctl2 = ads->ds_ctl2;
8002 last_ads->ds_ctl3 = ads->ds_ctl3;
8003} 3689}
8004 3690
8005void 3691void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
8006ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 3692 u32 ah_signal_type)
8007 u32 aggrLen)
8008{ 3693{
8009 struct ar5416_desc *ads = AR5416DESC(ds); 3694 u32 gpio_shift;
8010
8011 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8012
8013 ads->ds_ctl6 &= ~AR_AggrLen;
8014 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
8015}
8016 3695
8017void 3696 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
8018ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
8019 u32 numDelims)
8020{
8021 struct ar5416_desc *ads = AR5416DESC(ds);
8022 unsigned int ctl6;
8023 3697
8024 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); 3698 gpio_shift = 2 * gpio;
8025 3699
8026 ctl6 = ads->ds_ctl6; 3700 REG_RMW(ah,
8027 ctl6 &= ~AR_PadDelim; 3701 AR_GPIO_OE_OUT,
8028 ctl6 |= SM(numDelims, AR_PadDelim); 3702 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
8029 ads->ds_ctl6 = ctl6; 3703 (AR_GPIO_OE_OUT_DRV << gpio_shift));
8030} 3704}
8031 3705
8032void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) 3706void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
8033{ 3707{
8034 struct ar5416_desc *ads = AR5416DESC(ds); 3708 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
8035 3709 AR_GPIO_BIT(gpio));
8036 ads->ds_ctl1 |= AR_IsAggr;
8037 ads->ds_ctl1 &= ~AR_MoreAggr;
8038 ads->ds_ctl6 &= ~AR_PadDelim;
8039} 3710}
8040 3711
8041void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds) 3712#ifdef CONFIG_RFKILL
3713void ath9k_enable_rfkill(struct ath_hal *ah)
8042{ 3714{
8043 struct ar5416_desc *ads = AR5416DESC(ds); 3715 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3716 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
8044 3717
8045 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); 3718 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3719 AR_GPIO_INPUT_MUX2_RFSILENT);
3720
3721 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3722 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
8046} 3723}
3724#endif
8047 3725
8048void 3726int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
8049ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
8050 u32 burstDuration)
8051{ 3727{
8052 struct ar5416_desc *ads = AR5416DESC(ds); 3728 struct ath9k_channel *chan = ah->ah_curchan;
3729 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3730 u16 ant_config;
3731 u32 halNumAntConfig;
8053 3732
8054 ads->ds_ctl2 &= ~AR_BurstDur; 3733 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
8055 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); 3734 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
8056}
8057 3735
8058void 3736 if (cfg < halNumAntConfig) {
8059ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, 3737 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
8060 u32 vmf) 3738 cfg, &ant_config)) {
8061{ 3739 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
8062 struct ar5416_desc *ads = AR5416DESC(ds); 3740 return 0;
3741 }
3742 }
8063 3743
8064 if (vmf) 3744 return -EINVAL;
8065 ads->ds_ctl0 |= AR_VirtMoreFrag;
8066 else
8067 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
8068} 3745}
8069 3746
8070void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp) 3747u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
8071{ 3748{
8072 REG_WRITE(ah, AR_RXDP, rxdp); 3749 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
8073} 3750}
8074 3751
8075void ath9k_hw_rxena(struct ath_hal *ah) 3752void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
8076{ 3753{
8077 REG_WRITE(ah, AR_CR, AR_CR_RXE); 3754 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
8078} 3755}
8079 3756
8080bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) 3757bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3758 enum ath9k_ant_setting settings,
3759 struct ath9k_channel *chan,
3760 u8 *tx_chainmask,
3761 u8 *rx_chainmask,
3762 u8 *antenna_cfgd)
8081{ 3763{
8082 if (set) { 3764 struct ath_hal_5416 *ahp = AH5416(ah);
8083 3765 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
8084 REG_SET_BIT(ah, AR_DIAG_SW,
8085 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8086
8087 if (!ath9k_hw_wait
8088 (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
8089 u32 reg;
8090 3766
8091 REG_CLR_BIT(ah, AR_DIAG_SW, 3767 if (AR_SREV_9280(ah)) {
8092 (AR_DIAG_RX_DIS | 3768 if (!tx_chainmask_cfg) {
8093 AR_DIAG_RX_ABORT));
8094 3769
8095 reg = REG_READ(ah, AR_OBS_BUS_1); 3770 tx_chainmask_cfg = *tx_chainmask;
8096 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 3771 rx_chainmask_cfg = *rx_chainmask;
8097 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n", 3772 }
8098 __func__, reg);
8099 3773
8100 return false; 3774 switch (settings) {
3775 case ATH9K_ANT_FIXED_A:
3776 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3777 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3778 *antenna_cfgd = true;
3779 break;
3780 case ATH9K_ANT_FIXED_B:
3781 if (ah->ah_caps.tx_chainmask >
3782 ATH9K_ANTENNA1_CHAINMASK) {
3783 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3784 }
3785 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3786 *antenna_cfgd = true;
3787 break;
3788 case ATH9K_ANT_VARIABLE:
3789 *tx_chainmask = tx_chainmask_cfg;
3790 *rx_chainmask = rx_chainmask_cfg;
3791 *antenna_cfgd = true;
3792 break;
3793 default:
3794 break;
8101 } 3795 }
8102 } else { 3796 } else {
8103 REG_CLR_BIT(ah, AR_DIAG_SW, 3797 ahp->ah_diversityControl = settings;
8104 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8105 } 3798 }
8106 3799
8107 return true; 3800 return true;
8108} 3801}
8109 3802
8110void 3803/*********************/
8111ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, 3804/* General Operation */
8112 u32 filter1) 3805/*********************/
8113{
8114 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8115 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8116}
8117 3806
8118bool 3807u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
8119ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
8120 u32 size, u32 flags)
8121{ 3808{
8122 struct ar5416_desc *ads = AR5416DESC(ds); 3809 u32 bits = REG_READ(ah, AR_RX_FILTER);
8123 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3810 u32 phybits = REG_READ(ah, AR_PHY_ERR);
8124 3811
8125 ads->ds_ctl1 = size & AR_BufLen; 3812 if (phybits & AR_PHY_ERR_RADAR)
8126 if (flags & ATH9K_RXDESC_INTREQ) 3813 bits |= ATH9K_RX_FILTER_PHYRADAR;
8127 ads->ds_ctl1 |= AR_RxIntrReq; 3814 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3815 bits |= ATH9K_RX_FILTER_PHYERR;
8128 3816
8129 ads->ds_rxstatus8 &= ~AR_RxDone; 3817 return bits;
8130 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
8131 memset(&(ads->u), 0, sizeof(ads->u));
8132 return true;
8133} 3818}
8134 3819
8135int 3820void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
8136ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
8137 u32 pa, struct ath_desc *nds, u64 tsf)
8138{ 3821{
8139 struct ar5416_desc ads; 3822 u32 phybits;
8140 struct ar5416_desc *adsp = AR5416DESC(ds);
8141
8142 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
8143 return -EINPROGRESS;
8144
8145 ads.u.rx = adsp->u.rx;
8146
8147 ds->ds_rxstat.rs_status = 0;
8148 ds->ds_rxstat.rs_flags = 0;
8149 3823
8150 ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen; 3824 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
8151 ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp; 3825 phybits = 0;
3826 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3827 phybits |= AR_PHY_ERR_RADAR;
3828 if (bits & ATH9K_RX_FILTER_PHYERR)
3829 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3830 REG_WRITE(ah, AR_PHY_ERR, phybits);
8152 3831
8153 ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); 3832 if (phybits)
8154 ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00); 3833 REG_WRITE(ah, AR_RXCFG,
8155 ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01); 3834 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
8156 ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
8157 ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
8158 ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
8159 ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
8160 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8161 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
8162 else 3835 else
8163 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID; 3836 REG_WRITE(ah, AR_RXCFG,
8164 3837 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
8165 ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
8166 ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
8167
8168 ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
8169 ds->ds_rxstat.rs_moreaggr =
8170 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8171 ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
8172 ds->ds_rxstat.rs_flags =
8173 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
8174 ds->ds_rxstat.rs_flags |=
8175 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
8176
8177 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8178 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
8179 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8180 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
8181 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8182 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
8183
8184 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
8185
8186 if (ads.ds_rxstatus8 & AR_CRCErr)
8187 ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
8188 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8189 u32 phyerr;
8190
8191 ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
8192 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8193 ds->ds_rxstat.rs_phyerr = phyerr;
8194 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8195 ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
8196 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8197 ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
8198 }
8199
8200 return 0;
8201} 3838}
8202 3839
8203static void ath9k_hw_setup_rate_table(struct ath_hal *ah, 3840bool ath9k_hw_phy_disable(struct ath_hal *ah)
8204 struct ath9k_rate_table *rt)
8205{ 3841{
8206 int i; 3842 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
8207
8208 if (rt->rateCodeToIndex[0] != 0)
8209 return;
8210 for (i = 0; i < 256; i++)
8211 rt->rateCodeToIndex[i] = (u8) -1;
8212 for (i = 0; i < rt->rateCount; i++) {
8213 u8 code = rt->info[i].rateCode;
8214 u8 cix = rt->info[i].controlRate;
8215
8216 rt->rateCodeToIndex[code] = i;
8217 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
8218
8219 rt->info[i].lpAckDuration =
8220 ath9k_hw_computetxtime(ah, rt,
8221 WLAN_CTRL_FRAME_SIZE,
8222 cix,
8223 false);
8224 rt->info[i].spAckDuration =
8225 ath9k_hw_computetxtime(ah, rt,
8226 WLAN_CTRL_FRAME_SIZE,
8227 cix,
8228 true);
8229 }
8230} 3843}
8231 3844
8232const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah, 3845bool ath9k_hw_disable(struct ath_hal *ah)
8233 u32 mode)
8234{ 3846{
8235 struct ath9k_rate_table *rt; 3847 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
8236 switch (mode) { 3848 return false;
8237 case ATH9K_MODE_11A:
8238 rt = &ar5416_11a_table;
8239 break;
8240 case ATH9K_MODE_11B:
8241 rt = &ar5416_11b_table;
8242 break;
8243 case ATH9K_MODE_11G:
8244 rt = &ar5416_11g_table;
8245 break;
8246 case ATH9K_MODE_11NG_HT20:
8247 case ATH9K_MODE_11NG_HT40PLUS:
8248 case ATH9K_MODE_11NG_HT40MINUS:
8249 rt = &ar5416_11ng_table;
8250 break;
8251 case ATH9K_MODE_11NA_HT20:
8252 case ATH9K_MODE_11NA_HT40PLUS:
8253 case ATH9K_MODE_11NA_HT40MINUS:
8254 rt = &ar5416_11na_table;
8255 break;
8256 default:
8257 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
8258 __func__, mode);
8259 return NULL;
8260 }
8261 ath9k_hw_setup_rate_table(ah, rt);
8262 return rt;
8263}
8264 3849
8265static const char *ath9k_hw_devname(u16 devid) 3850 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
8266{
8267 switch (devid) {
8268 case AR5416_DEVID_PCI:
8269 case AR5416_DEVID_PCIE:
8270 return "Atheros 5416";
8271 case AR9160_DEVID_PCI:
8272 return "Atheros 9160";
8273 case AR9280_DEVID_PCI:
8274 case AR9280_DEVID_PCIE:
8275 return "Atheros 9280";
8276 }
8277 return NULL;
8278} 3851}
8279 3852
8280const char *ath9k_hw_probe(u16 vendorid, u16 devid) 3853bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
8281{ 3854{
8282 return vendorid == ATHEROS_VENDOR_ID ? 3855 struct ath9k_channel *chan = ah->ah_curchan;
8283 ath9k_hw_devname(devid) : NULL;
8284}
8285 3856
8286struct ath_hal *ath9k_hw_attach(u16 devid, 3857 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
8287 struct ath_softc *sc,
8288 void __iomem *mem,
8289 int *error)
8290{
8291 struct ath_hal *ah = NULL;
8292 3858
8293 switch (devid) { 3859 if (ath9k_hw_set_txpower(ah, chan,
8294 case AR5416_DEVID_PCI: 3860 ath9k_regd_get_ctl(ah, chan),
8295 case AR5416_DEVID_PCIE: 3861 ath9k_regd_get_antenna_allowed(ah, chan),
8296 case AR9160_DEVID_PCI: 3862 chan->maxRegTxPower * 2,
8297 case AR9280_DEVID_PCI: 3863 min((u32) MAX_RATE_POWER,
8298 case AR9280_DEVID_PCIE: 3864 (u32) ah->ah_powerLimit)) != 0)
8299 ah = ath9k_hw_do_attach(devid, sc, mem, error); 3865 return false;
8300 break;
8301 default:
8302 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
8303 "devid=0x%x not supported.\n", devid);
8304 ah = NULL;
8305 *error = -ENXIO;
8306 break;
8307 }
8308 3866
8309 return ah; 3867 return true;
8310} 3868}
8311 3869
8312u16 3870void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
8313ath9k_hw_computetxtime(struct ath_hal *ah,
8314 const struct ath9k_rate_table *rates,
8315 u32 frameLen, u16 rateix,
8316 bool shortPreamble)
8317{ 3871{
8318 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 3872 struct ath_hal_5416 *ahp = AH5416(ah);
8319 u32 kbps;
8320
8321 kbps = rates->info[rateix].rateKbps;
8322
8323 if (kbps == 0)
8324 return 0;
8325 switch (rates->info[rateix].phy) {
8326
8327 case PHY_CCK:
8328 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
8329 if (shortPreamble && rates->info[rateix].shortPreamble)
8330 phyTime >>= 1;
8331 numBits = frameLen << 3;
8332 txTime = CCK_SIFS_TIME + phyTime
8333 + ((numBits * 1000) / kbps);
8334 break;
8335 case PHY_OFDM:
8336 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
8337 bitsPerSymbol =
8338 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
8339
8340 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8341 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8342 txTime = OFDM_SIFS_TIME_QUARTER
8343 + OFDM_PREAMBLE_TIME_QUARTER
8344 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
8345 } else if (ah->ah_curchan &&
8346 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
8347 bitsPerSymbol =
8348 (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
8349
8350 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8351 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8352 txTime = OFDM_SIFS_TIME_HALF +
8353 OFDM_PREAMBLE_TIME_HALF
8354 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
8355 } else {
8356 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
8357
8358 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8359 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8360 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
8361 + (numSymbols * OFDM_SYMBOL_TIME);
8362 }
8363 break;
8364 3873
8365 default: 3874 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
8366 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
8367 "%s: unknown phy %u (rate ix %u)\n", __func__,
8368 rates->info[rateix].phy, rateix);
8369 txTime = 0;
8370 break;
8371 }
8372 return txTime;
8373} 3875}
8374 3876
8375u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags) 3877bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
8376{ 3878{
8377 if (flags & CHANNEL_2GHZ) { 3879 struct ath_hal_5416 *ahp = AH5416(ah);
8378 if (freq == 2484)
8379 return 14;
8380 if (freq < 2484)
8381 return (freq - 2407) / 5;
8382 else
8383 return 15 + ((freq - 2512) / 20);
8384 } else if (flags & CHANNEL_5GHZ) {
8385 if (ath9k_regd_is_public_safety_sku(ah) &&
8386 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8387 return ((freq * 10) +
8388 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
8389 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
8390 return (freq - 4000) / 5;
8391 } else {
8392 return (freq - 5000) / 5;
8393 }
8394 } else {
8395 if (freq == 2484)
8396 return 14;
8397 if (freq < 2484)
8398 return (freq - 2407) / 5;
8399 if (freq < 5000) {
8400 if (ath9k_regd_is_public_safety_sku(ah)
8401 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8402 return ((freq * 10) +
8403 (((freq % 5) ==
8404 2) ? 5 : 0) - 49400) / 5;
8405 } else if (freq > 4900) {
8406 return (freq - 4000) / 5;
8407 } else {
8408 return 15 + ((freq - 2512) / 20);
8409 }
8410 }
8411 return (freq - 5000) / 5;
8412 }
8413}
8414 3880
8415/* We can tune this as we go by monitoring really low values */ 3881 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
8416#define ATH9K_NF_TOO_LOW -60
8417 3882
8418/* AR5416 may return very high value (like -31 dBm), in those cases the nf
8419 * is incorrect and we should use the static NF value. Later we can try to
8420 * find out why they are reporting these values */
8421static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
8422{
8423 if (nf > ATH9K_NF_TOO_LOW) {
8424 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
8425 "%s: noise floor value detected (%d) is "
8426 "lower than what we think is a "
8427 "reasonable value (%d)\n",
8428 __func__, nf, ATH9K_NF_TOO_LOW);
8429 return false;
8430 }
8431 return true; 3883 return true;
8432} 3884}
8433 3885
8434s16 3886void ath9k_hw_setopmode(struct ath_hal *ah)
8435ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
8436{ 3887{
8437 struct ath9k_channel *ichan; 3888 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
8438 s16 nf;
8439
8440 ichan = ath9k_regd_check_channel(ah, chan);
8441 if (ichan == NULL) {
8442 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
8443 "%s: invalid channel %u/0x%x; no mapping\n",
8444 __func__, chan->channel, chan->channelFlags);
8445 return ATH_DEFAULT_NOISE_FLOOR;
8446 }
8447 if (ichan->rawNoiseFloor == 0) {
8448 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
8449 nf = NOISE_FLOOR[mode];
8450 } else
8451 nf = ichan->rawNoiseFloor;
8452
8453 if (!ath9k_hw_nf_in_range(ah, nf))
8454 nf = ATH_DEFAULT_NOISE_FLOOR;
8455
8456 return nf;
8457} 3889}
8458 3890
8459bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting) 3891void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
8460{ 3892{
8461 struct ath_hal_5416 *ahp = AH5416(ah); 3893 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8462 3894 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8463 if (setting)
8464 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8465 else
8466 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8467 return true;
8468} 3895}
8469 3896
8470bool ath9k_hw_phycounters(struct ath_hal *ah) 3897void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
8471{ 3898{
8472 struct ath_hal_5416 *ahp = AH5416(ah); 3899 struct ath_hal_5416 *ahp = AH5416(ah);
8473 3900
8474 return ahp->ah_hasHwPhyCounters ? true : false; 3901 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
8475} 3902}
8476 3903
8477u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q) 3904bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
8478{ 3905{
8479 return REG_READ(ah, AR_QTXDP(q)); 3906 struct ath_hal_5416 *ahp = AH5416(ah);
8480}
8481 3907
8482bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, 3908 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
8483 u32 txdp) 3909
8484{ 3910 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
8485 REG_WRITE(ah, AR_QTXDP(q), txdp); 3911 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
8486 3912
8487 return true; 3913 return true;
8488} 3914}
8489 3915
8490bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) 3916void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
8491{ 3917{
8492 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); 3918 struct ath_hal_5416 *ahp = AH5416(ah);
8493 3919
8494 REG_WRITE(ah, AR_Q_TXE, 1 << q); 3920 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3921 ahp->ah_assocId = assocId;
8495 3922
8496 return true; 3923 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3924 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3925 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
8497} 3926}
8498 3927
8499u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q) 3928u64 ath9k_hw_gettsf64(struct ath_hal *ah)
8500{ 3929{
8501 u32 npend; 3930 u64 tsf;
8502 3931
8503 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; 3932 tsf = REG_READ(ah, AR_TSF_U32);
8504 if (npend == 0) { 3933 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
8505 3934
8506 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) 3935 return tsf;
8507 npend = 1;
8508 }
8509 return npend;
8510} 3936}
8511 3937
8512bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) 3938void ath9k_hw_reset_tsf(struct ath_hal *ah)
8513{ 3939{
8514 u32 wait; 3940 int count;
8515
8516 REG_WRITE(ah, AR_Q_TXD, 1 << q);
8517 3941
8518 for (wait = 1000; wait != 0; wait--) { 3942 count = 0;
8519 if (ath9k_hw_numtxpending(ah, q) == 0) 3943 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3944 count++;
3945 if (count > 10) {
3946 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3947 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
3948 __func__);
8520 break; 3949 break;
8521 udelay(100); 3950 }
3951 udelay(10);
8522 } 3952 }
3953 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3954}
8523 3955
8524 if (ath9k_hw_numtxpending(ah, q)) { 3956bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
8525 u32 tsfLow, j; 3957{
8526 3958 struct ath_hal_5416 *ahp = AH5416(ah);
8527 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8528 "%s: Num of pending TX Frames %d on Q %d\n",
8529 __func__, ath9k_hw_numtxpending(ah, q), q);
8530
8531 for (j = 0; j < 2; j++) {
8532 tsfLow = REG_READ(ah, AR_TSF_L32);
8533 REG_WRITE(ah, AR_QUIET2,
8534 SM(10, AR_QUIET2_QUIET_DUR));
8535 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
8536 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
8537 REG_SET_BIT(ah, AR_TIMER_MODE,
8538 AR_QUIET_TIMER_EN);
8539 3959
8540 if ((REG_READ(ah, AR_TSF_L32) >> 10) == 3960 if (setting)
8541 (tsfLow >> 10)) { 3961 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8542 break; 3962 else
8543 } 3963 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8544 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8545 "%s: TSF have moved while trying to set "
8546 "quiet time TSF: 0x%08x\n",
8547 __func__, tsfLow);
8548 }
8549 3964
8550 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 3965 return true;
3966}
8551 3967
8552 udelay(200); 3968bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
8553 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 3969{
3970 struct ath_hal_5416 *ahp = AH5416(ah);
8554 3971
8555 wait = 1000; 3972 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3973 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
3974 __func__, us);
3975 ahp->ah_slottime = (u32) -1;
3976 return false;
3977 } else {
3978 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3979 ahp->ah_slottime = us;
3980 return true;
3981 }
3982}
8556 3983
8557 while (ath9k_hw_numtxpending(ah, q)) { 3984void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
8558 if ((--wait) == 0) { 3985{
8559 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 3986 u32 macmode;
8560 "%s: Failed to stop Tx DMA in 100 "
8561 "msec after killing last frame\n",
8562 __func__);
8563 break;
8564 }
8565 udelay(100);
8566 }
8567 3987
8568 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 3988 if (mode == ATH9K_HT_MACMODE_2040 &&
8569 } 3989 !ah->ah_config.cwm_ignore_extcca)
3990 macmode = AR_2040_JOINED_RX_CLEAR;
3991 else
3992 macmode = 0;
8570 3993
8571 REG_WRITE(ah, AR_Q_TXD, 0); 3994 REG_WRITE(ah, AR_2040_MODE, macmode);
8572 return wait != 0;
8573} 3995}
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h
index 2113818ee934..6a29f2d43c21 100644
--- a/drivers/net/wireless/ath9k/hw.h
+++ b/drivers/net/wireless/ath9k/hw.h
@@ -923,7 +923,7 @@ struct ath_hal_5416 {
923#define OFDM_PLCP_BITS_QUARTER 22 923#define OFDM_PLCP_BITS_QUARTER 22
924#define OFDM_SYMBOL_TIME_QUARTER 16 924#define OFDM_SYMBOL_TIME_QUARTER 16
925 925
926u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp, 926u32 ath9k_hw_get_eeprom(struct ath_hal *ah,
927 enum eeprom_param param); 927 enum eeprom_param param);
928 928
929#endif 929#endif
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c
new file mode 100644
index 000000000000..c344a81e738a
--- /dev/null
+++ b/drivers/net/wireless/ath9k/mac.c
@@ -0,0 +1,1031 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "core.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21
22static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
23 struct ath9k_tx_queue_info *qi)
24{
25 struct ath_hal_5416 *ahp = AH5416(ah);
26
27 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
28 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
29 __func__, ahp->ah_txOkInterruptMask,
30 ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
31 ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask);
32
33 REG_WRITE(ah, AR_IMR_S0,
34 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
35 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC));
36 REG_WRITE(ah, AR_IMR_S1,
37 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
38 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL));
39 REG_RMW_FIELD(ah, AR_IMR_S2,
40 AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
41}
42
43void ath9k_hw_dmaRegDump(struct ath_hal *ah)
44{
45 u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
46 int qcuOffset = 0, dcuOffset = 0;
47 u32 *qcuBase = &val[0], *dcuBase = &val[4];
48 int i;
49
50 REG_WRITE(ah, AR_MACMISC,
51 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
52 (AR_MACMISC_MISC_OBS_BUS_1 <<
53 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
54
55 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n");
56
57 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
58 if (i % 4 == 0)
59 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
60
61 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
62 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
63 }
64
65 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
66 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
67 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
68
69 for (i = 0; i < ATH9K_NUM_QUEUES;
70 i++, qcuOffset += 4, dcuOffset += 5) {
71 if (i == 8) {
72 qcuOffset = 0;
73 qcuBase++;
74 }
75
76 if (i == 6) {
77 dcuOffset = 0;
78 dcuBase++;
79 }
80
81 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
82 "%2d %2x %1x %2x %2x\n",
83 i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
84 (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset + 3),
85 val[2] & (0x7 << (i * 3)) >> (i * 3),
86 (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
87 }
88
89 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
90 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
91 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
92 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
93 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
94 "qcu_complete state: %2x dcu_complete state: %2x\n",
95 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
96 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
97 "dcu_arb state: %2x dcu_fp state: %2x\n",
98 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
99 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
100 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
101 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
102 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
103 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
104 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
105 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
106 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
107 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
108
109 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
110 REG_READ(ah, AR_OBS_BUS_1));
111 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
112 "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
113}
114
115u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q)
116{
117 return REG_READ(ah, AR_QTXDP(q));
118}
119
120bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp)
121{
122 REG_WRITE(ah, AR_QTXDP(q), txdp);
123
124 return true;
125}
126
127bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
128{
129 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
130
131 REG_WRITE(ah, AR_Q_TXE, 1 << q);
132
133 return true;
134}
135
136u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q)
137{
138 u32 npend;
139
140 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
141 if (npend == 0) {
142
143 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
144 npend = 1;
145 }
146
147 return npend;
148}
149
150bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
151{
152 struct ath_hal_5416 *ahp = AH5416(ah);
153 u32 txcfg, curLevel, newLevel;
154 enum ath9k_int omask;
155
156 if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
157 return false;
158
159 omask = ath9k_hw_set_interrupts(ah, ahp->ah_maskReg & ~ATH9K_INT_GLOBAL);
160
161 txcfg = REG_READ(ah, AR_TXCFG);
162 curLevel = MS(txcfg, AR_FTRIG);
163 newLevel = curLevel;
164 if (bIncTrigLevel) {
165 if (curLevel < MAX_TX_FIFO_THRESHOLD)
166 newLevel++;
167 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
168 newLevel--;
169 if (newLevel != curLevel)
170 REG_WRITE(ah, AR_TXCFG,
171 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
172
173 ath9k_hw_set_interrupts(ah, omask);
174
175 ah->ah_txTrigLevel = newLevel;
176
177 return newLevel != curLevel;
178}
179
180bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
181{
182 u32 tsfLow, j, wait;
183
184 REG_WRITE(ah, AR_Q_TXD, 1 << q);
185
186 for (wait = 1000; wait != 0; wait--) {
187 if (ath9k_hw_numtxpending(ah, q) == 0)
188 break;
189 udelay(100);
190 }
191
192 if (ath9k_hw_numtxpending(ah, q)) {
193 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
194 "%s: Num of pending TX Frames %d on Q %d\n",
195 __func__, ath9k_hw_numtxpending(ah, q), q);
196
197 for (j = 0; j < 2; j++) {
198 tsfLow = REG_READ(ah, AR_TSF_L32);
199 REG_WRITE(ah, AR_QUIET2,
200 SM(10, AR_QUIET2_QUIET_DUR));
201 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
202 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
203 REG_SET_BIT(ah, AR_TIMER_MODE,
204 AR_QUIET_TIMER_EN);
205
206 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
207 break;
208
209 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
210 "%s: TSF have moved while trying to set "
211 "quiet time TSF: 0x%08x\n",
212 __func__, tsfLow);
213 }
214
215 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
216
217 udelay(200);
218 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
219
220 wait = 1000;
221
222 while (ath9k_hw_numtxpending(ah, q)) {
223 if ((--wait) == 0) {
224 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
225 "%s: Failed to stop Tx DMA in 100 "
226 "msec after killing last frame\n",
227 __func__);
228 break;
229 }
230 udelay(100);
231 }
232
233 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
234 }
235
236 REG_WRITE(ah, AR_Q_TXD, 0);
237
238 return wait != 0;
239}
240
241bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
242 u32 segLen, bool firstSeg,
243 bool lastSeg, const struct ath_desc *ds0)
244{
245 struct ar5416_desc *ads = AR5416DESC(ds);
246
247 if (firstSeg) {
248 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
249 } else if (lastSeg) {
250 ads->ds_ctl0 = 0;
251 ads->ds_ctl1 = segLen;
252 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
253 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
254 } else {
255 ads->ds_ctl0 = 0;
256 ads->ds_ctl1 = segLen | AR_TxMore;
257 ads->ds_ctl2 = 0;
258 ads->ds_ctl3 = 0;
259 }
260 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
261 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
262 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
263 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
264 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
265
266 return true;
267}
268
269void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
270{
271 struct ar5416_desc *ads = AR5416DESC(ds);
272
273 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
274 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
275 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
276 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
277 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
278}
279
280int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
281{
282 struct ar5416_desc *ads = AR5416DESC(ds);
283
284 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
285 return -EINPROGRESS;
286
287 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
288 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
289 ds->ds_txstat.ts_status = 0;
290 ds->ds_txstat.ts_flags = 0;
291
292 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
293 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
294 if (ads->ds_txstatus1 & AR_Filtered)
295 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
296 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
297 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
298 if (ads->ds_txstatus9 & AR_TxOpExceeded)
299 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
300 if (ads->ds_txstatus1 & AR_TxTimerExpired)
301 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
302
303 if (ads->ds_txstatus1 & AR_DescCfgErr)
304 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
305 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
306 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
307 ath9k_hw_updatetxtriglevel(ah, true);
308 }
309 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
310 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
311 ath9k_hw_updatetxtriglevel(ah, true);
312 }
313 if (ads->ds_txstatus0 & AR_TxBaStatus) {
314 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
315 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
316 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
317 }
318
319 ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
320 switch (ds->ds_txstat.ts_rateindex) {
321 case 0:
322 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
323 break;
324 case 1:
325 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
326 break;
327 case 2:
328 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
329 break;
330 case 3:
331 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
332 break;
333 }
334
335 ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
336 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
337 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
338 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
339 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
340 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
341 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
342 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
343 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
344 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
345 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
346 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
347 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
348 ds->ds_txstat.ts_antenna = 1;
349
350 return 0;
351}
352
353void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
354 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
355 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
356{
357 struct ar5416_desc *ads = AR5416DESC(ds);
358 struct ath_hal_5416 *ahp = AH5416(ah);
359
360 txPower += ahp->ah_txPowerIndexOffset;
361 if (txPower > 63)
362 txPower = 63;
363
364 ads->ds_ctl0 = (pktLen & AR_FrameLen)
365 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
366 | SM(txPower, AR_XmitPower)
367 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
368 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
369 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
370 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
371
372 ads->ds_ctl1 =
373 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
374 | SM(type, AR_FrameType)
375 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
376 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
377 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
378
379 ads->ds_ctl6 = SM(keyType, AR_EncrType);
380
381 if (AR_SREV_9285(ah)) {
382 ads->ds_ctl8 = 0;
383 ads->ds_ctl9 = 0;
384 ads->ds_ctl10 = 0;
385 ads->ds_ctl11 = 0;
386 }
387}
388
389void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
390 struct ath_desc *lastds,
391 u32 durUpdateEn, u32 rtsctsRate,
392 u32 rtsctsDuration,
393 struct ath9k_11n_rate_series series[],
394 u32 nseries, u32 flags)
395{
396 struct ar5416_desc *ads = AR5416DESC(ds);
397 struct ar5416_desc *last_ads = AR5416DESC(lastds);
398 u32 ds_ctl0;
399
400 (void) nseries;
401 (void) rtsctsDuration;
402
403 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
404 ds_ctl0 = ads->ds_ctl0;
405
406 if (flags & ATH9K_TXDESC_RTSENA) {
407 ds_ctl0 &= ~AR_CTSEnable;
408 ds_ctl0 |= AR_RTSEnable;
409 } else {
410 ds_ctl0 &= ~AR_RTSEnable;
411 ds_ctl0 |= AR_CTSEnable;
412 }
413
414 ads->ds_ctl0 = ds_ctl0;
415 } else {
416 ads->ds_ctl0 =
417 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
418 }
419
420 ads->ds_ctl2 = set11nTries(series, 0)
421 | set11nTries(series, 1)
422 | set11nTries(series, 2)
423 | set11nTries(series, 3)
424 | (durUpdateEn ? AR_DurUpdateEna : 0)
425 | SM(0, AR_BurstDur);
426
427 ads->ds_ctl3 = set11nRate(series, 0)
428 | set11nRate(series, 1)
429 | set11nRate(series, 2)
430 | set11nRate(series, 3);
431
432 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
433 | set11nPktDurRTSCTS(series, 1);
434
435 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
436 | set11nPktDurRTSCTS(series, 3);
437
438 ads->ds_ctl7 = set11nRateFlags(series, 0)
439 | set11nRateFlags(series, 1)
440 | set11nRateFlags(series, 2)
441 | set11nRateFlags(series, 3)
442 | SM(rtsctsRate, AR_RTSCTSRate);
443 last_ads->ds_ctl2 = ads->ds_ctl2;
444 last_ads->ds_ctl3 = ads->ds_ctl3;
445}
446
447void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
448 u32 aggrLen)
449{
450 struct ar5416_desc *ads = AR5416DESC(ds);
451
452 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
453 ads->ds_ctl6 &= ~AR_AggrLen;
454 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
455}
456
457void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
458 u32 numDelims)
459{
460 struct ar5416_desc *ads = AR5416DESC(ds);
461 unsigned int ctl6;
462
463 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
464
465 ctl6 = ads->ds_ctl6;
466 ctl6 &= ~AR_PadDelim;
467 ctl6 |= SM(numDelims, AR_PadDelim);
468 ads->ds_ctl6 = ctl6;
469}
470
471void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
472{
473 struct ar5416_desc *ads = AR5416DESC(ds);
474
475 ads->ds_ctl1 |= AR_IsAggr;
476 ads->ds_ctl1 &= ~AR_MoreAggr;
477 ads->ds_ctl6 &= ~AR_PadDelim;
478}
479
480void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
481{
482 struct ar5416_desc *ads = AR5416DESC(ds);
483
484 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
485}
486
487void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
488 u32 burstDuration)
489{
490 struct ar5416_desc *ads = AR5416DESC(ds);
491
492 ads->ds_ctl2 &= ~AR_BurstDur;
493 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
494}
495
496void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
497 u32 vmf)
498{
499 struct ar5416_desc *ads = AR5416DESC(ds);
500
501 if (vmf)
502 ads->ds_ctl0 |= AR_VirtMoreFrag;
503 else
504 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
505}
506
507void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs)
508{
509 struct ath_hal_5416 *ahp = AH5416(ah);
510
511 *txqs &= ahp->ah_intrTxqs;
512 ahp->ah_intrTxqs &= ~(*txqs);
513}
514
515bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
516 const struct ath9k_tx_queue_info *qinfo)
517{
518 u32 cw;
519 struct ath_hal_5416 *ahp = AH5416(ah);
520 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
521 struct ath9k_tx_queue_info *qi;
522
523 if (q >= pCap->total_queues) {
524 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
525 __func__, q);
526 return false;
527 }
528
529 qi = &ahp->ah_txq[q];
530 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
531 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
532 __func__);
533 return false;
534 }
535
536 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi);
537
538 qi->tqi_ver = qinfo->tqi_ver;
539 qi->tqi_subtype = qinfo->tqi_subtype;
540 qi->tqi_qflags = qinfo->tqi_qflags;
541 qi->tqi_priority = qinfo->tqi_priority;
542 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
543 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
544 else
545 qi->tqi_aifs = INIT_AIFS;
546 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
547 cw = min(qinfo->tqi_cwmin, 1024U);
548 qi->tqi_cwmin = 1;
549 while (qi->tqi_cwmin < cw)
550 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
551 } else
552 qi->tqi_cwmin = qinfo->tqi_cwmin;
553 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
554 cw = min(qinfo->tqi_cwmax, 1024U);
555 qi->tqi_cwmax = 1;
556 while (qi->tqi_cwmax < cw)
557 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
558 } else
559 qi->tqi_cwmax = INIT_CWMAX;
560
561 if (qinfo->tqi_shretry != 0)
562 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
563 else
564 qi->tqi_shretry = INIT_SH_RETRY;
565 if (qinfo->tqi_lgretry != 0)
566 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
567 else
568 qi->tqi_lgretry = INIT_LG_RETRY;
569 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
570 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
571 qi->tqi_burstTime = qinfo->tqi_burstTime;
572 qi->tqi_readyTime = qinfo->tqi_readyTime;
573
574 switch (qinfo->tqi_subtype) {
575 case ATH9K_WME_UPSD:
576 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
577 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
578 break;
579 default:
580 break;
581 }
582
583 return true;
584}
585
586bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
587 struct ath9k_tx_queue_info *qinfo)
588{
589 struct ath_hal_5416 *ahp = AH5416(ah);
590 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
591 struct ath9k_tx_queue_info *qi;
592
593 if (q >= pCap->total_queues) {
594 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
595 __func__, q);
596 return false;
597 }
598
599 qi = &ahp->ah_txq[q];
600 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
601 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n",
602 __func__);
603 return false;
604 }
605
606 qinfo->tqi_qflags = qi->tqi_qflags;
607 qinfo->tqi_ver = qi->tqi_ver;
608 qinfo->tqi_subtype = qi->tqi_subtype;
609 qinfo->tqi_qflags = qi->tqi_qflags;
610 qinfo->tqi_priority = qi->tqi_priority;
611 qinfo->tqi_aifs = qi->tqi_aifs;
612 qinfo->tqi_cwmin = qi->tqi_cwmin;
613 qinfo->tqi_cwmax = qi->tqi_cwmax;
614 qinfo->tqi_shretry = qi->tqi_shretry;
615 qinfo->tqi_lgretry = qi->tqi_lgretry;
616 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
617 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
618 qinfo->tqi_burstTime = qi->tqi_burstTime;
619 qinfo->tqi_readyTime = qi->tqi_readyTime;
620
621 return true;
622}
623
624int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
625 const struct ath9k_tx_queue_info *qinfo)
626{
627 struct ath_hal_5416 *ahp = AH5416(ah);
628 struct ath9k_tx_queue_info *qi;
629 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
630 int q;
631
632 switch (type) {
633 case ATH9K_TX_QUEUE_BEACON:
634 q = pCap->total_queues - 1;
635 break;
636 case ATH9K_TX_QUEUE_CAB:
637 q = pCap->total_queues - 2;
638 break;
639 case ATH9K_TX_QUEUE_PSPOLL:
640 q = 1;
641 break;
642 case ATH9K_TX_QUEUE_UAPSD:
643 q = pCap->total_queues - 3;
644 break;
645 case ATH9K_TX_QUEUE_DATA:
646 for (q = 0; q < pCap->total_queues; q++)
647 if (ahp->ah_txq[q].tqi_type ==
648 ATH9K_TX_QUEUE_INACTIVE)
649 break;
650 if (q == pCap->total_queues) {
651 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
652 "%s: no available tx queue\n", __func__);
653 return -1;
654 }
655 break;
656 default:
657 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n",
658 __func__, type);
659 return -1;
660 }
661
662 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q);
663
664 qi = &ahp->ah_txq[q];
665 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
666 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
667 "%s: tx queue %u already active\n", __func__, q);
668 return -1;
669 }
670 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
671 qi->tqi_type = type;
672 if (qinfo == NULL) {
673 qi->tqi_qflags =
674 TXQ_FLAG_TXOKINT_ENABLE
675 | TXQ_FLAG_TXERRINT_ENABLE
676 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
677 qi->tqi_aifs = INIT_AIFS;
678 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
679 qi->tqi_cwmax = INIT_CWMAX;
680 qi->tqi_shretry = INIT_SH_RETRY;
681 qi->tqi_lgretry = INIT_LG_RETRY;
682 qi->tqi_physCompBuf = 0;
683 } else {
684 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
685 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
686 }
687
688 return q;
689}
690
691bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
692{
693 struct ath_hal_5416 *ahp = AH5416(ah);
694 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
695 struct ath9k_tx_queue_info *qi;
696
697 if (q >= pCap->total_queues) {
698 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
699 __func__, q);
700 return false;
701 }
702 qi = &ahp->ah_txq[q];
703 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
704 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
705 __func__, q);
706 return false;
707 }
708
709 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n",
710 __func__, q);
711
712 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
713 ahp->ah_txOkInterruptMask &= ~(1 << q);
714 ahp->ah_txErrInterruptMask &= ~(1 << q);
715 ahp->ah_txDescInterruptMask &= ~(1 << q);
716 ahp->ah_txEolInterruptMask &= ~(1 << q);
717 ahp->ah_txUrnInterruptMask &= ~(1 << q);
718 ath9k_hw_set_txq_interrupts(ah, qi);
719
720 return true;
721}
722
723bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
724{
725 struct ath_hal_5416 *ahp = AH5416(ah);
726 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
727 struct ath9k_channel *chan = ah->ah_curchan;
728 struct ath9k_tx_queue_info *qi;
729 u32 cwMin, chanCwMin, value;
730
731 if (q >= pCap->total_queues) {
732 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
733 __func__, q);
734 return false;
735 }
736
737 qi = &ahp->ah_txq[q];
738 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
739 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n",
740 __func__, q);
741 return true;
742 }
743
744 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
745
746 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
747 if (chan && IS_CHAN_B(chan))
748 chanCwMin = INIT_CWMIN_11B;
749 else
750 chanCwMin = INIT_CWMIN;
751
752 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
753 } else
754 cwMin = qi->tqi_cwmin;
755
756 REG_WRITE(ah, AR_DLCL_IFS(q),
757 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
758 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
759 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
760
761 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
762 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
763 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
764 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
765
766 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
767 REG_WRITE(ah, AR_DMISC(q),
768 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
769
770 if (qi->tqi_cbrPeriod) {
771 REG_WRITE(ah, AR_QCBRCFG(q),
772 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
773 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
774 REG_WRITE(ah, AR_QMISC(q),
775 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
776 (qi->tqi_cbrOverflowLimit ?
777 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
778 }
779 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
780 REG_WRITE(ah, AR_QRDYTIMECFG(q),
781 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
782 AR_Q_RDYTIMECFG_EN);
783 }
784
785 REG_WRITE(ah, AR_DCHNTIME(q),
786 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
787 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
788
789 if (qi->tqi_burstTime
790 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
791 REG_WRITE(ah, AR_QMISC(q),
792 REG_READ(ah, AR_QMISC(q)) |
793 AR_Q_MISC_RDYTIME_EXP_POLICY);
794
795 }
796
797 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
798 REG_WRITE(ah, AR_DMISC(q),
799 REG_READ(ah, AR_DMISC(q)) |
800 AR_D_MISC_POST_FR_BKOFF_DIS);
801 }
802 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
803 REG_WRITE(ah, AR_DMISC(q),
804 REG_READ(ah, AR_DMISC(q)) |
805 AR_D_MISC_FRAG_BKOFF_EN);
806 }
807 switch (qi->tqi_type) {
808 case ATH9K_TX_QUEUE_BEACON:
809 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
810 | AR_Q_MISC_FSP_DBA_GATED
811 | AR_Q_MISC_BEACON_USE
812 | AR_Q_MISC_CBR_INCR_DIS1);
813
814 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
815 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
816 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
817 | AR_D_MISC_BEACON_USE
818 | AR_D_MISC_POST_FR_BKOFF_DIS);
819 break;
820 case ATH9K_TX_QUEUE_CAB:
821 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
822 | AR_Q_MISC_FSP_DBA_GATED
823 | AR_Q_MISC_CBR_INCR_DIS1
824 | AR_Q_MISC_CBR_INCR_DIS0);
825 value = (qi->tqi_readyTime -
826 (ah->ah_config.sw_beacon_response_time -
827 ah->ah_config.dma_beacon_response_time) -
828 ah->ah_config.additional_swba_backoff) * 1024;
829 REG_WRITE(ah, AR_QRDYTIMECFG(q),
830 value | AR_Q_RDYTIMECFG_EN);
831 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
832 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
833 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
834 break;
835 case ATH9K_TX_QUEUE_PSPOLL:
836 REG_WRITE(ah, AR_QMISC(q),
837 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
838 break;
839 case ATH9K_TX_QUEUE_UAPSD:
840 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
841 AR_D_MISC_POST_FR_BKOFF_DIS);
842 break;
843 default:
844 break;
845 }
846
847 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
848 REG_WRITE(ah, AR_DMISC(q),
849 REG_READ(ah, AR_DMISC(q)) |
850 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
851 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
852 AR_D_MISC_POST_FR_BKOFF_DIS);
853 }
854
855 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
856 ahp->ah_txOkInterruptMask |= 1 << q;
857 else
858 ahp->ah_txOkInterruptMask &= ~(1 << q);
859 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
860 ahp->ah_txErrInterruptMask |= 1 << q;
861 else
862 ahp->ah_txErrInterruptMask &= ~(1 << q);
863 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
864 ahp->ah_txDescInterruptMask |= 1 << q;
865 else
866 ahp->ah_txDescInterruptMask &= ~(1 << q);
867 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
868 ahp->ah_txEolInterruptMask |= 1 << q;
869 else
870 ahp->ah_txEolInterruptMask &= ~(1 << q);
871 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
872 ahp->ah_txUrnInterruptMask |= 1 << q;
873 else
874 ahp->ah_txUrnInterruptMask &= ~(1 << q);
875 ath9k_hw_set_txq_interrupts(ah, qi);
876
877 return true;
878}
879
880int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
881 u32 pa, struct ath_desc *nds, u64 tsf)
882{
883 struct ar5416_desc ads;
884 struct ar5416_desc *adsp = AR5416DESC(ds);
885 u32 phyerr;
886
887 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
888 return -EINPROGRESS;
889
890 ads.u.rx = adsp->u.rx;
891
892 ds->ds_rxstat.rs_status = 0;
893 ds->ds_rxstat.rs_flags = 0;
894
895 ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
896 ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
897
898 ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
899 ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
900 ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
901 ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
902 ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
903 ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
904 ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
905 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
906 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
907 else
908 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID;
909
910 ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
911 ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
912
913 ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
914 ds->ds_rxstat.rs_moreaggr =
915 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
916 ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
917 ds->ds_rxstat.rs_flags =
918 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
919 ds->ds_rxstat.rs_flags |=
920 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
921
922 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
923 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
924 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
925 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
926 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
927 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
928
929 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
930 if (ads.ds_rxstatus8 & AR_CRCErr)
931 ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
932 else if (ads.ds_rxstatus8 & AR_PHYErr) {
933 ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
934 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
935 ds->ds_rxstat.rs_phyerr = phyerr;
936 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
937 ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
938 else if (ads.ds_rxstatus8 & AR_MichaelErr)
939 ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
940 }
941
942 return 0;
943}
944
945bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
946 u32 size, u32 flags)
947{
948 struct ar5416_desc *ads = AR5416DESC(ds);
949 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
950
951 ads->ds_ctl1 = size & AR_BufLen;
952 if (flags & ATH9K_RXDESC_INTREQ)
953 ads->ds_ctl1 |= AR_RxIntrReq;
954
955 ads->ds_rxstatus8 &= ~AR_RxDone;
956 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
957 memset(&(ads->u), 0, sizeof(ads->u));
958
959 return true;
960}
961
962bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
963{
964 u32 reg;
965
966 if (set) {
967 REG_SET_BIT(ah, AR_DIAG_SW,
968 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
969
970 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
971 REG_CLR_BIT(ah, AR_DIAG_SW,
972 (AR_DIAG_RX_DIS |
973 AR_DIAG_RX_ABORT));
974
975 reg = REG_READ(ah, AR_OBS_BUS_1);
976 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
977 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
978 __func__, reg);
979
980 return false;
981 }
982 } else {
983 REG_CLR_BIT(ah, AR_DIAG_SW,
984 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
985 }
986
987 return true;
988}
989
990void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp)
991{
992 REG_WRITE(ah, AR_RXDP, rxdp);
993}
994
995void ath9k_hw_rxena(struct ath_hal *ah)
996{
997 REG_WRITE(ah, AR_CR, AR_CR_RXE);
998}
999
1000void ath9k_hw_startpcureceive(struct ath_hal *ah)
1001{
1002 REG_CLR_BIT(ah, AR_DIAG_SW,
1003 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1004
1005 ath9k_enable_mib_counters(ah);
1006
1007 ath9k_ani_reset(ah);
1008}
1009
1010void ath9k_hw_stoppcurecv(struct ath_hal *ah)
1011{
1012 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1013
1014 ath9k_hw_disable_mib_counters(ah);
1015}
1016
1017bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
1018{
1019 REG_WRITE(ah, AR_CR, AR_CR_RXD);
1020
1021 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
1022 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1023 "%s: dma failed to stop in 10ms\n"
1024 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
1025 __func__,
1026 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
1027 return false;
1028 } else {
1029 return true;
1030 }
1031}
diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c
index eb9121fdfd38..4f1c8bf8342b 100644
--- a/drivers/net/wireless/ath9k/phy.c
+++ b/drivers/net/wireless/ath9k/phy.c
@@ -215,7 +215,7 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
215 if (AR_SREV_9280_10_OR_LATER(ah)) 215 if (AR_SREV_9280_10_OR_LATER(ah))
216 return true; 216 return true;
217 217
218 eepMinorRev = ath9k_hw_get_eeprom(ahp, EEP_MINOR_REV); 218 eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV);
219 219
220 RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1); 220 RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1);
221 221
@@ -235,15 +235,15 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
235 235
236 if (eepMinorRev >= 2) { 236 if (eepMinorRev >= 2) {
237 if (IS_CHAN_2GHZ(chan)) { 237 if (IS_CHAN_2GHZ(chan)) {
238 ob2GHz = ath9k_hw_get_eeprom(ahp, EEP_OB_2); 238 ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2);
239 db2GHz = ath9k_hw_get_eeprom(ahp, EEP_DB_2); 239 db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2);
240 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 240 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
241 ob2GHz, 3, 197, 0); 241 ob2GHz, 3, 197, 0);
242 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 242 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
243 db2GHz, 3, 194, 0); 243 db2GHz, 3, 194, 0);
244 } else { 244 } else {
245 ob5GHz = ath9k_hw_get_eeprom(ahp, EEP_OB_5); 245 ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5);
246 db5GHz = ath9k_hw_get_eeprom(ahp, EEP_DB_5); 246 db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5);
247 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 247 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
248 ob5GHz, 3, 203, 0); 248 ob5GHz, 3, 203, 0);
249 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 249 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 23:25:04 -0500