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-rw-r--r--arch/arm/mach-mmp/Kconfig7
-rw-r--r--arch/arm/mach-mmp/aspenite.c20
-rw-r--r--arch/arm/mach-mmp/devices.c282
-rw-r--r--arch/arm/mach-mmp/include/mach/devices.h3
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa168.h8
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa910.h3
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-usb.h253
-rw-r--r--arch/arm/mach-mmp/pxa168.c20
-rw-r--r--arch/arm/mach-mmp/pxa910.c2
-rw-r--r--arch/arm/mach-mmp/ttc_dkb.c37
-rw-r--r--arch/arm/mach-pxa/hx4700.c10
-rw-r--r--arch/arm/mach-pxa/include/mach/mioa701.h3
-rw-r--r--arch/arm/mach-pxa/include/mach/pcm990_baseboard.h68
-rw-r--r--arch/arm/mach-pxa/mioa701.c2
-rw-r--r--arch/arm/mach-pxa/pcm990-baseboard.c83
-rw-r--r--drivers/pcmcia/Kconfig2
-rw-r--r--drivers/pcmcia/Makefile1
-rw-r--r--drivers/pcmcia/pxa2xx_hx4700.c121
-rw-r--r--include/linux/mfd/asic3.h1
19 files changed, 809 insertions, 117 deletions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 5a90b9a3ab6e..fa03974fd838 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -113,4 +113,11 @@ config CPU_MMP2
113 select CPU_PJ4 113 select CPU_PJ4
114 help 114 help
115 Select code specific to MMP2. MMP2 is ARMv7 compatible. 115 Select code specific to MMP2. MMP2 is ARMv7 compatible.
116
117config USB_EHCI_MV_U2O
118 bool "EHCI support for PXA USB OTG controller"
119 depends on USB_EHCI_MV
120 help
121 Enables support for OTG controller which can be switched to host mode.
122
116endif 123endif
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index bf5d8e195c3e..223090b1444d 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -17,6 +17,7 @@
17#include <linux/mtd/partitions.h> 17#include <linux/mtd/partitions.h>
18#include <linux/mtd/nand.h> 18#include <linux/mtd/nand.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/platform_data/mv_usb.h>
20 21
21#include <asm/mach-types.h> 22#include <asm/mach-types.h>
22#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
@@ -221,6 +222,21 @@ static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
221 .debounce_interval = 30, 222 .debounce_interval = 30,
222}; 223};
223 224
225#if defined(CONFIG_USB_EHCI_MV)
226static char *pxa168_sph_clock_name[] = {
227 [0] = "PXA168-USBCLK",
228};
229
230static struct mv_usb_platform_data pxa168_sph_pdata = {
231 .clknum = 1,
232 .clkname = pxa168_sph_clock_name,
233 .mode = MV_USB_MODE_HOST,
234 .phy_init = pxa_usb_phy_init,
235 .phy_deinit = pxa_usb_phy_deinit,
236 .set_vbus = NULL,
237};
238#endif
239
224static void __init common_init(void) 240static void __init common_init(void)
225{ 241{
226 mfp_config(ARRAY_AND_SIZE(common_pin_config)); 242 mfp_config(ARRAY_AND_SIZE(common_pin_config));
@@ -236,6 +252,10 @@ static void __init common_init(void)
236 252
237 /* off-chip devices */ 253 /* off-chip devices */
238 platform_device_register(&smc91x_device); 254 platform_device_register(&smc91x_device);
255
256#if defined(CONFIG_USB_EHCI_MV)
257 pxa168_add_usb_host(&pxa168_sph_pdata);
258#endif
239} 259}
240 260
241MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform") 261MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
index 191d9dea8731..dd2d8b103cc8 100644
--- a/arch/arm/mach-mmp/devices.c
+++ b/arch/arm/mach-mmp/devices.c
@@ -9,9 +9,13 @@
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/dma-mapping.h> 11#include <linux/dma-mapping.h>
12#include <linux/delay.h>
12 13
13#include <asm/irq.h> 14#include <asm/irq.h>
15#include <mach/irqs.h>
14#include <mach/devices.h> 16#include <mach/devices.h>
17#include <mach/cputype.h>
18#include <mach/regs-usb.h>
15 19
16int __init pxa_register_device(struct pxa_device_desc *desc, 20int __init pxa_register_device(struct pxa_device_desc *desc,
17 void *data, size_t size) 21 void *data, size_t size)
@@ -67,3 +71,281 @@ int __init pxa_register_device(struct pxa_device_desc *desc,
67 71
68 return platform_device_add(pdev); 72 return platform_device_add(pdev);
69} 73}
74
75#if defined(CONFIG_USB) || defined(CONFIG_USB_GADGET)
76
77/*****************************************************************************
78 * The registers read/write routines
79 *****************************************************************************/
80
81static unsigned int u2o_get(void __iomem *base, unsigned int offset)
82{
83 return readl_relaxed(base + offset);
84}
85
86static void u2o_set(void __iomem *base, unsigned int offset,
87 unsigned int value)
88{
89 u32 reg;
90
91 reg = readl_relaxed(base + offset);
92 reg |= value;
93 writel_relaxed(reg, base + offset);
94 readl_relaxed(base + offset);
95}
96
97static void u2o_clear(void __iomem *base, unsigned int offset,
98 unsigned int value)
99{
100 u32 reg;
101
102 reg = readl_relaxed(base + offset);
103 reg &= ~value;
104 writel_relaxed(reg, base + offset);
105 readl_relaxed(base + offset);
106}
107
108static void u2o_write(void __iomem *base, unsigned int offset,
109 unsigned int value)
110{
111 writel_relaxed(value, base + offset);
112 readl_relaxed(base + offset);
113}
114
115#if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV)
116
117#if defined(CONFIG_CPU_PXA910) || defined(CONFIG_CPU_PXA168)
118
119static DEFINE_MUTEX(phy_lock);
120static int phy_init_cnt;
121
122static int usb_phy_init_internal(void __iomem *base)
123{
124 int loops;
125
126 pr_info("Init usb phy!!!\n");
127
128 /* Initialize the USB PHY power */
129 if (cpu_is_pxa910()) {
130 u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
131 | (1<<UTMI_CTRL_PU_REF_SHIFT));
132 }
133
134 u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
135 u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
136
137 /* UTMI_PLL settings */
138 u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK
139 | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK
140 | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK
141 | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK);
142
143 u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT
144 | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT
145 | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT
146 | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT);
147
148 /* UTMI_TX */
149 u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
150 | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK
151 | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK
152 | UTMI_TX_AMP_MASK);
153 u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT
154 | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT
155 | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT);
156
157 /* UTMI_RX */
158 u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK
159 | UTMI_REG_SQ_LENGTH_MASK);
160 u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT
161 | 2<<UTMI_REG_SQ_LENGTH_SHIFT);
162
163 /* UTMI_IVREF */
164 if (cpu_is_pxa168())
165 /* fixing Microsoft Altair board interface with NEC hub issue -
166 * Set UTMI_IVREF from 0x4a3 to 0x4bf */
167 u2o_write(base, UTMI_IVREF, 0x4bf);
168
169 /* toggle VCOCAL_START bit of UTMI_PLL */
170 udelay(200);
171 u2o_set(base, UTMI_PLL, VCOCAL_START);
172 udelay(40);
173 u2o_clear(base, UTMI_PLL, VCOCAL_START);
174
175 /* toggle REG_RCAL_START bit of UTMI_TX */
176 udelay(400);
177 u2o_set(base, UTMI_TX, REG_RCAL_START);
178 udelay(40);
179 u2o_clear(base, UTMI_TX, REG_RCAL_START);
180 udelay(400);
181
182 /* Make sure PHY PLL is ready */
183 loops = 0;
184 while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) {
185 mdelay(1);
186 loops++;
187 if (loops > 100) {
188 printk(KERN_WARNING "calibrate timeout, UTMI_PLL %x\n",
189 u2o_get(base, UTMI_PLL));
190 break;
191 }
192 }
193
194 if (cpu_is_pxa168()) {
195 u2o_set(base, UTMI_RESERVE, 1 << 5);
196 /* Turn on UTMI PHY OTG extension */
197 u2o_write(base, UTMI_OTG_ADDON, 1);
198 }
199
200 return 0;
201}
202
203static int usb_phy_deinit_internal(void __iomem *base)
204{
205 pr_info("Deinit usb phy!!!\n");
206
207 if (cpu_is_pxa168())
208 u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON);
209
210 u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN);
211 u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN);
212 u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN);
213 u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
214 u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
215
216 return 0;
217}
218
219int pxa_usb_phy_init(void __iomem *phy_reg)
220{
221 mutex_lock(&phy_lock);
222 if (phy_init_cnt++ == 0)
223 usb_phy_init_internal(phy_reg);
224 mutex_unlock(&phy_lock);
225 return 0;
226}
227
228void pxa_usb_phy_deinit(void __iomem *phy_reg)
229{
230 WARN_ON(phy_init_cnt == 0);
231
232 mutex_lock(&phy_lock);
233 if (--phy_init_cnt == 0)
234 usb_phy_deinit_internal(phy_reg);
235 mutex_unlock(&phy_lock);
236}
237#endif
238#endif
239#endif
240
241#ifdef CONFIG_USB_SUPPORT
242static u64 usb_dma_mask = ~(u32)0;
243
244#ifdef CONFIG_USB_MV_UDC
245struct resource pxa168_u2o_resources[] = {
246 /* regbase */
247 [0] = {
248 .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
249 .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
250 .flags = IORESOURCE_MEM,
251 .name = "capregs",
252 },
253 /* phybase */
254 [1] = {
255 .start = PXA168_U2O_PHYBASE,
256 .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
257 .flags = IORESOURCE_MEM,
258 .name = "phyregs",
259 },
260 [2] = {
261 .start = IRQ_PXA168_USB1,
262 .end = IRQ_PXA168_USB1,
263 .flags = IORESOURCE_IRQ,
264 },
265};
266
267struct platform_device pxa168_device_u2o = {
268 .name = "mv-udc",
269 .id = -1,
270 .resource = pxa168_u2o_resources,
271 .num_resources = ARRAY_SIZE(pxa168_u2o_resources),
272 .dev = {
273 .dma_mask = &usb_dma_mask,
274 .coherent_dma_mask = 0xffffffff,
275 }
276};
277#endif /* CONFIG_USB_MV_UDC */
278
279#ifdef CONFIG_USB_EHCI_MV_U2O
280struct resource pxa168_u2oehci_resources[] = {
281 /* regbase */
282 [0] = {
283 .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
284 .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
285 .flags = IORESOURCE_MEM,
286 .name = "capregs",
287 },
288 /* phybase */
289 [1] = {
290 .start = PXA168_U2O_PHYBASE,
291 .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
292 .flags = IORESOURCE_MEM,
293 .name = "phyregs",
294 },
295 [2] = {
296 .start = IRQ_PXA168_USB1,
297 .end = IRQ_PXA168_USB1,
298 .flags = IORESOURCE_IRQ,
299 },
300};
301
302struct platform_device pxa168_device_u2oehci = {
303 .name = "pxa-u2oehci",
304 .id = -1,
305 .dev = {
306 .dma_mask = &usb_dma_mask,
307 .coherent_dma_mask = 0xffffffff,
308 },
309
310 .num_resources = ARRAY_SIZE(pxa168_u2oehci_resources),
311 .resource = pxa168_u2oehci_resources,
312};
313#endif
314
315#if defined(CONFIG_USB_MV_OTG)
316struct resource pxa168_u2ootg_resources[] = {
317 /* regbase */
318 [0] = {
319 .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
320 .end = PXA168_U2O_REGBASE + USB_REG_RANGE,
321 .flags = IORESOURCE_MEM,
322 .name = "capregs",
323 },
324 /* phybase */
325 [1] = {
326 .start = PXA168_U2O_PHYBASE,
327 .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
328 .flags = IORESOURCE_MEM,
329 .name = "phyregs",
330 },
331 [2] = {
332 .start = IRQ_PXA168_USB1,
333 .end = IRQ_PXA168_USB1,
334 .flags = IORESOURCE_IRQ,
335 },
336};
337
338struct platform_device pxa168_device_u2ootg = {
339 .name = "mv-otg",
340 .id = -1,
341 .dev = {
342 .dma_mask = &usb_dma_mask,
343 .coherent_dma_mask = 0xffffffff,
344 },
345
346 .num_resources = ARRAY_SIZE(pxa168_u2ootg_resources),
347 .resource = pxa168_u2ootg_resources,
348};
349#endif /* CONFIG_USB_MV_OTG */
350
351#endif
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h
index d0ec7dae88e4..21217ef11b64 100644
--- a/arch/arm/mach-mmp/include/mach/devices.h
+++ b/arch/arm/mach-mmp/include/mach/devices.h
@@ -50,4 +50,7 @@ struct pxa_device_desc mmp2_device_##_name __initdata = { \
50} 50}
51 51
52extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); 52extern int pxa_register_device(struct pxa_device_desc *, void *, size_t);
53extern int pxa_usb_phy_init(void __iomem *phy_reg);
54extern void pxa_usb_phy_deinit(void __iomem *phy_reg);
55
53#endif /* __MACH_DEVICE_H */ 56#endif /* __MACH_DEVICE_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index dc03d580a06d..09dcd6e2b6a8 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -16,6 +16,7 @@ extern void pxa168_clear_keypad_wakeup(void);
16#include <plat/pxa27x_keypad.h> 16#include <plat/pxa27x_keypad.h>
17#include <mach/cputype.h> 17#include <mach/cputype.h>
18#include <linux/pxa168_eth.h> 18#include <linux/pxa168_eth.h>
19#include <linux/platform_data/mv_usb.h>
19 20
20extern struct pxa_device_desc pxa168_device_uart1; 21extern struct pxa_device_desc pxa168_device_uart1;
21extern struct pxa_device_desc pxa168_device_uart2; 22extern struct pxa_device_desc pxa168_device_uart2;
@@ -36,12 +37,9 @@ extern struct pxa_device_desc pxa168_device_fb;
36extern struct pxa_device_desc pxa168_device_keypad; 37extern struct pxa_device_desc pxa168_device_keypad;
37extern struct pxa_device_desc pxa168_device_eth; 38extern struct pxa_device_desc pxa168_device_eth;
38 39
39struct pxa168_usb_pdata {
40 /* If NULL, default phy init routine for PXA168 would be called */
41 int (*phy_init)(void __iomem *usb_phy_reg_base);
42};
43/* pdata can be NULL */ 40/* pdata can be NULL */
44int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata); 41extern int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata);
42
45 43
46extern struct platform_device pxa168_device_gpio; 44extern struct platform_device pxa168_device_gpio;
47 45
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index e2e1f1e5e124..793634c837ef 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -20,6 +20,9 @@ extern struct pxa_device_desc pxa910_device_pwm2;
20extern struct pxa_device_desc pxa910_device_pwm3; 20extern struct pxa_device_desc pxa910_device_pwm3;
21extern struct pxa_device_desc pxa910_device_pwm4; 21extern struct pxa_device_desc pxa910_device_pwm4;
22extern struct pxa_device_desc pxa910_device_nand; 22extern struct pxa_device_desc pxa910_device_nand;
23extern struct platform_device pxa168_device_u2o;
24extern struct platform_device pxa168_device_u2ootg;
25extern struct platform_device pxa168_device_u2oehci;
23 26
24extern struct platform_device pxa910_device_gpio; 27extern struct platform_device pxa910_device_gpio;
25extern struct platform_device pxa910_device_rtc; 28extern struct platform_device pxa910_device_rtc;
diff --git a/arch/arm/mach-mmp/include/mach/regs-usb.h b/arch/arm/mach-mmp/include/mach/regs-usb.h
new file mode 100644
index 000000000000..b047bf487506
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-usb.h
@@ -0,0 +1,253 @@
1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __ASM_ARCH_REGS_USB_H
11#define __ASM_ARCH_REGS_USB_H
12
13#define PXA168_U2O_REGBASE (0xd4208000)
14#define PXA168_U2O_PHYBASE (0xd4207000)
15
16#define PXA168_U2H_REGBASE (0xd4209000)
17#define PXA168_U2H_PHYBASE (0xd4206000)
18
19#define MMP3_HSIC1_REGBASE (0xf0001000)
20#define MMP3_HSIC1_PHYBASE (0xf0001800)
21
22#define MMP3_HSIC2_REGBASE (0xf0002000)
23#define MMP3_HSIC2_PHYBASE (0xf0002800)
24
25#define MMP3_FSIC_REGBASE (0xf0003000)
26#define MMP3_FSIC_PHYBASE (0xf0003800)
27
28
29#define USB_REG_RANGE (0x1ff)
30#define USB_PHY_RANGE (0xff)
31
32/* registers */
33#define U2x_CAPREGS_OFFSET 0x100
34
35/* phy regs */
36#define UTMI_REVISION 0x0
37#define UTMI_CTRL 0x4
38#define UTMI_PLL 0x8
39#define UTMI_TX 0xc
40#define UTMI_RX 0x10
41#define UTMI_IVREF 0x14
42#define UTMI_T0 0x18
43#define UTMI_T1 0x1c
44#define UTMI_T2 0x20
45#define UTMI_T3 0x24
46#define UTMI_T4 0x28
47#define UTMI_T5 0x2c
48#define UTMI_RESERVE 0x30
49#define UTMI_USB_INT 0x34
50#define UTMI_DBG_CTL 0x38
51#define UTMI_OTG_ADDON 0x3c
52
53/* For UTMICTRL Register */
54#define UTMI_CTRL_USB_CLK_EN (1 << 31)
55/* pxa168 */
56#define UTMI_CTRL_SUSPEND_SET1 (1 << 30)
57#define UTMI_CTRL_SUSPEND_SET2 (1 << 29)
58#define UTMI_CTRL_RXBUF_PDWN (1 << 24)
59#define UTMI_CTRL_TXBUF_PDWN (1 << 11)
60
61#define UTMI_CTRL_INPKT_DELAY_SHIFT 30
62#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28
63#define UTMI_CTRL_PU_REF_SHIFT 20
64#define UTMI_CTRL_ARC_PULLDN_SHIFT 12
65#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1
66#define UTMI_CTRL_PWR_UP_SHIFT 0
67
68/* For UTMI_PLL Register */
69#define UTMI_PLL_PLLCALI12_SHIFT 29
70#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29)
71
72#define UTMI_PLL_PLLVDD18_SHIFT 27
73#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27)
74
75#define UTMI_PLL_PLLVDD12_SHIFT 25
76#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25)
77
78#define UTMI_PLL_CLK_BLK_EN_SHIFT 24
79#define CLK_BLK_EN (0x1 << 24)
80#define PLL_READY (0x1 << 23)
81#define KVCO_EXT (0x1 << 22)
82#define VCOCAL_START (0x1 << 21)
83
84#define UTMI_PLL_KVCO_SHIFT 15
85#define UTMI_PLL_KVCO_MASK (0x7 << 15)
86
87#define UTMI_PLL_ICP_SHIFT 12
88#define UTMI_PLL_ICP_MASK (0x7 << 12)
89
90#define UTMI_PLL_FBDIV_SHIFT 4
91#define UTMI_PLL_FBDIV_MASK (0xFF << 4)
92
93#define UTMI_PLL_REFDIV_SHIFT 0
94#define UTMI_PLL_REFDIV_MASK (0xF << 0)
95
96/* For UTMI_TX Register */
97#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27
98#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27)
99
100#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26
101#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26)
102
103#define UTMI_TX_TXVDD12_SHIFT 22
104#define UTMI_TX_TXVDD12_MASK (0x3 << 22)
105
106#define UTMI_TX_CK60_PHSEL_SHIFT 17
107#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17)
108
109#define UTMI_TX_IMPCAL_VTH_SHIFT 14
110#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14)
111
112#define REG_RCAL_START (0x1 << 12)
113
114#define UTMI_TX_LOW_VDD_EN_SHIFT 11
115
116#define UTMI_TX_AMP_SHIFT 0
117#define UTMI_TX_AMP_MASK (0x7 << 0)
118
119/* For UTMI_RX Register */
120#define UTMI_REG_SQ_LENGTH_SHIFT 15
121#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15)
122
123#define UTMI_RX_SQ_THRESH_SHIFT 4
124#define UTMI_RX_SQ_THRESH_MASK (0xf << 4)
125
126#define UTMI_OTG_ADDON_OTG_ON (1 << 0)
127
128/* For MMP3 USB Phy */
129#define USB2_PLL_REG0 0x4
130#define USB2_PLL_REG1 0x8
131#define USB2_TX_REG0 0x10
132#define USB2_TX_REG1 0x14
133#define USB2_TX_REG2 0x18
134#define USB2_RX_REG0 0x20
135#define USB2_RX_REG1 0x24
136#define USB2_RX_REG2 0x28
137#define USB2_ANA_REG0 0x30
138#define USB2_ANA_REG1 0x34
139#define USB2_ANA_REG2 0x38
140#define USB2_DIG_REG0 0x3C
141#define USB2_DIG_REG1 0x40
142#define USB2_DIG_REG2 0x44
143#define USB2_DIG_REG3 0x48
144#define USB2_TEST_REG0 0x4C
145#define USB2_TEST_REG1 0x50
146#define USB2_TEST_REG2 0x54
147#define USB2_CHARGER_REG0 0x58
148#define USB2_OTG_REG0 0x5C
149#define USB2_PHY_MON0 0x60
150#define USB2_RESETVE_REG0 0x64
151#define USB2_ICID_REG0 0x78
152#define USB2_ICID_REG1 0x7C
153
154/* USB2_PLL_REG0 */
155/* This is for Ax stepping */
156#define USB2_PLL_FBDIV_SHIFT_MMP3 0
157#define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0)
158
159#define USB2_PLL_REFDIV_SHIFT_MMP3 8
160#define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8)
161
162#define USB2_PLL_VDD12_SHIFT_MMP3 12
163#define USB2_PLL_VDD18_SHIFT_MMP3 14
164
165/* This is for B0 stepping */
166#define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0
167#define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9
168#define USB2_PLL_VDD18_SHIFT_MMP3_B0 14
169#define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF
170#define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00
171
172#define USB2_PLL_CAL12_SHIFT_MMP3 0
173#define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0)
174
175#define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2
176
177#define USB2_PLL_KVCO_SHIFT_MMP3 4
178#define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4)
179
180#define USB2_PLL_ICP_SHIFT_MMP3 8
181#define USB2_PLL_ICP_MASK_MMP3 (0x7<<8)
182
183#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12
184
185#define USB2_PLL_PU_PLL_SHIFT_MMP3 13
186#define USB2_PLL_PU_PLL_MASK (0x1 << 13)
187
188#define USB2_PLL_READY_MASK_MMP3 (0x1 << 15)
189
190/* USB2_TX_REG0 */
191#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8
192#define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8)
193
194#define USB2_TX_RCAL_START_SHIFT_MMP3 13
195
196/* USB2_TX_REG1 */
197#define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0
198#define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0)
199
200#define USB2_TX_AMP_SHIFT_MMP3 4
201#define USB2_TX_AMP_MASK_MMP3 (0x7 << 4)
202
203#define USB2_TX_VDD12_SHIFT_MMP3 8
204#define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8)
205
206/* USB2_TX_REG2 */
207#define USB2_TX_DRV_SLEWRATE_SHIFT 10
208
209/* USB2_RX_REG0 */
210#define USB2_RX_SQ_THRESH_SHIFT_MMP3 4
211#define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4)
212
213#define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10
214#define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10)
215
216/* USB2_ANA_REG1*/
217#define USB2_ANA_PU_ANA_SHIFT_MMP3 14
218
219/* USB2_OTG_REG0 */
220#define USB2_OTG_PU_OTG_SHIFT_MMP3 3
221
222/* fsic registers */
223#define FSIC_MISC 0x4
224#define FSIC_INT 0x28
225#define FSIC_CTRL 0x30
226
227/* HSIC registers */
228#define HSIC_PAD_CTRL 0x4
229
230#define HSIC_CTRL 0x8
231#define HSIC_CTRL_HSIC_ENABLE (1<<7)
232#define HSIC_CTRL_PLL_BYPASS (1<<4)
233
234#define TEST_GRP_0 0xc
235#define TEST_GRP_1 0x10
236
237#define HSIC_INT 0x14
238#define HSIC_INT_READY_INT_EN (1<<10)
239#define HSIC_INT_CONNECT_INT_EN (1<<9)
240#define HSIC_INT_CORE_INT_EN (1<<8)
241#define HSIC_INT_HS_READY (1<<2)
242#define HSIC_INT_CONNECT (1<<1)
243#define HSIC_INT_CORE (1<<0)
244
245#define HSIC_CONFIG 0x18
246#define USBHSIC_CTRL 0x20
247
248#define HSIC_USB_CTRL 0x28
249#define HSIC_USB_CTRL_CLKEN 1
250#define HSIC_USB_CLK_PHY 0x0
251#define HSIC_USB_CLK_PMU 0x1
252
253#endif /* __ASM_ARCH_PXA_U2O_H */
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index b24d2c32cba9..62d787c34475 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/platform_data/mv_usb.h>
17 18
18#include <asm/mach/time.h> 19#include <asm/mach/time.h>
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
@@ -27,6 +28,7 @@
27#include <mach/mfp.h> 28#include <mach/mfp.h>
28#include <linux/dma-mapping.h> 29#include <linux/dma-mapping.h>
29#include <mach/pxa168.h> 30#include <mach/pxa168.h>
31#include <mach/regs-usb.h>
30 32
31#include "common.h" 33#include "common.h"
32#include "clock.h" 34#include "clock.h"
@@ -93,7 +95,7 @@ static struct clk_lookup pxa168_clkregs[] = {
93 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), 95 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
94 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), 96 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
95 INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), 97 INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
96 INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"), 98 INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
97 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), 99 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
98}; 100};
99 101
@@ -184,17 +186,17 @@ struct platform_device pxa168_device_gpio = {
184struct resource pxa168_usb_host_resources[] = { 186struct resource pxa168_usb_host_resources[] = {
185 /* USB Host conroller register base */ 187 /* USB Host conroller register base */
186 [0] = { 188 [0] = {
187 .start = 0xd4209000, 189 .start = PXA168_U2H_REGBASE + U2x_CAPREGS_OFFSET,
188 .end = 0xd4209000 + 0x200, 190 .end = PXA168_U2H_REGBASE + USB_REG_RANGE,
189 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
190 .name = "pxa168-usb-host", 192 .name = "capregs",
191 }, 193 },
192 /* USB PHY register base */ 194 /* USB PHY register base */
193 [1] = { 195 [1] = {
194 .start = 0xd4206000, 196 .start = PXA168_U2H_PHYBASE,
195 .end = 0xd4206000 + 0xff, 197 .end = PXA168_U2H_PHYBASE + USB_PHY_RANGE,
196 .flags = IORESOURCE_MEM, 198 .flags = IORESOURCE_MEM,
197 .name = "pxa168-usb-phy", 199 .name = "phyregs",
198 }, 200 },
199 [2] = { 201 [2] = {
200 .start = IRQ_PXA168_USB2, 202 .start = IRQ_PXA168_USB2,
@@ -205,7 +207,7 @@ struct resource pxa168_usb_host_resources[] = {
205 207
206static u64 pxa168_usb_host_dmamask = DMA_BIT_MASK(32); 208static u64 pxa168_usb_host_dmamask = DMA_BIT_MASK(32);
207struct platform_device pxa168_device_usb_host = { 209struct platform_device pxa168_device_usb_host = {
208 .name = "pxa168-ehci", 210 .name = "pxa-sph",
209 .id = -1, 211 .id = -1,
210 .dev = { 212 .dev = {
211 .dma_mask = &pxa168_usb_host_dmamask, 213 .dma_mask = &pxa168_usb_host_dmamask,
@@ -216,7 +218,7 @@ struct platform_device pxa168_device_usb_host = {
216 .resource = pxa168_usb_host_resources, 218 .resource = pxa168_usb_host_resources,
217}; 219};
218 220
219int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata) 221int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
220{ 222{
221 pxa168_device_usb_host.dev.platform_data = pdata; 223 pxa168_device_usb_host.dev.platform_data = pdata;
222 return platform_device_register(&pxa168_device_usb_host); 224 return platform_device_register(&pxa168_device_usb_host);
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 43f8bcc29b67..6da52e9f2bdc 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -109,7 +109,7 @@ static struct clk_lookup pxa910_clkregs[] = {
109 INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), 109 INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
110 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), 110 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
111 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), 111 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
112 INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"), 112 INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
113 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), 113 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
114}; 114};
115 115
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 3fc9ed21f97d..266215393f44 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -17,6 +17,7 @@
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/i2c/pca953x.h> 18#include <linux/i2c/pca953x.h>
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/platform_data/mv_usb.h>
20 21
21#include <asm/mach-types.h> 22#include <asm/mach-types.h>
22#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
@@ -25,6 +26,7 @@
25#include <mach/mfp-pxa910.h> 26#include <mach/mfp-pxa910.h>
26#include <mach/pxa910.h> 27#include <mach/pxa910.h>
27#include <mach/irqs.h> 28#include <mach/irqs.h>
29#include <mach/regs-usb.h>
28 30
29#include "common.h" 31#include "common.h"
30 32
@@ -144,6 +146,26 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = {
144 }, 146 },
145}; 147};
146 148
149#ifdef CONFIG_USB_SUPPORT
150#if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV_U2O)
151
152static char *pxa910_usb_clock_name[] = {
153 [0] = "U2OCLK",
154};
155
156static struct mv_usb_platform_data ttc_usb_pdata = {
157 .clknum = 1,
158 .clkname = pxa910_usb_clock_name,
159 .vbus = NULL,
160 .mode = MV_USB_MODE_OTG,
161 .otg_force_a_bus_req = 1,
162 .phy_init = pxa_usb_phy_init,
163 .phy_deinit = pxa_usb_phy_deinit,
164 .set_vbus = NULL,
165};
166#endif
167#endif
168
147static void __init ttc_dkb_init(void) 169static void __init ttc_dkb_init(void)
148{ 170{
149 mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config)); 171 mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
@@ -154,6 +176,21 @@ static void __init ttc_dkb_init(void)
154 /* off-chip devices */ 176 /* off-chip devices */
155 pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info)); 177 pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
156 platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices)); 178 platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
179
180#ifdef CONFIG_USB_MV_UDC
181 pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata;
182 platform_device_register(&pxa168_device_u2o);
183#endif
184
185#ifdef CONFIG_USB_EHCI_MV_U2O
186 pxa168_device_u2oehci.dev.platform_data = &ttc_usb_pdata;
187 platform_device_register(&pxa168_device_u2oehci);
188#endif
189
190#ifdef CONFIG_USB_MV_OTG
191 pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
192 platform_device_register(&pxa168_device_u2ootg);
193#endif
157} 194}
158 195
159MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") 196MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index b83b95a29503..6bd692d271c1 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -102,6 +102,10 @@ static unsigned long hx4700_pin_config[] __initdata = {
102 GPIO44_BTUART_CTS, 102 GPIO44_BTUART_CTS,
103 GPIO45_BTUART_RTS_LPM_LOW, 103 GPIO45_BTUART_RTS_LPM_LOW,
104 104
105 /* STUART (IRDA) */
106 GPIO46_STUART_RXD,
107 GPIO47_STUART_TXD,
108
105 /* PWM 1 (Backlight) */ 109 /* PWM 1 (Backlight) */
106 GPIO17_PWM1_OUT, 110 GPIO17_PWM1_OUT,
107 111
@@ -125,7 +129,7 @@ static unsigned long hx4700_pin_config[] __initdata = {
125 GPIO88_GPIO, 129 GPIO88_GPIO,
126 130
127 /* HX4700 specific input GPIOs */ 131 /* HX4700 specific input GPIOs */
128 GPIO12_GPIO, /* ASIC3_IRQ */ 132 GPIO12_GPIO | WAKEUP_ON_EDGE_RISE, /* ASIC3_IRQ */
129 GPIO13_GPIO, /* W3220_IRQ */ 133 GPIO13_GPIO, /* W3220_IRQ */
130 GPIO14_GPIO, /* nWLAN_IRQ */ 134 GPIO14_GPIO, /* nWLAN_IRQ */
131 135
@@ -227,7 +231,6 @@ static u16 asic3_gpio_config[] = {
227 ASIC3_GPIOC0_LED0, /* red */ 231 ASIC3_GPIOC0_LED0, /* red */
228 ASIC3_GPIOC1_LED1, /* green */ 232 ASIC3_GPIOC1_LED1, /* green */
229 ASIC3_GPIOC2_LED2, /* blue */ 233 ASIC3_GPIOC2_LED2, /* blue */
230 ASIC3_GPIOC4_CF_nCD,
231 ASIC3_GPIOC5_nCIOW, 234 ASIC3_GPIOC5_nCIOW,
232 ASIC3_GPIOC6_nCIOR, 235 ASIC3_GPIOC6_nCIOR,
233 ASIC3_GPIOC7_nPCE_1, 236 ASIC3_GPIOC7_nPCE_1,
@@ -241,6 +244,7 @@ static u16 asic3_gpio_config[] = {
241 ASIC3_GPIOC15_nPIOR, 244 ASIC3_GPIOC15_nPIOR,
242 245
243 /* GPIOD: input GPIOs, CF */ 246 /* GPIOD: input GPIOs, CF */
247 ASIC3_GPIOD4_CF_nCD,
244 ASIC3_GPIOD11_nCIOIS16, 248 ASIC3_GPIOD11_nCIOIS16,
245 ASIC3_GPIOD12_nCWAIT, 249 ASIC3_GPIOD12_nCWAIT,
246 ASIC3_GPIOD15_nPIOW, 250 ASIC3_GPIOD15_nPIOW,
@@ -291,6 +295,7 @@ static struct asic3_platform_data asic3_platform_data = {
291 .gpio_config_num = ARRAY_SIZE(asic3_gpio_config), 295 .gpio_config_num = ARRAY_SIZE(asic3_gpio_config),
292 .irq_base = IRQ_BOARD_START, 296 .irq_base = IRQ_BOARD_START,
293 .gpio_base = HX4700_ASIC3_GPIO_BASE, 297 .gpio_base = HX4700_ASIC3_GPIO_BASE,
298 .clock_rate = 4000000,
294 .leds = asic3_leds, 299 .leds = asic3_leds,
295}; 300};
296 301
@@ -859,6 +864,7 @@ static void __init hx4700_init(void)
859 int ret; 864 int ret;
860 865
861 pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config)); 866 pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
867 gpio_set_wake(GPIO12_HX4700_ASIC3_IRQ, 1);
862 ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios)); 868 ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
863 if (ret) 869 if (ret)
864 pr_err ("hx4700: Failed to request GPIOs.\n"); 870 pr_err ("hx4700: Failed to request GPIOs.\n");
diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h
index 02868447b0b1..e57f5c724e8a 100644
--- a/arch/arm/mach-pxa/include/mach/mioa701.h
+++ b/arch/arm/mach-pxa/include/mach/mioa701.h
@@ -61,6 +61,9 @@
61#define GPIO93_KEY_VOLUME_UP 93 61#define GPIO93_KEY_VOLUME_UP 93
62#define GPIO94_KEY_VOLUME_DOWN 94 62#define GPIO94_KEY_VOLUME_DOWN 94
63 63
64/* Camera */
65#define GPIO56_MT9M111_nOE 56
66
64extern struct input_dev *mioa701_evdev; 67extern struct input_dev *mioa701_evdev;
65extern void mioa701_gpio_lpm_set(unsigned long mfp_pin); 68extern void mioa701_gpio_lpm_set(unsigned long mfp_pin);
66 69
diff --git a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
index d72791695b26..0260aaa2fc17 100644
--- a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
+++ b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
@@ -31,7 +31,6 @@
31#define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO) 31#define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO)
32#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING 32#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING
33#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ 33#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
34#define PCM990_CTRL_BASE 0xea000000
35#define PCM990_CTRL_SIZE (1*1024*1024) 34#define PCM990_CTRL_SIZE (1*1024*1024)
36 35
37#define PCM990_CTRL_PWR_IRQ_GPIO 14 36#define PCM990_CTRL_PWR_IRQ_GPIO 14
@@ -69,13 +68,13 @@
69#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ 68#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */
70#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ 69#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */
71 70
72#define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */ 71#define PCM990_CTRL_INTSETCLR 0x000C /* Interrupt Clear REGISTER */
73#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */ 72#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */
74#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */ 73#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */
75#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */ 74#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */
76#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */ 75#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */
77 76
78#define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */ 77#define PCM990_CTRL_INTMSKENA 0x000E /* Interrupt Enable REGISTER */
79#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */ 78#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */
80#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */ 79#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */
81#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */ 80#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */
@@ -102,32 +101,6 @@
102#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */ 101#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */
103#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */ 102#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */
104 103
105#define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
106#define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
107
108#ifndef __ASSEMBLY__
109# define __PCM990_CTRL_REG(x) \
110 (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
111#else
112# define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x)
113#endif
114
115#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
116#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
117#define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
118#define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
119#define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
120#define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
121#define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
122#define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
123#define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
124#define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
125#define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
126#define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
127#define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
128#define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
129
130
131/* 104/*
132 * IDE 105 * IDE
133 */ 106 */
@@ -166,24 +139,6 @@
166#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE) 139#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
167#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS) 140#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
168 141
169#ifndef __ASSEMBLY__
170# define __PCM990_IDE_PLD_REG(x) \
171 (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
172#else
173# define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x)
174#endif
175
176#define PCM990_IDE0 \
177 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
178#define PCM990_IDE1 \
179 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
180#define PCM990_IDE2 \
181 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
182#define PCM990_IDE3 \
183 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
184#define PCM990_IDE4 \
185 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
186
187/* 142/*
188 * Compact Flash 143 * Compact Flash
189 */ 144 */
@@ -196,10 +151,6 @@
196#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING 151#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING
197 152
198#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ 153#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
199#define PCM990_CF_PLD_BASE 0xef000000
200#define PCM990_CF_PLD_SIZE (1*1024*1024)
201#define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
202#define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
203 154
204/* visible CPLD (U6) registers */ 155/* visible CPLD (U6) registers */
205#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */ 156#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */
@@ -239,21 +190,6 @@
239#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ 190#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */
240#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ 191#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */
241 192
242#ifndef __ASSEMBLY__
243# define __PCM990_CF_PLD_REG(x) \
244 (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
245#else
246# define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x)
247#endif
248
249#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
250#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
251#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
252#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
253#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
254#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
255#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
256
257/* 193/*
258 * Wolfson AC97 Touch 194 * Wolfson AC97 Touch
259 */ 195 */
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 061d57009cee..929c62b47b76 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -103,6 +103,7 @@ static unsigned long mioa701_pin_config[] = {
103 GPIO82_CIF_DD_5, 103 GPIO82_CIF_DD_5,
104 GPIO84_CIF_FV, 104 GPIO84_CIF_FV,
105 GPIO85_CIF_LV, 105 GPIO85_CIF_LV,
106 MIO_CFG_OUT(GPIO56_MT9M111_nOE, AF0, DRIVE_LOW),
106 107
107 /* Bluetooth */ 108 /* Bluetooth */
108 MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0), 109 MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0),
@@ -705,6 +706,7 @@ static struct gpio global_gpios[] = {
705 { GPIO9_CHARGE_EN, GPIOF_OUT_INIT_HIGH, "Charger enable" }, 706 { GPIO9_CHARGE_EN, GPIOF_OUT_INIT_HIGH, "Charger enable" },
706 { GPIO18_POWEROFF, GPIOF_OUT_INIT_LOW, "Power Off" }, 707 { GPIO18_POWEROFF, GPIOF_OUT_INIT_LOW, "Power Off" },
707 { GPIO87_LCD_POWER, GPIOF_OUT_INIT_LOW, "LCD Power" }, 708 { GPIO87_LCD_POWER, GPIOF_OUT_INIT_LOW, "LCD Power" },
709 { GPIO56_MT9M111_nOE, GPIOF_OUT_INIT_LOW, "Camera nOE" },
708}; 710};
709 711
710static void __init mioa701_machine_init(void) 712static void __init mioa701_machine_init(void)
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index abab4e2b122c..cb723e84bc27 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -65,6 +65,18 @@ static unsigned long pcm990_pin_config[] __initdata = {
65 GPIO31_AC97_SYNC, 65 GPIO31_AC97_SYNC,
66}; 66};
67 67
68static void __iomem *pcm990_cpld_base;
69
70static u8 pcm990_cpld_readb(unsigned int reg)
71{
72 return readb(pcm990_cpld_base + reg);
73}
74
75static void pcm990_cpld_writeb(u8 value, unsigned int reg)
76{
77 writeb(value, pcm990_cpld_base + reg);
78}
79
68/* 80/*
69 * pcm990_lcd_power - control power supply to the LCD 81 * pcm990_lcd_power - control power supply to the LCD
70 * @on: 0 = switch off, 1 = switch on 82 * @on: 0 = switch off, 1 = switch on
@@ -78,13 +90,13 @@ static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
78 /* enable LCD-Latches 90 /* enable LCD-Latches
79 * power on LCD 91 * power on LCD
80 */ 92 */
81 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) = 93 pcm990_cpld_writeb(PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON,
82 PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON; 94 PCM990_CTRL_REG3);
83 } else { 95 } else {
84 /* disable LCD-Latches 96 /* disable LCD-Latches
85 * power off LCD 97 * power off LCD
86 */ 98 */
87 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) = 0x00; 99 pcm990_cpld_writeb(0, PCM990_CTRL_REG3);
88 } 100 }
89} 101}
90#endif 102#endif
@@ -243,15 +255,26 @@ static unsigned long pcm990_irq_enabled;
243static void pcm990_mask_ack_irq(struct irq_data *d) 255static void pcm990_mask_ack_irq(struct irq_data *d)
244{ 256{
245 int pcm990_irq = (d->irq - PCM027_IRQ(0)); 257 int pcm990_irq = (d->irq - PCM027_IRQ(0));
246 PCM990_INTMSKENA = (pcm990_irq_enabled &= ~(1 << pcm990_irq)); 258
259 pcm990_irq_enabled &= ~(1 << pcm990_irq);
260
261 pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
247} 262}
248 263
249static void pcm990_unmask_irq(struct irq_data *d) 264static void pcm990_unmask_irq(struct irq_data *d)
250{ 265{
251 int pcm990_irq = (d->irq - PCM027_IRQ(0)); 266 int pcm990_irq = (d->irq - PCM027_IRQ(0));
267 u8 val;
268
252 /* the irq can be acknowledged only if deasserted, so it's done here */ 269 /* the irq can be acknowledged only if deasserted, so it's done here */
253 PCM990_INTSETCLR |= 1 << pcm990_irq; 270
254 PCM990_INTMSKENA = (pcm990_irq_enabled |= (1 << pcm990_irq)); 271 pcm990_irq_enabled |= (1 << pcm990_irq);
272
273 val = pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
274 val |= 1 << pcm990_irq;
275 pcm990_cpld_writeb(val, PCM990_CTRL_INTSETCLR);
276
277 pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
255} 278}
256 279
257static struct irq_chip pcm990_irq_chip = { 280static struct irq_chip pcm990_irq_chip = {
@@ -261,7 +284,10 @@ static struct irq_chip pcm990_irq_chip = {
261 284
262static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc) 285static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
263{ 286{
264 unsigned long pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled; 287 unsigned long pending;
288
289 pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
290 pending &= pcm990_irq_enabled;
265 291
266 do { 292 do {
267 /* clear our parent IRQ */ 293 /* clear our parent IRQ */
@@ -270,7 +296,8 @@ static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
270 irq = PCM027_IRQ(0) + __ffs(pending); 296 irq = PCM027_IRQ(0) + __ffs(pending);
271 generic_handle_irq(irq); 297 generic_handle_irq(irq);
272 } 298 }
273 pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled; 299 pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
300 pending &= pcm990_irq_enabled;
274 } while (pending); 301 } while (pending);
275} 302}
276 303
@@ -285,8 +312,9 @@ static void __init pcm990_init_irq(void)
285 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 312 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
286 } 313 }
287 314
288 PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ 315 /* disable all Interrupts */
289 PCM990_INTSETCLR = 0xFF; 316 pcm990_cpld_writeb(0x0, PCM990_CTRL_INTMSKENA);
317 pcm990_cpld_writeb(0xff, PCM990_CTRL_INTSETCLR);
290 318
291 irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); 319 irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
292 irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); 320 irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
@@ -309,13 +337,16 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
309static void pcm990_mci_setpower(struct device *dev, unsigned int vdd) 337static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
310{ 338{
311 struct pxamci_platform_data *p_d = dev->platform_data; 339 struct pxamci_platform_data *p_d = dev->platform_data;
340 u8 val;
341
342 val = pcm990_cpld_readb(PCM990_CTRL_REG5);
312 343
313 if ((1 << vdd) & p_d->ocr_mask) 344 if ((1 << vdd) & p_d->ocr_mask)
314 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) = 345 val |= PCM990_CTRL_MMC2PWR;
315 PCM990_CTRL_MMC2PWR;
316 else 346 else
317 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) = 347 val &= ~PCM990_CTRL_MMC2PWR;
318 ~PCM990_CTRL_MMC2PWR; 348
349 pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
319} 350}
320 351
321static void pcm990_mci_exit(struct device *dev, void *data) 352static void pcm990_mci_exit(struct device *dev, void *data)
@@ -481,23 +512,6 @@ static struct platform_device pcm990_camera[] = {
481#endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */ 512#endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */
482 513
483/* 514/*
484 * enable generic access to the base board control CPLDs U6 and U7
485 */
486static struct map_desc pcm990_io_desc[] __initdata = {
487 {
488 .virtual = PCM990_CTRL_BASE,
489 .pfn = __phys_to_pfn(PCM990_CTRL_PHYS),
490 .length = PCM990_CTRL_SIZE,
491 .type = MT_DEVICE /* CPLD */
492 }, {
493 .virtual = PCM990_CF_PLD_BASE,
494 .pfn = __phys_to_pfn(PCM990_CF_PLD_PHYS),
495 .length = PCM990_CF_PLD_SIZE,
496 .type = MT_DEVICE /* CPLD */
497 }
498};
499
500/*
501 * system init for baseboard usage. Will be called by pcm027 init. 515 * system init for baseboard usage. Will be called by pcm027 init.
502 * 516 *
503 * Add platform devices present on this baseboard and init 517 * Add platform devices present on this baseboard and init
@@ -507,8 +521,11 @@ void __init pcm990_baseboard_init(void)
507{ 521{
508 pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_pin_config)); 522 pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_pin_config));
509 523
510 /* register CPLD access */ 524 pcm990_cpld_base = ioremap(PCM990_CTRL_PHYS, PCM990_CTRL_SIZE);
511 iotable_init(ARRAY_AND_SIZE(pcm990_io_desc)); 525 if (!pcm990_cpld_base) {
526 pr_err("pcm990: failed to ioremap cpld\n");
527 return;
528 }
512 529
513 /* register CPLD's IRQ controller */ 530 /* register CPLD's IRQ controller */
514 pcm990_init_irq(); 531 pcm990_init_irq();
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index bba3ab2066ee..8fd255f7ee40 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -217,7 +217,7 @@ config PCMCIA_PXA2XX
217 || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \ 217 || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \
218 || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \ 218 || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \
219 || MACH_VPAC270 || MACH_BALLOON3 || MACH_COLIBRI \ 219 || MACH_VPAC270 || MACH_BALLOON3 || MACH_COLIBRI \
220 || MACH_COLIBRI320) 220 || MACH_COLIBRI320 || MACH_H4700)
221 select PCMCIA_SA1111 if ARCH_LUBBOCK && SA1111 221 select PCMCIA_SA1111 if ARCH_LUBBOCK && SA1111
222 select PCMCIA_SOC_COMMON 222 select PCMCIA_SOC_COMMON
223 help 223 help
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 47525de6a631..7745b512a87c 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -69,6 +69,7 @@ pxa2xx-obj-$(CONFIG_MACH_VPAC270) += pxa2xx_vpac270.o
69pxa2xx-obj-$(CONFIG_MACH_BALLOON3) += pxa2xx_balloon3.o 69pxa2xx-obj-$(CONFIG_MACH_BALLOON3) += pxa2xx_balloon3.o
70pxa2xx-obj-$(CONFIG_MACH_COLIBRI) += pxa2xx_colibri.o 70pxa2xx-obj-$(CONFIG_MACH_COLIBRI) += pxa2xx_colibri.o
71pxa2xx-obj-$(CONFIG_MACH_COLIBRI320) += pxa2xx_colibri.o 71pxa2xx-obj-$(CONFIG_MACH_COLIBRI320) += pxa2xx_colibri.o
72pxa2xx-obj-$(CONFIG_MACH_H4700) += pxa2xx_hx4700.o
72 73
73obj-$(CONFIG_PCMCIA_PXA2XX) += pxa2xx_base.o $(pxa2xx-obj-y) 74obj-$(CONFIG_PCMCIA_PXA2XX) += pxa2xx_base.o $(pxa2xx-obj-y)
74 75
diff --git a/drivers/pcmcia/pxa2xx_hx4700.c b/drivers/pcmcia/pxa2xx_hx4700.c
new file mode 100644
index 000000000000..7dfef3ee5b53
--- /dev/null
+++ b/drivers/pcmcia/pxa2xx_hx4700.c
@@ -0,0 +1,121 @@
1/*
2 * Copyright (C) 2012 Paul Parsons <lost.distance@yahoo.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/err.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14
15#include <asm/mach-types.h>
16#include <mach/hx4700.h>
17
18#include "soc_common.h"
19
20static struct gpio gpios[] = {
21 { GPIO114_HX4700_CF_RESET, GPIOF_OUT_INIT_LOW, "CF reset" },
22 { EGPIO4_CF_3V3_ON, GPIOF_OUT_INIT_LOW, "CF 3.3V enable" },
23};
24
25static int hx4700_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
26{
27 int ret;
28
29 ret = gpio_request_array(gpios, ARRAY_SIZE(gpios));
30 if (ret)
31 goto out;
32
33 /*
34 * IRQ type must be set before soc_pcmcia_hw_init() calls request_irq().
35 * The asic3 default IRQ type is level trigger low level detect, exactly
36 * the the signal present on GPIOD4_CF_nCD when a CF card is inserted.
37 * If the IRQ type is not changed, the asic3 interrupt handler will loop
38 * repeatedly because it is unable to clear the level trigger interrupt.
39 */
40 irq_set_irq_type(gpio_to_irq(GPIOD4_CF_nCD), IRQ_TYPE_EDGE_BOTH);
41
42 skt->stat[SOC_STAT_CD].gpio = GPIOD4_CF_nCD;
43 skt->stat[SOC_STAT_CD].name = "PCMCIA CD";
44 skt->stat[SOC_STAT_RDY].gpio = GPIO60_HX4700_CF_RNB;
45 skt->stat[SOC_STAT_RDY].name = "PCMCIA Ready";
46
47out:
48 return ret;
49}
50
51static void hx4700_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
52{
53 gpio_free_array(gpios, ARRAY_SIZE(gpios));
54}
55
56static void hx4700_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
57 struct pcmcia_state *state)
58{
59 state->vs_3v = 1;
60 state->vs_Xv = 0;
61}
62
63static int hx4700_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
64 const socket_state_t *state)
65{
66 switch (state->Vcc) {
67 case 0:
68 gpio_set_value(EGPIO4_CF_3V3_ON, 0);
69 break;
70 case 33:
71 gpio_set_value(EGPIO4_CF_3V3_ON, 1);
72 break;
73 default:
74 printk(KERN_ERR "pcmcia: Unsupported Vcc: %d\n", state->Vcc);
75 return -EINVAL;
76 }
77
78 gpio_set_value(GPIO114_HX4700_CF_RESET, (state->flags & SS_RESET) != 0);
79
80 return 0;
81}
82
83static struct pcmcia_low_level hx4700_pcmcia_ops = {
84 .owner = THIS_MODULE,
85 .nr = 1,
86 .hw_init = hx4700_pcmcia_hw_init,
87 .hw_shutdown = hx4700_pcmcia_hw_shutdown,
88 .socket_state = hx4700_pcmcia_socket_state,
89 .configure_socket = hx4700_pcmcia_configure_socket,
90};
91
92static struct platform_device *hx4700_pcmcia_device;
93
94static int __init hx4700_pcmcia_init(void)
95{
96 struct platform_device *pdev;
97
98 if (!machine_is_h4700())
99 return -ENODEV;
100
101 pdev = platform_device_register_data(NULL, "pxa2xx-pcmcia", -1,
102 &hx4700_pcmcia_ops, sizeof(hx4700_pcmcia_ops));
103 if (IS_ERR(pdev))
104 return PTR_ERR(pdev);
105
106 hx4700_pcmcia_device = pdev;
107
108 return 0;
109}
110
111static void __exit hx4700_pcmcia_exit(void)
112{
113 platform_device_unregister(hx4700_pcmcia_device);
114}
115
116module_init(hx4700_pcmcia_init);
117module_exit(hx4700_pcmcia_exit);
118
119MODULE_AUTHOR("Paul Parsons <lost.distance@yahoo.com>");
120MODULE_DESCRIPTION("HP iPAQ hx4700 PCMCIA driver");
121MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index ed793b77a1c5..ef6faa5cee46 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -138,6 +138,7 @@ struct asic3_platform_data {
138#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0) 138#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
139#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0) 139#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
140#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0) 140#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
141#define ASIC3_GPIOD4_CF_nCD ASIC3_CONFIG_GPIO(52, 1, 0, 0)
141#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0) 142#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
142#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0) 143#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
143#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0) 144#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 16:15:23 -0500