diff options
176 files changed, 3948 insertions, 3104 deletions
diff --git a/Documentation/devicetree/bindings/video/atmel,lcdc.txt b/Documentation/devicetree/bindings/video/atmel,lcdc.txt new file mode 100644 index 000000000000..1ec175eddca8 --- /dev/null +++ b/Documentation/devicetree/bindings/video/atmel,lcdc.txt | |||
@@ -0,0 +1,75 @@ | |||
1 | Atmel LCDC Framebuffer | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : | ||
6 | "atmel,at91sam9261-lcdc" , | ||
7 | "atmel,at91sam9263-lcdc" , | ||
8 | "atmel,at91sam9g10-lcdc" , | ||
9 | "atmel,at91sam9g45-lcdc" , | ||
10 | "atmel,at91sam9g45es-lcdc" , | ||
11 | "atmel,at91sam9rl-lcdc" , | ||
12 | "atmel,at32ap-lcdc" | ||
13 | - reg : Should contain 1 register ranges(address and length) | ||
14 | - interrupts : framebuffer controller interrupt | ||
15 | - display: a phandle pointing to the display node | ||
16 | |||
17 | Required nodes: | ||
18 | - display: a display node is required to initialize the lcd panel | ||
19 | This should be in the board dts. | ||
20 | - default-mode: a videomode within the display with timing parameters | ||
21 | as specified below. | ||
22 | |||
23 | Example: | ||
24 | |||
25 | fb0: fb@0x00500000 { | ||
26 | compatible = "atmel,at91sam9g45-lcdc"; | ||
27 | reg = <0x00500000 0x1000>; | ||
28 | interrupts = <23 3 0>; | ||
29 | pinctrl-names = "default"; | ||
30 | pinctrl-0 = <&pinctrl_fb>; | ||
31 | display = <&display0>; | ||
32 | status = "okay"; | ||
33 | #address-cells = <1>; | ||
34 | #size-cells = <1>; | ||
35 | |||
36 | }; | ||
37 | |||
38 | Atmel LCDC Display | ||
39 | ----------------------------------------------------- | ||
40 | Required properties (as per of_videomode_helper): | ||
41 | |||
42 | - atmel,dmacon: dma controler configuration | ||
43 | - atmel,lcdcon2: lcd controler configuration | ||
44 | - atmel,guard-time: lcd guard time (Delay in frame periods) | ||
45 | - bits-per-pixel: lcd panel bit-depth. | ||
46 | |||
47 | Optional properties (as per of_videomode_helper): | ||
48 | - atmel,lcdcon-backlight: enable backlight | ||
49 | - atmel,lcd-wiring-mode: lcd wiring mode "RGB" or "BRG" | ||
50 | - atmel,power-control-gpio: gpio to power on or off the LCD (as many as needed) | ||
51 | |||
52 | Example: | ||
53 | display0: display { | ||
54 | bits-per-pixel = <32>; | ||
55 | atmel,lcdcon-backlight; | ||
56 | atmel,dmacon = <0x1>; | ||
57 | atmel,lcdcon2 = <0x80008002>; | ||
58 | atmel,guard-time = <9>; | ||
59 | atmel,lcd-wiring-mode = <1>; | ||
60 | |||
61 | display-timings { | ||
62 | native-mode = <&timing0>; | ||
63 | timing0: timing0 { | ||
64 | clock-frequency = <9000000>; | ||
65 | hactive = <480>; | ||
66 | vactive = <272>; | ||
67 | hback-porch = <1>; | ||
68 | hfront-porch = <1>; | ||
69 | vback-porch = <40>; | ||
70 | vfront-porch = <1>; | ||
71 | hsync-len = <45>; | ||
72 | vsync-len = <1>; | ||
73 | }; | ||
74 | }; | ||
75 | }; | ||
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 629ea5fc95cf..b2a34740146a 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c | |||
@@ -465,7 +465,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | |||
465 | 465 | ||
466 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) | 466 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) |
467 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); | 467 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); |
468 | static struct atmel_lcdfb_info lcdc_data; | 468 | static struct atmel_lcdfb_pdata lcdc_data; |
469 | 469 | ||
470 | static struct resource lcdc_resources[] = { | 470 | static struct resource lcdc_resources[] = { |
471 | [0] = { | 471 | [0] = { |
@@ -498,7 +498,7 @@ static struct platform_device at91_lcdc_device = { | |||
498 | .num_resources = ARRAY_SIZE(lcdc_resources), | 498 | .num_resources = ARRAY_SIZE(lcdc_resources), |
499 | }; | 499 | }; |
500 | 500 | ||
501 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | 501 | void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) |
502 | { | 502 | { |
503 | if (!data) { | 503 | if (!data) { |
504 | return; | 504 | return; |
@@ -559,7 +559,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | |||
559 | platform_device_register(&at91_lcdc_device); | 559 | platform_device_register(&at91_lcdc_device); |
560 | } | 560 | } |
561 | #else | 561 | #else |
562 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} | 562 | void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {} |
563 | #endif | 563 | #endif |
564 | 564 | ||
565 | 565 | ||
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 858c8aac2daf..4aeadddbc181 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
@@ -832,7 +832,7 @@ void __init at91_add_device_can(struct at91_can_data *data) {} | |||
832 | 832 | ||
833 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) | 833 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) |
834 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); | 834 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); |
835 | static struct atmel_lcdfb_info lcdc_data; | 835 | static struct atmel_lcdfb_pdata lcdc_data; |
836 | 836 | ||
837 | static struct resource lcdc_resources[] = { | 837 | static struct resource lcdc_resources[] = { |
838 | [0] = { | 838 | [0] = { |
@@ -859,7 +859,7 @@ static struct platform_device at91_lcdc_device = { | |||
859 | .num_resources = ARRAY_SIZE(lcdc_resources), | 859 | .num_resources = ARRAY_SIZE(lcdc_resources), |
860 | }; | 860 | }; |
861 | 861 | ||
862 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | 862 | void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) |
863 | { | 863 | { |
864 | if (!data) | 864 | if (!data) |
865 | return; | 865 | return; |
@@ -891,7 +891,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | |||
891 | platform_device_register(&at91_lcdc_device); | 891 | platform_device_register(&at91_lcdc_device); |
892 | } | 892 | } |
893 | #else | 893 | #else |
894 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} | 894 | void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {} |
895 | #endif | 895 | #endif |
896 | 896 | ||
897 | 897 | ||
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index acb703e13331..cb36fa872d30 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c | |||
@@ -965,7 +965,7 @@ void __init at91_add_device_isi(struct isi_platform_data *data, | |||
965 | 965 | ||
966 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) | 966 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) |
967 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); | 967 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); |
968 | static struct atmel_lcdfb_info lcdc_data; | 968 | static struct atmel_lcdfb_pdata lcdc_data; |
969 | 969 | ||
970 | static struct resource lcdc_resources[] = { | 970 | static struct resource lcdc_resources[] = { |
971 | [0] = { | 971 | [0] = { |
@@ -991,7 +991,7 @@ static struct platform_device at91_lcdc_device = { | |||
991 | .num_resources = ARRAY_SIZE(lcdc_resources), | 991 | .num_resources = ARRAY_SIZE(lcdc_resources), |
992 | }; | 992 | }; |
993 | 993 | ||
994 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | 994 | void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) |
995 | { | 995 | { |
996 | if (!data) | 996 | if (!data) |
997 | return; | 997 | return; |
@@ -1037,7 +1037,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | |||
1037 | platform_device_register(&at91_lcdc_device); | 1037 | platform_device_register(&at91_lcdc_device); |
1038 | } | 1038 | } |
1039 | #else | 1039 | #else |
1040 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} | 1040 | void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {} |
1041 | #endif | 1041 | #endif |
1042 | 1042 | ||
1043 | 1043 | ||
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index 352468f265a9..a698bdab2cce 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c | |||
@@ -498,7 +498,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} | |||
498 | 498 | ||
499 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) | 499 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) |
500 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); | 500 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); |
501 | static struct atmel_lcdfb_info lcdc_data; | 501 | static struct atmel_lcdfb_pdata lcdc_data; |
502 | 502 | ||
503 | static struct resource lcdc_resources[] = { | 503 | static struct resource lcdc_resources[] = { |
504 | [0] = { | 504 | [0] = { |
@@ -525,7 +525,7 @@ static struct platform_device at91_lcdc_device = { | |||
525 | .num_resources = ARRAY_SIZE(lcdc_resources), | 525 | .num_resources = ARRAY_SIZE(lcdc_resources), |
526 | }; | 526 | }; |
527 | 527 | ||
528 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | 528 | void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) |
529 | { | 529 | { |
530 | if (!data) { | 530 | if (!data) { |
531 | return; | 531 | return; |
@@ -557,7 +557,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | |||
557 | platform_device_register(&at91_lcdc_device); | 557 | platform_device_register(&at91_lcdc_device); |
558 | } | 558 | } |
559 | #else | 559 | #else |
560 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} | 560 | void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {} |
561 | #endif | 561 | #endif |
562 | 562 | ||
563 | 563 | ||
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index d3437624ca4e..473546b9408b 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c | |||
@@ -389,7 +389,7 @@ static struct fb_monspecs at91fb_default_stn_monspecs = { | |||
389 | | ATMEL_LCDC_IFWIDTH_4 \ | 389 | | ATMEL_LCDC_IFWIDTH_4 \ |
390 | | ATMEL_LCDC_SCANMOD_SINGLE) | 390 | | ATMEL_LCDC_SCANMOD_SINGLE) |
391 | 391 | ||
392 | static void at91_lcdc_stn_power_control(int on) | 392 | static void at91_lcdc_stn_power_control(struct atmel_lcdfb_pdata *pdata, int on) |
393 | { | 393 | { |
394 | /* backlight */ | 394 | /* backlight */ |
395 | if (on) { /* power up */ | 395 | if (on) { /* power up */ |
@@ -401,7 +401,7 @@ static void at91_lcdc_stn_power_control(int on) | |||
401 | } | 401 | } |
402 | } | 402 | } |
403 | 403 | ||
404 | static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | 404 | static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { |
405 | .default_bpp = 1, | 405 | .default_bpp = 1, |
406 | .default_dmacon = ATMEL_LCDC_DMAEN, | 406 | .default_dmacon = ATMEL_LCDC_DMAEN, |
407 | .default_lcdcon2 = AT91SAM9261_DEFAULT_STN_LCDCON2, | 407 | .default_lcdcon2 = AT91SAM9261_DEFAULT_STN_LCDCON2, |
@@ -445,7 +445,7 @@ static struct fb_monspecs at91fb_default_tft_monspecs = { | |||
445 | | ATMEL_LCDC_DISTYPE_TFT \ | 445 | | ATMEL_LCDC_DISTYPE_TFT \ |
446 | | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) | 446 | | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) |
447 | 447 | ||
448 | static void at91_lcdc_tft_power_control(int on) | 448 | static void at91_lcdc_tft_power_control(struct atmel_lcdfb_pdata *pdata, int on) |
449 | { | 449 | { |
450 | if (on) | 450 | if (on) |
451 | at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ | 451 | at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ |
@@ -453,7 +453,7 @@ static void at91_lcdc_tft_power_control(int on) | |||
453 | at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ | 453 | at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ |
454 | } | 454 | } |
455 | 455 | ||
456 | static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | 456 | static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { |
457 | .lcdcon_is_backlight = true, | 457 | .lcdcon_is_backlight = true, |
458 | .default_bpp = 16, | 458 | .default_bpp = 16, |
459 | .default_dmacon = ATMEL_LCDC_DMAEN, | 459 | .default_dmacon = ATMEL_LCDC_DMAEN, |
@@ -465,7 +465,7 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | |||
465 | #endif | 465 | #endif |
466 | 466 | ||
467 | #else | 467 | #else |
468 | static struct atmel_lcdfb_info __initdata ek_lcdc_data; | 468 | static struct atmel_lcdfb_pdata __initdata ek_lcdc_data; |
469 | #endif | 469 | #endif |
470 | 470 | ||
471 | 471 | ||
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 3284df05df14..8b4942cbb6d9 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c | |||
@@ -275,13 +275,13 @@ static struct fb_monspecs at91fb_default_monspecs = { | |||
275 | | ATMEL_LCDC_DISTYPE_TFT \ | 275 | | ATMEL_LCDC_DISTYPE_TFT \ |
276 | | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) | 276 | | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) |
277 | 277 | ||
278 | static void at91_lcdc_power_control(int on) | 278 | static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on) |
279 | { | 279 | { |
280 | at91_set_gpio_value(AT91_PIN_PA30, on); | 280 | at91_set_gpio_value(AT91_PIN_PA30, on); |
281 | } | 281 | } |
282 | 282 | ||
283 | /* Driver datas */ | 283 | /* Driver datas */ |
284 | static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | 284 | static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { |
285 | .lcdcon_is_backlight = true, | 285 | .lcdcon_is_backlight = true, |
286 | .default_bpp = 16, | 286 | .default_bpp = 16, |
287 | .default_dmacon = ATMEL_LCDC_DMAEN, | 287 | .default_dmacon = ATMEL_LCDC_DMAEN, |
@@ -292,7 +292,7 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | |||
292 | }; | 292 | }; |
293 | 293 | ||
294 | #else | 294 | #else |
295 | static struct atmel_lcdfb_info __initdata ek_lcdc_data; | 295 | static struct atmel_lcdfb_pdata __initdata ek_lcdc_data; |
296 | #endif | 296 | #endif |
297 | 297 | ||
298 | 298 | ||
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index 2a94896a1375..ef39078c8ce2 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c | |||
@@ -284,7 +284,7 @@ static struct fb_monspecs at91fb_default_monspecs = { | |||
284 | | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) | 284 | | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) |
285 | 285 | ||
286 | /* Driver datas */ | 286 | /* Driver datas */ |
287 | static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | 287 | static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { |
288 | .lcdcon_is_backlight = true, | 288 | .lcdcon_is_backlight = true, |
289 | .default_bpp = 32, | 289 | .default_bpp = 32, |
290 | .default_dmacon = ATMEL_LCDC_DMAEN, | 290 | .default_dmacon = ATMEL_LCDC_DMAEN, |
@@ -295,7 +295,7 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | |||
295 | }; | 295 | }; |
296 | 296 | ||
297 | #else | 297 | #else |
298 | static struct atmel_lcdfb_info __initdata ek_lcdc_data; | 298 | static struct atmel_lcdfb_pdata __initdata ek_lcdc_data; |
299 | #endif | 299 | #endif |
300 | 300 | ||
301 | 301 | ||
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index aa265dcf2128..604eecf6cd70 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c | |||
@@ -170,7 +170,7 @@ static struct fb_monspecs at91fb_default_monspecs = { | |||
170 | | ATMEL_LCDC_DISTYPE_TFT \ | 170 | | ATMEL_LCDC_DISTYPE_TFT \ |
171 | | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) | 171 | | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) |
172 | 172 | ||
173 | static void at91_lcdc_power_control(int on) | 173 | static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on) |
174 | { | 174 | { |
175 | if (on) | 175 | if (on) |
176 | at91_set_gpio_value(AT91_PIN_PC1, 0); /* power up */ | 176 | at91_set_gpio_value(AT91_PIN_PC1, 0); /* power up */ |
@@ -179,7 +179,7 @@ static void at91_lcdc_power_control(int on) | |||
179 | } | 179 | } |
180 | 180 | ||
181 | /* Driver datas */ | 181 | /* Driver datas */ |
182 | static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | 182 | static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = { |
183 | .lcdcon_is_backlight = true, | 183 | .lcdcon_is_backlight = true, |
184 | .default_bpp = 16, | 184 | .default_bpp = 16, |
185 | .default_dmacon = ATMEL_LCDC_DMAEN, | 185 | .default_dmacon = ATMEL_LCDC_DMAEN, |
@@ -191,7 +191,7 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | |||
191 | }; | 191 | }; |
192 | 192 | ||
193 | #else | 193 | #else |
194 | static struct atmel_lcdfb_info __initdata ek_lcdc_data; | 194 | static struct atmel_lcdfb_pdata __initdata ek_lcdc_data; |
195 | #endif | 195 | #endif |
196 | 196 | ||
197 | 197 | ||
diff --git a/arch/arm/mach-at91/board.h b/arch/arm/mach-at91/board.h index 4a234fb2ab3b..6c08b341167d 100644 --- a/arch/arm/mach-at91/board.h +++ b/arch/arm/mach-at91/board.h | |||
@@ -107,8 +107,8 @@ extern void __init at91_add_device_pwm(u32 mask); | |||
107 | extern void __init at91_add_device_ssc(unsigned id, unsigned pins); | 107 | extern void __init at91_add_device_ssc(unsigned id, unsigned pins); |
108 | 108 | ||
109 | /* LCD Controller */ | 109 | /* LCD Controller */ |
110 | struct atmel_lcdfb_info; | 110 | struct atmel_lcdfb_pdata; |
111 | extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); | 111 | extern void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data); |
112 | 112 | ||
113 | /* AC97 */ | 113 | /* AC97 */ |
114 | extern void __init at91_add_device_ac97(struct ac97c_platform_data *data); | 114 | extern void __init at91_add_device_ac97(struct ac97c_platform_data *data); |
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index 702232996c8c..cfadd974f5ce 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c | |||
@@ -191,7 +191,6 @@ static struct pxa3xx_nand_platform_data dkb_nand_info = { | |||
191 | #define SCLK_SOURCE_SELECT(x) (x << 30) /* 0x0 ~ 0x3 */ | 191 | #define SCLK_SOURCE_SELECT(x) (x << 30) /* 0x0 ~ 0x3 */ |
192 | /* link config */ | 192 | /* link config */ |
193 | #define CFG_DUMBMODE(mode) (mode << 28) /* 0x0 ~ 0x6*/ | 193 | #define CFG_DUMBMODE(mode) (mode << 28) /* 0x0 ~ 0x6*/ |
194 | #define CFG_GRA_SWAPRB(x) (x << 0) /* 1: rbswap enabled */ | ||
195 | static struct mmp_mach_path_config dkb_disp_config[] = { | 194 | static struct mmp_mach_path_config dkb_disp_config[] = { |
196 | [0] = { | 195 | [0] = { |
197 | .name = "mmp-parallel", | 196 | .name = "mmp-parallel", |
@@ -199,8 +198,7 @@ static struct mmp_mach_path_config dkb_disp_config[] = { | |||
199 | .output_type = PATH_OUT_PARALLEL, | 198 | .output_type = PATH_OUT_PARALLEL, |
200 | .path_config = CFG_IOPADMODE(0x1) | 199 | .path_config = CFG_IOPADMODE(0x1) |
201 | | SCLK_SOURCE_SELECT(0x1), | 200 | | SCLK_SOURCE_SELECT(0x1), |
202 | .link_config = CFG_DUMBMODE(0x2) | 201 | .link_config = CFG_DUMBMODE(0x2), |
203 | | CFG_GRA_SWAPRB(0x1), | ||
204 | }, | 202 | }, |
205 | }; | 203 | }; |
206 | 204 | ||
diff --git a/arch/avr32/boards/atngw100/evklcd10x.c b/arch/avr32/boards/atngw100/evklcd10x.c index 20388750d564..64919b0da7aa 100644 --- a/arch/avr32/boards/atngw100/evklcd10x.c +++ b/arch/avr32/boards/atngw100/evklcd10x.c | |||
@@ -58,7 +58,7 @@ static struct fb_monspecs __initdata atevklcd10x_default_monspecs = { | |||
58 | .dclkmax = 28330000, | 58 | .dclkmax = 28330000, |
59 | }; | 59 | }; |
60 | 60 | ||
61 | static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = { | 61 | static struct atmel_lcdfb_pdata __initdata atevklcd10x_lcdc_data = { |
62 | .default_bpp = 16, | 62 | .default_bpp = 16, |
63 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 63 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
64 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 64 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
@@ -96,7 +96,7 @@ static struct fb_monspecs __initdata atevklcd10x_default_monspecs = { | |||
96 | .dclkmax = 7000000, | 96 | .dclkmax = 7000000, |
97 | }; | 97 | }; |
98 | 98 | ||
99 | static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = { | 99 | static struct atmel_lcdfb_pdata __initdata atevklcd10x_lcdc_data = { |
100 | .default_bpp = 16, | 100 | .default_bpp = 16, |
101 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 101 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
102 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 102 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
@@ -134,7 +134,7 @@ static struct fb_monspecs __initdata atevklcd10x_default_monspecs = { | |||
134 | .dclkmax = 6400000, | 134 | .dclkmax = 6400000, |
135 | }; | 135 | }; |
136 | 136 | ||
137 | static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = { | 137 | static struct atmel_lcdfb_pdata __initdata atevklcd10x_lcdc_data = { |
138 | .default_bpp = 16, | 138 | .default_bpp = 16, |
139 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 139 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
140 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 140 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
@@ -145,7 +145,7 @@ static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = { | |||
145 | }; | 145 | }; |
146 | #endif | 146 | #endif |
147 | 147 | ||
148 | static void atevklcd10x_lcdc_power_control(int on) | 148 | static void atevklcd10x_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on) |
149 | { | 149 | { |
150 | gpio_set_value(GPIO_PIN_PB(15), on); | 150 | gpio_set_value(GPIO_PIN_PB(15), on); |
151 | } | 151 | } |
diff --git a/arch/avr32/boards/atngw100/mrmt.c b/arch/avr32/boards/atngw100/mrmt.c index 7de083d19b7e..1ba09e4c02b1 100644 --- a/arch/avr32/boards/atngw100/mrmt.c +++ b/arch/avr32/boards/atngw100/mrmt.c | |||
@@ -83,7 +83,7 @@ static struct fb_monspecs __initdata lcd_fb_default_monspecs = { | |||
83 | .dclkmax = 9260000, | 83 | .dclkmax = 9260000, |
84 | }; | 84 | }; |
85 | 85 | ||
86 | static struct atmel_lcdfb_info __initdata rmt_lcdc_data = { | 86 | static struct atmel_lcdfb_pdata __initdata rmt_lcdc_data = { |
87 | .default_bpp = 24, | 87 | .default_bpp = 24, |
88 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 88 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
89 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 89 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
@@ -126,7 +126,7 @@ static struct fb_monspecs __initdata lcd_fb_default_monspecs = { | |||
126 | .dclkmax = 9260000, | 126 | .dclkmax = 9260000, |
127 | }; | 127 | }; |
128 | 128 | ||
129 | static struct atmel_lcdfb_info __initdata rmt_lcdc_data = { | 129 | static struct atmel_lcdfb_pdata __initdata rmt_lcdc_data = { |
130 | .default_bpp = 24, | 130 | .default_bpp = 24, |
131 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 131 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
132 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 132 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
diff --git a/arch/avr32/boards/atstk1000/atstk1000.h b/arch/avr32/boards/atstk1000/atstk1000.h index 9392d3252865..653cc09e536c 100644 --- a/arch/avr32/boards/atstk1000/atstk1000.h +++ b/arch/avr32/boards/atstk1000/atstk1000.h | |||
@@ -10,7 +10,7 @@ | |||
10 | #ifndef __ARCH_AVR32_BOARDS_ATSTK1000_ATSTK1000_H | 10 | #ifndef __ARCH_AVR32_BOARDS_ATSTK1000_ATSTK1000_H |
11 | #define __ARCH_AVR32_BOARDS_ATSTK1000_ATSTK1000_H | 11 | #define __ARCH_AVR32_BOARDS_ATSTK1000_ATSTK1000_H |
12 | 12 | ||
13 | extern struct atmel_lcdfb_info atstk1000_lcdc_data; | 13 | extern struct atmel_lcdfb_pdata atstk1000_lcdc_data; |
14 | 14 | ||
15 | void atstk1000_setup_j2_leds(void); | 15 | void atstk1000_setup_j2_leds(void); |
16 | 16 | ||
diff --git a/arch/avr32/boards/atstk1000/setup.c b/arch/avr32/boards/atstk1000/setup.c index 2d6b560115d9..b6b88f5e0b43 100644 --- a/arch/avr32/boards/atstk1000/setup.c +++ b/arch/avr32/boards/atstk1000/setup.c | |||
@@ -55,7 +55,7 @@ static struct fb_monspecs __initdata atstk1000_default_monspecs = { | |||
55 | .dclkmax = 30000000, | 55 | .dclkmax = 30000000, |
56 | }; | 56 | }; |
57 | 57 | ||
58 | struct atmel_lcdfb_info __initdata atstk1000_lcdc_data = { | 58 | struct atmel_lcdfb_pdata __initdata atstk1000_lcdc_data = { |
59 | .default_bpp = 24, | 59 | .default_bpp = 24, |
60 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 60 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
61 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 61 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
diff --git a/arch/avr32/boards/favr-32/setup.c b/arch/avr32/boards/favr-32/setup.c index 27bd6fbe21cb..7b1f2cd85400 100644 --- a/arch/avr32/boards/favr-32/setup.c +++ b/arch/avr32/boards/favr-32/setup.c | |||
@@ -125,7 +125,7 @@ static struct fb_monspecs __initdata favr32_default_monspecs = { | |||
125 | .dclkmax = 28000000, | 125 | .dclkmax = 28000000, |
126 | }; | 126 | }; |
127 | 127 | ||
128 | struct atmel_lcdfb_info __initdata favr32_lcdc_data = { | 128 | struct atmel_lcdfb_pdata __initdata favr32_lcdc_data = { |
129 | .default_bpp = 16, | 129 | .default_bpp = 16, |
130 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 130 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
131 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 131 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
diff --git a/arch/avr32/boards/hammerhead/setup.c b/arch/avr32/boards/hammerhead/setup.c index 9d1efd1cd425..dc0e317f2ecd 100644 --- a/arch/avr32/boards/hammerhead/setup.c +++ b/arch/avr32/boards/hammerhead/setup.c | |||
@@ -77,7 +77,7 @@ static struct fb_monspecs __initdata hammerhead_hda350t_monspecs = { | |||
77 | .dclkmax = 10000000, | 77 | .dclkmax = 10000000, |
78 | }; | 78 | }; |
79 | 79 | ||
80 | struct atmel_lcdfb_info __initdata hammerhead_lcdc_data = { | 80 | struct atmel_lcdfb_pdata __initdata hammerhead_lcdc_data = { |
81 | .default_bpp = 24, | 81 | .default_bpp = 24, |
82 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 82 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
83 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 83 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
diff --git a/arch/avr32/boards/merisc/display.c b/arch/avr32/boards/merisc/display.c index 85a543cd4abc..e7683ee7ed40 100644 --- a/arch/avr32/boards/merisc/display.c +++ b/arch/avr32/boards/merisc/display.c | |||
@@ -45,7 +45,7 @@ static struct fb_monspecs merisc_fb_monspecs = { | |||
45 | .dclkmax = 30000000, | 45 | .dclkmax = 30000000, |
46 | }; | 46 | }; |
47 | 47 | ||
48 | struct atmel_lcdfb_info merisc_lcdc_data = { | 48 | struct atmel_lcdfb_pdata merisc_lcdc_data = { |
49 | .default_bpp = 24, | 49 | .default_bpp = 24, |
50 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 50 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
51 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 51 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
diff --git a/arch/avr32/boards/mimc200/setup.c b/arch/avr32/boards/mimc200/setup.c index 05358aa5ef7d..1cb8e9cc5cfa 100644 --- a/arch/avr32/boards/mimc200/setup.c +++ b/arch/avr32/boards/mimc200/setup.c | |||
@@ -8,7 +8,7 @@ | |||
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | extern struct atmel_lcdfb_info mimc200_lcdc_data; | 11 | extern struct atmel_lcdfb_pdata mimc200_lcdc_data; |
12 | 12 | ||
13 | #include <linux/clk.h> | 13 | #include <linux/clk.h> |
14 | #include <linux/etherdevice.h> | 14 | #include <linux/etherdevice.h> |
@@ -71,7 +71,7 @@ static struct fb_monspecs __initdata mimc200_default_monspecs = { | |||
71 | .dclkmax = 25200000, | 71 | .dclkmax = 25200000, |
72 | }; | 72 | }; |
73 | 73 | ||
74 | struct atmel_lcdfb_info __initdata mimc200_lcdc_data = { | 74 | struct atmel_lcdfb_pdata __initdata mimc200_lcdc_data = { |
75 | .default_bpp = 16, | 75 | .default_bpp = 16, |
76 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, | 76 | .default_dmacon = ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN, |
77 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT | 77 | .default_lcdcon2 = (ATMEL_LCDC_DISTYPE_TFT |
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c index a68f3cf7c3c1..a1f4d1e91b52 100644 --- a/arch/avr32/mach-at32ap/at32ap700x.c +++ b/arch/avr32/mach-at32ap/at32ap700x.c | |||
@@ -1439,7 +1439,7 @@ fail: | |||
1439 | * LCDC | 1439 | * LCDC |
1440 | * -------------------------------------------------------------------- */ | 1440 | * -------------------------------------------------------------------- */ |
1441 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) | 1441 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
1442 | static struct atmel_lcdfb_info atmel_lcdfb0_data; | 1442 | static struct atmel_lcdfb_pdata atmel_lcdfb0_data; |
1443 | static struct resource atmel_lcdfb0_resource[] = { | 1443 | static struct resource atmel_lcdfb0_resource[] = { |
1444 | { | 1444 | { |
1445 | .start = 0xff000000, | 1445 | .start = 0xff000000, |
@@ -1467,12 +1467,12 @@ static struct clk atmel_lcdfb0_pixclk = { | |||
1467 | }; | 1467 | }; |
1468 | 1468 | ||
1469 | struct platform_device *__init | 1469 | struct platform_device *__init |
1470 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, | 1470 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_pdata *data, |
1471 | unsigned long fbmem_start, unsigned long fbmem_len, | 1471 | unsigned long fbmem_start, unsigned long fbmem_len, |
1472 | u64 pin_mask) | 1472 | u64 pin_mask) |
1473 | { | 1473 | { |
1474 | struct platform_device *pdev; | 1474 | struct platform_device *pdev; |
1475 | struct atmel_lcdfb_info *info; | 1475 | struct atmel_lcdfb_pdata *info; |
1476 | struct fb_monspecs *monspecs; | 1476 | struct fb_monspecs *monspecs; |
1477 | struct fb_videomode *modedb; | 1477 | struct fb_videomode *modedb; |
1478 | unsigned int modedb_size; | 1478 | unsigned int modedb_size; |
@@ -1529,7 +1529,7 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, | |||
1529 | } | 1529 | } |
1530 | 1530 | ||
1531 | info = pdev->dev.platform_data; | 1531 | info = pdev->dev.platform_data; |
1532 | memcpy(info, data, sizeof(struct atmel_lcdfb_info)); | 1532 | memcpy(info, data, sizeof(struct atmel_lcdfb_pdata)); |
1533 | info->default_monspecs = monspecs; | 1533 | info->default_monspecs = monspecs; |
1534 | 1534 | ||
1535 | pdev->name = "at32ap-lcdfb"; | 1535 | pdev->name = "at32ap-lcdfb"; |
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h index d485b0391357..f1a316d52c73 100644 --- a/arch/avr32/mach-at32ap/include/mach/board.h +++ b/arch/avr32/mach-at32ap/include/mach/board.h | |||
@@ -44,9 +44,9 @@ struct platform_device * | |||
44 | at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n); | 44 | at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n); |
45 | void at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n); | 45 | void at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n); |
46 | 46 | ||
47 | struct atmel_lcdfb_info; | 47 | struct atmel_lcdfb_pdata; |
48 | struct platform_device * | 48 | struct platform_device * |
49 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, | 49 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_pdata *data, |
50 | unsigned long fbmem_start, unsigned long fbmem_len, | 50 | unsigned long fbmem_start, unsigned long fbmem_len, |
51 | u64 pin_mask); | 51 | u64 pin_mask); |
52 | 52 | ||
diff --git a/drivers/auxdisplay/cfag12864bfb.c b/drivers/auxdisplay/cfag12864bfb.c index d585735430dd..a3874034e2ce 100644 --- a/drivers/auxdisplay/cfag12864bfb.c +++ b/drivers/auxdisplay/cfag12864bfb.c | |||
@@ -102,8 +102,7 @@ static int cfag12864bfb_probe(struct platform_device *device) | |||
102 | 102 | ||
103 | platform_set_drvdata(device, info); | 103 | platform_set_drvdata(device, info); |
104 | 104 | ||
105 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, | 105 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
106 | info->fix.id); | ||
107 | 106 | ||
108 | return 0; | 107 | return 0; |
109 | 108 | ||
diff --git a/drivers/video/68328fb.c b/drivers/video/68328fb.c index fa44fbed397d..552258c8f99d 100644 --- a/drivers/video/68328fb.c +++ b/drivers/video/68328fb.c | |||
@@ -478,11 +478,10 @@ int __init mc68x328fb_init(void) | |||
478 | return -EINVAL; | 478 | return -EINVAL; |
479 | } | 479 | } |
480 | 480 | ||
481 | printk(KERN_INFO | 481 | fb_info(&fb_info, "%s frame buffer device\n", fb_info.fix.id); |
482 | "fb%d: %s frame buffer device\n", fb_info.node, fb_info.fix.id); | 482 | fb_info(&fb_info, "%dx%dx%d at 0x%08lx\n", |
483 | printk(KERN_INFO | 483 | mc68x328fb_default.xres_virtual, |
484 | "fb%d: %dx%dx%d at 0x%08lx\n", fb_info.node, | 484 | mc68x328fb_default.yres_virtual, |
485 | mc68x328fb_default.xres_virtual, mc68x328fb_default.yres_virtual, | ||
486 | 1 << mc68x328fb_default.bits_per_pixel, videomemory); | 485 | 1 << mc68x328fb_default.bits_per_pixel, videomemory); |
487 | 486 | ||
488 | return 0; | 487 | return 0; |
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 84b685f7ab6e..14317b70b413 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig | |||
@@ -996,6 +996,8 @@ config FB_ATMEL | |||
996 | select FB_CFB_FILLRECT | 996 | select FB_CFB_FILLRECT |
997 | select FB_CFB_COPYAREA | 997 | select FB_CFB_COPYAREA |
998 | select FB_CFB_IMAGEBLIT | 998 | select FB_CFB_IMAGEBLIT |
999 | select FB_MODE_HELPERS | ||
1000 | select VIDEOMODE_HELPERS | ||
999 | help | 1001 | help |
1000 | This enables support for the AT91/AT32 LCD Controller. | 1002 | This enables support for the AT91/AT32 LCD Controller. |
1001 | 1003 | ||
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c index afe4702a5528..14d6b3793e0a 100644 --- a/drivers/video/amba-clcd.c +++ b/drivers/video/amba-clcd.c | |||
@@ -545,7 +545,7 @@ static int clcdfb_register(struct clcd_fb *fb) | |||
545 | 545 | ||
546 | static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id) | 546 | static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id) |
547 | { | 547 | { |
548 | struct clcd_board *board = dev->dev.platform_data; | 548 | struct clcd_board *board = dev_get_platdata(&dev->dev); |
549 | struct clcd_fb *fb; | 549 | struct clcd_fb *fb; |
550 | int ret; | 550 | int ret; |
551 | 551 | ||
@@ -599,8 +599,6 @@ static int clcdfb_remove(struct amba_device *dev) | |||
599 | { | 599 | { |
600 | struct clcd_fb *fb = amba_get_drvdata(dev); | 600 | struct clcd_fb *fb = amba_get_drvdata(dev); |
601 | 601 | ||
602 | amba_set_drvdata(dev, NULL); | ||
603 | |||
604 | clcdfb_disable(fb); | 602 | clcdfb_disable(fb); |
605 | unregister_framebuffer(&fb->fb); | 603 | unregister_framebuffer(&fb->fb); |
606 | if (fb->fb.cmap.len) | 604 | if (fb->fb.cmap.len) |
diff --git a/drivers/video/amifb.c b/drivers/video/amifb.c index a6780eecff0e..0dac36ce09d6 100644 --- a/drivers/video/amifb.c +++ b/drivers/video/amifb.c | |||
@@ -3742,13 +3742,12 @@ default_chipset: | |||
3742 | if (err) | 3742 | if (err) |
3743 | goto unset_drvdata; | 3743 | goto unset_drvdata; |
3744 | 3744 | ||
3745 | printk("fb%d: %s frame buffer device, using %dK of video memory\n", | 3745 | fb_info(info, "%s frame buffer device, using %dK of video memory\n", |
3746 | info->node, info->fix.id, info->fix.smem_len>>10); | 3746 | info->fix.id, info->fix.smem_len>>10); |
3747 | 3747 | ||
3748 | return 0; | 3748 | return 0; |
3749 | 3749 | ||
3750 | unset_drvdata: | 3750 | unset_drvdata: |
3751 | dev_set_drvdata(&pdev->dev, NULL); | ||
3752 | fb_dealloc_cmap(&info->cmap); | 3751 | fb_dealloc_cmap(&info->cmap); |
3753 | free_irq: | 3752 | free_irq: |
3754 | free_irq(IRQ_AMIGA_COPPER, info->par); | 3753 | free_irq(IRQ_AMIGA_COPPER, info->par); |
@@ -3768,7 +3767,6 @@ static int __exit amifb_remove(struct platform_device *pdev) | |||
3768 | struct fb_info *info = dev_get_drvdata(&pdev->dev); | 3767 | struct fb_info *info = dev_get_drvdata(&pdev->dev); |
3769 | 3768 | ||
3770 | unregister_framebuffer(info); | 3769 | unregister_framebuffer(info); |
3771 | dev_set_drvdata(&pdev->dev, NULL); | ||
3772 | fb_dealloc_cmap(&info->cmap); | 3770 | fb_dealloc_cmap(&info->cmap); |
3773 | free_irq(IRQ_AMIGA_COPPER, info->par); | 3771 | free_irq(IRQ_AMIGA_COPPER, info->par); |
3774 | custom.dmacon = DMAF_ALL | DMAF_MASTER; | 3772 | custom.dmacon = DMAF_ALL | DMAF_MASTER; |
diff --git a/drivers/video/arcfb.c b/drivers/video/arcfb.c index e43401afdd03..1b0b233b8b39 100644 --- a/drivers/video/arcfb.c +++ b/drivers/video/arcfb.c | |||
@@ -556,9 +556,8 @@ static int arcfb_probe(struct platform_device *dev) | |||
556 | goto err1; | 556 | goto err1; |
557 | } | 557 | } |
558 | } | 558 | } |
559 | printk(KERN_INFO | 559 | fb_info(info, "Arc frame buffer device, using %dK of video memory\n", |
560 | "fb%d: Arc frame buffer device, using %dK of video memory\n", | 560 | videomemorysize >> 10); |
561 | info->node, videomemorysize >> 10); | ||
562 | 561 | ||
563 | /* this inits the lcd but doesn't clear dirty pixels */ | 562 | /* this inits the lcd but doesn't clear dirty pixels */ |
564 | for (i = 0; i < num_cols * num_rows; i++) { | 563 | for (i = 0; i < num_cols * num_rows; i++) { |
@@ -572,8 +571,7 @@ static int arcfb_probe(struct platform_device *dev) | |||
572 | /* if we were told to splash the screen, we just clear it */ | 571 | /* if we were told to splash the screen, we just clear it */ |
573 | if (!nosplash) { | 572 | if (!nosplash) { |
574 | for (i = 0; i < num_cols * num_rows; i++) { | 573 | for (i = 0; i < num_cols * num_rows; i++) { |
575 | printk(KERN_INFO "fb%d: splashing lcd %d\n", | 574 | fb_info(info, "splashing lcd %d\n", i); |
576 | info->node, i); | ||
577 | ks108_set_start_line(par, i, 0); | 575 | ks108_set_start_line(par, i, 0); |
578 | ks108_clear_lcd(par, i); | 576 | ks108_clear_lcd(par, i); |
579 | } | 577 | } |
diff --git a/drivers/video/arkfb.c b/drivers/video/arkfb.c index 94a51f1ef904..a6b29bd4a12a 100644 --- a/drivers/video/arkfb.c +++ b/drivers/video/arkfb.c | |||
@@ -137,8 +137,7 @@ static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map) | |||
137 | 137 | ||
138 | if ((map->width != 8) || (map->height != 16) || | 138 | if ((map->width != 8) || (map->height != 16) || |
139 | (map->depth != 1) || (map->length != 256)) { | 139 | (map->depth != 1) || (map->length != 256)) { |
140 | printk(KERN_ERR "fb%d: unsupported font parameters: width %d, " | 140 | fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", |
141 | "height %d, depth %d, length %d\n", info->node, | ||
142 | map->width, map->height, map->depth, map->length); | 141 | map->width, map->height, map->depth, map->length); |
143 | return; | 142 | return; |
144 | } | 143 | } |
@@ -517,7 +516,7 @@ static void ark_set_pixclock(struct fb_info *info, u32 pixclock) | |||
517 | 516 | ||
518 | int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock); | 517 | int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock); |
519 | if (rv < 0) { | 518 | if (rv < 0) { |
520 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); | 519 | fb_err(info, "cannot set requested pixclock, keeping old value\n"); |
521 | return; | 520 | return; |
522 | } | 521 | } |
523 | 522 | ||
@@ -584,7 +583,7 @@ static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
584 | rv = svga_match_format (arkfb_formats, var, NULL); | 583 | rv = svga_match_format (arkfb_formats, var, NULL); |
585 | if (rv < 0) | 584 | if (rv < 0) |
586 | { | 585 | { |
587 | printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); | 586 | fb_err(info, "unsupported mode requested\n"); |
588 | return rv; | 587 | return rv; |
589 | } | 588 | } |
590 | 589 | ||
@@ -604,14 +603,15 @@ static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
604 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; | 603 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; |
605 | if (mem > info->screen_size) | 604 | if (mem > info->screen_size) |
606 | { | 605 | { |
607 | printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); | 606 | fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n", |
607 | mem >> 10, (unsigned int) (info->screen_size >> 10)); | ||
608 | return -EINVAL; | 608 | return -EINVAL; |
609 | } | 609 | } |
610 | 610 | ||
611 | rv = svga_check_timings (&ark_timing_regs, var, info->node); | 611 | rv = svga_check_timings (&ark_timing_regs, var, info->node); |
612 | if (rv < 0) | 612 | if (rv < 0) |
613 | { | 613 | { |
614 | printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); | 614 | fb_err(info, "invalid timings requested\n"); |
615 | return rv; | 615 | return rv; |
616 | } | 616 | } |
617 | 617 | ||
@@ -693,7 +693,7 @@ static int arkfb_set_par(struct fb_info *info) | |||
693 | vga_wseq(par->state.vgabase, 0x18, regval); | 693 | vga_wseq(par->state.vgabase, 0x18, regval); |
694 | 694 | ||
695 | /* Set the offset register */ | 695 | /* Set the offset register */ |
696 | pr_debug("fb%d: offset register : %d\n", info->node, offset_value); | 696 | fb_dbg(info, "offset register : %d\n", offset_value); |
697 | svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value); | 697 | svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value); |
698 | 698 | ||
699 | /* fix for hi-res textmode */ | 699 | /* fix for hi-res textmode */ |
@@ -716,7 +716,7 @@ static int arkfb_set_par(struct fb_info *info) | |||
716 | /* Set mode-specific register values */ | 716 | /* Set mode-specific register values */ |
717 | switch (mode) { | 717 | switch (mode) { |
718 | case 0: | 718 | case 0: |
719 | pr_debug("fb%d: text mode\n", info->node); | 719 | fb_dbg(info, "text mode\n"); |
720 | svga_set_textmode_vga_regs(par->state.vgabase); | 720 | svga_set_textmode_vga_regs(par->state.vgabase); |
721 | 721 | ||
722 | vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ | 722 | vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ |
@@ -725,7 +725,7 @@ static int arkfb_set_par(struct fb_info *info) | |||
725 | 725 | ||
726 | break; | 726 | break; |
727 | case 1: | 727 | case 1: |
728 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); | 728 | fb_dbg(info, "4 bit pseudocolor\n"); |
729 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); | 729 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); |
730 | 730 | ||
731 | vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ | 731 | vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ |
@@ -733,44 +733,44 @@ static int arkfb_set_par(struct fb_info *info) | |||
733 | dac_set_mode(par->dac, DAC_PSEUDO8_8); | 733 | dac_set_mode(par->dac, DAC_PSEUDO8_8); |
734 | break; | 734 | break; |
735 | case 2: | 735 | case 2: |
736 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); | 736 | fb_dbg(info, "4 bit pseudocolor, planar\n"); |
737 | 737 | ||
738 | vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ | 738 | vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ |
739 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ | 739 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ |
740 | dac_set_mode(par->dac, DAC_PSEUDO8_8); | 740 | dac_set_mode(par->dac, DAC_PSEUDO8_8); |
741 | break; | 741 | break; |
742 | case 3: | 742 | case 3: |
743 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); | 743 | fb_dbg(info, "8 bit pseudocolor\n"); |
744 | 744 | ||
745 | vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */ | 745 | vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */ |
746 | 746 | ||
747 | if (info->var.pixclock > 20000) { | 747 | if (info->var.pixclock > 20000) { |
748 | pr_debug("fb%d: not using multiplex\n", info->node); | 748 | fb_dbg(info, "not using multiplex\n"); |
749 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ | 749 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ |
750 | dac_set_mode(par->dac, DAC_PSEUDO8_8); | 750 | dac_set_mode(par->dac, DAC_PSEUDO8_8); |
751 | } else { | 751 | } else { |
752 | pr_debug("fb%d: using multiplex\n", info->node); | 752 | fb_dbg(info, "using multiplex\n"); |
753 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ | 753 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
754 | dac_set_mode(par->dac, DAC_PSEUDO8_16); | 754 | dac_set_mode(par->dac, DAC_PSEUDO8_16); |
755 | hdiv = 2; | 755 | hdiv = 2; |
756 | } | 756 | } |
757 | break; | 757 | break; |
758 | case 4: | 758 | case 4: |
759 | pr_debug("fb%d: 5/5/5 truecolor\n", info->node); | 759 | fb_dbg(info, "5/5/5 truecolor\n"); |
760 | 760 | ||
761 | vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ | 761 | vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ |
762 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ | 762 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
763 | dac_set_mode(par->dac, DAC_RGB1555_16); | 763 | dac_set_mode(par->dac, DAC_RGB1555_16); |
764 | break; | 764 | break; |
765 | case 5: | 765 | case 5: |
766 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); | 766 | fb_dbg(info, "5/6/5 truecolor\n"); |
767 | 767 | ||
768 | vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ | 768 | vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ |
769 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ | 769 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
770 | dac_set_mode(par->dac, DAC_RGB0565_16); | 770 | dac_set_mode(par->dac, DAC_RGB0565_16); |
771 | break; | 771 | break; |
772 | case 6: | 772 | case 6: |
773 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); | 773 | fb_dbg(info, "8/8/8 truecolor\n"); |
774 | 774 | ||
775 | vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */ | 775 | vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */ |
776 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ | 776 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
@@ -779,7 +779,7 @@ static int arkfb_set_par(struct fb_info *info) | |||
779 | hdiv = 2; | 779 | hdiv = 2; |
780 | break; | 780 | break; |
781 | case 7: | 781 | case 7: |
782 | pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); | 782 | fb_dbg(info, "8/8/8/8 truecolor\n"); |
783 | 783 | ||
784 | vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */ | 784 | vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */ |
785 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ | 785 | svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ |
@@ -787,7 +787,7 @@ static int arkfb_set_par(struct fb_info *info) | |||
787 | hmul = 2; | 787 | hmul = 2; |
788 | break; | 788 | break; |
789 | default: | 789 | default: |
790 | printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); | 790 | fb_err(info, "unsupported mode - bug\n"); |
791 | return -EINVAL; | 791 | return -EINVAL; |
792 | } | 792 | } |
793 | 793 | ||
@@ -879,19 +879,19 @@ static int arkfb_blank(int blank_mode, struct fb_info *info) | |||
879 | 879 | ||
880 | switch (blank_mode) { | 880 | switch (blank_mode) { |
881 | case FB_BLANK_UNBLANK: | 881 | case FB_BLANK_UNBLANK: |
882 | pr_debug("fb%d: unblank\n", info->node); | 882 | fb_dbg(info, "unblank\n"); |
883 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); | 883 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
884 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); | 884 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); |
885 | break; | 885 | break; |
886 | case FB_BLANK_NORMAL: | 886 | case FB_BLANK_NORMAL: |
887 | pr_debug("fb%d: blank\n", info->node); | 887 | fb_dbg(info, "blank\n"); |
888 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 888 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
889 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); | 889 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); |
890 | break; | 890 | break; |
891 | case FB_BLANK_POWERDOWN: | 891 | case FB_BLANK_POWERDOWN: |
892 | case FB_BLANK_HSYNC_SUSPEND: | 892 | case FB_BLANK_HSYNC_SUSPEND: |
893 | case FB_BLANK_VSYNC_SUSPEND: | 893 | case FB_BLANK_VSYNC_SUSPEND: |
894 | pr_debug("fb%d: sync down\n", info->node); | 894 | fb_dbg(info, "sync down\n"); |
895 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 895 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
896 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); | 896 | svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); |
897 | break; | 897 | break; |
@@ -1048,12 +1048,12 @@ static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
1048 | 1048 | ||
1049 | rc = register_framebuffer(info); | 1049 | rc = register_framebuffer(info); |
1050 | if (rc < 0) { | 1050 | if (rc < 0) { |
1051 | dev_err(info->device, "cannot register framebugger\n"); | 1051 | dev_err(info->device, "cannot register framebuffer\n"); |
1052 | goto err_reg_fb; | 1052 | goto err_reg_fb; |
1053 | } | 1053 | } |
1054 | 1054 | ||
1055 | printk(KERN_INFO "fb%d: %s on %s, %d MB RAM\n", info->node, info->fix.id, | 1055 | fb_info(info, "%s on %s, %d MB RAM\n", |
1056 | pci_name(dev), info->fix.smem_len >> 20); | 1056 | info->fix.id, pci_name(dev), info->fix.smem_len >> 20); |
1057 | 1057 | ||
1058 | /* Record a reference to the driver data */ | 1058 | /* Record a reference to the driver data */ |
1059 | pci_set_drvdata(dev, info); | 1059 | pci_set_drvdata(dev, info); |
@@ -1108,7 +1108,6 @@ static void ark_pci_remove(struct pci_dev *dev) | |||
1108 | pci_release_regions(dev); | 1108 | pci_release_regions(dev); |
1109 | /* pci_disable_device(dev); */ | 1109 | /* pci_disable_device(dev); */ |
1110 | 1110 | ||
1111 | pci_set_drvdata(dev, NULL); | ||
1112 | framebuffer_release(info); | 1111 | framebuffer_release(info); |
1113 | } | 1112 | } |
1114 | } | 1113 | } |
diff --git a/drivers/video/asiliantfb.c b/drivers/video/asiliantfb.c index d5a37d62847b..d611f1a1ac53 100644 --- a/drivers/video/asiliantfb.c +++ b/drivers/video/asiliantfb.c | |||
@@ -527,8 +527,8 @@ static int init_asiliant(struct fb_info *p, unsigned long addr) | |||
527 | return err; | 527 | return err; |
528 | } | 528 | } |
529 | 529 | ||
530 | printk(KERN_INFO "fb%d: Asiliant 69000 frame buffer (%dK RAM detected)\n", | 530 | fb_info(p, "Asiliant 69000 frame buffer (%dK RAM detected)\n", |
531 | p->node, p->fix.smem_len / 1024); | 531 | p->fix.smem_len / 1024); |
532 | 532 | ||
533 | writeb(0xff, mmio_base + 0x78c); | 533 | writeb(0xff, mmio_base + 0x78c); |
534 | chips_hw_init(p); | 534 | chips_hw_init(p); |
diff --git a/drivers/video/atafb.c b/drivers/video/atafb.c index 64e41f5448c4..e21d1f58554c 100644 --- a/drivers/video/atafb.c +++ b/drivers/video/atafb.c | |||
@@ -3246,11 +3246,8 @@ int __init atafb_init(void) | |||
3246 | return -EINVAL; | 3246 | return -EINVAL; |
3247 | } | 3247 | } |
3248 | 3248 | ||
3249 | // FIXME: mode needs setting! | 3249 | fb_info(&fb_info, "frame buffer device, using %dK of video memory\n", |
3250 | //printk("fb%d: %s frame buffer device, using %dK of video memory\n", | 3250 | screen_len >> 10); |
3251 | // fb_info.node, fb_info.mode->name, screen_len>>10); | ||
3252 | printk("fb%d: frame buffer device, using %dK of video memory\n", | ||
3253 | fb_info.node, screen_len >> 10); | ||
3254 | 3251 | ||
3255 | /* TODO: This driver cannot be unloaded yet */ | 3252 | /* TODO: This driver cannot be unloaded yet */ |
3256 | return 0; | 3253 | return 0; |
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 088511a58a26..8521051cf946 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c | |||
@@ -20,12 +20,55 @@ | |||
20 | #include <linux/gfp.h> | 20 | #include <linux/gfp.h> |
21 | #include <linux/module.h> | 21 | #include <linux/module.h> |
22 | #include <linux/platform_data/atmel.h> | 22 | #include <linux/platform_data/atmel.h> |
23 | #include <linux/of.h> | ||
24 | #include <linux/of_device.h> | ||
25 | #include <linux/of_gpio.h> | ||
26 | #include <video/of_display_timing.h> | ||
27 | #include <video/videomode.h> | ||
23 | 28 | ||
24 | #include <mach/cpu.h> | 29 | #include <mach/cpu.h> |
25 | #include <asm/gpio.h> | 30 | #include <asm/gpio.h> |
26 | 31 | ||
27 | #include <video/atmel_lcdc.h> | 32 | #include <video/atmel_lcdc.h> |
28 | 33 | ||
34 | struct atmel_lcdfb_config { | ||
35 | bool have_alt_pixclock; | ||
36 | bool have_hozval; | ||
37 | bool have_intensity_bit; | ||
38 | }; | ||
39 | |||
40 | /* LCD Controller info data structure, stored in device platform_data */ | ||
41 | struct atmel_lcdfb_info { | ||
42 | spinlock_t lock; | ||
43 | struct fb_info *info; | ||
44 | void __iomem *mmio; | ||
45 | int irq_base; | ||
46 | struct work_struct task; | ||
47 | |||
48 | unsigned int smem_len; | ||
49 | struct platform_device *pdev; | ||
50 | struct clk *bus_clk; | ||
51 | struct clk *lcdc_clk; | ||
52 | |||
53 | struct backlight_device *backlight; | ||
54 | u8 bl_power; | ||
55 | u8 saved_lcdcon; | ||
56 | |||
57 | u32 pseudo_palette[16]; | ||
58 | bool have_intensity_bit; | ||
59 | |||
60 | struct atmel_lcdfb_pdata pdata; | ||
61 | |||
62 | struct atmel_lcdfb_config *config; | ||
63 | }; | ||
64 | |||
65 | struct atmel_lcdfb_power_ctrl_gpio { | ||
66 | int gpio; | ||
67 | int active_low; | ||
68 | |||
69 | struct list_head list; | ||
70 | }; | ||
71 | |||
29 | #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg)) | 72 | #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg)) |
30 | #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg)) | 73 | #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg)) |
31 | 74 | ||
@@ -34,12 +77,6 @@ | |||
34 | #define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */ | 77 | #define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */ |
35 | #define ATMEL_LCDC_FIFO_SIZE 512 /* words */ | 78 | #define ATMEL_LCDC_FIFO_SIZE 512 /* words */ |
36 | 79 | ||
37 | struct atmel_lcdfb_config { | ||
38 | bool have_alt_pixclock; | ||
39 | bool have_hozval; | ||
40 | bool have_intensity_bit; | ||
41 | }; | ||
42 | |||
43 | static struct atmel_lcdfb_config at91sam9261_config = { | 80 | static struct atmel_lcdfb_config at91sam9261_config = { |
44 | .have_hozval = true, | 81 | .have_hozval = true, |
45 | .have_intensity_bit = true, | 82 | .have_intensity_bit = true, |
@@ -248,18 +285,27 @@ static void exit_backlight(struct atmel_lcdfb_info *sinfo) | |||
248 | 285 | ||
249 | static void init_contrast(struct atmel_lcdfb_info *sinfo) | 286 | static void init_contrast(struct atmel_lcdfb_info *sinfo) |
250 | { | 287 | { |
288 | struct atmel_lcdfb_pdata *pdata = &sinfo->pdata; | ||
289 | |||
251 | /* contrast pwm can be 'inverted' */ | 290 | /* contrast pwm can be 'inverted' */ |
252 | if (sinfo->lcdcon_pol_negative) | 291 | if (pdata->lcdcon_pol_negative) |
253 | contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE); | 292 | contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE); |
254 | 293 | ||
255 | /* have some default contrast/backlight settings */ | 294 | /* have some default contrast/backlight settings */ |
256 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); | 295 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); |
257 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); | 296 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); |
258 | 297 | ||
259 | if (sinfo->lcdcon_is_backlight) | 298 | if (pdata->lcdcon_is_backlight) |
260 | init_backlight(sinfo); | 299 | init_backlight(sinfo); |
261 | } | 300 | } |
262 | 301 | ||
302 | static inline void atmel_lcdfb_power_control(struct atmel_lcdfb_info *sinfo, int on) | ||
303 | { | ||
304 | struct atmel_lcdfb_pdata *pdata = &sinfo->pdata; | ||
305 | |||
306 | if (pdata->atmel_lcdfb_power_control) | ||
307 | pdata->atmel_lcdfb_power_control(pdata, on); | ||
308 | } | ||
263 | 309 | ||
264 | static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = { | 310 | static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = { |
265 | .type = FB_TYPE_PACKED_PIXELS, | 311 | .type = FB_TYPE_PACKED_PIXELS, |
@@ -299,9 +345,11 @@ static unsigned long compute_hozval(struct atmel_lcdfb_info *sinfo, | |||
299 | 345 | ||
300 | static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo) | 346 | static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo) |
301 | { | 347 | { |
348 | struct atmel_lcdfb_pdata *pdata = &sinfo->pdata; | ||
349 | |||
302 | /* Turn off the LCD controller and the DMA controller */ | 350 | /* Turn off the LCD controller and the DMA controller */ |
303 | lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, | 351 | lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, |
304 | sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET); | 352 | pdata->guard_time << ATMEL_LCDC_GUARDT_OFFSET); |
305 | 353 | ||
306 | /* Wait for the LCDC core to become idle */ | 354 | /* Wait for the LCDC core to become idle */ |
307 | while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) | 355 | while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) |
@@ -321,9 +369,11 @@ static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo) | |||
321 | 369 | ||
322 | static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo) | 370 | static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo) |
323 | { | 371 | { |
324 | lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon); | 372 | struct atmel_lcdfb_pdata *pdata = &sinfo->pdata; |
373 | |||
374 | lcdc_writel(sinfo, ATMEL_LCDC_DMACON, pdata->default_dmacon); | ||
325 | lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, | 375 | lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, |
326 | (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | 376 | (pdata->guard_time << ATMEL_LCDC_GUARDT_OFFSET) |
327 | | ATMEL_LCDC_PWR); | 377 | | ATMEL_LCDC_PWR); |
328 | } | 378 | } |
329 | 379 | ||
@@ -424,6 +474,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, | |||
424 | { | 474 | { |
425 | struct device *dev = info->device; | 475 | struct device *dev = info->device; |
426 | struct atmel_lcdfb_info *sinfo = info->par; | 476 | struct atmel_lcdfb_info *sinfo = info->par; |
477 | struct atmel_lcdfb_pdata *pdata = &sinfo->pdata; | ||
427 | unsigned long clk_value_khz; | 478 | unsigned long clk_value_khz; |
428 | 479 | ||
429 | clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; | 480 | clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; |
@@ -510,7 +561,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, | |||
510 | else | 561 | else |
511 | var->green.length = 6; | 562 | var->green.length = 6; |
512 | 563 | ||
513 | if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { | 564 | if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { |
514 | /* RGB:5X5 mode */ | 565 | /* RGB:5X5 mode */ |
515 | var->red.offset = var->green.length + 5; | 566 | var->red.offset = var->green.length + 5; |
516 | var->blue.offset = 0; | 567 | var->blue.offset = 0; |
@@ -527,7 +578,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, | |||
527 | var->transp.length = 8; | 578 | var->transp.length = 8; |
528 | /* fall through */ | 579 | /* fall through */ |
529 | case 24: | 580 | case 24: |
530 | if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { | 581 | if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { |
531 | /* RGB:888 mode */ | 582 | /* RGB:888 mode */ |
532 | var->red.offset = 16; | 583 | var->red.offset = 16; |
533 | var->blue.offset = 0; | 584 | var->blue.offset = 0; |
@@ -576,6 +627,7 @@ static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo) | |||
576 | static int atmel_lcdfb_set_par(struct fb_info *info) | 627 | static int atmel_lcdfb_set_par(struct fb_info *info) |
577 | { | 628 | { |
578 | struct atmel_lcdfb_info *sinfo = info->par; | 629 | struct atmel_lcdfb_info *sinfo = info->par; |
630 | struct atmel_lcdfb_pdata *pdata = &sinfo->pdata; | ||
579 | unsigned long hozval_linesz; | 631 | unsigned long hozval_linesz; |
580 | unsigned long value; | 632 | unsigned long value; |
581 | unsigned long clk_value_khz; | 633 | unsigned long clk_value_khz; |
@@ -637,7 +689,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info) | |||
637 | 689 | ||
638 | 690 | ||
639 | /* Initialize control register 2 */ | 691 | /* Initialize control register 2 */ |
640 | value = sinfo->default_lcdcon2; | 692 | value = pdata->default_lcdcon2; |
641 | 693 | ||
642 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) | 694 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) |
643 | value |= ATMEL_LCDC_INVLINE_INVERTED; | 695 | value |= ATMEL_LCDC_INVLINE_INVERTED; |
@@ -741,6 +793,7 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red, | |||
741 | unsigned int transp, struct fb_info *info) | 793 | unsigned int transp, struct fb_info *info) |
742 | { | 794 | { |
743 | struct atmel_lcdfb_info *sinfo = info->par; | 795 | struct atmel_lcdfb_info *sinfo = info->par; |
796 | struct atmel_lcdfb_pdata *pdata = &sinfo->pdata; | ||
744 | unsigned int val; | 797 | unsigned int val; |
745 | u32 *pal; | 798 | u32 *pal; |
746 | int ret = 1; | 799 | int ret = 1; |
@@ -777,8 +830,7 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red, | |||
777 | */ | 830 | */ |
778 | } else { | 831 | } else { |
779 | /* new style BGR:565 / RGB:565 */ | 832 | /* new style BGR:565 / RGB:565 */ |
780 | if (sinfo->lcd_wiring_mode == | 833 | if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { |
781 | ATMEL_LCDC_WIRING_RGB) { | ||
782 | val = ((blue >> 11) & 0x001f); | 834 | val = ((blue >> 11) & 0x001f); |
783 | val |= ((red >> 0) & 0xf800); | 835 | val |= ((red >> 0) & 0xf800); |
784 | } else { | 836 | } else { |
@@ -912,16 +964,187 @@ static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo) | |||
912 | clk_disable_unprepare(sinfo->lcdc_clk); | 964 | clk_disable_unprepare(sinfo->lcdc_clk); |
913 | } | 965 | } |
914 | 966 | ||
967 | #ifdef CONFIG_OF | ||
968 | static const struct of_device_id atmel_lcdfb_dt_ids[] = { | ||
969 | { .compatible = "atmel,at91sam9261-lcdc" , .data = &at91sam9261_config, }, | ||
970 | { .compatible = "atmel,at91sam9263-lcdc" , .data = &at91sam9263_config, }, | ||
971 | { .compatible = "atmel,at91sam9g10-lcdc" , .data = &at91sam9g10_config, }, | ||
972 | { .compatible = "atmel,at91sam9g45-lcdc" , .data = &at91sam9g45_config, }, | ||
973 | { .compatible = "atmel,at91sam9g45es-lcdc" , .data = &at91sam9g45es_config, }, | ||
974 | { .compatible = "atmel,at91sam9rl-lcdc" , .data = &at91sam9rl_config, }, | ||
975 | { .compatible = "atmel,at32ap-lcdc" , .data = &at32ap_config, }, | ||
976 | { /* sentinel */ } | ||
977 | }; | ||
978 | |||
979 | MODULE_DEVICE_TABLE(of, atmel_lcdfb_dt_ids); | ||
980 | |||
981 | static const char *atmel_lcdfb_wiring_modes[] = { | ||
982 | [ATMEL_LCDC_WIRING_BGR] = "BRG", | ||
983 | [ATMEL_LCDC_WIRING_RGB] = "RGB", | ||
984 | }; | ||
985 | |||
986 | const int atmel_lcdfb_get_of_wiring_modes(struct device_node *np) | ||
987 | { | ||
988 | const char *mode; | ||
989 | int err, i; | ||
990 | |||
991 | err = of_property_read_string(np, "atmel,lcd-wiring-mode", &mode); | ||
992 | if (err < 0) | ||
993 | return ATMEL_LCDC_WIRING_BGR; | ||
994 | |||
995 | for (i = 0; i < ARRAY_SIZE(atmel_lcdfb_wiring_modes); i++) | ||
996 | if (!strcasecmp(mode, atmel_lcdfb_wiring_modes[i])) | ||
997 | return i; | ||
998 | |||
999 | return -ENODEV; | ||
1000 | } | ||
1001 | |||
1002 | static void atmel_lcdfb_power_control_gpio(struct atmel_lcdfb_pdata *pdata, int on) | ||
1003 | { | ||
1004 | struct atmel_lcdfb_power_ctrl_gpio *og; | ||
1005 | |||
1006 | list_for_each_entry(og, &pdata->pwr_gpios, list) | ||
1007 | gpio_set_value(og->gpio, on); | ||
1008 | } | ||
1009 | |||
1010 | static int atmel_lcdfb_of_init(struct atmel_lcdfb_info *sinfo) | ||
1011 | { | ||
1012 | struct fb_info *info = sinfo->info; | ||
1013 | struct atmel_lcdfb_pdata *pdata = &sinfo->pdata; | ||
1014 | struct fb_var_screeninfo *var = &info->var; | ||
1015 | struct device *dev = &sinfo->pdev->dev; | ||
1016 | struct device_node *np =dev->of_node; | ||
1017 | struct device_node *display_np; | ||
1018 | struct device_node *timings_np; | ||
1019 | struct display_timings *timings; | ||
1020 | enum of_gpio_flags flags; | ||
1021 | struct atmel_lcdfb_power_ctrl_gpio *og; | ||
1022 | bool is_gpio_power = false; | ||
1023 | int ret = -ENOENT; | ||
1024 | int i, gpio; | ||
1025 | |||
1026 | sinfo->config = (struct atmel_lcdfb_config*) | ||
1027 | of_match_device(atmel_lcdfb_dt_ids, dev)->data; | ||
1028 | |||
1029 | display_np = of_parse_phandle(np, "display", 0); | ||
1030 | if (!display_np) { | ||
1031 | dev_err(dev, "failed to find display phandle\n"); | ||
1032 | return -ENOENT; | ||
1033 | } | ||
1034 | |||
1035 | ret = of_property_read_u32(display_np, "bits-per-pixel", &var->bits_per_pixel); | ||
1036 | if (ret < 0) { | ||
1037 | dev_err(dev, "failed to get property bits-per-pixel\n"); | ||
1038 | goto put_display_node; | ||
1039 | } | ||
1040 | |||
1041 | ret = of_property_read_u32(display_np, "atmel,guard-time", &pdata->guard_time); | ||
1042 | if (ret < 0) { | ||
1043 | dev_err(dev, "failed to get property atmel,guard-time\n"); | ||
1044 | goto put_display_node; | ||
1045 | } | ||
1046 | |||
1047 | ret = of_property_read_u32(display_np, "atmel,lcdcon2", &pdata->default_lcdcon2); | ||
1048 | if (ret < 0) { | ||
1049 | dev_err(dev, "failed to get property atmel,lcdcon2\n"); | ||
1050 | goto put_display_node; | ||
1051 | } | ||
1052 | |||
1053 | ret = of_property_read_u32(display_np, "atmel,dmacon", &pdata->default_dmacon); | ||
1054 | if (ret < 0) { | ||
1055 | dev_err(dev, "failed to get property bits-per-pixel\n"); | ||
1056 | goto put_display_node; | ||
1057 | } | ||
1058 | |||
1059 | ret = -ENOMEM; | ||
1060 | for (i = 0; i < of_gpio_named_count(display_np, "atmel,power-control-gpio"); i++) { | ||
1061 | gpio = of_get_named_gpio_flags(display_np, "atmel,power-control-gpio", | ||
1062 | i, &flags); | ||
1063 | if (gpio < 0) | ||
1064 | continue; | ||
1065 | |||
1066 | og = devm_kzalloc(dev, sizeof(*og), GFP_KERNEL); | ||
1067 | if (!og) | ||
1068 | goto put_display_node; | ||
1069 | |||
1070 | og->gpio = gpio; | ||
1071 | og->active_low = flags & OF_GPIO_ACTIVE_LOW; | ||
1072 | is_gpio_power = true; | ||
1073 | ret = devm_gpio_request(dev, gpio, "lcd-power-control-gpio"); | ||
1074 | if (ret) { | ||
1075 | dev_err(dev, "request gpio %d failed\n", gpio); | ||
1076 | goto put_display_node; | ||
1077 | } | ||
1078 | |||
1079 | ret = gpio_direction_output(gpio, og->active_low); | ||
1080 | if (ret) { | ||
1081 | dev_err(dev, "set direction output gpio %d failed\n", gpio); | ||
1082 | goto put_display_node; | ||
1083 | } | ||
1084 | } | ||
1085 | |||
1086 | if (is_gpio_power) | ||
1087 | pdata->atmel_lcdfb_power_control = atmel_lcdfb_power_control_gpio; | ||
1088 | |||
1089 | ret = atmel_lcdfb_get_of_wiring_modes(display_np); | ||
1090 | if (ret < 0) { | ||
1091 | dev_err(dev, "invalid atmel,lcd-wiring-mode\n"); | ||
1092 | goto put_display_node; | ||
1093 | } | ||
1094 | pdata->lcd_wiring_mode = ret; | ||
1095 | |||
1096 | pdata->lcdcon_is_backlight = of_property_read_bool(display_np, "atmel,lcdcon-backlight"); | ||
1097 | |||
1098 | timings = of_get_display_timings(display_np); | ||
1099 | if (!timings) { | ||
1100 | dev_err(dev, "failed to get display timings\n"); | ||
1101 | goto put_display_node; | ||
1102 | } | ||
1103 | |||
1104 | timings_np = of_find_node_by_name(display_np, "display-timings"); | ||
1105 | if (!timings_np) { | ||
1106 | dev_err(dev, "failed to find display-timings node\n"); | ||
1107 | goto put_display_node; | ||
1108 | } | ||
1109 | |||
1110 | for (i = 0; i < of_get_child_count(timings_np); i++) { | ||
1111 | struct videomode vm; | ||
1112 | struct fb_videomode fb_vm; | ||
1113 | |||
1114 | ret = videomode_from_timings(timings, &vm, i); | ||
1115 | if (ret < 0) | ||
1116 | goto put_timings_node; | ||
1117 | ret = fb_videomode_from_videomode(&vm, &fb_vm); | ||
1118 | if (ret < 0) | ||
1119 | goto put_timings_node; | ||
1120 | |||
1121 | fb_add_videomode(&fb_vm, &info->modelist); | ||
1122 | } | ||
1123 | |||
1124 | return 0; | ||
1125 | |||
1126 | put_timings_node: | ||
1127 | of_node_put(timings_np); | ||
1128 | put_display_node: | ||
1129 | of_node_put(display_np); | ||
1130 | return ret; | ||
1131 | } | ||
1132 | #else | ||
1133 | static int atmel_lcdfb_of_init(struct atmel_lcdfb_info *sinfo) | ||
1134 | { | ||
1135 | return 0; | ||
1136 | } | ||
1137 | #endif | ||
915 | 1138 | ||
916 | static int __init atmel_lcdfb_probe(struct platform_device *pdev) | 1139 | static int __init atmel_lcdfb_probe(struct platform_device *pdev) |
917 | { | 1140 | { |
918 | struct device *dev = &pdev->dev; | 1141 | struct device *dev = &pdev->dev; |
919 | struct fb_info *info; | 1142 | struct fb_info *info; |
920 | struct atmel_lcdfb_info *sinfo; | 1143 | struct atmel_lcdfb_info *sinfo; |
921 | struct atmel_lcdfb_info *pdata_sinfo; | 1144 | struct atmel_lcdfb_pdata *pdata = NULL; |
922 | struct fb_videomode fbmode; | ||
923 | struct resource *regs = NULL; | 1145 | struct resource *regs = NULL; |
924 | struct resource *map = NULL; | 1146 | struct resource *map = NULL; |
1147 | struct fb_modelist *modelist; | ||
925 | int ret; | 1148 | int ret; |
926 | 1149 | ||
927 | dev_dbg(dev, "%s BEGIN\n", __func__); | 1150 | dev_dbg(dev, "%s BEGIN\n", __func__); |
@@ -934,26 +1157,35 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev) | |||
934 | } | 1157 | } |
935 | 1158 | ||
936 | sinfo = info->par; | 1159 | sinfo = info->par; |
1160 | sinfo->pdev = pdev; | ||
1161 | sinfo->info = info; | ||
1162 | |||
1163 | INIT_LIST_HEAD(&info->modelist); | ||
937 | 1164 | ||
938 | if (dev->platform_data) { | 1165 | if (pdev->dev.of_node) { |
939 | pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data; | 1166 | ret = atmel_lcdfb_of_init(sinfo); |
940 | sinfo->default_bpp = pdata_sinfo->default_bpp; | 1167 | if (ret) |
941 | sinfo->default_dmacon = pdata_sinfo->default_dmacon; | 1168 | goto free_info; |
942 | sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2; | 1169 | } else if (dev_get_platdata(dev)) { |
943 | sinfo->default_monspecs = pdata_sinfo->default_monspecs; | 1170 | struct fb_monspecs *monspecs; |
944 | sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control; | 1171 | int i; |
945 | sinfo->guard_time = pdata_sinfo->guard_time; | 1172 | |
946 | sinfo->smem_len = pdata_sinfo->smem_len; | 1173 | pdata = dev_get_platdata(dev); |
947 | sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight; | 1174 | monspecs = pdata->default_monspecs; |
948 | sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative; | 1175 | sinfo->pdata = *pdata; |
949 | sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode; | 1176 | |
1177 | for (i = 0; i < monspecs->modedb_len; i++) | ||
1178 | fb_add_videomode(&monspecs->modedb[i], &info->modelist); | ||
1179 | |||
1180 | sinfo->config = atmel_lcdfb_get_config(pdev); | ||
1181 | |||
1182 | info->var.bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16; | ||
1183 | memcpy(&info->monspecs, pdata->default_monspecs, sizeof(info->monspecs)); | ||
950 | } else { | 1184 | } else { |
951 | dev_err(dev, "cannot get default configuration\n"); | 1185 | dev_err(dev, "cannot get default configuration\n"); |
952 | goto free_info; | 1186 | goto free_info; |
953 | } | 1187 | } |
954 | sinfo->info = info; | 1188 | |
955 | sinfo->pdev = pdev; | ||
956 | sinfo->config = atmel_lcdfb_get_config(pdev); | ||
957 | if (!sinfo->config) | 1189 | if (!sinfo->config) |
958 | goto free_info; | 1190 | goto free_info; |
959 | 1191 | ||
@@ -962,7 +1194,6 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev) | |||
962 | info->pseudo_palette = sinfo->pseudo_palette; | 1194 | info->pseudo_palette = sinfo->pseudo_palette; |
963 | info->fbops = &atmel_lcdfb_ops; | 1195 | info->fbops = &atmel_lcdfb_ops; |
964 | 1196 | ||
965 | memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs)); | ||
966 | info->fix = atmel_lcdfb_fix; | 1197 | info->fix = atmel_lcdfb_fix; |
967 | 1198 | ||
968 | /* Enable LCDC Clocks */ | 1199 | /* Enable LCDC Clocks */ |
@@ -978,14 +1209,11 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev) | |||
978 | } | 1209 | } |
979 | atmel_lcdfb_start_clock(sinfo); | 1210 | atmel_lcdfb_start_clock(sinfo); |
980 | 1211 | ||
981 | ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb, | 1212 | modelist = list_first_entry(&info->modelist, |
982 | info->monspecs.modedb_len, info->monspecs.modedb, | 1213 | struct fb_modelist, list); |
983 | sinfo->default_bpp); | 1214 | fb_videomode_to_var(&info->var, &modelist->mode); |
984 | if (!ret) { | ||
985 | dev_err(dev, "no suitable video mode found\n"); | ||
986 | goto stop_clk; | ||
987 | } | ||
988 | 1215 | ||
1216 | atmel_lcdfb_check_var(&info->var, info); | ||
989 | 1217 | ||
990 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1218 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
991 | if (!regs) { | 1219 | if (!regs) { |
@@ -1069,18 +1297,6 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev) | |||
1069 | goto unregister_irqs; | 1297 | goto unregister_irqs; |
1070 | } | 1298 | } |
1071 | 1299 | ||
1072 | /* | ||
1073 | * This makes sure that our colour bitfield | ||
1074 | * descriptors are correctly initialised. | ||
1075 | */ | ||
1076 | atmel_lcdfb_check_var(&info->var, info); | ||
1077 | |||
1078 | ret = fb_set_var(info, &info->var); | ||
1079 | if (ret) { | ||
1080 | dev_warn(dev, "unable to set display parameters\n"); | ||
1081 | goto free_cmap; | ||
1082 | } | ||
1083 | |||
1084 | dev_set_drvdata(dev, info); | 1300 | dev_set_drvdata(dev, info); |
1085 | 1301 | ||
1086 | /* | 1302 | /* |
@@ -1092,13 +1308,8 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev) | |||
1092 | goto reset_drvdata; | 1308 | goto reset_drvdata; |
1093 | } | 1309 | } |
1094 | 1310 | ||
1095 | /* add selected videomode to modelist */ | ||
1096 | fb_var_to_videomode(&fbmode, &info->var); | ||
1097 | fb_add_videomode(&fbmode, &info->modelist); | ||
1098 | |||
1099 | /* Power up the LCDC screen */ | 1311 | /* Power up the LCDC screen */ |
1100 | if (sinfo->atmel_lcdfb_power_control) | 1312 | atmel_lcdfb_power_control(sinfo, 1); |
1101 | sinfo->atmel_lcdfb_power_control(1); | ||
1102 | 1313 | ||
1103 | dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n", | 1314 | dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n", |
1104 | info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base); | 1315 | info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base); |
@@ -1107,7 +1318,6 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev) | |||
1107 | 1318 | ||
1108 | reset_drvdata: | 1319 | reset_drvdata: |
1109 | dev_set_drvdata(dev, NULL); | 1320 | dev_set_drvdata(dev, NULL); |
1110 | free_cmap: | ||
1111 | fb_dealloc_cmap(&info->cmap); | 1321 | fb_dealloc_cmap(&info->cmap); |
1112 | unregister_irqs: | 1322 | unregister_irqs: |
1113 | cancel_work_sync(&sinfo->task); | 1323 | cancel_work_sync(&sinfo->task); |
@@ -1143,15 +1353,16 @@ static int __exit atmel_lcdfb_remove(struct platform_device *pdev) | |||
1143 | struct device *dev = &pdev->dev; | 1353 | struct device *dev = &pdev->dev; |
1144 | struct fb_info *info = dev_get_drvdata(dev); | 1354 | struct fb_info *info = dev_get_drvdata(dev); |
1145 | struct atmel_lcdfb_info *sinfo; | 1355 | struct atmel_lcdfb_info *sinfo; |
1356 | struct atmel_lcdfb_pdata *pdata; | ||
1146 | 1357 | ||
1147 | if (!info || !info->par) | 1358 | if (!info || !info->par) |
1148 | return 0; | 1359 | return 0; |
1149 | sinfo = info->par; | 1360 | sinfo = info->par; |
1361 | pdata = &sinfo->pdata; | ||
1150 | 1362 | ||
1151 | cancel_work_sync(&sinfo->task); | 1363 | cancel_work_sync(&sinfo->task); |
1152 | exit_backlight(sinfo); | 1364 | exit_backlight(sinfo); |
1153 | if (sinfo->atmel_lcdfb_power_control) | 1365 | atmel_lcdfb_power_control(sinfo, 0); |
1154 | sinfo->atmel_lcdfb_power_control(0); | ||
1155 | unregister_framebuffer(info); | 1366 | unregister_framebuffer(info); |
1156 | atmel_lcdfb_stop_clock(sinfo); | 1367 | atmel_lcdfb_stop_clock(sinfo); |
1157 | clk_put(sinfo->lcdc_clk); | 1368 | clk_put(sinfo->lcdc_clk); |
@@ -1167,7 +1378,6 @@ static int __exit atmel_lcdfb_remove(struct platform_device *pdev) | |||
1167 | atmel_lcdfb_free_video_memory(sinfo); | 1378 | atmel_lcdfb_free_video_memory(sinfo); |
1168 | } | 1379 | } |
1169 | 1380 | ||
1170 | dev_set_drvdata(dev, NULL); | ||
1171 | framebuffer_release(info); | 1381 | framebuffer_release(info); |
1172 | 1382 | ||
1173 | return 0; | 1383 | return 0; |
@@ -1188,9 +1398,7 @@ static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg) | |||
1188 | 1398 | ||
1189 | sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_CTR); | 1399 | sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_CTR); |
1190 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0); | 1400 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0); |
1191 | if (sinfo->atmel_lcdfb_power_control) | 1401 | atmel_lcdfb_power_control(sinfo, 0); |
1192 | sinfo->atmel_lcdfb_power_control(0); | ||
1193 | |||
1194 | atmel_lcdfb_stop(sinfo); | 1402 | atmel_lcdfb_stop(sinfo); |
1195 | atmel_lcdfb_stop_clock(sinfo); | 1403 | atmel_lcdfb_stop_clock(sinfo); |
1196 | 1404 | ||
@@ -1204,8 +1412,7 @@ static int atmel_lcdfb_resume(struct platform_device *pdev) | |||
1204 | 1412 | ||
1205 | atmel_lcdfb_start_clock(sinfo); | 1413 | atmel_lcdfb_start_clock(sinfo); |
1206 | atmel_lcdfb_start(sinfo); | 1414 | atmel_lcdfb_start(sinfo); |
1207 | if (sinfo->atmel_lcdfb_power_control) | 1415 | atmel_lcdfb_power_control(sinfo, 1); |
1208 | sinfo->atmel_lcdfb_power_control(1); | ||
1209 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon); | 1416 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon); |
1210 | 1417 | ||
1211 | /* Enable FIFO & DMA errors */ | 1418 | /* Enable FIFO & DMA errors */ |
@@ -1228,6 +1435,7 @@ static struct platform_driver atmel_lcdfb_driver = { | |||
1228 | .driver = { | 1435 | .driver = { |
1229 | .name = "atmel_lcdfb", | 1436 | .name = "atmel_lcdfb", |
1230 | .owner = THIS_MODULE, | 1437 | .owner = THIS_MODULE, |
1438 | .of_match_table = of_match_ptr(atmel_lcdfb_dt_ids), | ||
1231 | }, | 1439 | }, |
1232 | }; | 1440 | }; |
1233 | 1441 | ||
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c index a4dfe8cb0a0a..12ca031877d4 100644 --- a/drivers/video/aty/aty128fb.c +++ b/drivers/video/aty/aty128fb.c | |||
@@ -413,7 +413,6 @@ struct aty128fb_par { | |||
413 | int blitter_may_be_busy; | 413 | int blitter_may_be_busy; |
414 | int fifo_slots; /* free slots in FIFO (64 max) */ | 414 | int fifo_slots; /* free slots in FIFO (64 max) */ |
415 | 415 | ||
416 | int pm_reg; | ||
417 | int crt_on, lcd_on; | 416 | int crt_on, lcd_on; |
418 | struct pci_dev *pdev; | 417 | struct pci_dev *pdev; |
419 | struct fb_info *next; | 418 | struct fb_info *next; |
@@ -2016,7 +2015,6 @@ static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2016 | 2015 | ||
2017 | aty128_init_engine(par); | 2016 | aty128_init_engine(par); |
2018 | 2017 | ||
2019 | par->pm_reg = pdev->pm_cap; | ||
2020 | par->pdev = pdev; | 2018 | par->pdev = pdev; |
2021 | par->asleep = 0; | 2019 | par->asleep = 0; |
2022 | par->lock_blank = 0; | 2020 | par->lock_blank = 0; |
@@ -2029,8 +2027,8 @@ static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2029 | if (register_framebuffer(info) < 0) | 2027 | if (register_framebuffer(info) < 0) |
2030 | return 0; | 2028 | return 0; |
2031 | 2029 | ||
2032 | printk(KERN_INFO "fb%d: %s frame buffer device on %s\n", | 2030 | fb_info(info, "%s frame buffer device on %s\n", |
2033 | info->node, info->fix.id, video_card); | 2031 | info->fix.id, video_card); |
2034 | 2032 | ||
2035 | return 1; /* success! */ | 2033 | return 1; /* success! */ |
2036 | } | 2034 | } |
@@ -2397,7 +2395,7 @@ static void aty128_set_suspend(struct aty128fb_par *par, int suspend) | |||
2397 | u32 pmgt; | 2395 | u32 pmgt; |
2398 | struct pci_dev *pdev = par->pdev; | 2396 | struct pci_dev *pdev = par->pdev; |
2399 | 2397 | ||
2400 | if (!par->pm_reg) | 2398 | if (!par->pdev->pm_cap) |
2401 | return; | 2399 | return; |
2402 | 2400 | ||
2403 | /* Set the chip into the appropriate suspend mode (we use D2, | 2401 | /* Set the chip into the appropriate suspend mode (we use D2, |
diff --git a/drivers/video/aty/atyfb_base.c b/drivers/video/aty/atyfb_base.c index 9b0f12c5c284..28fafbf864a5 100644 --- a/drivers/video/aty/atyfb_base.c +++ b/drivers/video/aty/atyfb_base.c | |||
@@ -1848,7 +1848,6 @@ static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg) | |||
1848 | 1848 | ||
1849 | return aty_waitforvblank(par, crtc); | 1849 | return aty_waitforvblank(par, crtc); |
1850 | } | 1850 | } |
1851 | break; | ||
1852 | 1851 | ||
1853 | #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT) | 1852 | #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT) |
1854 | case ATYIO_CLKR: | 1853 | case ATYIO_CLKR: |
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c index 1e30b2b3e79f..26d80a4486fb 100644 --- a/drivers/video/aty/radeon_base.c +++ b/drivers/video/aty/radeon_base.c | |||
@@ -819,11 +819,6 @@ static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *in | |||
819 | if (v.xres_virtual < v.xres) | 819 | if (v.xres_virtual < v.xres) |
820 | v.xres = v.xres_virtual; | 820 | v.xres = v.xres_virtual; |
821 | 821 | ||
822 | if (v.xoffset < 0) | ||
823 | v.xoffset = 0; | ||
824 | if (v.yoffset < 0) | ||
825 | v.yoffset = 0; | ||
826 | |||
827 | if (v.xoffset > v.xres_virtual - v.xres) | 822 | if (v.xoffset > v.xres_virtual - v.xres) |
828 | v.xoffset = v.xres_virtual - v.xres - 1; | 823 | v.xoffset = v.xres_virtual - v.xres - 1; |
829 | 824 | ||
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c index f7091ece580d..46a12f1a93c3 100644 --- a/drivers/video/aty/radeon_pm.c +++ b/drivers/video/aty/radeon_pm.c | |||
@@ -1427,6 +1427,8 @@ static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo) | |||
1427 | mdelay( 15); | 1427 | mdelay( 15); |
1428 | } | 1428 | } |
1429 | 1429 | ||
1430 | #if defined(CONFIG_PM) | ||
1431 | #if defined(CONFIG_X86) || defined(CONFIG_PPC_PMAC) | ||
1430 | static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo) | 1432 | static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo) |
1431 | { | 1433 | { |
1432 | u32 tmp, tmp2; | 1434 | u32 tmp, tmp2; |
@@ -1939,9 +1941,10 @@ static void radeon_reinitialize_M10(struct radeonfb_info *rinfo) | |||
1939 | */ | 1941 | */ |
1940 | radeon_pm_m10_enable_lvds_spread_spectrum(rinfo); | 1942 | radeon_pm_m10_enable_lvds_spread_spectrum(rinfo); |
1941 | } | 1943 | } |
1944 | #endif | ||
1942 | 1945 | ||
1943 | #ifdef CONFIG_PPC_OF | 1946 | #ifdef CONFIG_PPC_OF |
1944 | 1947 | #ifdef CONFIG_PPC_PMAC | |
1945 | static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo) | 1948 | static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo) |
1946 | { | 1949 | { |
1947 | OUTREG(MC_CNTL, rinfo->save_regs[46]); | 1950 | OUTREG(MC_CNTL, rinfo->save_regs[46]); |
@@ -2202,6 +2205,8 @@ static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo) | |||
2202 | radeon_pm_restore_pixel_pll(rinfo); | 2205 | radeon_pm_restore_pixel_pll(rinfo); |
2203 | radeon_pm_m10_enable_lvds_spread_spectrum(rinfo); | 2206 | radeon_pm_m10_enable_lvds_spread_spectrum(rinfo); |
2204 | } | 2207 | } |
2208 | #endif | ||
2209 | #endif | ||
2205 | 2210 | ||
2206 | #if 0 /* Not ready yet */ | 2211 | #if 0 /* Not ready yet */ |
2207 | static void radeon_reinitialize_QW(struct radeonfb_info *rinfo) | 2212 | static void radeon_reinitialize_QW(struct radeonfb_info *rinfo) |
@@ -2515,13 +2520,13 @@ static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t | |||
2515 | 2520 | ||
2516 | for (;;) { | 2521 | for (;;) { |
2517 | pci_read_config_word(rinfo->pdev, | 2522 | pci_read_config_word(rinfo->pdev, |
2518 | rinfo->pm_reg+PCI_PM_CTRL, | 2523 | rinfo->pdev->pm_cap + PCI_PM_CTRL, |
2519 | &pwr_cmd); | 2524 | &pwr_cmd); |
2520 | if (pwr_cmd & 2) | 2525 | if (pwr_cmd & state) |
2521 | break; | 2526 | break; |
2522 | pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2; | 2527 | pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | state; |
2523 | pci_write_config_word(rinfo->pdev, | 2528 | pci_write_config_word(rinfo->pdev, |
2524 | rinfo->pm_reg+PCI_PM_CTRL, | 2529 | rinfo->pdev->pm_cap + PCI_PM_CTRL, |
2525 | pwr_cmd); | 2530 | pwr_cmd); |
2526 | msleep(500); | 2531 | msleep(500); |
2527 | } | 2532 | } |
@@ -2532,7 +2537,7 @@ static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend) | |||
2532 | { | 2537 | { |
2533 | u32 tmp; | 2538 | u32 tmp; |
2534 | 2539 | ||
2535 | if (!rinfo->pm_reg) | 2540 | if (!rinfo->pdev->pm_cap) |
2536 | return; | 2541 | return; |
2537 | 2542 | ||
2538 | /* Set the chip into appropriate suspend mode (we use D2, | 2543 | /* Set the chip into appropriate suspend mode (we use D2, |
@@ -2804,9 +2809,6 @@ static void radeonfb_early_resume(void *data) | |||
2804 | 2809 | ||
2805 | void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep) | 2810 | void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep) |
2806 | { | 2811 | { |
2807 | /* Find PM registers in config space if any*/ | ||
2808 | rinfo->pm_reg = rinfo->pdev->pm_cap; | ||
2809 | |||
2810 | /* Enable/Disable dynamic clocks: TODO add sysfs access */ | 2812 | /* Enable/Disable dynamic clocks: TODO add sysfs access */ |
2811 | if (rinfo->family == CHIP_FAMILY_RS480) | 2813 | if (rinfo->family == CHIP_FAMILY_RS480) |
2812 | rinfo->dynclk = -1; | 2814 | rinfo->dynclk = -1; |
@@ -2830,7 +2832,7 @@ void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlis | |||
2830 | * reason. --BenH | 2832 | * reason. --BenH |
2831 | */ | 2833 | */ |
2832 | if (machine_is(powermac) && rinfo->of_node) { | 2834 | if (machine_is(powermac) && rinfo->of_node) { |
2833 | if (rinfo->is_mobility && rinfo->pm_reg && | 2835 | if (rinfo->is_mobility && rinfo->pdev->pm_cap && |
2834 | rinfo->family <= CHIP_FAMILY_RV250) | 2836 | rinfo->family <= CHIP_FAMILY_RV250) |
2835 | rinfo->pm_mode |= radeon_pm_d2; | 2837 | rinfo->pm_mode |= radeon_pm_d2; |
2836 | 2838 | ||
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h index 7351e66c7f54..cb846044f57c 100644 --- a/drivers/video/aty/radeonfb.h +++ b/drivers/video/aty/radeonfb.h | |||
@@ -342,7 +342,6 @@ struct radeonfb_info { | |||
342 | 342 | ||
343 | int mtrr_hdl; | 343 | int mtrr_hdl; |
344 | 344 | ||
345 | int pm_reg; | ||
346 | u32 save_regs[100]; | 345 | u32 save_regs[100]; |
347 | int asleep; | 346 | int asleep; |
348 | int lock_blank; | 347 | int lock_blank; |
diff --git a/drivers/video/au1100fb.c b/drivers/video/au1100fb.c index 22ad85242e5b..372d4aea9d1c 100644 --- a/drivers/video/au1100fb.c +++ b/drivers/video/au1100fb.c | |||
@@ -564,7 +564,7 @@ int au1100fb_drv_remove(struct platform_device *dev) | |||
564 | if (!dev) | 564 | if (!dev) |
565 | return -ENODEV; | 565 | return -ENODEV; |
566 | 566 | ||
567 | fbdev = (struct au1100fb_device *) platform_get_drvdata(dev); | 567 | fbdev = platform_get_drvdata(dev); |
568 | 568 | ||
569 | #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO) | 569 | #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO) |
570 | au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info); | 570 | au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info); |
@@ -636,19 +636,7 @@ static struct platform_driver au1100fb_driver = { | |||
636 | .suspend = au1100fb_drv_suspend, | 636 | .suspend = au1100fb_drv_suspend, |
637 | .resume = au1100fb_drv_resume, | 637 | .resume = au1100fb_drv_resume, |
638 | }; | 638 | }; |
639 | 639 | module_platform_driver(au1100fb_driver); | |
640 | static int __init au1100fb_load(void) | ||
641 | { | ||
642 | return platform_driver_register(&au1100fb_driver); | ||
643 | } | ||
644 | |||
645 | static void __exit au1100fb_unload(void) | ||
646 | { | ||
647 | platform_driver_unregister(&au1100fb_driver); | ||
648 | } | ||
649 | |||
650 | module_init(au1100fb_load); | ||
651 | module_exit(au1100fb_unload); | ||
652 | 640 | ||
653 | MODULE_DESCRIPTION(DRIVER_DESC); | 641 | MODULE_DESCRIPTION(DRIVER_DESC); |
654 | MODULE_LICENSE("GPL"); | 642 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c index 1d02897d17f2..4cfba78a1458 100644 --- a/drivers/video/au1200fb.c +++ b/drivers/video/au1200fb.c | |||
@@ -1853,21 +1853,7 @@ static struct platform_driver au1200fb_driver = { | |||
1853 | .probe = au1200fb_drv_probe, | 1853 | .probe = au1200fb_drv_probe, |
1854 | .remove = au1200fb_drv_remove, | 1854 | .remove = au1200fb_drv_remove, |
1855 | }; | 1855 | }; |
1856 | 1856 | module_platform_driver(au1200fb_driver); | |
1857 | /*-------------------------------------------------------------------------*/ | ||
1858 | |||
1859 | static int __init au1200fb_init(void) | ||
1860 | { | ||
1861 | return platform_driver_register(&au1200fb_driver); | ||
1862 | } | ||
1863 | |||
1864 | static void __exit au1200fb_cleanup(void) | ||
1865 | { | ||
1866 | platform_driver_unregister(&au1200fb_driver); | ||
1867 | } | ||
1868 | |||
1869 | module_init(au1200fb_init); | ||
1870 | module_exit(au1200fb_cleanup); | ||
1871 | 1857 | ||
1872 | MODULE_DESCRIPTION(DRIVER_DESC); | 1858 | MODULE_DESCRIPTION(DRIVER_DESC); |
1873 | MODULE_LICENSE("GPL"); | 1859 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/video/backlight/l4f00242t03.c b/drivers/video/backlight/l4f00242t03.c index 923eae2f85f8..b5fc13bc24e7 100644 --- a/drivers/video/backlight/l4f00242t03.c +++ b/drivers/video/backlight/l4f00242t03.c | |||
@@ -244,7 +244,6 @@ static int l4f00242t03_remove(struct spi_device *spi) | |||
244 | 244 | ||
245 | l4f00242t03_lcd_power_set(priv->ld, FB_BLANK_POWERDOWN); | 245 | l4f00242t03_lcd_power_set(priv->ld, FB_BLANK_POWERDOWN); |
246 | lcd_device_unregister(priv->ld); | 246 | lcd_device_unregister(priv->ld); |
247 | spi_set_drvdata(spi, NULL); | ||
248 | 247 | ||
249 | return 0; | 248 | return 0; |
250 | } | 249 | } |
diff --git a/drivers/video/backlight/tosa_lcd.c b/drivers/video/backlight/tosa_lcd.c index bf081573e5b5..be5d636764bf 100644 --- a/drivers/video/backlight/tosa_lcd.c +++ b/drivers/video/backlight/tosa_lcd.c | |||
@@ -198,7 +198,7 @@ static int tosa_lcd_probe(struct spi_device *spi) | |||
198 | ret = devm_gpio_request_one(&spi->dev, TOSA_GPIO_TG_ON, | 198 | ret = devm_gpio_request_one(&spi->dev, TOSA_GPIO_TG_ON, |
199 | GPIOF_OUT_INIT_LOW, "tg #pwr"); | 199 | GPIOF_OUT_INIT_LOW, "tg #pwr"); |
200 | if (ret < 0) | 200 | if (ret < 0) |
201 | goto err_gpio_tg; | 201 | return ret; |
202 | 202 | ||
203 | mdelay(60); | 203 | mdelay(60); |
204 | 204 | ||
@@ -219,8 +219,6 @@ static int tosa_lcd_probe(struct spi_device *spi) | |||
219 | 219 | ||
220 | err_register: | 220 | err_register: |
221 | tosa_lcd_tg_off(data); | 221 | tosa_lcd_tg_off(data); |
222 | err_gpio_tg: | ||
223 | spi_set_drvdata(spi, NULL); | ||
224 | return ret; | 222 | return ret; |
225 | } | 223 | } |
226 | 224 | ||
@@ -235,8 +233,6 @@ static int tosa_lcd_remove(struct spi_device *spi) | |||
235 | 233 | ||
236 | tosa_lcd_tg_off(data); | 234 | tosa_lcd_tg_off(data); |
237 | 235 | ||
238 | spi_set_drvdata(spi, NULL); | ||
239 | |||
240 | return 0; | 236 | return 0; |
241 | } | 237 | } |
242 | 238 | ||
diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c index 87f288bfc58c..42b8f9d11018 100644 --- a/drivers/video/bf54x-lq043fb.c +++ b/drivers/video/bf54x-lq043fb.c | |||
@@ -761,19 +761,7 @@ static struct platform_driver bfin_bf54x_driver = { | |||
761 | .owner = THIS_MODULE, | 761 | .owner = THIS_MODULE, |
762 | }, | 762 | }, |
763 | }; | 763 | }; |
764 | 764 | module_platform_driver(bfin_bf54x_driver); | |
765 | static int __init bfin_bf54x_driver_init(void) | ||
766 | { | ||
767 | return platform_driver_register(&bfin_bf54x_driver); | ||
768 | } | ||
769 | |||
770 | static void __exit bfin_bf54x_driver_cleanup(void) | ||
771 | { | ||
772 | platform_driver_unregister(&bfin_bf54x_driver); | ||
773 | } | ||
774 | 765 | ||
775 | MODULE_DESCRIPTION("Blackfin BF54x TFT LCD Driver"); | 766 | MODULE_DESCRIPTION("Blackfin BF54x TFT LCD Driver"); |
776 | MODULE_LICENSE("GPL"); | 767 | MODULE_LICENSE("GPL"); |
777 | |||
778 | module_init(bfin_bf54x_driver_init); | ||
779 | module_exit(bfin_bf54x_driver_cleanup); | ||
diff --git a/drivers/video/bfin-t350mcqb-fb.c b/drivers/video/bfin-t350mcqb-fb.c index 48c0c4e38a62..b5cf1307a3d9 100644 --- a/drivers/video/bfin-t350mcqb-fb.c +++ b/drivers/video/bfin-t350mcqb-fb.c | |||
@@ -664,19 +664,7 @@ static struct platform_driver bfin_t350mcqb_driver = { | |||
664 | .owner = THIS_MODULE, | 664 | .owner = THIS_MODULE, |
665 | }, | 665 | }, |
666 | }; | 666 | }; |
667 | 667 | module_platform_driver(bfin_t350mcqb_driver); | |
668 | static int __init bfin_t350mcqb_driver_init(void) | ||
669 | { | ||
670 | return platform_driver_register(&bfin_t350mcqb_driver); | ||
671 | } | ||
672 | |||
673 | static void __exit bfin_t350mcqb_driver_cleanup(void) | ||
674 | { | ||
675 | platform_driver_unregister(&bfin_t350mcqb_driver); | ||
676 | } | ||
677 | 668 | ||
678 | MODULE_DESCRIPTION("Blackfin TFT LCD Driver"); | 669 | MODULE_DESCRIPTION("Blackfin TFT LCD Driver"); |
679 | MODULE_LICENSE("GPL"); | 670 | MODULE_LICENSE("GPL"); |
680 | |||
681 | module_init(bfin_t350mcqb_driver_init); | ||
682 | module_exit(bfin_t350mcqb_driver_cleanup); | ||
diff --git a/drivers/video/broadsheetfb.c b/drivers/video/broadsheetfb.c index b09701c79432..8556264b16b7 100644 --- a/drivers/video/broadsheetfb.c +++ b/drivers/video/broadsheetfb.c | |||
@@ -1167,9 +1167,8 @@ static int broadsheetfb_probe(struct platform_device *dev) | |||
1167 | if (retval < 0) | 1167 | if (retval < 0) |
1168 | goto err_unreg_fb; | 1168 | goto err_unreg_fb; |
1169 | 1169 | ||
1170 | printk(KERN_INFO | 1170 | fb_info(info, "Broadsheet frame buffer, using %dK of video memory\n", |
1171 | "fb%d: Broadsheet frame buffer, using %dK of video memory\n", | 1171 | videomemorysize >> 10); |
1172 | info->node, videomemorysize >> 10); | ||
1173 | 1172 | ||
1174 | 1173 | ||
1175 | return 0; | 1174 | return 0; |
@@ -1217,19 +1216,7 @@ static struct platform_driver broadsheetfb_driver = { | |||
1217 | .name = "broadsheetfb", | 1216 | .name = "broadsheetfb", |
1218 | }, | 1217 | }, |
1219 | }; | 1218 | }; |
1220 | 1219 | module_platform_driver(broadsheetfb_driver); | |
1221 | static int __init broadsheetfb_init(void) | ||
1222 | { | ||
1223 | return platform_driver_register(&broadsheetfb_driver); | ||
1224 | } | ||
1225 | |||
1226 | static void __exit broadsheetfb_exit(void) | ||
1227 | { | ||
1228 | platform_driver_unregister(&broadsheetfb_driver); | ||
1229 | } | ||
1230 | |||
1231 | module_init(broadsheetfb_init); | ||
1232 | module_exit(broadsheetfb_exit); | ||
1233 | 1220 | ||
1234 | MODULE_DESCRIPTION("fbdev driver for Broadsheet controller"); | 1221 | MODULE_DESCRIPTION("fbdev driver for Broadsheet controller"); |
1235 | MODULE_AUTHOR("Jaya Kumar"); | 1222 | MODULE_AUTHOR("Jaya Kumar"); |
diff --git a/drivers/video/bw2.c b/drivers/video/bw2.c index 60017fc634b5..bc123d6947a4 100644 --- a/drivers/video/bw2.c +++ b/drivers/video/bw2.c | |||
@@ -363,8 +363,6 @@ static int bw2_remove(struct platform_device *op) | |||
363 | 363 | ||
364 | framebuffer_release(info); | 364 | framebuffer_release(info); |
365 | 365 | ||
366 | dev_set_drvdata(&op->dev, NULL); | ||
367 | |||
368 | return 0; | 366 | return 0; |
369 | } | 367 | } |
370 | 368 | ||
diff --git a/drivers/video/carminefb.c b/drivers/video/carminefb.c index 153dd65b0ae8..65f7c15f5fdb 100644 --- a/drivers/video/carminefb.c +++ b/drivers/video/carminefb.c | |||
@@ -585,8 +585,7 @@ static int alloc_carmine_fb(void __iomem *regs, void __iomem *smem_base, | |||
585 | if (ret < 0) | 585 | if (ret < 0) |
586 | goto err_dealloc_cmap; | 586 | goto err_dealloc_cmap; |
587 | 587 | ||
588 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, | 588 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
589 | info->fix.id); | ||
590 | 589 | ||
591 | *rinfo = info; | 590 | *rinfo = info; |
592 | return 0; | 591 | return 0; |
@@ -746,7 +745,6 @@ static void carminefb_remove(struct pci_dev *dev) | |||
746 | iounmap(hw->v_regs); | 745 | iounmap(hw->v_regs); |
747 | release_mem_region(fix.mmio_start, fix.mmio_len); | 746 | release_mem_region(fix.mmio_start, fix.mmio_len); |
748 | 747 | ||
749 | pci_set_drvdata(dev, NULL); | ||
750 | pci_disable_device(dev); | 748 | pci_disable_device(dev); |
751 | kfree(hw); | 749 | kfree(hw); |
752 | } | 750 | } |
diff --git a/drivers/video/cfbimgblt.c b/drivers/video/cfbimgblt.c index baed57d3cfff..a2bb276a8b24 100644 --- a/drivers/video/cfbimgblt.c +++ b/drivers/video/cfbimgblt.c | |||
@@ -181,7 +181,7 @@ static inline void slow_imageblit(const struct fb_image *image, struct fb_info * | |||
181 | } | 181 | } |
182 | shift += bpp; | 182 | shift += bpp; |
183 | shift &= (32 - 1); | 183 | shift &= (32 - 1); |
184 | if (!l) { l = 8; s++; }; | 184 | if (!l) { l = 8; s++; } |
185 | } | 185 | } |
186 | 186 | ||
187 | /* write trailing bits */ | 187 | /* write trailing bits */ |
diff --git a/drivers/video/cg14.c b/drivers/video/cg14.c index ed3b8891e006..c79745b136bb 100644 --- a/drivers/video/cg14.c +++ b/drivers/video/cg14.c | |||
@@ -330,7 +330,7 @@ static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) | |||
330 | default: | 330 | default: |
331 | ret = -ENOSYS; | 331 | ret = -ENOSYS; |
332 | break; | 332 | break; |
333 | }; | 333 | } |
334 | if (!ret) { | 334 | if (!ret) { |
335 | sbus_writeb(cur_mode, ®s->mcr); | 335 | sbus_writeb(cur_mode, ®s->mcr); |
336 | par->mode = mode; | 336 | par->mode = mode; |
@@ -343,7 +343,7 @@ static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) | |||
343 | FBTYPE_MDICOLOR, 8, | 343 | FBTYPE_MDICOLOR, 8, |
344 | info->fix.smem_len); | 344 | info->fix.smem_len); |
345 | break; | 345 | break; |
346 | }; | 346 | } |
347 | 347 | ||
348 | return ret; | 348 | return ret; |
349 | } | 349 | } |
@@ -583,8 +583,6 @@ static int cg14_remove(struct platform_device *op) | |||
583 | 583 | ||
584 | framebuffer_release(info); | 584 | framebuffer_release(info); |
585 | 585 | ||
586 | dev_set_drvdata(&op->dev, NULL); | ||
587 | |||
588 | return 0; | 586 | return 0; |
589 | } | 587 | } |
590 | 588 | ||
diff --git a/drivers/video/cg3.c b/drivers/video/cg3.c index 9f63507ded37..64a89d5747ed 100644 --- a/drivers/video/cg3.c +++ b/drivers/video/cg3.c | |||
@@ -446,8 +446,6 @@ static int cg3_remove(struct platform_device *op) | |||
446 | 446 | ||
447 | framebuffer_release(info); | 447 | framebuffer_release(info); |
448 | 448 | ||
449 | dev_set_drvdata(&op->dev, NULL); | ||
450 | |||
451 | return 0; | 449 | return 0; |
452 | } | 450 | } |
453 | 451 | ||
diff --git a/drivers/video/cg6.c b/drivers/video/cg6.c index 3545decc7485..70781fea092a 100644 --- a/drivers/video/cg6.c +++ b/drivers/video/cg6.c | |||
@@ -624,7 +624,7 @@ static void cg6_init_fix(struct fb_info *info, int linebytes) | |||
624 | default: | 624 | default: |
625 | cg6_cpu_name = "i386"; | 625 | cg6_cpu_name = "i386"; |
626 | break; | 626 | break; |
627 | }; | 627 | } |
628 | if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) { | 628 | if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) { |
629 | if (info->fix.smem_len <= 0x100000) | 629 | if (info->fix.smem_len <= 0x100000) |
630 | cg6_card_name = "TGX"; | 630 | cg6_card_name = "TGX"; |
@@ -839,8 +839,6 @@ static int cg6_remove(struct platform_device *op) | |||
839 | 839 | ||
840 | framebuffer_release(info); | 840 | framebuffer_release(info); |
841 | 841 | ||
842 | dev_set_drvdata(&op->dev, NULL); | ||
843 | |||
844 | return 0; | 842 | return 0; |
845 | } | 843 | } |
846 | 844 | ||
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c index 97db3ba8f237..5aab9b9dc210 100644 --- a/drivers/video/cirrusfb.c +++ b/drivers/video/cirrusfb.c | |||
@@ -595,11 +595,6 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var, | |||
595 | return -EINVAL; | 595 | return -EINVAL; |
596 | } | 596 | } |
597 | 597 | ||
598 | if (var->xoffset < 0) | ||
599 | var->xoffset = 0; | ||
600 | if (var->yoffset < 0) | ||
601 | var->yoffset = 0; | ||
602 | |||
603 | /* truncate xoffset and yoffset to maximum if too high */ | 598 | /* truncate xoffset and yoffset to maximum if too high */ |
604 | if (var->xoffset > var->xres_virtual - var->xres) | 599 | if (var->xoffset > var->xres_virtual - var->xres) |
605 | var->xoffset = var->xres_virtual - var->xres - 1; | 600 | var->xoffset = var->xres_virtual - var->xres - 1; |
@@ -2159,7 +2154,6 @@ static int cirrusfb_pci_register(struct pci_dev *pdev, | |||
2159 | if (!ret) | 2154 | if (!ret) |
2160 | return 0; | 2155 | return 0; |
2161 | 2156 | ||
2162 | pci_set_drvdata(pdev, NULL); | ||
2163 | iounmap(info->screen_base); | 2157 | iounmap(info->screen_base); |
2164 | err_release_legacy: | 2158 | err_release_legacy: |
2165 | if (release_io_ports) | 2159 | if (release_io_ports) |
diff --git a/drivers/video/cobalt_lcdfb.c b/drivers/video/cobalt_lcdfb.c index a9031498e10c..d5533f4db1cf 100644 --- a/drivers/video/cobalt_lcdfb.c +++ b/drivers/video/cobalt_lcdfb.c | |||
@@ -368,8 +368,7 @@ static int cobalt_lcdfb_probe(struct platform_device *dev) | |||
368 | 368 | ||
369 | lcd_clear(info); | 369 | lcd_clear(info); |
370 | 370 | ||
371 | printk(KERN_INFO "fb%d: Cobalt server LCD frame buffer device\n", | 371 | fb_info(info, "Cobalt server LCD frame buffer device\n"); |
372 | info->node); | ||
373 | 372 | ||
374 | return 0; | 373 | return 0; |
375 | } | 374 | } |
@@ -395,19 +394,7 @@ static struct platform_driver cobalt_lcdfb_driver = { | |||
395 | .owner = THIS_MODULE, | 394 | .owner = THIS_MODULE, |
396 | }, | 395 | }, |
397 | }; | 396 | }; |
398 | 397 | module_platform_driver(cobalt_lcdfb_driver); | |
399 | static int __init cobalt_lcdfb_init(void) | ||
400 | { | ||
401 | return platform_driver_register(&cobalt_lcdfb_driver); | ||
402 | } | ||
403 | |||
404 | static void __exit cobalt_lcdfb_exit(void) | ||
405 | { | ||
406 | platform_driver_unregister(&cobalt_lcdfb_driver); | ||
407 | } | ||
408 | |||
409 | module_init(cobalt_lcdfb_init); | ||
410 | module_exit(cobalt_lcdfb_exit); | ||
411 | 398 | ||
412 | MODULE_LICENSE("GPL v2"); | 399 | MODULE_LICENSE("GPL v2"); |
413 | MODULE_AUTHOR("Yoichi Yuasa"); | 400 | MODULE_AUTHOR("Yoichi Yuasa"); |
diff --git a/drivers/video/controlfb.c b/drivers/video/controlfb.c index 67b77b40aa7f..fdadef979238 100644 --- a/drivers/video/controlfb.c +++ b/drivers/video/controlfb.c | |||
@@ -471,8 +471,8 @@ try_again: | |||
471 | /* Register with fbdev layer */ | 471 | /* Register with fbdev layer */ |
472 | if (register_framebuffer(&p->info) < 0) | 472 | if (register_framebuffer(&p->info) < 0) |
473 | return -ENXIO; | 473 | return -ENXIO; |
474 | 474 | ||
475 | printk(KERN_INFO "fb%d: control display adapter\n", p->info.node); | 475 | fb_info(&p->info, "control display adapter\n"); |
476 | 476 | ||
477 | return 0; | 477 | return 0; |
478 | } | 478 | } |
diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c index 1c446bc48b42..b0a950f36970 100644 --- a/drivers/video/cyber2000fb.c +++ b/drivers/video/cyber2000fb.c | |||
@@ -1810,11 +1810,6 @@ static void cyberpro_pci_remove(struct pci_dev *dev) | |||
1810 | iounmap(cfb->region); | 1810 | iounmap(cfb->region); |
1811 | cyberpro_free_fb_info(cfb); | 1811 | cyberpro_free_fb_info(cfb); |
1812 | 1812 | ||
1813 | /* | ||
1814 | * Ensure that the driver data is no longer | ||
1815 | * valid. | ||
1816 | */ | ||
1817 | pci_set_drvdata(dev, NULL); | ||
1818 | if (cfb == int_cfb_info) | 1813 | if (cfb == int_cfb_info) |
1819 | int_cfb_info = NULL; | 1814 | int_cfb_info = NULL; |
1820 | 1815 | ||
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index e030e17a83f2..a1d74dd11988 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c | |||
@@ -129,7 +129,6 @@ | |||
129 | 129 | ||
130 | #define LCD_NUM_BUFFERS 2 | 130 | #define LCD_NUM_BUFFERS 2 |
131 | 131 | ||
132 | #define WSI_TIMEOUT 50 | ||
133 | #define PALETTE_SIZE 256 | 132 | #define PALETTE_SIZE 256 |
134 | 133 | ||
135 | #define CLK_MIN_DIV 2 | 134 | #define CLK_MIN_DIV 2 |
@@ -1314,7 +1313,7 @@ static struct fb_ops da8xx_fb_ops = { | |||
1314 | 1313 | ||
1315 | static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev) | 1314 | static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev) |
1316 | { | 1315 | { |
1317 | struct da8xx_lcdc_platform_data *fb_pdata = dev->dev.platform_data; | 1316 | struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev); |
1318 | struct fb_videomode *lcdc_info; | 1317 | struct fb_videomode *lcdc_info; |
1319 | int i; | 1318 | int i; |
1320 | 1319 | ||
@@ -1336,7 +1335,7 @@ static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev) | |||
1336 | static int fb_probe(struct platform_device *device) | 1335 | static int fb_probe(struct platform_device *device) |
1337 | { | 1336 | { |
1338 | struct da8xx_lcdc_platform_data *fb_pdata = | 1337 | struct da8xx_lcdc_platform_data *fb_pdata = |
1339 | device->dev.platform_data; | 1338 | dev_get_platdata(&device->dev); |
1340 | static struct resource *lcdc_regs; | 1339 | static struct resource *lcdc_regs; |
1341 | struct lcd_ctrl_config *lcd_cfg; | 1340 | struct lcd_ctrl_config *lcd_cfg; |
1342 | struct fb_videomode *lcdc_info; | 1341 | struct fb_videomode *lcdc_info; |
@@ -1548,7 +1547,7 @@ err_pm_runtime_disable: | |||
1548 | } | 1547 | } |
1549 | 1548 | ||
1550 | #ifdef CONFIG_PM | 1549 | #ifdef CONFIG_PM |
1551 | struct lcdc_context { | 1550 | static struct lcdc_context { |
1552 | u32 clk_enable; | 1551 | u32 clk_enable; |
1553 | u32 ctrl; | 1552 | u32 ctrl; |
1554 | u32 dma_ctrl; | 1553 | u32 dma_ctrl; |
@@ -1663,19 +1662,7 @@ static struct platform_driver da8xx_fb_driver = { | |||
1663 | .owner = THIS_MODULE, | 1662 | .owner = THIS_MODULE, |
1664 | }, | 1663 | }, |
1665 | }; | 1664 | }; |
1666 | 1665 | module_platform_driver(da8xx_fb_driver); | |
1667 | static int __init da8xx_fb_init(void) | ||
1668 | { | ||
1669 | return platform_driver_register(&da8xx_fb_driver); | ||
1670 | } | ||
1671 | |||
1672 | static void __exit da8xx_fb_cleanup(void) | ||
1673 | { | ||
1674 | platform_driver_unregister(&da8xx_fb_driver); | ||
1675 | } | ||
1676 | |||
1677 | module_init(da8xx_fb_init); | ||
1678 | module_exit(da8xx_fb_cleanup); | ||
1679 | 1666 | ||
1680 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); | 1667 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); |
1681 | MODULE_AUTHOR("Texas Instruments"); | 1668 | MODULE_AUTHOR("Texas Instruments"); |
diff --git a/drivers/video/efifb.c b/drivers/video/efifb.c index 7f9ff75d0db2..cd7c0df9f24b 100644 --- a/drivers/video/efifb.c +++ b/drivers/video/efifb.c | |||
@@ -108,8 +108,8 @@ static int efifb_setup(char *options) | |||
108 | if (!*this_opt) continue; | 108 | if (!*this_opt) continue; |
109 | 109 | ||
110 | for (i = 0; i < M_UNKNOWN; i++) { | 110 | for (i = 0; i < M_UNKNOWN; i++) { |
111 | if (!strcmp(this_opt, efifb_dmi_list[i].optname) && | 111 | if (efifb_dmi_list[i].base != 0 && |
112 | efifb_dmi_list[i].base != 0) { | 112 | !strcmp(this_opt, efifb_dmi_list[i].optname)) { |
113 | screen_info.lfb_base = efifb_dmi_list[i].base; | 113 | screen_info.lfb_base = efifb_dmi_list[i].base; |
114 | screen_info.lfb_linelength = efifb_dmi_list[i].stride; | 114 | screen_info.lfb_linelength = efifb_dmi_list[i].stride; |
115 | screen_info.lfb_width = efifb_dmi_list[i].width; | 115 | screen_info.lfb_width = efifb_dmi_list[i].width; |
@@ -322,8 +322,7 @@ static int efifb_probe(struct platform_device *dev) | |||
322 | printk(KERN_ERR "efifb: cannot register framebuffer\n"); | 322 | printk(KERN_ERR "efifb: cannot register framebuffer\n"); |
323 | goto err_fb_dealoc; | 323 | goto err_fb_dealoc; |
324 | } | 324 | } |
325 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 325 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
326 | info->node, info->fix.id); | ||
327 | return 0; | 326 | return 0; |
328 | 327 | ||
329 | err_fb_dealoc: | 328 | err_fb_dealoc: |
diff --git a/drivers/video/ep93xx-fb.c b/drivers/video/ep93xx-fb.c index 28a837dfddd1..35a0f533f1a2 100644 --- a/drivers/video/ep93xx-fb.c +++ b/drivers/video/ep93xx-fb.c | |||
@@ -487,7 +487,7 @@ static void ep93xxfb_dealloc_videomem(struct fb_info *info) | |||
487 | 487 | ||
488 | static int ep93xxfb_probe(struct platform_device *pdev) | 488 | static int ep93xxfb_probe(struct platform_device *pdev) |
489 | { | 489 | { |
490 | struct ep93xxfb_mach_info *mach_info = pdev->dev.platform_data; | 490 | struct ep93xxfb_mach_info *mach_info = dev_get_platdata(&pdev->dev); |
491 | struct fb_info *info; | 491 | struct fb_info *info; |
492 | struct ep93xx_fbi *fbi; | 492 | struct ep93xx_fbi *fbi; |
493 | struct resource *res; | 493 | struct resource *res; |
diff --git a/drivers/video/exynos/exynos_mipi_dsi_common.c b/drivers/video/exynos/exynos_mipi_dsi_common.c index 520fc9bd887b..7eed957b6014 100644 --- a/drivers/video/exynos/exynos_mipi_dsi_common.c +++ b/drivers/video/exynos/exynos_mipi_dsi_common.c | |||
@@ -376,6 +376,7 @@ int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id, | |||
376 | "data id %x is not supported current DSI spec.\n", | 376 | "data id %x is not supported current DSI spec.\n", |
377 | data_id); | 377 | data_id); |
378 | 378 | ||
379 | mutex_unlock(&dsim->lock); | ||
379 | return -EINVAL; | 380 | return -EINVAL; |
380 | } | 381 | } |
381 | 382 | ||
@@ -667,7 +668,7 @@ int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim) | |||
667 | default: | 668 | default: |
668 | dev_info(dsim->dev, "data lane is invalid.\n"); | 669 | dev_info(dsim->dev, "data lane is invalid.\n"); |
669 | return -EINVAL; | 670 | return -EINVAL; |
670 | }; | 671 | } |
671 | 672 | ||
672 | exynos_mipi_dsi_sw_reset(dsim); | 673 | exynos_mipi_dsi_sw_reset(dsim); |
673 | exynos_mipi_dsi_func_reset(dsim); | 674 | exynos_mipi_dsi_func_reset(dsim); |
diff --git a/drivers/video/fb-puv3.c b/drivers/video/fb-puv3.c index 27fc956166fa..6db9ebd042a3 100644 --- a/drivers/video/fb-puv3.c +++ b/drivers/video/fb-puv3.c | |||
@@ -713,9 +713,8 @@ static int unifb_probe(struct platform_device *dev) | |||
713 | platform_set_drvdata(dev, info); | 713 | platform_set_drvdata(dev, info); |
714 | platform_device_add_data(dev, unifb_regs, sizeof(u32) * UNIFB_REGS_NUM); | 714 | platform_device_add_data(dev, unifb_regs, sizeof(u32) * UNIFB_REGS_NUM); |
715 | 715 | ||
716 | printk(KERN_INFO | 716 | fb_info(info, "Virtual frame buffer device, using %dM of video memory\n", |
717 | "fb%d: Virtual frame buffer device, using %dM of video memory\n", | 717 | UNIFB_MEMSIZE >> 20); |
718 | info->node, UNIFB_MEMSIZE >> 20); | ||
719 | return 0; | 718 | return 0; |
720 | err2: | 719 | err2: |
721 | fb_dealloc_cmap(&info->cmap); | 720 | fb_dealloc_cmap(&info->cmap); |
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index dacaf74256a3..010d19105ebc 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c | |||
@@ -1108,14 +1108,16 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, | |||
1108 | case FBIOPUT_VSCREENINFO: | 1108 | case FBIOPUT_VSCREENINFO: |
1109 | if (copy_from_user(&var, argp, sizeof(var))) | 1109 | if (copy_from_user(&var, argp, sizeof(var))) |
1110 | return -EFAULT; | 1110 | return -EFAULT; |
1111 | if (!lock_fb_info(info)) | ||
1112 | return -ENODEV; | ||
1113 | console_lock(); | 1111 | console_lock(); |
1112 | if (!lock_fb_info(info)) { | ||
1113 | console_unlock(); | ||
1114 | return -ENODEV; | ||
1115 | } | ||
1114 | info->flags |= FBINFO_MISC_USEREVENT; | 1116 | info->flags |= FBINFO_MISC_USEREVENT; |
1115 | ret = fb_set_var(info, &var); | 1117 | ret = fb_set_var(info, &var); |
1116 | info->flags &= ~FBINFO_MISC_USEREVENT; | 1118 | info->flags &= ~FBINFO_MISC_USEREVENT; |
1117 | console_unlock(); | ||
1118 | unlock_fb_info(info); | 1119 | unlock_fb_info(info); |
1120 | console_unlock(); | ||
1119 | if (!ret && copy_to_user(argp, &var, sizeof(var))) | 1121 | if (!ret && copy_to_user(argp, &var, sizeof(var))) |
1120 | ret = -EFAULT; | 1122 | ret = -EFAULT; |
1121 | break; | 1123 | break; |
@@ -1144,12 +1146,14 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, | |||
1144 | case FBIOPAN_DISPLAY: | 1146 | case FBIOPAN_DISPLAY: |
1145 | if (copy_from_user(&var, argp, sizeof(var))) | 1147 | if (copy_from_user(&var, argp, sizeof(var))) |
1146 | return -EFAULT; | 1148 | return -EFAULT; |
1147 | if (!lock_fb_info(info)) | ||
1148 | return -ENODEV; | ||
1149 | console_lock(); | 1149 | console_lock(); |
1150 | if (!lock_fb_info(info)) { | ||
1151 | console_unlock(); | ||
1152 | return -ENODEV; | ||
1153 | } | ||
1150 | ret = fb_pan_display(info, &var); | 1154 | ret = fb_pan_display(info, &var); |
1151 | console_unlock(); | ||
1152 | unlock_fb_info(info); | 1155 | unlock_fb_info(info); |
1156 | console_unlock(); | ||
1153 | if (ret == 0 && copy_to_user(argp, &var, sizeof(var))) | 1157 | if (ret == 0 && copy_to_user(argp, &var, sizeof(var))) |
1154 | return -EFAULT; | 1158 | return -EFAULT; |
1155 | break; | 1159 | break; |
@@ -1184,23 +1188,27 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, | |||
1184 | break; | 1188 | break; |
1185 | } | 1189 | } |
1186 | event.data = &con2fb; | 1190 | event.data = &con2fb; |
1187 | if (!lock_fb_info(info)) | ||
1188 | return -ENODEV; | ||
1189 | console_lock(); | 1191 | console_lock(); |
1192 | if (!lock_fb_info(info)) { | ||
1193 | console_unlock(); | ||
1194 | return -ENODEV; | ||
1195 | } | ||
1190 | event.info = info; | 1196 | event.info = info; |
1191 | ret = fb_notifier_call_chain(FB_EVENT_SET_CONSOLE_MAP, &event); | 1197 | ret = fb_notifier_call_chain(FB_EVENT_SET_CONSOLE_MAP, &event); |
1192 | console_unlock(); | ||
1193 | unlock_fb_info(info); | 1198 | unlock_fb_info(info); |
1199 | console_unlock(); | ||
1194 | break; | 1200 | break; |
1195 | case FBIOBLANK: | 1201 | case FBIOBLANK: |
1196 | if (!lock_fb_info(info)) | ||
1197 | return -ENODEV; | ||
1198 | console_lock(); | 1202 | console_lock(); |
1203 | if (!lock_fb_info(info)) { | ||
1204 | console_unlock(); | ||
1205 | return -ENODEV; | ||
1206 | } | ||
1199 | info->flags |= FBINFO_MISC_USEREVENT; | 1207 | info->flags |= FBINFO_MISC_USEREVENT; |
1200 | ret = fb_blank(info, arg); | 1208 | ret = fb_blank(info, arg); |
1201 | info->flags &= ~FBINFO_MISC_USEREVENT; | 1209 | info->flags &= ~FBINFO_MISC_USEREVENT; |
1202 | console_unlock(); | ||
1203 | unlock_fb_info(info); | 1210 | unlock_fb_info(info); |
1211 | console_unlock(); | ||
1204 | break; | 1212 | break; |
1205 | default: | 1213 | default: |
1206 | if (!lock_fb_info(info)) | 1214 | if (!lock_fb_info(info)) |
@@ -1660,12 +1668,15 @@ static int do_register_framebuffer(struct fb_info *fb_info) | |||
1660 | registered_fb[i] = fb_info; | 1668 | registered_fb[i] = fb_info; |
1661 | 1669 | ||
1662 | event.info = fb_info; | 1670 | event.info = fb_info; |
1663 | if (!lock_fb_info(fb_info)) | ||
1664 | return -ENODEV; | ||
1665 | console_lock(); | 1671 | console_lock(); |
1672 | if (!lock_fb_info(fb_info)) { | ||
1673 | console_unlock(); | ||
1674 | return -ENODEV; | ||
1675 | } | ||
1676 | |||
1666 | fb_notifier_call_chain(FB_EVENT_FB_REGISTERED, &event); | 1677 | fb_notifier_call_chain(FB_EVENT_FB_REGISTERED, &event); |
1667 | console_unlock(); | ||
1668 | unlock_fb_info(fb_info); | 1678 | unlock_fb_info(fb_info); |
1679 | console_unlock(); | ||
1669 | return 0; | 1680 | return 0; |
1670 | } | 1681 | } |
1671 | 1682 | ||
@@ -1678,13 +1689,16 @@ static int do_unregister_framebuffer(struct fb_info *fb_info) | |||
1678 | if (i < 0 || i >= FB_MAX || registered_fb[i] != fb_info) | 1689 | if (i < 0 || i >= FB_MAX || registered_fb[i] != fb_info) |
1679 | return -EINVAL; | 1690 | return -EINVAL; |
1680 | 1691 | ||
1681 | if (!lock_fb_info(fb_info)) | ||
1682 | return -ENODEV; | ||
1683 | console_lock(); | 1692 | console_lock(); |
1693 | if (!lock_fb_info(fb_info)) { | ||
1694 | console_unlock(); | ||
1695 | return -ENODEV; | ||
1696 | } | ||
1697 | |||
1684 | event.info = fb_info; | 1698 | event.info = fb_info; |
1685 | ret = fb_notifier_call_chain(FB_EVENT_FB_UNBIND, &event); | 1699 | ret = fb_notifier_call_chain(FB_EVENT_FB_UNBIND, &event); |
1686 | console_unlock(); | ||
1687 | unlock_fb_info(fb_info); | 1700 | unlock_fb_info(fb_info); |
1701 | console_unlock(); | ||
1688 | 1702 | ||
1689 | if (ret) | 1703 | if (ret) |
1690 | return -EINVAL; | 1704 | return -EINVAL; |
diff --git a/drivers/video/fbsysfs.c b/drivers/video/fbsysfs.c index ef476b02fbe5..53444ac19fe0 100644 --- a/drivers/video/fbsysfs.c +++ b/drivers/video/fbsysfs.c | |||
@@ -177,9 +177,12 @@ static ssize_t store_modes(struct device *device, | |||
177 | if (i * sizeof(struct fb_videomode) != count) | 177 | if (i * sizeof(struct fb_videomode) != count) |
178 | return -EINVAL; | 178 | return -EINVAL; |
179 | 179 | ||
180 | if (!lock_fb_info(fb_info)) | ||
181 | return -ENODEV; | ||
182 | console_lock(); | 180 | console_lock(); |
181 | if (!lock_fb_info(fb_info)) { | ||
182 | console_unlock(); | ||
183 | return -ENODEV; | ||
184 | } | ||
185 | |||
183 | list_splice(&fb_info->modelist, &old_list); | 186 | list_splice(&fb_info->modelist, &old_list); |
184 | fb_videomode_to_modelist((const struct fb_videomode *)buf, i, | 187 | fb_videomode_to_modelist((const struct fb_videomode *)buf, i, |
185 | &fb_info->modelist); | 188 | &fb_info->modelist); |
@@ -189,8 +192,8 @@ static ssize_t store_modes(struct device *device, | |||
189 | } else | 192 | } else |
190 | fb_destroy_modelist(&old_list); | 193 | fb_destroy_modelist(&old_list); |
191 | 194 | ||
192 | console_unlock(); | ||
193 | unlock_fb_info(fb_info); | 195 | unlock_fb_info(fb_info); |
196 | console_unlock(); | ||
194 | 197 | ||
195 | return 0; | 198 | return 0; |
196 | } | 199 | } |
@@ -404,12 +407,16 @@ static ssize_t store_fbstate(struct device *device, | |||
404 | 407 | ||
405 | state = simple_strtoul(buf, &last, 0); | 408 | state = simple_strtoul(buf, &last, 0); |
406 | 409 | ||
407 | if (!lock_fb_info(fb_info)) | ||
408 | return -ENODEV; | ||
409 | console_lock(); | 410 | console_lock(); |
411 | if (!lock_fb_info(fb_info)) { | ||
412 | console_unlock(); | ||
413 | return -ENODEV; | ||
414 | } | ||
415 | |||
410 | fb_set_suspend(fb_info, (int)state); | 416 | fb_set_suspend(fb_info, (int)state); |
411 | console_unlock(); | 417 | |
412 | unlock_fb_info(fb_info); | 418 | unlock_fb_info(fb_info); |
419 | console_unlock(); | ||
413 | 420 | ||
414 | return count; | 421 | return count; |
415 | } | 422 | } |
diff --git a/drivers/video/ffb.c b/drivers/video/ffb.c index 6d2744794dd1..4c4ffa61ae26 100644 --- a/drivers/video/ffb.c +++ b/drivers/video/ffb.c | |||
@@ -1035,8 +1035,6 @@ static int ffb_remove(struct platform_device *op) | |||
1035 | 1035 | ||
1036 | framebuffer_release(info); | 1036 | framebuffer_release(info); |
1037 | 1037 | ||
1038 | dev_set_drvdata(&op->dev, NULL); | ||
1039 | |||
1040 | return 0; | 1038 | return 0; |
1041 | } | 1039 | } |
1042 | 1040 | ||
diff --git a/drivers/video/fm2fb.c b/drivers/video/fm2fb.c index c99c9671302b..e69d47af9932 100644 --- a/drivers/video/fm2fb.c +++ b/drivers/video/fm2fb.c | |||
@@ -289,7 +289,7 @@ static int fm2fb_probe(struct zorro_dev *z, const struct zorro_device_id *id) | |||
289 | zorro_release_device(z); | 289 | zorro_release_device(z); |
290 | return -EINVAL; | 290 | return -EINVAL; |
291 | } | 291 | } |
292 | printk("fb%d: %s frame buffer device\n", info->node, fb_fix.id); | 292 | fb_info(info, "%s frame buffer device\n", fb_fix.id); |
293 | return 0; | 293 | return 0; |
294 | } | 294 | } |
295 | 295 | ||
diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c index b047ec58ac30..e8758b9c3bcc 100644 --- a/drivers/video/fsl-diu-fb.c +++ b/drivers/video/fsl-diu-fb.c | |||
@@ -1104,7 +1104,7 @@ static int fsl_diu_cursor(struct fb_info *info, struct fb_cursor *cursor) | |||
1104 | 1104 | ||
1105 | fsl_diu_load_cursor_image(info, image, bg, fg, | 1105 | fsl_diu_load_cursor_image(info, image, bg, fg, |
1106 | cursor->image.width, cursor->image.height); | 1106 | cursor->image.width, cursor->image.height); |
1107 | }; | 1107 | } |
1108 | 1108 | ||
1109 | /* | 1109 | /* |
1110 | * Show or hide the cursor. The cursor data is always stored in the | 1110 | * Show or hide the cursor. The cursor data is always stored in the |
diff --git a/drivers/video/gbefb.c b/drivers/video/gbefb.c index ceab37020fff..4c7cb368a9dc 100644 --- a/drivers/video/gbefb.c +++ b/drivers/video/gbefb.c | |||
@@ -1236,9 +1236,9 @@ static int gbefb_probe(struct platform_device *p_dev) | |||
1236 | platform_set_drvdata(p_dev, info); | 1236 | platform_set_drvdata(p_dev, info); |
1237 | gbefb_create_sysfs(&p_dev->dev); | 1237 | gbefb_create_sysfs(&p_dev->dev); |
1238 | 1238 | ||
1239 | printk(KERN_INFO "fb%d: %s rev %d @ 0x%08x using %dkB memory\n", | 1239 | fb_info(info, "%s rev %d @ 0x%08x using %dkB memory\n", |
1240 | info->node, info->fix.id, gbe_revision, (unsigned) GBE_BASE, | 1240 | info->fix.id, gbe_revision, (unsigned)GBE_BASE, |
1241 | gbe_mem_size >> 10); | 1241 | gbe_mem_size >> 10); |
1242 | 1242 | ||
1243 | return 0; | 1243 | return 0; |
1244 | 1244 | ||
diff --git a/drivers/video/geode/gx1fb_core.c b/drivers/video/geode/gx1fb_core.c index ebbaada7b941..2794ba11f332 100644 --- a/drivers/video/geode/gx1fb_core.c +++ b/drivers/video/geode/gx1fb_core.c | |||
@@ -357,7 +357,7 @@ static int gx1fb_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
357 | goto err; | 357 | goto err; |
358 | } | 358 | } |
359 | pci_set_drvdata(pdev, info); | 359 | pci_set_drvdata(pdev, info); |
360 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); | 360 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
361 | return 0; | 361 | return 0; |
362 | 362 | ||
363 | err: | 363 | err: |
@@ -399,7 +399,6 @@ static void gx1fb_remove(struct pci_dev *pdev) | |||
399 | release_mem_region(gx1_gx_base() + 0x8300, 0x100); | 399 | release_mem_region(gx1_gx_base() + 0x8300, 0x100); |
400 | 400 | ||
401 | fb_dealloc_cmap(&info->cmap); | 401 | fb_dealloc_cmap(&info->cmap); |
402 | pci_set_drvdata(pdev, NULL); | ||
403 | 402 | ||
404 | framebuffer_release(info); | 403 | framebuffer_release(info); |
405 | } | 404 | } |
diff --git a/drivers/video/geode/gxfb_core.c b/drivers/video/geode/gxfb_core.c index 19f0c1add747..1790f14bab15 100644 --- a/drivers/video/geode/gxfb_core.c +++ b/drivers/video/geode/gxfb_core.c | |||
@@ -423,7 +423,7 @@ static int gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
423 | goto err; | 423 | goto err; |
424 | } | 424 | } |
425 | pci_set_drvdata(pdev, info); | 425 | pci_set_drvdata(pdev, info); |
426 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); | 426 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
427 | return 0; | 427 | return 0; |
428 | 428 | ||
429 | err: | 429 | err: |
@@ -471,7 +471,6 @@ static void gxfb_remove(struct pci_dev *pdev) | |||
471 | pci_release_region(pdev, 1); | 471 | pci_release_region(pdev, 1); |
472 | 472 | ||
473 | fb_dealloc_cmap(&info->cmap); | 473 | fb_dealloc_cmap(&info->cmap); |
474 | pci_set_drvdata(pdev, NULL); | ||
475 | 474 | ||
476 | framebuffer_release(info); | 475 | framebuffer_release(info); |
477 | } | 476 | } |
diff --git a/drivers/video/geode/lxfb_core.c b/drivers/video/geode/lxfb_core.c index 4dd7b5566962..9e1d19d673a1 100644 --- a/drivers/video/geode/lxfb_core.c +++ b/drivers/video/geode/lxfb_core.c | |||
@@ -555,8 +555,7 @@ static int lxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
555 | goto err; | 555 | goto err; |
556 | } | 556 | } |
557 | pci_set_drvdata(pdev, info); | 557 | pci_set_drvdata(pdev, info); |
558 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 558 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
559 | info->node, info->fix.id); | ||
560 | 559 | ||
561 | return 0; | 560 | return 0; |
562 | 561 | ||
@@ -606,7 +605,6 @@ static void lxfb_remove(struct pci_dev *pdev) | |||
606 | pci_release_region(pdev, 3); | 605 | pci_release_region(pdev, 3); |
607 | 606 | ||
608 | fb_dealloc_cmap(&info->cmap); | 607 | fb_dealloc_cmap(&info->cmap); |
609 | pci_set_drvdata(pdev, NULL); | ||
610 | framebuffer_release(info); | 608 | framebuffer_release(info); |
611 | } | 609 | } |
612 | 610 | ||
diff --git a/drivers/video/grvga.c b/drivers/video/grvga.c index 861109e7de1b..c078701f15f6 100644 --- a/drivers/video/grvga.c +++ b/drivers/video/grvga.c | |||
@@ -496,7 +496,6 @@ static int grvga_probe(struct platform_device *dev) | |||
496 | return 0; | 496 | return 0; |
497 | 497 | ||
498 | free_mem: | 498 | free_mem: |
499 | dev_set_drvdata(&dev->dev, NULL); | ||
500 | if (grvga_fix_addr) | 499 | if (grvga_fix_addr) |
501 | iounmap((void *)virtual_start); | 500 | iounmap((void *)virtual_start); |
502 | else | 501 | else |
@@ -530,7 +529,6 @@ static int grvga_remove(struct platform_device *device) | |||
530 | kfree((void *)info->screen_base); | 529 | kfree((void *)info->screen_base); |
531 | 530 | ||
532 | framebuffer_release(info); | 531 | framebuffer_release(info); |
533 | dev_set_drvdata(&device->dev, NULL); | ||
534 | } | 532 | } |
535 | 533 | ||
536 | return 0; | 534 | return 0; |
@@ -557,19 +555,7 @@ static struct platform_driver grvga_driver = { | |||
557 | .remove = grvga_remove, | 555 | .remove = grvga_remove, |
558 | }; | 556 | }; |
559 | 557 | ||
560 | 558 | module_platform_driver(grvga_driver); | |
561 | static int __init grvga_init(void) | ||
562 | { | ||
563 | return platform_driver_register(&grvga_driver); | ||
564 | } | ||
565 | |||
566 | static void __exit grvga_exit(void) | ||
567 | { | ||
568 | platform_driver_unregister(&grvga_driver); | ||
569 | } | ||
570 | |||
571 | module_init(grvga_init); | ||
572 | module_exit(grvga_exit); | ||
573 | 559 | ||
574 | MODULE_LICENSE("GPL"); | 560 | MODULE_LICENSE("GPL"); |
575 | MODULE_AUTHOR("Aeroflex Gaisler"); | 561 | MODULE_AUTHOR("Aeroflex Gaisler"); |
diff --git a/drivers/video/gxt4500.c b/drivers/video/gxt4500.c index c35663f6a54a..135d78a02588 100644 --- a/drivers/video/gxt4500.c +++ b/drivers/video/gxt4500.c | |||
@@ -698,8 +698,7 @@ static int gxt4500_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
698 | dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n"); | 698 | dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n"); |
699 | goto err_free_cmap; | 699 | goto err_free_cmap; |
700 | } | 700 | } |
701 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 701 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
702 | info->node, info->fix.id); | ||
703 | 702 | ||
704 | return 0; | 703 | return 0; |
705 | 704 | ||
diff --git a/drivers/video/hecubafb.c b/drivers/video/hecubafb.c index 59d23181fdb0..f64120ec9192 100644 --- a/drivers/video/hecubafb.c +++ b/drivers/video/hecubafb.c | |||
@@ -261,9 +261,8 @@ static int hecubafb_probe(struct platform_device *dev) | |||
261 | goto err_fbreg; | 261 | goto err_fbreg; |
262 | platform_set_drvdata(dev, info); | 262 | platform_set_drvdata(dev, info); |
263 | 263 | ||
264 | printk(KERN_INFO | 264 | fb_info(info, "Hecuba frame buffer device, using %dK of video memory\n", |
265 | "fb%d: Hecuba frame buffer device, using %dK of video memory\n", | 265 | videomemorysize >> 10); |
266 | info->node, videomemorysize >> 10); | ||
267 | 266 | ||
268 | /* this inits the dpy */ | 267 | /* this inits the dpy */ |
269 | retval = par->board->init(par); | 268 | retval = par->board->init(par); |
@@ -305,19 +304,7 @@ static struct platform_driver hecubafb_driver = { | |||
305 | .name = "hecubafb", | 304 | .name = "hecubafb", |
306 | }, | 305 | }, |
307 | }; | 306 | }; |
308 | 307 | module_platform_driver(hecubafb_driver); | |
309 | static int __init hecubafb_init(void) | ||
310 | { | ||
311 | return platform_driver_register(&hecubafb_driver); | ||
312 | } | ||
313 | |||
314 | static void __exit hecubafb_exit(void) | ||
315 | { | ||
316 | platform_driver_unregister(&hecubafb_driver); | ||
317 | } | ||
318 | |||
319 | module_init(hecubafb_init); | ||
320 | module_exit(hecubafb_exit); | ||
321 | 308 | ||
322 | MODULE_DESCRIPTION("fbdev driver for Hecuba/Apollo controller"); | 309 | MODULE_DESCRIPTION("fbdev driver for Hecuba/Apollo controller"); |
323 | MODULE_AUTHOR("Jaya Kumar"); | 310 | MODULE_AUTHOR("Jaya Kumar"); |
diff --git a/drivers/video/hgafb.c b/drivers/video/hgafb.c index 1e9e2d819d1f..5ff9fe2116a4 100644 --- a/drivers/video/hgafb.c +++ b/drivers/video/hgafb.c | |||
@@ -586,8 +586,7 @@ static int hgafb_probe(struct platform_device *pdev) | |||
586 | return -EINVAL; | 586 | return -EINVAL; |
587 | } | 587 | } |
588 | 588 | ||
589 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 589 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
590 | info->node, info->fix.id); | ||
591 | platform_set_drvdata(pdev, info); | 590 | platform_set_drvdata(pdev, info); |
592 | return 0; | 591 | return 0; |
593 | } | 592 | } |
diff --git a/drivers/video/hitfb.c b/drivers/video/hitfb.c index c2414d6ab646..a648d5186c6e 100644 --- a/drivers/video/hitfb.c +++ b/drivers/video/hitfb.c | |||
@@ -405,8 +405,7 @@ static int hitfb_probe(struct platform_device *dev) | |||
405 | 405 | ||
406 | platform_set_drvdata(dev, info); | 406 | platform_set_drvdata(dev, info); |
407 | 407 | ||
408 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 408 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
409 | info->node, info->fix.id); | ||
410 | 409 | ||
411 | return 0; | 410 | return 0; |
412 | 411 | ||
diff --git a/drivers/video/hpfb.c b/drivers/video/hpfb.c index b802f93cef5d..a1b7e5fa9b09 100644 --- a/drivers/video/hpfb.c +++ b/drivers/video/hpfb.c | |||
@@ -298,8 +298,7 @@ static int hpfb_init_one(unsigned long phys_base, unsigned long virt_base) | |||
298 | if (ret < 0) | 298 | if (ret < 0) |
299 | goto dealloc_cmap; | 299 | goto dealloc_cmap; |
300 | 300 | ||
301 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 301 | fb_info(&fb_info, "%s frame buffer device\n", fb_info.fix.id); |
302 | fb_info.node, fb_info.fix.id); | ||
303 | 302 | ||
304 | return 0; | 303 | return 0; |
305 | 304 | ||
diff --git a/drivers/video/hyperv_fb.c b/drivers/video/hyperv_fb.c index 8ac99b87c07e..130708f96430 100644 --- a/drivers/video/hyperv_fb.c +++ b/drivers/video/hyperv_fb.c | |||
@@ -575,6 +575,10 @@ static int hvfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |||
575 | return 0; | 575 | return 0; |
576 | } | 576 | } |
577 | 577 | ||
578 | static int hvfb_blank(int blank, struct fb_info *info) | ||
579 | { | ||
580 | return 1; /* get fb_blank to set the colormap to all black */ | ||
581 | } | ||
578 | 582 | ||
579 | static struct fb_ops hvfb_ops = { | 583 | static struct fb_ops hvfb_ops = { |
580 | .owner = THIS_MODULE, | 584 | .owner = THIS_MODULE, |
@@ -584,6 +588,7 @@ static struct fb_ops hvfb_ops = { | |||
584 | .fb_fillrect = cfb_fillrect, | 588 | .fb_fillrect = cfb_fillrect, |
585 | .fb_copyarea = cfb_copyarea, | 589 | .fb_copyarea = cfb_copyarea, |
586 | .fb_imageblit = cfb_imageblit, | 590 | .fb_imageblit = cfb_imageblit, |
591 | .fb_blank = hvfb_blank, | ||
587 | }; | 592 | }; |
588 | 593 | ||
589 | 594 | ||
@@ -795,12 +800,21 @@ static int hvfb_remove(struct hv_device *hdev) | |||
795 | } | 800 | } |
796 | 801 | ||
797 | 802 | ||
803 | static DEFINE_PCI_DEVICE_TABLE(pci_stub_id_table) = { | ||
804 | { | ||
805 | .vendor = PCI_VENDOR_ID_MICROSOFT, | ||
806 | .device = PCI_DEVICE_ID_HYPERV_VIDEO, | ||
807 | }, | ||
808 | { /* end of list */ } | ||
809 | }; | ||
810 | |||
798 | static const struct hv_vmbus_device_id id_table[] = { | 811 | static const struct hv_vmbus_device_id id_table[] = { |
799 | /* Synthetic Video Device GUID */ | 812 | /* Synthetic Video Device GUID */ |
800 | {HV_SYNTHVID_GUID}, | 813 | {HV_SYNTHVID_GUID}, |
801 | {} | 814 | {} |
802 | }; | 815 | }; |
803 | 816 | ||
817 | MODULE_DEVICE_TABLE(pci, pci_stub_id_table); | ||
804 | MODULE_DEVICE_TABLE(vmbus, id_table); | 818 | MODULE_DEVICE_TABLE(vmbus, id_table); |
805 | 819 | ||
806 | static struct hv_driver hvfb_drv = { | 820 | static struct hv_driver hvfb_drv = { |
@@ -810,14 +824,43 @@ static struct hv_driver hvfb_drv = { | |||
810 | .remove = hvfb_remove, | 824 | .remove = hvfb_remove, |
811 | }; | 825 | }; |
812 | 826 | ||
827 | static int hvfb_pci_stub_probe(struct pci_dev *pdev, | ||
828 | const struct pci_device_id *ent) | ||
829 | { | ||
830 | return 0; | ||
831 | } | ||
832 | |||
833 | static void hvfb_pci_stub_remove(struct pci_dev *pdev) | ||
834 | { | ||
835 | } | ||
836 | |||
837 | static struct pci_driver hvfb_pci_stub_driver = { | ||
838 | .name = KBUILD_MODNAME, | ||
839 | .id_table = pci_stub_id_table, | ||
840 | .probe = hvfb_pci_stub_probe, | ||
841 | .remove = hvfb_pci_stub_remove, | ||
842 | }; | ||
813 | 843 | ||
814 | static int __init hvfb_drv_init(void) | 844 | static int __init hvfb_drv_init(void) |
815 | { | 845 | { |
816 | return vmbus_driver_register(&hvfb_drv); | 846 | int ret; |
847 | |||
848 | ret = vmbus_driver_register(&hvfb_drv); | ||
849 | if (ret != 0) | ||
850 | return ret; | ||
851 | |||
852 | ret = pci_register_driver(&hvfb_pci_stub_driver); | ||
853 | if (ret != 0) { | ||
854 | vmbus_driver_unregister(&hvfb_drv); | ||
855 | return ret; | ||
856 | } | ||
857 | |||
858 | return 0; | ||
817 | } | 859 | } |
818 | 860 | ||
819 | static void __exit hvfb_drv_exit(void) | 861 | static void __exit hvfb_drv_exit(void) |
820 | { | 862 | { |
863 | pci_unregister_driver(&hvfb_pci_stub_driver); | ||
821 | vmbus_driver_unregister(&hvfb_drv); | 864 | vmbus_driver_unregister(&hvfb_drv); |
822 | } | 865 | } |
823 | 866 | ||
diff --git a/drivers/video/i740fb.c b/drivers/video/i740fb.c index 6c4838818950..ca7c9df193b0 100644 --- a/drivers/video/i740fb.c +++ b/drivers/video/i740fb.c | |||
@@ -203,8 +203,7 @@ static int i740fb_release(struct fb_info *info, int user) | |||
203 | 203 | ||
204 | mutex_lock(&(par->open_lock)); | 204 | mutex_lock(&(par->open_lock)); |
205 | if (par->ref_count == 0) { | 205 | if (par->ref_count == 0) { |
206 | printk(KERN_ERR "fb%d: release called with zero refcount\n", | 206 | fb_err(info, "release called with zero refcount\n"); |
207 | info->node); | ||
208 | mutex_unlock(&(par->open_lock)); | 207 | mutex_unlock(&(par->open_lock)); |
209 | return -EINVAL; | 208 | return -EINVAL; |
210 | } | 209 | } |
@@ -1067,7 +1066,7 @@ static int i740fb_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |||
1067 | par->has_sgram = !((tmp & DRAM_RAS_TIMING) || | 1066 | par->has_sgram = !((tmp & DRAM_RAS_TIMING) || |
1068 | (tmp & DRAM_RAS_PRECHARGE)); | 1067 | (tmp & DRAM_RAS_PRECHARGE)); |
1069 | 1068 | ||
1070 | printk(KERN_INFO "fb%d: Intel740 on %s, %ld KB %s\n", info->node, | 1069 | fb_info(info, "Intel740 on %s, %ld KB %s\n", |
1071 | pci_name(dev), info->screen_size >> 10, | 1070 | pci_name(dev), info->screen_size >> 10, |
1072 | par->has_sgram ? "SGRAM" : "SDRAM"); | 1071 | par->has_sgram ? "SGRAM" : "SDRAM"); |
1073 | 1072 | ||
@@ -1143,8 +1142,7 @@ static int i740fb_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |||
1143 | goto err_reg_framebuffer; | 1142 | goto err_reg_framebuffer; |
1144 | } | 1143 | } |
1145 | 1144 | ||
1146 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 1145 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
1147 | info->node, info->fix.id); | ||
1148 | pci_set_drvdata(dev, info); | 1146 | pci_set_drvdata(dev, info); |
1149 | #ifdef CONFIG_MTRR | 1147 | #ifdef CONFIG_MTRR |
1150 | if (mtrr) { | 1148 | if (mtrr) { |
@@ -1194,7 +1192,6 @@ static void i740fb_remove(struct pci_dev *dev) | |||
1194 | pci_iounmap(dev, info->screen_base); | 1192 | pci_iounmap(dev, info->screen_base); |
1195 | pci_release_regions(dev); | 1193 | pci_release_regions(dev); |
1196 | /* pci_disable_device(dev); */ | 1194 | /* pci_disable_device(dev); */ |
1197 | pci_set_drvdata(dev, NULL); | ||
1198 | framebuffer_release(info); | 1195 | framebuffer_release(info); |
1199 | } | 1196 | } |
1200 | } | 1197 | } |
diff --git a/drivers/video/i810/i810_main.c b/drivers/video/i810/i810_main.c index 4ce3438ade6f..038192ac7369 100644 --- a/drivers/video/i810/i810_main.c +++ b/drivers/video/i810/i810_main.c | |||
@@ -2129,7 +2129,6 @@ static void __exit i810fb_remove_pci(struct pci_dev *dev) | |||
2129 | 2129 | ||
2130 | unregister_framebuffer(info); | 2130 | unregister_framebuffer(info); |
2131 | i810fb_release_resource(info, par); | 2131 | i810fb_release_resource(info, par); |
2132 | pci_set_drvdata(dev, NULL); | ||
2133 | printk("cleanup_module: unloaded i810 framebuffer device\n"); | 2132 | printk("cleanup_module: unloaded i810 framebuffer device\n"); |
2134 | } | 2133 | } |
2135 | 2134 | ||
diff --git a/drivers/video/igafb.c b/drivers/video/igafb.c index 79cbfa7d1a9b..486f18897414 100644 --- a/drivers/video/igafb.c +++ b/drivers/video/igafb.c | |||
@@ -360,9 +360,8 @@ static int __init iga_init(struct fb_info *info, struct iga_par *par) | |||
360 | if (register_framebuffer(info) < 0) | 360 | if (register_framebuffer(info) < 0) |
361 | return 0; | 361 | return 0; |
362 | 362 | ||
363 | printk("fb%d: %s frame buffer device at 0x%08lx [%dMB VRAM]\n", | 363 | fb_info(info, "%s frame buffer device at 0x%08lx [%dMB VRAM]\n", |
364 | info->node, info->fix.id, | 364 | info->fix.id, par->frame_buffer_phys, info->fix.smem_len >> 20); |
365 | par->frame_buffer_phys, info->fix.smem_len >> 20); | ||
366 | 365 | ||
367 | iga_blank_border(par); | 366 | iga_blank_border(par); |
368 | return 1; | 367 | return 1; |
diff --git a/drivers/video/imsttfb.c b/drivers/video/imsttfb.c index d5220cc90e93..aae10ce74f14 100644 --- a/drivers/video/imsttfb.c +++ b/drivers/video/imsttfb.c | |||
@@ -1461,8 +1461,8 @@ static void init_imstt(struct fb_info *info) | |||
1461 | } | 1461 | } |
1462 | 1462 | ||
1463 | tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8; | 1463 | tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8; |
1464 | printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n", | 1464 | fb_info(info, "%s frame buffer; %uMB vram; chip version %u\n", |
1465 | info->node, info->fix.id, info->fix.smem_len >> 20, tmp); | 1465 | info->fix.id, info->fix.smem_len >> 20, tmp); |
1466 | } | 1466 | } |
1467 | 1467 | ||
1468 | static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | 1468 | static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c index 38733ac2b698..44ee678481d5 100644 --- a/drivers/video/imxfb.c +++ b/drivers/video/imxfb.c | |||
@@ -755,7 +755,7 @@ static int imxfb_resume(struct platform_device *dev) | |||
755 | 755 | ||
756 | static int imxfb_init_fbinfo(struct platform_device *pdev) | 756 | static int imxfb_init_fbinfo(struct platform_device *pdev) |
757 | { | 757 | { |
758 | struct imx_fb_platform_data *pdata = pdev->dev.platform_data; | 758 | struct imx_fb_platform_data *pdata = dev_get_platdata(&pdev->dev); |
759 | struct fb_info *info = dev_get_drvdata(&pdev->dev); | 759 | struct fb_info *info = dev_get_drvdata(&pdev->dev); |
760 | struct imxfb_info *fbi = info->par; | 760 | struct imxfb_info *fbi = info->par; |
761 | struct device_node *np; | 761 | struct device_node *np; |
@@ -877,7 +877,7 @@ static int imxfb_probe(struct platform_device *pdev) | |||
877 | if (!res) | 877 | if (!res) |
878 | return -ENODEV; | 878 | return -ENODEV; |
879 | 879 | ||
880 | pdata = pdev->dev.platform_data; | 880 | pdata = dev_get_platdata(&pdev->dev); |
881 | 881 | ||
882 | info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); | 882 | info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); |
883 | if (!info) | 883 | if (!info) |
@@ -1066,7 +1066,7 @@ static int imxfb_remove(struct platform_device *pdev) | |||
1066 | #endif | 1066 | #endif |
1067 | unregister_framebuffer(info); | 1067 | unregister_framebuffer(info); |
1068 | 1068 | ||
1069 | pdata = pdev->dev.platform_data; | 1069 | pdata = dev_get_platdata(&pdev->dev); |
1070 | if (pdata && pdata->exit) | 1070 | if (pdata && pdata->exit) |
1071 | pdata->exit(fbi->pdev); | 1071 | pdata->exit(fbi->pdev); |
1072 | 1072 | ||
diff --git a/drivers/video/intelfb/intelfbdrv.c b/drivers/video/intelfb/intelfbdrv.c index 8209e46c5d28..b847d530471a 100644 --- a/drivers/video/intelfb/intelfbdrv.c +++ b/drivers/video/intelfb/intelfbdrv.c | |||
@@ -931,8 +931,6 @@ static void intelfb_pci_unregister(struct pci_dev *pdev) | |||
931 | return; | 931 | return; |
932 | 932 | ||
933 | cleanup(dinfo); | 933 | cleanup(dinfo); |
934 | |||
935 | pci_set_drvdata(pdev, NULL); | ||
936 | } | 934 | } |
937 | 935 | ||
938 | /*************************************************************** | 936 | /*************************************************************** |
diff --git a/drivers/video/jz4740_fb.c b/drivers/video/jz4740_fb.c index 2c49112fdd6c..87790e9644d0 100644 --- a/drivers/video/jz4740_fb.c +++ b/drivers/video/jz4740_fb.c | |||
@@ -99,9 +99,9 @@ | |||
99 | #define JZ_LCD_CTRL_BPP_15_16 0x4 | 99 | #define JZ_LCD_CTRL_BPP_15_16 0x4 |
100 | #define JZ_LCD_CTRL_BPP_18_24 0x5 | 100 | #define JZ_LCD_CTRL_BPP_18_24 0x5 |
101 | 101 | ||
102 | #define JZ_LCD_CMD_SOF_IRQ BIT(15) | 102 | #define JZ_LCD_CMD_SOF_IRQ BIT(31) |
103 | #define JZ_LCD_CMD_EOF_IRQ BIT(16) | 103 | #define JZ_LCD_CMD_EOF_IRQ BIT(30) |
104 | #define JZ_LCD_CMD_ENABLE_PAL BIT(12) | 104 | #define JZ_LCD_CMD_ENABLE_PAL BIT(28) |
105 | 105 | ||
106 | #define JZ_LCD_SYNC_MASK 0x3ff | 106 | #define JZ_LCD_SYNC_MASK 0x3ff |
107 | 107 | ||
@@ -471,7 +471,7 @@ static int jzfb_set_par(struct fb_info *info) | |||
471 | writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); | 471 | writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); |
472 | 472 | ||
473 | if (!jzfb->is_enabled) | 473 | if (!jzfb->is_enabled) |
474 | clk_disable(jzfb->ldclk); | 474 | clk_disable_unprepare(jzfb->ldclk); |
475 | 475 | ||
476 | mutex_unlock(&jzfb->lock); | 476 | mutex_unlock(&jzfb->lock); |
477 | 477 | ||
@@ -485,7 +485,7 @@ static void jzfb_enable(struct jzfb *jzfb) | |||
485 | { | 485 | { |
486 | uint32_t ctrl; | 486 | uint32_t ctrl; |
487 | 487 | ||
488 | clk_enable(jzfb->ldclk); | 488 | clk_prepare_enable(jzfb->ldclk); |
489 | 489 | ||
490 | jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); | 490 | jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
491 | jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); | 491 | jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); |
@@ -514,7 +514,7 @@ static void jzfb_disable(struct jzfb *jzfb) | |||
514 | jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); | 514 | jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); |
515 | jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); | 515 | jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); |
516 | 516 | ||
517 | clk_disable(jzfb->ldclk); | 517 | clk_disable_unprepare(jzfb->ldclk); |
518 | } | 518 | } |
519 | 519 | ||
520 | static int jzfb_blank(int blank_mode, struct fb_info *info) | 520 | static int jzfb_blank(int blank_mode, struct fb_info *info) |
@@ -693,7 +693,7 @@ static int jzfb_probe(struct platform_device *pdev) | |||
693 | 693 | ||
694 | fb_alloc_cmap(&fb->cmap, 256, 0); | 694 | fb_alloc_cmap(&fb->cmap, 256, 0); |
695 | 695 | ||
696 | clk_enable(jzfb->ldclk); | 696 | clk_prepare_enable(jzfb->ldclk); |
697 | jzfb->is_enabled = 1; | 697 | jzfb->is_enabled = 1; |
698 | 698 | ||
699 | writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); | 699 | writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0); |
@@ -763,7 +763,7 @@ static int jzfb_suspend(struct device *dev) | |||
763 | static int jzfb_resume(struct device *dev) | 763 | static int jzfb_resume(struct device *dev) |
764 | { | 764 | { |
765 | struct jzfb *jzfb = dev_get_drvdata(dev); | 765 | struct jzfb *jzfb = dev_get_drvdata(dev); |
766 | clk_enable(jzfb->ldclk); | 766 | clk_prepare_enable(jzfb->ldclk); |
767 | 767 | ||
768 | mutex_lock(&jzfb->lock); | 768 | mutex_lock(&jzfb->lock); |
769 | if (jzfb->is_enabled) | 769 | if (jzfb->is_enabled) |
@@ -798,18 +798,7 @@ static struct platform_driver jzfb_driver = { | |||
798 | .pm = JZFB_PM_OPS, | 798 | .pm = JZFB_PM_OPS, |
799 | }, | 799 | }, |
800 | }; | 800 | }; |
801 | 801 | module_platform_driver(jzfb_driver); | |
802 | static int __init jzfb_init(void) | ||
803 | { | ||
804 | return platform_driver_register(&jzfb_driver); | ||
805 | } | ||
806 | module_init(jzfb_init); | ||
807 | |||
808 | static void __exit jzfb_exit(void) | ||
809 | { | ||
810 | platform_driver_unregister(&jzfb_driver); | ||
811 | } | ||
812 | module_exit(jzfb_exit); | ||
813 | 802 | ||
814 | MODULE_LICENSE("GPL"); | 803 | MODULE_LICENSE("GPL"); |
815 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | 804 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); |
diff --git a/drivers/video/kyro/fbdev.c b/drivers/video/kyro/fbdev.c index 6157f74ac600..50c857477e4f 100644 --- a/drivers/video/kyro/fbdev.c +++ b/drivers/video/kyro/fbdev.c | |||
@@ -623,7 +623,6 @@ static int kyrofb_ioctl(struct fb_info *info, | |||
623 | "command instead.\n"); | 623 | "command instead.\n"); |
624 | return -EINVAL; | 624 | return -EINVAL; |
625 | } | 625 | } |
626 | break; | ||
627 | case KYRO_IOCTL_UVSTRIDE: | 626 | case KYRO_IOCTL_UVSTRIDE: |
628 | if (copy_to_user(argp, &deviceInfo.ulOverlayUVStride, sizeof(unsigned long))) | 627 | if (copy_to_user(argp, &deviceInfo.ulOverlayUVStride, sizeof(unsigned long))) |
629 | return -EFAULT; | 628 | return -EFAULT; |
@@ -736,10 +735,10 @@ static int kyrofb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
736 | if (register_framebuffer(info) < 0) | 735 | if (register_framebuffer(info) < 0) |
737 | goto out_unmap; | 736 | goto out_unmap; |
738 | 737 | ||
739 | printk("fb%d: %s frame buffer device, at %dx%d@%d using %ldk/%ldk of VRAM\n", | 738 | fb_info(info, "%s frame buffer device, at %dx%d@%d using %ldk/%ldk of VRAM\n", |
740 | info->node, info->fix.id, info->var.xres, | 739 | info->fix.id, |
741 | info->var.yres, info->var.bits_per_pixel, size >> 10, | 740 | info->var.xres, info->var.yres, info->var.bits_per_pixel, |
742 | (unsigned long)info->fix.smem_len >> 10); | 741 | size >> 10, (unsigned long)info->fix.smem_len >> 10); |
743 | 742 | ||
744 | pci_set_drvdata(pdev, info); | 743 | pci_set_drvdata(pdev, info); |
745 | 744 | ||
@@ -779,7 +778,6 @@ static void kyrofb_remove(struct pci_dev *pdev) | |||
779 | #endif | 778 | #endif |
780 | 779 | ||
781 | unregister_framebuffer(info); | 780 | unregister_framebuffer(info); |
782 | pci_set_drvdata(pdev, NULL); | ||
783 | framebuffer_release(info); | 781 | framebuffer_release(info); |
784 | } | 782 | } |
785 | 783 | ||
diff --git a/drivers/video/leo.c b/drivers/video/leo.c index b17f5009a436..2c7f7d479fe2 100644 --- a/drivers/video/leo.c +++ b/drivers/video/leo.c | |||
@@ -469,7 +469,7 @@ static void leo_wid_put(struct fb_info *info, struct fb_wid_list *wl) | |||
469 | 469 | ||
470 | default: | 470 | default: |
471 | continue; | 471 | continue; |
472 | }; | 472 | } |
473 | sbus_writel(0x5800 + j, &lx_krn->krn_type); | 473 | sbus_writel(0x5800 + j, &lx_krn->krn_type); |
474 | sbus_writel(wi->wi_values[0], &lx_krn->krn_value); | 474 | sbus_writel(wi->wi_values[0], &lx_krn->krn_value); |
475 | } | 475 | } |
@@ -648,8 +648,6 @@ static int leo_remove(struct platform_device *op) | |||
648 | 648 | ||
649 | framebuffer_release(info); | 649 | framebuffer_release(info); |
650 | 650 | ||
651 | dev_set_drvdata(&op->dev, NULL); | ||
652 | |||
653 | return 0; | 651 | return 0; |
654 | } | 652 | } |
655 | 653 | ||
diff --git a/drivers/video/macfb.c b/drivers/video/macfb.c index fe01add3700e..5bd2eb8d4f39 100644 --- a/drivers/video/macfb.c +++ b/drivers/video/macfb.c | |||
@@ -913,8 +913,7 @@ static int __init macfb_init(void) | |||
913 | if (err) | 913 | if (err) |
914 | goto fail_dealloc; | 914 | goto fail_dealloc; |
915 | 915 | ||
916 | pr_info("fb%d: %s frame buffer device\n", | 916 | fb_info(&fb_info, "%s frame buffer device\n", fb_info.fix.id); |
917 | fb_info.node, fb_info.fix.id); | ||
918 | 917 | ||
919 | return 0; | 918 | return 0; |
920 | 919 | ||
diff --git a/drivers/video/matrox/matroxfb_DAC1064.c b/drivers/video/matrox/matroxfb_DAC1064.c index 1717623aabc0..a01147fdf270 100644 --- a/drivers/video/matrox/matroxfb_DAC1064.c +++ b/drivers/video/matrox/matroxfb_DAC1064.c | |||
@@ -494,7 +494,7 @@ static int m1064_compute(void* out, struct my_timming* m) { | |||
494 | if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40) | 494 | if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40) |
495 | break; | 495 | break; |
496 | udelay(10); | 496 | udelay(10); |
497 | }; | 497 | } |
498 | 498 | ||
499 | CRITEND | 499 | CRITEND |
500 | 500 | ||
@@ -639,7 +639,7 @@ static void MGAG100_progPixClock(const struct matrox_fb_info *minfo, int flags, | |||
639 | if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40) | 639 | if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40) |
640 | break; | 640 | break; |
641 | udelay(10); | 641 | udelay(10); |
642 | }; | 642 | } |
643 | if (!clk) | 643 | if (!clk) |
644 | printk(KERN_ERR "matroxfb: Pixel PLL%c not locked after usual time\n", (reg-M1064_XPIXPLLAM-2)/4 + 'A'); | 644 | printk(KERN_ERR "matroxfb: Pixel PLL%c not locked after usual time\n", (reg-M1064_XPIXPLLAM-2)/4 + 'A'); |
645 | selClk = inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_SRC_MASK; | 645 | selClk = inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_SRC_MASK; |
diff --git a/drivers/video/matrox/matroxfb_Ti3026.c b/drivers/video/matrox/matroxfb_Ti3026.c index 9a44cec394b5..195ad7cac1ba 100644 --- a/drivers/video/matrox/matroxfb_Ti3026.c +++ b/drivers/video/matrox/matroxfb_Ti3026.c | |||
@@ -473,7 +473,7 @@ static void ti3026_setMCLK(struct matrox_fb_info *minfo, int fout) | |||
473 | if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40) | 473 | if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40) |
474 | break; | 474 | break; |
475 | udelay(10); | 475 | udelay(10); |
476 | }; | 476 | } |
477 | if (!tmout) | 477 | if (!tmout) |
478 | printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n"); | 478 | printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n"); |
479 | 479 | ||
diff --git a/drivers/video/matrox/matroxfb_base.c b/drivers/video/matrox/matroxfb_base.c index 245652911650..87c64ff4546c 100644 --- a/drivers/video/matrox/matroxfb_base.c +++ b/drivers/video/matrox/matroxfb_base.c | |||
@@ -1893,14 +1893,12 @@ static int initMatrox2(struct matrox_fb_info *minfo, struct board *b) | |||
1893 | if (register_framebuffer(&minfo->fbcon) < 0) { | 1893 | if (register_framebuffer(&minfo->fbcon) < 0) { |
1894 | goto failVideoIO; | 1894 | goto failVideoIO; |
1895 | } | 1895 | } |
1896 | printk("fb%d: %s frame buffer device\n", | 1896 | fb_info(&minfo->fbcon, "%s frame buffer device\n", minfo->fbcon.fix.id); |
1897 | minfo->fbcon.node, minfo->fbcon.fix.id); | ||
1898 | 1897 | ||
1899 | /* there is no console on this fb... but we have to initialize hardware | 1898 | /* there is no console on this fb... but we have to initialize hardware |
1900 | * until someone tells me what is proper thing to do */ | 1899 | * until someone tells me what is proper thing to do */ |
1901 | if (!minfo->initialized) { | 1900 | if (!minfo->initialized) { |
1902 | printk(KERN_INFO "fb%d: initializing hardware\n", | 1901 | fb_info(&minfo->fbcon, "initializing hardware\n"); |
1903 | minfo->fbcon.node); | ||
1904 | /* We have to use FB_ACTIVATE_FORCE, as we had to put vesafb_defined to the fbcon.var | 1902 | /* We have to use FB_ACTIVATE_FORCE, as we had to put vesafb_defined to the fbcon.var |
1905 | * already before, so register_framebuffer works correctly. */ | 1903 | * already before, so register_framebuffer works correctly. */ |
1906 | vesafb_defined.activate |= FB_ACTIVATE_FORCE; | 1904 | vesafb_defined.activate |= FB_ACTIVATE_FORCE; |
diff --git a/drivers/video/matrox/matroxfb_maven.c b/drivers/video/matrox/matroxfb_maven.c index fd2897455696..ee41a0f276b2 100644 --- a/drivers/video/matrox/matroxfb_maven.c +++ b/drivers/video/matrox/matroxfb_maven.c | |||
@@ -1295,19 +1295,7 @@ static struct i2c_driver maven_driver={ | |||
1295 | .id_table = maven_id, | 1295 | .id_table = maven_id, |
1296 | }; | 1296 | }; |
1297 | 1297 | ||
1298 | static int __init matroxfb_maven_init(void) | 1298 | module_i2c_driver(maven_driver); |
1299 | { | ||
1300 | return i2c_add_driver(&maven_driver); | ||
1301 | } | ||
1302 | |||
1303 | static void __exit matroxfb_maven_exit(void) | ||
1304 | { | ||
1305 | i2c_del_driver(&maven_driver); | ||
1306 | } | ||
1307 | |||
1308 | MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>"); | 1299 | MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>"); |
1309 | MODULE_DESCRIPTION("Matrox G200/G400 Matrox MGA-TVO driver"); | 1300 | MODULE_DESCRIPTION("Matrox G200/G400 Matrox MGA-TVO driver"); |
1310 | MODULE_LICENSE("GPL"); | 1301 | MODULE_LICENSE("GPL"); |
1311 | module_init(matroxfb_maven_init); | ||
1312 | module_exit(matroxfb_maven_exit); | ||
1313 | /* we do not have __setup() yet */ | ||
diff --git a/drivers/video/mb862xx/mb862xxfbdrv.c b/drivers/video/mb862xx/mb862xxfbdrv.c index 91c59c9fb082..0cd4c3318511 100644 --- a/drivers/video/mb862xx/mb862xxfbdrv.c +++ b/drivers/video/mb862xx/mb862xxfbdrv.c | |||
@@ -781,7 +781,6 @@ rel_reg: | |||
781 | irqdisp: | 781 | irqdisp: |
782 | irq_dispose_mapping(par->irq); | 782 | irq_dispose_mapping(par->irq); |
783 | fbrel: | 783 | fbrel: |
784 | dev_set_drvdata(dev, NULL); | ||
785 | framebuffer_release(info); | 784 | framebuffer_release(info); |
786 | return ret; | 785 | return ret; |
787 | } | 786 | } |
@@ -814,7 +813,6 @@ static int of_platform_mb862xx_remove(struct platform_device *ofdev) | |||
814 | iounmap(par->mmio_base); | 813 | iounmap(par->mmio_base); |
815 | iounmap(par->fb_base); | 814 | iounmap(par->fb_base); |
816 | 815 | ||
817 | dev_set_drvdata(&ofdev->dev, NULL); | ||
818 | release_mem_region(par->res->start, res_size); | 816 | release_mem_region(par->res->start, res_size); |
819 | framebuffer_release(fbi); | 817 | framebuffer_release(fbi); |
820 | return 0; | 818 | return 0; |
@@ -1157,7 +1155,6 @@ static void mb862xx_pci_remove(struct pci_dev *pdev) | |||
1157 | 1155 | ||
1158 | device_remove_file(&pdev->dev, &dev_attr_dispregs); | 1156 | device_remove_file(&pdev->dev, &dev_attr_dispregs); |
1159 | 1157 | ||
1160 | pci_set_drvdata(pdev, NULL); | ||
1161 | unregister_framebuffer(fbi); | 1158 | unregister_framebuffer(fbi); |
1162 | fb_dealloc_cmap(&fbi->cmap); | 1159 | fb_dealloc_cmap(&fbi->cmap); |
1163 | 1160 | ||
diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c index 0c1a874ffd2b..f0a5392f5fd3 100644 --- a/drivers/video/mbx/mbxfb.c +++ b/drivers/video/mbx/mbxfb.c | |||
@@ -890,7 +890,7 @@ static int mbxfb_probe(struct platform_device *dev) | |||
890 | 890 | ||
891 | dev_dbg(&dev->dev, "mbxfb_probe\n"); | 891 | dev_dbg(&dev->dev, "mbxfb_probe\n"); |
892 | 892 | ||
893 | pdata = dev->dev.platform_data; | 893 | pdata = dev_get_platdata(&dev->dev); |
894 | if (!pdata) { | 894 | if (!pdata) { |
895 | dev_err(&dev->dev, "platform data is required\n"); | 895 | dev_err(&dev->dev, "platform data is required\n"); |
896 | return -EINVAL; | 896 | return -EINVAL; |
@@ -976,7 +976,7 @@ static int mbxfb_probe(struct platform_device *dev) | |||
976 | 976 | ||
977 | platform_set_drvdata(dev, fbi); | 977 | platform_set_drvdata(dev, fbi); |
978 | 978 | ||
979 | printk(KERN_INFO "fb%d: mbx frame buffer device\n", fbi->node); | 979 | fb_info(fbi, "mbx frame buffer device\n"); |
980 | 980 | ||
981 | if (mfbi->platform_probe) | 981 | if (mfbi->platform_probe) |
982 | mfbi->platform_probe(fbi); | 982 | mfbi->platform_probe(fbi); |
diff --git a/drivers/video/metronomefb.c b/drivers/video/metronomefb.c index f30150d71be9..195cc2db4c2c 100644 --- a/drivers/video/metronomefb.c +++ b/drivers/video/metronomefb.c | |||
@@ -690,7 +690,8 @@ static int metronomefb_probe(struct platform_device *dev) | |||
690 | goto err_csum_table; | 690 | goto err_csum_table; |
691 | } | 691 | } |
692 | 692 | ||
693 | if (board->setup_irq(info)) | 693 | retval = board->setup_irq(info); |
694 | if (retval) | ||
694 | goto err_csum_table; | 695 | goto err_csum_table; |
695 | 696 | ||
696 | retval = metronome_init_regs(par); | 697 | retval = metronome_init_regs(par); |
@@ -769,23 +770,11 @@ static struct platform_driver metronomefb_driver = { | |||
769 | .name = "metronomefb", | 770 | .name = "metronomefb", |
770 | }, | 771 | }, |
771 | }; | 772 | }; |
772 | 773 | module_platform_driver(metronomefb_driver); | |
773 | static int __init metronomefb_init(void) | ||
774 | { | ||
775 | return platform_driver_register(&metronomefb_driver); | ||
776 | } | ||
777 | |||
778 | static void __exit metronomefb_exit(void) | ||
779 | { | ||
780 | platform_driver_unregister(&metronomefb_driver); | ||
781 | } | ||
782 | 774 | ||
783 | module_param(user_wfm_size, uint, 0); | 775 | module_param(user_wfm_size, uint, 0); |
784 | MODULE_PARM_DESC(user_wfm_size, "Set custom waveform size"); | 776 | MODULE_PARM_DESC(user_wfm_size, "Set custom waveform size"); |
785 | 777 | ||
786 | module_init(metronomefb_init); | ||
787 | module_exit(metronomefb_exit); | ||
788 | |||
789 | MODULE_DESCRIPTION("fbdev driver for Metronome controller"); | 778 | MODULE_DESCRIPTION("fbdev driver for Metronome controller"); |
790 | MODULE_AUTHOR("Jaya Kumar"); | 779 | MODULE_AUTHOR("Jaya Kumar"); |
791 | MODULE_LICENSE("GPL"); | 780 | MODULE_LICENSE("GPL"); |
diff --git a/drivers/video/mmp/fb/mmpfb.c b/drivers/video/mmp/fb/mmpfb.c index 4ab95b8daed3..7ab31eb76a8c 100644 --- a/drivers/video/mmp/fb/mmpfb.c +++ b/drivers/video/mmp/fb/mmpfb.c | |||
@@ -392,12 +392,29 @@ static int var_update(struct fb_info *info) | |||
392 | return 0; | 392 | return 0; |
393 | } | 393 | } |
394 | 394 | ||
395 | static void mmpfb_set_win(struct fb_info *info) | ||
396 | { | ||
397 | struct mmpfb_info *fbi = info->par; | ||
398 | struct fb_var_screeninfo *var = &info->var; | ||
399 | struct mmp_win win; | ||
400 | u32 stride; | ||
401 | |||
402 | memset(&win, 0, sizeof(win)); | ||
403 | win.xsrc = win.xdst = fbi->mode.xres; | ||
404 | win.ysrc = win.ydst = fbi->mode.yres; | ||
405 | win.pix_fmt = fbi->pix_fmt; | ||
406 | stride = pixfmt_to_stride(win.pix_fmt); | ||
407 | win.pitch[0] = var->xres_virtual * stride; | ||
408 | win.pitch[1] = win.pitch[2] = | ||
409 | (stride == 1) ? (var->xres_virtual >> 1) : 0; | ||
410 | mmp_overlay_set_win(fbi->overlay, &win); | ||
411 | } | ||
412 | |||
395 | static int mmpfb_set_par(struct fb_info *info) | 413 | static int mmpfb_set_par(struct fb_info *info) |
396 | { | 414 | { |
397 | struct mmpfb_info *fbi = info->par; | 415 | struct mmpfb_info *fbi = info->par; |
398 | struct fb_var_screeninfo *var = &info->var; | 416 | struct fb_var_screeninfo *var = &info->var; |
399 | struct mmp_addr addr; | 417 | struct mmp_addr addr; |
400 | struct mmp_win win; | ||
401 | struct mmp_mode mode; | 418 | struct mmp_mode mode; |
402 | int ret; | 419 | int ret; |
403 | 420 | ||
@@ -409,11 +426,8 @@ static int mmpfb_set_par(struct fb_info *info) | |||
409 | fbmode_to_mmpmode(&mode, &fbi->mode, fbi->output_fmt); | 426 | fbmode_to_mmpmode(&mode, &fbi->mode, fbi->output_fmt); |
410 | mmp_path_set_mode(fbi->path, &mode); | 427 | mmp_path_set_mode(fbi->path, &mode); |
411 | 428 | ||
412 | memset(&win, 0, sizeof(win)); | 429 | /* set window related info */ |
413 | win.xsrc = win.xdst = fbi->mode.xres; | 430 | mmpfb_set_win(info); |
414 | win.ysrc = win.ydst = fbi->mode.yres; | ||
415 | win.pix_fmt = fbi->pix_fmt; | ||
416 | mmp_overlay_set_win(fbi->overlay, &win); | ||
417 | 431 | ||
418 | /* set address always */ | 432 | /* set address always */ |
419 | memset(&addr, 0, sizeof(addr)); | 433 | memset(&addr, 0, sizeof(addr)); |
@@ -427,16 +441,12 @@ static int mmpfb_set_par(struct fb_info *info) | |||
427 | static void mmpfb_power(struct mmpfb_info *fbi, int power) | 441 | static void mmpfb_power(struct mmpfb_info *fbi, int power) |
428 | { | 442 | { |
429 | struct mmp_addr addr; | 443 | struct mmp_addr addr; |
430 | struct mmp_win win; | ||
431 | struct fb_var_screeninfo *var = &fbi->fb_info->var; | 444 | struct fb_var_screeninfo *var = &fbi->fb_info->var; |
432 | 445 | ||
433 | /* for power on, always set address/window again */ | 446 | /* for power on, always set address/window again */ |
434 | if (power) { | 447 | if (power) { |
435 | memset(&win, 0, sizeof(win)); | 448 | /* set window related info */ |
436 | win.xsrc = win.xdst = fbi->mode.xres; | 449 | mmpfb_set_win(fbi->fb_info); |
437 | win.ysrc = win.ydst = fbi->mode.yres; | ||
438 | win.pix_fmt = fbi->pix_fmt; | ||
439 | mmp_overlay_set_win(fbi->overlay, &win); | ||
440 | 450 | ||
441 | /* set address always */ | 451 | /* set address always */ |
442 | memset(&addr, 0, sizeof(addr)); | 452 | memset(&addr, 0, sizeof(addr)); |
diff --git a/drivers/video/mmp/hw/mmp_ctrl.c b/drivers/video/mmp/hw/mmp_ctrl.c index 6ac755270ab4..8621a9f2bdcc 100644 --- a/drivers/video/mmp/hw/mmp_ctrl.c +++ b/drivers/video/mmp/hw/mmp_ctrl.c | |||
@@ -53,15 +53,14 @@ static irqreturn_t ctrl_handle_irq(int irq, void *dev_id) | |||
53 | tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); | 53 | tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); |
54 | if (tmp & isr) | 54 | if (tmp & isr) |
55 | writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); | 55 | writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); |
56 | } while ((isr = readl(ctrl->reg_base + SPU_IRQ_ISR)) & imask); | 56 | } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask); |
57 | 57 | ||
58 | return IRQ_HANDLED; | 58 | return IRQ_HANDLED; |
59 | } | 59 | } |
60 | 60 | ||
61 | static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt) | 61 | static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt) |
62 | { | 62 | { |
63 | u32 link_config = path_to_path_plat(overlay->path)->link_config; | 63 | u32 rbswap = 0, uvswap = 0, yuvswap = 0, |
64 | u32 rbswap, uvswap = 0, yuvswap = 0, | ||
65 | csc_en = 0, val = 0, | 64 | csc_en = 0, val = 0, |
66 | vid = overlay_is_vid(overlay); | 65 | vid = overlay_is_vid(overlay); |
67 | 66 | ||
@@ -71,27 +70,23 @@ static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt) | |||
71 | case PIXFMT_RGB888PACK: | 70 | case PIXFMT_RGB888PACK: |
72 | case PIXFMT_RGB888UNPACK: | 71 | case PIXFMT_RGB888UNPACK: |
73 | case PIXFMT_RGBA888: | 72 | case PIXFMT_RGBA888: |
74 | rbswap = !(link_config & 0x1); | 73 | rbswap = 1; |
75 | break; | 74 | break; |
76 | case PIXFMT_VYUY: | 75 | case PIXFMT_VYUY: |
77 | case PIXFMT_YVU422P: | 76 | case PIXFMT_YVU422P: |
78 | case PIXFMT_YVU420P: | 77 | case PIXFMT_YVU420P: |
79 | rbswap = link_config & 0x1; | ||
80 | uvswap = 1; | 78 | uvswap = 1; |
81 | break; | 79 | break; |
82 | case PIXFMT_YUYV: | 80 | case PIXFMT_YUYV: |
83 | rbswap = link_config & 0x1; | ||
84 | yuvswap = 1; | 81 | yuvswap = 1; |
85 | break; | 82 | break; |
86 | default: | 83 | default: |
87 | rbswap = link_config & 0x1; | ||
88 | break; | 84 | break; |
89 | } | 85 | } |
90 | 86 | ||
91 | switch (pix_fmt) { | 87 | switch (pix_fmt) { |
92 | case PIXFMT_RGB565: | 88 | case PIXFMT_RGB565: |
93 | case PIXFMT_BGR565: | 89 | case PIXFMT_BGR565: |
94 | val = 0; | ||
95 | break; | 90 | break; |
96 | case PIXFMT_RGB1555: | 91 | case PIXFMT_RGB1555: |
97 | case PIXFMT_BGR1555: | 92 | case PIXFMT_BGR1555: |
@@ -147,17 +142,27 @@ static void dmafetch_set_fmt(struct mmp_overlay *overlay) | |||
147 | static void overlay_set_win(struct mmp_overlay *overlay, struct mmp_win *win) | 142 | static void overlay_set_win(struct mmp_overlay *overlay, struct mmp_win *win) |
148 | { | 143 | { |
149 | struct lcd_regs *regs = path_regs(overlay->path); | 144 | struct lcd_regs *regs = path_regs(overlay->path); |
150 | u32 pitch; | ||
151 | 145 | ||
152 | /* assert win supported */ | 146 | /* assert win supported */ |
153 | memcpy(&overlay->win, win, sizeof(struct mmp_win)); | 147 | memcpy(&overlay->win, win, sizeof(struct mmp_win)); |
154 | 148 | ||
155 | mutex_lock(&overlay->access_ok); | 149 | mutex_lock(&overlay->access_ok); |
156 | pitch = win->xsrc * pixfmt_to_stride(win->pix_fmt); | 150 | |
157 | writel_relaxed(pitch, ®s->g_pitch); | 151 | if (overlay_is_vid(overlay)) { |
158 | writel_relaxed((win->ysrc << 16) | win->xsrc, ®s->g_size); | 152 | writel_relaxed(win->pitch[0], ®s->v_pitch_yc); |
159 | writel_relaxed((win->ydst << 16) | win->xdst, ®s->g_size_z); | 153 | writel_relaxed(win->pitch[2] << 16 | |
160 | writel_relaxed(0, ®s->g_start); | 154 | win->pitch[1], ®s->v_pitch_uv); |
155 | |||
156 | writel_relaxed((win->ysrc << 16) | win->xsrc, ®s->v_size); | ||
157 | writel_relaxed((win->ydst << 16) | win->xdst, ®s->v_size_z); | ||
158 | writel_relaxed(win->ypos << 16 | win->xpos, ®s->v_start); | ||
159 | } else { | ||
160 | writel_relaxed(win->pitch[0], ®s->g_pitch); | ||
161 | |||
162 | writel_relaxed((win->ysrc << 16) | win->xsrc, ®s->g_size); | ||
163 | writel_relaxed((win->ydst << 16) | win->xdst, ®s->g_size_z); | ||
164 | writel_relaxed(win->ypos << 16 | win->xpos, ®s->g_start); | ||
165 | } | ||
161 | 166 | ||
162 | dmafetch_set_fmt(overlay); | 167 | dmafetch_set_fmt(overlay); |
163 | mutex_unlock(&overlay->access_ok); | 168 | mutex_unlock(&overlay->access_ok); |
@@ -239,7 +244,13 @@ static int overlay_set_addr(struct mmp_overlay *overlay, struct mmp_addr *addr) | |||
239 | 244 | ||
240 | /* FIXME: assert addr supported */ | 245 | /* FIXME: assert addr supported */ |
241 | memcpy(&overlay->addr, addr, sizeof(struct mmp_addr)); | 246 | memcpy(&overlay->addr, addr, sizeof(struct mmp_addr)); |
242 | writel(addr->phys[0], ®s->g_0); | 247 | |
248 | if (overlay_is_vid(overlay)) { | ||
249 | writel_relaxed(addr->phys[0], ®s->v_y0); | ||
250 | writel_relaxed(addr->phys[1], ®s->v_u0); | ||
251 | writel_relaxed(addr->phys[2], ®s->v_v0); | ||
252 | } else | ||
253 | writel_relaxed(addr->phys[0], ®s->g_0); | ||
243 | 254 | ||
244 | return overlay->addr.phys[0]; | 255 | return overlay->addr.phys[0]; |
245 | } | 256 | } |
@@ -248,7 +259,8 @@ static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode) | |||
248 | { | 259 | { |
249 | struct lcd_regs *regs = path_regs(path); | 260 | struct lcd_regs *regs = path_regs(path); |
250 | u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div, | 261 | u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div, |
251 | link_config = path_to_path_plat(path)->link_config; | 262 | link_config = path_to_path_plat(path)->link_config, |
263 | dsi_rbswap = path_to_path_plat(path)->link_config; | ||
252 | 264 | ||
253 | /* FIXME: assert videomode supported */ | 265 | /* FIXME: assert videomode supported */ |
254 | memcpy(&path->mode, mode, sizeof(struct mmp_mode)); | 266 | memcpy(&path->mode, mode, sizeof(struct mmp_mode)); |
@@ -263,6 +275,12 @@ static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode) | |||
263 | tmp |= CFG_DUMB_ENA(1); | 275 | tmp |= CFG_DUMB_ENA(1); |
264 | writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id)); | 276 | writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id)); |
265 | 277 | ||
278 | /* interface rb_swap setting */ | ||
279 | tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) & | ||
280 | (~(CFG_INTFRBSWAP_MASK)); | ||
281 | tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK; | ||
282 | writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id)); | ||
283 | |||
266 | writel_relaxed((mode->yres << 16) | mode->xres, ®s->screen_active); | 284 | writel_relaxed((mode->yres << 16) | mode->xres, ®s->screen_active); |
267 | writel_relaxed((mode->left_margin << 16) | mode->right_margin, | 285 | writel_relaxed((mode->left_margin << 16) | mode->right_margin, |
268 | ®s->screen_h_porch); | 286 | ®s->screen_h_porch); |
@@ -370,20 +388,12 @@ static void path_set_default(struct mmp_path *path) | |||
370 | * bus arbiter for faster read if not tv path; | 388 | * bus arbiter for faster read if not tv path; |
371 | * 2.enable horizontal smooth filter; | 389 | * 2.enable horizontal smooth filter; |
372 | */ | 390 | */ |
373 | if (PATH_PN == path->id) { | 391 | mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1); |
374 | mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | 392 | tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); |
375 | | CFG_ARBFAST_ENA(1); | 393 | tmp |= mask; |
376 | tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); | 394 | if (PATH_TV == path->id) |
377 | tmp |= mask; | 395 | tmp &= ~CFG_ARBFAST_ENA(1); |
378 | writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); | 396 | writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); |
379 | } else if (PATH_TV == path->id) { | ||
380 | mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | ||
381 | | CFG_ARBFAST_ENA(1); | ||
382 | tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); | ||
383 | tmp &= ~mask; | ||
384 | tmp |= CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK; | ||
385 | writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); | ||
386 | } | ||
387 | } | 397 | } |
388 | 398 | ||
389 | static int path_init(struct mmphw_path_plat *path_plat, | 399 | static int path_init(struct mmphw_path_plat *path_plat, |
@@ -419,6 +429,7 @@ static int path_init(struct mmphw_path_plat *path_plat, | |||
419 | path_plat->path = path; | 429 | path_plat->path = path; |
420 | path_plat->path_config = config->path_config; | 430 | path_plat->path_config = config->path_config; |
421 | path_plat->link_config = config->link_config; | 431 | path_plat->link_config = config->link_config; |
432 | path_plat->dsi_rbswap = config->dsi_rbswap; | ||
422 | path_set_default(path); | 433 | path_set_default(path); |
423 | 434 | ||
424 | kfree(path_info); | 435 | kfree(path_info); |
diff --git a/drivers/video/mmp/hw/mmp_ctrl.h b/drivers/video/mmp/hw/mmp_ctrl.h index edd2002b0e99..53301cfdb1ae 100644 --- a/drivers/video/mmp/hw/mmp_ctrl.h +++ b/drivers/video/mmp/hw/mmp_ctrl.h | |||
@@ -163,6 +163,8 @@ struct lcd_regs { | |||
163 | 163 | ||
164 | #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\ | 164 | #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\ |
165 | ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV)) | 165 | ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV)) |
166 | #define intf_rbswap_ctrl(id) ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \ | ||
167 | PN2_IOPAD_CONTROL) : LCD_TOP_CTRL) | ||
166 | 168 | ||
167 | /* dither configure */ | 169 | /* dither configure */ |
168 | #ifdef CONFIG_CPU_PXA988 | 170 | #ifdef CONFIG_CPU_PXA988 |
@@ -615,6 +617,8 @@ struct lcd_regs { | |||
615 | #define LCD_SPU_DUMB_CTRL 0x01B8 | 617 | #define LCD_SPU_DUMB_CTRL 0x01B8 |
616 | #define CFG_DUMBMODE(mode) ((mode)<<28) | 618 | #define CFG_DUMBMODE(mode) ((mode)<<28) |
617 | #define CFG_DUMBMODE_MASK 0xF0000000 | 619 | #define CFG_DUMBMODE_MASK 0xF0000000 |
620 | #define CFG_INTFRBSWAP(mode) ((mode)<<24) | ||
621 | #define CFG_INTFRBSWAP_MASK 0x0F000000 | ||
618 | #define CFG_LCDGPIO_O(data) ((data)<<20) | 622 | #define CFG_LCDGPIO_O(data) ((data)<<20) |
619 | #define CFG_LCDGPIO_O_MASK 0x0FF00000 | 623 | #define CFG_LCDGPIO_O_MASK 0x0FF00000 |
620 | #define CFG_LCDGPIO_ENA(gpio) ((gpio)<<12) | 624 | #define CFG_LCDGPIO_ENA(gpio) ((gpio)<<12) |
@@ -1427,6 +1431,7 @@ struct mmphw_path_plat { | |||
1427 | struct mmp_path *path; | 1431 | struct mmp_path *path; |
1428 | u32 path_config; | 1432 | u32 path_config; |
1429 | u32 link_config; | 1433 | u32 link_config; |
1434 | u32 dsi_rbswap; | ||
1430 | }; | 1435 | }; |
1431 | 1436 | ||
1432 | /* mmp ctrl describes mmp controller related info */ | 1437 | /* mmp ctrl describes mmp controller related info */ |
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c index cfdb380ec81e..804f874d32d3 100644 --- a/drivers/video/mx3fb.c +++ b/drivers/video/mx3fb.c | |||
@@ -1354,7 +1354,7 @@ static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops) | |||
1354 | static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan) | 1354 | static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan) |
1355 | { | 1355 | { |
1356 | struct device *dev = mx3fb->dev; | 1356 | struct device *dev = mx3fb->dev; |
1357 | struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data; | 1357 | struct mx3fb_platform_data *mx3fb_pdata = dev_get_platdata(dev); |
1358 | const char *name = mx3fb_pdata->name; | 1358 | const char *name = mx3fb_pdata->name; |
1359 | unsigned int irq; | 1359 | unsigned int irq; |
1360 | struct fb_info *fbi; | 1360 | struct fb_info *fbi; |
@@ -1462,7 +1462,7 @@ static bool chan_filter(struct dma_chan *chan, void *arg) | |||
1462 | return false; | 1462 | return false; |
1463 | 1463 | ||
1464 | dev = rq->mx3fb->dev; | 1464 | dev = rq->mx3fb->dev; |
1465 | mx3fb_pdata = dev->platform_data; | 1465 | mx3fb_pdata = dev_get_platdata(dev); |
1466 | 1466 | ||
1467 | return rq->id == chan->chan_id && | 1467 | return rq->id == chan->chan_id && |
1468 | mx3fb_pdata->dma_dev == chan->device->dev; | 1468 | mx3fb_pdata->dma_dev == chan->device->dev; |
diff --git a/drivers/video/neofb.c b/drivers/video/neofb.c index c172a5281f9e..44f99a60bb9b 100644 --- a/drivers/video/neofb.c +++ b/drivers/video/neofb.c | |||
@@ -2106,8 +2106,7 @@ static int neofb_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
2106 | if (err < 0) | 2106 | if (err < 0) |
2107 | goto err_reg_fb; | 2107 | goto err_reg_fb; |
2108 | 2108 | ||
2109 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 2109 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
2110 | info->node, info->fix.id); | ||
2111 | 2110 | ||
2112 | /* | 2111 | /* |
2113 | * Our driver data | 2112 | * Our driver data |
@@ -2148,12 +2147,6 @@ static void neofb_remove(struct pci_dev *dev) | |||
2148 | fb_destroy_modedb(info->monspecs.modedb); | 2147 | fb_destroy_modedb(info->monspecs.modedb); |
2149 | neo_unmap_mmio(info); | 2148 | neo_unmap_mmio(info); |
2150 | neo_free_fb_info(info); | 2149 | neo_free_fb_info(info); |
2151 | |||
2152 | /* | ||
2153 | * Ensure that the driver data is no longer | ||
2154 | * valid. | ||
2155 | */ | ||
2156 | pci_set_drvdata(dev, NULL); | ||
2157 | } | 2150 | } |
2158 | } | 2151 | } |
2159 | 2152 | ||
diff --git a/drivers/video/nuc900fb.c b/drivers/video/nuc900fb.c index 796e5112ceee..478f9808dee4 100644 --- a/drivers/video/nuc900fb.c +++ b/drivers/video/nuc900fb.c | |||
@@ -91,7 +91,7 @@ static int nuc900fb_check_var(struct fb_var_screeninfo *var, | |||
91 | struct fb_info *info) | 91 | struct fb_info *info) |
92 | { | 92 | { |
93 | struct nuc900fb_info *fbi = info->par; | 93 | struct nuc900fb_info *fbi = info->par; |
94 | struct nuc900fb_mach_info *mach_info = fbi->dev->platform_data; | 94 | struct nuc900fb_mach_info *mach_info = dev_get_platdata(fbi->dev); |
95 | struct nuc900fb_display *display = NULL; | 95 | struct nuc900fb_display *display = NULL; |
96 | struct nuc900fb_display *default_display = mach_info->displays + | 96 | struct nuc900fb_display *default_display = mach_info->displays + |
97 | mach_info->default_display; | 97 | mach_info->default_display; |
@@ -358,7 +358,7 @@ static inline void modify_gpio(void __iomem *reg, | |||
358 | static int nuc900fb_init_registers(struct fb_info *info) | 358 | static int nuc900fb_init_registers(struct fb_info *info) |
359 | { | 359 | { |
360 | struct nuc900fb_info *fbi = info->par; | 360 | struct nuc900fb_info *fbi = info->par; |
361 | struct nuc900fb_mach_info *mach_info = fbi->dev->platform_data; | 361 | struct nuc900fb_mach_info *mach_info = dev_get_platdata(fbi->dev); |
362 | void __iomem *regs = fbi->io; | 362 | void __iomem *regs = fbi->io; |
363 | 363 | ||
364 | /*reset the display engine*/ | 364 | /*reset the display engine*/ |
@@ -512,7 +512,7 @@ static int nuc900fb_probe(struct platform_device *pdev) | |||
512 | int size; | 512 | int size; |
513 | 513 | ||
514 | dev_dbg(&pdev->dev, "devinit\n"); | 514 | dev_dbg(&pdev->dev, "devinit\n"); |
515 | mach_info = pdev->dev.platform_data; | 515 | mach_info = dev_get_platdata(&pdev->dev); |
516 | if (mach_info == NULL) { | 516 | if (mach_info == NULL) { |
517 | dev_err(&pdev->dev, | 517 | dev_err(&pdev->dev, |
518 | "no platform data for lcd, cannot attach\n"); | 518 | "no platform data for lcd, cannot attach\n"); |
@@ -647,8 +647,7 @@ static int nuc900fb_probe(struct platform_device *pdev) | |||
647 | goto free_cpufreq; | 647 | goto free_cpufreq; |
648 | } | 648 | } |
649 | 649 | ||
650 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 650 | fb_info(fbinfo, "%s frame buffer device\n", fbinfo->fix.id); |
651 | fbinfo->node, fbinfo->fix.id); | ||
652 | 651 | ||
653 | return 0; | 652 | return 0; |
654 | 653 | ||
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c index ed20a9871b33..81c80ac3c76f 100644 --- a/drivers/video/nvidia/nv_hw.c +++ b/drivers/video/nvidia/nv_hw.c | |||
@@ -1300,7 +1300,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) | |||
1300 | break; | 1300 | break; |
1301 | default: | 1301 | default: |
1302 | break; | 1302 | break; |
1303 | }; | 1303 | } |
1304 | 1304 | ||
1305 | NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800); | 1305 | NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800); |
1306 | NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000); | 1306 | NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000); |
diff --git a/drivers/video/offb.c b/drivers/video/offb.c index 0c4f34311eda..9dbea2223401 100644 --- a/drivers/video/offb.c +++ b/drivers/video/offb.c | |||
@@ -515,8 +515,7 @@ static void __init offb_init_fb(const char *name, const char *full_name, | |||
515 | if (register_framebuffer(info) < 0) | 515 | if (register_framebuffer(info) < 0) |
516 | goto out_err; | 516 | goto out_err; |
517 | 517 | ||
518 | printk(KERN_INFO "fb%d: Open Firmware frame buffer device on %s\n", | 518 | fb_info(info, "Open Firmware frame buffer device on %s\n", full_name); |
519 | info->node, full_name); | ||
520 | return; | 519 | return; |
521 | 520 | ||
522 | out_err: | 521 | out_err: |
diff --git a/drivers/video/omap/hwa742.c b/drivers/video/omap/hwa742.c index f349ee6f0cea..a4ee65b8f918 100644 --- a/drivers/video/omap/hwa742.c +++ b/drivers/video/omap/hwa742.c | |||
@@ -947,7 +947,7 @@ static int hwa742_init(struct omapfb_device *fbdev, int ext_mode, | |||
947 | hwa742.extif = fbdev->ext_if; | 947 | hwa742.extif = fbdev->ext_if; |
948 | hwa742.int_ctrl = fbdev->int_ctrl; | 948 | hwa742.int_ctrl = fbdev->int_ctrl; |
949 | 949 | ||
950 | omapfb_conf = fbdev->dev->platform_data; | 950 | omapfb_conf = dev_get_platdata(fbdev->dev); |
951 | 951 | ||
952 | hwa742.sys_ck = clk_get(NULL, "hwa_sys_ck"); | 952 | hwa742.sys_ck = clk_get(NULL, "hwa_sys_ck"); |
953 | 953 | ||
diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c index d40612c31a98..e4fc6d9b5371 100644 --- a/drivers/video/omap/omapfb_main.c +++ b/drivers/video/omap/omapfb_main.c | |||
@@ -1602,7 +1602,7 @@ static int omapfb_find_ctrl(struct omapfb_device *fbdev) | |||
1602 | char name[17]; | 1602 | char name[17]; |
1603 | int i; | 1603 | int i; |
1604 | 1604 | ||
1605 | conf = fbdev->dev->platform_data; | 1605 | conf = dev_get_platdata(fbdev->dev); |
1606 | 1606 | ||
1607 | fbdev->ctrl = NULL; | 1607 | fbdev->ctrl = NULL; |
1608 | 1608 | ||
@@ -1674,7 +1674,7 @@ static int omapfb_do_probe(struct platform_device *pdev, | |||
1674 | goto cleanup; | 1674 | goto cleanup; |
1675 | } | 1675 | } |
1676 | 1676 | ||
1677 | if (pdev->dev.platform_data == NULL) { | 1677 | if (dev_get_platdata(&pdev->dev) == NULL) { |
1678 | dev_err(&pdev->dev, "missing platform data\n"); | 1678 | dev_err(&pdev->dev, "missing platform data\n"); |
1679 | r = -ENOENT; | 1679 | r = -ENOENT; |
1680 | goto cleanup; | 1680 | goto cleanup; |
diff --git a/drivers/video/omap2/displays-new/Kconfig b/drivers/video/omap2/displays-new/Kconfig index 10b25e7cd878..e6cfc38160d3 100644 --- a/drivers/video/omap2/displays-new/Kconfig +++ b/drivers/video/omap2/displays-new/Kconfig | |||
@@ -57,6 +57,12 @@ config DISPLAY_PANEL_SHARP_LS037V7DW01 | |||
57 | help | 57 | help |
58 | LCD Panel used in TI's SDP3430 and EVM boards | 58 | LCD Panel used in TI's SDP3430 and EVM boards |
59 | 59 | ||
60 | config DISPLAY_PANEL_TPO_TD028TTEC1 | ||
61 | tristate "TPO TD028TTEC1 LCD Panel" | ||
62 | depends on SPI | ||
63 | help | ||
64 | LCD panel used in Openmoko. | ||
65 | |||
60 | config DISPLAY_PANEL_TPO_TD043MTEA1 | 66 | config DISPLAY_PANEL_TPO_TD043MTEA1 |
61 | tristate "TPO TD043MTEA1 LCD Panel" | 67 | tristate "TPO TD043MTEA1 LCD Panel" |
62 | depends on SPI | 68 | depends on SPI |
diff --git a/drivers/video/omap2/displays-new/Makefile b/drivers/video/omap2/displays-new/Makefile index 5aeb11b8fcd5..0323a8a1c682 100644 --- a/drivers/video/omap2/displays-new/Makefile +++ b/drivers/video/omap2/displays-new/Makefile | |||
@@ -8,5 +8,6 @@ obj-$(CONFIG_DISPLAY_PANEL_DSI_CM) += panel-dsi-cm.o | |||
8 | obj-$(CONFIG_DISPLAY_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o | 8 | obj-$(CONFIG_DISPLAY_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o |
9 | obj-$(CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02) += panel-lgphilips-lb035q02.o | 9 | obj-$(CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02) += panel-lgphilips-lb035q02.o |
10 | obj-$(CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o | 10 | obj-$(CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o |
11 | obj-$(CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1) += panel-tpo-td028ttec1.o | ||
11 | obj-$(CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o | 12 | obj-$(CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o |
12 | obj-$(CONFIG_DISPLAY_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o | 13 | obj-$(CONFIG_DISPLAY_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o |
diff --git a/drivers/video/omap2/displays-new/connector-dvi.c b/drivers/video/omap2/displays-new/connector-dvi.c index 63d88ee6dfe4..b6c50904038e 100644 --- a/drivers/video/omap2/displays-new/connector-dvi.c +++ b/drivers/video/omap2/displays-new/connector-dvi.c | |||
@@ -262,6 +262,9 @@ static int dvic_probe_pdata(struct platform_device *pdev) | |||
262 | 262 | ||
263 | in = omap_dss_find_output(pdata->source); | 263 | in = omap_dss_find_output(pdata->source); |
264 | if (in == NULL) { | 264 | if (in == NULL) { |
265 | if (ddata->i2c_adapter) | ||
266 | i2c_put_adapter(ddata->i2c_adapter); | ||
267 | |||
265 | dev_err(&pdev->dev, "Failed to find video source\n"); | 268 | dev_err(&pdev->dev, "Failed to find video source\n"); |
266 | return -EPROBE_DEFER; | 269 | return -EPROBE_DEFER; |
267 | } | 270 | } |
@@ -313,6 +316,10 @@ static int dvic_probe(struct platform_device *pdev) | |||
313 | 316 | ||
314 | err_reg: | 317 | err_reg: |
315 | omap_dss_put_device(ddata->in); | 318 | omap_dss_put_device(ddata->in); |
319 | |||
320 | if (ddata->i2c_adapter) | ||
321 | i2c_put_adapter(ddata->i2c_adapter); | ||
322 | |||
316 | return r; | 323 | return r; |
317 | } | 324 | } |
318 | 325 | ||
diff --git a/drivers/video/omap2/displays-new/panel-dsi-cm.c b/drivers/video/omap2/displays-new/panel-dsi-cm.c index aaaea6469cd9..b7baafe83aa3 100644 --- a/drivers/video/omap2/displays-new/panel-dsi-cm.c +++ b/drivers/video/omap2/displays-new/panel-dsi-cm.c | |||
@@ -599,7 +599,7 @@ static int dsicm_power_on(struct panel_drv_data *ddata) | |||
599 | if (r) { | 599 | if (r) { |
600 | dev_err(&ddata->pdev->dev, "failed to configure DSI pins\n"); | 600 | dev_err(&ddata->pdev->dev, "failed to configure DSI pins\n"); |
601 | goto err0; | 601 | goto err0; |
602 | }; | 602 | } |
603 | 603 | ||
604 | r = in->ops.dsi->set_config(in, &dsi_config); | 604 | r = in->ops.dsi->set_config(in, &dsi_config); |
605 | if (r) { | 605 | if (r) { |
diff --git a/drivers/video/omap2/displays-new/panel-tpo-td028ttec1.c b/drivers/video/omap2/displays-new/panel-tpo-td028ttec1.c new file mode 100644 index 000000000000..9a08908fe998 --- /dev/null +++ b/drivers/video/omap2/displays-new/panel-tpo-td028ttec1.c | |||
@@ -0,0 +1,480 @@ | |||
1 | /* | ||
2 | * Toppoly TD028TTEC1 panel support | ||
3 | * | ||
4 | * Copyright (C) 2008 Nokia Corporation | ||
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | ||
6 | * | ||
7 | * Neo 1973 code (jbt6k74.c): | ||
8 | * Copyright (C) 2006-2007 by OpenMoko, Inc. | ||
9 | * Author: Harald Welte <laforge@openmoko.org> | ||
10 | * | ||
11 | * Ported and adapted from Neo 1973 U-Boot by: | ||
12 | * H. Nikolaus Schaller <hns@goldelico.com> | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify it | ||
15 | * under the terms of the GNU General Public License version 2 as published by | ||
16 | * the Free Software Foundation. | ||
17 | * | ||
18 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
19 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
20 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
21 | * more details. | ||
22 | * | ||
23 | * You should have received a copy of the GNU General Public License along with | ||
24 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
25 | */ | ||
26 | |||
27 | #include <linux/module.h> | ||
28 | #include <linux/delay.h> | ||
29 | #include <linux/spi/spi.h> | ||
30 | #include <linux/gpio.h> | ||
31 | #include <video/omapdss.h> | ||
32 | #include <video/omap-panel-data.h> | ||
33 | |||
34 | struct panel_drv_data { | ||
35 | struct omap_dss_device dssdev; | ||
36 | struct omap_dss_device *in; | ||
37 | |||
38 | int data_lines; | ||
39 | |||
40 | struct omap_video_timings videomode; | ||
41 | |||
42 | struct spi_device *spi_dev; | ||
43 | }; | ||
44 | |||
45 | static struct omap_video_timings td028ttec1_panel_timings = { | ||
46 | .x_res = 480, | ||
47 | .y_res = 640, | ||
48 | .pixel_clock = 22153, | ||
49 | .hfp = 24, | ||
50 | .hsw = 8, | ||
51 | .hbp = 8, | ||
52 | .vfp = 4, | ||
53 | .vsw = 2, | ||
54 | .vbp = 2, | ||
55 | |||
56 | .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, | ||
57 | .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, | ||
58 | |||
59 | .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, | ||
60 | .de_level = OMAPDSS_SIG_ACTIVE_HIGH, | ||
61 | .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES, | ||
62 | }; | ||
63 | |||
64 | #define JBT_COMMAND 0x000 | ||
65 | #define JBT_DATA 0x100 | ||
66 | |||
67 | static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg) | ||
68 | { | ||
69 | int rc; | ||
70 | u16 tx_buf = JBT_COMMAND | reg; | ||
71 | |||
72 | rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf, | ||
73 | 1*sizeof(u16)); | ||
74 | if (rc != 0) | ||
75 | dev_err(&ddata->spi_dev->dev, | ||
76 | "jbt_ret_write_0 spi_write ret %d\n", rc); | ||
77 | |||
78 | return rc; | ||
79 | } | ||
80 | |||
81 | static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data) | ||
82 | { | ||
83 | int rc; | ||
84 | u16 tx_buf[2]; | ||
85 | |||
86 | tx_buf[0] = JBT_COMMAND | reg; | ||
87 | tx_buf[1] = JBT_DATA | data; | ||
88 | rc = spi_write(ddata->spi_dev, (u8 *)tx_buf, | ||
89 | 2*sizeof(u16)); | ||
90 | if (rc != 0) | ||
91 | dev_err(&ddata->spi_dev->dev, | ||
92 | "jbt_reg_write_1 spi_write ret %d\n", rc); | ||
93 | |||
94 | return rc; | ||
95 | } | ||
96 | |||
97 | static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data) | ||
98 | { | ||
99 | int rc; | ||
100 | u16 tx_buf[3]; | ||
101 | |||
102 | tx_buf[0] = JBT_COMMAND | reg; | ||
103 | tx_buf[1] = JBT_DATA | (data >> 8); | ||
104 | tx_buf[2] = JBT_DATA | (data & 0xff); | ||
105 | |||
106 | rc = spi_write(ddata->spi_dev, (u8 *)tx_buf, | ||
107 | 3*sizeof(u16)); | ||
108 | |||
109 | if (rc != 0) | ||
110 | dev_err(&ddata->spi_dev->dev, | ||
111 | "jbt_reg_write_2 spi_write ret %d\n", rc); | ||
112 | |||
113 | return rc; | ||
114 | } | ||
115 | |||
116 | enum jbt_register { | ||
117 | JBT_REG_SLEEP_IN = 0x10, | ||
118 | JBT_REG_SLEEP_OUT = 0x11, | ||
119 | |||
120 | JBT_REG_DISPLAY_OFF = 0x28, | ||
121 | JBT_REG_DISPLAY_ON = 0x29, | ||
122 | |||
123 | JBT_REG_RGB_FORMAT = 0x3a, | ||
124 | JBT_REG_QUAD_RATE = 0x3b, | ||
125 | |||
126 | JBT_REG_POWER_ON_OFF = 0xb0, | ||
127 | JBT_REG_BOOSTER_OP = 0xb1, | ||
128 | JBT_REG_BOOSTER_MODE = 0xb2, | ||
129 | JBT_REG_BOOSTER_FREQ = 0xb3, | ||
130 | JBT_REG_OPAMP_SYSCLK = 0xb4, | ||
131 | JBT_REG_VSC_VOLTAGE = 0xb5, | ||
132 | JBT_REG_VCOM_VOLTAGE = 0xb6, | ||
133 | JBT_REG_EXT_DISPL = 0xb7, | ||
134 | JBT_REG_OUTPUT_CONTROL = 0xb8, | ||
135 | JBT_REG_DCCLK_DCEV = 0xb9, | ||
136 | JBT_REG_DISPLAY_MODE1 = 0xba, | ||
137 | JBT_REG_DISPLAY_MODE2 = 0xbb, | ||
138 | JBT_REG_DISPLAY_MODE = 0xbc, | ||
139 | JBT_REG_ASW_SLEW = 0xbd, | ||
140 | JBT_REG_DUMMY_DISPLAY = 0xbe, | ||
141 | JBT_REG_DRIVE_SYSTEM = 0xbf, | ||
142 | |||
143 | JBT_REG_SLEEP_OUT_FR_A = 0xc0, | ||
144 | JBT_REG_SLEEP_OUT_FR_B = 0xc1, | ||
145 | JBT_REG_SLEEP_OUT_FR_C = 0xc2, | ||
146 | JBT_REG_SLEEP_IN_LCCNT_D = 0xc3, | ||
147 | JBT_REG_SLEEP_IN_LCCNT_E = 0xc4, | ||
148 | JBT_REG_SLEEP_IN_LCCNT_F = 0xc5, | ||
149 | JBT_REG_SLEEP_IN_LCCNT_G = 0xc6, | ||
150 | |||
151 | JBT_REG_GAMMA1_FINE_1 = 0xc7, | ||
152 | JBT_REG_GAMMA1_FINE_2 = 0xc8, | ||
153 | JBT_REG_GAMMA1_INCLINATION = 0xc9, | ||
154 | JBT_REG_GAMMA1_BLUE_OFFSET = 0xca, | ||
155 | |||
156 | JBT_REG_BLANK_CONTROL = 0xcf, | ||
157 | JBT_REG_BLANK_TH_TV = 0xd0, | ||
158 | JBT_REG_CKV_ON_OFF = 0xd1, | ||
159 | JBT_REG_CKV_1_2 = 0xd2, | ||
160 | JBT_REG_OEV_TIMING = 0xd3, | ||
161 | JBT_REG_ASW_TIMING_1 = 0xd4, | ||
162 | JBT_REG_ASW_TIMING_2 = 0xd5, | ||
163 | |||
164 | JBT_REG_HCLOCK_VGA = 0xec, | ||
165 | JBT_REG_HCLOCK_QVGA = 0xed, | ||
166 | }; | ||
167 | |||
168 | #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) | ||
169 | |||
170 | static int td028ttec1_panel_connect(struct omap_dss_device *dssdev) | ||
171 | { | ||
172 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
173 | struct omap_dss_device *in = ddata->in; | ||
174 | int r; | ||
175 | |||
176 | if (omapdss_device_is_connected(dssdev)) | ||
177 | return 0; | ||
178 | |||
179 | r = in->ops.dpi->connect(in, dssdev); | ||
180 | if (r) | ||
181 | return r; | ||
182 | |||
183 | return 0; | ||
184 | } | ||
185 | |||
186 | static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev) | ||
187 | { | ||
188 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
189 | struct omap_dss_device *in = ddata->in; | ||
190 | |||
191 | if (!omapdss_device_is_connected(dssdev)) | ||
192 | return; | ||
193 | |||
194 | in->ops.dpi->disconnect(in, dssdev); | ||
195 | } | ||
196 | |||
197 | static int td028ttec1_panel_enable(struct omap_dss_device *dssdev) | ||
198 | { | ||
199 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
200 | struct omap_dss_device *in = ddata->in; | ||
201 | int r; | ||
202 | |||
203 | if (!omapdss_device_is_connected(dssdev)) | ||
204 | return -ENODEV; | ||
205 | |||
206 | if (omapdss_device_is_enabled(dssdev)) | ||
207 | return 0; | ||
208 | |||
209 | in->ops.dpi->set_data_lines(in, ddata->data_lines); | ||
210 | in->ops.dpi->set_timings(in, &ddata->videomode); | ||
211 | |||
212 | r = in->ops.dpi->enable(in); | ||
213 | if (r) | ||
214 | return r; | ||
215 | |||
216 | dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n", | ||
217 | dssdev->state); | ||
218 | |||
219 | /* three times command zero */ | ||
220 | r |= jbt_ret_write_0(ddata, 0x00); | ||
221 | usleep_range(1000, 2000); | ||
222 | r |= jbt_ret_write_0(ddata, 0x00); | ||
223 | usleep_range(1000, 2000); | ||
224 | r |= jbt_ret_write_0(ddata, 0x00); | ||
225 | usleep_range(1000, 2000); | ||
226 | |||
227 | if (r) { | ||
228 | dev_warn(dssdev->dev, "transfer error\n"); | ||
229 | goto transfer_err; | ||
230 | } | ||
231 | |||
232 | /* deep standby out */ | ||
233 | r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17); | ||
234 | |||
235 | /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */ | ||
236 | r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80); | ||
237 | |||
238 | /* Quad mode off */ | ||
239 | r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00); | ||
240 | |||
241 | /* AVDD on, XVDD on */ | ||
242 | r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16); | ||
243 | |||
244 | /* Output control */ | ||
245 | r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9); | ||
246 | |||
247 | /* Sleep mode off */ | ||
248 | r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT); | ||
249 | |||
250 | /* at this point we have like 50% grey */ | ||
251 | |||
252 | /* initialize register set */ | ||
253 | r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01); | ||
254 | r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00); | ||
255 | r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60); | ||
256 | r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10); | ||
257 | r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56); | ||
258 | r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33); | ||
259 | r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11); | ||
260 | r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11); | ||
261 | r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02); | ||
262 | r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b); | ||
263 | r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40); | ||
264 | r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03); | ||
265 | r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04); | ||
266 | /* | ||
267 | * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement | ||
268 | * to avoid red / blue flicker | ||
269 | */ | ||
270 | r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04); | ||
271 | r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00); | ||
272 | |||
273 | r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11); | ||
274 | r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11); | ||
275 | r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11); | ||
276 | r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040); | ||
277 | r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0); | ||
278 | r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020); | ||
279 | r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0); | ||
280 | |||
281 | r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533); | ||
282 | r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00); | ||
283 | r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00); | ||
284 | r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00); | ||
285 | |||
286 | r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0); | ||
287 | r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02); | ||
288 | r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804); | ||
289 | |||
290 | r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01); | ||
291 | r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000); | ||
292 | |||
293 | r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e); | ||
294 | r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4); | ||
295 | r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e); | ||
296 | |||
297 | r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON); | ||
298 | |||
299 | dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; | ||
300 | |||
301 | transfer_err: | ||
302 | |||
303 | return r ? -EIO : 0; | ||
304 | } | ||
305 | |||
306 | static void td028ttec1_panel_disable(struct omap_dss_device *dssdev) | ||
307 | { | ||
308 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
309 | struct omap_dss_device *in = ddata->in; | ||
310 | |||
311 | if (!omapdss_device_is_enabled(dssdev)) | ||
312 | return; | ||
313 | |||
314 | dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n"); | ||
315 | |||
316 | jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF); | ||
317 | jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002); | ||
318 | jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN); | ||
319 | jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00); | ||
320 | |||
321 | in->ops.dpi->disable(in); | ||
322 | |||
323 | dssdev->state = OMAP_DSS_DISPLAY_DISABLED; | ||
324 | } | ||
325 | |||
326 | static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev, | ||
327 | struct omap_video_timings *timings) | ||
328 | { | ||
329 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
330 | struct omap_dss_device *in = ddata->in; | ||
331 | |||
332 | ddata->videomode = *timings; | ||
333 | dssdev->panel.timings = *timings; | ||
334 | |||
335 | in->ops.dpi->set_timings(in, timings); | ||
336 | } | ||
337 | |||
338 | static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev, | ||
339 | struct omap_video_timings *timings) | ||
340 | { | ||
341 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
342 | |||
343 | *timings = ddata->videomode; | ||
344 | } | ||
345 | |||
346 | static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev, | ||
347 | struct omap_video_timings *timings) | ||
348 | { | ||
349 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
350 | struct omap_dss_device *in = ddata->in; | ||
351 | |||
352 | return in->ops.dpi->check_timings(in, timings); | ||
353 | } | ||
354 | |||
355 | static struct omap_dss_driver td028ttec1_ops = { | ||
356 | .connect = td028ttec1_panel_connect, | ||
357 | .disconnect = td028ttec1_panel_disconnect, | ||
358 | |||
359 | .enable = td028ttec1_panel_enable, | ||
360 | .disable = td028ttec1_panel_disable, | ||
361 | |||
362 | .set_timings = td028ttec1_panel_set_timings, | ||
363 | .get_timings = td028ttec1_panel_get_timings, | ||
364 | .check_timings = td028ttec1_panel_check_timings, | ||
365 | }; | ||
366 | |||
367 | static int td028ttec1_panel_probe_pdata(struct spi_device *spi) | ||
368 | { | ||
369 | const struct panel_tpo_td028ttec1_platform_data *pdata; | ||
370 | struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); | ||
371 | struct omap_dss_device *dssdev, *in; | ||
372 | |||
373 | pdata = dev_get_platdata(&spi->dev); | ||
374 | |||
375 | in = omap_dss_find_output(pdata->source); | ||
376 | if (in == NULL) { | ||
377 | dev_err(&spi->dev, "failed to find video source '%s'\n", | ||
378 | pdata->source); | ||
379 | return -EPROBE_DEFER; | ||
380 | } | ||
381 | |||
382 | ddata->in = in; | ||
383 | |||
384 | ddata->data_lines = pdata->data_lines; | ||
385 | |||
386 | dssdev = &ddata->dssdev; | ||
387 | dssdev->name = pdata->name; | ||
388 | |||
389 | return 0; | ||
390 | } | ||
391 | |||
392 | static int td028ttec1_panel_probe(struct spi_device *spi) | ||
393 | { | ||
394 | struct panel_drv_data *ddata; | ||
395 | struct omap_dss_device *dssdev; | ||
396 | int r; | ||
397 | |||
398 | dev_dbg(&spi->dev, "%s\n", __func__); | ||
399 | |||
400 | spi->bits_per_word = 9; | ||
401 | spi->mode = SPI_MODE_3; | ||
402 | |||
403 | r = spi_setup(spi); | ||
404 | if (r < 0) { | ||
405 | dev_err(&spi->dev, "spi_setup failed: %d\n", r); | ||
406 | return r; | ||
407 | } | ||
408 | |||
409 | ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL); | ||
410 | if (ddata == NULL) | ||
411 | return -ENOMEM; | ||
412 | |||
413 | dev_set_drvdata(&spi->dev, ddata); | ||
414 | |||
415 | ddata->spi_dev = spi; | ||
416 | |||
417 | if (dev_get_platdata(&spi->dev)) { | ||
418 | r = td028ttec1_panel_probe_pdata(spi); | ||
419 | if (r) | ||
420 | return r; | ||
421 | } else { | ||
422 | return -ENODEV; | ||
423 | } | ||
424 | |||
425 | ddata->videomode = td028ttec1_panel_timings; | ||
426 | |||
427 | dssdev = &ddata->dssdev; | ||
428 | dssdev->dev = &spi->dev; | ||
429 | dssdev->driver = &td028ttec1_ops; | ||
430 | dssdev->type = OMAP_DISPLAY_TYPE_DPI; | ||
431 | dssdev->owner = THIS_MODULE; | ||
432 | dssdev->panel.timings = ddata->videomode; | ||
433 | dssdev->phy.dpi.data_lines = ddata->data_lines; | ||
434 | |||
435 | r = omapdss_register_display(dssdev); | ||
436 | if (r) { | ||
437 | dev_err(&spi->dev, "Failed to register panel\n"); | ||
438 | goto err_reg; | ||
439 | } | ||
440 | |||
441 | return 0; | ||
442 | |||
443 | err_reg: | ||
444 | omap_dss_put_device(ddata->in); | ||
445 | return r; | ||
446 | } | ||
447 | |||
448 | static int td028ttec1_panel_remove(struct spi_device *spi) | ||
449 | { | ||
450 | struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); | ||
451 | struct omap_dss_device *dssdev = &ddata->dssdev; | ||
452 | struct omap_dss_device *in = ddata->in; | ||
453 | |||
454 | dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__); | ||
455 | |||
456 | omapdss_unregister_display(dssdev); | ||
457 | |||
458 | td028ttec1_panel_disable(dssdev); | ||
459 | td028ttec1_panel_disconnect(dssdev); | ||
460 | |||
461 | omap_dss_put_device(in); | ||
462 | |||
463 | return 0; | ||
464 | } | ||
465 | |||
466 | static struct spi_driver td028ttec1_spi_driver = { | ||
467 | .probe = td028ttec1_panel_probe, | ||
468 | .remove = td028ttec1_panel_remove, | ||
469 | |||
470 | .driver = { | ||
471 | .name = "panel-tpo-td028ttec1", | ||
472 | .owner = THIS_MODULE, | ||
473 | }, | ||
474 | }; | ||
475 | |||
476 | module_spi_driver(td028ttec1_spi_driver); | ||
477 | |||
478 | MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>"); | ||
479 | MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver"); | ||
480 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile index 94832eb06a3d..d3aa91bdd6a8 100644 --- a/drivers/video/omap2/dss/Makefile +++ b/drivers/video/omap2/dss/Makefile | |||
@@ -10,5 +10,6 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o | |||
10 | omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o | 10 | omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o |
11 | omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o | 11 | omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o |
12 | omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o | 12 | omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o |
13 | omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o ti_hdmi_4xxx_ip.o | 13 | omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi_common.o hdmi_wp.o hdmi_pll.o \ |
14 | hdmi_phy.o hdmi4_core.o | ||
14 | ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG | 15 | ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG |
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index 60d3958d04f7..ffa45c894cd4 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c | |||
@@ -266,7 +266,7 @@ static int (*dss_output_drv_reg_funcs[])(void) __initdata = { | |||
266 | venc_init_platform_driver, | 266 | venc_init_platform_driver, |
267 | #endif | 267 | #endif |
268 | #ifdef CONFIG_OMAP4_DSS_HDMI | 268 | #ifdef CONFIG_OMAP4_DSS_HDMI |
269 | hdmi_init_platform_driver, | 269 | hdmi4_init_platform_driver, |
270 | #endif | 270 | #endif |
271 | }; | 271 | }; |
272 | 272 | ||
@@ -287,7 +287,7 @@ static void (*dss_output_drv_unreg_funcs[])(void) __exitdata = { | |||
287 | venc_uninit_platform_driver, | 287 | venc_uninit_platform_driver, |
288 | #endif | 288 | #endif |
289 | #ifdef CONFIG_OMAP4_DSS_HDMI | 289 | #ifdef CONFIG_OMAP4_DSS_HDMI |
290 | hdmi_uninit_platform_driver, | 290 | hdmi4_uninit_platform_driver, |
291 | #endif | 291 | #endif |
292 | }; | 292 | }; |
293 | 293 | ||
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 477975009eee..4ec59ca72e5d 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c | |||
@@ -2352,7 +2352,7 @@ int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, | |||
2352 | { | 2352 | { |
2353 | enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); | 2353 | enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); |
2354 | bool five_taps = true; | 2354 | bool five_taps = true; |
2355 | bool fieldmode = 0; | 2355 | bool fieldmode = false; |
2356 | u16 in_height = oi->height; | 2356 | u16 in_height = oi->height; |
2357 | u16 in_width = oi->width; | 2357 | u16 in_width = oi->width; |
2358 | bool ilace = timings->interlace; | 2358 | bool ilace = timings->interlace; |
@@ -2365,7 +2365,7 @@ int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, | |||
2365 | out_height = oi->out_height == 0 ? oi->height : oi->out_height; | 2365 | out_height = oi->out_height == 0 ? oi->height : oi->out_height; |
2366 | 2366 | ||
2367 | if (ilace && oi->height == out_height) | 2367 | if (ilace && oi->height == out_height) |
2368 | fieldmode = 1; | 2368 | fieldmode = true; |
2369 | 2369 | ||
2370 | if (ilace) { | 2370 | if (ilace) { |
2371 | if (fieldmode) | 2371 | if (fieldmode) |
@@ -2396,7 +2396,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane, | |||
2396 | bool mem_to_mem) | 2396 | bool mem_to_mem) |
2397 | { | 2397 | { |
2398 | bool five_taps = true; | 2398 | bool five_taps = true; |
2399 | bool fieldmode = 0; | 2399 | bool fieldmode = false; |
2400 | int r, cconv = 0; | 2400 | int r, cconv = 0; |
2401 | unsigned offset0, offset1; | 2401 | unsigned offset0, offset1; |
2402 | s32 row_inc; | 2402 | s32 row_inc; |
@@ -2417,7 +2417,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane, | |||
2417 | out_height = out_height == 0 ? height : out_height; | 2417 | out_height = out_height == 0 ? height : out_height; |
2418 | 2418 | ||
2419 | if (ilace && height == out_height) | 2419 | if (ilace && height == out_height) |
2420 | fieldmode = 1; | 2420 | fieldmode = true; |
2421 | 2421 | ||
2422 | if (ilace) { | 2422 | if (ilace) { |
2423 | if (fieldmode) | 2423 | if (fieldmode) |
@@ -2918,7 +2918,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, | |||
2918 | break; | 2918 | break; |
2919 | default: | 2919 | default: |
2920 | BUG(); | 2920 | BUG(); |
2921 | }; | 2921 | } |
2922 | 2922 | ||
2923 | l = dispc_read_reg(DISPC_POL_FREQ(channel)); | 2923 | l = dispc_read_reg(DISPC_POL_FREQ(channel)); |
2924 | l |= FLD_VAL(onoff, 17, 17); | 2924 | l |= FLD_VAL(onoff, 17, 17); |
diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c index fafe7c941a60..669a81fdf58e 100644 --- a/drivers/video/omap2/dss/display.c +++ b/drivers/video/omap2/dss/display.c | |||
@@ -266,7 +266,7 @@ void videomode_to_omap_video_timings(const struct videomode *vm, | |||
266 | OMAPDSS_SIG_ACTIVE_LOW; | 266 | OMAPDSS_SIG_ACTIVE_LOW; |
267 | ovt->de_level = vm->flags & DISPLAY_FLAGS_DE_HIGH ? | 267 | ovt->de_level = vm->flags & DISPLAY_FLAGS_DE_HIGH ? |
268 | OMAPDSS_SIG_ACTIVE_HIGH : | 268 | OMAPDSS_SIG_ACTIVE_HIGH : |
269 | OMAPDSS_SIG_ACTIVE_HIGH; | 269 | OMAPDSS_SIG_ACTIVE_LOW; |
270 | ovt->data_pclk_edge = vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE ? | 270 | ovt->data_pclk_edge = vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE ? |
271 | OMAPDSS_DRIVE_SIG_RISING_EDGE : | 271 | OMAPDSS_DRIVE_SIG_RISING_EDGE : |
272 | OMAPDSS_DRIVE_SIG_FALLING_EDGE; | 272 | OMAPDSS_DRIVE_SIG_FALLING_EDGE; |
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index a598b5812285..6056b27cf73c 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c | |||
@@ -312,7 +312,7 @@ struct dsi_data { | |||
312 | struct dsi_isr_tables isr_tables_copy; | 312 | struct dsi_isr_tables isr_tables_copy; |
313 | 313 | ||
314 | int update_channel; | 314 | int update_channel; |
315 | #ifdef DEBUG | 315 | #ifdef DSI_PERF_MEASURE |
316 | unsigned update_bytes; | 316 | unsigned update_bytes; |
317 | #endif | 317 | #endif |
318 | 318 | ||
@@ -334,7 +334,7 @@ struct dsi_data { | |||
334 | 334 | ||
335 | u32 errors; | 335 | u32 errors; |
336 | spinlock_t errors_lock; | 336 | spinlock_t errors_lock; |
337 | #ifdef DEBUG | 337 | #ifdef DSI_PERF_MEASURE |
338 | ktime_t perf_setup_time; | 338 | ktime_t perf_setup_time; |
339 | ktime_t perf_start_time; | 339 | ktime_t perf_start_time; |
340 | #endif | 340 | #endif |
@@ -373,7 +373,7 @@ struct dsi_packet_sent_handler_data { | |||
373 | struct completion *completion; | 373 | struct completion *completion; |
374 | }; | 374 | }; |
375 | 375 | ||
376 | #ifdef DEBUG | 376 | #ifdef DSI_PERF_MEASURE |
377 | static bool dsi_perf; | 377 | static bool dsi_perf; |
378 | module_param(dsi_perf, bool, 0644); | 378 | module_param(dsi_perf, bool, 0644); |
379 | #endif | 379 | #endif |
@@ -497,7 +497,7 @@ u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) | |||
497 | } | 497 | } |
498 | } | 498 | } |
499 | 499 | ||
500 | #ifdef DEBUG | 500 | #ifdef DSI_PERF_MEASURE |
501 | static void dsi_perf_mark_setup(struct platform_device *dsidev) | 501 | static void dsi_perf_mark_setup(struct platform_device *dsidev) |
502 | { | 502 | { |
503 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | 503 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
@@ -4066,7 +4066,7 @@ static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) | |||
4066 | default: | 4066 | default: |
4067 | r = -EINVAL; | 4067 | r = -EINVAL; |
4068 | goto err_pix_fmt; | 4068 | goto err_pix_fmt; |
4069 | }; | 4069 | } |
4070 | 4070 | ||
4071 | dsi_if_enable(dsidev, false); | 4071 | dsi_if_enable(dsidev, false); |
4072 | dsi_vc_enable(dsidev, channel, false); | 4072 | dsi_vc_enable(dsidev, channel, false); |
@@ -4277,7 +4277,7 @@ static int dsi_update(struct omap_dss_device *dssdev, int channel, | |||
4277 | dw = dsi->timings.x_res; | 4277 | dw = dsi->timings.x_res; |
4278 | dh = dsi->timings.y_res; | 4278 | dh = dsi->timings.y_res; |
4279 | 4279 | ||
4280 | #ifdef DEBUG | 4280 | #ifdef DSI_PERF_MEASURE |
4281 | dsi->update_bytes = dw * dh * | 4281 | dsi->update_bytes = dw * dh * |
4282 | dsi_get_pixel_size(dsi->pix_fmt) / 8; | 4282 | dsi_get_pixel_size(dsi->pix_fmt) / 8; |
4283 | #endif | 4283 | #endif |
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index e172531d196b..f538e867c0f8 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h | |||
@@ -427,8 +427,8 @@ int venc_init_platform_driver(void) __init; | |||
427 | void venc_uninit_platform_driver(void) __exit; | 427 | void venc_uninit_platform_driver(void) __exit; |
428 | 428 | ||
429 | /* HDMI */ | 429 | /* HDMI */ |
430 | int hdmi_init_platform_driver(void) __init; | 430 | int hdmi4_init_platform_driver(void) __init; |
431 | void hdmi_uninit_platform_driver(void) __exit; | 431 | void hdmi4_uninit_platform_driver(void) __exit; |
432 | 432 | ||
433 | /* RFBI */ | 433 | /* RFBI */ |
434 | int rfbi_init_platform_driver(void) __init; | 434 | int rfbi_init_platform_driver(void) __init; |
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index b9cfebb378a2..f8fd6dbacabc 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c | |||
@@ -789,50 +789,6 @@ static const struct omap_dss_features omap5_dss_features = { | |||
789 | .burst_size_unit = 16, | 789 | .burst_size_unit = 16, |
790 | }; | 790 | }; |
791 | 791 | ||
792 | #if defined(CONFIG_OMAP4_DSS_HDMI) | ||
793 | /* HDMI OMAP4 Functions*/ | ||
794 | static const struct ti_hdmi_ip_ops omap4_hdmi_functions = { | ||
795 | |||
796 | .video_configure = ti_hdmi_4xxx_basic_configure, | ||
797 | .phy_enable = ti_hdmi_4xxx_phy_enable, | ||
798 | .phy_disable = ti_hdmi_4xxx_phy_disable, | ||
799 | .read_edid = ti_hdmi_4xxx_read_edid, | ||
800 | .pll_enable = ti_hdmi_4xxx_pll_enable, | ||
801 | .pll_disable = ti_hdmi_4xxx_pll_disable, | ||
802 | .video_enable = ti_hdmi_4xxx_wp_video_start, | ||
803 | .video_disable = ti_hdmi_4xxx_wp_video_stop, | ||
804 | .dump_wrapper = ti_hdmi_4xxx_wp_dump, | ||
805 | .dump_core = ti_hdmi_4xxx_core_dump, | ||
806 | .dump_pll = ti_hdmi_4xxx_pll_dump, | ||
807 | .dump_phy = ti_hdmi_4xxx_phy_dump, | ||
808 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
809 | .audio_enable = ti_hdmi_4xxx_wp_audio_enable, | ||
810 | .audio_disable = ti_hdmi_4xxx_wp_audio_disable, | ||
811 | .audio_start = ti_hdmi_4xxx_audio_start, | ||
812 | .audio_stop = ti_hdmi_4xxx_audio_stop, | ||
813 | .audio_config = ti_hdmi_4xxx_audio_config, | ||
814 | .audio_get_dma_port = ti_hdmi_4xxx_audio_get_dma_port, | ||
815 | #endif | ||
816 | |||
817 | }; | ||
818 | |||
819 | void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data, | ||
820 | enum omapdss_version version) | ||
821 | { | ||
822 | switch (version) { | ||
823 | case OMAPDSS_VER_OMAP4430_ES1: | ||
824 | case OMAPDSS_VER_OMAP4430_ES2: | ||
825 | case OMAPDSS_VER_OMAP4: | ||
826 | ip_data->ops = &omap4_hdmi_functions; | ||
827 | break; | ||
828 | default: | ||
829 | ip_data->ops = NULL; | ||
830 | } | ||
831 | |||
832 | WARN_ON(ip_data->ops == NULL); | ||
833 | } | ||
834 | #endif | ||
835 | |||
836 | /* Functions returning values related to a DSS feature */ | 792 | /* Functions returning values related to a DSS feature */ |
837 | int dss_feat_get_num_mgrs(void) | 793 | int dss_feat_get_num_mgrs(void) |
838 | { | 794 | { |
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 489b9bec4a6d..10b0556e1352 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h | |||
@@ -20,10 +20,6 @@ | |||
20 | #ifndef __OMAP2_DSS_FEATURES_H | 20 | #ifndef __OMAP2_DSS_FEATURES_H |
21 | #define __OMAP2_DSS_FEATURES_H | 21 | #define __OMAP2_DSS_FEATURES_H |
22 | 22 | ||
23 | #if defined(CONFIG_OMAP4_DSS_HDMI) | ||
24 | #include "ti_hdmi.h" | ||
25 | #endif | ||
26 | |||
27 | #define MAX_DSS_MANAGERS 4 | 23 | #define MAX_DSS_MANAGERS 4 |
28 | #define MAX_DSS_OVERLAYS 4 | 24 | #define MAX_DSS_OVERLAYS 4 |
29 | #define MAX_DSS_LCD_MANAGERS 3 | 25 | #define MAX_DSS_LCD_MANAGERS 3 |
@@ -117,8 +113,4 @@ bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type); | |||
117 | bool dss_has_feature(enum dss_feat_id id); | 113 | bool dss_has_feature(enum dss_feat_id id); |
118 | void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); | 114 | void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); |
119 | void dss_features_init(enum omapdss_version version); | 115 | void dss_features_init(enum omapdss_version version); |
120 | #if defined(CONFIG_OMAP4_DSS_HDMI) | ||
121 | void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data, | ||
122 | enum omapdss_version version); | ||
123 | #endif | ||
124 | #endif | 116 | #endif |
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c deleted file mode 100644 index 82a964074993..000000000000 --- a/drivers/video/omap2/dss/hdmi.c +++ /dev/null | |||
@@ -1,1184 +0,0 @@ | |||
1 | /* | ||
2 | * hdmi.c | ||
3 | * | ||
4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. | ||
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | ||
6 | * Authors: Yong Zhi | ||
7 | * Mythri pk <mythripk@ti.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License version 2 as published by | ||
11 | * the Free Software Foundation. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
16 | * more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along with | ||
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
20 | */ | ||
21 | |||
22 | #define DSS_SUBSYS_NAME "HDMI" | ||
23 | |||
24 | #include <linux/kernel.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/err.h> | ||
27 | #include <linux/io.h> | ||
28 | #include <linux/interrupt.h> | ||
29 | #include <linux/mutex.h> | ||
30 | #include <linux/delay.h> | ||
31 | #include <linux/string.h> | ||
32 | #include <linux/platform_device.h> | ||
33 | #include <linux/pm_runtime.h> | ||
34 | #include <linux/clk.h> | ||
35 | #include <linux/gpio.h> | ||
36 | #include <linux/regulator/consumer.h> | ||
37 | #include <video/omapdss.h> | ||
38 | |||
39 | #include "ti_hdmi.h" | ||
40 | #include "dss.h" | ||
41 | #include "dss_features.h" | ||
42 | |||
43 | #define HDMI_WP 0x0 | ||
44 | #define HDMI_CORE_SYS 0x400 | ||
45 | #define HDMI_CORE_AV 0x900 | ||
46 | #define HDMI_PLLCTRL 0x200 | ||
47 | #define HDMI_PHY 0x300 | ||
48 | |||
49 | /* HDMI EDID Length move this */ | ||
50 | #define HDMI_EDID_MAX_LENGTH 256 | ||
51 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 | ||
52 | #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 | ||
53 | #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 | ||
54 | #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 | ||
55 | #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 | ||
56 | |||
57 | #define HDMI_DEFAULT_REGN 16 | ||
58 | #define HDMI_DEFAULT_REGM2 1 | ||
59 | |||
60 | static struct { | ||
61 | struct mutex lock; | ||
62 | struct platform_device *pdev; | ||
63 | |||
64 | struct hdmi_ip_data ip_data; | ||
65 | |||
66 | struct clk *sys_clk; | ||
67 | struct regulator *vdda_hdmi_dac_reg; | ||
68 | |||
69 | bool core_enabled; | ||
70 | |||
71 | struct omap_dss_device output; | ||
72 | } hdmi; | ||
73 | |||
74 | /* | ||
75 | * Logic for the below structure : | ||
76 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. | ||
77 | * There is a correspondence between CEA/VESA timing and code, please | ||
78 | * refer to section 6.3 in HDMI 1.3 specification for timing code. | ||
79 | * | ||
80 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 | ||
81 | * supported CEA and VESA timing values.code_cea corresponds to the CEA | ||
82 | * code, It is used to get the timing from cea_vesa_timing array.Similarly | ||
83 | * with code_vesa. Code_index is used for back mapping, that is once EDID | ||
84 | * is read from the TV, EDID is parsed to find the timing values and then | ||
85 | * map it to corresponding CEA or VESA index. | ||
86 | */ | ||
87 | |||
88 | static const struct hdmi_config cea_timings[] = { | ||
89 | { | ||
90 | { 640, 480, 25200, 96, 16, 48, 2, 10, 33, | ||
91 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
92 | false, }, | ||
93 | { 1, HDMI_HDMI }, | ||
94 | }, | ||
95 | { | ||
96 | { 720, 480, 27027, 62, 16, 60, 6, 9, 30, | ||
97 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
98 | false, }, | ||
99 | { 2, HDMI_HDMI }, | ||
100 | }, | ||
101 | { | ||
102 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | ||
103 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
104 | false, }, | ||
105 | { 4, HDMI_HDMI }, | ||
106 | }, | ||
107 | { | ||
108 | { 1920, 540, 74250, 44, 88, 148, 5, 2, 15, | ||
109 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
110 | true, }, | ||
111 | { 5, HDMI_HDMI }, | ||
112 | }, | ||
113 | { | ||
114 | { 1440, 240, 27027, 124, 38, 114, 3, 4, 15, | ||
115 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
116 | true, }, | ||
117 | { 6, HDMI_HDMI }, | ||
118 | }, | ||
119 | { | ||
120 | { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36, | ||
121 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
122 | false, }, | ||
123 | { 16, HDMI_HDMI }, | ||
124 | }, | ||
125 | { | ||
126 | { 720, 576, 27000, 64, 12, 68, 5, 5, 39, | ||
127 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
128 | false, }, | ||
129 | { 17, HDMI_HDMI }, | ||
130 | }, | ||
131 | { | ||
132 | { 1280, 720, 74250, 40, 440, 220, 5, 5, 20, | ||
133 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
134 | false, }, | ||
135 | { 19, HDMI_HDMI }, | ||
136 | }, | ||
137 | { | ||
138 | { 1920, 540, 74250, 44, 528, 148, 5, 2, 15, | ||
139 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
140 | true, }, | ||
141 | { 20, HDMI_HDMI }, | ||
142 | }, | ||
143 | { | ||
144 | { 1440, 288, 27000, 126, 24, 138, 3, 2, 19, | ||
145 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
146 | true, }, | ||
147 | { 21, HDMI_HDMI }, | ||
148 | }, | ||
149 | { | ||
150 | { 1440, 576, 54000, 128, 24, 136, 5, 5, 39, | ||
151 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
152 | false, }, | ||
153 | { 29, HDMI_HDMI }, | ||
154 | }, | ||
155 | { | ||
156 | { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36, | ||
157 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
158 | false, }, | ||
159 | { 31, HDMI_HDMI }, | ||
160 | }, | ||
161 | { | ||
162 | { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36, | ||
163 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
164 | false, }, | ||
165 | { 32, HDMI_HDMI }, | ||
166 | }, | ||
167 | { | ||
168 | { 2880, 480, 108108, 248, 64, 240, 6, 9, 30, | ||
169 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
170 | false, }, | ||
171 | { 35, HDMI_HDMI }, | ||
172 | }, | ||
173 | { | ||
174 | { 2880, 576, 108000, 256, 48, 272, 5, 5, 39, | ||
175 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
176 | false, }, | ||
177 | { 37, HDMI_HDMI }, | ||
178 | }, | ||
179 | }; | ||
180 | |||
181 | static const struct hdmi_config vesa_timings[] = { | ||
182 | /* VESA From Here */ | ||
183 | { | ||
184 | { 640, 480, 25175, 96, 16, 48, 2, 11, 31, | ||
185 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
186 | false, }, | ||
187 | { 4, HDMI_DVI }, | ||
188 | }, | ||
189 | { | ||
190 | { 800, 600, 40000, 128, 40, 88, 4, 1, 23, | ||
191 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
192 | false, }, | ||
193 | { 9, HDMI_DVI }, | ||
194 | }, | ||
195 | { | ||
196 | { 848, 480, 33750, 112, 16, 112, 8, 6, 23, | ||
197 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
198 | false, }, | ||
199 | { 0xE, HDMI_DVI }, | ||
200 | }, | ||
201 | { | ||
202 | { 1280, 768, 79500, 128, 64, 192, 7, 3, 20, | ||
203 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
204 | false, }, | ||
205 | { 0x17, HDMI_DVI }, | ||
206 | }, | ||
207 | { | ||
208 | { 1280, 800, 83500, 128, 72, 200, 6, 3, 22, | ||
209 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
210 | false, }, | ||
211 | { 0x1C, HDMI_DVI }, | ||
212 | }, | ||
213 | { | ||
214 | { 1360, 768, 85500, 112, 64, 256, 6, 3, 18, | ||
215 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
216 | false, }, | ||
217 | { 0x27, HDMI_DVI }, | ||
218 | }, | ||
219 | { | ||
220 | { 1280, 960, 108000, 112, 96, 312, 3, 1, 36, | ||
221 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
222 | false, }, | ||
223 | { 0x20, HDMI_DVI }, | ||
224 | }, | ||
225 | { | ||
226 | { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38, | ||
227 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
228 | false, }, | ||
229 | { 0x23, HDMI_DVI }, | ||
230 | }, | ||
231 | { | ||
232 | { 1024, 768, 65000, 136, 24, 160, 6, 3, 29, | ||
233 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
234 | false, }, | ||
235 | { 0x10, HDMI_DVI }, | ||
236 | }, | ||
237 | { | ||
238 | { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32, | ||
239 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
240 | false, }, | ||
241 | { 0x2A, HDMI_DVI }, | ||
242 | }, | ||
243 | { | ||
244 | { 1440, 900, 106500, 152, 80, 232, 6, 3, 25, | ||
245 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
246 | false, }, | ||
247 | { 0x2F, HDMI_DVI }, | ||
248 | }, | ||
249 | { | ||
250 | { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, | ||
251 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
252 | false, }, | ||
253 | { 0x3A, HDMI_DVI }, | ||
254 | }, | ||
255 | { | ||
256 | { 1366, 768, 85500, 143, 70, 213, 3, 3, 24, | ||
257 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
258 | false, }, | ||
259 | { 0x51, HDMI_DVI }, | ||
260 | }, | ||
261 | { | ||
262 | { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36, | ||
263 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
264 | false, }, | ||
265 | { 0x52, HDMI_DVI }, | ||
266 | }, | ||
267 | { | ||
268 | { 1280, 768, 68250, 32, 48, 80, 7, 3, 12, | ||
269 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
270 | false, }, | ||
271 | { 0x16, HDMI_DVI }, | ||
272 | }, | ||
273 | { | ||
274 | { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23, | ||
275 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
276 | false, }, | ||
277 | { 0x29, HDMI_DVI }, | ||
278 | }, | ||
279 | { | ||
280 | { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21, | ||
281 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
282 | false, }, | ||
283 | { 0x39, HDMI_DVI }, | ||
284 | }, | ||
285 | { | ||
286 | { 1280, 800, 79500, 32, 48, 80, 6, 3, 14, | ||
287 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
288 | false, }, | ||
289 | { 0x1B, HDMI_DVI }, | ||
290 | }, | ||
291 | { | ||
292 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | ||
293 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
294 | false, }, | ||
295 | { 0x55, HDMI_DVI }, | ||
296 | }, | ||
297 | { | ||
298 | { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26, | ||
299 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
300 | false, }, | ||
301 | { 0x44, HDMI_DVI }, | ||
302 | }, | ||
303 | }; | ||
304 | |||
305 | static int hdmi_runtime_get(void) | ||
306 | { | ||
307 | int r; | ||
308 | |||
309 | DSSDBG("hdmi_runtime_get\n"); | ||
310 | |||
311 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | ||
312 | WARN_ON(r < 0); | ||
313 | if (r < 0) | ||
314 | return r; | ||
315 | |||
316 | return 0; | ||
317 | } | ||
318 | |||
319 | static void hdmi_runtime_put(void) | ||
320 | { | ||
321 | int r; | ||
322 | |||
323 | DSSDBG("hdmi_runtime_put\n"); | ||
324 | |||
325 | r = pm_runtime_put_sync(&hdmi.pdev->dev); | ||
326 | WARN_ON(r < 0 && r != -ENOSYS); | ||
327 | } | ||
328 | |||
329 | static int hdmi_init_regulator(void) | ||
330 | { | ||
331 | struct regulator *reg; | ||
332 | |||
333 | if (hdmi.vdda_hdmi_dac_reg != NULL) | ||
334 | return 0; | ||
335 | |||
336 | reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac"); | ||
337 | |||
338 | /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */ | ||
339 | if (IS_ERR(reg)) | ||
340 | reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC"); | ||
341 | |||
342 | if (IS_ERR(reg)) { | ||
343 | DSSERR("can't get VDDA_HDMI_DAC regulator\n"); | ||
344 | return PTR_ERR(reg); | ||
345 | } | ||
346 | |||
347 | hdmi.vdda_hdmi_dac_reg = reg; | ||
348 | |||
349 | return 0; | ||
350 | } | ||
351 | |||
352 | static const struct hdmi_config *hdmi_find_timing( | ||
353 | const struct hdmi_config *timings_arr, | ||
354 | int len) | ||
355 | { | ||
356 | int i; | ||
357 | |||
358 | for (i = 0; i < len; i++) { | ||
359 | if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code) | ||
360 | return &timings_arr[i]; | ||
361 | } | ||
362 | return NULL; | ||
363 | } | ||
364 | |||
365 | static const struct hdmi_config *hdmi_get_timings(void) | ||
366 | { | ||
367 | const struct hdmi_config *arr; | ||
368 | int len; | ||
369 | |||
370 | if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) { | ||
371 | arr = vesa_timings; | ||
372 | len = ARRAY_SIZE(vesa_timings); | ||
373 | } else { | ||
374 | arr = cea_timings; | ||
375 | len = ARRAY_SIZE(cea_timings); | ||
376 | } | ||
377 | |||
378 | return hdmi_find_timing(arr, len); | ||
379 | } | ||
380 | |||
381 | static bool hdmi_timings_compare(struct omap_video_timings *timing1, | ||
382 | const struct omap_video_timings *timing2) | ||
383 | { | ||
384 | int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; | ||
385 | |||
386 | if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) == | ||
387 | DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) && | ||
388 | (timing2->x_res == timing1->x_res) && | ||
389 | (timing2->y_res == timing1->y_res)) { | ||
390 | |||
391 | timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp; | ||
392 | timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp; | ||
393 | timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | ||
394 | timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | ||
395 | |||
396 | DSSDBG("timing1_hsync = %d timing1_vsync = %d"\ | ||
397 | "timing2_hsync = %d timing2_vsync = %d\n", | ||
398 | timing1_hsync, timing1_vsync, | ||
399 | timing2_hsync, timing2_vsync); | ||
400 | |||
401 | if ((timing1_hsync == timing2_hsync) && | ||
402 | (timing1_vsync == timing2_vsync)) { | ||
403 | return true; | ||
404 | } | ||
405 | } | ||
406 | return false; | ||
407 | } | ||
408 | |||
409 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | ||
410 | { | ||
411 | int i; | ||
412 | struct hdmi_cm cm = {-1}; | ||
413 | DSSDBG("hdmi_get_code\n"); | ||
414 | |||
415 | for (i = 0; i < ARRAY_SIZE(cea_timings); i++) { | ||
416 | if (hdmi_timings_compare(timing, &cea_timings[i].timings)) { | ||
417 | cm = cea_timings[i].cm; | ||
418 | goto end; | ||
419 | } | ||
420 | } | ||
421 | for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) { | ||
422 | if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) { | ||
423 | cm = vesa_timings[i].cm; | ||
424 | goto end; | ||
425 | } | ||
426 | } | ||
427 | |||
428 | end: return cm; | ||
429 | |||
430 | } | ||
431 | |||
432 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, | ||
433 | struct hdmi_pll_info *pi) | ||
434 | { | ||
435 | unsigned long clkin, refclk; | ||
436 | u32 mf; | ||
437 | |||
438 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; | ||
439 | /* | ||
440 | * Input clock is predivided by N + 1 | ||
441 | * out put of which is reference clk | ||
442 | */ | ||
443 | |||
444 | pi->regn = HDMI_DEFAULT_REGN; | ||
445 | |||
446 | refclk = clkin / pi->regn; | ||
447 | |||
448 | pi->regm2 = HDMI_DEFAULT_REGM2; | ||
449 | |||
450 | /* | ||
451 | * multiplier is pixel_clk/ref_clk | ||
452 | * Multiplying by 100 to avoid fractional part removal | ||
453 | */ | ||
454 | pi->regm = phy * pi->regm2 / refclk; | ||
455 | |||
456 | /* | ||
457 | * fractional multiplier is remainder of the difference between | ||
458 | * multiplier and actual phy(required pixel clock thus should be | ||
459 | * multiplied by 2^18(262144) divided by the reference clock | ||
460 | */ | ||
461 | mf = (phy - pi->regm / pi->regm2 * refclk) * 262144; | ||
462 | pi->regmf = pi->regm2 * mf / refclk; | ||
463 | |||
464 | /* | ||
465 | * Dcofreq should be set to 1 if required pixel clock | ||
466 | * is greater than 1000MHz | ||
467 | */ | ||
468 | pi->dcofreq = phy > 1000 * 100; | ||
469 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; | ||
470 | |||
471 | /* Set the reference clock to sysclk reference */ | ||
472 | pi->refsel = HDMI_REFSEL_SYSCLK; | ||
473 | |||
474 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); | ||
475 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | ||
476 | } | ||
477 | |||
478 | static int hdmi_power_on_core(struct omap_dss_device *dssdev) | ||
479 | { | ||
480 | int r; | ||
481 | |||
482 | r = regulator_enable(hdmi.vdda_hdmi_dac_reg); | ||
483 | if (r) | ||
484 | return r; | ||
485 | |||
486 | r = hdmi_runtime_get(); | ||
487 | if (r) | ||
488 | goto err_runtime_get; | ||
489 | |||
490 | /* Make selection of HDMI in DSS */ | ||
491 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | ||
492 | |||
493 | hdmi.core_enabled = true; | ||
494 | |||
495 | return 0; | ||
496 | |||
497 | err_runtime_get: | ||
498 | regulator_disable(hdmi.vdda_hdmi_dac_reg); | ||
499 | |||
500 | return r; | ||
501 | } | ||
502 | |||
503 | static void hdmi_power_off_core(struct omap_dss_device *dssdev) | ||
504 | { | ||
505 | hdmi.core_enabled = false; | ||
506 | |||
507 | hdmi_runtime_put(); | ||
508 | regulator_disable(hdmi.vdda_hdmi_dac_reg); | ||
509 | } | ||
510 | |||
511 | static int hdmi_power_on_full(struct omap_dss_device *dssdev) | ||
512 | { | ||
513 | int r; | ||
514 | struct omap_video_timings *p; | ||
515 | struct omap_overlay_manager *mgr = hdmi.output.manager; | ||
516 | unsigned long phy; | ||
517 | |||
518 | r = hdmi_power_on_core(dssdev); | ||
519 | if (r) | ||
520 | return r; | ||
521 | |||
522 | dss_mgr_disable(mgr); | ||
523 | |||
524 | p = &hdmi.ip_data.cfg.timings; | ||
525 | |||
526 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); | ||
527 | |||
528 | phy = p->pixel_clock; | ||
529 | |||
530 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); | ||
531 | |||
532 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); | ||
533 | |||
534 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ | ||
535 | r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); | ||
536 | if (r) { | ||
537 | DSSDBG("Failed to lock PLL\n"); | ||
538 | goto err_pll_enable; | ||
539 | } | ||
540 | |||
541 | r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data); | ||
542 | if (r) { | ||
543 | DSSDBG("Failed to start PHY\n"); | ||
544 | goto err_phy_enable; | ||
545 | } | ||
546 | |||
547 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); | ||
548 | |||
549 | /* bypass TV gamma table */ | ||
550 | dispc_enable_gamma_table(0); | ||
551 | |||
552 | /* tv size */ | ||
553 | dss_mgr_set_timings(mgr, p); | ||
554 | |||
555 | r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data); | ||
556 | if (r) | ||
557 | goto err_vid_enable; | ||
558 | |||
559 | r = dss_mgr_enable(mgr); | ||
560 | if (r) | ||
561 | goto err_mgr_enable; | ||
562 | |||
563 | return 0; | ||
564 | |||
565 | err_mgr_enable: | ||
566 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); | ||
567 | err_vid_enable: | ||
568 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); | ||
569 | err_phy_enable: | ||
570 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); | ||
571 | err_pll_enable: | ||
572 | hdmi_power_off_core(dssdev); | ||
573 | return -EIO; | ||
574 | } | ||
575 | |||
576 | static void hdmi_power_off_full(struct omap_dss_device *dssdev) | ||
577 | { | ||
578 | struct omap_overlay_manager *mgr = hdmi.output.manager; | ||
579 | |||
580 | dss_mgr_disable(mgr); | ||
581 | |||
582 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); | ||
583 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); | ||
584 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); | ||
585 | |||
586 | hdmi_power_off_core(dssdev); | ||
587 | } | ||
588 | |||
589 | static int hdmi_display_check_timing(struct omap_dss_device *dssdev, | ||
590 | struct omap_video_timings *timings) | ||
591 | { | ||
592 | struct hdmi_cm cm; | ||
593 | |||
594 | cm = hdmi_get_code(timings); | ||
595 | if (cm.code == -1) { | ||
596 | return -EINVAL; | ||
597 | } | ||
598 | |||
599 | return 0; | ||
600 | |||
601 | } | ||
602 | |||
603 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | ||
604 | struct omap_video_timings *timings) | ||
605 | { | ||
606 | struct hdmi_cm cm; | ||
607 | const struct hdmi_config *t; | ||
608 | |||
609 | mutex_lock(&hdmi.lock); | ||
610 | |||
611 | cm = hdmi_get_code(timings); | ||
612 | hdmi.ip_data.cfg.cm = cm; | ||
613 | |||
614 | t = hdmi_get_timings(); | ||
615 | if (t != NULL) { | ||
616 | hdmi.ip_data.cfg = *t; | ||
617 | |||
618 | dispc_set_tv_pclk(t->timings.pixel_clock * 1000); | ||
619 | } | ||
620 | |||
621 | mutex_unlock(&hdmi.lock); | ||
622 | } | ||
623 | |||
624 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, | ||
625 | struct omap_video_timings *timings) | ||
626 | { | ||
627 | const struct hdmi_config *cfg; | ||
628 | |||
629 | cfg = hdmi_get_timings(); | ||
630 | if (cfg == NULL) | ||
631 | cfg = &vesa_timings[0]; | ||
632 | |||
633 | memcpy(timings, &cfg->timings, sizeof(cfg->timings)); | ||
634 | } | ||
635 | |||
636 | static void hdmi_dump_regs(struct seq_file *s) | ||
637 | { | ||
638 | mutex_lock(&hdmi.lock); | ||
639 | |||
640 | if (hdmi_runtime_get()) { | ||
641 | mutex_unlock(&hdmi.lock); | ||
642 | return; | ||
643 | } | ||
644 | |||
645 | hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s); | ||
646 | hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); | ||
647 | hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); | ||
648 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); | ||
649 | |||
650 | hdmi_runtime_put(); | ||
651 | mutex_unlock(&hdmi.lock); | ||
652 | } | ||
653 | |||
654 | static int read_edid(u8 *buf, int len) | ||
655 | { | ||
656 | int r; | ||
657 | |||
658 | mutex_lock(&hdmi.lock); | ||
659 | |||
660 | r = hdmi_runtime_get(); | ||
661 | BUG_ON(r); | ||
662 | |||
663 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); | ||
664 | |||
665 | hdmi_runtime_put(); | ||
666 | mutex_unlock(&hdmi.lock); | ||
667 | |||
668 | return r; | ||
669 | } | ||
670 | |||
671 | static int hdmi_display_enable(struct omap_dss_device *dssdev) | ||
672 | { | ||
673 | struct omap_dss_device *out = &hdmi.output; | ||
674 | int r = 0; | ||
675 | |||
676 | DSSDBG("ENTER hdmi_display_enable\n"); | ||
677 | |||
678 | mutex_lock(&hdmi.lock); | ||
679 | |||
680 | if (out == NULL || out->manager == NULL) { | ||
681 | DSSERR("failed to enable display: no output/manager\n"); | ||
682 | r = -ENODEV; | ||
683 | goto err0; | ||
684 | } | ||
685 | |||
686 | r = hdmi_power_on_full(dssdev); | ||
687 | if (r) { | ||
688 | DSSERR("failed to power on device\n"); | ||
689 | goto err0; | ||
690 | } | ||
691 | |||
692 | mutex_unlock(&hdmi.lock); | ||
693 | return 0; | ||
694 | |||
695 | err0: | ||
696 | mutex_unlock(&hdmi.lock); | ||
697 | return r; | ||
698 | } | ||
699 | |||
700 | static void hdmi_display_disable(struct omap_dss_device *dssdev) | ||
701 | { | ||
702 | DSSDBG("Enter hdmi_display_disable\n"); | ||
703 | |||
704 | mutex_lock(&hdmi.lock); | ||
705 | |||
706 | hdmi_power_off_full(dssdev); | ||
707 | |||
708 | mutex_unlock(&hdmi.lock); | ||
709 | } | ||
710 | |||
711 | static int hdmi_core_enable(struct omap_dss_device *dssdev) | ||
712 | { | ||
713 | int r = 0; | ||
714 | |||
715 | DSSDBG("ENTER omapdss_hdmi_core_enable\n"); | ||
716 | |||
717 | mutex_lock(&hdmi.lock); | ||
718 | |||
719 | r = hdmi_power_on_core(dssdev); | ||
720 | if (r) { | ||
721 | DSSERR("failed to power on device\n"); | ||
722 | goto err0; | ||
723 | } | ||
724 | |||
725 | mutex_unlock(&hdmi.lock); | ||
726 | return 0; | ||
727 | |||
728 | err0: | ||
729 | mutex_unlock(&hdmi.lock); | ||
730 | return r; | ||
731 | } | ||
732 | |||
733 | static void hdmi_core_disable(struct omap_dss_device *dssdev) | ||
734 | { | ||
735 | DSSDBG("Enter omapdss_hdmi_core_disable\n"); | ||
736 | |||
737 | mutex_lock(&hdmi.lock); | ||
738 | |||
739 | hdmi_power_off_core(dssdev); | ||
740 | |||
741 | mutex_unlock(&hdmi.lock); | ||
742 | } | ||
743 | |||
744 | static int hdmi_get_clocks(struct platform_device *pdev) | ||
745 | { | ||
746 | struct clk *clk; | ||
747 | |||
748 | clk = devm_clk_get(&pdev->dev, "sys_clk"); | ||
749 | if (IS_ERR(clk)) { | ||
750 | DSSERR("can't get sys_clk\n"); | ||
751 | return PTR_ERR(clk); | ||
752 | } | ||
753 | |||
754 | hdmi.sys_clk = clk; | ||
755 | |||
756 | return 0; | ||
757 | } | ||
758 | |||
759 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
760 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts) | ||
761 | { | ||
762 | u32 deep_color; | ||
763 | bool deep_color_correct = false; | ||
764 | u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock; | ||
765 | |||
766 | if (n == NULL || cts == NULL) | ||
767 | return -EINVAL; | ||
768 | |||
769 | /* TODO: When implemented, query deep color mode here. */ | ||
770 | deep_color = 100; | ||
771 | |||
772 | /* | ||
773 | * When using deep color, the default N value (as in the HDMI | ||
774 | * specification) yields to an non-integer CTS. Hence, we | ||
775 | * modify it while keeping the restrictions described in | ||
776 | * section 7.2.1 of the HDMI 1.4a specification. | ||
777 | */ | ||
778 | switch (sample_freq) { | ||
779 | case 32000: | ||
780 | case 48000: | ||
781 | case 96000: | ||
782 | case 192000: | ||
783 | if (deep_color == 125) | ||
784 | if (pclk == 27027 || pclk == 74250) | ||
785 | deep_color_correct = true; | ||
786 | if (deep_color == 150) | ||
787 | if (pclk == 27027) | ||
788 | deep_color_correct = true; | ||
789 | break; | ||
790 | case 44100: | ||
791 | case 88200: | ||
792 | case 176400: | ||
793 | if (deep_color == 125) | ||
794 | if (pclk == 27027) | ||
795 | deep_color_correct = true; | ||
796 | break; | ||
797 | default: | ||
798 | return -EINVAL; | ||
799 | } | ||
800 | |||
801 | if (deep_color_correct) { | ||
802 | switch (sample_freq) { | ||
803 | case 32000: | ||
804 | *n = 8192; | ||
805 | break; | ||
806 | case 44100: | ||
807 | *n = 12544; | ||
808 | break; | ||
809 | case 48000: | ||
810 | *n = 8192; | ||
811 | break; | ||
812 | case 88200: | ||
813 | *n = 25088; | ||
814 | break; | ||
815 | case 96000: | ||
816 | *n = 16384; | ||
817 | break; | ||
818 | case 176400: | ||
819 | *n = 50176; | ||
820 | break; | ||
821 | case 192000: | ||
822 | *n = 32768; | ||
823 | break; | ||
824 | default: | ||
825 | return -EINVAL; | ||
826 | } | ||
827 | } else { | ||
828 | switch (sample_freq) { | ||
829 | case 32000: | ||
830 | *n = 4096; | ||
831 | break; | ||
832 | case 44100: | ||
833 | *n = 6272; | ||
834 | break; | ||
835 | case 48000: | ||
836 | *n = 6144; | ||
837 | break; | ||
838 | case 88200: | ||
839 | *n = 12544; | ||
840 | break; | ||
841 | case 96000: | ||
842 | *n = 12288; | ||
843 | break; | ||
844 | case 176400: | ||
845 | *n = 25088; | ||
846 | break; | ||
847 | case 192000: | ||
848 | *n = 24576; | ||
849 | break; | ||
850 | default: | ||
851 | return -EINVAL; | ||
852 | } | ||
853 | } | ||
854 | /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */ | ||
855 | *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10); | ||
856 | |||
857 | return 0; | ||
858 | } | ||
859 | |||
860 | static bool hdmi_mode_has_audio(void) | ||
861 | { | ||
862 | if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI) | ||
863 | return true; | ||
864 | else | ||
865 | return false; | ||
866 | } | ||
867 | |||
868 | #endif | ||
869 | |||
870 | static int hdmi_connect(struct omap_dss_device *dssdev, | ||
871 | struct omap_dss_device *dst) | ||
872 | { | ||
873 | struct omap_overlay_manager *mgr; | ||
874 | int r; | ||
875 | |||
876 | dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version()); | ||
877 | |||
878 | r = hdmi_init_regulator(); | ||
879 | if (r) | ||
880 | return r; | ||
881 | |||
882 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | ||
883 | if (!mgr) | ||
884 | return -ENODEV; | ||
885 | |||
886 | r = dss_mgr_connect(mgr, dssdev); | ||
887 | if (r) | ||
888 | return r; | ||
889 | |||
890 | r = omapdss_output_set_device(dssdev, dst); | ||
891 | if (r) { | ||
892 | DSSERR("failed to connect output to new device: %s\n", | ||
893 | dst->name); | ||
894 | dss_mgr_disconnect(mgr, dssdev); | ||
895 | return r; | ||
896 | } | ||
897 | |||
898 | return 0; | ||
899 | } | ||
900 | |||
901 | static void hdmi_disconnect(struct omap_dss_device *dssdev, | ||
902 | struct omap_dss_device *dst) | ||
903 | { | ||
904 | WARN_ON(dst != dssdev->dst); | ||
905 | |||
906 | if (dst != dssdev->dst) | ||
907 | return; | ||
908 | |||
909 | omapdss_output_unset_device(dssdev); | ||
910 | |||
911 | if (dssdev->manager) | ||
912 | dss_mgr_disconnect(dssdev->manager, dssdev); | ||
913 | } | ||
914 | |||
915 | static int hdmi_read_edid(struct omap_dss_device *dssdev, | ||
916 | u8 *edid, int len) | ||
917 | { | ||
918 | bool need_enable; | ||
919 | int r; | ||
920 | |||
921 | need_enable = hdmi.core_enabled == false; | ||
922 | |||
923 | if (need_enable) { | ||
924 | r = hdmi_core_enable(dssdev); | ||
925 | if (r) | ||
926 | return r; | ||
927 | } | ||
928 | |||
929 | r = read_edid(edid, len); | ||
930 | |||
931 | if (need_enable) | ||
932 | hdmi_core_disable(dssdev); | ||
933 | |||
934 | return r; | ||
935 | } | ||
936 | |||
937 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
938 | static int hdmi_audio_enable(struct omap_dss_device *dssdev) | ||
939 | { | ||
940 | int r; | ||
941 | |||
942 | mutex_lock(&hdmi.lock); | ||
943 | |||
944 | if (!hdmi_mode_has_audio()) { | ||
945 | r = -EPERM; | ||
946 | goto err; | ||
947 | } | ||
948 | |||
949 | |||
950 | r = hdmi.ip_data.ops->audio_enable(&hdmi.ip_data); | ||
951 | if (r) | ||
952 | goto err; | ||
953 | |||
954 | mutex_unlock(&hdmi.lock); | ||
955 | return 0; | ||
956 | |||
957 | err: | ||
958 | mutex_unlock(&hdmi.lock); | ||
959 | return r; | ||
960 | } | ||
961 | |||
962 | static void hdmi_audio_disable(struct omap_dss_device *dssdev) | ||
963 | { | ||
964 | hdmi.ip_data.ops->audio_disable(&hdmi.ip_data); | ||
965 | } | ||
966 | |||
967 | static int hdmi_audio_start(struct omap_dss_device *dssdev) | ||
968 | { | ||
969 | return hdmi.ip_data.ops->audio_start(&hdmi.ip_data); | ||
970 | } | ||
971 | |||
972 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) | ||
973 | { | ||
974 | hdmi.ip_data.ops->audio_stop(&hdmi.ip_data); | ||
975 | } | ||
976 | |||
977 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) | ||
978 | { | ||
979 | bool r; | ||
980 | |||
981 | mutex_lock(&hdmi.lock); | ||
982 | |||
983 | r = hdmi_mode_has_audio(); | ||
984 | |||
985 | mutex_unlock(&hdmi.lock); | ||
986 | return r; | ||
987 | } | ||
988 | |||
989 | static int hdmi_audio_config(struct omap_dss_device *dssdev, | ||
990 | struct omap_dss_audio *audio) | ||
991 | { | ||
992 | int r; | ||
993 | |||
994 | mutex_lock(&hdmi.lock); | ||
995 | |||
996 | if (!hdmi_mode_has_audio()) { | ||
997 | r = -EPERM; | ||
998 | goto err; | ||
999 | } | ||
1000 | |||
1001 | r = hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio); | ||
1002 | if (r) | ||
1003 | goto err; | ||
1004 | |||
1005 | mutex_unlock(&hdmi.lock); | ||
1006 | return 0; | ||
1007 | |||
1008 | err: | ||
1009 | mutex_unlock(&hdmi.lock); | ||
1010 | return r; | ||
1011 | } | ||
1012 | #else | ||
1013 | static int hdmi_audio_enable(struct omap_dss_device *dssdev) | ||
1014 | { | ||
1015 | return -EPERM; | ||
1016 | } | ||
1017 | |||
1018 | static void hdmi_audio_disable(struct omap_dss_device *dssdev) | ||
1019 | { | ||
1020 | } | ||
1021 | |||
1022 | static int hdmi_audio_start(struct omap_dss_device *dssdev) | ||
1023 | { | ||
1024 | return -EPERM; | ||
1025 | } | ||
1026 | |||
1027 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) | ||
1028 | { | ||
1029 | } | ||
1030 | |||
1031 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) | ||
1032 | { | ||
1033 | return false; | ||
1034 | } | ||
1035 | |||
1036 | static int hdmi_audio_config(struct omap_dss_device *dssdev, | ||
1037 | struct omap_dss_audio *audio) | ||
1038 | { | ||
1039 | return -EPERM; | ||
1040 | } | ||
1041 | #endif | ||
1042 | |||
1043 | static const struct omapdss_hdmi_ops hdmi_ops = { | ||
1044 | .connect = hdmi_connect, | ||
1045 | .disconnect = hdmi_disconnect, | ||
1046 | |||
1047 | .enable = hdmi_display_enable, | ||
1048 | .disable = hdmi_display_disable, | ||
1049 | |||
1050 | .check_timings = hdmi_display_check_timing, | ||
1051 | .set_timings = hdmi_display_set_timing, | ||
1052 | .get_timings = hdmi_display_get_timings, | ||
1053 | |||
1054 | .read_edid = hdmi_read_edid, | ||
1055 | |||
1056 | .audio_enable = hdmi_audio_enable, | ||
1057 | .audio_disable = hdmi_audio_disable, | ||
1058 | .audio_start = hdmi_audio_start, | ||
1059 | .audio_stop = hdmi_audio_stop, | ||
1060 | .audio_supported = hdmi_audio_supported, | ||
1061 | .audio_config = hdmi_audio_config, | ||
1062 | }; | ||
1063 | |||
1064 | static void hdmi_init_output(struct platform_device *pdev) | ||
1065 | { | ||
1066 | struct omap_dss_device *out = &hdmi.output; | ||
1067 | |||
1068 | out->dev = &pdev->dev; | ||
1069 | out->id = OMAP_DSS_OUTPUT_HDMI; | ||
1070 | out->output_type = OMAP_DISPLAY_TYPE_HDMI; | ||
1071 | out->name = "hdmi.0"; | ||
1072 | out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; | ||
1073 | out->ops.hdmi = &hdmi_ops; | ||
1074 | out->owner = THIS_MODULE; | ||
1075 | |||
1076 | omapdss_register_output(out); | ||
1077 | } | ||
1078 | |||
1079 | static void __exit hdmi_uninit_output(struct platform_device *pdev) | ||
1080 | { | ||
1081 | struct omap_dss_device *out = &hdmi.output; | ||
1082 | |||
1083 | omapdss_unregister_output(out); | ||
1084 | } | ||
1085 | |||
1086 | /* HDMI HW IP initialisation */ | ||
1087 | static int omapdss_hdmihw_probe(struct platform_device *pdev) | ||
1088 | { | ||
1089 | struct resource *res; | ||
1090 | int r; | ||
1091 | |||
1092 | hdmi.pdev = pdev; | ||
1093 | |||
1094 | mutex_init(&hdmi.lock); | ||
1095 | mutex_init(&hdmi.ip_data.lock); | ||
1096 | |||
1097 | res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); | ||
1098 | |||
1099 | /* Base address taken from platform */ | ||
1100 | hdmi.ip_data.base_wp = devm_ioremap_resource(&pdev->dev, res); | ||
1101 | if (IS_ERR(hdmi.ip_data.base_wp)) | ||
1102 | return PTR_ERR(hdmi.ip_data.base_wp); | ||
1103 | |||
1104 | hdmi.ip_data.irq = platform_get_irq(pdev, 0); | ||
1105 | if (hdmi.ip_data.irq < 0) { | ||
1106 | DSSERR("platform_get_irq failed\n"); | ||
1107 | return -ENODEV; | ||
1108 | } | ||
1109 | |||
1110 | r = hdmi_get_clocks(pdev); | ||
1111 | if (r) { | ||
1112 | DSSERR("can't get clocks\n"); | ||
1113 | return r; | ||
1114 | } | ||
1115 | |||
1116 | pm_runtime_enable(&pdev->dev); | ||
1117 | |||
1118 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; | ||
1119 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; | ||
1120 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; | ||
1121 | hdmi.ip_data.phy_offset = HDMI_PHY; | ||
1122 | |||
1123 | hdmi_init_output(pdev); | ||
1124 | |||
1125 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); | ||
1126 | |||
1127 | return 0; | ||
1128 | } | ||
1129 | |||
1130 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) | ||
1131 | { | ||
1132 | hdmi_uninit_output(pdev); | ||
1133 | |||
1134 | pm_runtime_disable(&pdev->dev); | ||
1135 | |||
1136 | return 0; | ||
1137 | } | ||
1138 | |||
1139 | static int hdmi_runtime_suspend(struct device *dev) | ||
1140 | { | ||
1141 | clk_disable_unprepare(hdmi.sys_clk); | ||
1142 | |||
1143 | dispc_runtime_put(); | ||
1144 | |||
1145 | return 0; | ||
1146 | } | ||
1147 | |||
1148 | static int hdmi_runtime_resume(struct device *dev) | ||
1149 | { | ||
1150 | int r; | ||
1151 | |||
1152 | r = dispc_runtime_get(); | ||
1153 | if (r < 0) | ||
1154 | return r; | ||
1155 | |||
1156 | clk_prepare_enable(hdmi.sys_clk); | ||
1157 | |||
1158 | return 0; | ||
1159 | } | ||
1160 | |||
1161 | static const struct dev_pm_ops hdmi_pm_ops = { | ||
1162 | .runtime_suspend = hdmi_runtime_suspend, | ||
1163 | .runtime_resume = hdmi_runtime_resume, | ||
1164 | }; | ||
1165 | |||
1166 | static struct platform_driver omapdss_hdmihw_driver = { | ||
1167 | .probe = omapdss_hdmihw_probe, | ||
1168 | .remove = __exit_p(omapdss_hdmihw_remove), | ||
1169 | .driver = { | ||
1170 | .name = "omapdss_hdmi", | ||
1171 | .owner = THIS_MODULE, | ||
1172 | .pm = &hdmi_pm_ops, | ||
1173 | }, | ||
1174 | }; | ||
1175 | |||
1176 | int __init hdmi_init_platform_driver(void) | ||
1177 | { | ||
1178 | return platform_driver_register(&omapdss_hdmihw_driver); | ||
1179 | } | ||
1180 | |||
1181 | void __exit hdmi_uninit_platform_driver(void) | ||
1182 | { | ||
1183 | platform_driver_unregister(&omapdss_hdmihw_driver); | ||
1184 | } | ||
diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h new file mode 100644 index 000000000000..b0493768a5d7 --- /dev/null +++ b/drivers/video/omap2/dss/hdmi.h | |||
@@ -0,0 +1,444 @@ | |||
1 | /* | ||
2 | * HDMI driver definition for TI OMAP4 Processor. | ||
3 | * | ||
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License version 2 as published by | ||
8 | * the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #ifndef _HDMI_H | ||
20 | #define _HDMI_H | ||
21 | |||
22 | #include <linux/delay.h> | ||
23 | #include <linux/io.h> | ||
24 | #include <linux/platform_device.h> | ||
25 | #include <video/omapdss.h> | ||
26 | |||
27 | #include "dss.h" | ||
28 | |||
29 | /* HDMI Wrapper */ | ||
30 | |||
31 | #define HDMI_WP_REVISION 0x0 | ||
32 | #define HDMI_WP_SYSCONFIG 0x10 | ||
33 | #define HDMI_WP_IRQSTATUS_RAW 0x24 | ||
34 | #define HDMI_WP_IRQSTATUS 0x28 | ||
35 | #define HDMI_WP_IRQENABLE_SET 0x2C | ||
36 | #define HDMI_WP_IRQENABLE_CLR 0x30 | ||
37 | #define HDMI_WP_IRQWAKEEN 0x34 | ||
38 | #define HDMI_WP_PWR_CTRL 0x40 | ||
39 | #define HDMI_WP_DEBOUNCE 0x44 | ||
40 | #define HDMI_WP_VIDEO_CFG 0x50 | ||
41 | #define HDMI_WP_VIDEO_SIZE 0x60 | ||
42 | #define HDMI_WP_VIDEO_TIMING_H 0x68 | ||
43 | #define HDMI_WP_VIDEO_TIMING_V 0x6C | ||
44 | #define HDMI_WP_WP_CLK 0x70 | ||
45 | #define HDMI_WP_AUDIO_CFG 0x80 | ||
46 | #define HDMI_WP_AUDIO_CFG2 0x84 | ||
47 | #define HDMI_WP_AUDIO_CTRL 0x88 | ||
48 | #define HDMI_WP_AUDIO_DATA 0x8C | ||
49 | |||
50 | /* HDMI WP IRQ flags */ | ||
51 | |||
52 | #define HDMI_IRQ_OCP_TIMEOUT (1 << 4) | ||
53 | #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8) | ||
54 | #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9) | ||
55 | #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10) | ||
56 | #define HDMI_IRQ_VIDEO_VSYNC (1 << 16) | ||
57 | #define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17) | ||
58 | #define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24) | ||
59 | #define HDMI_IRQ_LINK_CONNECT (1 << 25) | ||
60 | #define HDMI_IRQ_LINK_DISCONNECT (1 << 26) | ||
61 | #define HDMI_IRQ_PLL_LOCK (1 << 29) | ||
62 | #define HDMI_IRQ_PLL_UNLOCK (1 << 30) | ||
63 | #define HDMI_IRQ_PLL_RECAL (1 << 31) | ||
64 | |||
65 | /* HDMI PLL */ | ||
66 | |||
67 | #define PLLCTRL_PLL_CONTROL 0x0 | ||
68 | #define PLLCTRL_PLL_STATUS 0x4 | ||
69 | #define PLLCTRL_PLL_GO 0x8 | ||
70 | #define PLLCTRL_CFG1 0xC | ||
71 | #define PLLCTRL_CFG2 0x10 | ||
72 | #define PLLCTRL_CFG3 0x14 | ||
73 | #define PLLCTRL_SSC_CFG1 0x18 | ||
74 | #define PLLCTRL_SSC_CFG2 0x1C | ||
75 | #define PLLCTRL_CFG4 0x20 | ||
76 | |||
77 | /* HDMI PHY */ | ||
78 | |||
79 | #define HDMI_TXPHY_TX_CTRL 0x0 | ||
80 | #define HDMI_TXPHY_DIGITAL_CTRL 0x4 | ||
81 | #define HDMI_TXPHY_POWER_CTRL 0x8 | ||
82 | #define HDMI_TXPHY_PAD_CFG_CTRL 0xC | ||
83 | |||
84 | enum hdmi_pll_pwr { | ||
85 | HDMI_PLLPWRCMD_ALLOFF = 0, | ||
86 | HDMI_PLLPWRCMD_PLLONLY = 1, | ||
87 | HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, | ||
88 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 | ||
89 | }; | ||
90 | |||
91 | enum hdmi_phy_pwr { | ||
92 | HDMI_PHYPWRCMD_OFF = 0, | ||
93 | HDMI_PHYPWRCMD_LDOON = 1, | ||
94 | HDMI_PHYPWRCMD_TXON = 2 | ||
95 | }; | ||
96 | |||
97 | enum hdmi_core_hdmi_dvi { | ||
98 | HDMI_DVI = 0, | ||
99 | HDMI_HDMI = 1 | ||
100 | }; | ||
101 | |||
102 | enum hdmi_clk_refsel { | ||
103 | HDMI_REFSEL_PCLK = 0, | ||
104 | HDMI_REFSEL_REF1 = 1, | ||
105 | HDMI_REFSEL_REF2 = 2, | ||
106 | HDMI_REFSEL_SYSCLK = 3 | ||
107 | }; | ||
108 | |||
109 | enum hdmi_packing_mode { | ||
110 | HDMI_PACK_10b_RGB_YUV444 = 0, | ||
111 | HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, | ||
112 | HDMI_PACK_20b_YUV422 = 2, | ||
113 | HDMI_PACK_ALREADYPACKED = 7 | ||
114 | }; | ||
115 | |||
116 | enum hdmi_stereo_channels { | ||
117 | HDMI_AUDIO_STEREO_NOCHANNELS = 0, | ||
118 | HDMI_AUDIO_STEREO_ONECHANNEL = 1, | ||
119 | HDMI_AUDIO_STEREO_TWOCHANNELS = 2, | ||
120 | HDMI_AUDIO_STEREO_THREECHANNELS = 3, | ||
121 | HDMI_AUDIO_STEREO_FOURCHANNELS = 4 | ||
122 | }; | ||
123 | |||
124 | enum hdmi_audio_type { | ||
125 | HDMI_AUDIO_TYPE_LPCM = 0, | ||
126 | HDMI_AUDIO_TYPE_IEC = 1 | ||
127 | }; | ||
128 | |||
129 | enum hdmi_audio_justify { | ||
130 | HDMI_AUDIO_JUSTIFY_LEFT = 0, | ||
131 | HDMI_AUDIO_JUSTIFY_RIGHT = 1 | ||
132 | }; | ||
133 | |||
134 | enum hdmi_audio_sample_order { | ||
135 | HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0, | ||
136 | HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1 | ||
137 | }; | ||
138 | |||
139 | enum hdmi_audio_samples_perword { | ||
140 | HDMI_AUDIO_ONEWORD_ONESAMPLE = 0, | ||
141 | HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1 | ||
142 | }; | ||
143 | |||
144 | enum hdmi_audio_sample_size { | ||
145 | HDMI_AUDIO_SAMPLE_16BITS = 0, | ||
146 | HDMI_AUDIO_SAMPLE_24BITS = 1 | ||
147 | }; | ||
148 | |||
149 | enum hdmi_audio_transf_mode { | ||
150 | HDMI_AUDIO_TRANSF_DMA = 0, | ||
151 | HDMI_AUDIO_TRANSF_IRQ = 1 | ||
152 | }; | ||
153 | |||
154 | enum hdmi_audio_blk_strt_end_sig { | ||
155 | HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0, | ||
156 | HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1 | ||
157 | }; | ||
158 | |||
159 | enum hdmi_core_audio_layout { | ||
160 | HDMI_AUDIO_LAYOUT_2CH = 0, | ||
161 | HDMI_AUDIO_LAYOUT_8CH = 1 | ||
162 | }; | ||
163 | |||
164 | enum hdmi_core_cts_mode { | ||
165 | HDMI_AUDIO_CTS_MODE_HW = 0, | ||
166 | HDMI_AUDIO_CTS_MODE_SW = 1 | ||
167 | }; | ||
168 | |||
169 | enum hdmi_audio_mclk_mode { | ||
170 | HDMI_AUDIO_MCLK_128FS = 0, | ||
171 | HDMI_AUDIO_MCLK_256FS = 1, | ||
172 | HDMI_AUDIO_MCLK_384FS = 2, | ||
173 | HDMI_AUDIO_MCLK_512FS = 3, | ||
174 | HDMI_AUDIO_MCLK_768FS = 4, | ||
175 | HDMI_AUDIO_MCLK_1024FS = 5, | ||
176 | HDMI_AUDIO_MCLK_1152FS = 6, | ||
177 | HDMI_AUDIO_MCLK_192FS = 7 | ||
178 | }; | ||
179 | |||
180 | /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */ | ||
181 | enum hdmi_core_infoframe { | ||
182 | HDMI_INFOFRAME_AVI_DB1Y_RGB = 0, | ||
183 | HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1, | ||
184 | HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2, | ||
185 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0, | ||
186 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1, | ||
187 | HDMI_INFOFRAME_AVI_DB1B_NO = 0, | ||
188 | HDMI_INFOFRAME_AVI_DB1B_VERT = 1, | ||
189 | HDMI_INFOFRAME_AVI_DB1B_HORI = 2, | ||
190 | HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3, | ||
191 | HDMI_INFOFRAME_AVI_DB1S_0 = 0, | ||
192 | HDMI_INFOFRAME_AVI_DB1S_1 = 1, | ||
193 | HDMI_INFOFRAME_AVI_DB1S_2 = 2, | ||
194 | HDMI_INFOFRAME_AVI_DB2C_NO = 0, | ||
195 | HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1, | ||
196 | HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2, | ||
197 | HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3, | ||
198 | HDMI_INFOFRAME_AVI_DB2M_NO = 0, | ||
199 | HDMI_INFOFRAME_AVI_DB2M_43 = 1, | ||
200 | HDMI_INFOFRAME_AVI_DB2M_169 = 2, | ||
201 | HDMI_INFOFRAME_AVI_DB2R_SAME = 8, | ||
202 | HDMI_INFOFRAME_AVI_DB2R_43 = 9, | ||
203 | HDMI_INFOFRAME_AVI_DB2R_169 = 10, | ||
204 | HDMI_INFOFRAME_AVI_DB2R_149 = 11, | ||
205 | HDMI_INFOFRAME_AVI_DB3ITC_NO = 0, | ||
206 | HDMI_INFOFRAME_AVI_DB3ITC_YES = 1, | ||
207 | HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0, | ||
208 | HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1, | ||
209 | HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0, | ||
210 | HDMI_INFOFRAME_AVI_DB3Q_LR = 1, | ||
211 | HDMI_INFOFRAME_AVI_DB3Q_FR = 2, | ||
212 | HDMI_INFOFRAME_AVI_DB3SC_NO = 0, | ||
213 | HDMI_INFOFRAME_AVI_DB3SC_HORI = 1, | ||
214 | HDMI_INFOFRAME_AVI_DB3SC_VERT = 2, | ||
215 | HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3, | ||
216 | HDMI_INFOFRAME_AVI_DB5PR_NO = 0, | ||
217 | HDMI_INFOFRAME_AVI_DB5PR_2 = 1, | ||
218 | HDMI_INFOFRAME_AVI_DB5PR_3 = 2, | ||
219 | HDMI_INFOFRAME_AVI_DB5PR_4 = 3, | ||
220 | HDMI_INFOFRAME_AVI_DB5PR_5 = 4, | ||
221 | HDMI_INFOFRAME_AVI_DB5PR_6 = 5, | ||
222 | HDMI_INFOFRAME_AVI_DB5PR_7 = 6, | ||
223 | HDMI_INFOFRAME_AVI_DB5PR_8 = 7, | ||
224 | HDMI_INFOFRAME_AVI_DB5PR_9 = 8, | ||
225 | HDMI_INFOFRAME_AVI_DB5PR_10 = 9, | ||
226 | }; | ||
227 | |||
228 | struct hdmi_cm { | ||
229 | int code; | ||
230 | int mode; | ||
231 | }; | ||
232 | |||
233 | struct hdmi_video_format { | ||
234 | enum hdmi_packing_mode packing_mode; | ||
235 | u32 y_res; /* Line per panel */ | ||
236 | u32 x_res; /* pixel per line */ | ||
237 | }; | ||
238 | |||
239 | struct hdmi_config { | ||
240 | struct omap_video_timings timings; | ||
241 | struct hdmi_cm cm; | ||
242 | }; | ||
243 | |||
244 | /* HDMI PLL structure */ | ||
245 | struct hdmi_pll_info { | ||
246 | u16 regn; | ||
247 | u16 regm; | ||
248 | u32 regmf; | ||
249 | u16 regm2; | ||
250 | u16 regsd; | ||
251 | u16 dcofreq; | ||
252 | enum hdmi_clk_refsel refsel; | ||
253 | }; | ||
254 | |||
255 | struct hdmi_audio_format { | ||
256 | enum hdmi_stereo_channels stereo_channels; | ||
257 | u8 active_chnnls_msk; | ||
258 | enum hdmi_audio_type type; | ||
259 | enum hdmi_audio_justify justification; | ||
260 | enum hdmi_audio_sample_order sample_order; | ||
261 | enum hdmi_audio_samples_perword samples_per_word; | ||
262 | enum hdmi_audio_sample_size sample_size; | ||
263 | enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end; | ||
264 | }; | ||
265 | |||
266 | struct hdmi_audio_dma { | ||
267 | u8 transfer_size; | ||
268 | u8 block_size; | ||
269 | enum hdmi_audio_transf_mode mode; | ||
270 | u16 fifo_threshold; | ||
271 | }; | ||
272 | |||
273 | struct hdmi_core_audio_i2s_config { | ||
274 | u8 in_length_bits; | ||
275 | u8 justification; | ||
276 | u8 sck_edge_mode; | ||
277 | u8 vbit; | ||
278 | u8 direction; | ||
279 | u8 shift; | ||
280 | u8 active_sds; | ||
281 | }; | ||
282 | |||
283 | struct hdmi_core_audio_config { | ||
284 | struct hdmi_core_audio_i2s_config i2s_cfg; | ||
285 | struct snd_aes_iec958 *iec60958_cfg; | ||
286 | bool fs_override; | ||
287 | u32 n; | ||
288 | u32 cts; | ||
289 | u32 aud_par_busclk; | ||
290 | enum hdmi_core_audio_layout layout; | ||
291 | enum hdmi_core_cts_mode cts_mode; | ||
292 | bool use_mclk; | ||
293 | enum hdmi_audio_mclk_mode mclk_mode; | ||
294 | bool en_acr_pkt; | ||
295 | bool en_dsd_audio; | ||
296 | bool en_parallel_aud_input; | ||
297 | bool en_spdif; | ||
298 | }; | ||
299 | |||
300 | /* | ||
301 | * Refer to section 8.2 in HDMI 1.3 specification for | ||
302 | * details about infoframe databytes | ||
303 | */ | ||
304 | struct hdmi_core_infoframe_avi { | ||
305 | /* Y0, Y1 rgb,yCbCr */ | ||
306 | u8 db1_format; | ||
307 | /* A0 Active information Present */ | ||
308 | u8 db1_active_info; | ||
309 | /* B0, B1 Bar info data valid */ | ||
310 | u8 db1_bar_info_dv; | ||
311 | /* S0, S1 scan information */ | ||
312 | u8 db1_scan_info; | ||
313 | /* C0, C1 colorimetry */ | ||
314 | u8 db2_colorimetry; | ||
315 | /* M0, M1 Aspect ratio (4:3, 16:9) */ | ||
316 | u8 db2_aspect_ratio; | ||
317 | /* R0...R3 Active format aspect ratio */ | ||
318 | u8 db2_active_fmt_ar; | ||
319 | /* ITC IT content. */ | ||
320 | u8 db3_itc; | ||
321 | /* EC0, EC1, EC2 Extended colorimetry */ | ||
322 | u8 db3_ec; | ||
323 | /* Q1, Q0 Quantization range */ | ||
324 | u8 db3_q_range; | ||
325 | /* SC1, SC0 Non-uniform picture scaling */ | ||
326 | u8 db3_nup_scaling; | ||
327 | /* VIC0..6 Video format identification */ | ||
328 | u8 db4_videocode; | ||
329 | /* PR0..PR3 Pixel repetition factor */ | ||
330 | u8 db5_pixel_repeat; | ||
331 | /* Line number end of top bar */ | ||
332 | u16 db6_7_line_eoftop; | ||
333 | /* Line number start of bottom bar */ | ||
334 | u16 db8_9_line_sofbottom; | ||
335 | /* Pixel number end of left bar */ | ||
336 | u16 db10_11_pixel_eofleft; | ||
337 | /* Pixel number start of right bar */ | ||
338 | u16 db12_13_pixel_sofright; | ||
339 | }; | ||
340 | |||
341 | struct hdmi_wp_data { | ||
342 | void __iomem *base; | ||
343 | }; | ||
344 | |||
345 | struct hdmi_pll_data { | ||
346 | void __iomem *base; | ||
347 | |||
348 | struct hdmi_pll_info info; | ||
349 | }; | ||
350 | |||
351 | struct hdmi_phy_data { | ||
352 | void __iomem *base; | ||
353 | |||
354 | int irq; | ||
355 | }; | ||
356 | |||
357 | struct hdmi_core_data { | ||
358 | void __iomem *base; | ||
359 | |||
360 | struct hdmi_core_infoframe_avi avi_cfg; | ||
361 | }; | ||
362 | |||
363 | static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx, | ||
364 | u32 val) | ||
365 | { | ||
366 | __raw_writel(val, base_addr + idx); | ||
367 | } | ||
368 | |||
369 | static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx) | ||
370 | { | ||
371 | return __raw_readl(base_addr + idx); | ||
372 | } | ||
373 | |||
374 | #define REG_FLD_MOD(base, idx, val, start, end) \ | ||
375 | hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ | ||
376 | val, start, end)) | ||
377 | #define REG_GET(base, idx, start, end) \ | ||
378 | FLD_GET(hdmi_read_reg(base, idx), start, end) | ||
379 | |||
380 | static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, | ||
381 | const u16 idx, int b2, int b1, u32 val) | ||
382 | { | ||
383 | u32 t = 0; | ||
384 | while (val != REG_GET(base_addr, idx, b2, b1)) { | ||
385 | udelay(1); | ||
386 | if (t++ > 10000) | ||
387 | return !val; | ||
388 | } | ||
389 | return val; | ||
390 | } | ||
391 | |||
392 | /* HDMI wrapper funcs */ | ||
393 | int hdmi_wp_video_start(struct hdmi_wp_data *wp); | ||
394 | void hdmi_wp_video_stop(struct hdmi_wp_data *wp); | ||
395 | void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s); | ||
396 | u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp); | ||
397 | void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus); | ||
398 | void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); | ||
399 | void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); | ||
400 | int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); | ||
401 | int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); | ||
402 | void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, | ||
403 | struct hdmi_video_format *video_fmt); | ||
404 | void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, | ||
405 | struct omap_video_timings *timings); | ||
406 | void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, | ||
407 | struct omap_video_timings *timings); | ||
408 | void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, | ||
409 | struct omap_video_timings *timings, struct hdmi_config *param); | ||
410 | int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); | ||
411 | |||
412 | /* HDMI PLL funcs */ | ||
413 | int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); | ||
414 | void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); | ||
415 | void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); | ||
416 | void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy); | ||
417 | int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll); | ||
418 | |||
419 | /* HDMI PHY funcs */ | ||
420 | int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp, | ||
421 | struct hdmi_config *cfg); | ||
422 | void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp); | ||
423 | void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); | ||
424 | int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy); | ||
425 | |||
426 | /* HDMI common funcs */ | ||
427 | const struct hdmi_config *hdmi_default_timing(void); | ||
428 | const struct hdmi_config *hdmi_get_timings(int mode, int code); | ||
429 | struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing); | ||
430 | |||
431 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
432 | int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts); | ||
433 | int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); | ||
434 | int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable); | ||
435 | void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, | ||
436 | struct hdmi_audio_format *aud_fmt); | ||
437 | void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, | ||
438 | struct hdmi_audio_dma *aud_dma); | ||
439 | static inline bool hdmi_mode_has_audio(int mode) | ||
440 | { | ||
441 | return mode == HDMI_HDMI ? true : false; | ||
442 | } | ||
443 | #endif | ||
444 | #endif | ||
diff --git a/drivers/video/omap2/dss/hdmi4.c b/drivers/video/omap2/dss/hdmi4.c new file mode 100644 index 000000000000..e14009614338 --- /dev/null +++ b/drivers/video/omap2/dss/hdmi4.c | |||
@@ -0,0 +1,696 @@ | |||
1 | /* | ||
2 | * HDMI interface DSS driver for TI's OMAP4 family of SoCs. | ||
3 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | ||
4 | * Authors: Yong Zhi | ||
5 | * Mythri pk <mythripk@ti.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License version 2 as published by | ||
9 | * the Free Software Foundation. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
14 | * more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License along with | ||
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
18 | */ | ||
19 | |||
20 | #define DSS_SUBSYS_NAME "HDMI" | ||
21 | |||
22 | #include <linux/kernel.h> | ||
23 | #include <linux/module.h> | ||
24 | #include <linux/err.h> | ||
25 | #include <linux/io.h> | ||
26 | #include <linux/interrupt.h> | ||
27 | #include <linux/mutex.h> | ||
28 | #include <linux/delay.h> | ||
29 | #include <linux/string.h> | ||
30 | #include <linux/platform_device.h> | ||
31 | #include <linux/pm_runtime.h> | ||
32 | #include <linux/clk.h> | ||
33 | #include <linux/gpio.h> | ||
34 | #include <linux/regulator/consumer.h> | ||
35 | #include <video/omapdss.h> | ||
36 | |||
37 | #include "hdmi4_core.h" | ||
38 | #include "dss.h" | ||
39 | #include "dss_features.h" | ||
40 | |||
41 | static struct { | ||
42 | struct mutex lock; | ||
43 | struct platform_device *pdev; | ||
44 | |||
45 | struct hdmi_wp_data wp; | ||
46 | struct hdmi_pll_data pll; | ||
47 | struct hdmi_phy_data phy; | ||
48 | struct hdmi_core_data core; | ||
49 | |||
50 | struct hdmi_config cfg; | ||
51 | |||
52 | struct clk *sys_clk; | ||
53 | struct regulator *vdda_hdmi_dac_reg; | ||
54 | |||
55 | bool core_enabled; | ||
56 | |||
57 | struct omap_dss_device output; | ||
58 | } hdmi; | ||
59 | |||
60 | static int hdmi_runtime_get(void) | ||
61 | { | ||
62 | int r; | ||
63 | |||
64 | DSSDBG("hdmi_runtime_get\n"); | ||
65 | |||
66 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | ||
67 | WARN_ON(r < 0); | ||
68 | if (r < 0) | ||
69 | return r; | ||
70 | |||
71 | return 0; | ||
72 | } | ||
73 | |||
74 | static void hdmi_runtime_put(void) | ||
75 | { | ||
76 | int r; | ||
77 | |||
78 | DSSDBG("hdmi_runtime_put\n"); | ||
79 | |||
80 | r = pm_runtime_put_sync(&hdmi.pdev->dev); | ||
81 | WARN_ON(r < 0 && r != -ENOSYS); | ||
82 | } | ||
83 | |||
84 | static int hdmi_init_regulator(void) | ||
85 | { | ||
86 | struct regulator *reg; | ||
87 | |||
88 | if (hdmi.vdda_hdmi_dac_reg != NULL) | ||
89 | return 0; | ||
90 | |||
91 | reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac"); | ||
92 | |||
93 | /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */ | ||
94 | if (IS_ERR(reg)) | ||
95 | reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC"); | ||
96 | |||
97 | if (IS_ERR(reg)) { | ||
98 | DSSERR("can't get VDDA_HDMI_DAC regulator\n"); | ||
99 | return PTR_ERR(reg); | ||
100 | } | ||
101 | |||
102 | hdmi.vdda_hdmi_dac_reg = reg; | ||
103 | |||
104 | return 0; | ||
105 | } | ||
106 | |||
107 | static int hdmi_power_on_core(struct omap_dss_device *dssdev) | ||
108 | { | ||
109 | int r; | ||
110 | |||
111 | r = regulator_enable(hdmi.vdda_hdmi_dac_reg); | ||
112 | if (r) | ||
113 | return r; | ||
114 | |||
115 | r = hdmi_runtime_get(); | ||
116 | if (r) | ||
117 | goto err_runtime_get; | ||
118 | |||
119 | /* Make selection of HDMI in DSS */ | ||
120 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | ||
121 | |||
122 | hdmi.core_enabled = true; | ||
123 | |||
124 | return 0; | ||
125 | |||
126 | err_runtime_get: | ||
127 | regulator_disable(hdmi.vdda_hdmi_dac_reg); | ||
128 | |||
129 | return r; | ||
130 | } | ||
131 | |||
132 | static void hdmi_power_off_core(struct omap_dss_device *dssdev) | ||
133 | { | ||
134 | hdmi.core_enabled = false; | ||
135 | |||
136 | hdmi_runtime_put(); | ||
137 | regulator_disable(hdmi.vdda_hdmi_dac_reg); | ||
138 | } | ||
139 | |||
140 | static int hdmi_power_on_full(struct omap_dss_device *dssdev) | ||
141 | { | ||
142 | int r; | ||
143 | struct omap_video_timings *p; | ||
144 | struct omap_overlay_manager *mgr = hdmi.output.manager; | ||
145 | unsigned long phy; | ||
146 | |||
147 | r = hdmi_power_on_core(dssdev); | ||
148 | if (r) | ||
149 | return r; | ||
150 | |||
151 | dss_mgr_disable(mgr); | ||
152 | |||
153 | p = &hdmi.cfg.timings; | ||
154 | |||
155 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); | ||
156 | |||
157 | phy = p->pixel_clock; | ||
158 | |||
159 | hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy); | ||
160 | |||
161 | hdmi_wp_video_stop(&hdmi.wp); | ||
162 | |||
163 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ | ||
164 | r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp); | ||
165 | if (r) { | ||
166 | DSSDBG("Failed to lock PLL\n"); | ||
167 | goto err_pll_enable; | ||
168 | } | ||
169 | |||
170 | r = hdmi_phy_enable(&hdmi.phy, &hdmi.wp, &hdmi.cfg); | ||
171 | if (r) { | ||
172 | DSSDBG("Failed to start PHY\n"); | ||
173 | goto err_phy_enable; | ||
174 | } | ||
175 | |||
176 | hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); | ||
177 | |||
178 | /* bypass TV gamma table */ | ||
179 | dispc_enable_gamma_table(0); | ||
180 | |||
181 | /* tv size */ | ||
182 | dss_mgr_set_timings(mgr, p); | ||
183 | |||
184 | r = hdmi_wp_video_start(&hdmi.wp); | ||
185 | if (r) | ||
186 | goto err_vid_enable; | ||
187 | |||
188 | r = dss_mgr_enable(mgr); | ||
189 | if (r) | ||
190 | goto err_mgr_enable; | ||
191 | |||
192 | return 0; | ||
193 | |||
194 | err_mgr_enable: | ||
195 | hdmi_wp_video_stop(&hdmi.wp); | ||
196 | err_vid_enable: | ||
197 | hdmi_phy_disable(&hdmi.phy, &hdmi.wp); | ||
198 | err_phy_enable: | ||
199 | hdmi_pll_disable(&hdmi.pll, &hdmi.wp); | ||
200 | err_pll_enable: | ||
201 | hdmi_power_off_core(dssdev); | ||
202 | return -EIO; | ||
203 | } | ||
204 | |||
205 | static void hdmi_power_off_full(struct omap_dss_device *dssdev) | ||
206 | { | ||
207 | struct omap_overlay_manager *mgr = hdmi.output.manager; | ||
208 | |||
209 | dss_mgr_disable(mgr); | ||
210 | |||
211 | hdmi_wp_video_stop(&hdmi.wp); | ||
212 | hdmi_phy_disable(&hdmi.phy, &hdmi.wp); | ||
213 | hdmi_pll_disable(&hdmi.pll, &hdmi.wp); | ||
214 | |||
215 | hdmi_power_off_core(dssdev); | ||
216 | } | ||
217 | |||
218 | static int hdmi_display_check_timing(struct omap_dss_device *dssdev, | ||
219 | struct omap_video_timings *timings) | ||
220 | { | ||
221 | struct hdmi_cm cm; | ||
222 | |||
223 | cm = hdmi_get_code(timings); | ||
224 | if (cm.code == -1) | ||
225 | return -EINVAL; | ||
226 | |||
227 | return 0; | ||
228 | |||
229 | } | ||
230 | |||
231 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | ||
232 | struct omap_video_timings *timings) | ||
233 | { | ||
234 | struct hdmi_cm cm; | ||
235 | const struct hdmi_config *t; | ||
236 | |||
237 | mutex_lock(&hdmi.lock); | ||
238 | |||
239 | cm = hdmi_get_code(timings); | ||
240 | hdmi.cfg.cm = cm; | ||
241 | |||
242 | t = hdmi_get_timings(cm.mode, cm.code); | ||
243 | if (t != NULL) { | ||
244 | hdmi.cfg = *t; | ||
245 | |||
246 | dispc_set_tv_pclk(t->timings.pixel_clock * 1000); | ||
247 | } | ||
248 | |||
249 | mutex_unlock(&hdmi.lock); | ||
250 | } | ||
251 | |||
252 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, | ||
253 | struct omap_video_timings *timings) | ||
254 | { | ||
255 | const struct hdmi_config *cfg; | ||
256 | struct hdmi_cm cm = hdmi.cfg.cm; | ||
257 | |||
258 | cfg = hdmi_get_timings(cm.mode, cm.code); | ||
259 | if (cfg == NULL) | ||
260 | cfg = hdmi_default_timing(); | ||
261 | |||
262 | memcpy(timings, &cfg->timings, sizeof(cfg->timings)); | ||
263 | } | ||
264 | |||
265 | static void hdmi_dump_regs(struct seq_file *s) | ||
266 | { | ||
267 | mutex_lock(&hdmi.lock); | ||
268 | |||
269 | if (hdmi_runtime_get()) { | ||
270 | mutex_unlock(&hdmi.lock); | ||
271 | return; | ||
272 | } | ||
273 | |||
274 | hdmi_wp_dump(&hdmi.wp, s); | ||
275 | hdmi_pll_dump(&hdmi.pll, s); | ||
276 | hdmi_phy_dump(&hdmi.phy, s); | ||
277 | hdmi4_core_dump(&hdmi.core, s); | ||
278 | |||
279 | hdmi_runtime_put(); | ||
280 | mutex_unlock(&hdmi.lock); | ||
281 | } | ||
282 | |||
283 | static int read_edid(u8 *buf, int len) | ||
284 | { | ||
285 | int r; | ||
286 | |||
287 | mutex_lock(&hdmi.lock); | ||
288 | |||
289 | r = hdmi_runtime_get(); | ||
290 | BUG_ON(r); | ||
291 | |||
292 | r = hdmi4_read_edid(&hdmi.core, buf, len); | ||
293 | |||
294 | hdmi_runtime_put(); | ||
295 | mutex_unlock(&hdmi.lock); | ||
296 | |||
297 | return r; | ||
298 | } | ||
299 | |||
300 | static int hdmi_display_enable(struct omap_dss_device *dssdev) | ||
301 | { | ||
302 | struct omap_dss_device *out = &hdmi.output; | ||
303 | int r = 0; | ||
304 | |||
305 | DSSDBG("ENTER hdmi_display_enable\n"); | ||
306 | |||
307 | mutex_lock(&hdmi.lock); | ||
308 | |||
309 | if (out == NULL || out->manager == NULL) { | ||
310 | DSSERR("failed to enable display: no output/manager\n"); | ||
311 | r = -ENODEV; | ||
312 | goto err0; | ||
313 | } | ||
314 | |||
315 | r = hdmi_power_on_full(dssdev); | ||
316 | if (r) { | ||
317 | DSSERR("failed to power on device\n"); | ||
318 | goto err0; | ||
319 | } | ||
320 | |||
321 | mutex_unlock(&hdmi.lock); | ||
322 | return 0; | ||
323 | |||
324 | err0: | ||
325 | mutex_unlock(&hdmi.lock); | ||
326 | return r; | ||
327 | } | ||
328 | |||
329 | static void hdmi_display_disable(struct omap_dss_device *dssdev) | ||
330 | { | ||
331 | DSSDBG("Enter hdmi_display_disable\n"); | ||
332 | |||
333 | mutex_lock(&hdmi.lock); | ||
334 | |||
335 | hdmi_power_off_full(dssdev); | ||
336 | |||
337 | mutex_unlock(&hdmi.lock); | ||
338 | } | ||
339 | |||
340 | static int hdmi_core_enable(struct omap_dss_device *dssdev) | ||
341 | { | ||
342 | int r = 0; | ||
343 | |||
344 | DSSDBG("ENTER omapdss_hdmi_core_enable\n"); | ||
345 | |||
346 | mutex_lock(&hdmi.lock); | ||
347 | |||
348 | r = hdmi_power_on_core(dssdev); | ||
349 | if (r) { | ||
350 | DSSERR("failed to power on device\n"); | ||
351 | goto err0; | ||
352 | } | ||
353 | |||
354 | mutex_unlock(&hdmi.lock); | ||
355 | return 0; | ||
356 | |||
357 | err0: | ||
358 | mutex_unlock(&hdmi.lock); | ||
359 | return r; | ||
360 | } | ||
361 | |||
362 | static void hdmi_core_disable(struct omap_dss_device *dssdev) | ||
363 | { | ||
364 | DSSDBG("Enter omapdss_hdmi_core_disable\n"); | ||
365 | |||
366 | mutex_lock(&hdmi.lock); | ||
367 | |||
368 | hdmi_power_off_core(dssdev); | ||
369 | |||
370 | mutex_unlock(&hdmi.lock); | ||
371 | } | ||
372 | |||
373 | static int hdmi_get_clocks(struct platform_device *pdev) | ||
374 | { | ||
375 | struct clk *clk; | ||
376 | |||
377 | clk = devm_clk_get(&pdev->dev, "sys_clk"); | ||
378 | if (IS_ERR(clk)) { | ||
379 | DSSERR("can't get sys_clk\n"); | ||
380 | return PTR_ERR(clk); | ||
381 | } | ||
382 | |||
383 | hdmi.sys_clk = clk; | ||
384 | |||
385 | return 0; | ||
386 | } | ||
387 | |||
388 | static int hdmi_connect(struct omap_dss_device *dssdev, | ||
389 | struct omap_dss_device *dst) | ||
390 | { | ||
391 | struct omap_overlay_manager *mgr; | ||
392 | int r; | ||
393 | |||
394 | r = hdmi_init_regulator(); | ||
395 | if (r) | ||
396 | return r; | ||
397 | |||
398 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | ||
399 | if (!mgr) | ||
400 | return -ENODEV; | ||
401 | |||
402 | r = dss_mgr_connect(mgr, dssdev); | ||
403 | if (r) | ||
404 | return r; | ||
405 | |||
406 | r = omapdss_output_set_device(dssdev, dst); | ||
407 | if (r) { | ||
408 | DSSERR("failed to connect output to new device: %s\n", | ||
409 | dst->name); | ||
410 | dss_mgr_disconnect(mgr, dssdev); | ||
411 | return r; | ||
412 | } | ||
413 | |||
414 | return 0; | ||
415 | } | ||
416 | |||
417 | static void hdmi_disconnect(struct omap_dss_device *dssdev, | ||
418 | struct omap_dss_device *dst) | ||
419 | { | ||
420 | WARN_ON(dst != dssdev->dst); | ||
421 | |||
422 | if (dst != dssdev->dst) | ||
423 | return; | ||
424 | |||
425 | omapdss_output_unset_device(dssdev); | ||
426 | |||
427 | if (dssdev->manager) | ||
428 | dss_mgr_disconnect(dssdev->manager, dssdev); | ||
429 | } | ||
430 | |||
431 | static int hdmi_read_edid(struct omap_dss_device *dssdev, | ||
432 | u8 *edid, int len) | ||
433 | { | ||
434 | bool need_enable; | ||
435 | int r; | ||
436 | |||
437 | need_enable = hdmi.core_enabled == false; | ||
438 | |||
439 | if (need_enable) { | ||
440 | r = hdmi_core_enable(dssdev); | ||
441 | if (r) | ||
442 | return r; | ||
443 | } | ||
444 | |||
445 | r = read_edid(edid, len); | ||
446 | |||
447 | if (need_enable) | ||
448 | hdmi_core_disable(dssdev); | ||
449 | |||
450 | return r; | ||
451 | } | ||
452 | |||
453 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
454 | static int hdmi_audio_enable(struct omap_dss_device *dssdev) | ||
455 | { | ||
456 | int r; | ||
457 | |||
458 | mutex_lock(&hdmi.lock); | ||
459 | |||
460 | if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) { | ||
461 | r = -EPERM; | ||
462 | goto err; | ||
463 | } | ||
464 | |||
465 | r = hdmi_wp_audio_enable(&hdmi.wp, true); | ||
466 | if (r) | ||
467 | goto err; | ||
468 | |||
469 | mutex_unlock(&hdmi.lock); | ||
470 | return 0; | ||
471 | |||
472 | err: | ||
473 | mutex_unlock(&hdmi.lock); | ||
474 | return r; | ||
475 | } | ||
476 | |||
477 | static void hdmi_audio_disable(struct omap_dss_device *dssdev) | ||
478 | { | ||
479 | hdmi_wp_audio_enable(&hdmi.wp, false); | ||
480 | } | ||
481 | |||
482 | static int hdmi_audio_start(struct omap_dss_device *dssdev) | ||
483 | { | ||
484 | return hdmi4_audio_start(&hdmi.core, &hdmi.wp); | ||
485 | } | ||
486 | |||
487 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) | ||
488 | { | ||
489 | hdmi4_audio_stop(&hdmi.core, &hdmi.wp); | ||
490 | } | ||
491 | |||
492 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) | ||
493 | { | ||
494 | bool r; | ||
495 | |||
496 | mutex_lock(&hdmi.lock); | ||
497 | |||
498 | r = hdmi_mode_has_audio(hdmi.cfg.cm.mode); | ||
499 | |||
500 | mutex_unlock(&hdmi.lock); | ||
501 | return r; | ||
502 | } | ||
503 | |||
504 | static int hdmi_audio_config(struct omap_dss_device *dssdev, | ||
505 | struct omap_dss_audio *audio) | ||
506 | { | ||
507 | int r; | ||
508 | u32 pclk = hdmi.cfg.timings.pixel_clock; | ||
509 | |||
510 | mutex_lock(&hdmi.lock); | ||
511 | |||
512 | if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) { | ||
513 | r = -EPERM; | ||
514 | goto err; | ||
515 | } | ||
516 | |||
517 | r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, audio, pclk); | ||
518 | if (r) | ||
519 | goto err; | ||
520 | |||
521 | mutex_unlock(&hdmi.lock); | ||
522 | return 0; | ||
523 | |||
524 | err: | ||
525 | mutex_unlock(&hdmi.lock); | ||
526 | return r; | ||
527 | } | ||
528 | #else | ||
529 | static int hdmi_audio_enable(struct omap_dss_device *dssdev) | ||
530 | { | ||
531 | return -EPERM; | ||
532 | } | ||
533 | |||
534 | static void hdmi_audio_disable(struct omap_dss_device *dssdev) | ||
535 | { | ||
536 | } | ||
537 | |||
538 | static int hdmi_audio_start(struct omap_dss_device *dssdev) | ||
539 | { | ||
540 | return -EPERM; | ||
541 | } | ||
542 | |||
543 | static void hdmi_audio_stop(struct omap_dss_device *dssdev) | ||
544 | { | ||
545 | } | ||
546 | |||
547 | static bool hdmi_audio_supported(struct omap_dss_device *dssdev) | ||
548 | { | ||
549 | return false; | ||
550 | } | ||
551 | |||
552 | static int hdmi_audio_config(struct omap_dss_device *dssdev, | ||
553 | struct omap_dss_audio *audio) | ||
554 | { | ||
555 | return -EPERM; | ||
556 | } | ||
557 | #endif | ||
558 | |||
559 | static const struct omapdss_hdmi_ops hdmi_ops = { | ||
560 | .connect = hdmi_connect, | ||
561 | .disconnect = hdmi_disconnect, | ||
562 | |||
563 | .enable = hdmi_display_enable, | ||
564 | .disable = hdmi_display_disable, | ||
565 | |||
566 | .check_timings = hdmi_display_check_timing, | ||
567 | .set_timings = hdmi_display_set_timing, | ||
568 | .get_timings = hdmi_display_get_timings, | ||
569 | |||
570 | .read_edid = hdmi_read_edid, | ||
571 | |||
572 | .audio_enable = hdmi_audio_enable, | ||
573 | .audio_disable = hdmi_audio_disable, | ||
574 | .audio_start = hdmi_audio_start, | ||
575 | .audio_stop = hdmi_audio_stop, | ||
576 | .audio_supported = hdmi_audio_supported, | ||
577 | .audio_config = hdmi_audio_config, | ||
578 | }; | ||
579 | |||
580 | static void hdmi_init_output(struct platform_device *pdev) | ||
581 | { | ||
582 | struct omap_dss_device *out = &hdmi.output; | ||
583 | |||
584 | out->dev = &pdev->dev; | ||
585 | out->id = OMAP_DSS_OUTPUT_HDMI; | ||
586 | out->output_type = OMAP_DISPLAY_TYPE_HDMI; | ||
587 | out->name = "hdmi.0"; | ||
588 | out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; | ||
589 | out->ops.hdmi = &hdmi_ops; | ||
590 | out->owner = THIS_MODULE; | ||
591 | |||
592 | omapdss_register_output(out); | ||
593 | } | ||
594 | |||
595 | static void __exit hdmi_uninit_output(struct platform_device *pdev) | ||
596 | { | ||
597 | struct omap_dss_device *out = &hdmi.output; | ||
598 | |||
599 | omapdss_unregister_output(out); | ||
600 | } | ||
601 | |||
602 | /* HDMI HW IP initialisation */ | ||
603 | static int omapdss_hdmihw_probe(struct platform_device *pdev) | ||
604 | { | ||
605 | int r; | ||
606 | |||
607 | hdmi.pdev = pdev; | ||
608 | |||
609 | mutex_init(&hdmi.lock); | ||
610 | |||
611 | r = hdmi_wp_init(pdev, &hdmi.wp); | ||
612 | if (r) | ||
613 | return r; | ||
614 | |||
615 | r = hdmi_pll_init(pdev, &hdmi.pll); | ||
616 | if (r) | ||
617 | return r; | ||
618 | |||
619 | r = hdmi_phy_init(pdev, &hdmi.phy); | ||
620 | if (r) | ||
621 | return r; | ||
622 | |||
623 | r = hdmi4_core_init(pdev, &hdmi.core); | ||
624 | if (r) | ||
625 | return r; | ||
626 | |||
627 | r = hdmi_get_clocks(pdev); | ||
628 | if (r) { | ||
629 | DSSERR("can't get clocks\n"); | ||
630 | return r; | ||
631 | } | ||
632 | |||
633 | pm_runtime_enable(&pdev->dev); | ||
634 | |||
635 | hdmi_init_output(pdev); | ||
636 | |||
637 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); | ||
638 | |||
639 | return 0; | ||
640 | } | ||
641 | |||
642 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) | ||
643 | { | ||
644 | hdmi_uninit_output(pdev); | ||
645 | |||
646 | pm_runtime_disable(&pdev->dev); | ||
647 | |||
648 | return 0; | ||
649 | } | ||
650 | |||
651 | static int hdmi_runtime_suspend(struct device *dev) | ||
652 | { | ||
653 | clk_disable_unprepare(hdmi.sys_clk); | ||
654 | |||
655 | dispc_runtime_put(); | ||
656 | |||
657 | return 0; | ||
658 | } | ||
659 | |||
660 | static int hdmi_runtime_resume(struct device *dev) | ||
661 | { | ||
662 | int r; | ||
663 | |||
664 | r = dispc_runtime_get(); | ||
665 | if (r < 0) | ||
666 | return r; | ||
667 | |||
668 | clk_prepare_enable(hdmi.sys_clk); | ||
669 | |||
670 | return 0; | ||
671 | } | ||
672 | |||
673 | static const struct dev_pm_ops hdmi_pm_ops = { | ||
674 | .runtime_suspend = hdmi_runtime_suspend, | ||
675 | .runtime_resume = hdmi_runtime_resume, | ||
676 | }; | ||
677 | |||
678 | static struct platform_driver omapdss_hdmihw_driver = { | ||
679 | .probe = omapdss_hdmihw_probe, | ||
680 | .remove = __exit_p(omapdss_hdmihw_remove), | ||
681 | .driver = { | ||
682 | .name = "omapdss_hdmi", | ||
683 | .owner = THIS_MODULE, | ||
684 | .pm = &hdmi_pm_ops, | ||
685 | }, | ||
686 | }; | ||
687 | |||
688 | int __init hdmi4_init_platform_driver(void) | ||
689 | { | ||
690 | return platform_driver_register(&omapdss_hdmihw_driver); | ||
691 | } | ||
692 | |||
693 | void __exit hdmi4_uninit_platform_driver(void) | ||
694 | { | ||
695 | platform_driver_unregister(&omapdss_hdmihw_driver); | ||
696 | } | ||
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/hdmi4_core.c index 3dfe00956a4f..5dd5e5489b41 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c +++ b/drivers/video/omap2/dss/hdmi4_core.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
27 | #include <linux/mutex.h> | 27 | #include <linux/mutex.h> |
28 | #include <linux/delay.h> | 28 | #include <linux/delay.h> |
29 | #include <linux/platform_device.h> | ||
29 | #include <linux/string.h> | 30 | #include <linux/string.h> |
30 | #include <linux/seq_file.h> | 31 | #include <linux/seq_file.h> |
31 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | 32 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
@@ -33,304 +34,19 @@ | |||
33 | #include <sound/asoundef.h> | 34 | #include <sound/asoundef.h> |
34 | #endif | 35 | #endif |
35 | 36 | ||
36 | #include "ti_hdmi_4xxx_ip.h" | 37 | #include "hdmi4_core.h" |
37 | #include "dss.h" | ||
38 | #include "dss_features.h" | 38 | #include "dss_features.h" |
39 | 39 | ||
40 | #define HDMI_IRQ_LINK_CONNECT (1 << 25) | 40 | #define HDMI_CORE_AV 0x500 |
41 | #define HDMI_IRQ_LINK_DISCONNECT (1 << 26) | ||
42 | 41 | ||
43 | static inline void hdmi_write_reg(void __iomem *base_addr, | 42 | static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core) |
44 | const u16 idx, u32 val) | ||
45 | { | 43 | { |
46 | __raw_writel(val, base_addr + idx); | 44 | return core->base + HDMI_CORE_AV; |
47 | } | 45 | } |
48 | 46 | ||
49 | static inline u32 hdmi_read_reg(void __iomem *base_addr, | 47 | static int hdmi_core_ddc_init(struct hdmi_core_data *core) |
50 | const u16 idx) | ||
51 | { | 48 | { |
52 | return __raw_readl(base_addr + idx); | 49 | void __iomem *base = core->base; |
53 | } | ||
54 | |||
55 | static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data) | ||
56 | { | ||
57 | return ip_data->base_wp; | ||
58 | } | ||
59 | |||
60 | static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data) | ||
61 | { | ||
62 | return ip_data->base_wp + ip_data->phy_offset; | ||
63 | } | ||
64 | |||
65 | static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data) | ||
66 | { | ||
67 | return ip_data->base_wp + ip_data->pll_offset; | ||
68 | } | ||
69 | |||
70 | static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data) | ||
71 | { | ||
72 | return ip_data->base_wp + ip_data->core_av_offset; | ||
73 | } | ||
74 | |||
75 | static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data) | ||
76 | { | ||
77 | return ip_data->base_wp + ip_data->core_sys_offset; | ||
78 | } | ||
79 | |||
80 | static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, | ||
81 | const u16 idx, | ||
82 | int b2, int b1, u32 val) | ||
83 | { | ||
84 | u32 t = 0; | ||
85 | while (val != REG_GET(base_addr, idx, b2, b1)) { | ||
86 | udelay(1); | ||
87 | if (t++ > 10000) | ||
88 | return !val; | ||
89 | } | ||
90 | return val; | ||
91 | } | ||
92 | |||
93 | static int hdmi_pll_init(struct hdmi_ip_data *ip_data) | ||
94 | { | ||
95 | u32 r; | ||
96 | void __iomem *pll_base = hdmi_pll_base(ip_data); | ||
97 | struct hdmi_pll_info *fmt = &ip_data->pll_data; | ||
98 | |||
99 | /* PLL start always use manual mode */ | ||
100 | REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); | ||
101 | |||
102 | r = hdmi_read_reg(pll_base, PLLCTRL_CFG1); | ||
103 | r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ | ||
104 | r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */ | ||
105 | |||
106 | hdmi_write_reg(pll_base, PLLCTRL_CFG1, r); | ||
107 | |||
108 | r = hdmi_read_reg(pll_base, PLLCTRL_CFG2); | ||
109 | |||
110 | r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ | ||
111 | r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ | ||
112 | r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ | ||
113 | r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */ | ||
114 | |||
115 | if (fmt->dcofreq) { | ||
116 | /* divider programming for frequency beyond 1000Mhz */ | ||
117 | REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); | ||
118 | r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ | ||
119 | } else { | ||
120 | r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ | ||
121 | } | ||
122 | |||
123 | hdmi_write_reg(pll_base, PLLCTRL_CFG2, r); | ||
124 | |||
125 | r = hdmi_read_reg(pll_base, PLLCTRL_CFG4); | ||
126 | r = FLD_MOD(r, fmt->regm2, 24, 18); | ||
127 | r = FLD_MOD(r, fmt->regmf, 17, 0); | ||
128 | |||
129 | hdmi_write_reg(pll_base, PLLCTRL_CFG4, r); | ||
130 | |||
131 | /* go now */ | ||
132 | REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0); | ||
133 | |||
134 | /* wait for bit change */ | ||
135 | if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO, | ||
136 | 0, 0, 1) != 1) { | ||
137 | pr_err("PLL GO bit not set\n"); | ||
138 | return -ETIMEDOUT; | ||
139 | } | ||
140 | |||
141 | /* Wait till the lock bit is set in PLL status */ | ||
142 | if (hdmi_wait_for_bit_change(pll_base, | ||
143 | PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { | ||
144 | pr_err("cannot lock PLL\n"); | ||
145 | pr_err("CFG1 0x%x\n", | ||
146 | hdmi_read_reg(pll_base, PLLCTRL_CFG1)); | ||
147 | pr_err("CFG2 0x%x\n", | ||
148 | hdmi_read_reg(pll_base, PLLCTRL_CFG2)); | ||
149 | pr_err("CFG4 0x%x\n", | ||
150 | hdmi_read_reg(pll_base, PLLCTRL_CFG4)); | ||
151 | return -ETIMEDOUT; | ||
152 | } | ||
153 | |||
154 | pr_debug("PLL locked!\n"); | ||
155 | |||
156 | return 0; | ||
157 | } | ||
158 | |||
159 | /* PHY_PWR_CMD */ | ||
160 | static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val) | ||
161 | { | ||
162 | /* Return if already the state */ | ||
163 | if (REG_GET(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, 5, 4) == val) | ||
164 | return 0; | ||
165 | |||
166 | /* Command for power control of HDMI PHY */ | ||
167 | REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6); | ||
168 | |||
169 | /* Status of the power control of HDMI PHY */ | ||
170 | if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), | ||
171 | HDMI_WP_PWR_CTRL, 5, 4, val) != val) { | ||
172 | pr_err("Failed to set PHY power mode to %d\n", val); | ||
173 | return -ETIMEDOUT; | ||
174 | } | ||
175 | |||
176 | return 0; | ||
177 | } | ||
178 | |||
179 | /* PLL_PWR_CMD */ | ||
180 | static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val) | ||
181 | { | ||
182 | /* Command for power control of HDMI PLL */ | ||
183 | REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2); | ||
184 | |||
185 | /* wait till PHY_PWR_STATUS is set */ | ||
186 | if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, | ||
187 | 1, 0, val) != val) { | ||
188 | pr_err("Failed to set PLL_PWR_STATUS\n"); | ||
189 | return -ETIMEDOUT; | ||
190 | } | ||
191 | |||
192 | return 0; | ||
193 | } | ||
194 | |||
195 | static int hdmi_pll_reset(struct hdmi_ip_data *ip_data) | ||
196 | { | ||
197 | /* SYSRESET controlled by power FSM */ | ||
198 | REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3); | ||
199 | |||
200 | /* READ 0x0 reset is in progress */ | ||
201 | if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data), | ||
202 | PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { | ||
203 | pr_err("Failed to sysreset PLL\n"); | ||
204 | return -ETIMEDOUT; | ||
205 | } | ||
206 | |||
207 | return 0; | ||
208 | } | ||
209 | |||
210 | int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data) | ||
211 | { | ||
212 | u16 r = 0; | ||
213 | |||
214 | r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); | ||
215 | if (r) | ||
216 | return r; | ||
217 | |||
218 | r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); | ||
219 | if (r) | ||
220 | return r; | ||
221 | |||
222 | r = hdmi_pll_reset(ip_data); | ||
223 | if (r) | ||
224 | return r; | ||
225 | |||
226 | r = hdmi_pll_init(ip_data); | ||
227 | if (r) | ||
228 | return r; | ||
229 | |||
230 | return 0; | ||
231 | } | ||
232 | |||
233 | void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data) | ||
234 | { | ||
235 | hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); | ||
236 | } | ||
237 | |||
238 | static irqreturn_t hdmi_irq_handler(int irq, void *data) | ||
239 | { | ||
240 | struct hdmi_ip_data *ip_data = data; | ||
241 | void __iomem *wp_base = hdmi_wp_base(ip_data); | ||
242 | u32 irqstatus; | ||
243 | |||
244 | irqstatus = hdmi_read_reg(wp_base, HDMI_WP_IRQSTATUS); | ||
245 | hdmi_write_reg(wp_base, HDMI_WP_IRQSTATUS, irqstatus); | ||
246 | /* flush posted write */ | ||
247 | hdmi_read_reg(wp_base, HDMI_WP_IRQSTATUS); | ||
248 | |||
249 | if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && | ||
250 | irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | ||
251 | /* | ||
252 | * If we get both connect and disconnect interrupts at the same | ||
253 | * time, turn off the PHY, clear interrupts, and restart, which | ||
254 | * raises connect interrupt if a cable is connected, or nothing | ||
255 | * if cable is not connected. | ||
256 | */ | ||
257 | hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); | ||
258 | |||
259 | hdmi_write_reg(wp_base, HDMI_WP_IRQSTATUS, | ||
260 | HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); | ||
261 | /* flush posted write */ | ||
262 | hdmi_read_reg(wp_base, HDMI_WP_IRQSTATUS); | ||
263 | |||
264 | hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); | ||
265 | } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { | ||
266 | hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON); | ||
267 | } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | ||
268 | hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); | ||
269 | } | ||
270 | |||
271 | return IRQ_HANDLED; | ||
272 | } | ||
273 | |||
274 | int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data) | ||
275 | { | ||
276 | u16 r = 0; | ||
277 | void __iomem *phy_base = hdmi_phy_base(ip_data); | ||
278 | |||
279 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_IRQENABLE_CLR, | ||
280 | 0xffffffff); | ||
281 | |||
282 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_IRQSTATUS, | ||
283 | HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); | ||
284 | |||
285 | r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); | ||
286 | if (r) | ||
287 | return r; | ||
288 | |||
289 | /* | ||
290 | * Read address 0 in order to get the SCP reset done completed | ||
291 | * Dummy access performed to make sure reset is done | ||
292 | */ | ||
293 | hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL); | ||
294 | |||
295 | /* | ||
296 | * Write to phy address 0 to configure the clock | ||
297 | * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field | ||
298 | */ | ||
299 | REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); | ||
300 | |||
301 | /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ | ||
302 | hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); | ||
303 | |||
304 | /* Setup max LDO voltage */ | ||
305 | REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); | ||
306 | |||
307 | /* Write to phy address 3 to change the polarity control */ | ||
308 | REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); | ||
309 | |||
310 | r = request_threaded_irq(ip_data->irq, NULL, hdmi_irq_handler, | ||
311 | IRQF_ONESHOT, "OMAP HDMI", ip_data); | ||
312 | if (r) { | ||
313 | DSSERR("HDMI IRQ request failed\n"); | ||
314 | hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); | ||
315 | return r; | ||
316 | } | ||
317 | |||
318 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_IRQENABLE_SET, | ||
319 | HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); | ||
320 | |||
321 | return 0; | ||
322 | } | ||
323 | |||
324 | void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data) | ||
325 | { | ||
326 | free_irq(ip_data->irq, ip_data); | ||
327 | |||
328 | hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); | ||
329 | } | ||
330 | |||
331 | static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data) | ||
332 | { | ||
333 | void __iomem *base = hdmi_core_sys_base(ip_data); | ||
334 | 50 | ||
335 | /* Turn on CLK for DDC */ | 51 | /* Turn on CLK for DDC */ |
336 | REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); | 52 | REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); |
@@ -370,10 +86,10 @@ static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data) | |||
370 | return 0; | 86 | return 0; |
371 | } | 87 | } |
372 | 88 | ||
373 | static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data, | 89 | static int hdmi_core_ddc_edid(struct hdmi_core_data *core, |
374 | u8 *pedid, int ext) | 90 | u8 *pedid, int ext) |
375 | { | 91 | { |
376 | void __iomem *base = hdmi_core_sys_base(ip_data); | 92 | void __iomem *base = core->base; |
377 | u32 i; | 93 | u32 i; |
378 | char checksum; | 94 | char checksum; |
379 | u32 offset = 0; | 95 | u32 offset = 0; |
@@ -452,26 +168,25 @@ static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data, | |||
452 | return 0; | 168 | return 0; |
453 | } | 169 | } |
454 | 170 | ||
455 | int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, | 171 | int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) |
456 | u8 *edid, int len) | ||
457 | { | 172 | { |
458 | int r, l; | 173 | int r, l; |
459 | 174 | ||
460 | if (len < 128) | 175 | if (len < 128) |
461 | return -EINVAL; | 176 | return -EINVAL; |
462 | 177 | ||
463 | r = hdmi_core_ddc_init(ip_data); | 178 | r = hdmi_core_ddc_init(core); |
464 | if (r) | 179 | if (r) |
465 | return r; | 180 | return r; |
466 | 181 | ||
467 | r = hdmi_core_ddc_edid(ip_data, edid, 0); | 182 | r = hdmi_core_ddc_edid(core, edid, 0); |
468 | if (r) | 183 | if (r) |
469 | return r; | 184 | return r; |
470 | 185 | ||
471 | l = 128; | 186 | l = 128; |
472 | 187 | ||
473 | if (len >= 128 * 2 && edid[0x7e] > 0) { | 188 | if (len >= 128 * 2 && edid[0x7e] > 0) { |
474 | r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1); | 189 | r = hdmi_core_ddc_edid(core, edid + 0x80, 1); |
475 | if (r) | 190 | if (r) |
476 | return r; | 191 | return r; |
477 | l += 128; | 192 | l += 128; |
@@ -508,7 +223,7 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | |||
508 | avi_cfg->db3_nup_scaling = 0; | 223 | avi_cfg->db3_nup_scaling = 0; |
509 | avi_cfg->db4_videocode = 0; | 224 | avi_cfg->db4_videocode = 0; |
510 | avi_cfg->db5_pixel_repeat = 0; | 225 | avi_cfg->db5_pixel_repeat = 0; |
511 | avi_cfg->db6_7_line_eoftop = 0 ; | 226 | avi_cfg->db6_7_line_eoftop = 0; |
512 | avi_cfg->db8_9_line_sofbottom = 0; | 227 | avi_cfg->db8_9_line_sofbottom = 0; |
513 | avi_cfg->db10_11_pixel_eofleft = 0; | 228 | avi_cfg->db10_11_pixel_eofleft = 0; |
514 | avi_cfg->db12_13_pixel_sofright = 0; | 229 | avi_cfg->db12_13_pixel_sofright = 0; |
@@ -524,38 +239,39 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | |||
524 | repeat_cfg->generic_pkt_repeat = 0; | 239 | repeat_cfg->generic_pkt_repeat = 0; |
525 | } | 240 | } |
526 | 241 | ||
527 | static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data) | 242 | static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) |
528 | { | 243 | { |
529 | pr_debug("Enter hdmi_core_powerdown_disable\n"); | 244 | pr_debug("Enter hdmi_core_powerdown_disable\n"); |
530 | REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0); | 245 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); |
531 | } | 246 | } |
532 | 247 | ||
533 | static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data) | 248 | static void hdmi_core_swreset_release(struct hdmi_core_data *core) |
534 | { | 249 | { |
535 | pr_debug("Enter hdmi_core_swreset_release\n"); | 250 | pr_debug("Enter hdmi_core_swreset_release\n"); |
536 | REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0); | 251 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); |
537 | } | 252 | } |
538 | 253 | ||
539 | static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data) | 254 | static void hdmi_core_swreset_assert(struct hdmi_core_data *core) |
540 | { | 255 | { |
541 | pr_debug("Enter hdmi_core_swreset_assert\n"); | 256 | pr_debug("Enter hdmi_core_swreset_assert\n"); |
542 | REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0); | 257 | REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); |
543 | } | 258 | } |
544 | 259 | ||
545 | /* HDMI_CORE_VIDEO_CONFIG */ | 260 | /* HDMI_CORE_VIDEO_CONFIG */ |
546 | static void hdmi_core_video_config(struct hdmi_ip_data *ip_data, | 261 | static void hdmi_core_video_config(struct hdmi_core_data *core, |
547 | struct hdmi_core_video_config *cfg) | 262 | struct hdmi_core_video_config *cfg) |
548 | { | 263 | { |
549 | u32 r = 0; | 264 | u32 r = 0; |
550 | void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); | 265 | void __iomem *core_sys_base = core->base; |
266 | void __iomem *core_av_base = hdmi_av_base(core); | ||
551 | 267 | ||
552 | /* sys_ctrl1 default configuration not tunable */ | 268 | /* sys_ctrl1 default configuration not tunable */ |
553 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1); | 269 | r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); |
554 | r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); | 270 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5); |
555 | r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); | 271 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4); |
556 | r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); | 272 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2); |
557 | r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); | 273 | r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1); |
558 | hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r); | 274 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r); |
559 | 275 | ||
560 | REG_FLD_MOD(core_sys_base, | 276 | REG_FLD_MOD(core_sys_base, |
561 | HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); | 277 | HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); |
@@ -574,23 +290,23 @@ static void hdmi_core_video_config(struct hdmi_ip_data *ip_data, | |||
574 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); | 290 | hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); |
575 | 291 | ||
576 | /* HDMI_Ctrl */ | 292 | /* HDMI_Ctrl */ |
577 | r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL); | 293 | r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); |
578 | r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); | 294 | r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); |
579 | r = FLD_MOD(r, cfg->pkt_mode, 5, 3); | 295 | r = FLD_MOD(r, cfg->pkt_mode, 5, 3); |
580 | r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); | 296 | r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); |
581 | hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r); | 297 | hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r); |
582 | 298 | ||
583 | /* TMDS_CTRL */ | 299 | /* TMDS_CTRL */ |
584 | REG_FLD_MOD(core_sys_base, | 300 | REG_FLD_MOD(core_sys_base, |
585 | HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); | 301 | HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); |
586 | } | 302 | } |
587 | 303 | ||
588 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data) | 304 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core) |
589 | { | 305 | { |
590 | u32 val; | 306 | u32 val; |
591 | char sum = 0, checksum = 0; | 307 | char sum = 0, checksum = 0; |
592 | void __iomem *av_base = hdmi_av_base(ip_data); | 308 | void __iomem *av_base = hdmi_av_base(core); |
593 | struct hdmi_core_infoframe_avi info_avi = ip_data->avi_cfg; | 309 | struct hdmi_core_infoframe_avi info_avi = core->avi_cfg; |
594 | 310 | ||
595 | sum += 0x82 + 0x002 + 0x00D; | 311 | sum += 0x82 + 0x002 + 0x00D; |
596 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); | 312 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); |
@@ -661,160 +377,64 @@ static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data) | |||
661 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); | 377 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); |
662 | } | 378 | } |
663 | 379 | ||
664 | static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data, | 380 | static void hdmi_core_av_packet_config(struct hdmi_core_data *core, |
665 | struct hdmi_core_packet_enable_repeat repeat_cfg) | 381 | struct hdmi_core_packet_enable_repeat repeat_cfg) |
666 | { | 382 | { |
667 | /* enable/repeat the infoframe */ | 383 | /* enable/repeat the infoframe */ |
668 | hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1, | 384 | hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1, |
669 | (repeat_cfg.audio_pkt << 5) | | 385 | (repeat_cfg.audio_pkt << 5) | |
670 | (repeat_cfg.audio_pkt_repeat << 4) | | 386 | (repeat_cfg.audio_pkt_repeat << 4) | |
671 | (repeat_cfg.avi_infoframe << 1) | | 387 | (repeat_cfg.avi_infoframe << 1) | |
672 | (repeat_cfg.avi_infoframe_repeat)); | 388 | (repeat_cfg.avi_infoframe_repeat)); |
673 | 389 | ||
674 | /* enable/repeat the packet */ | 390 | /* enable/repeat the packet */ |
675 | hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2, | 391 | hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2, |
676 | (repeat_cfg.gen_cntrl_pkt << 3) | | 392 | (repeat_cfg.gen_cntrl_pkt << 3) | |
677 | (repeat_cfg.gen_cntrl_pkt_repeat << 2) | | 393 | (repeat_cfg.gen_cntrl_pkt_repeat << 2) | |
678 | (repeat_cfg.generic_pkt << 1) | | 394 | (repeat_cfg.generic_pkt << 1) | |
679 | (repeat_cfg.generic_pkt_repeat)); | 395 | (repeat_cfg.generic_pkt_repeat)); |
680 | } | 396 | } |
681 | 397 | ||
682 | static void hdmi_wp_init(struct omap_video_timings *timings, | 398 | void hdmi4_configure(struct hdmi_core_data *core, |
683 | struct hdmi_video_format *video_fmt) | 399 | struct hdmi_wp_data *wp, struct hdmi_config *cfg) |
684 | { | ||
685 | pr_debug("Enter hdmi_wp_init\n"); | ||
686 | |||
687 | timings->hbp = 0; | ||
688 | timings->hfp = 0; | ||
689 | timings->hsw = 0; | ||
690 | timings->vbp = 0; | ||
691 | timings->vfp = 0; | ||
692 | timings->vsw = 0; | ||
693 | |||
694 | video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; | ||
695 | video_fmt->y_res = 0; | ||
696 | video_fmt->x_res = 0; | ||
697 | |||
698 | } | ||
699 | |||
700 | int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data) | ||
701 | { | ||
702 | REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, true, 31, 31); | ||
703 | return 0; | ||
704 | } | ||
705 | |||
706 | void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data) | ||
707 | { | ||
708 | REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, false, 31, 31); | ||
709 | } | ||
710 | |||
711 | static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, | ||
712 | struct omap_video_timings *timings, struct hdmi_config *param) | ||
713 | { | ||
714 | pr_debug("Enter hdmi_wp_video_init_format\n"); | ||
715 | |||
716 | video_fmt->y_res = param->timings.y_res; | ||
717 | video_fmt->x_res = param->timings.x_res; | ||
718 | |||
719 | timings->hbp = param->timings.hbp; | ||
720 | timings->hfp = param->timings.hfp; | ||
721 | timings->hsw = param->timings.hsw; | ||
722 | timings->vbp = param->timings.vbp; | ||
723 | timings->vfp = param->timings.vfp; | ||
724 | timings->vsw = param->timings.vsw; | ||
725 | } | ||
726 | |||
727 | static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data, | ||
728 | struct hdmi_video_format *video_fmt) | ||
729 | { | ||
730 | u32 l = 0; | ||
731 | |||
732 | REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, | ||
733 | video_fmt->packing_mode, 10, 8); | ||
734 | |||
735 | l |= FLD_VAL(video_fmt->y_res, 31, 16); | ||
736 | l |= FLD_VAL(video_fmt->x_res, 15, 0); | ||
737 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l); | ||
738 | } | ||
739 | |||
740 | static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data) | ||
741 | { | ||
742 | u32 r; | ||
743 | bool vsync_pol, hsync_pol; | ||
744 | pr_debug("Enter hdmi_wp_video_config_interface\n"); | ||
745 | |||
746 | vsync_pol = ip_data->cfg.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; | ||
747 | hsync_pol = ip_data->cfg.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; | ||
748 | |||
749 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); | ||
750 | r = FLD_MOD(r, vsync_pol, 7, 7); | ||
751 | r = FLD_MOD(r, hsync_pol, 6, 6); | ||
752 | r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3); | ||
753 | r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ | ||
754 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); | ||
755 | } | ||
756 | |||
757 | static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data, | ||
758 | struct omap_video_timings *timings) | ||
759 | { | ||
760 | u32 timing_h = 0; | ||
761 | u32 timing_v = 0; | ||
762 | |||
763 | pr_debug("Enter hdmi_wp_video_config_timing\n"); | ||
764 | |||
765 | timing_h |= FLD_VAL(timings->hbp, 31, 20); | ||
766 | timing_h |= FLD_VAL(timings->hfp, 19, 8); | ||
767 | timing_h |= FLD_VAL(timings->hsw, 7, 0); | ||
768 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h); | ||
769 | |||
770 | timing_v |= FLD_VAL(timings->vbp, 31, 20); | ||
771 | timing_v |= FLD_VAL(timings->vfp, 19, 8); | ||
772 | timing_v |= FLD_VAL(timings->vsw, 7, 0); | ||
773 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); | ||
774 | } | ||
775 | |||
776 | void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data) | ||
777 | { | 400 | { |
778 | /* HDMI */ | 401 | /* HDMI */ |
779 | struct omap_video_timings video_timing; | 402 | struct omap_video_timings video_timing; |
780 | struct hdmi_video_format video_format; | 403 | struct hdmi_video_format video_format; |
781 | /* HDMI core */ | 404 | /* HDMI core */ |
782 | struct hdmi_core_infoframe_avi *avi_cfg = &ip_data->avi_cfg; | 405 | struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg; |
783 | struct hdmi_core_video_config v_core_cfg; | 406 | struct hdmi_core_video_config v_core_cfg; |
784 | struct hdmi_core_packet_enable_repeat repeat_cfg; | 407 | struct hdmi_core_packet_enable_repeat repeat_cfg; |
785 | struct hdmi_config *cfg = &ip_data->cfg; | ||
786 | |||
787 | hdmi_wp_init(&video_timing, &video_format); | ||
788 | 408 | ||
789 | hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg); | 409 | hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg); |
790 | 410 | ||
791 | hdmi_wp_video_init_format(&video_format, &video_timing, cfg); | 411 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); |
792 | 412 | ||
793 | hdmi_wp_video_config_timing(ip_data, &video_timing); | 413 | hdmi_wp_video_config_timing(wp, &video_timing); |
794 | 414 | ||
795 | /* video config */ | 415 | /* video config */ |
796 | video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; | 416 | video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; |
797 | 417 | ||
798 | hdmi_wp_video_config_format(ip_data, &video_format); | 418 | hdmi_wp_video_config_format(wp, &video_format); |
799 | 419 | ||
800 | hdmi_wp_video_config_interface(ip_data); | 420 | hdmi_wp_video_config_interface(wp, &video_timing); |
801 | 421 | ||
802 | /* | 422 | /* |
803 | * configure core video part | 423 | * configure core video part |
804 | * set software reset in the core | 424 | * set software reset in the core |
805 | */ | 425 | */ |
806 | hdmi_core_swreset_assert(ip_data); | 426 | hdmi_core_swreset_assert(core); |
807 | 427 | ||
808 | /* power down off */ | 428 | /* power down off */ |
809 | hdmi_core_powerdown_disable(ip_data); | 429 | hdmi_core_powerdown_disable(core); |
810 | 430 | ||
811 | v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; | 431 | v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; |
812 | v_core_cfg.hdmi_dvi = cfg->cm.mode; | 432 | v_core_cfg.hdmi_dvi = cfg->cm.mode; |
813 | 433 | ||
814 | hdmi_core_video_config(ip_data, &v_core_cfg); | 434 | hdmi_core_video_config(core, &v_core_cfg); |
815 | 435 | ||
816 | /* release software reset in the core */ | 436 | /* release software reset in the core */ |
817 | hdmi_core_swreset_release(ip_data); | 437 | hdmi_core_swreset_release(core); |
818 | 438 | ||
819 | /* | 439 | /* |
820 | * configure packet | 440 | * configure packet |
@@ -839,7 +459,7 @@ void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data) | |||
839 | avi_cfg->db10_11_pixel_eofleft = 0; | 459 | avi_cfg->db10_11_pixel_eofleft = 0; |
840 | avi_cfg->db12_13_pixel_sofright = 0; | 460 | avi_cfg->db12_13_pixel_sofright = 0; |
841 | 461 | ||
842 | hdmi_core_aux_infoframe_avi_config(ip_data); | 462 | hdmi_core_aux_infoframe_avi_config(core); |
843 | 463 | ||
844 | /* enable/repeat the infoframe */ | 464 | /* enable/repeat the infoframe */ |
845 | repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; | 465 | repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; |
@@ -847,65 +467,30 @@ void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data) | |||
847 | /* wakeup */ | 467 | /* wakeup */ |
848 | repeat_cfg.audio_pkt = HDMI_PACKETENABLE; | 468 | repeat_cfg.audio_pkt = HDMI_PACKETENABLE; |
849 | repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; | 469 | repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; |
850 | hdmi_core_av_packet_config(ip_data, repeat_cfg); | 470 | hdmi_core_av_packet_config(core, repeat_cfg); |
851 | } | ||
852 | |||
853 | void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) | ||
854 | { | ||
855 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\ | ||
856 | hdmi_read_reg(hdmi_wp_base(ip_data), r)) | ||
857 | |||
858 | DUMPREG(HDMI_WP_REVISION); | ||
859 | DUMPREG(HDMI_WP_SYSCONFIG); | ||
860 | DUMPREG(HDMI_WP_IRQSTATUS_RAW); | ||
861 | DUMPREG(HDMI_WP_IRQSTATUS); | ||
862 | DUMPREG(HDMI_WP_PWR_CTRL); | ||
863 | DUMPREG(HDMI_WP_IRQENABLE_SET); | ||
864 | DUMPREG(HDMI_WP_VIDEO_CFG); | ||
865 | DUMPREG(HDMI_WP_VIDEO_SIZE); | ||
866 | DUMPREG(HDMI_WP_VIDEO_TIMING_H); | ||
867 | DUMPREG(HDMI_WP_VIDEO_TIMING_V); | ||
868 | DUMPREG(HDMI_WP_WP_CLK); | ||
869 | DUMPREG(HDMI_WP_AUDIO_CFG); | ||
870 | DUMPREG(HDMI_WP_AUDIO_CFG2); | ||
871 | DUMPREG(HDMI_WP_AUDIO_CTRL); | ||
872 | DUMPREG(HDMI_WP_AUDIO_DATA); | ||
873 | } | ||
874 | |||
875 | void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) | ||
876 | { | ||
877 | #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ | ||
878 | hdmi_read_reg(hdmi_pll_base(ip_data), r)) | ||
879 | |||
880 | DUMPPLL(PLLCTRL_PLL_CONTROL); | ||
881 | DUMPPLL(PLLCTRL_PLL_STATUS); | ||
882 | DUMPPLL(PLLCTRL_PLL_GO); | ||
883 | DUMPPLL(PLLCTRL_CFG1); | ||
884 | DUMPPLL(PLLCTRL_CFG2); | ||
885 | DUMPPLL(PLLCTRL_CFG3); | ||
886 | DUMPPLL(PLLCTRL_CFG4); | ||
887 | } | 471 | } |
888 | 472 | ||
889 | void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) | 473 | void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s) |
890 | { | 474 | { |
891 | int i; | 475 | int i; |
892 | 476 | ||
893 | #define CORE_REG(i, name) name(i) | 477 | #define CORE_REG(i, name) name(i) |
894 | #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ | 478 | #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ |
895 | hdmi_read_reg(hdmi_core_sys_base(ip_data), r)) | 479 | hdmi_read_reg(core->base, r)) |
896 | #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ | 480 | #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ |
897 | hdmi_read_reg(hdmi_av_base(ip_data), r)) | 481 | hdmi_read_reg(hdmi_av_base(core), r)) |
898 | #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ | 482 | #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ |
899 | (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ | 483 | (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ |
900 | hdmi_read_reg(hdmi_av_base(ip_data), CORE_REG(i, r))) | 484 | hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) |
901 | 485 | ||
902 | DUMPCORE(HDMI_CORE_SYS_VND_IDL); | 486 | DUMPCORE(HDMI_CORE_SYS_VND_IDL); |
903 | DUMPCORE(HDMI_CORE_SYS_DEV_IDL); | 487 | DUMPCORE(HDMI_CORE_SYS_DEV_IDL); |
904 | DUMPCORE(HDMI_CORE_SYS_DEV_IDH); | 488 | DUMPCORE(HDMI_CORE_SYS_DEV_IDH); |
905 | DUMPCORE(HDMI_CORE_SYS_DEV_REV); | 489 | DUMPCORE(HDMI_CORE_SYS_DEV_REV); |
906 | DUMPCORE(HDMI_CORE_SYS_SRST); | 490 | DUMPCORE(HDMI_CORE_SYS_SRST); |
907 | DUMPCORE(HDMI_CORE_CTRL1); | 491 | DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1); |
908 | DUMPCORE(HDMI_CORE_SYS_SYS_STAT); | 492 | DUMPCORE(HDMI_CORE_SYS_SYS_STAT); |
493 | DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3); | ||
909 | DUMPCORE(HDMI_CORE_SYS_DE_DLY); | 494 | DUMPCORE(HDMI_CORE_SYS_DE_DLY); |
910 | DUMPCORE(HDMI_CORE_SYS_DE_CTRL); | 495 | DUMPCORE(HDMI_CORE_SYS_DE_CTRL); |
911 | DUMPCORE(HDMI_CORE_SYS_DE_TOP); | 496 | DUMPCORE(HDMI_CORE_SYS_DE_TOP); |
@@ -913,14 +498,58 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) | |||
913 | DUMPCORE(HDMI_CORE_SYS_DE_CNTH); | 498 | DUMPCORE(HDMI_CORE_SYS_DE_CNTH); |
914 | DUMPCORE(HDMI_CORE_SYS_DE_LINL); | 499 | DUMPCORE(HDMI_CORE_SYS_DE_LINL); |
915 | DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); | 500 | DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); |
501 | DUMPCORE(HDMI_CORE_SYS_HRES_L); | ||
502 | DUMPCORE(HDMI_CORE_SYS_HRES_H); | ||
503 | DUMPCORE(HDMI_CORE_SYS_VRES_L); | ||
504 | DUMPCORE(HDMI_CORE_SYS_VRES_H); | ||
505 | DUMPCORE(HDMI_CORE_SYS_IADJUST); | ||
506 | DUMPCORE(HDMI_CORE_SYS_POLDETECT); | ||
507 | DUMPCORE(HDMI_CORE_SYS_HWIDTH1); | ||
508 | DUMPCORE(HDMI_CORE_SYS_HWIDTH2); | ||
509 | DUMPCORE(HDMI_CORE_SYS_VWIDTH); | ||
510 | DUMPCORE(HDMI_CORE_SYS_VID_CTRL); | ||
916 | DUMPCORE(HDMI_CORE_SYS_VID_ACEN); | 511 | DUMPCORE(HDMI_CORE_SYS_VID_ACEN); |
917 | DUMPCORE(HDMI_CORE_SYS_VID_MODE); | 512 | DUMPCORE(HDMI_CORE_SYS_VID_MODE); |
513 | DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); | ||
514 | DUMPCORE(HDMI_CORE_SYS_VID_BLANK3); | ||
515 | DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); | ||
516 | DUMPCORE(HDMI_CORE_SYS_DC_HEADER); | ||
517 | DUMPCORE(HDMI_CORE_SYS_VID_DITHER); | ||
518 | DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT); | ||
519 | DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW); | ||
520 | DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP); | ||
521 | DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW); | ||
522 | DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP); | ||
523 | DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW); | ||
524 | DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP); | ||
525 | DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW); | ||
526 | DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP); | ||
527 | DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW); | ||
528 | DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP); | ||
529 | DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW); | ||
530 | DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP); | ||
531 | DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW); | ||
532 | DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP); | ||
533 | DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW); | ||
534 | DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP); | ||
535 | DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW); | ||
536 | DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP); | ||
537 | DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW); | ||
538 | DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP); | ||
539 | DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW); | ||
540 | DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP); | ||
541 | DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW); | ||
542 | DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP); | ||
918 | DUMPCORE(HDMI_CORE_SYS_INTR_STATE); | 543 | DUMPCORE(HDMI_CORE_SYS_INTR_STATE); |
919 | DUMPCORE(HDMI_CORE_SYS_INTR1); | 544 | DUMPCORE(HDMI_CORE_SYS_INTR1); |
920 | DUMPCORE(HDMI_CORE_SYS_INTR2); | 545 | DUMPCORE(HDMI_CORE_SYS_INTR2); |
921 | DUMPCORE(HDMI_CORE_SYS_INTR3); | 546 | DUMPCORE(HDMI_CORE_SYS_INTR3); |
922 | DUMPCORE(HDMI_CORE_SYS_INTR4); | 547 | DUMPCORE(HDMI_CORE_SYS_INTR4); |
923 | DUMPCORE(HDMI_CORE_SYS_UMASK1); | 548 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1); |
549 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2); | ||
550 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3); | ||
551 | DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4); | ||
552 | DUMPCORE(HDMI_CORE_SYS_INTR_CTRL); | ||
924 | DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL); | 553 | DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL); |
925 | 554 | ||
926 | DUMPCORE(HDMI_CORE_DDC_ADDR); | 555 | DUMPCORE(HDMI_CORE_DDC_ADDR); |
@@ -1009,60 +638,12 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) | |||
1009 | DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID); | 638 | DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID); |
1010 | } | 639 | } |
1011 | 640 | ||
1012 | void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) | ||
1013 | { | ||
1014 | #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\ | ||
1015 | hdmi_read_reg(hdmi_phy_base(ip_data), r)) | ||
1016 | |||
1017 | DUMPPHY(HDMI_TXPHY_TX_CTRL); | ||
1018 | DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL); | ||
1019 | DUMPPHY(HDMI_TXPHY_POWER_CTRL); | ||
1020 | DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL); | ||
1021 | } | ||
1022 | |||
1023 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | 641 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
1024 | static void ti_hdmi_4xxx_wp_audio_config_format(struct hdmi_ip_data *ip_data, | 642 | static void hdmi_core_audio_config(struct hdmi_core_data *core, |
1025 | struct hdmi_audio_format *aud_fmt) | ||
1026 | { | ||
1027 | u32 r; | ||
1028 | |||
1029 | DSSDBG("Enter hdmi_wp_audio_config_format\n"); | ||
1030 | |||
1031 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG); | ||
1032 | r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); | ||
1033 | r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); | ||
1034 | r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); | ||
1035 | r = FLD_MOD(r, aud_fmt->type, 4, 4); | ||
1036 | r = FLD_MOD(r, aud_fmt->justification, 3, 3); | ||
1037 | r = FLD_MOD(r, aud_fmt->sample_order, 2, 2); | ||
1038 | r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1); | ||
1039 | r = FLD_MOD(r, aud_fmt->sample_size, 0, 0); | ||
1040 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r); | ||
1041 | } | ||
1042 | |||
1043 | static void ti_hdmi_4xxx_wp_audio_config_dma(struct hdmi_ip_data *ip_data, | ||
1044 | struct hdmi_audio_dma *aud_dma) | ||
1045 | { | ||
1046 | u32 r; | ||
1047 | |||
1048 | DSSDBG("Enter hdmi_wp_audio_config_dma\n"); | ||
1049 | |||
1050 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2); | ||
1051 | r = FLD_MOD(r, aud_dma->transfer_size, 15, 8); | ||
1052 | r = FLD_MOD(r, aud_dma->block_size, 7, 0); | ||
1053 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r); | ||
1054 | |||
1055 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL); | ||
1056 | r = FLD_MOD(r, aud_dma->mode, 9, 9); | ||
1057 | r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0); | ||
1058 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r); | ||
1059 | } | ||
1060 | |||
1061 | static void ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data *ip_data, | ||
1062 | struct hdmi_core_audio_config *cfg) | 643 | struct hdmi_core_audio_config *cfg) |
1063 | { | 644 | { |
1064 | u32 r; | 645 | u32 r; |
1065 | void __iomem *av_base = hdmi_av_base(ip_data); | 646 | void __iomem *av_base = hdmi_av_base(core); |
1066 | 647 | ||
1067 | /* | 648 | /* |
1068 | * Parameters for generation of Audio Clock Recovery packets | 649 | * Parameters for generation of Audio Clock Recovery packets |
@@ -1157,11 +738,11 @@ static void ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data *ip_data, | |||
1157 | REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); | 738 | REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); |
1158 | } | 739 | } |
1159 | 740 | ||
1160 | static void ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data *ip_data, | 741 | static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core, |
1161 | struct snd_cea_861_aud_if *info_aud) | 742 | struct snd_cea_861_aud_if *info_aud) |
1162 | { | 743 | { |
1163 | u8 sum = 0, checksum = 0; | 744 | u8 sum = 0, checksum = 0; |
1164 | void __iomem *av_base = hdmi_av_base(ip_data); | 745 | void __iomem *av_base = hdmi_av_base(core); |
1165 | 746 | ||
1166 | /* | 747 | /* |
1167 | * Set audio info frame type, version and length as | 748 | * Set audio info frame type, version and length as |
@@ -1207,20 +788,20 @@ static void ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data *ip_data, | |||
1207 | */ | 788 | */ |
1208 | } | 789 | } |
1209 | 790 | ||
1210 | int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | 791 | int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, |
1211 | struct omap_dss_audio *audio) | 792 | struct omap_dss_audio *audio, u32 pclk) |
1212 | { | 793 | { |
1213 | struct hdmi_audio_format audio_format; | 794 | struct hdmi_audio_format audio_format; |
1214 | struct hdmi_audio_dma audio_dma; | 795 | struct hdmi_audio_dma audio_dma; |
1215 | struct hdmi_core_audio_config core; | 796 | struct hdmi_core_audio_config acore; |
1216 | int err, n, cts, channel_count; | 797 | int err, n, cts, channel_count; |
1217 | unsigned int fs_nr; | 798 | unsigned int fs_nr; |
1218 | bool word_length_16b = false; | 799 | bool word_length_16b = false; |
1219 | 800 | ||
1220 | if (!audio || !audio->iec || !audio->cea || !ip_data) | 801 | if (!audio || !audio->iec || !audio->cea || !core) |
1221 | return -EINVAL; | 802 | return -EINVAL; |
1222 | 803 | ||
1223 | core.iec60958_cfg = audio->iec; | 804 | acore.iec60958_cfg = audio->iec; |
1224 | /* | 805 | /* |
1225 | * In the IEC-60958 status word, check if the audio sample word length | 806 | * In the IEC-60958 status word, check if the audio sample word length |
1226 | * is 16-bit as several optimizations can be performed in such case. | 807 | * is 16-bit as several optimizations can be performed in such case. |
@@ -1231,22 +812,22 @@ int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | |||
1231 | 812 | ||
1232 | /* I2S configuration. See Phillips' specification */ | 813 | /* I2S configuration. See Phillips' specification */ |
1233 | if (word_length_16b) | 814 | if (word_length_16b) |
1234 | core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; | 815 | acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
1235 | else | 816 | else |
1236 | core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; | 817 | acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
1237 | /* | 818 | /* |
1238 | * The I2S input word length is twice the lenght given in the IEC-60958 | 819 | * The I2S input word length is twice the lenght given in the IEC-60958 |
1239 | * status word. If the word size is greater than | 820 | * status word. If the word size is greater than |
1240 | * 20 bits, increment by one. | 821 | * 20 bits, increment by one. |
1241 | */ | 822 | */ |
1242 | core.i2s_cfg.in_length_bits = audio->iec->status[4] | 823 | acore.i2s_cfg.in_length_bits = audio->iec->status[4] |
1243 | & IEC958_AES4_CON_WORDLEN; | 824 | & IEC958_AES4_CON_WORDLEN; |
1244 | if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) | 825 | if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) |
1245 | core.i2s_cfg.in_length_bits++; | 826 | acore.i2s_cfg.in_length_bits++; |
1246 | core.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; | 827 | acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; |
1247 | core.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; | 828 | acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; |
1248 | core.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; | 829 | acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; |
1249 | core.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; | 830 | acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; |
1250 | 831 | ||
1251 | /* convert sample frequency to a number */ | 832 | /* convert sample frequency to a number */ |
1252 | switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { | 833 | switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { |
@@ -1275,23 +856,23 @@ int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | |||
1275 | return -EINVAL; | 856 | return -EINVAL; |
1276 | } | 857 | } |
1277 | 858 | ||
1278 | err = hdmi_compute_acr(fs_nr, &n, &cts); | 859 | err = hdmi_compute_acr(pclk, fs_nr, &n, &cts); |
1279 | 860 | ||
1280 | /* Audio clock regeneration settings */ | 861 | /* Audio clock regeneration settings */ |
1281 | core.n = n; | 862 | acore.n = n; |
1282 | core.cts = cts; | 863 | acore.cts = cts; |
1283 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { | 864 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { |
1284 | core.aud_par_busclk = 0; | 865 | acore.aud_par_busclk = 0; |
1285 | core.cts_mode = HDMI_AUDIO_CTS_MODE_SW; | 866 | acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW; |
1286 | core.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK); | 867 | acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK); |
1287 | } else { | 868 | } else { |
1288 | core.aud_par_busclk = (((128 * 31) - 1) << 8); | 869 | acore.aud_par_busclk = (((128 * 31) - 1) << 8); |
1289 | core.cts_mode = HDMI_AUDIO_CTS_MODE_HW; | 870 | acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW; |
1290 | core.use_mclk = true; | 871 | acore.use_mclk = true; |
1291 | } | 872 | } |
1292 | 873 | ||
1293 | if (core.use_mclk) | 874 | if (acore.use_mclk) |
1294 | core.mclk_mode = HDMI_AUDIO_MCLK_128FS; | 875 | acore.mclk_mode = HDMI_AUDIO_MCLK_128FS; |
1295 | 876 | ||
1296 | /* Audio channels settings */ | 877 | /* Audio channels settings */ |
1297 | channel_count = (audio->cea->db1_ct_cc & | 878 | channel_count = (audio->cea->db1_ct_cc & |
@@ -1329,25 +910,25 @@ int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | |||
1329 | */ | 910 | */ |
1330 | if (channel_count == 2) { | 911 | if (channel_count == 2) { |
1331 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; | 912 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; |
1332 | core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; | 913 | acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; |
1333 | core.layout = HDMI_AUDIO_LAYOUT_2CH; | 914 | acore.layout = HDMI_AUDIO_LAYOUT_2CH; |
1334 | } else { | 915 | } else { |
1335 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; | 916 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; |
1336 | core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | | 917 | acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | |
1337 | HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | | 918 | HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | |
1338 | HDMI_AUDIO_I2S_SD3_EN; | 919 | HDMI_AUDIO_I2S_SD3_EN; |
1339 | core.layout = HDMI_AUDIO_LAYOUT_8CH; | 920 | acore.layout = HDMI_AUDIO_LAYOUT_8CH; |
1340 | } | 921 | } |
1341 | 922 | ||
1342 | core.en_spdif = false; | 923 | acore.en_spdif = false; |
1343 | /* use sample frequency from channel status word */ | 924 | /* use sample frequency from channel status word */ |
1344 | core.fs_override = true; | 925 | acore.fs_override = true; |
1345 | /* enable ACR packets */ | 926 | /* enable ACR packets */ |
1346 | core.en_acr_pkt = true; | 927 | acore.en_acr_pkt = true; |
1347 | /* disable direct streaming digital audio */ | 928 | /* disable direct streaming digital audio */ |
1348 | core.en_dsd_audio = false; | 929 | acore.en_dsd_audio = false; |
1349 | /* use parallel audio interface */ | 930 | /* use parallel audio interface */ |
1350 | core.en_parallel_aud_input = true; | 931 | acore.en_parallel_aud_input = true; |
1351 | 932 | ||
1352 | /* DMA settings */ | 933 | /* DMA settings */ |
1353 | if (word_length_16b) | 934 | if (word_length_16b) |
@@ -1374,49 +955,37 @@ int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | |||
1374 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; | 955 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; |
1375 | 956 | ||
1376 | /* configure DMA and audio FIFO format*/ | 957 | /* configure DMA and audio FIFO format*/ |
1377 | ti_hdmi_4xxx_wp_audio_config_dma(ip_data, &audio_dma); | 958 | hdmi_wp_audio_config_dma(wp, &audio_dma); |
1378 | ti_hdmi_4xxx_wp_audio_config_format(ip_data, &audio_format); | 959 | hdmi_wp_audio_config_format(wp, &audio_format); |
1379 | 960 | ||
1380 | /* configure the core*/ | 961 | /* configure the core*/ |
1381 | ti_hdmi_4xxx_core_audio_config(ip_data, &core); | 962 | hdmi_core_audio_config(core, &acore); |
1382 | 963 | ||
1383 | /* configure CEA 861 audio infoframe*/ | 964 | /* configure CEA 861 audio infoframe*/ |
1384 | ti_hdmi_4xxx_core_audio_infoframe_cfg(ip_data, audio->cea); | 965 | hdmi_core_audio_infoframe_cfg(core, audio->cea); |
1385 | 966 | ||
1386 | return 0; | 967 | return 0; |
1387 | } | 968 | } |
1388 | 969 | ||
1389 | int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data) | 970 | int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) |
1390 | { | 971 | { |
1391 | REG_FLD_MOD(hdmi_wp_base(ip_data), | 972 | REG_FLD_MOD(hdmi_av_base(core), |
1392 | HDMI_WP_AUDIO_CTRL, true, 31, 31); | 973 | HDMI_CORE_AV_AUD_MODE, true, 0, 0); |
1393 | return 0; | ||
1394 | } | ||
1395 | 974 | ||
1396 | void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data) | 975 | hdmi_wp_audio_core_req_enable(wp, true); |
1397 | { | ||
1398 | REG_FLD_MOD(hdmi_wp_base(ip_data), | ||
1399 | HDMI_WP_AUDIO_CTRL, false, 31, 31); | ||
1400 | } | ||
1401 | 976 | ||
1402 | int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data) | ||
1403 | { | ||
1404 | REG_FLD_MOD(hdmi_av_base(ip_data), | ||
1405 | HDMI_CORE_AV_AUD_MODE, true, 0, 0); | ||
1406 | REG_FLD_MOD(hdmi_wp_base(ip_data), | ||
1407 | HDMI_WP_AUDIO_CTRL, true, 30, 30); | ||
1408 | return 0; | 977 | return 0; |
1409 | } | 978 | } |
1410 | 979 | ||
1411 | void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data) | 980 | void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) |
1412 | { | 981 | { |
1413 | REG_FLD_MOD(hdmi_av_base(ip_data), | 982 | REG_FLD_MOD(hdmi_av_base(core), |
1414 | HDMI_CORE_AV_AUD_MODE, false, 0, 0); | 983 | HDMI_CORE_AV_AUD_MODE, false, 0, 0); |
1415 | REG_FLD_MOD(hdmi_wp_base(ip_data), | 984 | |
1416 | HDMI_WP_AUDIO_CTRL, false, 30, 30); | 985 | hdmi_wp_audio_core_req_enable(wp, false); |
1417 | } | 986 | } |
1418 | 987 | ||
1419 | int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size) | 988 | int hdmi4_audio_get_dma_port(u32 *offset, u32 *size) |
1420 | { | 989 | { |
1421 | if (!offset || !size) | 990 | if (!offset || !size) |
1422 | return -EINVAL; | 991 | return -EINVAL; |
@@ -1424,4 +993,42 @@ int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size) | |||
1424 | *size = 4; | 993 | *size = 4; |
1425 | return 0; | 994 | return 0; |
1426 | } | 995 | } |
996 | |||
1427 | #endif | 997 | #endif |
998 | |||
999 | #define CORE_OFFSET 0x400 | ||
1000 | #define CORE_SIZE 0xc00 | ||
1001 | |||
1002 | int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) | ||
1003 | { | ||
1004 | struct resource *res; | ||
1005 | struct resource temp_res; | ||
1006 | |||
1007 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_core"); | ||
1008 | if (!res) { | ||
1009 | DSSDBG("can't get CORE mem resource by name\n"); | ||
1010 | /* | ||
1011 | * if hwmod/DT doesn't have the memory resource information | ||
1012 | * split into HDMI sub blocks by name, we try again by getting | ||
1013 | * the platform's first resource. this code will be removed when | ||
1014 | * the driver can get the mem resources by name | ||
1015 | */ | ||
1016 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1017 | if (!res) { | ||
1018 | DSSERR("can't get CORE mem resource\n"); | ||
1019 | return -EINVAL; | ||
1020 | } | ||
1021 | |||
1022 | temp_res.start = res->start + CORE_OFFSET; | ||
1023 | temp_res.end = temp_res.start + CORE_SIZE - 1; | ||
1024 | res = &temp_res; | ||
1025 | } | ||
1026 | |||
1027 | core->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | ||
1028 | if (!core->base) { | ||
1029 | DSSERR("can't ioremap CORE\n"); | ||
1030 | return -ENOMEM; | ||
1031 | } | ||
1032 | |||
1033 | return 0; | ||
1034 | } | ||
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h b/drivers/video/omap2/dss/hdmi4_core.h index 6ef2f929a76d..bb646896fa82 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.h +++ b/drivers/video/omap2/dss/hdmi4_core.h | |||
@@ -1,7 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * ti_hdmi_4xxx_ip.h | 2 | * HDMI header definition for OMAP4 HDMI core IP |
3 | * | ||
4 | * HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors. | ||
5 | * | 3 | * |
6 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | 4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * | 5 | * |
@@ -18,41 +16,22 @@ | |||
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
19 | */ | 17 | */ |
20 | 18 | ||
21 | #ifndef _HDMI_TI_4xxx_H_ | 19 | #ifndef _HDMI4_CORE_H_ |
22 | #define _HDMI_TI_4xxx_H_ | 20 | #define _HDMI4_CORE_H_ |
23 | |||
24 | #include <linux/string.h> | ||
25 | #include <video/omapdss.h> | ||
26 | #include "ti_hdmi.h" | ||
27 | |||
28 | /* HDMI Wrapper */ | ||
29 | 21 | ||
30 | #define HDMI_WP_REVISION 0x0 | 22 | #include "hdmi.h" |
31 | #define HDMI_WP_SYSCONFIG 0x10 | ||
32 | #define HDMI_WP_IRQSTATUS_RAW 0x24 | ||
33 | #define HDMI_WP_IRQSTATUS 0x28 | ||
34 | #define HDMI_WP_PWR_CTRL 0x40 | ||
35 | #define HDMI_WP_IRQENABLE_SET 0x2C | ||
36 | #define HDMI_WP_IRQENABLE_CLR 0x30 | ||
37 | #define HDMI_WP_VIDEO_CFG 0x50 | ||
38 | #define HDMI_WP_VIDEO_SIZE 0x60 | ||
39 | #define HDMI_WP_VIDEO_TIMING_H 0x68 | ||
40 | #define HDMI_WP_VIDEO_TIMING_V 0x6C | ||
41 | #define HDMI_WP_WP_CLK 0x70 | ||
42 | #define HDMI_WP_AUDIO_CFG 0x80 | ||
43 | #define HDMI_WP_AUDIO_CFG2 0x84 | ||
44 | #define HDMI_WP_AUDIO_CTRL 0x88 | ||
45 | #define HDMI_WP_AUDIO_DATA 0x8C | ||
46 | 23 | ||
47 | /* HDMI IP Core System */ | 24 | /* OMAP4 HDMI IP Core System */ |
48 | 25 | ||
49 | #define HDMI_CORE_SYS_VND_IDL 0x0 | 26 | #define HDMI_CORE_SYS_VND_IDL 0x0 |
50 | #define HDMI_CORE_SYS_DEV_IDL 0x8 | 27 | #define HDMI_CORE_SYS_DEV_IDL 0x8 |
51 | #define HDMI_CORE_SYS_DEV_IDH 0xC | 28 | #define HDMI_CORE_SYS_DEV_IDH 0xC |
52 | #define HDMI_CORE_SYS_DEV_REV 0x10 | 29 | #define HDMI_CORE_SYS_DEV_REV 0x10 |
53 | #define HDMI_CORE_SYS_SRST 0x14 | 30 | #define HDMI_CORE_SYS_SRST 0x14 |
54 | #define HDMI_CORE_CTRL1 0x20 | 31 | #define HDMI_CORE_SYS_SYS_CTRL1 0x20 |
55 | #define HDMI_CORE_SYS_SYS_STAT 0x24 | 32 | #define HDMI_CORE_SYS_SYS_STAT 0x24 |
33 | #define HDMI_CORE_SYS_SYS_CTRL3 0x28 | ||
34 | #define HDMI_CORE_SYS_DCTL 0x34 | ||
56 | #define HDMI_CORE_SYS_DE_DLY 0xC8 | 35 | #define HDMI_CORE_SYS_DE_DLY 0xC8 |
57 | #define HDMI_CORE_SYS_DE_CTRL 0xCC | 36 | #define HDMI_CORE_SYS_DE_CTRL 0xCC |
58 | #define HDMI_CORE_SYS_DE_TOP 0xD0 | 37 | #define HDMI_CORE_SYS_DE_TOP 0xD0 |
@@ -60,20 +39,65 @@ | |||
60 | #define HDMI_CORE_SYS_DE_CNTH 0xDC | 39 | #define HDMI_CORE_SYS_DE_CNTH 0xDC |
61 | #define HDMI_CORE_SYS_DE_LINL 0xE0 | 40 | #define HDMI_CORE_SYS_DE_LINL 0xE0 |
62 | #define HDMI_CORE_SYS_DE_LINH_1 0xE4 | 41 | #define HDMI_CORE_SYS_DE_LINH_1 0xE4 |
42 | #define HDMI_CORE_SYS_HRES_L 0xE8 | ||
43 | #define HDMI_CORE_SYS_HRES_H 0xEC | ||
44 | #define HDMI_CORE_SYS_VRES_L 0xF0 | ||
45 | #define HDMI_CORE_SYS_VRES_H 0xF4 | ||
46 | #define HDMI_CORE_SYS_IADJUST 0xF8 | ||
47 | #define HDMI_CORE_SYS_POLDETECT 0xFC | ||
48 | #define HDMI_CORE_SYS_HWIDTH1 0x110 | ||
49 | #define HDMI_CORE_SYS_HWIDTH2 0x114 | ||
50 | #define HDMI_CORE_SYS_VWIDTH 0x11C | ||
51 | #define HDMI_CORE_SYS_VID_CTRL 0x120 | ||
63 | #define HDMI_CORE_SYS_VID_ACEN 0x124 | 52 | #define HDMI_CORE_SYS_VID_ACEN 0x124 |
64 | #define HDMI_CORE_SYS_VID_MODE 0x128 | 53 | #define HDMI_CORE_SYS_VID_MODE 0x128 |
54 | #define HDMI_CORE_SYS_VID_BLANK1 0x12C | ||
55 | #define HDMI_CORE_SYS_VID_BLANK2 0x130 | ||
56 | #define HDMI_CORE_SYS_VID_BLANK3 0x134 | ||
57 | #define HDMI_CORE_SYS_DC_HEADER 0x138 | ||
58 | #define HDMI_CORE_SYS_VID_DITHER 0x13C | ||
59 | #define HDMI_CORE_SYS_RGB2XVYCC_CT 0x140 | ||
60 | #define HDMI_CORE_SYS_R2Y_COEFF_LOW 0x144 | ||
61 | #define HDMI_CORE_SYS_R2Y_COEFF_UP 0x148 | ||
62 | #define HDMI_CORE_SYS_G2Y_COEFF_LOW 0x14C | ||
63 | #define HDMI_CORE_SYS_G2Y_COEFF_UP 0x150 | ||
64 | #define HDMI_CORE_SYS_B2Y_COEFF_LOW 0x154 | ||
65 | #define HDMI_CORE_SYS_B2Y_COEFF_UP 0x158 | ||
66 | #define HDMI_CORE_SYS_R2CB_COEFF_LOW 0x15C | ||
67 | #define HDMI_CORE_SYS_R2CB_COEFF_UP 0x160 | ||
68 | #define HDMI_CORE_SYS_G2CB_COEFF_LOW 0x164 | ||
69 | #define HDMI_CORE_SYS_G2CB_COEFF_UP 0x168 | ||
70 | #define HDMI_CORE_SYS_B2CB_COEFF_LOW 0x16C | ||
71 | #define HDMI_CORE_SYS_B2CB_COEFF_UP 0x170 | ||
72 | #define HDMI_CORE_SYS_R2CR_COEFF_LOW 0x174 | ||
73 | #define HDMI_CORE_SYS_R2CR_COEFF_UP 0x178 | ||
74 | #define HDMI_CORE_SYS_G2CR_COEFF_LOW 0x17C | ||
75 | #define HDMI_CORE_SYS_G2CR_COEFF_UP 0x180 | ||
76 | #define HDMI_CORE_SYS_B2CR_COEFF_LOW 0x184 | ||
77 | #define HDMI_CORE_SYS_B2CR_COEFF_UP 0x188 | ||
78 | #define HDMI_CORE_SYS_RGB_OFFSET_LOW 0x18C | ||
79 | #define HDMI_CORE_SYS_RGB_OFFSET_UP 0x190 | ||
80 | #define HDMI_CORE_SYS_Y_OFFSET_LOW 0x194 | ||
81 | #define HDMI_CORE_SYS_Y_OFFSET_UP 0x198 | ||
82 | #define HDMI_CORE_SYS_CBCR_OFFSET_LOW 0x19C | ||
83 | #define HDMI_CORE_SYS_CBCR_OFFSET_UP 0x1A0 | ||
65 | #define HDMI_CORE_SYS_INTR_STATE 0x1C0 | 84 | #define HDMI_CORE_SYS_INTR_STATE 0x1C0 |
66 | #define HDMI_CORE_SYS_INTR1 0x1C4 | 85 | #define HDMI_CORE_SYS_INTR1 0x1C4 |
67 | #define HDMI_CORE_SYS_INTR2 0x1C8 | 86 | #define HDMI_CORE_SYS_INTR2 0x1C8 |
68 | #define HDMI_CORE_SYS_INTR3 0x1CC | 87 | #define HDMI_CORE_SYS_INTR3 0x1CC |
69 | #define HDMI_CORE_SYS_INTR4 0x1D0 | 88 | #define HDMI_CORE_SYS_INTR4 0x1D0 |
70 | #define HDMI_CORE_SYS_UMASK1 0x1D4 | 89 | #define HDMI_CORE_SYS_INTR_UNMASK1 0x1D4 |
90 | #define HDMI_CORE_SYS_INTR_UNMASK2 0x1D8 | ||
91 | #define HDMI_CORE_SYS_INTR_UNMASK3 0x1DC | ||
92 | #define HDMI_CORE_SYS_INTR_UNMASK4 0x1E0 | ||
93 | #define HDMI_CORE_SYS_INTR_CTRL 0x1E4 | ||
71 | #define HDMI_CORE_SYS_TMDS_CTRL 0x208 | 94 | #define HDMI_CORE_SYS_TMDS_CTRL 0x208 |
72 | 95 | ||
73 | #define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1 | 96 | /* value definitions for HDMI_CORE_SYS_SYS_CTRL1 fields */ |
74 | #define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1 | 97 | #define HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC 0x1 |
75 | #define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1 | 98 | #define HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC 0x1 |
76 | #define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1 | 99 | #define HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS 0x1 |
100 | #define HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE 0x1 | ||
77 | 101 | ||
78 | /* HDMI DDC E-DID */ | 102 | /* HDMI DDC E-DID */ |
79 | #define HDMI_CORE_DDC_ADDR 0x3B4 | 103 | #define HDMI_CORE_DDC_ADDR 0x3B4 |
@@ -158,35 +182,6 @@ | |||
158 | #define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31 | 182 | #define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31 |
159 | #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31 | 183 | #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31 |
160 | 184 | ||
161 | /* PLL */ | ||
162 | |||
163 | #define PLLCTRL_PLL_CONTROL 0x0 | ||
164 | #define PLLCTRL_PLL_STATUS 0x4 | ||
165 | #define PLLCTRL_PLL_GO 0x8 | ||
166 | #define PLLCTRL_CFG1 0xC | ||
167 | #define PLLCTRL_CFG2 0x10 | ||
168 | #define PLLCTRL_CFG3 0x14 | ||
169 | #define PLLCTRL_CFG4 0x20 | ||
170 | |||
171 | /* HDMI PHY */ | ||
172 | |||
173 | #define HDMI_TXPHY_TX_CTRL 0x0 | ||
174 | #define HDMI_TXPHY_DIGITAL_CTRL 0x4 | ||
175 | #define HDMI_TXPHY_POWER_CTRL 0x8 | ||
176 | #define HDMI_TXPHY_PAD_CFG_CTRL 0xC | ||
177 | |||
178 | #define REG_FLD_MOD(base, idx, val, start, end) \ | ||
179 | hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ | ||
180 | val, start, end)) | ||
181 | #define REG_GET(base, idx, start, end) \ | ||
182 | FLD_GET(hdmi_read_reg(base, idx), start, end) | ||
183 | |||
184 | enum hdmi_phy_pwr { | ||
185 | HDMI_PHYPWRCMD_OFF = 0, | ||
186 | HDMI_PHYPWRCMD_LDOON = 1, | ||
187 | HDMI_PHYPWRCMD_TXON = 2 | ||
188 | }; | ||
189 | |||
190 | enum hdmi_core_inputbus_width { | 185 | enum hdmi_core_inputbus_width { |
191 | HDMI_INPUT_8BIT = 0, | 186 | HDMI_INPUT_8BIT = 0, |
192 | HDMI_INPUT_10BIT = 1, | 187 | HDMI_INPUT_10BIT = 1, |
@@ -229,114 +224,6 @@ enum hdmi_core_packet_ctrl { | |||
229 | HDMI_PACKETREPEATOFF = 0 | 224 | HDMI_PACKETREPEATOFF = 0 |
230 | }; | 225 | }; |
231 | 226 | ||
232 | /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */ | ||
233 | enum hdmi_core_infoframe { | ||
234 | HDMI_INFOFRAME_AVI_DB1Y_RGB = 0, | ||
235 | HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1, | ||
236 | HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2, | ||
237 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0, | ||
238 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1, | ||
239 | HDMI_INFOFRAME_AVI_DB1B_NO = 0, | ||
240 | HDMI_INFOFRAME_AVI_DB1B_VERT = 1, | ||
241 | HDMI_INFOFRAME_AVI_DB1B_HORI = 2, | ||
242 | HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3, | ||
243 | HDMI_INFOFRAME_AVI_DB1S_0 = 0, | ||
244 | HDMI_INFOFRAME_AVI_DB1S_1 = 1, | ||
245 | HDMI_INFOFRAME_AVI_DB1S_2 = 2, | ||
246 | HDMI_INFOFRAME_AVI_DB2C_NO = 0, | ||
247 | HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1, | ||
248 | HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2, | ||
249 | HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3, | ||
250 | HDMI_INFOFRAME_AVI_DB2M_NO = 0, | ||
251 | HDMI_INFOFRAME_AVI_DB2M_43 = 1, | ||
252 | HDMI_INFOFRAME_AVI_DB2M_169 = 2, | ||
253 | HDMI_INFOFRAME_AVI_DB2R_SAME = 8, | ||
254 | HDMI_INFOFRAME_AVI_DB2R_43 = 9, | ||
255 | HDMI_INFOFRAME_AVI_DB2R_169 = 10, | ||
256 | HDMI_INFOFRAME_AVI_DB2R_149 = 11, | ||
257 | HDMI_INFOFRAME_AVI_DB3ITC_NO = 0, | ||
258 | HDMI_INFOFRAME_AVI_DB3ITC_YES = 1, | ||
259 | HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0, | ||
260 | HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1, | ||
261 | HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0, | ||
262 | HDMI_INFOFRAME_AVI_DB3Q_LR = 1, | ||
263 | HDMI_INFOFRAME_AVI_DB3Q_FR = 2, | ||
264 | HDMI_INFOFRAME_AVI_DB3SC_NO = 0, | ||
265 | HDMI_INFOFRAME_AVI_DB3SC_HORI = 1, | ||
266 | HDMI_INFOFRAME_AVI_DB3SC_VERT = 2, | ||
267 | HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3, | ||
268 | HDMI_INFOFRAME_AVI_DB5PR_NO = 0, | ||
269 | HDMI_INFOFRAME_AVI_DB5PR_2 = 1, | ||
270 | HDMI_INFOFRAME_AVI_DB5PR_3 = 2, | ||
271 | HDMI_INFOFRAME_AVI_DB5PR_4 = 3, | ||
272 | HDMI_INFOFRAME_AVI_DB5PR_5 = 4, | ||
273 | HDMI_INFOFRAME_AVI_DB5PR_6 = 5, | ||
274 | HDMI_INFOFRAME_AVI_DB5PR_7 = 6, | ||
275 | HDMI_INFOFRAME_AVI_DB5PR_8 = 7, | ||
276 | HDMI_INFOFRAME_AVI_DB5PR_9 = 8, | ||
277 | HDMI_INFOFRAME_AVI_DB5PR_10 = 9, | ||
278 | }; | ||
279 | |||
280 | enum hdmi_packing_mode { | ||
281 | HDMI_PACK_10b_RGB_YUV444 = 0, | ||
282 | HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, | ||
283 | HDMI_PACK_20b_YUV422 = 2, | ||
284 | HDMI_PACK_ALREADYPACKED = 7 | ||
285 | }; | ||
286 | |||
287 | enum hdmi_core_audio_layout { | ||
288 | HDMI_AUDIO_LAYOUT_2CH = 0, | ||
289 | HDMI_AUDIO_LAYOUT_8CH = 1 | ||
290 | }; | ||
291 | |||
292 | enum hdmi_core_cts_mode { | ||
293 | HDMI_AUDIO_CTS_MODE_HW = 0, | ||
294 | HDMI_AUDIO_CTS_MODE_SW = 1 | ||
295 | }; | ||
296 | |||
297 | enum hdmi_stereo_channels { | ||
298 | HDMI_AUDIO_STEREO_NOCHANNELS = 0, | ||
299 | HDMI_AUDIO_STEREO_ONECHANNEL = 1, | ||
300 | HDMI_AUDIO_STEREO_TWOCHANNELS = 2, | ||
301 | HDMI_AUDIO_STEREO_THREECHANNELS = 3, | ||
302 | HDMI_AUDIO_STEREO_FOURCHANNELS = 4 | ||
303 | }; | ||
304 | |||
305 | enum hdmi_audio_type { | ||
306 | HDMI_AUDIO_TYPE_LPCM = 0, | ||
307 | HDMI_AUDIO_TYPE_IEC = 1 | ||
308 | }; | ||
309 | |||
310 | enum hdmi_audio_justify { | ||
311 | HDMI_AUDIO_JUSTIFY_LEFT = 0, | ||
312 | HDMI_AUDIO_JUSTIFY_RIGHT = 1 | ||
313 | }; | ||
314 | |||
315 | enum hdmi_audio_sample_order { | ||
316 | HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0, | ||
317 | HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1 | ||
318 | }; | ||
319 | |||
320 | enum hdmi_audio_samples_perword { | ||
321 | HDMI_AUDIO_ONEWORD_ONESAMPLE = 0, | ||
322 | HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1 | ||
323 | }; | ||
324 | |||
325 | enum hdmi_audio_sample_size { | ||
326 | HDMI_AUDIO_SAMPLE_16BITS = 0, | ||
327 | HDMI_AUDIO_SAMPLE_24BITS = 1 | ||
328 | }; | ||
329 | |||
330 | enum hdmi_audio_transf_mode { | ||
331 | HDMI_AUDIO_TRANSF_DMA = 0, | ||
332 | HDMI_AUDIO_TRANSF_IRQ = 1 | ||
333 | }; | ||
334 | |||
335 | enum hdmi_audio_blk_strt_end_sig { | ||
336 | HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0, | ||
337 | HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1 | ||
338 | }; | ||
339 | |||
340 | enum hdmi_audio_i2s_config { | 227 | enum hdmi_audio_i2s_config { |
341 | HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0, | 228 | HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0, |
342 | HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1, | 229 | HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1, |
@@ -352,17 +239,6 @@ enum hdmi_audio_i2s_config { | |||
352 | HDMI_AUDIO_I2S_SD3_EN = 1 << 3, | 239 | HDMI_AUDIO_I2S_SD3_EN = 1 << 3, |
353 | }; | 240 | }; |
354 | 241 | ||
355 | enum hdmi_audio_mclk_mode { | ||
356 | HDMI_AUDIO_MCLK_128FS = 0, | ||
357 | HDMI_AUDIO_MCLK_256FS = 1, | ||
358 | HDMI_AUDIO_MCLK_384FS = 2, | ||
359 | HDMI_AUDIO_MCLK_512FS = 3, | ||
360 | HDMI_AUDIO_MCLK_768FS = 4, | ||
361 | HDMI_AUDIO_MCLK_1024FS = 5, | ||
362 | HDMI_AUDIO_MCLK_1152FS = 6, | ||
363 | HDMI_AUDIO_MCLK_192FS = 7 | ||
364 | }; | ||
365 | |||
366 | struct hdmi_core_video_config { | 242 | struct hdmi_core_video_config { |
367 | enum hdmi_core_inputbus_width ip_bus_width; | 243 | enum hdmi_core_inputbus_width ip_bus_width; |
368 | enum hdmi_core_dither_trunc op_dither_truc; | 244 | enum hdmi_core_dither_trunc op_dither_truc; |
@@ -383,55 +259,18 @@ struct hdmi_core_packet_enable_repeat { | |||
383 | u32 generic_pkt_repeat; | 259 | u32 generic_pkt_repeat; |
384 | }; | 260 | }; |
385 | 261 | ||
386 | struct hdmi_video_format { | 262 | int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len); |
387 | enum hdmi_packing_mode packing_mode; | 263 | void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, |
388 | u32 y_res; /* Line per panel */ | 264 | struct hdmi_config *cfg); |
389 | u32 x_res; /* pixel per line */ | 265 | void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s); |
390 | }; | 266 | int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core); |
391 | 267 | ||
392 | struct hdmi_audio_format { | 268 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
393 | enum hdmi_stereo_channels stereo_channels; | 269 | int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp); |
394 | u8 active_chnnls_msk; | 270 | void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp); |
395 | enum hdmi_audio_type type; | 271 | int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, |
396 | enum hdmi_audio_justify justification; | 272 | struct omap_dss_audio *audio, u32 pclk); |
397 | enum hdmi_audio_sample_order sample_order; | 273 | int hdmi4_audio_get_dma_port(u32 *offset, u32 *size); |
398 | enum hdmi_audio_samples_perword samples_per_word; | 274 | #endif |
399 | enum hdmi_audio_sample_size sample_size; | ||
400 | enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end; | ||
401 | }; | ||
402 | |||
403 | struct hdmi_audio_dma { | ||
404 | u8 transfer_size; | ||
405 | u8 block_size; | ||
406 | enum hdmi_audio_transf_mode mode; | ||
407 | u16 fifo_threshold; | ||
408 | }; | ||
409 | |||
410 | struct hdmi_core_audio_i2s_config { | ||
411 | u8 in_length_bits; | ||
412 | u8 justification; | ||
413 | u8 sck_edge_mode; | ||
414 | u8 vbit; | ||
415 | u8 direction; | ||
416 | u8 shift; | ||
417 | u8 active_sds; | ||
418 | }; | ||
419 | |||
420 | struct hdmi_core_audio_config { | ||
421 | struct hdmi_core_audio_i2s_config i2s_cfg; | ||
422 | struct snd_aes_iec958 *iec60958_cfg; | ||
423 | bool fs_override; | ||
424 | u32 n; | ||
425 | u32 cts; | ||
426 | u32 aud_par_busclk; | ||
427 | enum hdmi_core_audio_layout layout; | ||
428 | enum hdmi_core_cts_mode cts_mode; | ||
429 | bool use_mclk; | ||
430 | enum hdmi_audio_mclk_mode mclk_mode; | ||
431 | bool en_acr_pkt; | ||
432 | bool en_dsd_audio; | ||
433 | bool en_parallel_aud_input; | ||
434 | bool en_spdif; | ||
435 | }; | ||
436 | 275 | ||
437 | #endif | 276 | #endif |
diff --git a/drivers/video/omap2/dss/hdmi_common.c b/drivers/video/omap2/dss/hdmi_common.c new file mode 100644 index 000000000000..5586aaad9d63 --- /dev/null +++ b/drivers/video/omap2/dss/hdmi_common.c | |||
@@ -0,0 +1,423 @@ | |||
1 | |||
2 | /* | ||
3 | * Logic for the below structure : | ||
4 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. | ||
5 | * There is a correspondence between CEA/VESA timing and code, please | ||
6 | * refer to section 6.3 in HDMI 1.3 specification for timing code. | ||
7 | * | ||
8 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 | ||
9 | * supported CEA and VESA timing values.code_cea corresponds to the CEA | ||
10 | * code, It is used to get the timing from cea_vesa_timing array.Similarly | ||
11 | * with code_vesa. Code_index is used for back mapping, that is once EDID | ||
12 | * is read from the TV, EDID is parsed to find the timing values and then | ||
13 | * map it to corresponding CEA or VESA index. | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/err.h> | ||
18 | #include <video/omapdss.h> | ||
19 | |||
20 | #include "hdmi.h" | ||
21 | |||
22 | static const struct hdmi_config cea_timings[] = { | ||
23 | { | ||
24 | { 640, 480, 25200, 96, 16, 48, 2, 10, 33, | ||
25 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
26 | false, }, | ||
27 | { 1, HDMI_HDMI }, | ||
28 | }, | ||
29 | { | ||
30 | { 720, 480, 27027, 62, 16, 60, 6, 9, 30, | ||
31 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
32 | false, }, | ||
33 | { 2, HDMI_HDMI }, | ||
34 | }, | ||
35 | { | ||
36 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | ||
37 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
38 | false, }, | ||
39 | { 4, HDMI_HDMI }, | ||
40 | }, | ||
41 | { | ||
42 | { 1920, 540, 74250, 44, 88, 148, 5, 2, 15, | ||
43 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
44 | true, }, | ||
45 | { 5, HDMI_HDMI }, | ||
46 | }, | ||
47 | { | ||
48 | { 1440, 240, 27027, 124, 38, 114, 3, 4, 15, | ||
49 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
50 | true, }, | ||
51 | { 6, HDMI_HDMI }, | ||
52 | }, | ||
53 | { | ||
54 | { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36, | ||
55 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
56 | false, }, | ||
57 | { 16, HDMI_HDMI }, | ||
58 | }, | ||
59 | { | ||
60 | { 720, 576, 27000, 64, 12, 68, 5, 5, 39, | ||
61 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
62 | false, }, | ||
63 | { 17, HDMI_HDMI }, | ||
64 | }, | ||
65 | { | ||
66 | { 1280, 720, 74250, 40, 440, 220, 5, 5, 20, | ||
67 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
68 | false, }, | ||
69 | { 19, HDMI_HDMI }, | ||
70 | }, | ||
71 | { | ||
72 | { 1920, 540, 74250, 44, 528, 148, 5, 2, 15, | ||
73 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
74 | true, }, | ||
75 | { 20, HDMI_HDMI }, | ||
76 | }, | ||
77 | { | ||
78 | { 1440, 288, 27000, 126, 24, 138, 3, 2, 19, | ||
79 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
80 | true, }, | ||
81 | { 21, HDMI_HDMI }, | ||
82 | }, | ||
83 | { | ||
84 | { 1440, 576, 54000, 128, 24, 136, 5, 5, 39, | ||
85 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
86 | false, }, | ||
87 | { 29, HDMI_HDMI }, | ||
88 | }, | ||
89 | { | ||
90 | { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36, | ||
91 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
92 | false, }, | ||
93 | { 31, HDMI_HDMI }, | ||
94 | }, | ||
95 | { | ||
96 | { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36, | ||
97 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
98 | false, }, | ||
99 | { 32, HDMI_HDMI }, | ||
100 | }, | ||
101 | { | ||
102 | { 2880, 480, 108108, 248, 64, 240, 6, 9, 30, | ||
103 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
104 | false, }, | ||
105 | { 35, HDMI_HDMI }, | ||
106 | }, | ||
107 | { | ||
108 | { 2880, 576, 108000, 256, 48, 272, 5, 5, 39, | ||
109 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
110 | false, }, | ||
111 | { 37, HDMI_HDMI }, | ||
112 | }, | ||
113 | }; | ||
114 | |||
115 | static const struct hdmi_config vesa_timings[] = { | ||
116 | /* VESA From Here */ | ||
117 | { | ||
118 | { 640, 480, 25175, 96, 16, 48, 2, 11, 31, | ||
119 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
120 | false, }, | ||
121 | { 4, HDMI_DVI }, | ||
122 | }, | ||
123 | { | ||
124 | { 800, 600, 40000, 128, 40, 88, 4, 1, 23, | ||
125 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
126 | false, }, | ||
127 | { 9, HDMI_DVI }, | ||
128 | }, | ||
129 | { | ||
130 | { 848, 480, 33750, 112, 16, 112, 8, 6, 23, | ||
131 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
132 | false, }, | ||
133 | { 0xE, HDMI_DVI }, | ||
134 | }, | ||
135 | { | ||
136 | { 1280, 768, 79500, 128, 64, 192, 7, 3, 20, | ||
137 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
138 | false, }, | ||
139 | { 0x17, HDMI_DVI }, | ||
140 | }, | ||
141 | { | ||
142 | { 1280, 800, 83500, 128, 72, 200, 6, 3, 22, | ||
143 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
144 | false, }, | ||
145 | { 0x1C, HDMI_DVI }, | ||
146 | }, | ||
147 | { | ||
148 | { 1360, 768, 85500, 112, 64, 256, 6, 3, 18, | ||
149 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
150 | false, }, | ||
151 | { 0x27, HDMI_DVI }, | ||
152 | }, | ||
153 | { | ||
154 | { 1280, 960, 108000, 112, 96, 312, 3, 1, 36, | ||
155 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
156 | false, }, | ||
157 | { 0x20, HDMI_DVI }, | ||
158 | }, | ||
159 | { | ||
160 | { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38, | ||
161 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
162 | false, }, | ||
163 | { 0x23, HDMI_DVI }, | ||
164 | }, | ||
165 | { | ||
166 | { 1024, 768, 65000, 136, 24, 160, 6, 3, 29, | ||
167 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
168 | false, }, | ||
169 | { 0x10, HDMI_DVI }, | ||
170 | }, | ||
171 | { | ||
172 | { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32, | ||
173 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
174 | false, }, | ||
175 | { 0x2A, HDMI_DVI }, | ||
176 | }, | ||
177 | { | ||
178 | { 1440, 900, 106500, 152, 80, 232, 6, 3, 25, | ||
179 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
180 | false, }, | ||
181 | { 0x2F, HDMI_DVI }, | ||
182 | }, | ||
183 | { | ||
184 | { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, | ||
185 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
186 | false, }, | ||
187 | { 0x3A, HDMI_DVI }, | ||
188 | }, | ||
189 | { | ||
190 | { 1366, 768, 85500, 143, 70, 213, 3, 3, 24, | ||
191 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
192 | false, }, | ||
193 | { 0x51, HDMI_DVI }, | ||
194 | }, | ||
195 | { | ||
196 | { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36, | ||
197 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
198 | false, }, | ||
199 | { 0x52, HDMI_DVI }, | ||
200 | }, | ||
201 | { | ||
202 | { 1280, 768, 68250, 32, 48, 80, 7, 3, 12, | ||
203 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
204 | false, }, | ||
205 | { 0x16, HDMI_DVI }, | ||
206 | }, | ||
207 | { | ||
208 | { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23, | ||
209 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
210 | false, }, | ||
211 | { 0x29, HDMI_DVI }, | ||
212 | }, | ||
213 | { | ||
214 | { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21, | ||
215 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
216 | false, }, | ||
217 | { 0x39, HDMI_DVI }, | ||
218 | }, | ||
219 | { | ||
220 | { 1280, 800, 79500, 32, 48, 80, 6, 3, 14, | ||
221 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
222 | false, }, | ||
223 | { 0x1B, HDMI_DVI }, | ||
224 | }, | ||
225 | { | ||
226 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | ||
227 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
228 | false, }, | ||
229 | { 0x55, HDMI_DVI }, | ||
230 | }, | ||
231 | { | ||
232 | { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26, | ||
233 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
234 | false, }, | ||
235 | { 0x44, HDMI_DVI }, | ||
236 | }, | ||
237 | }; | ||
238 | |||
239 | const struct hdmi_config *hdmi_default_timing(void) | ||
240 | { | ||
241 | return &vesa_timings[0]; | ||
242 | } | ||
243 | |||
244 | static const struct hdmi_config *hdmi_find_timing(int code, | ||
245 | const struct hdmi_config *timings_arr, int len) | ||
246 | { | ||
247 | int i; | ||
248 | |||
249 | for (i = 0; i < len; i++) { | ||
250 | if (timings_arr[i].cm.code == code) | ||
251 | return &timings_arr[i]; | ||
252 | } | ||
253 | |||
254 | return NULL; | ||
255 | } | ||
256 | |||
257 | const struct hdmi_config *hdmi_get_timings(int mode, int code) | ||
258 | { | ||
259 | const struct hdmi_config *arr; | ||
260 | int len; | ||
261 | |||
262 | if (mode == HDMI_DVI) { | ||
263 | arr = vesa_timings; | ||
264 | len = ARRAY_SIZE(vesa_timings); | ||
265 | } else { | ||
266 | arr = cea_timings; | ||
267 | len = ARRAY_SIZE(cea_timings); | ||
268 | } | ||
269 | |||
270 | return hdmi_find_timing(code, arr, len); | ||
271 | } | ||
272 | |||
273 | static bool hdmi_timings_compare(struct omap_video_timings *timing1, | ||
274 | const struct omap_video_timings *timing2) | ||
275 | { | ||
276 | int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; | ||
277 | |||
278 | if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) == | ||
279 | DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) && | ||
280 | (timing2->x_res == timing1->x_res) && | ||
281 | (timing2->y_res == timing1->y_res)) { | ||
282 | |||
283 | timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp; | ||
284 | timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp; | ||
285 | timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | ||
286 | timing1_vsync = timing1->vfp + timing1->vsw + timing1->vbp; | ||
287 | |||
288 | DSSDBG("timing1_hsync = %d timing1_vsync = %d"\ | ||
289 | "timing2_hsync = %d timing2_vsync = %d\n", | ||
290 | timing1_hsync, timing1_vsync, | ||
291 | timing2_hsync, timing2_vsync); | ||
292 | |||
293 | if ((timing1_hsync == timing2_hsync) && | ||
294 | (timing1_vsync == timing2_vsync)) { | ||
295 | return true; | ||
296 | } | ||
297 | } | ||
298 | return false; | ||
299 | } | ||
300 | |||
301 | struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | ||
302 | { | ||
303 | int i; | ||
304 | struct hdmi_cm cm = {-1}; | ||
305 | DSSDBG("hdmi_get_code\n"); | ||
306 | |||
307 | for (i = 0; i < ARRAY_SIZE(cea_timings); i++) { | ||
308 | if (hdmi_timings_compare(timing, &cea_timings[i].timings)) { | ||
309 | cm = cea_timings[i].cm; | ||
310 | goto end; | ||
311 | } | ||
312 | } | ||
313 | for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) { | ||
314 | if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) { | ||
315 | cm = vesa_timings[i].cm; | ||
316 | goto end; | ||
317 | } | ||
318 | } | ||
319 | |||
320 | end: | ||
321 | return cm; | ||
322 | } | ||
323 | |||
324 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
325 | int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts) | ||
326 | { | ||
327 | u32 deep_color; | ||
328 | bool deep_color_correct = false; | ||
329 | |||
330 | if (n == NULL || cts == NULL) | ||
331 | return -EINVAL; | ||
332 | |||
333 | /* TODO: When implemented, query deep color mode here. */ | ||
334 | deep_color = 100; | ||
335 | |||
336 | /* | ||
337 | * When using deep color, the default N value (as in the HDMI | ||
338 | * specification) yields to an non-integer CTS. Hence, we | ||
339 | * modify it while keeping the restrictions described in | ||
340 | * section 7.2.1 of the HDMI 1.4a specification. | ||
341 | */ | ||
342 | switch (sample_freq) { | ||
343 | case 32000: | ||
344 | case 48000: | ||
345 | case 96000: | ||
346 | case 192000: | ||
347 | if (deep_color == 125) | ||
348 | if (pclk == 27027 || pclk == 74250) | ||
349 | deep_color_correct = true; | ||
350 | if (deep_color == 150) | ||
351 | if (pclk == 27027) | ||
352 | deep_color_correct = true; | ||
353 | break; | ||
354 | case 44100: | ||
355 | case 88200: | ||
356 | case 176400: | ||
357 | if (deep_color == 125) | ||
358 | if (pclk == 27027) | ||
359 | deep_color_correct = true; | ||
360 | break; | ||
361 | default: | ||
362 | return -EINVAL; | ||
363 | } | ||
364 | |||
365 | if (deep_color_correct) { | ||
366 | switch (sample_freq) { | ||
367 | case 32000: | ||
368 | *n = 8192; | ||
369 | break; | ||
370 | case 44100: | ||
371 | *n = 12544; | ||
372 | break; | ||
373 | case 48000: | ||
374 | *n = 8192; | ||
375 | break; | ||
376 | case 88200: | ||
377 | *n = 25088; | ||
378 | break; | ||
379 | case 96000: | ||
380 | *n = 16384; | ||
381 | break; | ||
382 | case 176400: | ||
383 | *n = 50176; | ||
384 | break; | ||
385 | case 192000: | ||
386 | *n = 32768; | ||
387 | break; | ||
388 | default: | ||
389 | return -EINVAL; | ||
390 | } | ||
391 | } else { | ||
392 | switch (sample_freq) { | ||
393 | case 32000: | ||
394 | *n = 4096; | ||
395 | break; | ||
396 | case 44100: | ||
397 | *n = 6272; | ||
398 | break; | ||
399 | case 48000: | ||
400 | *n = 6144; | ||
401 | break; | ||
402 | case 88200: | ||
403 | *n = 12544; | ||
404 | break; | ||
405 | case 96000: | ||
406 | *n = 12288; | ||
407 | break; | ||
408 | case 176400: | ||
409 | *n = 25088; | ||
410 | break; | ||
411 | case 192000: | ||
412 | *n = 24576; | ||
413 | break; | ||
414 | default: | ||
415 | return -EINVAL; | ||
416 | } | ||
417 | } | ||
418 | /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */ | ||
419 | *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10); | ||
420 | |||
421 | return 0; | ||
422 | } | ||
423 | #endif | ||
diff --git a/drivers/video/omap2/dss/hdmi_phy.c b/drivers/video/omap2/dss/hdmi_phy.c new file mode 100644 index 000000000000..45acb997ac00 --- /dev/null +++ b/drivers/video/omap2/dss/hdmi_phy.c | |||
@@ -0,0 +1,160 @@ | |||
1 | /* | ||
2 | * HDMI PHY | ||
3 | * | ||
4 | * Copyright (C) 2013 Texas Instruments Incorporated | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License version 2 as published by | ||
8 | * the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/err.h> | ||
13 | #include <linux/io.h> | ||
14 | #include <linux/platform_device.h> | ||
15 | #include <video/omapdss.h> | ||
16 | |||
17 | #include "dss.h" | ||
18 | #include "hdmi.h" | ||
19 | |||
20 | void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s) | ||
21 | { | ||
22 | #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\ | ||
23 | hdmi_read_reg(phy->base, r)) | ||
24 | |||
25 | DUMPPHY(HDMI_TXPHY_TX_CTRL); | ||
26 | DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL); | ||
27 | DUMPPHY(HDMI_TXPHY_POWER_CTRL); | ||
28 | DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL); | ||
29 | } | ||
30 | |||
31 | static irqreturn_t hdmi_irq_handler(int irq, void *data) | ||
32 | { | ||
33 | struct hdmi_wp_data *wp = data; | ||
34 | u32 irqstatus; | ||
35 | |||
36 | irqstatus = hdmi_wp_get_irqstatus(wp); | ||
37 | hdmi_wp_set_irqstatus(wp, irqstatus); | ||
38 | |||
39 | if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && | ||
40 | irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | ||
41 | /* | ||
42 | * If we get both connect and disconnect interrupts at the same | ||
43 | * time, turn off the PHY, clear interrupts, and restart, which | ||
44 | * raises connect interrupt if a cable is connected, or nothing | ||
45 | * if cable is not connected. | ||
46 | */ | ||
47 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); | ||
48 | |||
49 | hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | | ||
50 | HDMI_IRQ_LINK_DISCONNECT); | ||
51 | |||
52 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | ||
53 | } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { | ||
54 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); | ||
55 | } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | ||
56 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | ||
57 | } | ||
58 | |||
59 | return IRQ_HANDLED; | ||
60 | } | ||
61 | |||
62 | int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp, | ||
63 | struct hdmi_config *cfg) | ||
64 | { | ||
65 | u16 r = 0; | ||
66 | u32 irqstatus; | ||
67 | |||
68 | hdmi_wp_clear_irqenable(wp, 0xffffffff); | ||
69 | |||
70 | irqstatus = hdmi_wp_get_irqstatus(wp); | ||
71 | hdmi_wp_set_irqstatus(wp, irqstatus); | ||
72 | |||
73 | r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | ||
74 | if (r) | ||
75 | return r; | ||
76 | |||
77 | /* | ||
78 | * Read address 0 in order to get the SCP reset done completed | ||
79 | * Dummy access performed to make sure reset is done | ||
80 | */ | ||
81 | hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL); | ||
82 | |||
83 | /* | ||
84 | * Write to phy address 0 to configure the clock | ||
85 | * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field | ||
86 | */ | ||
87 | REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); | ||
88 | |||
89 | /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ | ||
90 | hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); | ||
91 | |||
92 | /* Setup max LDO voltage */ | ||
93 | REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); | ||
94 | |||
95 | /* Write to phy address 3 to change the polarity control */ | ||
96 | REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); | ||
97 | |||
98 | r = request_threaded_irq(phy->irq, NULL, hdmi_irq_handler, | ||
99 | IRQF_ONESHOT, "OMAP HDMI", wp); | ||
100 | if (r) { | ||
101 | DSSERR("HDMI IRQ request failed\n"); | ||
102 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); | ||
103 | return r; | ||
104 | } | ||
105 | |||
106 | hdmi_wp_set_irqenable(wp, | ||
107 | HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); | ||
108 | |||
109 | return 0; | ||
110 | } | ||
111 | |||
112 | void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp) | ||
113 | { | ||
114 | free_irq(phy->irq, wp); | ||
115 | |||
116 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); | ||
117 | } | ||
118 | |||
119 | #define PHY_OFFSET 0x300 | ||
120 | #define PHY_SIZE 0x100 | ||
121 | |||
122 | int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy) | ||
123 | { | ||
124 | struct resource *res; | ||
125 | struct resource temp_res; | ||
126 | |||
127 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_txphy"); | ||
128 | if (!res) { | ||
129 | DSSDBG("can't get PHY mem resource by name\n"); | ||
130 | /* | ||
131 | * if hwmod/DT doesn't have the memory resource information | ||
132 | * split into HDMI sub blocks by name, we try again by getting | ||
133 | * the platform's first resource. this code will be removed when | ||
134 | * the driver can get the mem resources by name | ||
135 | */ | ||
136 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
137 | if (!res) { | ||
138 | DSSERR("can't get PHY mem resource\n"); | ||
139 | return -EINVAL; | ||
140 | } | ||
141 | |||
142 | temp_res.start = res->start + PHY_OFFSET; | ||
143 | temp_res.end = temp_res.start + PHY_SIZE - 1; | ||
144 | res = &temp_res; | ||
145 | } | ||
146 | |||
147 | phy->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | ||
148 | if (!phy->base) { | ||
149 | DSSERR("can't ioremap TX PHY\n"); | ||
150 | return -ENOMEM; | ||
151 | } | ||
152 | |||
153 | phy->irq = platform_get_irq(pdev, 0); | ||
154 | if (phy->irq < 0) { | ||
155 | DSSERR("platform_get_irq failed\n"); | ||
156 | return -ENODEV; | ||
157 | } | ||
158 | |||
159 | return 0; | ||
160 | } | ||
diff --git a/drivers/video/omap2/dss/hdmi_pll.c b/drivers/video/omap2/dss/hdmi_pll.c new file mode 100644 index 000000000000..d3e6e78c0082 --- /dev/null +++ b/drivers/video/omap2/dss/hdmi_pll.c | |||
@@ -0,0 +1,230 @@ | |||
1 | /* | ||
2 | * HDMI PLL | ||
3 | * | ||
4 | * Copyright (C) 2013 Texas Instruments Incorporated | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License version 2 as published by | ||
8 | * the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/module.h> | ||
13 | #include <linux/err.h> | ||
14 | #include <linux/io.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | #include <video/omapdss.h> | ||
17 | |||
18 | #include "dss.h" | ||
19 | #include "hdmi.h" | ||
20 | |||
21 | #define HDMI_DEFAULT_REGN 16 | ||
22 | #define HDMI_DEFAULT_REGM2 1 | ||
23 | |||
24 | void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) | ||
25 | { | ||
26 | #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ | ||
27 | hdmi_read_reg(pll->base, r)) | ||
28 | |||
29 | DUMPPLL(PLLCTRL_PLL_CONTROL); | ||
30 | DUMPPLL(PLLCTRL_PLL_STATUS); | ||
31 | DUMPPLL(PLLCTRL_PLL_GO); | ||
32 | DUMPPLL(PLLCTRL_CFG1); | ||
33 | DUMPPLL(PLLCTRL_CFG2); | ||
34 | DUMPPLL(PLLCTRL_CFG3); | ||
35 | DUMPPLL(PLLCTRL_SSC_CFG1); | ||
36 | DUMPPLL(PLLCTRL_SSC_CFG2); | ||
37 | DUMPPLL(PLLCTRL_CFG4); | ||
38 | } | ||
39 | |||
40 | void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy) | ||
41 | { | ||
42 | struct hdmi_pll_info *pi = &pll->info; | ||
43 | unsigned long refclk; | ||
44 | u32 mf; | ||
45 | |||
46 | /* use our funky units */ | ||
47 | clkin /= 10000; | ||
48 | |||
49 | /* | ||
50 | * Input clock is predivided by N + 1 | ||
51 | * out put of which is reference clk | ||
52 | */ | ||
53 | |||
54 | pi->regn = HDMI_DEFAULT_REGN; | ||
55 | |||
56 | refclk = clkin / pi->regn; | ||
57 | |||
58 | pi->regm2 = HDMI_DEFAULT_REGM2; | ||
59 | |||
60 | /* | ||
61 | * multiplier is pixel_clk/ref_clk | ||
62 | * Multiplying by 100 to avoid fractional part removal | ||
63 | */ | ||
64 | pi->regm = phy * pi->regm2 / refclk; | ||
65 | |||
66 | /* | ||
67 | * fractional multiplier is remainder of the difference between | ||
68 | * multiplier and actual phy(required pixel clock thus should be | ||
69 | * multiplied by 2^18(262144) divided by the reference clock | ||
70 | */ | ||
71 | mf = (phy - pi->regm / pi->regm2 * refclk) * 262144; | ||
72 | pi->regmf = pi->regm2 * mf / refclk; | ||
73 | |||
74 | /* | ||
75 | * Dcofreq should be set to 1 if required pixel clock | ||
76 | * is greater than 1000MHz | ||
77 | */ | ||
78 | pi->dcofreq = phy > 1000 * 100; | ||
79 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; | ||
80 | |||
81 | /* Set the reference clock to sysclk reference */ | ||
82 | pi->refsel = HDMI_REFSEL_SYSCLK; | ||
83 | |||
84 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); | ||
85 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | ||
86 | } | ||
87 | |||
88 | |||
89 | static int hdmi_pll_config(struct hdmi_pll_data *pll) | ||
90 | { | ||
91 | u32 r; | ||
92 | struct hdmi_pll_info *fmt = &pll->info; | ||
93 | |||
94 | /* PLL start always use manual mode */ | ||
95 | REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); | ||
96 | |||
97 | r = hdmi_read_reg(pll->base, PLLCTRL_CFG1); | ||
98 | r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ | ||
99 | r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */ | ||
100 | hdmi_write_reg(pll->base, PLLCTRL_CFG1, r); | ||
101 | |||
102 | r = hdmi_read_reg(pll->base, PLLCTRL_CFG2); | ||
103 | |||
104 | r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ | ||
105 | r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ | ||
106 | r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ | ||
107 | r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */ | ||
108 | |||
109 | if (fmt->dcofreq) { | ||
110 | /* divider programming for frequency beyond 1000Mhz */ | ||
111 | REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10); | ||
112 | r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ | ||
113 | } else { | ||
114 | r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ | ||
115 | } | ||
116 | |||
117 | hdmi_write_reg(pll->base, PLLCTRL_CFG2, r); | ||
118 | |||
119 | r = hdmi_read_reg(pll->base, PLLCTRL_CFG4); | ||
120 | r = FLD_MOD(r, fmt->regm2, 24, 18); | ||
121 | r = FLD_MOD(r, fmt->regmf, 17, 0); | ||
122 | hdmi_write_reg(pll->base, PLLCTRL_CFG4, r); | ||
123 | |||
124 | /* go now */ | ||
125 | REG_FLD_MOD(pll->base, PLLCTRL_PLL_GO, 0x1, 0, 0); | ||
126 | |||
127 | /* wait for bit change */ | ||
128 | if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO, | ||
129 | 0, 0, 1) != 1) { | ||
130 | pr_err("PLL GO bit not set\n"); | ||
131 | return -ETIMEDOUT; | ||
132 | } | ||
133 | |||
134 | /* Wait till the lock bit is set in PLL status */ | ||
135 | if (hdmi_wait_for_bit_change(pll->base, | ||
136 | PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { | ||
137 | pr_err("cannot lock PLL\n"); | ||
138 | pr_err("CFG1 0x%x\n", | ||
139 | hdmi_read_reg(pll->base, PLLCTRL_CFG1)); | ||
140 | pr_err("CFG2 0x%x\n", | ||
141 | hdmi_read_reg(pll->base, PLLCTRL_CFG2)); | ||
142 | pr_err("CFG4 0x%x\n", | ||
143 | hdmi_read_reg(pll->base, PLLCTRL_CFG4)); | ||
144 | return -ETIMEDOUT; | ||
145 | } | ||
146 | |||
147 | pr_debug("PLL locked!\n"); | ||
148 | |||
149 | return 0; | ||
150 | } | ||
151 | |||
152 | static int hdmi_pll_reset(struct hdmi_pll_data *pll) | ||
153 | { | ||
154 | /* SYSRESET controlled by power FSM */ | ||
155 | REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 3, 3); | ||
156 | |||
157 | /* READ 0x0 reset is in progress */ | ||
158 | if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1) | ||
159 | != 1) { | ||
160 | pr_err("Failed to sysreset PLL\n"); | ||
161 | return -ETIMEDOUT; | ||
162 | } | ||
163 | |||
164 | return 0; | ||
165 | } | ||
166 | |||
167 | int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) | ||
168 | { | ||
169 | u16 r = 0; | ||
170 | |||
171 | r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); | ||
172 | if (r) | ||
173 | return r; | ||
174 | |||
175 | r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); | ||
176 | if (r) | ||
177 | return r; | ||
178 | |||
179 | r = hdmi_pll_reset(pll); | ||
180 | if (r) | ||
181 | return r; | ||
182 | |||
183 | r = hdmi_pll_config(pll); | ||
184 | if (r) | ||
185 | return r; | ||
186 | |||
187 | return 0; | ||
188 | } | ||
189 | |||
190 | void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) | ||
191 | { | ||
192 | hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); | ||
193 | } | ||
194 | |||
195 | #define PLL_OFFSET 0x200 | ||
196 | #define PLL_SIZE 0x100 | ||
197 | |||
198 | int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll) | ||
199 | { | ||
200 | struct resource *res; | ||
201 | struct resource temp_res; | ||
202 | |||
203 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_pllctrl"); | ||
204 | if (!res) { | ||
205 | DSSDBG("can't get PLL mem resource by name\n"); | ||
206 | /* | ||
207 | * if hwmod/DT doesn't have the memory resource information | ||
208 | * split into HDMI sub blocks by name, we try again by getting | ||
209 | * the platform's first resource. this code will be removed when | ||
210 | * the driver can get the mem resources by name | ||
211 | */ | ||
212 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
213 | if (!res) { | ||
214 | DSSERR("can't get PLL mem resource\n"); | ||
215 | return -EINVAL; | ||
216 | } | ||
217 | |||
218 | temp_res.start = res->start + PLL_OFFSET; | ||
219 | temp_res.end = temp_res.start + PLL_SIZE - 1; | ||
220 | res = &temp_res; | ||
221 | } | ||
222 | |||
223 | pll->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | ||
224 | if (!pll->base) { | ||
225 | DSSERR("can't ioremap PLLCTRL\n"); | ||
226 | return -ENOMEM; | ||
227 | } | ||
228 | |||
229 | return 0; | ||
230 | } | ||
diff --git a/drivers/video/omap2/dss/hdmi_wp.c b/drivers/video/omap2/dss/hdmi_wp.c new file mode 100644 index 000000000000..8151d8969a6e --- /dev/null +++ b/drivers/video/omap2/dss/hdmi_wp.c | |||
@@ -0,0 +1,271 @@ | |||
1 | /* | ||
2 | * HDMI wrapper | ||
3 | * | ||
4 | * Copyright (C) 2013 Texas Instruments Incorporated | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License version 2 as published by | ||
8 | * the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/err.h> | ||
13 | #include <linux/io.h> | ||
14 | #include <linux/platform_device.h> | ||
15 | #include <video/omapdss.h> | ||
16 | |||
17 | #include "dss.h" | ||
18 | #include "hdmi.h" | ||
19 | |||
20 | void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) | ||
21 | { | ||
22 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) | ||
23 | |||
24 | DUMPREG(HDMI_WP_REVISION); | ||
25 | DUMPREG(HDMI_WP_SYSCONFIG); | ||
26 | DUMPREG(HDMI_WP_IRQSTATUS_RAW); | ||
27 | DUMPREG(HDMI_WP_IRQSTATUS); | ||
28 | DUMPREG(HDMI_WP_IRQENABLE_SET); | ||
29 | DUMPREG(HDMI_WP_IRQENABLE_CLR); | ||
30 | DUMPREG(HDMI_WP_IRQWAKEEN); | ||
31 | DUMPREG(HDMI_WP_PWR_CTRL); | ||
32 | DUMPREG(HDMI_WP_DEBOUNCE); | ||
33 | DUMPREG(HDMI_WP_VIDEO_CFG); | ||
34 | DUMPREG(HDMI_WP_VIDEO_SIZE); | ||
35 | DUMPREG(HDMI_WP_VIDEO_TIMING_H); | ||
36 | DUMPREG(HDMI_WP_VIDEO_TIMING_V); | ||
37 | DUMPREG(HDMI_WP_WP_CLK); | ||
38 | DUMPREG(HDMI_WP_AUDIO_CFG); | ||
39 | DUMPREG(HDMI_WP_AUDIO_CFG2); | ||
40 | DUMPREG(HDMI_WP_AUDIO_CTRL); | ||
41 | DUMPREG(HDMI_WP_AUDIO_DATA); | ||
42 | } | ||
43 | |||
44 | u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) | ||
45 | { | ||
46 | return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); | ||
47 | } | ||
48 | |||
49 | void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) | ||
50 | { | ||
51 | hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); | ||
52 | /* flush posted write */ | ||
53 | hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); | ||
54 | } | ||
55 | |||
56 | void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) | ||
57 | { | ||
58 | hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); | ||
59 | } | ||
60 | |||
61 | void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) | ||
62 | { | ||
63 | hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); | ||
64 | } | ||
65 | |||
66 | /* PHY_PWR_CMD */ | ||
67 | int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val) | ||
68 | { | ||
69 | /* Return if already the state */ | ||
70 | if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) | ||
71 | return 0; | ||
72 | |||
73 | /* Command for power control of HDMI PHY */ | ||
74 | REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); | ||
75 | |||
76 | /* Status of the power control of HDMI PHY */ | ||
77 | if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) | ||
78 | != val) { | ||
79 | pr_err("Failed to set PHY power mode to %d\n", val); | ||
80 | return -ETIMEDOUT; | ||
81 | } | ||
82 | |||
83 | return 0; | ||
84 | } | ||
85 | |||
86 | /* PLL_PWR_CMD */ | ||
87 | int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val) | ||
88 | { | ||
89 | /* Command for power control of HDMI PLL */ | ||
90 | REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); | ||
91 | |||
92 | /* wait till PHY_PWR_STATUS is set */ | ||
93 | if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) | ||
94 | != val) { | ||
95 | pr_err("Failed to set PLL_PWR_STATUS\n"); | ||
96 | return -ETIMEDOUT; | ||
97 | } | ||
98 | |||
99 | return 0; | ||
100 | } | ||
101 | |||
102 | int hdmi_wp_video_start(struct hdmi_wp_data *wp) | ||
103 | { | ||
104 | REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); | ||
105 | |||
106 | return 0; | ||
107 | } | ||
108 | |||
109 | void hdmi_wp_video_stop(struct hdmi_wp_data *wp) | ||
110 | { | ||
111 | REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); | ||
112 | } | ||
113 | |||
114 | void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, | ||
115 | struct hdmi_video_format *video_fmt) | ||
116 | { | ||
117 | u32 l = 0; | ||
118 | |||
119 | REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, | ||
120 | 10, 8); | ||
121 | |||
122 | l |= FLD_VAL(video_fmt->y_res, 31, 16); | ||
123 | l |= FLD_VAL(video_fmt->x_res, 15, 0); | ||
124 | hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l); | ||
125 | } | ||
126 | |||
127 | void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, | ||
128 | struct omap_video_timings *timings) | ||
129 | { | ||
130 | u32 r; | ||
131 | bool vsync_pol, hsync_pol; | ||
132 | pr_debug("Enter hdmi_wp_video_config_interface\n"); | ||
133 | |||
134 | vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; | ||
135 | hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; | ||
136 | |||
137 | r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); | ||
138 | r = FLD_MOD(r, vsync_pol, 7, 7); | ||
139 | r = FLD_MOD(r, hsync_pol, 6, 6); | ||
140 | r = FLD_MOD(r, timings->interlace, 3, 3); | ||
141 | r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ | ||
142 | hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r); | ||
143 | } | ||
144 | |||
145 | void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, | ||
146 | struct omap_video_timings *timings) | ||
147 | { | ||
148 | u32 timing_h = 0; | ||
149 | u32 timing_v = 0; | ||
150 | |||
151 | pr_debug("Enter hdmi_wp_video_config_timing\n"); | ||
152 | |||
153 | timing_h |= FLD_VAL(timings->hbp, 31, 20); | ||
154 | timing_h |= FLD_VAL(timings->hfp, 19, 8); | ||
155 | timing_h |= FLD_VAL(timings->hsw, 7, 0); | ||
156 | hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); | ||
157 | |||
158 | timing_v |= FLD_VAL(timings->vbp, 31, 20); | ||
159 | timing_v |= FLD_VAL(timings->vfp, 19, 8); | ||
160 | timing_v |= FLD_VAL(timings->vsw, 7, 0); | ||
161 | hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); | ||
162 | } | ||
163 | |||
164 | void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, | ||
165 | struct omap_video_timings *timings, struct hdmi_config *param) | ||
166 | { | ||
167 | pr_debug("Enter hdmi_wp_video_init_format\n"); | ||
168 | |||
169 | video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; | ||
170 | video_fmt->y_res = param->timings.y_res; | ||
171 | video_fmt->x_res = param->timings.x_res; | ||
172 | |||
173 | timings->hbp = param->timings.hbp; | ||
174 | timings->hfp = param->timings.hfp; | ||
175 | timings->hsw = param->timings.hsw; | ||
176 | timings->vbp = param->timings.vbp; | ||
177 | timings->vfp = param->timings.vfp; | ||
178 | timings->vsw = param->timings.vsw; | ||
179 | timings->vsync_level = param->timings.vsync_level; | ||
180 | timings->hsync_level = param->timings.hsync_level; | ||
181 | timings->interlace = param->timings.interlace; | ||
182 | } | ||
183 | |||
184 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
185 | void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, | ||
186 | struct hdmi_audio_format *aud_fmt) | ||
187 | { | ||
188 | u32 r; | ||
189 | |||
190 | DSSDBG("Enter hdmi_wp_audio_config_format\n"); | ||
191 | |||
192 | r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); | ||
193 | r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); | ||
194 | r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); | ||
195 | r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); | ||
196 | r = FLD_MOD(r, aud_fmt->type, 4, 4); | ||
197 | r = FLD_MOD(r, aud_fmt->justification, 3, 3); | ||
198 | r = FLD_MOD(r, aud_fmt->sample_order, 2, 2); | ||
199 | r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1); | ||
200 | r = FLD_MOD(r, aud_fmt->sample_size, 0, 0); | ||
201 | hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r); | ||
202 | } | ||
203 | |||
204 | void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, | ||
205 | struct hdmi_audio_dma *aud_dma) | ||
206 | { | ||
207 | u32 r; | ||
208 | |||
209 | DSSDBG("Enter hdmi_wp_audio_config_dma\n"); | ||
210 | |||
211 | r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2); | ||
212 | r = FLD_MOD(r, aud_dma->transfer_size, 15, 8); | ||
213 | r = FLD_MOD(r, aud_dma->block_size, 7, 0); | ||
214 | hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r); | ||
215 | |||
216 | r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL); | ||
217 | r = FLD_MOD(r, aud_dma->mode, 9, 9); | ||
218 | r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0); | ||
219 | hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r); | ||
220 | } | ||
221 | |||
222 | int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable) | ||
223 | { | ||
224 | REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); | ||
225 | |||
226 | return 0; | ||
227 | } | ||
228 | |||
229 | int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable) | ||
230 | { | ||
231 | REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); | ||
232 | |||
233 | return 0; | ||
234 | } | ||
235 | #endif | ||
236 | |||
237 | #define WP_SIZE 0x200 | ||
238 | |||
239 | int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp) | ||
240 | { | ||
241 | struct resource *res; | ||
242 | struct resource temp_res; | ||
243 | |||
244 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_wp"); | ||
245 | if (!res) { | ||
246 | DSSDBG("can't get WP mem resource by name\n"); | ||
247 | /* | ||
248 | * if hwmod/DT doesn't have the memory resource information | ||
249 | * split into HDMI sub blocks by name, we try again by getting | ||
250 | * the platform's first resource. this code will be removed when | ||
251 | * the driver can get the mem resources by name | ||
252 | */ | ||
253 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
254 | if (!res) { | ||
255 | DSSERR("can't get WP mem resource\n"); | ||
256 | return -EINVAL; | ||
257 | } | ||
258 | |||
259 | temp_res.start = res->start; | ||
260 | temp_res.end = temp_res.start + WP_SIZE - 1; | ||
261 | res = &temp_res; | ||
262 | } | ||
263 | |||
264 | wp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | ||
265 | if (!wp->base) { | ||
266 | DSSERR("can't ioremap HDMI WP\n"); | ||
267 | return -ENOMEM; | ||
268 | } | ||
269 | |||
270 | return 0; | ||
271 | } | ||
diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h deleted file mode 100644 index 45215f44617c..000000000000 --- a/drivers/video/omap2/dss/ti_hdmi.h +++ /dev/null | |||
@@ -1,187 +0,0 @@ | |||
1 | /* | ||
2 | * ti_hdmi.h | ||
3 | * | ||
4 | * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor. | ||
5 | * | ||
6 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License version 2 as published by | ||
10 | * the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
19 | */ | ||
20 | |||
21 | #ifndef _TI_HDMI_H | ||
22 | #define _TI_HDMI_H | ||
23 | |||
24 | struct hdmi_ip_data; | ||
25 | |||
26 | enum hdmi_pll_pwr { | ||
27 | HDMI_PLLPWRCMD_ALLOFF = 0, | ||
28 | HDMI_PLLPWRCMD_PLLONLY = 1, | ||
29 | HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, | ||
30 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 | ||
31 | }; | ||
32 | |||
33 | enum hdmi_core_hdmi_dvi { | ||
34 | HDMI_DVI = 0, | ||
35 | HDMI_HDMI = 1 | ||
36 | }; | ||
37 | |||
38 | enum hdmi_clk_refsel { | ||
39 | HDMI_REFSEL_PCLK = 0, | ||
40 | HDMI_REFSEL_REF1 = 1, | ||
41 | HDMI_REFSEL_REF2 = 2, | ||
42 | HDMI_REFSEL_SYSCLK = 3 | ||
43 | }; | ||
44 | |||
45 | struct hdmi_cm { | ||
46 | int code; | ||
47 | int mode; | ||
48 | }; | ||
49 | |||
50 | struct hdmi_config { | ||
51 | struct omap_video_timings timings; | ||
52 | struct hdmi_cm cm; | ||
53 | }; | ||
54 | |||
55 | /* HDMI PLL structure */ | ||
56 | struct hdmi_pll_info { | ||
57 | u16 regn; | ||
58 | u16 regm; | ||
59 | u32 regmf; | ||
60 | u16 regm2; | ||
61 | u16 regsd; | ||
62 | u16 dcofreq; | ||
63 | enum hdmi_clk_refsel refsel; | ||
64 | }; | ||
65 | |||
66 | struct ti_hdmi_ip_ops { | ||
67 | |||
68 | void (*video_configure)(struct hdmi_ip_data *ip_data); | ||
69 | |||
70 | int (*phy_enable)(struct hdmi_ip_data *ip_data); | ||
71 | |||
72 | void (*phy_disable)(struct hdmi_ip_data *ip_data); | ||
73 | |||
74 | int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len); | ||
75 | |||
76 | int (*pll_enable)(struct hdmi_ip_data *ip_data); | ||
77 | |||
78 | void (*pll_disable)(struct hdmi_ip_data *ip_data); | ||
79 | |||
80 | int (*video_enable)(struct hdmi_ip_data *ip_data); | ||
81 | |||
82 | void (*video_disable)(struct hdmi_ip_data *ip_data); | ||
83 | |||
84 | void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
85 | |||
86 | void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
87 | |||
88 | void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
89 | |||
90 | void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
91 | |||
92 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
93 | int (*audio_enable)(struct hdmi_ip_data *ip_data); | ||
94 | |||
95 | void (*audio_disable)(struct hdmi_ip_data *ip_data); | ||
96 | |||
97 | int (*audio_start)(struct hdmi_ip_data *ip_data); | ||
98 | |||
99 | void (*audio_stop)(struct hdmi_ip_data *ip_data); | ||
100 | |||
101 | int (*audio_config)(struct hdmi_ip_data *ip_data, | ||
102 | struct omap_dss_audio *audio); | ||
103 | |||
104 | int (*audio_get_dma_port)(u32 *offset, u32 *size); | ||
105 | #endif | ||
106 | |||
107 | }; | ||
108 | |||
109 | /* | ||
110 | * Refer to section 8.2 in HDMI 1.3 specification for | ||
111 | * details about infoframe databytes | ||
112 | */ | ||
113 | struct hdmi_core_infoframe_avi { | ||
114 | /* Y0, Y1 rgb,yCbCr */ | ||
115 | u8 db1_format; | ||
116 | /* A0 Active information Present */ | ||
117 | u8 db1_active_info; | ||
118 | /* B0, B1 Bar info data valid */ | ||
119 | u8 db1_bar_info_dv; | ||
120 | /* S0, S1 scan information */ | ||
121 | u8 db1_scan_info; | ||
122 | /* C0, C1 colorimetry */ | ||
123 | u8 db2_colorimetry; | ||
124 | /* M0, M1 Aspect ratio (4:3, 16:9) */ | ||
125 | u8 db2_aspect_ratio; | ||
126 | /* R0...R3 Active format aspect ratio */ | ||
127 | u8 db2_active_fmt_ar; | ||
128 | /* ITC IT content. */ | ||
129 | u8 db3_itc; | ||
130 | /* EC0, EC1, EC2 Extended colorimetry */ | ||
131 | u8 db3_ec; | ||
132 | /* Q1, Q0 Quantization range */ | ||
133 | u8 db3_q_range; | ||
134 | /* SC1, SC0 Non-uniform picture scaling */ | ||
135 | u8 db3_nup_scaling; | ||
136 | /* VIC0..6 Video format identification */ | ||
137 | u8 db4_videocode; | ||
138 | /* PR0..PR3 Pixel repetition factor */ | ||
139 | u8 db5_pixel_repeat; | ||
140 | /* Line number end of top bar */ | ||
141 | u16 db6_7_line_eoftop; | ||
142 | /* Line number start of bottom bar */ | ||
143 | u16 db8_9_line_sofbottom; | ||
144 | /* Pixel number end of left bar */ | ||
145 | u16 db10_11_pixel_eofleft; | ||
146 | /* Pixel number start of right bar */ | ||
147 | u16 db12_13_pixel_sofright; | ||
148 | }; | ||
149 | |||
150 | struct hdmi_ip_data { | ||
151 | void __iomem *base_wp; /* HDMI wrapper */ | ||
152 | unsigned long core_sys_offset; | ||
153 | unsigned long core_av_offset; | ||
154 | unsigned long pll_offset; | ||
155 | unsigned long phy_offset; | ||
156 | int irq; | ||
157 | const struct ti_hdmi_ip_ops *ops; | ||
158 | struct hdmi_config cfg; | ||
159 | struct hdmi_pll_info pll_data; | ||
160 | struct hdmi_core_infoframe_avi avi_cfg; | ||
161 | |||
162 | /* ti_hdmi_4xxx_ip private data. These should be in a separate struct */ | ||
163 | struct mutex lock; | ||
164 | }; | ||
165 | int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data); | ||
166 | void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data); | ||
167 | int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len); | ||
168 | int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data); | ||
169 | void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data); | ||
170 | int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data); | ||
171 | void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data); | ||
172 | void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data); | ||
173 | void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
174 | void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
175 | void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
176 | void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); | ||
177 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) | ||
178 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts); | ||
179 | int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data); | ||
180 | void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data); | ||
181 | int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data); | ||
182 | void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data); | ||
183 | int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, | ||
184 | struct omap_dss_audio *audio); | ||
185 | int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size); | ||
186 | #endif | ||
187 | #endif | ||
diff --git a/drivers/video/p9100.c b/drivers/video/p9100.c index 4b23af6e5c28..367cea8f43f3 100644 --- a/drivers/video/p9100.c +++ b/drivers/video/p9100.c | |||
@@ -339,8 +339,6 @@ static int p9100_remove(struct platform_device *op) | |||
339 | 339 | ||
340 | framebuffer_release(info); | 340 | framebuffer_release(info); |
341 | 341 | ||
342 | dev_set_drvdata(&op->dev, NULL); | ||
343 | |||
344 | return 0; | 342 | return 0; |
345 | } | 343 | } |
346 | 344 | ||
diff --git a/drivers/video/platinumfb.c b/drivers/video/platinumfb.c index 3d86bac62d3e..4c9299576827 100644 --- a/drivers/video/platinumfb.c +++ b/drivers/video/platinumfb.c | |||
@@ -403,7 +403,7 @@ try_again: | |||
403 | if (rc < 0) | 403 | if (rc < 0) |
404 | return rc; | 404 | return rc; |
405 | 405 | ||
406 | printk(KERN_INFO "fb%d: Apple Platinum frame buffer device\n", info->node); | 406 | fb_info(info, "Apple Platinum frame buffer device\n"); |
407 | 407 | ||
408 | return 0; | 408 | return 0; |
409 | } | 409 | } |
@@ -639,7 +639,6 @@ static int platinumfb_probe(struct platform_device* odev) | |||
639 | iounmap(pinfo->frame_buffer); | 639 | iounmap(pinfo->frame_buffer); |
640 | iounmap(pinfo->platinum_regs); | 640 | iounmap(pinfo->platinum_regs); |
641 | iounmap(pinfo->cmap_regs); | 641 | iounmap(pinfo->cmap_regs); |
642 | dev_set_drvdata(&odev->dev, NULL); | ||
643 | framebuffer_release(info); | 642 | framebuffer_release(info); |
644 | } | 643 | } |
645 | 644 | ||
diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c index 81354eeab021..3b85b647bc10 100644 --- a/drivers/video/pm2fb.c +++ b/drivers/video/pm2fb.c | |||
@@ -1694,8 +1694,8 @@ static int pm2fb_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1694 | if (retval < 0) | 1694 | if (retval < 0) |
1695 | goto err_exit_all; | 1695 | goto err_exit_all; |
1696 | 1696 | ||
1697 | printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n", | 1697 | fb_info(info, "%s frame buffer device, memory = %dK\n", |
1698 | info->node, info->fix.id, pm2fb_fix.smem_len / 1024); | 1698 | info->fix.id, pm2fb_fix.smem_len / 1024); |
1699 | 1699 | ||
1700 | /* | 1700 | /* |
1701 | * Our driver data | 1701 | * Our driver data |
@@ -1744,7 +1744,6 @@ static void pm2fb_remove(struct pci_dev *pdev) | |||
1744 | iounmap(par->v_regs); | 1744 | iounmap(par->v_regs); |
1745 | release_mem_region(fix->mmio_start, fix->mmio_len); | 1745 | release_mem_region(fix->mmio_start, fix->mmio_len); |
1746 | 1746 | ||
1747 | pci_set_drvdata(pdev, NULL); | ||
1748 | fb_dealloc_cmap(&info->cmap); | 1747 | fb_dealloc_cmap(&info->cmap); |
1749 | kfree(info->pixmap.addr); | 1748 | kfree(info->pixmap.addr); |
1750 | framebuffer_release(info); | 1749 | framebuffer_release(info); |
diff --git a/drivers/video/pm3fb.c b/drivers/video/pm3fb.c index 7718faa4a73b..4bf3273d0433 100644 --- a/drivers/video/pm3fb.c +++ b/drivers/video/pm3fb.c | |||
@@ -1445,8 +1445,7 @@ static int pm3fb_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |||
1445 | retval = -EINVAL; | 1445 | retval = -EINVAL; |
1446 | goto err_exit_all; | 1446 | goto err_exit_all; |
1447 | } | 1447 | } |
1448 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, | 1448 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
1449 | info->fix.id); | ||
1450 | pci_set_drvdata(dev, info); | 1449 | pci_set_drvdata(dev, info); |
1451 | return 0; | 1450 | return 0; |
1452 | 1451 | ||
@@ -1489,7 +1488,6 @@ static void pm3fb_remove(struct pci_dev *dev) | |||
1489 | iounmap(par->v_regs); | 1488 | iounmap(par->v_regs); |
1490 | release_mem_region(fix->mmio_start, fix->mmio_len); | 1489 | release_mem_region(fix->mmio_start, fix->mmio_len); |
1491 | 1490 | ||
1492 | pci_set_drvdata(dev, NULL); | ||
1493 | kfree(info->pixmap.addr); | 1491 | kfree(info->pixmap.addr); |
1494 | framebuffer_release(info); | 1492 | framebuffer_release(info); |
1495 | } | 1493 | } |
diff --git a/drivers/video/pmag-ba-fb.c b/drivers/video/pmag-ba-fb.c index d1e46cedb1f7..914a52ba8477 100644 --- a/drivers/video/pmag-ba-fb.c +++ b/drivers/video/pmag-ba-fb.c | |||
@@ -212,8 +212,8 @@ static int pmagbafb_probe(struct device *dev) | |||
212 | 212 | ||
213 | get_device(dev); | 213 | get_device(dev); |
214 | 214 | ||
215 | pr_info("fb%d: %s frame buffer device at %s\n", | 215 | fb_info(info, "%s frame buffer device at %s\n", |
216 | info->node, info->fix.id, dev_name(dev)); | 216 | info->fix.id, dev_name(dev)); |
217 | 217 | ||
218 | return 0; | 218 | return 0; |
219 | 219 | ||
diff --git a/drivers/video/pmagb-b-fb.c b/drivers/video/pmagb-b-fb.c index 0e1317400328..0822b6f8dddc 100644 --- a/drivers/video/pmagb-b-fb.c +++ b/drivers/video/pmagb-b-fb.c | |||
@@ -328,11 +328,10 @@ static int pmagbbfb_probe(struct device *dev) | |||
328 | snprintf(freq1, sizeof(freq1), "%u.%03uMHz", | 328 | snprintf(freq1, sizeof(freq1), "%u.%03uMHz", |
329 | par->osc1 / 1000, par->osc1 % 1000); | 329 | par->osc1 / 1000, par->osc1 % 1000); |
330 | 330 | ||
331 | pr_info("fb%d: %s frame buffer device at %s\n", | 331 | fb_info(info, "%s frame buffer device at %s\n", |
332 | info->node, info->fix.id, dev_name(dev)); | 332 | info->fix.id, dev_name(dev)); |
333 | pr_info("fb%d: Osc0: %s, Osc1: %s, Osc%u selected\n", | 333 | fb_info(info, "Osc0: %s, Osc1: %s, Osc%u selected\n", |
334 | info->node, freq0, par->osc1 ? freq1 : "disabled", | 334 | freq0, par->osc1 ? freq1 : "disabled", par->osc1 != 0); |
335 | par->osc1 != 0); | ||
336 | 335 | ||
337 | return 0; | 336 | return 0; |
338 | 337 | ||
diff --git a/drivers/video/pvr2fb.c b/drivers/video/pvr2fb.c index df07860563e6..167cffff3d4e 100644 --- a/drivers/video/pvr2fb.c +++ b/drivers/video/pvr2fb.c | |||
@@ -817,24 +817,25 @@ static int pvr2fb_common_init(void) | |||
817 | 817 | ||
818 | rev = fb_readl(par->mmio_base + 0x04); | 818 | rev = fb_readl(par->mmio_base + 0x04); |
819 | 819 | ||
820 | printk("fb%d: %s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n", | 820 | fb_info(fb_info, "%s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n", |
821 | fb_info->node, fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f, | 821 | fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f, |
822 | modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10)); | 822 | modememused >> 10, |
823 | printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n", | 823 | (unsigned long)(fb_info->fix.smem_len >> 10)); |
824 | fb_info->node, fb_info->var.xres, fb_info->var.yres, | 824 | fb_info(fb_info, "Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n", |
825 | fb_info->var.bits_per_pixel, | 825 | fb_info->var.xres, fb_info->var.yres, |
826 | get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel), | 826 | fb_info->var.bits_per_pixel, |
827 | (char *)pvr2_get_param(cables, NULL, cable_type, 3), | 827 | get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel), |
828 | (char *)pvr2_get_param(outputs, NULL, video_output, 3)); | 828 | (char *)pvr2_get_param(cables, NULL, cable_type, 3), |
829 | (char *)pvr2_get_param(outputs, NULL, video_output, 3)); | ||
829 | 830 | ||
830 | #ifdef CONFIG_SH_STORE_QUEUES | 831 | #ifdef CONFIG_SH_STORE_QUEUES |
831 | printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node); | 832 | fb_notice(fb_info, "registering with SQ API\n"); |
832 | 833 | ||
833 | pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len, | 834 | pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len, |
834 | fb_info->fix.id, PAGE_SHARED); | 835 | fb_info->fix.id, PAGE_SHARED); |
835 | 836 | ||
836 | printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n", | 837 | fb_notice(fb_info, "Mapped video memory to SQ addr 0x%lx\n", |
837 | fb_info->node, pvr2fb_map); | 838 | pvr2fb_map); |
838 | #endif | 839 | #endif |
839 | 840 | ||
840 | return 0; | 841 | return 0; |
diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c index aa9bd1f76d60..c95b9e46d48f 100644 --- a/drivers/video/pxa168fb.c +++ b/drivers/video/pxa168fb.c | |||
@@ -364,7 +364,7 @@ static void set_graphics_start(struct fb_info *info, int xoffset, int yoffset) | |||
364 | static void set_dumb_panel_control(struct fb_info *info) | 364 | static void set_dumb_panel_control(struct fb_info *info) |
365 | { | 365 | { |
366 | struct pxa168fb_info *fbi = info->par; | 366 | struct pxa168fb_info *fbi = info->par; |
367 | struct pxa168fb_mach_info *mi = fbi->dev->platform_data; | 367 | struct pxa168fb_mach_info *mi = dev_get_platdata(fbi->dev); |
368 | u32 x; | 368 | u32 x; |
369 | 369 | ||
370 | /* | 370 | /* |
@@ -407,7 +407,7 @@ static int pxa168fb_set_par(struct fb_info *info) | |||
407 | u32 x; | 407 | u32 x; |
408 | struct pxa168fb_mach_info *mi; | 408 | struct pxa168fb_mach_info *mi; |
409 | 409 | ||
410 | mi = fbi->dev->platform_data; | 410 | mi = dev_get_platdata(fbi->dev); |
411 | 411 | ||
412 | /* | 412 | /* |
413 | * Set additional mode info. | 413 | * Set additional mode info. |
@@ -609,7 +609,7 @@ static int pxa168fb_probe(struct platform_device *pdev) | |||
609 | struct clk *clk; | 609 | struct clk *clk; |
610 | int irq, ret; | 610 | int irq, ret; |
611 | 611 | ||
612 | mi = pdev->dev.platform_data; | 612 | mi = dev_get_platdata(&pdev->dev); |
613 | if (mi == NULL) { | 613 | if (mi == NULL) { |
614 | dev_err(&pdev->dev, "no platform data defined\n"); | 614 | dev_err(&pdev->dev, "no platform data defined\n"); |
615 | return -EINVAL; | 615 | return -EINVAL; |
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index eca2de45f7a6..1ecd9cec2921 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c | |||
@@ -457,7 +457,7 @@ static int pxafb_adjust_timing(struct pxafb_info *fbi, | |||
457 | static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | 457 | static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
458 | { | 458 | { |
459 | struct pxafb_info *fbi = (struct pxafb_info *)info; | 459 | struct pxafb_info *fbi = (struct pxafb_info *)info; |
460 | struct pxafb_mach_info *inf = fbi->dev->platform_data; | 460 | struct pxafb_mach_info *inf = dev_get_platdata(fbi->dev); |
461 | int err; | 461 | int err; |
462 | 462 | ||
463 | if (inf->fixed_modes) { | 463 | if (inf->fixed_modes) { |
@@ -1230,7 +1230,7 @@ static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk) | |||
1230 | static void setup_smart_timing(struct pxafb_info *fbi, | 1230 | static void setup_smart_timing(struct pxafb_info *fbi, |
1231 | struct fb_var_screeninfo *var) | 1231 | struct fb_var_screeninfo *var) |
1232 | { | 1232 | { |
1233 | struct pxafb_mach_info *inf = fbi->dev->platform_data; | 1233 | struct pxafb_mach_info *inf = dev_get_platdata(fbi->dev); |
1234 | struct pxafb_mode_info *mode = &inf->modes[0]; | 1234 | struct pxafb_mode_info *mode = &inf->modes[0]; |
1235 | unsigned long lclk = clk_get_rate(fbi->clk); | 1235 | unsigned long lclk = clk_get_rate(fbi->clk); |
1236 | unsigned t1, t2, t3, t4; | 1236 | unsigned t1, t2, t3, t4; |
@@ -1258,14 +1258,14 @@ static void setup_smart_timing(struct pxafb_info *fbi, | |||
1258 | static int pxafb_smart_thread(void *arg) | 1258 | static int pxafb_smart_thread(void *arg) |
1259 | { | 1259 | { |
1260 | struct pxafb_info *fbi = arg; | 1260 | struct pxafb_info *fbi = arg; |
1261 | struct pxafb_mach_info *inf = fbi->dev->platform_data; | 1261 | struct pxafb_mach_info *inf = dev_get_platdata(fbi->dev); |
1262 | 1262 | ||
1263 | if (!inf->smart_update) { | 1263 | if (!inf->smart_update) { |
1264 | pr_err("%s: not properly initialized, thread terminated\n", | 1264 | pr_err("%s: not properly initialized, thread terminated\n", |
1265 | __func__); | 1265 | __func__); |
1266 | return -EINVAL; | 1266 | return -EINVAL; |
1267 | } | 1267 | } |
1268 | inf = fbi->dev->platform_data; | 1268 | inf = dev_get_platdata(fbi->dev); |
1269 | 1269 | ||
1270 | pr_debug("%s(): task starting\n", __func__); | 1270 | pr_debug("%s(): task starting\n", __func__); |
1271 | 1271 | ||
@@ -1793,7 +1793,7 @@ static struct pxafb_info *pxafb_init_fbinfo(struct device *dev) | |||
1793 | { | 1793 | { |
1794 | struct pxafb_info *fbi; | 1794 | struct pxafb_info *fbi; |
1795 | void *addr; | 1795 | void *addr; |
1796 | struct pxafb_mach_info *inf = dev->platform_data; | 1796 | struct pxafb_mach_info *inf = dev_get_platdata(dev); |
1797 | 1797 | ||
1798 | /* Alloc the pxafb_info and pseudo_palette in one step */ | 1798 | /* Alloc the pxafb_info and pseudo_palette in one step */ |
1799 | fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); | 1799 | fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); |
@@ -1855,7 +1855,7 @@ static struct pxafb_info *pxafb_init_fbinfo(struct device *dev) | |||
1855 | #ifdef CONFIG_FB_PXA_PARAMETERS | 1855 | #ifdef CONFIG_FB_PXA_PARAMETERS |
1856 | static int parse_opt_mode(struct device *dev, const char *this_opt) | 1856 | static int parse_opt_mode(struct device *dev, const char *this_opt) |
1857 | { | 1857 | { |
1858 | struct pxafb_mach_info *inf = dev->platform_data; | 1858 | struct pxafb_mach_info *inf = dev_get_platdata(dev); |
1859 | 1859 | ||
1860 | const char *name = this_opt+5; | 1860 | const char *name = this_opt+5; |
1861 | unsigned int namelen = strlen(name); | 1861 | unsigned int namelen = strlen(name); |
@@ -1914,7 +1914,7 @@ done: | |||
1914 | 1914 | ||
1915 | static int parse_opt(struct device *dev, char *this_opt) | 1915 | static int parse_opt(struct device *dev, char *this_opt) |
1916 | { | 1916 | { |
1917 | struct pxafb_mach_info *inf = dev->platform_data; | 1917 | struct pxafb_mach_info *inf = dev_get_platdata(dev); |
1918 | struct pxafb_mode_info *mode = &inf->modes[0]; | 1918 | struct pxafb_mode_info *mode = &inf->modes[0]; |
1919 | char s[64]; | 1919 | char s[64]; |
1920 | 1920 | ||
@@ -2102,7 +2102,7 @@ static int pxafb_probe(struct platform_device *dev) | |||
2102 | 2102 | ||
2103 | dev_dbg(&dev->dev, "pxafb_probe\n"); | 2103 | dev_dbg(&dev->dev, "pxafb_probe\n"); |
2104 | 2104 | ||
2105 | inf = dev->dev.platform_data; | 2105 | inf = dev_get_platdata(&dev->dev); |
2106 | ret = -ENOMEM; | 2106 | ret = -ENOMEM; |
2107 | fbi = NULL; | 2107 | fbi = NULL; |
2108 | if (!inf) | 2108 | if (!inf) |
diff --git a/drivers/video/q40fb.c b/drivers/video/q40fb.c index d44c7351de0f..7487f76f6275 100644 --- a/drivers/video/q40fb.c +++ b/drivers/video/q40fb.c | |||
@@ -119,8 +119,7 @@ static int q40fb_probe(struct platform_device *dev) | |||
119 | return -EINVAL; | 119 | return -EINVAL; |
120 | } | 120 | } |
121 | 121 | ||
122 | printk(KERN_INFO "fb%d: Q40 frame buffer alive and kicking !\n", | 122 | fb_info(info, "Q40 frame buffer alive and kicking !\n"); |
123 | info->node); | ||
124 | return 0; | 123 | return 0; |
125 | } | 124 | } |
126 | 125 | ||
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c index 9536715b5a1b..a5514acd2ac6 100644 --- a/drivers/video/riva/fbdev.c +++ b/drivers/video/riva/fbdev.c | |||
@@ -1185,11 +1185,6 @@ static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
1185 | if (rivafb_do_maximize(info, var, nom, den) < 0) | 1185 | if (rivafb_do_maximize(info, var, nom, den) < 0) |
1186 | return -EINVAL; | 1186 | return -EINVAL; |
1187 | 1187 | ||
1188 | if (var->xoffset < 0) | ||
1189 | var->xoffset = 0; | ||
1190 | if (var->yoffset < 0) | ||
1191 | var->yoffset = 0; | ||
1192 | |||
1193 | /* truncate xoffset and yoffset to maximum if too high */ | 1188 | /* truncate xoffset and yoffset to maximum if too high */ |
1194 | if (var->xoffset > var->xres_virtual - var->xres) | 1189 | if (var->xoffset > var->xres_virtual - var->xres) |
1195 | var->xoffset = var->xres_virtual - var->xres - 1; | 1190 | var->xoffset = var->xres_virtual - var->xres - 1; |
diff --git a/drivers/video/s1d13xxxfb.c b/drivers/video/s1d13xxxfb.c index 05c2dc3d4bc0..83433cb0dfba 100644 --- a/drivers/video/s1d13xxxfb.c +++ b/drivers/video/s1d13xxxfb.c | |||
@@ -777,8 +777,8 @@ static int s1d13xxxfb_probe(struct platform_device *pdev) | |||
777 | printk(KERN_INFO "Epson S1D13XXX FB Driver\n"); | 777 | printk(KERN_INFO "Epson S1D13XXX FB Driver\n"); |
778 | 778 | ||
779 | /* enable platform-dependent hardware glue, if any */ | 779 | /* enable platform-dependent hardware glue, if any */ |
780 | if (pdev->dev.platform_data) | 780 | if (dev_get_platdata(&pdev->dev)) |
781 | pdata = pdev->dev.platform_data; | 781 | pdata = dev_get_platdata(&pdev->dev); |
782 | 782 | ||
783 | if (pdata && pdata->platform_init_video) | 783 | if (pdata && pdata->platform_init_video) |
784 | pdata->platform_init_video(); | 784 | pdata->platform_init_video(); |
@@ -901,8 +901,7 @@ static int s1d13xxxfb_probe(struct platform_device *pdev) | |||
901 | goto bail; | 901 | goto bail; |
902 | } | 902 | } |
903 | 903 | ||
904 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 904 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
905 | info->node, info->fix.id); | ||
906 | 905 | ||
907 | return 0; | 906 | return 0; |
908 | 907 | ||
@@ -923,8 +922,8 @@ static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state) | |||
923 | lcd_enable(s1dfb, 0); | 922 | lcd_enable(s1dfb, 0); |
924 | crt_enable(s1dfb, 0); | 923 | crt_enable(s1dfb, 0); |
925 | 924 | ||
926 | if (dev->dev.platform_data) | 925 | if (dev_get_platdata(&dev->dev)) |
927 | pdata = dev->dev.platform_data; | 926 | pdata = dev_get_platdata(&dev->dev); |
928 | 927 | ||
929 | #if 0 | 928 | #if 0 |
930 | if (!s1dfb->disp_save) | 929 | if (!s1dfb->disp_save) |
@@ -973,8 +972,8 @@ static int s1d13xxxfb_resume(struct platform_device *dev) | |||
973 | while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01)) | 972 | while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01)) |
974 | udelay(10); | 973 | udelay(10); |
975 | 974 | ||
976 | if (dev->dev.platform_data) | 975 | if (dev_get_platdata(&dev->dev)) |
977 | pdata = dev->dev.platform_data; | 976 | pdata = dev_get_platdata(&dev->dev); |
978 | 977 | ||
979 | if (s1dfb->regs_save) { | 978 | if (s1dfb->regs_save) { |
980 | /* will write RO regs, *should* get away with it :) */ | 979 | /* will write RO regs, *should* get away with it :) */ |
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c index 2e7991c7ca08..62acae2694a9 100644 --- a/drivers/video/s3c-fb.c +++ b/drivers/video/s3c-fb.c | |||
@@ -1378,7 +1378,7 @@ static int s3c_fb_probe(struct platform_device *pdev) | |||
1378 | return -EINVAL; | 1378 | return -EINVAL; |
1379 | } | 1379 | } |
1380 | 1380 | ||
1381 | pd = pdev->dev.platform_data; | 1381 | pd = dev_get_platdata(&pdev->dev); |
1382 | if (!pd) { | 1382 | if (!pd) { |
1383 | dev_err(dev, "no platform data specified\n"); | 1383 | dev_err(dev, "no platform data specified\n"); |
1384 | return -EINVAL; | 1384 | return -EINVAL; |
diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c index 21a32adbb8ea..81af5a63e9e1 100644 --- a/drivers/video/s3c2410fb.c +++ b/drivers/video/s3c2410fb.c | |||
@@ -123,7 +123,7 @@ static int s3c2410fb_check_var(struct fb_var_screeninfo *var, | |||
123 | struct fb_info *info) | 123 | struct fb_info *info) |
124 | { | 124 | { |
125 | struct s3c2410fb_info *fbi = info->par; | 125 | struct s3c2410fb_info *fbi = info->par; |
126 | struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data; | 126 | struct s3c2410fb_mach_info *mach_info = dev_get_platdata(fbi->dev); |
127 | struct s3c2410fb_display *display = NULL; | 127 | struct s3c2410fb_display *display = NULL; |
128 | struct s3c2410fb_display *default_display = mach_info->displays + | 128 | struct s3c2410fb_display *default_display = mach_info->displays + |
129 | mach_info->default_display; | 129 | mach_info->default_display; |
@@ -686,7 +686,7 @@ static inline void modify_gpio(void __iomem *reg, | |||
686 | static int s3c2410fb_init_registers(struct fb_info *info) | 686 | static int s3c2410fb_init_registers(struct fb_info *info) |
687 | { | 687 | { |
688 | struct s3c2410fb_info *fbi = info->par; | 688 | struct s3c2410fb_info *fbi = info->par; |
689 | struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data; | 689 | struct s3c2410fb_mach_info *mach_info = dev_get_platdata(fbi->dev); |
690 | unsigned long flags; | 690 | unsigned long flags; |
691 | void __iomem *regs = fbi->io; | 691 | void __iomem *regs = fbi->io; |
692 | void __iomem *tpal; | 692 | void __iomem *tpal; |
@@ -833,7 +833,7 @@ static int s3c24xxfb_probe(struct platform_device *pdev, | |||
833 | int size; | 833 | int size; |
834 | u32 lcdcon1; | 834 | u32 lcdcon1; |
835 | 835 | ||
836 | mach_info = pdev->dev.platform_data; | 836 | mach_info = dev_get_platdata(&pdev->dev); |
837 | if (mach_info == NULL) { | 837 | if (mach_info == NULL) { |
838 | dev_err(&pdev->dev, | 838 | dev_err(&pdev->dev, |
839 | "no platform data for lcd, cannot attach\n"); | 839 | "no platform data for lcd, cannot attach\n"); |
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c index d838ba829459..968b2997175a 100644 --- a/drivers/video/s3fb.c +++ b/drivers/video/s3fb.c | |||
@@ -306,8 +306,8 @@ static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map) | |||
306 | 306 | ||
307 | if ((map->width != 8) || (map->height != 16) || | 307 | if ((map->width != 8) || (map->height != 16) || |
308 | (map->depth != 1) || (map->length != 256)) { | 308 | (map->depth != 1) || (map->length != 256)) { |
309 | printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", | 309 | fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", |
310 | info->node, map->width, map->height, map->depth, map->length); | 310 | map->width, map->height, map->depth, map->length); |
311 | return; | 311 | return; |
312 | } | 312 | } |
313 | 313 | ||
@@ -476,7 +476,7 @@ static void s3_set_pixclock(struct fb_info *info, u32 pixclock) | |||
476 | rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, | 476 | rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, |
477 | 1000000000 / pixclock, &m, &n, &r, info->node); | 477 | 1000000000 / pixclock, &m, &n, &r, info->node); |
478 | if (rv < 0) { | 478 | if (rv < 0) { |
479 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); | 479 | fb_err(info, "cannot set requested pixclock, keeping old value\n"); |
480 | return; | 480 | return; |
481 | } | 481 | } |
482 | 482 | ||
@@ -569,7 +569,7 @@ static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
569 | rv = -EINVAL; | 569 | rv = -EINVAL; |
570 | 570 | ||
571 | if (rv < 0) { | 571 | if (rv < 0) { |
572 | printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); | 572 | fb_err(info, "unsupported mode requested\n"); |
573 | return rv; | 573 | return rv; |
574 | } | 574 | } |
575 | 575 | ||
@@ -587,22 +587,21 @@ static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
587 | /* Check whether have enough memory */ | 587 | /* Check whether have enough memory */ |
588 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; | 588 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; |
589 | if (mem > info->screen_size) { | 589 | if (mem > info->screen_size) { |
590 | printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", | 590 | fb_err(info, "not enough framebuffer memory (%d kB requested , %u kB available)\n", |
591 | info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); | 591 | mem >> 10, (unsigned int) (info->screen_size >> 10)); |
592 | return -EINVAL; | 592 | return -EINVAL; |
593 | } | 593 | } |
594 | 594 | ||
595 | rv = svga_check_timings (&s3_timing_regs, var, info->node); | 595 | rv = svga_check_timings (&s3_timing_regs, var, info->node); |
596 | if (rv < 0) { | 596 | if (rv < 0) { |
597 | printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); | 597 | fb_err(info, "invalid timings requested\n"); |
598 | return rv; | 598 | return rv; |
599 | } | 599 | } |
600 | 600 | ||
601 | rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, | 601 | rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, |
602 | info->node); | 602 | info->node); |
603 | if (rv < 0) { | 603 | if (rv < 0) { |
604 | printk(KERN_ERR "fb%d: invalid pixclock value requested\n", | 604 | fb_err(info, "invalid pixclock value requested\n"); |
605 | info->node); | ||
606 | return rv; | 605 | return rv; |
607 | } | 606 | } |
608 | 607 | ||
@@ -686,7 +685,7 @@ static int s3fb_set_par(struct fb_info *info) | |||
686 | 685 | ||
687 | 686 | ||
688 | /* Set the offset register */ | 687 | /* Set the offset register */ |
689 | pr_debug("fb%d: offset register : %d\n", info->node, offset_value); | 688 | fb_dbg(info, "offset register : %d\n", offset_value); |
690 | svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); | 689 | svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); |
691 | 690 | ||
692 | if (par->chip != CHIP_357_VIRGE_GX2 && | 691 | if (par->chip != CHIP_357_VIRGE_GX2 && |
@@ -769,7 +768,7 @@ static int s3fb_set_par(struct fb_info *info) | |||
769 | /* Set mode-specific register values */ | 768 | /* Set mode-specific register values */ |
770 | switch (mode) { | 769 | switch (mode) { |
771 | case 0: | 770 | case 0: |
772 | pr_debug("fb%d: text mode\n", info->node); | 771 | fb_dbg(info, "text mode\n"); |
773 | svga_set_textmode_vga_regs(par->state.vgabase); | 772 | svga_set_textmode_vga_regs(par->state.vgabase); |
774 | 773 | ||
775 | /* Set additional registers like in 8-bit mode */ | 774 | /* Set additional registers like in 8-bit mode */ |
@@ -780,12 +779,12 @@ static int s3fb_set_par(struct fb_info *info) | |||
780 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); | 779 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
781 | 780 | ||
782 | if (fasttext) { | 781 | if (fasttext) { |
783 | pr_debug("fb%d: high speed text mode set\n", info->node); | 782 | fb_dbg(info, "high speed text mode set\n"); |
784 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); | 783 | svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); |
785 | } | 784 | } |
786 | break; | 785 | break; |
787 | case 1: | 786 | case 1: |
788 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); | 787 | fb_dbg(info, "4 bit pseudocolor\n"); |
789 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); | 788 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); |
790 | 789 | ||
791 | /* Set additional registers like in 8-bit mode */ | 790 | /* Set additional registers like in 8-bit mode */ |
@@ -796,7 +795,7 @@ static int s3fb_set_par(struct fb_info *info) | |||
796 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); | 795 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
797 | break; | 796 | break; |
798 | case 2: | 797 | case 2: |
799 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); | 798 | fb_dbg(info, "4 bit pseudocolor, planar\n"); |
800 | 799 | ||
801 | /* Set additional registers like in 8-bit mode */ | 800 | /* Set additional registers like in 8-bit mode */ |
802 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); | 801 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
@@ -806,7 +805,7 @@ static int s3fb_set_par(struct fb_info *info) | |||
806 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); | 805 | svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); |
807 | break; | 806 | break; |
808 | case 3: | 807 | case 3: |
809 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); | 808 | fb_dbg(info, "8 bit pseudocolor\n"); |
810 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); | 809 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); |
811 | if (info->var.pixclock > 20000 || | 810 | if (info->var.pixclock > 20000 || |
812 | par->chip == CHIP_357_VIRGE_GX2 || | 811 | par->chip == CHIP_357_VIRGE_GX2 || |
@@ -822,7 +821,7 @@ static int s3fb_set_par(struct fb_info *info) | |||
822 | } | 821 | } |
823 | break; | 822 | break; |
824 | case 4: | 823 | case 4: |
825 | pr_debug("fb%d: 5/5/5 truecolor\n", info->node); | 824 | fb_dbg(info, "5/5/5 truecolor\n"); |
826 | if (par->chip == CHIP_988_VIRGE_VX) { | 825 | if (par->chip == CHIP_988_VIRGE_VX) { |
827 | if (info->var.pixclock > 20000) | 826 | if (info->var.pixclock > 20000) |
828 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); | 827 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); |
@@ -850,7 +849,7 @@ static int s3fb_set_par(struct fb_info *info) | |||
850 | } | 849 | } |
851 | break; | 850 | break; |
852 | case 5: | 851 | case 5: |
853 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); | 852 | fb_dbg(info, "5/6/5 truecolor\n"); |
854 | if (par->chip == CHIP_988_VIRGE_VX) { | 853 | if (par->chip == CHIP_988_VIRGE_VX) { |
855 | if (info->var.pixclock > 20000) | 854 | if (info->var.pixclock > 20000) |
856 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); | 855 | svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); |
@@ -879,16 +878,16 @@ static int s3fb_set_par(struct fb_info *info) | |||
879 | break; | 878 | break; |
880 | case 6: | 879 | case 6: |
881 | /* VIRGE VX case */ | 880 | /* VIRGE VX case */ |
882 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); | 881 | fb_dbg(info, "8/8/8 truecolor\n"); |
883 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); | 882 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); |
884 | break; | 883 | break; |
885 | case 7: | 884 | case 7: |
886 | pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node); | 885 | fb_dbg(info, "8/8/8/8 truecolor\n"); |
887 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); | 886 | svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); |
888 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); | 887 | svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); |
889 | break; | 888 | break; |
890 | default: | 889 | default: |
891 | printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node); | 890 | fb_err(info, "unsupported mode - bug\n"); |
892 | return -EINVAL; | 891 | return -EINVAL; |
893 | } | 892 | } |
894 | 893 | ||
@@ -991,27 +990,27 @@ static int s3fb_blank(int blank_mode, struct fb_info *info) | |||
991 | 990 | ||
992 | switch (blank_mode) { | 991 | switch (blank_mode) { |
993 | case FB_BLANK_UNBLANK: | 992 | case FB_BLANK_UNBLANK: |
994 | pr_debug("fb%d: unblank\n", info->node); | 993 | fb_dbg(info, "unblank\n"); |
995 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); | 994 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
996 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); | 995 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
997 | break; | 996 | break; |
998 | case FB_BLANK_NORMAL: | 997 | case FB_BLANK_NORMAL: |
999 | pr_debug("fb%d: blank\n", info->node); | 998 | fb_dbg(info, "blank\n"); |
1000 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); | 999 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); |
1001 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 1000 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
1002 | break; | 1001 | break; |
1003 | case FB_BLANK_HSYNC_SUSPEND: | 1002 | case FB_BLANK_HSYNC_SUSPEND: |
1004 | pr_debug("fb%d: hsync\n", info->node); | 1003 | fb_dbg(info, "hsync\n"); |
1005 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); | 1004 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); |
1006 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 1005 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
1007 | break; | 1006 | break; |
1008 | case FB_BLANK_VSYNC_SUSPEND: | 1007 | case FB_BLANK_VSYNC_SUSPEND: |
1009 | pr_debug("fb%d: vsync\n", info->node); | 1008 | fb_dbg(info, "vsync\n"); |
1010 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); | 1009 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); |
1011 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 1010 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
1012 | break; | 1011 | break; |
1013 | case FB_BLANK_POWERDOWN: | 1012 | case FB_BLANK_POWERDOWN: |
1014 | pr_debug("fb%d: sync down\n", info->node); | 1013 | fb_dbg(info, "sync down\n"); |
1015 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); | 1014 | svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); |
1016 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 1015 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
1017 | break; | 1016 | break; |
@@ -1352,13 +1351,16 @@ static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
1352 | goto err_reg_fb; | 1351 | goto err_reg_fb; |
1353 | } | 1352 | } |
1354 | 1353 | ||
1355 | printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id, | 1354 | fb_info(info, "%s on %s, %d MB RAM, %d MHz MCLK\n", |
1356 | pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); | 1355 | info->fix.id, pci_name(dev), |
1356 | info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); | ||
1357 | 1357 | ||
1358 | if (par->chip == CHIP_UNKNOWN) | 1358 | if (par->chip == CHIP_UNKNOWN) |
1359 | printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", | 1359 | fb_info(info, "unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n", |
1360 | info->node, vga_rcrt(par->state.vgabase, 0x2d), vga_rcrt(par->state.vgabase, 0x2e), | 1360 | vga_rcrt(par->state.vgabase, 0x2d), |
1361 | vga_rcrt(par->state.vgabase, 0x2f), vga_rcrt(par->state.vgabase, 0x30)); | 1361 | vga_rcrt(par->state.vgabase, 0x2e), |
1362 | vga_rcrt(par->state.vgabase, 0x2f), | ||
1363 | vga_rcrt(par->state.vgabase, 0x30)); | ||
1362 | 1364 | ||
1363 | /* Record a reference to the driver data */ | 1365 | /* Record a reference to the driver data */ |
1364 | pci_set_drvdata(dev, info); | 1366 | pci_set_drvdata(dev, info); |
@@ -1424,7 +1426,6 @@ static void s3_pci_remove(struct pci_dev *dev) | |||
1424 | pci_release_regions(dev); | 1426 | pci_release_regions(dev); |
1425 | /* pci_disable_device(dev); */ | 1427 | /* pci_disable_device(dev); */ |
1426 | 1428 | ||
1427 | pci_set_drvdata(dev, NULL); | ||
1428 | framebuffer_release(info); | 1429 | framebuffer_release(info); |
1429 | } | 1430 | } |
1430 | } | 1431 | } |
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c index de76da0c6429..580c444ec301 100644 --- a/drivers/video/sa1100fb.c +++ b/drivers/video/sa1100fb.c | |||
@@ -1116,7 +1116,7 @@ static struct fb_monspecs monspecs = { | |||
1116 | 1116 | ||
1117 | static struct sa1100fb_info *sa1100fb_init_fbinfo(struct device *dev) | 1117 | static struct sa1100fb_info *sa1100fb_init_fbinfo(struct device *dev) |
1118 | { | 1118 | { |
1119 | struct sa1100fb_mach_info *inf = dev->platform_data; | 1119 | struct sa1100fb_mach_info *inf = dev_get_platdata(dev); |
1120 | struct sa1100fb_info *fbi; | 1120 | struct sa1100fb_info *fbi; |
1121 | unsigned i; | 1121 | unsigned i; |
1122 | 1122 | ||
@@ -1201,7 +1201,7 @@ static int sa1100fb_probe(struct platform_device *pdev) | |||
1201 | struct resource *res; | 1201 | struct resource *res; |
1202 | int ret, irq; | 1202 | int ret, irq; |
1203 | 1203 | ||
1204 | if (!pdev->dev.platform_data) { | 1204 | if (!dev_get_platdata(&pdev->dev)) { |
1205 | dev_err(&pdev->dev, "no platform LCD data\n"); | 1205 | dev_err(&pdev->dev, "no platform LCD data\n"); |
1206 | return -EINVAL; | 1206 | return -EINVAL; |
1207 | } | 1207 | } |
diff --git a/drivers/video/savage/savagefb_driver.c b/drivers/video/savage/savagefb_driver.c index 741b2395d01e..4dbf45f3b21a 100644 --- a/drivers/video/savage/savagefb_driver.c +++ b/drivers/video/savage/savagefb_driver.c | |||
@@ -2362,12 +2362,6 @@ static void savagefb_remove(struct pci_dev *dev) | |||
2362 | kfree(info->pixmap.addr); | 2362 | kfree(info->pixmap.addr); |
2363 | pci_release_regions(dev); | 2363 | pci_release_regions(dev); |
2364 | framebuffer_release(info); | 2364 | framebuffer_release(info); |
2365 | |||
2366 | /* | ||
2367 | * Ensure that the driver data is no longer | ||
2368 | * valid. | ||
2369 | */ | ||
2370 | pci_set_drvdata(dev, NULL); | ||
2371 | } | 2365 | } |
2372 | } | 2366 | } |
2373 | 2367 | ||
diff --git a/drivers/video/sbuslib.c b/drivers/video/sbuslib.c index 296afae442f4..a350209ffbd3 100644 --- a/drivers/video/sbuslib.c +++ b/drivers/video/sbuslib.c | |||
@@ -186,7 +186,7 @@ int sbusfb_ioctl_helper(unsigned long cmd, unsigned long arg, | |||
186 | } | 186 | } |
187 | default: | 187 | default: |
188 | return -EINVAL; | 188 | return -EINVAL; |
189 | }; | 189 | } |
190 | } | 190 | } |
191 | EXPORT_SYMBOL(sbusfb_ioctl_helper); | 191 | EXPORT_SYMBOL(sbusfb_ioctl_helper); |
192 | 192 | ||
diff --git a/drivers/video/sgivwfb.c b/drivers/video/sgivwfb.c index a9ac3ce2d0e9..bc74d0408998 100644 --- a/drivers/video/sgivwfb.c +++ b/drivers/video/sgivwfb.c | |||
@@ -803,8 +803,8 @@ static int sgivwfb_probe(struct platform_device *dev) | |||
803 | 803 | ||
804 | platform_set_drvdata(dev, info); | 804 | platform_set_drvdata(dev, info); |
805 | 805 | ||
806 | printk(KERN_INFO "fb%d: SGI DBE frame buffer device, using %ldK of video memory at %#lx\n", | 806 | fb_info(info, "SGI DBE frame buffer device, using %ldK of video memory at %#lx\n", |
807 | info->node, sgivwfb_mem_size >> 10, sgivwfb_mem_phys); | 807 | sgivwfb_mem_size >> 10, sgivwfb_mem_phys); |
808 | return 0; | 808 | return 0; |
809 | 809 | ||
810 | fail_register_framebuffer: | 810 | fail_register_framebuffer: |
diff --git a/drivers/video/sh_mobile_hdmi.c b/drivers/video/sh_mobile_hdmi.c index bfe4728480fd..9a33ee0413fb 100644 --- a/drivers/video/sh_mobile_hdmi.c +++ b/drivers/video/sh_mobile_hdmi.c | |||
@@ -498,7 +498,7 @@ static void sh_hdmi_video_config(struct sh_hdmi *hdmi) | |||
498 | static void sh_hdmi_audio_config(struct sh_hdmi *hdmi) | 498 | static void sh_hdmi_audio_config(struct sh_hdmi *hdmi) |
499 | { | 499 | { |
500 | u8 data; | 500 | u8 data; |
501 | struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data; | 501 | struct sh_mobile_hdmi_info *pdata = dev_get_platdata(hdmi->dev); |
502 | 502 | ||
503 | /* | 503 | /* |
504 | * [7:4] L/R data swap control | 504 | * [7:4] L/R data swap control |
@@ -815,7 +815,7 @@ static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi, | |||
815 | unsigned long *hdmi_rate, unsigned long *parent_rate) | 815 | unsigned long *hdmi_rate, unsigned long *parent_rate) |
816 | { | 816 | { |
817 | unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error; | 817 | unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error; |
818 | struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data; | 818 | struct sh_mobile_hdmi_info *pdata = dev_get_platdata(hdmi->dev); |
819 | 819 | ||
820 | *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target); | 820 | *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target); |
821 | if ((long)*hdmi_rate < 0) | 821 | if ((long)*hdmi_rate < 0) |
@@ -1271,7 +1271,7 @@ static void sh_hdmi_htop1_init(struct sh_hdmi *hdmi) | |||
1271 | 1271 | ||
1272 | static int __init sh_hdmi_probe(struct platform_device *pdev) | 1272 | static int __init sh_hdmi_probe(struct platform_device *pdev) |
1273 | { | 1273 | { |
1274 | struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data; | 1274 | struct sh_mobile_hdmi_info *pdata = dev_get_platdata(&pdev->dev); |
1275 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1275 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1276 | struct resource *htop1_res; | 1276 | struct resource *htop1_res; |
1277 | int irq = platform_get_irq(pdev, 0), ret; | 1277 | int irq = platform_get_irq(pdev, 0), ret; |
@@ -1290,7 +1290,7 @@ static int __init sh_hdmi_probe(struct platform_device *pdev) | |||
1290 | } | 1290 | } |
1291 | } | 1291 | } |
1292 | 1292 | ||
1293 | hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL); | 1293 | hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); |
1294 | if (!hdmi) { | 1294 | if (!hdmi) { |
1295 | dev_err(&pdev->dev, "Cannot allocate device data\n"); | 1295 | dev_err(&pdev->dev, "Cannot allocate device data\n"); |
1296 | return -ENOMEM; | 1296 | return -ENOMEM; |
@@ -1304,7 +1304,7 @@ static int __init sh_hdmi_probe(struct platform_device *pdev) | |||
1304 | if (IS_ERR(hdmi->hdmi_clk)) { | 1304 | if (IS_ERR(hdmi->hdmi_clk)) { |
1305 | ret = PTR_ERR(hdmi->hdmi_clk); | 1305 | ret = PTR_ERR(hdmi->hdmi_clk); |
1306 | dev_err(&pdev->dev, "Unable to get clock: %d\n", ret); | 1306 | dev_err(&pdev->dev, "Unable to get clock: %d\n", ret); |
1307 | goto egetclk; | 1307 | return ret; |
1308 | } | 1308 | } |
1309 | 1309 | ||
1310 | /* select register access functions */ | 1310 | /* select register access functions */ |
@@ -1326,7 +1326,7 @@ static int __init sh_hdmi_probe(struct platform_device *pdev) | |||
1326 | goto erate; | 1326 | goto erate; |
1327 | } | 1327 | } |
1328 | 1328 | ||
1329 | ret = clk_enable(hdmi->hdmi_clk); | 1329 | ret = clk_prepare_enable(hdmi->hdmi_clk); |
1330 | if (ret < 0) { | 1330 | if (ret < 0) { |
1331 | dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret); | 1331 | dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret); |
1332 | goto erate; | 1332 | goto erate; |
@@ -1404,11 +1404,9 @@ emap_htop1: | |||
1404 | emap: | 1404 | emap: |
1405 | release_mem_region(res->start, resource_size(res)); | 1405 | release_mem_region(res->start, resource_size(res)); |
1406 | ereqreg: | 1406 | ereqreg: |
1407 | clk_disable(hdmi->hdmi_clk); | 1407 | clk_disable_unprepare(hdmi->hdmi_clk); |
1408 | erate: | 1408 | erate: |
1409 | clk_put(hdmi->hdmi_clk); | 1409 | clk_put(hdmi->hdmi_clk); |
1410 | egetclk: | ||
1411 | kfree(hdmi); | ||
1412 | 1410 | ||
1413 | return ret; | 1411 | return ret; |
1414 | } | 1412 | } |
@@ -1427,13 +1425,12 @@ static int __exit sh_hdmi_remove(struct platform_device *pdev) | |||
1427 | cancel_delayed_work_sync(&hdmi->edid_work); | 1425 | cancel_delayed_work_sync(&hdmi->edid_work); |
1428 | pm_runtime_put(&pdev->dev); | 1426 | pm_runtime_put(&pdev->dev); |
1429 | pm_runtime_disable(&pdev->dev); | 1427 | pm_runtime_disable(&pdev->dev); |
1430 | clk_disable(hdmi->hdmi_clk); | 1428 | clk_disable_unprepare(hdmi->hdmi_clk); |
1431 | clk_put(hdmi->hdmi_clk); | 1429 | clk_put(hdmi->hdmi_clk); |
1432 | if (hdmi->htop1) | 1430 | if (hdmi->htop1) |
1433 | iounmap(hdmi->htop1); | 1431 | iounmap(hdmi->htop1); |
1434 | iounmap(hdmi->base); | 1432 | iounmap(hdmi->base); |
1435 | release_mem_region(res->start, resource_size(res)); | 1433 | release_mem_region(res->start, resource_size(res)); |
1436 | kfree(hdmi); | ||
1437 | 1434 | ||
1438 | return 0; | 1435 | return 0; |
1439 | } | 1436 | } |
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c index 0264704a52be..ab85ad6c25ec 100644 --- a/drivers/video/sh_mobile_lcdcfb.c +++ b/drivers/video/sh_mobile_lcdcfb.c | |||
@@ -344,7 +344,7 @@ static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) | |||
344 | { | 344 | { |
345 | if (atomic_inc_and_test(&priv->hw_usecnt)) { | 345 | if (atomic_inc_and_test(&priv->hw_usecnt)) { |
346 | if (priv->dot_clk) | 346 | if (priv->dot_clk) |
347 | clk_enable(priv->dot_clk); | 347 | clk_prepare_enable(priv->dot_clk); |
348 | pm_runtime_get_sync(priv->dev); | 348 | pm_runtime_get_sync(priv->dev); |
349 | if (priv->meram_dev && priv->meram_dev->pdev) | 349 | if (priv->meram_dev && priv->meram_dev->pdev) |
350 | pm_runtime_get_sync(&priv->meram_dev->pdev->dev); | 350 | pm_runtime_get_sync(&priv->meram_dev->pdev->dev); |
@@ -358,7 +358,7 @@ static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) | |||
358 | pm_runtime_put_sync(&priv->meram_dev->pdev->dev); | 358 | pm_runtime_put_sync(&priv->meram_dev->pdev->dev); |
359 | pm_runtime_put(priv->dev); | 359 | pm_runtime_put(priv->dev); |
360 | if (priv->dot_clk) | 360 | if (priv->dot_clk) |
361 | clk_disable(priv->dot_clk); | 361 | clk_disable_unprepare(priv->dot_clk); |
362 | } | 362 | } |
363 | } | 363 | } |
364 | 364 | ||
@@ -574,8 +574,9 @@ static int sh_mobile_lcdc_display_notify(struct sh_mobile_lcdc_chan *ch, | |||
574 | switch (event) { | 574 | switch (event) { |
575 | case SH_MOBILE_LCDC_EVENT_DISPLAY_CONNECT: | 575 | case SH_MOBILE_LCDC_EVENT_DISPLAY_CONNECT: |
576 | /* HDMI plug in */ | 576 | /* HDMI plug in */ |
577 | console_lock(); | ||
577 | if (lock_fb_info(info)) { | 578 | if (lock_fb_info(info)) { |
578 | console_lock(); | 579 | |
579 | 580 | ||
580 | ch->display.width = monspec->max_x * 10; | 581 | ch->display.width = monspec->max_x * 10; |
581 | ch->display.height = monspec->max_y * 10; | 582 | ch->display.height = monspec->max_y * 10; |
@@ -594,19 +595,20 @@ static int sh_mobile_lcdc_display_notify(struct sh_mobile_lcdc_chan *ch, | |||
594 | fb_set_suspend(info, 0); | 595 | fb_set_suspend(info, 0); |
595 | } | 596 | } |
596 | 597 | ||
597 | console_unlock(); | 598 | |
598 | unlock_fb_info(info); | 599 | unlock_fb_info(info); |
599 | } | 600 | } |
601 | console_unlock(); | ||
600 | break; | 602 | break; |
601 | 603 | ||
602 | case SH_MOBILE_LCDC_EVENT_DISPLAY_DISCONNECT: | 604 | case SH_MOBILE_LCDC_EVENT_DISPLAY_DISCONNECT: |
603 | /* HDMI disconnect */ | 605 | /* HDMI disconnect */ |
606 | console_lock(); | ||
604 | if (lock_fb_info(info)) { | 607 | if (lock_fb_info(info)) { |
605 | console_lock(); | ||
606 | fb_set_suspend(info, 1); | 608 | fb_set_suspend(info, 1); |
607 | console_unlock(); | ||
608 | unlock_fb_info(info); | 609 | unlock_fb_info(info); |
609 | } | 610 | } |
611 | console_unlock(); | ||
610 | break; | 612 | break; |
611 | 613 | ||
612 | case SH_MOBILE_LCDC_EVENT_DISPLAY_MODE: | 614 | case SH_MOBILE_LCDC_EVENT_DISPLAY_MODE: |
diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 8d7810613058..210f3a02121a 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c | |||
@@ -66,8 +66,15 @@ static int simplefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |||
66 | return 0; | 66 | return 0; |
67 | } | 67 | } |
68 | 68 | ||
69 | static void simplefb_destroy(struct fb_info *info) | ||
70 | { | ||
71 | if (info->screen_base) | ||
72 | iounmap(info->screen_base); | ||
73 | } | ||
74 | |||
69 | static struct fb_ops simplefb_ops = { | 75 | static struct fb_ops simplefb_ops = { |
70 | .owner = THIS_MODULE, | 76 | .owner = THIS_MODULE, |
77 | .fb_destroy = simplefb_destroy, | ||
71 | .fb_setcolreg = simplefb_setcolreg, | 78 | .fb_setcolreg = simplefb_setcolreg, |
72 | .fb_fillrect = cfb_fillrect, | 79 | .fb_fillrect = cfb_fillrect, |
73 | .fb_copyarea = cfb_copyarea, | 80 | .fb_copyarea = cfb_copyarea, |
@@ -132,7 +139,7 @@ static int simplefb_parse_dt(struct platform_device *pdev, | |||
132 | static int simplefb_parse_pd(struct platform_device *pdev, | 139 | static int simplefb_parse_pd(struct platform_device *pdev, |
133 | struct simplefb_params *params) | 140 | struct simplefb_params *params) |
134 | { | 141 | { |
135 | struct simplefb_platform_data *pd = pdev->dev.platform_data; | 142 | struct simplefb_platform_data *pd = dev_get_platdata(&pdev->dev); |
136 | int i; | 143 | int i; |
137 | 144 | ||
138 | params->width = pd->width; | 145 | params->width = pd->width; |
@@ -167,7 +174,7 @@ static int simplefb_probe(struct platform_device *pdev) | |||
167 | return -ENODEV; | 174 | return -ENODEV; |
168 | 175 | ||
169 | ret = -ENODEV; | 176 | ret = -ENODEV; |
170 | if (pdev->dev.platform_data) | 177 | if (dev_get_platdata(&pdev->dev)) |
171 | ret = simplefb_parse_pd(pdev, ¶ms); | 178 | ret = simplefb_parse_pd(pdev, ¶ms); |
172 | else if (pdev->dev.of_node) | 179 | else if (pdev->dev.of_node) |
173 | ret = simplefb_parse_dt(pdev, ¶ms); | 180 | ret = simplefb_parse_dt(pdev, ¶ms); |
@@ -212,17 +219,26 @@ static int simplefb_probe(struct platform_device *pdev) | |||
212 | 219 | ||
213 | info->fbops = &simplefb_ops; | 220 | info->fbops = &simplefb_ops; |
214 | info->flags = FBINFO_DEFAULT | FBINFO_MISC_FIRMWARE; | 221 | info->flags = FBINFO_DEFAULT | FBINFO_MISC_FIRMWARE; |
215 | info->screen_base = devm_ioremap(&pdev->dev, info->fix.smem_start, | 222 | info->screen_base = ioremap_wc(info->fix.smem_start, |
216 | info->fix.smem_len); | 223 | info->fix.smem_len); |
217 | if (!info->screen_base) { | 224 | if (!info->screen_base) { |
218 | framebuffer_release(info); | 225 | framebuffer_release(info); |
219 | return -ENODEV; | 226 | return -ENODEV; |
220 | } | 227 | } |
221 | info->pseudo_palette = (void *)(info + 1); | 228 | info->pseudo_palette = (void *)(info + 1); |
222 | 229 | ||
230 | dev_info(&pdev->dev, "framebuffer at 0x%lx, 0x%x bytes, mapped to 0x%p\n", | ||
231 | info->fix.smem_start, info->fix.smem_len, | ||
232 | info->screen_base); | ||
233 | dev_info(&pdev->dev, "format=%s, mode=%dx%dx%d, linelength=%d\n", | ||
234 | params.format->name, | ||
235 | info->var.xres, info->var.yres, | ||
236 | info->var.bits_per_pixel, info->fix.line_length); | ||
237 | |||
223 | ret = register_framebuffer(info); | 238 | ret = register_framebuffer(info); |
224 | if (ret < 0) { | 239 | if (ret < 0) { |
225 | dev_err(&pdev->dev, "Unable to register simplefb: %d\n", ret); | 240 | dev_err(&pdev->dev, "Unable to register simplefb: %d\n", ret); |
241 | iounmap(info->screen_base); | ||
226 | framebuffer_release(info); | 242 | framebuffer_release(info); |
227 | return ret; | 243 | return ret; |
228 | } | 244 | } |
diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index 977e27927a21..22ad028bf123 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c | |||
@@ -5994,7 +5994,6 @@ static int sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
5994 | if(!ivideo->sisvga_enabled) { | 5994 | if(!ivideo->sisvga_enabled) { |
5995 | if(pci_enable_device(pdev)) { | 5995 | if(pci_enable_device(pdev)) { |
5996 | if(ivideo->nbridge) pci_dev_put(ivideo->nbridge); | 5996 | if(ivideo->nbridge) pci_dev_put(ivideo->nbridge); |
5997 | pci_set_drvdata(pdev, NULL); | ||
5998 | framebuffer_release(sis_fb_info); | 5997 | framebuffer_release(sis_fb_info); |
5999 | return -EIO; | 5998 | return -EIO; |
6000 | } | 5999 | } |
@@ -6211,7 +6210,6 @@ error_3: vfree(ivideo->bios_abase); | |||
6211 | pci_dev_put(ivideo->lpcdev); | 6210 | pci_dev_put(ivideo->lpcdev); |
6212 | if(ivideo->nbridge) | 6211 | if(ivideo->nbridge) |
6213 | pci_dev_put(ivideo->nbridge); | 6212 | pci_dev_put(ivideo->nbridge); |
6214 | pci_set_drvdata(pdev, NULL); | ||
6215 | if(!ivideo->sisvga_enabled) | 6213 | if(!ivideo->sisvga_enabled) |
6216 | pci_disable_device(pdev); | 6214 | pci_disable_device(pdev); |
6217 | framebuffer_release(sis_fb_info); | 6215 | framebuffer_release(sis_fb_info); |
@@ -6480,8 +6478,8 @@ error_3: vfree(ivideo->bios_abase); | |||
6480 | "disabled"); | 6478 | "disabled"); |
6481 | 6479 | ||
6482 | 6480 | ||
6483 | printk(KERN_INFO "fb%d: %s frame buffer device version %d.%d.%d\n", | 6481 | fb_info(sis_fb_info, "%s frame buffer device version %d.%d.%d\n", |
6484 | sis_fb_info->node, ivideo->myid, VER_MAJOR, VER_MINOR, VER_LEVEL); | 6482 | ivideo->myid, VER_MAJOR, VER_MINOR, VER_LEVEL); |
6485 | 6483 | ||
6486 | printk(KERN_INFO "sisfb: Copyright (C) 2001-2005 Thomas Winischhofer\n"); | 6484 | printk(KERN_INFO "sisfb: Copyright (C) 2001-2005 Thomas Winischhofer\n"); |
6487 | 6485 | ||
@@ -6523,8 +6521,6 @@ static void sisfb_remove(struct pci_dev *pdev) | |||
6523 | mtrr_del(ivideo->mtrr, ivideo->video_base, ivideo->video_size); | 6521 | mtrr_del(ivideo->mtrr, ivideo->video_base, ivideo->video_size); |
6524 | #endif | 6522 | #endif |
6525 | 6523 | ||
6526 | pci_set_drvdata(pdev, NULL); | ||
6527 | |||
6528 | /* If device was disabled when starting, disable | 6524 | /* If device was disabled when starting, disable |
6529 | * it when quitting. | 6525 | * it when quitting. |
6530 | */ | 6526 | */ |
diff --git a/drivers/video/skeletonfb.c b/drivers/video/skeletonfb.c index 2d4694c6b9e0..fefde7c6add7 100644 --- a/drivers/video/skeletonfb.c +++ b/drivers/video/skeletonfb.c | |||
@@ -824,8 +824,7 @@ static int xxxfb_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |||
824 | fb_dealloc_cmap(&info->cmap); | 824 | fb_dealloc_cmap(&info->cmap); |
825 | return -EINVAL; | 825 | return -EINVAL; |
826 | } | 826 | } |
827 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, | 827 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
828 | info->fix.id); | ||
829 | pci_set_drvdata(dev, info); /* or platform_set_drvdata(pdev, info) */ | 828 | pci_set_drvdata(dev, info); /* or platform_set_drvdata(pdev, info) */ |
830 | return 0; | 829 | return 0; |
831 | } | 830 | } |
diff --git a/drivers/video/smscufx.c b/drivers/video/smscufx.c index e188ada2ffd1..d513ed6a49f2 100644 --- a/drivers/video/smscufx.c +++ b/drivers/video/smscufx.c | |||
@@ -1147,7 +1147,7 @@ static void ufx_free_framebuffer_work(struct work_struct *work) | |||
1147 | 1147 | ||
1148 | fb_destroy_modelist(&info->modelist); | 1148 | fb_destroy_modelist(&info->modelist); |
1149 | 1149 | ||
1150 | dev->info = 0; | 1150 | dev->info = NULL; |
1151 | 1151 | ||
1152 | /* Assume info structure is freed after this point */ | 1152 | /* Assume info structure is freed after this point */ |
1153 | framebuffer_release(info); | 1153 | framebuffer_release(info); |
diff --git a/drivers/video/ssd1307fb.c b/drivers/video/ssd1307fb.c index 44967c8fef2b..f4daa59f0a80 100644 --- a/drivers/video/ssd1307fb.c +++ b/drivers/video/ssd1307fb.c | |||
@@ -569,7 +569,7 @@ static struct i2c_driver ssd1307fb_driver = { | |||
569 | .id_table = ssd1307fb_i2c_id, | 569 | .id_table = ssd1307fb_i2c_id, |
570 | .driver = { | 570 | .driver = { |
571 | .name = "ssd1307fb", | 571 | .name = "ssd1307fb", |
572 | .of_match_table = of_match_ptr(ssd1307fb_of_match), | 572 | .of_match_table = ssd1307fb_of_match, |
573 | .owner = THIS_MODULE, | 573 | .owner = THIS_MODULE, |
574 | }, | 574 | }, |
575 | }; | 575 | }; |
diff --git a/drivers/video/sstfb.c b/drivers/video/sstfb.c index 9c00026e3ae2..f0cb279ef333 100644 --- a/drivers/video/sstfb.c +++ b/drivers/video/sstfb.c | |||
@@ -706,10 +706,10 @@ static void sstfb_setvgapass( struct fb_info *info, int enable ) | |||
706 | fbiinit0 = sst_read (FBIINIT0); | 706 | fbiinit0 = sst_read (FBIINIT0); |
707 | if (par->vgapass) { | 707 | if (par->vgapass) { |
708 | sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH); | 708 | sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH); |
709 | printk(KERN_INFO "fb%d: Enabling VGA pass-through\n", info->node ); | 709 | fb_info(info, "Enabling VGA pass-through\n"); |
710 | } else { | 710 | } else { |
711 | sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH); | 711 | sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH); |
712 | printk(KERN_INFO "fb%d: Disabling VGA pass-through\n", info->node ); | 712 | fb_info(info, "Disabling VGA pass-through\n"); |
713 | } | 713 | } |
714 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp); | 714 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp); |
715 | } | 715 | } |
@@ -1437,8 +1437,8 @@ static int sstfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1437 | printk(KERN_WARNING "sstfb: can't create sysfs entry.\n"); | 1437 | printk(KERN_WARNING "sstfb: can't create sysfs entry.\n"); |
1438 | 1438 | ||
1439 | 1439 | ||
1440 | printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n", | 1440 | fb_info(info, "%s frame buffer device at 0x%p\n", |
1441 | info->node, fix->id, info->screen_base); | 1441 | fix->id, info->screen_base); |
1442 | 1442 | ||
1443 | return 0; | 1443 | return 0; |
1444 | 1444 | ||
diff --git a/drivers/video/stifb.c b/drivers/video/stifb.c index 019a1feef995..cfe8a2f905c5 100644 --- a/drivers/video/stifb.c +++ b/drivers/video/stifb.c | |||
@@ -1283,9 +1283,7 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref) | |||
1283 | 1283 | ||
1284 | sti->info = info; /* save for unregister_framebuffer() */ | 1284 | sti->info = info; /* save for unregister_framebuffer() */ |
1285 | 1285 | ||
1286 | printk(KERN_INFO | 1286 | fb_info(&fb->info, "%s %dx%d-%d frame buffer device, %s, id: %04x, mmio: 0x%04lx\n", |
1287 | "fb%d: %s %dx%d-%d frame buffer device, %s, id: %04x, mmio: 0x%04lx\n", | ||
1288 | fb->info.node, | ||
1289 | fix->id, | 1287 | fix->id, |
1290 | var->xres, | 1288 | var->xres, |
1291 | var->yres, | 1289 | var->yres, |
diff --git a/drivers/video/sunxvr1000.c b/drivers/video/sunxvr1000.c index cc6f48bba36b..58241b47a96d 100644 --- a/drivers/video/sunxvr1000.c +++ b/drivers/video/sunxvr1000.c | |||
@@ -186,8 +186,6 @@ static int gfb_remove(struct platform_device *op) | |||
186 | 186 | ||
187 | framebuffer_release(info); | 187 | framebuffer_release(info); |
188 | 188 | ||
189 | dev_set_drvdata(&op->dev, NULL); | ||
190 | |||
191 | return 0; | 189 | return 0; |
192 | } | 190 | } |
193 | 191 | ||
diff --git a/drivers/video/svgalib.c b/drivers/video/svgalib.c index 33df9ec91795..9e01322fabe3 100644 --- a/drivers/video/svgalib.c +++ b/drivers/video/svgalib.c | |||
@@ -198,8 +198,8 @@ void svga_settile(struct fb_info *info, struct fb_tilemap *map) | |||
198 | 198 | ||
199 | if ((map->width != 8) || (map->height != 16) || | 199 | if ((map->width != 8) || (map->height != 16) || |
200 | (map->depth != 1) || (map->length != 256)) { | 200 | (map->depth != 1) || (map->length != 256)) { |
201 | printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n", | 201 | fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", |
202 | info->node, map->width, map->height, map->depth, map->length); | 202 | map->width, map->height, map->depth, map->length); |
203 | return; | 203 | return; |
204 | } | 204 | } |
205 | 205 | ||
diff --git a/drivers/video/sysimgblt.c b/drivers/video/sysimgblt.c index 186c6f607be2..a4d05b1b17d7 100644 --- a/drivers/video/sysimgblt.c +++ b/drivers/video/sysimgblt.c | |||
@@ -152,7 +152,7 @@ static void slow_imageblit(const struct fb_image *image, struct fb_info *p, | |||
152 | } | 152 | } |
153 | shift += bpp; | 153 | shift += bpp; |
154 | shift &= (32 - 1); | 154 | shift &= (32 - 1); |
155 | if (!l) { l = 8; s++; }; | 155 | if (!l) { l = 8; s++; } |
156 | } | 156 | } |
157 | 157 | ||
158 | /* write trailing bits */ | 158 | /* write trailing bits */ |
diff --git a/drivers/video/tcx.c b/drivers/video/tcx.c index c000852500aa..7fb2d696fac7 100644 --- a/drivers/video/tcx.c +++ b/drivers/video/tcx.c | |||
@@ -232,7 +232,7 @@ tcx_blank(int blank, struct fb_info *info) | |||
232 | 232 | ||
233 | case FB_BLANK_POWERDOWN: /* Poweroff */ | 233 | case FB_BLANK_POWERDOWN: /* Poweroff */ |
234 | break; | 234 | break; |
235 | }; | 235 | } |
236 | 236 | ||
237 | sbus_writel(val, &thc->thc_misc); | 237 | sbus_writel(val, &thc->thc_misc); |
238 | 238 | ||
@@ -434,7 +434,7 @@ static int tcx_probe(struct platform_device *op) | |||
434 | default: | 434 | default: |
435 | j = i; | 435 | j = i; |
436 | break; | 436 | break; |
437 | }; | 437 | } |
438 | par->mmap_map[i].poff = op->resource[j].start; | 438 | par->mmap_map[i].poff = op->resource[j].start; |
439 | } | 439 | } |
440 | 440 | ||
@@ -498,8 +498,6 @@ static int tcx_remove(struct platform_device *op) | |||
498 | 498 | ||
499 | framebuffer_release(info); | 499 | framebuffer_release(info); |
500 | 500 | ||
501 | dev_set_drvdata(&op->dev, NULL); | ||
502 | |||
503 | return 0; | 501 | return 0; |
504 | } | 502 | } |
505 | 503 | ||
diff --git a/drivers/video/tdfxfb.c b/drivers/video/tdfxfb.c index 64bc28ba4037..f761fe375f5b 100644 --- a/drivers/video/tdfxfb.c +++ b/drivers/video/tdfxfb.c | |||
@@ -1646,7 +1646,6 @@ static void tdfxfb_remove(struct pci_dev *pdev) | |||
1646 | pci_resource_len(pdev, 1)); | 1646 | pci_resource_len(pdev, 1)); |
1647 | release_mem_region(pci_resource_start(pdev, 0), | 1647 | release_mem_region(pci_resource_start(pdev, 0), |
1648 | pci_resource_len(pdev, 0)); | 1648 | pci_resource_len(pdev, 0)); |
1649 | pci_set_drvdata(pdev, NULL); | ||
1650 | fb_dealloc_cmap(&info->cmap); | 1649 | fb_dealloc_cmap(&info->cmap); |
1651 | framebuffer_release(info); | 1650 | framebuffer_release(info); |
1652 | } | 1651 | } |
diff --git a/drivers/video/tgafb.c b/drivers/video/tgafb.c index c9c8e5a1fdee..f28674fea909 100644 --- a/drivers/video/tgafb.c +++ b/drivers/video/tgafb.c | |||
@@ -1671,8 +1671,8 @@ static int tgafb_register(struct device *dev) | |||
1671 | if (tga_bus_tc) | 1671 | if (tga_bus_tc) |
1672 | pr_info("tgafb: SFB+ detected, rev=0x%02x\n", | 1672 | pr_info("tgafb: SFB+ detected, rev=0x%02x\n", |
1673 | par->tga_chip_rev); | 1673 | par->tga_chip_rev); |
1674 | pr_info("fb%d: %s frame buffer device at 0x%lx\n", | 1674 | fb_info(info, "%s frame buffer device at 0x%lx\n", |
1675 | info->node, info->fix.id, (long)bar0_start); | 1675 | info->fix.id, (long)bar0_start); |
1676 | 1676 | ||
1677 | return 0; | 1677 | return 0; |
1678 | 1678 | ||
diff --git a/drivers/video/tmiofb.c b/drivers/video/tmiofb.c index deb8733f3c70..7fb4e321a431 100644 --- a/drivers/video/tmiofb.c +++ b/drivers/video/tmiofb.c | |||
@@ -250,7 +250,7 @@ static irqreturn_t tmiofb_irq(int irq, void *__info) | |||
250 | */ | 250 | */ |
251 | static int tmiofb_hw_stop(struct platform_device *dev) | 251 | static int tmiofb_hw_stop(struct platform_device *dev) |
252 | { | 252 | { |
253 | struct tmio_fb_data *data = dev->dev.platform_data; | 253 | struct tmio_fb_data *data = dev_get_platdata(&dev->dev); |
254 | struct fb_info *info = platform_get_drvdata(dev); | 254 | struct fb_info *info = platform_get_drvdata(dev); |
255 | struct tmiofb_par *par = info->par; | 255 | struct tmiofb_par *par = info->par; |
256 | 256 | ||
@@ -311,7 +311,7 @@ static int tmiofb_hw_init(struct platform_device *dev) | |||
311 | */ | 311 | */ |
312 | static void tmiofb_hw_mode(struct platform_device *dev) | 312 | static void tmiofb_hw_mode(struct platform_device *dev) |
313 | { | 313 | { |
314 | struct tmio_fb_data *data = dev->dev.platform_data; | 314 | struct tmio_fb_data *data = dev_get_platdata(&dev->dev); |
315 | struct fb_info *info = platform_get_drvdata(dev); | 315 | struct fb_info *info = platform_get_drvdata(dev); |
316 | struct fb_videomode *mode = info->mode; | 316 | struct fb_videomode *mode = info->mode; |
317 | struct tmiofb_par *par = info->par; | 317 | struct tmiofb_par *par = info->par; |
@@ -557,7 +557,7 @@ static int tmiofb_ioctl(struct fb_info *fbi, | |||
557 | static struct fb_videomode * | 557 | static struct fb_videomode * |
558 | tmiofb_find_mode(struct fb_info *info, struct fb_var_screeninfo *var) | 558 | tmiofb_find_mode(struct fb_info *info, struct fb_var_screeninfo *var) |
559 | { | 559 | { |
560 | struct tmio_fb_data *data = info->device->platform_data; | 560 | struct tmio_fb_data *data = dev_get_platdata(info->device); |
561 | struct fb_videomode *best = NULL; | 561 | struct fb_videomode *best = NULL; |
562 | int i; | 562 | int i; |
563 | 563 | ||
@@ -577,7 +577,7 @@ static int tmiofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
577 | { | 577 | { |
578 | 578 | ||
579 | struct fb_videomode *mode; | 579 | struct fb_videomode *mode; |
580 | struct tmio_fb_data *data = info->device->platform_data; | 580 | struct tmio_fb_data *data = dev_get_platdata(info->device); |
581 | 581 | ||
582 | mode = tmiofb_find_mode(info, var); | 582 | mode = tmiofb_find_mode(info, var); |
583 | if (!mode || var->bits_per_pixel > 16) | 583 | if (!mode || var->bits_per_pixel > 16) |
@@ -678,7 +678,7 @@ static struct fb_ops tmiofb_ops = { | |||
678 | static int tmiofb_probe(struct platform_device *dev) | 678 | static int tmiofb_probe(struct platform_device *dev) |
679 | { | 679 | { |
680 | const struct mfd_cell *cell = mfd_get_cell(dev); | 680 | const struct mfd_cell *cell = mfd_get_cell(dev); |
681 | struct tmio_fb_data *data = dev->dev.platform_data; | 681 | struct tmio_fb_data *data = dev_get_platdata(&dev->dev); |
682 | struct resource *ccr = platform_get_resource(dev, IORESOURCE_MEM, 1); | 682 | struct resource *ccr = platform_get_resource(dev, IORESOURCE_MEM, 1); |
683 | struct resource *lcr = platform_get_resource(dev, IORESOURCE_MEM, 0); | 683 | struct resource *lcr = platform_get_resource(dev, IORESOURCE_MEM, 0); |
684 | struct resource *vram = platform_get_resource(dev, IORESOURCE_MEM, 2); | 684 | struct resource *vram = platform_get_resource(dev, IORESOURCE_MEM, 2); |
@@ -781,8 +781,7 @@ static int tmiofb_probe(struct platform_device *dev) | |||
781 | if (retval < 0) | 781 | if (retval < 0) |
782 | goto err_register_framebuffer; | 782 | goto err_register_framebuffer; |
783 | 783 | ||
784 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 784 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
785 | info->node, info->fix.id); | ||
786 | 785 | ||
787 | return 0; | 786 | return 0; |
788 | 787 | ||
diff --git a/drivers/video/tridentfb.c b/drivers/video/tridentfb.c index ab57d387d6b5..7ed9a227f5ea 100644 --- a/drivers/video/tridentfb.c +++ b/drivers/video/tridentfb.c | |||
@@ -1553,7 +1553,6 @@ static void trident_pci_remove(struct pci_dev *dev) | |||
1553 | iounmap(info->screen_base); | 1553 | iounmap(info->screen_base); |
1554 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); | 1554 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
1555 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); | 1555 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
1556 | pci_set_drvdata(dev, NULL); | ||
1557 | kfree(info->pixmap.addr); | 1556 | kfree(info->pixmap.addr); |
1558 | fb_dealloc_cmap(&info->cmap); | 1557 | fb_dealloc_cmap(&info->cmap); |
1559 | framebuffer_release(info); | 1558 | framebuffer_release(info); |
diff --git a/drivers/video/udlfb.c b/drivers/video/udlfb.c index d2e5bc3cf969..025f14e30eed 100644 --- a/drivers/video/udlfb.c +++ b/drivers/video/udlfb.c | |||
@@ -1166,7 +1166,7 @@ static int dlfb_realloc_framebuffer(struct dlfb_data *dev, struct fb_info *info) | |||
1166 | int new_len; | 1166 | int new_len; |
1167 | unsigned char *old_fb = info->screen_base; | 1167 | unsigned char *old_fb = info->screen_base; |
1168 | unsigned char *new_fb; | 1168 | unsigned char *new_fb; |
1169 | unsigned char *new_back = 0; | 1169 | unsigned char *new_back = NULL; |
1170 | 1170 | ||
1171 | pr_warn("Reallocating framebuffer. Addresses will change!\n"); | 1171 | pr_warn("Reallocating framebuffer. Addresses will change!\n"); |
1172 | 1172 | ||
diff --git a/drivers/video/uvesafb.c b/drivers/video/uvesafb.c index 7aec6f39fdd5..256fba7f4641 100644 --- a/drivers/video/uvesafb.c +++ b/drivers/video/uvesafb.c | |||
@@ -233,8 +233,7 @@ out: | |||
233 | static void uvesafb_free(struct uvesafb_ktask *task) | 233 | static void uvesafb_free(struct uvesafb_ktask *task) |
234 | { | 234 | { |
235 | if (task) { | 235 | if (task) { |
236 | if (task->done) | 236 | kfree(task->done); |
237 | kfree(task->done); | ||
238 | kfree(task); | 237 | kfree(task); |
239 | } | 238 | } |
240 | } | 239 | } |
@@ -1332,8 +1331,8 @@ setmode: | |||
1332 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | 1331 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
1333 | info->fix.line_length = mode->bytes_per_scan_line; | 1332 | info->fix.line_length = mode->bytes_per_scan_line; |
1334 | 1333 | ||
1335 | out: if (crtc != NULL) | 1334 | out: |
1336 | kfree(crtc); | 1335 | kfree(crtc); |
1337 | uvesafb_free(task); | 1336 | uvesafb_free(task); |
1338 | 1337 | ||
1339 | return err; | 1338 | return err; |
@@ -1771,13 +1770,11 @@ static int uvesafb_probe(struct platform_device *dev) | |||
1771 | "using %dk, total %dk\n", info->fix.smem_start, | 1770 | "using %dk, total %dk\n", info->fix.smem_start, |
1772 | info->screen_base, info->fix.smem_len/1024, | 1771 | info->screen_base, info->fix.smem_len/1024, |
1773 | par->vbe_ib.total_memory * 64); | 1772 | par->vbe_ib.total_memory * 64); |
1774 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, | 1773 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
1775 | info->fix.id); | ||
1776 | 1774 | ||
1777 | err = sysfs_create_group(&dev->dev.kobj, &uvesafb_dev_attgrp); | 1775 | err = sysfs_create_group(&dev->dev.kobj, &uvesafb_dev_attgrp); |
1778 | if (err != 0) | 1776 | if (err != 0) |
1779 | printk(KERN_WARNING "fb%d: failed to register attributes\n", | 1777 | fb_warn(info, "failed to register attributes\n"); |
1780 | info->node); | ||
1781 | 1778 | ||
1782 | return 0; | 1779 | return 0; |
1783 | 1780 | ||
@@ -1793,8 +1790,7 @@ out_mode: | |||
1793 | fb_destroy_modedb(info->monspecs.modedb); | 1790 | fb_destroy_modedb(info->monspecs.modedb); |
1794 | fb_dealloc_cmap(&info->cmap); | 1791 | fb_dealloc_cmap(&info->cmap); |
1795 | out: | 1792 | out: |
1796 | if (par->vbe_modes) | 1793 | kfree(par->vbe_modes); |
1797 | kfree(par->vbe_modes); | ||
1798 | 1794 | ||
1799 | framebuffer_release(info); | 1795 | framebuffer_release(info); |
1800 | return err; | 1796 | return err; |
@@ -1817,12 +1813,9 @@ static int uvesafb_remove(struct platform_device *dev) | |||
1817 | fb_dealloc_cmap(&info->cmap); | 1813 | fb_dealloc_cmap(&info->cmap); |
1818 | 1814 | ||
1819 | if (par) { | 1815 | if (par) { |
1820 | if (par->vbe_modes) | 1816 | kfree(par->vbe_modes); |
1821 | kfree(par->vbe_modes); | 1817 | kfree(par->vbe_state_orig); |
1822 | if (par->vbe_state_orig) | 1818 | kfree(par->vbe_state_saved); |
1823 | kfree(par->vbe_state_orig); | ||
1824 | if (par->vbe_state_saved) | ||
1825 | kfree(par->vbe_state_saved); | ||
1826 | } | 1819 | } |
1827 | 1820 | ||
1828 | framebuffer_release(info); | 1821 | framebuffer_release(info); |
diff --git a/drivers/video/valkyriefb.c b/drivers/video/valkyriefb.c index 3f5a041601da..e287ebc47817 100644 --- a/drivers/video/valkyriefb.c +++ b/drivers/video/valkyriefb.c | |||
@@ -392,7 +392,7 @@ int __init valkyriefb_init(void) | |||
392 | if ((err = register_framebuffer(&p->info)) != 0) | 392 | if ((err = register_framebuffer(&p->info)) != 0) |
393 | goto out_cmap_free; | 393 | goto out_cmap_free; |
394 | 394 | ||
395 | printk(KERN_INFO "fb%d: valkyrie frame buffer device\n", p->info.node); | 395 | fb_info(&p->info, "valkyrie frame buffer device\n"); |
396 | return 0; | 396 | return 0; |
397 | 397 | ||
398 | out_cmap_free: | 398 | out_cmap_free: |
diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c index bd83233ec227..1c7da3b098d6 100644 --- a/drivers/video/vesafb.c +++ b/drivers/video/vesafb.c | |||
@@ -489,8 +489,7 @@ static int vesafb_probe(struct platform_device *dev) | |||
489 | fb_dealloc_cmap(&info->cmap); | 489 | fb_dealloc_cmap(&info->cmap); |
490 | goto err; | 490 | goto err; |
491 | } | 491 | } |
492 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 492 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
493 | info->node, info->fix.id); | ||
494 | return 0; | 493 | return 0; |
495 | err: | 494 | err: |
496 | if (info->screen_base) | 495 | if (info->screen_base) |
diff --git a/drivers/video/vfb.c b/drivers/video/vfb.c index ee5985efa15c..70a897b1e458 100644 --- a/drivers/video/vfb.c +++ b/drivers/video/vfb.c | |||
@@ -390,9 +390,8 @@ static int vfb_pan_display(struct fb_var_screeninfo *var, | |||
390 | struct fb_info *info) | 390 | struct fb_info *info) |
391 | { | 391 | { |
392 | if (var->vmode & FB_VMODE_YWRAP) { | 392 | if (var->vmode & FB_VMODE_YWRAP) { |
393 | if (var->yoffset < 0 | 393 | if (var->yoffset >= info->var.yres_virtual || |
394 | || var->yoffset >= info->var.yres_virtual | 394 | var->xoffset) |
395 | || var->xoffset) | ||
396 | return -EINVAL; | 395 | return -EINVAL; |
397 | } else { | 396 | } else { |
398 | if (var->xoffset + info->var.xres > info->var.xres_virtual || | 397 | if (var->xoffset + info->var.xres > info->var.xres_virtual || |
@@ -527,9 +526,8 @@ static int vfb_probe(struct platform_device *dev) | |||
527 | goto err2; | 526 | goto err2; |
528 | platform_set_drvdata(dev, info); | 527 | platform_set_drvdata(dev, info); |
529 | 528 | ||
530 | printk(KERN_INFO | 529 | fb_info(info, "Virtual frame buffer device, using %ldK of video memory\n", |
531 | "fb%d: Virtual frame buffer device, using %ldK of video memory\n", | 530 | videomemorysize >> 10); |
532 | info->node, videomemorysize >> 10); | ||
533 | return 0; | 531 | return 0; |
534 | err2: | 532 | err2: |
535 | fb_dealloc_cmap(&info->cmap); | 533 | fb_dealloc_cmap(&info->cmap); |
diff --git a/drivers/video/vga16fb.c b/drivers/video/vga16fb.c index 2827333703d9..283d335a759f 100644 --- a/drivers/video/vga16fb.c +++ b/drivers/video/vga16fb.c | |||
@@ -1377,8 +1377,7 @@ static int vga16fb_probe(struct platform_device *dev) | |||
1377 | goto err_check_var; | 1377 | goto err_check_var; |
1378 | } | 1378 | } |
1379 | 1379 | ||
1380 | printk(KERN_INFO "fb%d: %s frame buffer device\n", | 1380 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
1381 | info->node, info->fix.id); | ||
1382 | platform_set_drvdata(dev, info); | 1381 | platform_set_drvdata(dev, info); |
1383 | 1382 | ||
1384 | return 0; | 1383 | return 0; |
diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c index 897484903c30..b30e5a439d1f 100644 --- a/drivers/video/vt8500lcdfb.c +++ b/drivers/video/vt8500lcdfb.c | |||
@@ -365,7 +365,7 @@ static int vt8500lcd_probe(struct platform_device *pdev) | |||
365 | if (!fb_mem_virt) { | 365 | if (!fb_mem_virt) { |
366 | pr_err("%s: Failed to allocate framebuffer\n", __func__); | 366 | pr_err("%s: Failed to allocate framebuffer\n", __func__); |
367 | return -ENOMEM; | 367 | return -ENOMEM; |
368 | }; | 368 | } |
369 | 369 | ||
370 | fbi->fb.fix.smem_start = fb_mem_phys; | 370 | fbi->fb.fix.smem_start = fb_mem_phys; |
371 | fbi->fb.fix.smem_len = fb_mem_len; | 371 | fbi->fb.fix.smem_len = fb_mem_len; |
diff --git a/drivers/video/vt8623fb.c b/drivers/video/vt8623fb.c index e9557fa014ee..8bc6e0958a09 100644 --- a/drivers/video/vt8623fb.c +++ b/drivers/video/vt8623fb.c | |||
@@ -266,7 +266,7 @@ static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock) | |||
266 | 266 | ||
267 | rv = svga_compute_pll(&vt8623_pll, 1000000000 / pixclock, &m, &n, &r, info->node); | 267 | rv = svga_compute_pll(&vt8623_pll, 1000000000 / pixclock, &m, &n, &r, info->node); |
268 | if (rv < 0) { | 268 | if (rv < 0) { |
269 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); | 269 | fb_err(info, "cannot set requested pixclock, keeping old value\n"); |
270 | return; | 270 | return; |
271 | } | 271 | } |
272 | 272 | ||
@@ -335,7 +335,7 @@ static int vt8623fb_check_var(struct fb_var_screeninfo *var, struct fb_info *inf | |||
335 | rv = svga_match_format (vt8623fb_formats, var, NULL); | 335 | rv = svga_match_format (vt8623fb_formats, var, NULL); |
336 | if (rv < 0) | 336 | if (rv < 0) |
337 | { | 337 | { |
338 | printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); | 338 | fb_err(info, "unsupported mode requested\n"); |
339 | return rv; | 339 | return rv; |
340 | } | 340 | } |
341 | 341 | ||
@@ -354,21 +354,23 @@ static int vt8623fb_check_var(struct fb_var_screeninfo *var, struct fb_info *inf | |||
354 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; | 354 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; |
355 | if (mem > info->screen_size) | 355 | if (mem > info->screen_size) |
356 | { | 356 | { |
357 | printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); | 357 | fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n", |
358 | mem >> 10, (unsigned int) (info->screen_size >> 10)); | ||
358 | return -EINVAL; | 359 | return -EINVAL; |
359 | } | 360 | } |
360 | 361 | ||
361 | /* Text mode is limited to 256 kB of memory */ | 362 | /* Text mode is limited to 256 kB of memory */ |
362 | if ((var->bits_per_pixel == 0) && (mem > (256*1024))) | 363 | if ((var->bits_per_pixel == 0) && (mem > (256*1024))) |
363 | { | 364 | { |
364 | printk(KERN_ERR "fb%d: text framebuffer size too large (%d kB requested, 256 kB possible)\n", info->node, mem >> 10); | 365 | fb_err(info, "text framebuffer size too large (%d kB requested, 256 kB possible)\n", |
366 | mem >> 10); | ||
365 | return -EINVAL; | 367 | return -EINVAL; |
366 | } | 368 | } |
367 | 369 | ||
368 | rv = svga_check_timings (&vt8623_timing_regs, var, info->node); | 370 | rv = svga_check_timings (&vt8623_timing_regs, var, info->node); |
369 | if (rv < 0) | 371 | if (rv < 0) |
370 | { | 372 | { |
371 | printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); | 373 | fb_err(info, "invalid timings requested\n"); |
372 | return rv; | 374 | return rv; |
373 | } | 375 | } |
374 | 376 | ||
@@ -474,32 +476,32 @@ static int vt8623fb_set_par(struct fb_info *info) | |||
474 | mode = svga_match_format(vt8623fb_formats, &(info->var), &(info->fix)); | 476 | mode = svga_match_format(vt8623fb_formats, &(info->var), &(info->fix)); |
475 | switch (mode) { | 477 | switch (mode) { |
476 | case 0: | 478 | case 0: |
477 | pr_debug("fb%d: text mode\n", info->node); | 479 | fb_dbg(info, "text mode\n"); |
478 | svga_set_textmode_vga_regs(par->state.vgabase); | 480 | svga_set_textmode_vga_regs(par->state.vgabase); |
479 | svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); | 481 | svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); |
480 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70); | 482 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70); |
481 | break; | 483 | break; |
482 | case 1: | 484 | case 1: |
483 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); | 485 | fb_dbg(info, "4 bit pseudocolor\n"); |
484 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); | 486 | vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); |
485 | svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE); | 487 | svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE); |
486 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70); | 488 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70); |
487 | break; | 489 | break; |
488 | case 2: | 490 | case 2: |
489 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); | 491 | fb_dbg(info, "4 bit pseudocolor, planar\n"); |
490 | svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); | 492 | svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE); |
491 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70); | 493 | svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70); |
492 | break; | 494 | break; |
493 | case 3: | 495 | case 3: |
494 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); | 496 | fb_dbg(info, "8 bit pseudocolor\n"); |
495 | svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE); | 497 | svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE); |
496 | break; | 498 | break; |
497 | case 4: | 499 | case 4: |
498 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); | 500 | fb_dbg(info, "5/6/5 truecolor\n"); |
499 | svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE); | 501 | svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE); |
500 | break; | 502 | break; |
501 | case 5: | 503 | case 5: |
502 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); | 504 | fb_dbg(info, "8/8/8 truecolor\n"); |
503 | svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE); | 505 | svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE); |
504 | break; | 506 | break; |
505 | default: | 507 | default: |
@@ -584,27 +586,27 @@ static int vt8623fb_blank(int blank_mode, struct fb_info *info) | |||
584 | 586 | ||
585 | switch (blank_mode) { | 587 | switch (blank_mode) { |
586 | case FB_BLANK_UNBLANK: | 588 | case FB_BLANK_UNBLANK: |
587 | pr_debug("fb%d: unblank\n", info->node); | 589 | fb_dbg(info, "unblank\n"); |
588 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); | 590 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); |
589 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); | 591 | svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); |
590 | break; | 592 | break; |
591 | case FB_BLANK_NORMAL: | 593 | case FB_BLANK_NORMAL: |
592 | pr_debug("fb%d: blank\n", info->node); | 594 | fb_dbg(info, "blank\n"); |
593 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); | 595 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30); |
594 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 596 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
595 | break; | 597 | break; |
596 | case FB_BLANK_HSYNC_SUSPEND: | 598 | case FB_BLANK_HSYNC_SUSPEND: |
597 | pr_debug("fb%d: DPMS standby (hsync off)\n", info->node); | 599 | fb_dbg(info, "DPMS standby (hsync off)\n"); |
598 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30); | 600 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30); |
599 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 601 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
600 | break; | 602 | break; |
601 | case FB_BLANK_VSYNC_SUSPEND: | 603 | case FB_BLANK_VSYNC_SUSPEND: |
602 | pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node); | 604 | fb_dbg(info, "DPMS suspend (vsync off)\n"); |
603 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30); | 605 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30); |
604 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 606 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
605 | break; | 607 | break; |
606 | case FB_BLANK_POWERDOWN: | 608 | case FB_BLANK_POWERDOWN: |
607 | pr_debug("fb%d: DPMS off (no sync)\n", info->node); | 609 | fb_dbg(info, "DPMS off (no sync)\n"); |
608 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30); | 610 | svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30); |
609 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); | 611 | svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); |
610 | break; | 612 | break; |
@@ -769,12 +771,12 @@ static int vt8623_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
769 | 771 | ||
770 | rc = register_framebuffer(info); | 772 | rc = register_framebuffer(info); |
771 | if (rc < 0) { | 773 | if (rc < 0) { |
772 | dev_err(info->device, "cannot register framebugger\n"); | 774 | dev_err(info->device, "cannot register framebuffer\n"); |
773 | goto err_reg_fb; | 775 | goto err_reg_fb; |
774 | } | 776 | } |
775 | 777 | ||
776 | printk(KERN_INFO "fb%d: %s on %s, %d MB RAM\n", info->node, info->fix.id, | 778 | fb_info(info, "%s on %s, %d MB RAM\n", |
777 | pci_name(dev), info->fix.smem_len >> 20); | 779 | info->fix.id, pci_name(dev), info->fix.smem_len >> 20); |
778 | 780 | ||
779 | /* Record a reference to the driver data */ | 781 | /* Record a reference to the driver data */ |
780 | pci_set_drvdata(dev, info); | 782 | pci_set_drvdata(dev, info); |
@@ -829,7 +831,6 @@ static void vt8623_pci_remove(struct pci_dev *dev) | |||
829 | pci_release_regions(dev); | 831 | pci_release_regions(dev); |
830 | /* pci_disable_device(dev); */ | 832 | /* pci_disable_device(dev); */ |
831 | 833 | ||
832 | pci_set_drvdata(dev, NULL); | ||
833 | framebuffer_release(info); | 834 | framebuffer_release(info); |
834 | } | 835 | } |
835 | } | 836 | } |
diff --git a/drivers/video/w100fb.c b/drivers/video/w100fb.c index 7a299e951f75..10951c82f6ed 100644 --- a/drivers/video/w100fb.c +++ b/drivers/video/w100fb.c | |||
@@ -680,7 +680,7 @@ int w100fb_probe(struct platform_device *pdev) | |||
680 | par = info->par; | 680 | par = info->par; |
681 | platform_set_drvdata(pdev, info); | 681 | platform_set_drvdata(pdev, info); |
682 | 682 | ||
683 | inf = pdev->dev.platform_data; | 683 | inf = dev_get_platdata(&pdev->dev); |
684 | par->chip_id = chip_id; | 684 | par->chip_id = chip_id; |
685 | par->mach = inf; | 685 | par->mach = inf; |
686 | par->fastpll_mode = 0; | 686 | par->fastpll_mode = 0; |
@@ -761,10 +761,9 @@ int w100fb_probe(struct platform_device *pdev) | |||
761 | err |= device_create_file(&pdev->dev, &dev_attr_flip); | 761 | err |= device_create_file(&pdev->dev, &dev_attr_flip); |
762 | 762 | ||
763 | if (err != 0) | 763 | if (err != 0) |
764 | printk(KERN_WARNING "fb%d: failed to register attributes (%d)\n", | 764 | fb_warn(info, "failed to register attributes (%d)\n", err); |
765 | info->node, err); | ||
766 | 765 | ||
767 | printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); | 766 | fb_info(info, "%s frame buffer device\n", info->fix.id); |
768 | return 0; | 767 | return 0; |
769 | out: | 768 | out: |
770 | if (info) { | 769 | if (info) { |
diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c index 3072f30cad19..537d199612af 100644 --- a/drivers/video/wm8505fb.c +++ b/drivers/video/wm8505fb.c | |||
@@ -372,14 +372,12 @@ static int wm8505fb_probe(struct platform_device *pdev) | |||
372 | } | 372 | } |
373 | 373 | ||
374 | ret = device_create_file(&pdev->dev, &dev_attr_contrast); | 374 | ret = device_create_file(&pdev->dev, &dev_attr_contrast); |
375 | if (ret < 0) { | 375 | if (ret < 0) |
376 | printk(KERN_WARNING "fb%d: failed to register attributes (%d)\n", | 376 | fb_warn(&fbi->fb, "failed to register attributes (%d)\n", ret); |
377 | fbi->fb.node, ret); | ||
378 | } | ||
379 | 377 | ||
380 | printk(KERN_INFO "fb%d: %s frame buffer at 0x%lx-0x%lx\n", | 378 | fb_info(&fbi->fb, "%s frame buffer at 0x%lx-0x%lx\n", |
381 | fbi->fb.node, fbi->fb.fix.id, fbi->fb.fix.smem_start, | 379 | fbi->fb.fix.id, fbi->fb.fix.smem_start, |
382 | fbi->fb.fix.smem_start + fbi->fb.fix.smem_len - 1); | 380 | fbi->fb.fix.smem_start + fbi->fb.fix.smem_len - 1); |
383 | 381 | ||
384 | return 0; | 382 | return 0; |
385 | } | 383 | } |
@@ -411,7 +409,7 @@ static struct platform_driver wm8505fb_driver = { | |||
411 | .driver = { | 409 | .driver = { |
412 | .owner = THIS_MODULE, | 410 | .owner = THIS_MODULE, |
413 | .name = DRIVER_NAME, | 411 | .name = DRIVER_NAME, |
414 | .of_match_table = of_match_ptr(wmt_dt_ids), | 412 | .of_match_table = wmt_dt_ids, |
415 | }, | 413 | }, |
416 | }; | 414 | }; |
417 | 415 | ||
diff --git a/drivers/video/wmt_ge_rops.c b/drivers/video/wmt_ge_rops.c index 4aaeb18223bc..b0a9f34b2e01 100644 --- a/drivers/video/wmt_ge_rops.c +++ b/drivers/video/wmt_ge_rops.c | |||
@@ -169,13 +169,13 @@ static struct platform_driver wmt_ge_rops_driver = { | |||
169 | .driver = { | 169 | .driver = { |
170 | .owner = THIS_MODULE, | 170 | .owner = THIS_MODULE, |
171 | .name = "wmt_ge_rops", | 171 | .name = "wmt_ge_rops", |
172 | .of_match_table = of_match_ptr(wmt_dt_ids), | 172 | .of_match_table = wmt_dt_ids, |
173 | }, | 173 | }, |
174 | }; | 174 | }; |
175 | 175 | ||
176 | module_platform_driver(wmt_ge_rops_driver); | 176 | module_platform_driver(wmt_ge_rops_driver); |
177 | 177 | ||
178 | MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com"); | 178 | MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>"); |
179 | MODULE_DESCRIPTION("Accelerators for raster operations using " | 179 | MODULE_DESCRIPTION("Accelerators for raster operations using " |
180 | "WonderMedia Graphics Engine"); | 180 | "WonderMedia Graphics Engine"); |
181 | MODULE_LICENSE("GPL v2"); | 181 | MODULE_LICENSE("GPL v2"); |
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c index 84c664ea8eb9..6ff1a91e9dfd 100644 --- a/drivers/video/xilinxfb.c +++ b/drivers/video/xilinxfb.c | |||
@@ -260,10 +260,9 @@ static int xilinxfb_assign(struct platform_device *pdev, | |||
260 | 260 | ||
261 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 261 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
262 | drvdata->regs = devm_ioremap_resource(&pdev->dev, res); | 262 | drvdata->regs = devm_ioremap_resource(&pdev->dev, res); |
263 | if (IS_ERR(drvdata->regs)) { | 263 | if (IS_ERR(drvdata->regs)) |
264 | rc = PTR_ERR(drvdata->regs); | 264 | return PTR_ERR(drvdata->regs); |
265 | goto err_region; | 265 | |
266 | } | ||
267 | drvdata->regs_phys = res->start; | 266 | drvdata->regs_phys = res->start; |
268 | } | 267 | } |
269 | 268 | ||
@@ -279,11 +278,7 @@ static int xilinxfb_assign(struct platform_device *pdev, | |||
279 | 278 | ||
280 | if (!drvdata->fb_virt) { | 279 | if (!drvdata->fb_virt) { |
281 | dev_err(dev, "Could not allocate frame buffer memory\n"); | 280 | dev_err(dev, "Could not allocate frame buffer memory\n"); |
282 | rc = -ENOMEM; | 281 | return -ENOMEM; |
283 | if (drvdata->flags & BUS_ACCESS_FLAG) | ||
284 | goto err_fbmem; | ||
285 | else | ||
286 | goto err_region; | ||
287 | } | 282 | } |
288 | 283 | ||
289 | /* Clear (turn to black) the framebuffer */ | 284 | /* Clear (turn to black) the framebuffer */ |
@@ -363,14 +358,6 @@ err_cmap: | |||
363 | /* Turn off the display */ | 358 | /* Turn off the display */ |
364 | xilinx_fb_out32(drvdata, REG_CTRL, 0); | 359 | xilinx_fb_out32(drvdata, REG_CTRL, 0); |
365 | 360 | ||
366 | err_fbmem: | ||
367 | if (drvdata->flags & BUS_ACCESS_FLAG) | ||
368 | devm_iounmap(dev, drvdata->regs); | ||
369 | |||
370 | err_region: | ||
371 | kfree(drvdata); | ||
372 | dev_set_drvdata(dev, NULL); | ||
373 | |||
374 | return rc; | 361 | return rc; |
375 | } | 362 | } |
376 | 363 | ||
@@ -395,17 +382,12 @@ static int xilinxfb_release(struct device *dev) | |||
395 | /* Turn off the display */ | 382 | /* Turn off the display */ |
396 | xilinx_fb_out32(drvdata, REG_CTRL, 0); | 383 | xilinx_fb_out32(drvdata, REG_CTRL, 0); |
397 | 384 | ||
398 | /* Release the resources, as allocated based on interface */ | ||
399 | if (drvdata->flags & BUS_ACCESS_FLAG) | ||
400 | devm_iounmap(dev, drvdata->regs); | ||
401 | #ifdef CONFIG_PPC_DCR | 385 | #ifdef CONFIG_PPC_DCR |
402 | else | 386 | /* Release the resources, as allocated based on interface */ |
387 | if (!(drvdata->flags & BUS_ACCESS_FLAG)) | ||
403 | dcr_unmap(drvdata->dcr_host, drvdata->dcr_len); | 388 | dcr_unmap(drvdata->dcr_host, drvdata->dcr_len); |
404 | #endif | 389 | #endif |
405 | 390 | ||
406 | kfree(drvdata); | ||
407 | dev_set_drvdata(dev, NULL); | ||
408 | |||
409 | return 0; | 391 | return 0; |
410 | } | 392 | } |
411 | 393 | ||
@@ -413,7 +395,7 @@ static int xilinxfb_release(struct device *dev) | |||
413 | * OF bus binding | 395 | * OF bus binding |
414 | */ | 396 | */ |
415 | 397 | ||
416 | static int xilinxfb_of_probe(struct platform_device *op) | 398 | static int xilinxfb_of_probe(struct platform_device *pdev) |
417 | { | 399 | { |
418 | const u32 *prop; | 400 | const u32 *prop; |
419 | u32 tft_access = 0; | 401 | u32 tft_access = 0; |
@@ -425,17 +407,15 @@ static int xilinxfb_of_probe(struct platform_device *op) | |||
425 | pdata = xilinx_fb_default_pdata; | 407 | pdata = xilinx_fb_default_pdata; |
426 | 408 | ||
427 | /* Allocate the driver data region */ | 409 | /* Allocate the driver data region */ |
428 | drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); | 410 | drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); |
429 | if (!drvdata) { | 411 | if (!drvdata) |
430 | dev_err(&op->dev, "Couldn't allocate device private record\n"); | ||
431 | return -ENOMEM; | 412 | return -ENOMEM; |
432 | } | ||
433 | 413 | ||
434 | /* | 414 | /* |
435 | * To check whether the core is connected directly to DCR or BUS | 415 | * To check whether the core is connected directly to DCR or BUS |
436 | * interface and initialize the tft_access accordingly. | 416 | * interface and initialize the tft_access accordingly. |
437 | */ | 417 | */ |
438 | of_property_read_u32(op->dev.of_node, "xlnx,dcr-splb-slave-if", | 418 | of_property_read_u32(pdev->dev.of_node, "xlnx,dcr-splb-slave-if", |
439 | &tft_access); | 419 | &tft_access); |
440 | 420 | ||
441 | /* | 421 | /* |
@@ -448,40 +428,39 @@ static int xilinxfb_of_probe(struct platform_device *op) | |||
448 | #ifdef CONFIG_PPC_DCR | 428 | #ifdef CONFIG_PPC_DCR |
449 | else { | 429 | else { |
450 | int start; | 430 | int start; |
451 | start = dcr_resource_start(op->dev.of_node, 0); | 431 | start = dcr_resource_start(pdev->dev.of_node, 0); |
452 | drvdata->dcr_len = dcr_resource_len(op->dev.of_node, 0); | 432 | drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0); |
453 | drvdata->dcr_host = dcr_map(op->dev.of_node, start, drvdata->dcr_len); | 433 | drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len); |
454 | if (!DCR_MAP_OK(drvdata->dcr_host)) { | 434 | if (!DCR_MAP_OK(drvdata->dcr_host)) { |
455 | dev_err(&op->dev, "invalid DCR address\n"); | 435 | dev_err(&pdev->dev, "invalid DCR address\n"); |
456 | kfree(drvdata); | ||
457 | return -ENODEV; | 436 | return -ENODEV; |
458 | } | 437 | } |
459 | } | 438 | } |
460 | #endif | 439 | #endif |
461 | 440 | ||
462 | prop = of_get_property(op->dev.of_node, "phys-size", &size); | 441 | prop = of_get_property(pdev->dev.of_node, "phys-size", &size); |
463 | if ((prop) && (size >= sizeof(u32)*2)) { | 442 | if ((prop) && (size >= sizeof(u32)*2)) { |
464 | pdata.screen_width_mm = prop[0]; | 443 | pdata.screen_width_mm = prop[0]; |
465 | pdata.screen_height_mm = prop[1]; | 444 | pdata.screen_height_mm = prop[1]; |
466 | } | 445 | } |
467 | 446 | ||
468 | prop = of_get_property(op->dev.of_node, "resolution", &size); | 447 | prop = of_get_property(pdev->dev.of_node, "resolution", &size); |
469 | if ((prop) && (size >= sizeof(u32)*2)) { | 448 | if ((prop) && (size >= sizeof(u32)*2)) { |
470 | pdata.xres = prop[0]; | 449 | pdata.xres = prop[0]; |
471 | pdata.yres = prop[1]; | 450 | pdata.yres = prop[1]; |
472 | } | 451 | } |
473 | 452 | ||
474 | prop = of_get_property(op->dev.of_node, "virtual-resolution", &size); | 453 | prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size); |
475 | if ((prop) && (size >= sizeof(u32)*2)) { | 454 | if ((prop) && (size >= sizeof(u32)*2)) { |
476 | pdata.xvirt = prop[0]; | 455 | pdata.xvirt = prop[0]; |
477 | pdata.yvirt = prop[1]; | 456 | pdata.yvirt = prop[1]; |
478 | } | 457 | } |
479 | 458 | ||
480 | if (of_find_property(op->dev.of_node, "rotate-display", NULL)) | 459 | if (of_find_property(pdev->dev.of_node, "rotate-display", NULL)) |
481 | pdata.rotate_screen = 1; | 460 | pdata.rotate_screen = 1; |
482 | 461 | ||
483 | dev_set_drvdata(&op->dev, drvdata); | 462 | dev_set_drvdata(&pdev->dev, drvdata); |
484 | return xilinxfb_assign(op, drvdata, &pdata); | 463 | return xilinxfb_assign(pdev, drvdata, &pdata); |
485 | } | 464 | } |
486 | 465 | ||
487 | static int xilinxfb_of_remove(struct platform_device *op) | 466 | static int xilinxfb_of_remove(struct platform_device *op) |
diff --git a/include/linux/fb.h b/include/linux/fb.h index ffac70aab3e9..70c4836e4a9f 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h | |||
@@ -792,4 +792,16 @@ extern int fb_find_mode(struct fb_var_screeninfo *var, | |||
792 | const struct fb_videomode *default_mode, | 792 | const struct fb_videomode *default_mode, |
793 | unsigned int default_bpp); | 793 | unsigned int default_bpp); |
794 | 794 | ||
795 | /* Convenience logging macros */ | ||
796 | #define fb_err(fb_info, fmt, ...) \ | ||
797 | pr_err("fb%d: " fmt, (fb_info)->node, ##__VA_ARGS__) | ||
798 | #define fb_notice(info, fmt, ...) \ | ||
799 | pr_notice("fb%d: " fmt, (fb_info)->node, ##__VA_ARGS__) | ||
800 | #define fb_warn(fb_info, fmt, ...) \ | ||
801 | pr_warn("fb%d: " fmt, (fb_info)->node, ##__VA_ARGS__) | ||
802 | #define fb_info(fb_info, fmt, ...) \ | ||
803 | pr_info("fb%d: " fmt, (fb_info)->node, ##__VA_ARGS__) | ||
804 | #define fb_dbg(fb_info, fmt, ...) \ | ||
805 | pr_debug("fb%d: " fmt, (fb_info)->node, ##__VA_ARGS__) | ||
806 | |||
795 | #endif /* _LINUX_FB_H */ | 807 | #endif /* _LINUX_FB_H */ |
diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h index 0f5a2fc69af9..c79f38131926 100644 --- a/include/video/atmel_lcdc.h +++ b/include/video/atmel_lcdc.h | |||
@@ -31,39 +31,20 @@ | |||
31 | #define ATMEL_LCDC_WIRING_BGR 0 | 31 | #define ATMEL_LCDC_WIRING_BGR 0 |
32 | #define ATMEL_LCDC_WIRING_RGB 1 | 32 | #define ATMEL_LCDC_WIRING_RGB 1 |
33 | 33 | ||
34 | struct atmel_lcdfb_config; | ||
35 | 34 | ||
36 | /* LCD Controller info data structure, stored in device platform_data */ | 35 | /* LCD Controller info data structure, stored in device platform_data */ |
37 | struct atmel_lcdfb_info { | 36 | struct atmel_lcdfb_pdata { |
38 | spinlock_t lock; | ||
39 | struct fb_info *info; | ||
40 | void __iomem *mmio; | ||
41 | int irq_base; | ||
42 | struct work_struct task; | ||
43 | |||
44 | unsigned int guard_time; | 37 | unsigned int guard_time; |
45 | unsigned int smem_len; | ||
46 | struct platform_device *pdev; | ||
47 | struct clk *bus_clk; | ||
48 | struct clk *lcdc_clk; | ||
49 | |||
50 | #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC | ||
51 | struct backlight_device *backlight; | ||
52 | u8 bl_power; | ||
53 | #endif | ||
54 | bool lcdcon_is_backlight; | 38 | bool lcdcon_is_backlight; |
55 | bool lcdcon_pol_negative; | 39 | bool lcdcon_pol_negative; |
56 | u8 saved_lcdcon; | ||
57 | |||
58 | u8 default_bpp; | 40 | u8 default_bpp; |
59 | u8 lcd_wiring_mode; | 41 | u8 lcd_wiring_mode; |
60 | unsigned int default_lcdcon2; | 42 | unsigned int default_lcdcon2; |
61 | unsigned int default_dmacon; | 43 | unsigned int default_dmacon; |
62 | void (*atmel_lcdfb_power_control)(int on); | 44 | void (*atmel_lcdfb_power_control)(struct atmel_lcdfb_pdata *pdata, int on); |
63 | struct fb_monspecs *default_monspecs; | 45 | struct fb_monspecs *default_monspecs; |
64 | u32 pseudo_palette[16]; | ||
65 | 46 | ||
66 | struct atmel_lcdfb_config *config; | 47 | struct list_head pwr_gpios; |
67 | }; | 48 | }; |
68 | 49 | ||
69 | #define ATMEL_LCDC_DMABADDR1 0x00 | 50 | #define ATMEL_LCDC_DMABADDR1 0x00 |
diff --git a/include/video/mmp_disp.h b/include/video/mmp_disp.h index b9dd1fbb0082..9fd9398368d5 100644 --- a/include/video/mmp_disp.h +++ b/include/video/mmp_disp.h | |||
@@ -91,6 +91,11 @@ struct mmp_win { | |||
91 | u16 up_crop; | 91 | u16 up_crop; |
92 | u16 bottom_crop; | 92 | u16 bottom_crop; |
93 | int pix_fmt; | 93 | int pix_fmt; |
94 | /* | ||
95 | * pitch[0]: graphics/video layer line length or y pitch | ||
96 | * pitch[1]/pitch[2]: video u/v pitch if non-zero | ||
97 | */ | ||
98 | u32 pitch[3]; | ||
94 | }; | 99 | }; |
95 | 100 | ||
96 | struct mmp_addr { | 101 | struct mmp_addr { |
@@ -334,6 +339,7 @@ struct mmp_mach_path_config { | |||
334 | int output_type; | 339 | int output_type; |
335 | u32 path_config; | 340 | u32 path_config; |
336 | u32 link_config; | 341 | u32 link_config; |
342 | u32 dsi_rbswap; | ||
337 | }; | 343 | }; |
338 | 344 | ||
339 | struct mmp_mach_plat_info { | 345 | struct mmp_mach_plat_info { |
diff --git a/include/video/omap-panel-data.h b/include/video/omap-panel-data.h index f7ac8d972af0..69279c013ac4 100644 --- a/include/video/omap-panel-data.h +++ b/include/video/omap-panel-data.h | |||
@@ -238,4 +238,17 @@ struct panel_nec_nl8048hl11_platform_data { | |||
238 | int qvga_gpio; | 238 | int qvga_gpio; |
239 | }; | 239 | }; |
240 | 240 | ||
241 | /** | ||
242 | * panel-tpo-td028ttec1 platform data | ||
243 | * @name: name for display entity | ||
244 | * @source: name of the display entity used as a video source | ||
245 | * @data_lines: number of DPI datalines | ||
246 | */ | ||
247 | struct panel_tpo_td028ttec1_platform_data { | ||
248 | const char *name; | ||
249 | const char *source; | ||
250 | |||
251 | int data_lines; | ||
252 | }; | ||
253 | |||
241 | #endif /* __OMAP_PANEL_DATA_H */ | 254 | #endif /* __OMAP_PANEL_DATA_H */ |