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-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index ccdf20a2e9be..170c5b32e49b 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -87,6 +87,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
87 struct ath_softc *sc; 87 struct ath_softc *sc;
88 struct ieee80211_hw *hw; 88 struct ieee80211_hw *hw;
89 u8 csz; 89 u8 csz;
90 u32 val;
90 int ret = 0; 91 int ret = 0;
91 struct ath_hw *ah; 92 struct ath_hw *ah;
92 93
@@ -133,6 +134,14 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
133 134
134 pci_set_master(pdev); 135 pci_set_master(pdev);
135 136
137 /*
138 * Disable the RETRY_TIMEOUT register (0x41) to keep
139 * PCI Tx retries from interfering with C3 CPU state.
140 */
141 pci_read_config_dword(pdev, 0x40, &val);
142 if ((val & 0x0000ff00) != 0)
143 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
144
136 ret = pci_request_region(pdev, 0, "ath9k"); 145 ret = pci_request_region(pdev, 0, "ath9k");
137 if (ret) { 146 if (ret) {
138 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 147 dev_err(&pdev->dev, "PCI memory region reserve error\n");
@@ -239,12 +248,21 @@ static int ath_pci_resume(struct pci_dev *pdev)
239 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 248 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
240 struct ath_wiphy *aphy = hw->priv; 249 struct ath_wiphy *aphy = hw->priv;
241 struct ath_softc *sc = aphy->sc; 250 struct ath_softc *sc = aphy->sc;
251 u32 val;
242 int err; 252 int err;
243 253
244 err = pci_enable_device(pdev); 254 err = pci_enable_device(pdev);
245 if (err) 255 if (err)
246 return err; 256 return err;
247 pci_restore_state(pdev); 257 pci_restore_state(pdev);
258 /*
259 * Suspend/Resume resets the PCI configuration space, so we have to
260 * re-disable the RETRY_TIMEOUT register (0x41) to keep
261 * PCI Tx retries from interfering with C3 CPU state
262 */
263 pci_read_config_dword(pdev, 0x40, &val);
264 if ((val & 0x0000ff00) != 0)
265 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
248 266
249 /* Enable LED */ 267 /* Enable LED */
250 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN, 268 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,