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-rw-r--r--drivers/video/omap2/dss/dispc.c232
-rw-r--r--drivers/video/omap2/dss/dsi.c6
-rw-r--r--drivers/video/omap2/dss/dss.h6
-rw-r--r--drivers/video/omap2/dss/manager.c12
4 files changed, 120 insertions, 136 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 397d4eee11bb..eb1c9be20d0a 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -119,6 +119,80 @@ enum omap_color_component {
119 DISPC_COLOR_COMPONENT_UV = 1 << 1, 119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120}; 120};
121 121
122enum mgr_reg_fields {
123 DISPC_MGR_FLD_ENABLE,
124 DISPC_MGR_FLD_STNTFT,
125 DISPC_MGR_FLD_GO,
126 DISPC_MGR_FLD_TFTDATALINES,
127 DISPC_MGR_FLD_STALLMODE,
128 DISPC_MGR_FLD_TCKENABLE,
129 DISPC_MGR_FLD_TCKSELECTION,
130 DISPC_MGR_FLD_CPR,
131 DISPC_MGR_FLD_FIFOHANDCHECK,
132 /* used to maintain a count of the above fields */
133 DISPC_MGR_FLD_NUM,
134};
135
136static const struct {
137 const char *name;
138 u32 vsync_irq;
139 u32 framedone_irq;
140 u32 sync_lost_irq;
141 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
142} mgr_desc[] = {
143 [OMAP_DSS_CHANNEL_LCD] = {
144 .name = "LCD",
145 .vsync_irq = DISPC_IRQ_VSYNC,
146 .framedone_irq = DISPC_IRQ_FRAMEDONE,
147 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
148 .reg_desc = {
149 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
150 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
151 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
152 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
153 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
154 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
155 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
156 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
157 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
158 },
159 },
160 [OMAP_DSS_CHANNEL_DIGIT] = {
161 .name = "DIGIT",
162 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
163 .framedone_irq = 0,
164 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
165 .reg_desc = {
166 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
167 [DISPC_MGR_FLD_STNTFT] = { },
168 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
169 [DISPC_MGR_FLD_TFTDATALINES] = { },
170 [DISPC_MGR_FLD_STALLMODE] = { },
171 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
172 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
173 [DISPC_MGR_FLD_CPR] = { },
174 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
175 },
176 },
177 [OMAP_DSS_CHANNEL_LCD2] = {
178 .name = "LCD2",
179 .vsync_irq = DISPC_IRQ_VSYNC2,
180 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
181 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
182 .reg_desc = {
183 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
184 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
185 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
186 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
187 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
188 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
189 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
190 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
191 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
192 },
193 },
194};
195
122static void _omap_dispc_set_irqs(void); 196static void _omap_dispc_set_irqs(void);
123 197
124static inline void dispc_write_reg(const u16 idx, u32 val) 198static inline void dispc_write_reg(const u16 idx, u32 val)
@@ -131,6 +205,18 @@ static inline u32 dispc_read_reg(const u16 idx)
131 return __raw_readl(dispc.base + idx); 205 return __raw_readl(dispc.base + idx);
132} 206}
133 207
208static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
209{
210 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
211 return REG_GET(rfld.reg, rfld.high, rfld.low);
212}
213
214static void mgr_fld_write(enum omap_channel channel,
215 enum mgr_reg_fields regfld, int val) {
216 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
217 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
218}
219
134#define SR(reg) \ 220#define SR(reg) \
135 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) 221 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
136#define RR(reg) \ 222#define RR(reg) \
@@ -398,90 +484,39 @@ static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
398 484
399u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) 485u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
400{ 486{
401 switch (channel) { 487 return mgr_desc[channel].vsync_irq;
402 case OMAP_DSS_CHANNEL_LCD:
403 return DISPC_IRQ_VSYNC;
404 case OMAP_DSS_CHANNEL_LCD2:
405 return DISPC_IRQ_VSYNC2;
406 case OMAP_DSS_CHANNEL_DIGIT:
407 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
408 default:
409 BUG();
410 return 0;
411 }
412} 488}
413 489
414u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) 490u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
415{ 491{
416 switch (channel) { 492 return mgr_desc[channel].framedone_irq;
417 case OMAP_DSS_CHANNEL_LCD:
418 return DISPC_IRQ_FRAMEDONE;
419 case OMAP_DSS_CHANNEL_LCD2:
420 return DISPC_IRQ_FRAMEDONE2;
421 case OMAP_DSS_CHANNEL_DIGIT:
422 return 0;
423 default:
424 BUG();
425 return 0;
426 }
427} 493}
428 494
429bool dispc_mgr_go_busy(enum omap_channel channel) 495bool dispc_mgr_go_busy(enum omap_channel channel)
430{ 496{
431 int bit; 497 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
432
433 if (dispc_mgr_is_lcd(channel))
434 bit = 5; /* GOLCD */
435 else
436 bit = 6; /* GODIGIT */
437
438 if (channel == OMAP_DSS_CHANNEL_LCD2)
439 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
440 else
441 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
442} 498}
443 499
444void dispc_mgr_go(enum omap_channel channel) 500void dispc_mgr_go(enum omap_channel channel)
445{ 501{
446 int bit;
447 bool enable_bit, go_bit; 502 bool enable_bit, go_bit;
448 503
449 if (dispc_mgr_is_lcd(channel))
450 bit = 0; /* LCDENABLE */
451 else
452 bit = 1; /* DIGITALENABLE */
453
454 /* if the channel is not enabled, we don't need GO */ 504 /* if the channel is not enabled, we don't need GO */
455 if (channel == OMAP_DSS_CHANNEL_LCD2) 505 enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
456 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
457 else
458 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
459 506
460 if (!enable_bit) 507 if (!enable_bit)
461 return; 508 return;
462 509
463 if (dispc_mgr_is_lcd(channel)) 510 go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
464 bit = 5; /* GOLCD */
465 else
466 bit = 6; /* GODIGIT */
467
468 if (channel == OMAP_DSS_CHANNEL_LCD2)
469 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
470 else
471 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
472 511
473 if (go_bit) { 512 if (go_bit) {
474 DSSERR("GO bit not down for channel %d\n", channel); 513 DSSERR("GO bit not down for channel %d\n", channel);
475 return; 514 return;
476 } 515 }
477 516
478 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : 517 DSSDBG("GO %s\n", mgr_desc[channel].name);
479 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
480 518
481 if (channel == OMAP_DSS_CHANNEL_LCD2) 519 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
482 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
483 else
484 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
485} 520}
486 521
487static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) 522static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
@@ -922,16 +957,10 @@ void dispc_enable_gamma_table(bool enable)
922 957
923static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) 958static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
924{ 959{
925 u16 reg; 960 if (channel == OMAP_DSS_CHANNEL_DIGIT)
926
927 if (channel == OMAP_DSS_CHANNEL_LCD)
928 reg = DISPC_CONFIG;
929 else if (channel == OMAP_DSS_CHANNEL_LCD2)
930 reg = DISPC_CONFIG2;
931 else
932 return; 961 return;
933 962
934 REG_FLD_MOD(reg, enable, 15, 15); 963 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
935} 964}
936 965
937static void dispc_mgr_set_cpr_coef(enum omap_channel channel, 966static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
@@ -2254,14 +2283,9 @@ static void dispc_disable_isr(void *data, u32 mask)
2254 2283
2255static void _enable_lcd_out(enum omap_channel channel, bool enable) 2284static void _enable_lcd_out(enum omap_channel channel, bool enable)
2256{ 2285{
2257 if (channel == OMAP_DSS_CHANNEL_LCD2) { 2286 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2258 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0); 2287 /* flush posted write */
2259 /* flush posted write */ 2288 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2260 dispc_read_reg(DISPC_CONTROL2);
2261 } else {
2262 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
2263 dispc_read_reg(DISPC_CONTROL);
2264 }
2265} 2289}
2266 2290
2267static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable) 2291static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
@@ -2274,12 +2298,9 @@ static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
2274 /* When we disable LCD output, we need to wait until frame is done. 2298 /* When we disable LCD output, we need to wait until frame is done.
2275 * Otherwise the DSS is still working, and turning off the clocks 2299 * Otherwise the DSS is still working, and turning off the clocks
2276 * prevents DSS from going to OFF mode */ 2300 * prevents DSS from going to OFF mode */
2277 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ? 2301 is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2278 REG_GET(DISPC_CONTROL2, 0, 0) :
2279 REG_GET(DISPC_CONTROL, 0, 0);
2280 2302
2281 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 : 2303 irq = mgr_desc[channel].framedone_irq;
2282 DISPC_IRQ_FRAMEDONE;
2283 2304
2284 if (!enable && is_on) { 2305 if (!enable && is_on) {
2285 init_completion(&frame_done_completion); 2306 init_completion(&frame_done_completion);
@@ -2384,16 +2405,7 @@ static void dispc_mgr_enable_digit_out(bool enable)
2384 2405
2385bool dispc_mgr_is_enabled(enum omap_channel channel) 2406bool dispc_mgr_is_enabled(enum omap_channel channel)
2386{ 2407{
2387 if (channel == OMAP_DSS_CHANNEL_LCD) 2408 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2388 return !!REG_GET(DISPC_CONTROL, 0, 0);
2389 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2390 return !!REG_GET(DISPC_CONTROL, 1, 1);
2391 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2392 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2393 else {
2394 BUG();
2395 return false;
2396 }
2397} 2409}
2398 2410
2399void dispc_mgr_enable(enum omap_channel channel, bool enable) 2411void dispc_mgr_enable(enum omap_channel channel, bool enable)
@@ -2432,10 +2444,7 @@ void dispc_pck_free_enable(bool enable)
2432 2444
2433void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) 2445void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2434{ 2446{
2435 if (channel == OMAP_DSS_CHANNEL_LCD2) 2447 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2436 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2437 else
2438 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2439} 2448}
2440 2449
2441 2450
@@ -2458,10 +2467,7 @@ void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2458 return; 2467 return;
2459 } 2468 }
2460 2469
2461 if (channel == OMAP_DSS_CHANNEL_LCD2) 2470 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, mode);
2462 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2463 else
2464 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2465} 2471}
2466 2472
2467void dispc_set_loadmode(enum omap_dss_load_mode mode) 2473void dispc_set_loadmode(enum omap_dss_load_mode mode)
@@ -2479,24 +2485,14 @@ static void dispc_mgr_set_trans_key(enum omap_channel ch,
2479 enum omap_dss_trans_key_type type, 2485 enum omap_dss_trans_key_type type,
2480 u32 trans_key) 2486 u32 trans_key)
2481{ 2487{
2482 if (ch == OMAP_DSS_CHANNEL_LCD) 2488 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2483 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2484 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2485 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2486 else /* OMAP_DSS_CHANNEL_LCD2 */
2487 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2488 2489
2489 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); 2490 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2490} 2491}
2491 2492
2492static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) 2493static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2493{ 2494{
2494 if (ch == OMAP_DSS_CHANNEL_LCD) 2495 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2495 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2496 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2497 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2498 else /* OMAP_DSS_CHANNEL_LCD2 */
2499 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2500} 2496}
2501 2497
2502static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, 2498static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
@@ -2547,10 +2543,7 @@ void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2547 return; 2543 return;
2548 } 2544 }
2549 2545
2550 if (channel == OMAP_DSS_CHANNEL_LCD2) 2546 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2551 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2552 else
2553 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2554} 2547}
2555 2548
2556void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) 2549void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
@@ -2584,10 +2577,7 @@ void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2584 2577
2585void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) 2578void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2586{ 2579{
2587 if (channel == OMAP_DSS_CHANNEL_LCD2) 2580 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2588 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2589 else
2590 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2591} 2581}
2592 2582
2593static bool _dispc_mgr_size_ok(u16 width, u16 height) 2583static bool _dispc_mgr_size_ok(u16 width, u16 height)
@@ -3450,12 +3440,6 @@ static void dispc_error_worker(struct work_struct *work)
3450 DISPC_IRQ_VID3_FIFO_UNDERFLOW, 3440 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3451 }; 3441 };
3452 3442
3453 static const unsigned sync_lost_bits[] = {
3454 DISPC_IRQ_SYNC_LOST,
3455 DISPC_IRQ_SYNC_LOST_DIGIT,
3456 DISPC_IRQ_SYNC_LOST2,
3457 };
3458
3459 spin_lock_irqsave(&dispc.irq_lock, flags); 3443 spin_lock_irqsave(&dispc.irq_lock, flags);
3460 errors = dispc.error_irqs; 3444 errors = dispc.error_irqs;
3461 dispc.error_irqs = 0; 3445 dispc.error_irqs = 0;
@@ -3484,7 +3468,7 @@ static void dispc_error_worker(struct work_struct *work)
3484 unsigned bit; 3468 unsigned bit;
3485 3469
3486 mgr = omap_dss_get_overlay_manager(i); 3470 mgr = omap_dss_get_overlay_manager(i);
3487 bit = sync_lost_bits[i]; 3471 bit = mgr_desc[i].sync_lost_irq;
3488 3472
3489 if (bit & errors) { 3473 if (bit & errors) {
3490 struct omap_dss_device *dssdev = mgr->device; 3474 struct omap_dss_device *dssdev = mgr->device;
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index a9767f31d4b1..df65b93c0659 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -4360,8 +4360,7 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4360 timings.x_res = dw; 4360 timings.x_res = dw;
4361 timings.y_res = dh; 4361 timings.y_res = dh;
4362 4362
4363 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ? 4363 irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
4364 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4365 4364
4366 r = omap_dispc_register_isr(dsi_framedone_irq_callback, 4365 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4367 (void *) dssdev, irq); 4366 (void *) dssdev, irq);
@@ -4393,8 +4392,7 @@ static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4393 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { 4392 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4394 u32 irq; 4393 u32 irq;
4395 4394
4396 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ? 4395 irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
4397 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4398 4396
4399 omap_dispc_unregister_isr(dsi_framedone_irq_callback, 4397 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4400 (void *) dssdev, irq); 4398 (void *) dssdev, irq);
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index dd1092ceaeef..df131fc68952 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -152,6 +152,12 @@ struct dsi_clock_info {
152 u16 lp_clk_div; 152 u16 lp_clk_div;
153}; 153};
154 154
155struct reg_field {
156 u16 reg;
157 u8 high;
158 u8 low;
159};
160
155struct seq_file; 161struct seq_file;
156struct platform_device; 162struct platform_device;
157 163
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index 0cbcde4c688a..bb602a2d57c1 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -500,16 +500,12 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
500 if (r) 500 if (r)
501 return r; 501 return r;
502 502
503 if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) { 503 if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC)
504 irq = DISPC_IRQ_EVSYNC_ODD; 504 irq = DISPC_IRQ_EVSYNC_ODD;
505 } else if (mgr->device->type == OMAP_DISPLAY_TYPE_HDMI) { 505 else if (mgr->device->type == OMAP_DISPLAY_TYPE_HDMI)
506 irq = DISPC_IRQ_EVSYNC_EVEN; 506 irq = DISPC_IRQ_EVSYNC_EVEN;
507 } else { 507 else
508 if (mgr->id == OMAP_DSS_CHANNEL_LCD) 508 irq = dispc_mgr_get_vsync_irq(mgr->id);
509 irq = DISPC_IRQ_VSYNC;
510 else
511 irq = DISPC_IRQ_VSYNC2;
512 }
513 509
514 r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout); 510 r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
515 511
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-26 13:31:18 -0500