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-rw-r--r--Documentation/devicetree/bindings/clock/imx31-clock.txt91
-rw-r--r--arch/arm/boot/dts/imx31.dtsi17
-rw-r--r--arch/arm/mach-imx/clk-imx31.c10
-rw-r--r--arch/arm/mach-imx/imx31-dt.c17
4 files changed, 119 insertions, 16 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx31-clock.txt b/Documentation/devicetree/bindings/clock/imx31-clock.txt
new file mode 100644
index 000000000000..19df842c694f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx31-clock.txt
@@ -0,0 +1,91 @@
1* Clock bindings for Freescale i.MX31
2
3Required properties:
4- compatible: Should be "fsl,imx31-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX31
11clocks and IDs.
12
13 Clock ID
14 -----------------------
15 dummy 0
16 ckih 1
17 ckil 2
18 mpll 3
19 spll 4
20 upll 5
21 mcu_main 6
22 hsp 7
23 ahb 8
24 nfc 9
25 ipg 10
26 per_div 11
27 per 12
28 csi_sel 13
29 fir_sel 14
30 csi_div 15
31 usb_div_pre 16
32 usb_div_post 17
33 fir_div_pre 18
34 fir_div_post 19
35 sdhc1_gate 20
36 sdhc2_gate 21
37 gpt_gate 22
38 epit1_gate 23
39 epit2_gate 24
40 iim_gate 25
41 ata_gate 26
42 sdma_gate 27
43 cspi3_gate 28
44 rng_gate 29
45 uart1_gate 30
46 uart2_gate 31
47 ssi1_gate 32
48 i2c1_gate 33
49 i2c2_gate 34
50 i2c3_gate 35
51 hantro_gate 36
52 mstick1_gate 37
53 mstick2_gate 38
54 csi_gate 39
55 rtc_gate 40
56 wdog_gate 41
57 pwm_gate 42
58 sim_gate 43
59 ect_gate 44
60 usb_gate 45
61 kpp_gate 46
62 ipu_gate 47
63 uart3_gate 48
64 uart4_gate 49
65 uart5_gate 50
66 owire_gate 51
67 ssi2_gate 52
68 cspi1_gate 53
69 cspi2_gate 54
70 gacc_gate 55
71 emi_gate 56
72 rtic_gate 57
73 firi_gate 58
74
75Examples:
76
77clks: ccm@53f80000{
78 compatible = "fsl,imx31-ccm";
79 reg = <0x53f80000 0x4000>;
80 interrupts = <0 31 0x04 0 53 0x04>;
81 #clock-cells = <1>;
82};
83
84uart1: serial@43f90000 {
85 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
86 reg = <0x43f90000 0x4000>;
87 interrupts = <45>;
88 clocks = <&clks 10>, <&clks 30>;
89 clock-names = "ipg", "per";
90 status = "disabled";
91};
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index eef7099f3e3c..454c2d175402 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -45,6 +45,8 @@
45 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 45 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
46 reg = <0x43f90000 0x4000>; 46 reg = <0x43f90000 0x4000>;
47 interrupts = <45>; 47 interrupts = <45>;
48 clocks = <&clks 10>, <&clks 30>;
49 clock-names = "ipg", "per";
48 status = "disabled"; 50 status = "disabled";
49 }; 51 };
50 52
@@ -52,12 +54,16 @@
52 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 54 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
53 reg = <0x43f94000 0x4000>; 55 reg = <0x43f94000 0x4000>;
54 interrupts = <32>; 56 interrupts = <32>;
57 clocks = <&clks 10>, <&clks 31>;
58 clock-names = "ipg", "per";
55 status = "disabled"; 59 status = "disabled";
56 }; 60 };
57 61
58 uart4: serial@43fb0000 { 62 uart4: serial@43fb0000 {
59 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 63 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
60 reg = <0x43fb0000 0x4000>; 64 reg = <0x43fb0000 0x4000>;
65 clocks = <&clks 10>, <&clks 49>;
66 clock-names = "ipg", "per";
61 interrupts = <46>; 67 interrupts = <46>;
62 status = "disabled"; 68 status = "disabled";
63 }; 69 };
@@ -66,6 +72,8 @@
66 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 72 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
67 reg = <0x43fb4000 0x4000>; 73 reg = <0x43fb4000 0x4000>;
68 interrupts = <47>; 74 interrupts = <47>;
75 clocks = <&clks 10>, <&clks 50>;
76 clock-names = "ipg", "per";
69 status = "disabled"; 77 status = "disabled";
70 }; 78 };
71 }; 79 };
@@ -81,8 +89,17 @@
81 compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 89 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
82 reg = <0x5000c000 0x4000>; 90 reg = <0x5000c000 0x4000>;
83 interrupts = <18>; 91 interrupts = <18>;
92 clocks = <&clks 10>, <&clks 48>;
93 clock-names = "ipg", "per";
84 status = "disabled"; 94 status = "disabled";
85 }; 95 };
96
97 clks: ccm@53f80000{
98 compatible = "fsl,imx31-ccm";
99 reg = <0x53f80000 0x4000>;
100 interrupts = <0 31 0x04 0 53 0x04>;
101 #clock-cells = <1>;
102 };
86 }; 103 };
87 }; 104 };
88}; 105};
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 590dd876d66a..a42494d22c59 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -46,11 +46,13 @@ enum mx31_clks {
46}; 46};
47 47
48static struct clk *clk[clk_max]; 48static struct clk *clk[clk_max];
49static struct clk_onecell_data clk_data;
49 50
50int __init mx31_clocks_init(unsigned long fref) 51int __init mx31_clocks_init(unsigned long fref)
51{ 52{
52 void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); 53 void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
53 int i; 54 int i;
55 struct device_node *np;
54 56
55 clk[dummy] = imx_clk_fixed("dummy", 0); 57 clk[dummy] = imx_clk_fixed("dummy", 0);
56 clk[ckih] = imx_clk_fixed("ckih", fref); 58 clk[ckih] = imx_clk_fixed("ckih", fref);
@@ -117,6 +119,14 @@ int __init mx31_clocks_init(unsigned long fref)
117 pr_err("imx31 clk %d: register failed with %ld\n", 119 pr_err("imx31 clk %d: register failed with %ld\n",
118 i, PTR_ERR(clk[i])); 120 i, PTR_ERR(clk[i]));
119 121
122 np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
123
124 if (np) {
125 clk_data.clks = clk;
126 clk_data.clk_num = ARRAY_SIZE(clk);
127 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
128 }
129
120 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); 130 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
121 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); 131 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
122 clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0"); 132 clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index af476de2570e..dc083d33a758 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -18,24 +18,9 @@
18#include "common.h" 18#include "common.h"
19#include "mx31.h" 19#include "mx31.h"
20 20
21static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
22 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
23 "imx21-uart.0", NULL),
24 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR,
25 "imx21-uart.1", NULL),
26 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR,
27 "imx21-uart.2", NULL),
28 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR,
29 "imx21-uart.3", NULL),
30 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR,
31 "imx21-uart.4", NULL),
32 { /* sentinel */ }
33};
34
35static void __init imx31_dt_init(void) 21static void __init imx31_dt_init(void)
36{ 22{
37 of_platform_populate(NULL, of_default_bus_match_table, 23 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
38 imx31_auxdata_lookup, NULL);
39} 24}
40 25
41static void __init imx31_timer_init(void) 26static void __init imx31_timer_init(void)
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 07:49:49 -0500