diff options
-rw-r--r-- | arch/arm/kernel/arch_timer.c | 30 |
1 files changed, 11 insertions, 19 deletions
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c index 1bb3b582043c..498c29ffbd39 100644 --- a/arch/arm/kernel/arch_timer.c +++ b/arch/arm/kernel/arch_timer.c | |||
@@ -25,7 +25,7 @@ | |||
25 | #include <asm/arch_timer.h> | 25 | #include <asm/arch_timer.h> |
26 | #include <asm/sched_clock.h> | 26 | #include <asm/sched_clock.h> |
27 | 27 | ||
28 | static unsigned long arch_timer_rate; | 28 | static u32 arch_timer_rate; |
29 | 29 | ||
30 | enum ppi_nr { | 30 | enum ppi_nr { |
31 | PHYS_SECURE_PPI, | 31 | PHYS_SECURE_PPI, |
@@ -121,27 +121,18 @@ static inline u32 arch_timer_reg_read(const int access, const int reg) | |||
121 | return val; | 121 | return val; |
122 | } | 122 | } |
123 | 123 | ||
124 | static inline cycle_t arch_timer_counter_read(const int access) | 124 | static inline u64 arch_counter_get_cntpct(void) |
125 | { | 125 | { |
126 | cycle_t cval = 0; | 126 | u64 cval; |
127 | 127 | asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); | |
128 | if (access == ARCH_TIMER_PHYS_ACCESS) | ||
129 | asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); | ||
130 | |||
131 | if (access == ARCH_TIMER_VIRT_ACCESS) | ||
132 | asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval)); | ||
133 | |||
134 | return cval; | 128 | return cval; |
135 | } | 129 | } |
136 | 130 | ||
137 | static inline cycle_t arch_counter_get_cntpct(void) | 131 | static inline u64 arch_counter_get_cntvct(void) |
138 | { | ||
139 | return arch_timer_counter_read(ARCH_TIMER_PHYS_ACCESS); | ||
140 | } | ||
141 | |||
142 | static inline cycle_t arch_counter_get_cntvct(void) | ||
143 | { | 132 | { |
144 | return arch_timer_counter_read(ARCH_TIMER_VIRT_ACCESS); | 133 | u64 cval; |
134 | asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval)); | ||
135 | return cval; | ||
145 | } | 136 | } |
146 | 137 | ||
147 | static irqreturn_t inline timer_handler(const int access, | 138 | static irqreturn_t inline timer_handler(const int access, |
@@ -259,7 +250,7 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk) | |||
259 | 250 | ||
260 | static int arch_timer_available(void) | 251 | static int arch_timer_available(void) |
261 | { | 252 | { |
262 | unsigned long freq; | 253 | u32 freq; |
263 | 254 | ||
264 | if (arch_timer_rate == 0) { | 255 | if (arch_timer_rate == 0) { |
265 | freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS, | 256 | freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS, |
@@ -275,7 +266,8 @@ static int arch_timer_available(void) | |||
275 | } | 266 | } |
276 | 267 | ||
277 | pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n", | 268 | pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n", |
278 | arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100, | 269 | (unsigned long)arch_timer_rate / 1000000, |
270 | (unsigned long)(arch_timer_rate / 10000) % 100, | ||
279 | arch_timer_use_virtual ? "virt" : "phys"); | 271 | arch_timer_use_virtual ? "virt" : "phys"); |
280 | return 0; | 272 | return 0; |
281 | } | 273 | } |