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-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h272
-rw-r--r--drivers/iommu/Makefile1
-rw-r--r--drivers/iommu/omap-iommu-debug.c1
-rw-r--r--drivers/iommu/omap-iommu.c19
-rw-r--r--drivers/iommu/omap-iommu.h255
-rw-r--r--drivers/iommu/omap-iommu2.c (renamed from arch/arm/mach-omap2/iommu2.c)2
-rw-r--r--drivers/iommu/omap-iopgtable.h22
-rw-r--r--drivers/iommu/omap-iovmm.c1
9 files changed, 293 insertions, 282 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fe40d9e488c9..d6721a7f4c3b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -184,8 +184,6 @@ obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
184obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 184obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
185mailbox_mach-objs := mailbox.o 185mailbox_mach-objs := mailbox.o
186 186
187obj-$(CONFIG_OMAP_IOMMU) += iommu2.o
188
189iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o 187iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o
190obj-y += $(iommu-m) $(iommu-y) 188obj-y += $(iommu-m) $(iommu-y)
191 189
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index a4b71b14975a..c677b9f2fefa 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -10,103 +10,21 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13#ifndef __MACH_IOMMU_H 13#define MMU_REG_SIZE 256
14#define __MACH_IOMMU_H
15
16#include <linux/io.h>
17
18#if defined(CONFIG_ARCH_OMAP1)
19#error "iommu for this processor not implemented yet"
20#endif
21
22struct iotlb_entry {
23 u32 da;
24 u32 pa;
25 u32 pgsz, prsvd, valid;
26 union {
27 u16 ap;
28 struct {
29 u32 endian, elsz, mixed;
30 };
31 };
32};
33
34struct omap_iommu {
35 const char *name;
36 struct module *owner;
37 struct clk *clk;
38 void __iomem *regbase;
39 struct device *dev;
40 void *isr_priv;
41 struct iommu_domain *domain;
42
43 unsigned int refcount;
44 spinlock_t iommu_lock; /* global for this whole object */
45
46 /*
47 * We don't change iopgd for a situation like pgd for a task,
48 * but share it globally for each iommu.
49 */
50 u32 *iopgd;
51 spinlock_t page_table_lock; /* protect iopgd */
52
53 int nr_tlb_entries;
54
55 struct list_head mmap;
56 struct mutex mmap_lock; /* protect mmap */
57
58 void *ctx; /* iommu context: registres saved area */
59 u32 da_start;
60 u32 da_end;
61};
62
63struct cr_regs {
64 union {
65 struct {
66 u16 cam_l;
67 u16 cam_h;
68 };
69 u32 cam;
70 };
71 union {
72 struct {
73 u16 ram_l;
74 u16 ram_h;
75 };
76 u32 ram;
77 };
78};
79
80struct iotlb_lock {
81 short base;
82 short vict;
83};
84
85/* architecture specific functions */
86struct iommu_functions {
87 unsigned long version;
88
89 int (*enable)(struct omap_iommu *obj);
90 void (*disable)(struct omap_iommu *obj);
91 void (*set_twl)(struct omap_iommu *obj, bool on);
92 u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
93
94 void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
95 void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
96
97 struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
98 struct iotlb_entry *e);
99 int (*cr_valid)(struct cr_regs *cr);
100 u32 (*cr_to_virt)(struct cr_regs *cr);
101 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
102 ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
103 char *buf);
104
105 u32 (*get_pte_attr)(struct iotlb_entry *e);
106 14
107 void (*save_ctx)(struct omap_iommu *obj); 15/**
108 void (*restore_ctx)(struct omap_iommu *obj); 16 * struct iommu_arch_data - omap iommu private data
109 ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len); 17 * @name: name of the iommu device
18 * @iommu_dev: handle of the iommu device
19 *
20 * This is an omap iommu private data object, which binds an iommu user
21 * to its iommu device. This object should be placed at the iommu user's
22 * dev_archdata so generic IOMMU API can be used without having to
23 * utilize omap-specific plumbing anymore.
24 */
25struct omap_iommu_arch_data {
26 const char *name;
27 struct omap_iommu *iommu_dev;
110}; 28};
111 29
112/** 30/**
@@ -129,165 +47,3 @@ struct iommu_platform_data {
129 u32 da_start; 47 u32 da_start;
130 u32 da_end; 48 u32 da_end;
131}; 49};
132
133/**
134 * struct iommu_arch_data - omap iommu private data
135 * @name: name of the iommu device
136 * @iommu_dev: handle of the iommu device
137 *
138 * This is an omap iommu private data object, which binds an iommu user
139 * to its iommu device. This object should be placed at the iommu user's
140 * dev_archdata so generic IOMMU API can be used without having to
141 * utilize omap-specific plumbing anymore.
142 */
143struct omap_iommu_arch_data {
144 const char *name;
145 struct omap_iommu *iommu_dev;
146};
147
148#ifdef CONFIG_IOMMU_API
149/**
150 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
151 * @dev: iommu client device
152 */
153static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
154{
155 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
156
157 return arch_data->iommu_dev;
158}
159#endif
160
161/* IOMMU errors */
162#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
163#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
164#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
165#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
166#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
167
168/*
169 * MMU Register offsets
170 */
171#define MMU_REVISION 0x00
172#define MMU_SYSCONFIG 0x10
173#define MMU_SYSSTATUS 0x14
174#define MMU_IRQSTATUS 0x18
175#define MMU_IRQENABLE 0x1c
176#define MMU_WALKING_ST 0x40
177#define MMU_CNTL 0x44
178#define MMU_FAULT_AD 0x48
179#define MMU_TTB 0x4c
180#define MMU_LOCK 0x50
181#define MMU_LD_TLB 0x54
182#define MMU_CAM 0x58
183#define MMU_RAM 0x5c
184#define MMU_GFLUSH 0x60
185#define MMU_FLUSH_ENTRY 0x64
186#define MMU_READ_CAM 0x68
187#define MMU_READ_RAM 0x6c
188#define MMU_EMU_FAULT_AD 0x70
189
190#define MMU_REG_SIZE 256
191
192/*
193 * MMU Register bit definitions
194 */
195#define MMU_LOCK_BASE_SHIFT 10
196#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
197#define MMU_LOCK_BASE(x) \
198 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
199
200#define MMU_LOCK_VICT_SHIFT 4
201#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
202#define MMU_LOCK_VICT(x) \
203 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
204
205#define MMU_CAM_VATAG_SHIFT 12
206#define MMU_CAM_VATAG_MASK \
207 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
208#define MMU_CAM_P (1 << 3)
209#define MMU_CAM_V (1 << 2)
210#define MMU_CAM_PGSZ_MASK 3
211#define MMU_CAM_PGSZ_1M (0 << 0)
212#define MMU_CAM_PGSZ_64K (1 << 0)
213#define MMU_CAM_PGSZ_4K (2 << 0)
214#define MMU_CAM_PGSZ_16M (3 << 0)
215
216#define MMU_RAM_PADDR_SHIFT 12
217#define MMU_RAM_PADDR_MASK \
218 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
219
220#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
221#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
222
223#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
224#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
225#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
226#define MMU_RAM_MIXED_SHIFT 6
227#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
228#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
229
230/*
231 * utilities for super page(16MB, 1MB, 64KB and 4KB)
232 */
233
234#define iopgsz_max(bytes) \
235 (((bytes) >= SZ_16M) ? SZ_16M : \
236 ((bytes) >= SZ_1M) ? SZ_1M : \
237 ((bytes) >= SZ_64K) ? SZ_64K : \
238 ((bytes) >= SZ_4K) ? SZ_4K : 0)
239
240#define bytes_to_iopgsz(bytes) \
241 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
242 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
243 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
244 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
245
246#define iopgsz_to_bytes(iopgsz) \
247 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
248 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
249 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
250 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
251
252#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
253
254/*
255 * global functions
256 */
257extern u32 omap_iommu_arch_version(void);
258
259extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
260
261extern int
262omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
263
264extern int omap_iommu_set_isr(const char *name,
265 int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
266 void *priv),
267 void *isr_priv);
268
269extern int omap_install_iommu_arch(const struct iommu_functions *ops);
270extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
271
272extern int omap_foreach_iommu_device(void *data,
273 int (*fn)(struct device *, void *));
274
275extern ssize_t
276omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
277extern size_t
278omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
279
280/*
281 * register accessors
282 */
283static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
284{
285 return __raw_readl(obj->regbase + offs);
286}
287
288static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
289{
290 __raw_writel(val, obj->regbase + offs);
291}
292
293#endif /* __MACH_IOMMU_H */
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 14a4d5fc94fa..f66b816d455c 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_DMAR_TABLE) += dmar.o
7obj-$(CONFIG_INTEL_IOMMU) += iova.o intel-iommu.o 7obj-$(CONFIG_INTEL_IOMMU) += iova.o intel-iommu.o
8obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o 8obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
9obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o 9obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
10obj-$(CONFIG_OMAP_IOMMU) += omap-iommu2.o
10obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o 11obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
11obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o 12obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
12obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o 13obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
diff --git a/drivers/iommu/omap-iommu-debug.c b/drivers/iommu/omap-iommu-debug.c
index cf4a0b5c1d82..d0427bd21361 100644
--- a/drivers/iommu/omap-iommu-debug.c
+++ b/drivers/iommu/omap-iommu-debug.c
@@ -23,6 +23,7 @@
23#include <plat/iommu.h> 23#include <plat/iommu.h>
24 24
25#include "omap-iopgtable.h" 25#include "omap-iopgtable.h"
26#include "omap-iommu.h"
26 27
27#define MAXCOLUMN 100 /* for short messages */ 28#define MAXCOLUMN 100 /* for short messages */
28 29
diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index eadcfde757ee..4db86e12c200 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -22,12 +22,14 @@
22#include <linux/omap-iommu.h> 22#include <linux/omap-iommu.h>
23#include <linux/mutex.h> 23#include <linux/mutex.h>
24#include <linux/spinlock.h> 24#include <linux/spinlock.h>
25#include <linux/io.h>
25 26
26#include <asm/cacheflush.h> 27#include <asm/cacheflush.h>
27 28
28#include <plat/iommu.h> 29#include <plat/iommu.h>
29 30
30#include "omap-iopgtable.h" 31#include "omap-iopgtable.h"
32#include "omap-iommu.h"
31 33
32#define for_each_iotlb_cr(obj, n, __i, cr) \ 34#define for_each_iotlb_cr(obj, n, __i, cr) \
33 for (__i = 0; \ 35 for (__i = 0; \
@@ -1016,6 +1018,23 @@ static void iopte_cachep_ctor(void *iopte)
1016 clean_dcache_area(iopte, IOPTE_TABLE_SIZE); 1018 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1017} 1019}
1018 1020
1021static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
1022 u32 flags)
1023{
1024 memset(e, 0, sizeof(*e));
1025
1026 e->da = da;
1027 e->pa = pa;
1028 e->valid = 1;
1029 /* FIXME: add OMAP1 support */
1030 e->pgsz = flags & MMU_CAM_PGSZ_MASK;
1031 e->endian = flags & MMU_RAM_ENDIAN_MASK;
1032 e->elsz = flags & MMU_RAM_ELSZ_MASK;
1033 e->mixed = flags & MMU_RAM_MIXED_MASK;
1034
1035 return iopgsz_to_bytes(e->pgsz);
1036}
1037
1019static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, 1038static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1020 phys_addr_t pa, size_t bytes, int prot) 1039 phys_addr_t pa, size_t bytes, int prot)
1021{ 1040{
diff --git a/drivers/iommu/omap-iommu.h b/drivers/iommu/omap-iommu.h
new file mode 100644
index 000000000000..8c3378d99b81
--- /dev/null
+++ b/drivers/iommu/omap-iommu.h
@@ -0,0 +1,255 @@
1/*
2 * omap iommu: main structures
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#if defined(CONFIG_ARCH_OMAP1)
14#error "iommu for this processor not implemented yet"
15#endif
16
17struct iotlb_entry {
18 u32 da;
19 u32 pa;
20 u32 pgsz, prsvd, valid;
21 union {
22 u16 ap;
23 struct {
24 u32 endian, elsz, mixed;
25 };
26 };
27};
28
29struct omap_iommu {
30 const char *name;
31 struct module *owner;
32 struct clk *clk;
33 void __iomem *regbase;
34 struct device *dev;
35 void *isr_priv;
36 struct iommu_domain *domain;
37
38 unsigned int refcount;
39 spinlock_t iommu_lock; /* global for this whole object */
40
41 /*
42 * We don't change iopgd for a situation like pgd for a task,
43 * but share it globally for each iommu.
44 */
45 u32 *iopgd;
46 spinlock_t page_table_lock; /* protect iopgd */
47
48 int nr_tlb_entries;
49
50 struct list_head mmap;
51 struct mutex mmap_lock; /* protect mmap */
52
53 void *ctx; /* iommu context: registres saved area */
54 u32 da_start;
55 u32 da_end;
56};
57
58struct cr_regs {
59 union {
60 struct {
61 u16 cam_l;
62 u16 cam_h;
63 };
64 u32 cam;
65 };
66 union {
67 struct {
68 u16 ram_l;
69 u16 ram_h;
70 };
71 u32 ram;
72 };
73};
74
75struct iotlb_lock {
76 short base;
77 short vict;
78};
79
80/* architecture specific functions */
81struct iommu_functions {
82 unsigned long version;
83
84 int (*enable)(struct omap_iommu *obj);
85 void (*disable)(struct omap_iommu *obj);
86 void (*set_twl)(struct omap_iommu *obj, bool on);
87 u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
88
89 void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
90 void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
91
92 struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
93 struct iotlb_entry *e);
94 int (*cr_valid)(struct cr_regs *cr);
95 u32 (*cr_to_virt)(struct cr_regs *cr);
96 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
97 ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
98 char *buf);
99
100 u32 (*get_pte_attr)(struct iotlb_entry *e);
101
102 void (*save_ctx)(struct omap_iommu *obj);
103 void (*restore_ctx)(struct omap_iommu *obj);
104 ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
105};
106
107#ifdef CONFIG_IOMMU_API
108/**
109 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
110 * @dev: iommu client device
111 */
112static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
113{
114 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
115
116 return arch_data->iommu_dev;
117}
118#endif
119
120/* IOMMU errors */
121#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
122#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
123#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
124#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
125#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
126
127/*
128 * MMU Register offsets
129 */
130#define MMU_REVISION 0x00
131#define MMU_SYSCONFIG 0x10
132#define MMU_SYSSTATUS 0x14
133#define MMU_IRQSTATUS 0x18
134#define MMU_IRQENABLE 0x1c
135#define MMU_WALKING_ST 0x40
136#define MMU_CNTL 0x44
137#define MMU_FAULT_AD 0x48
138#define MMU_TTB 0x4c
139#define MMU_LOCK 0x50
140#define MMU_LD_TLB 0x54
141#define MMU_CAM 0x58
142#define MMU_RAM 0x5c
143#define MMU_GFLUSH 0x60
144#define MMU_FLUSH_ENTRY 0x64
145#define MMU_READ_CAM 0x68
146#define MMU_READ_RAM 0x6c
147#define MMU_EMU_FAULT_AD 0x70
148
149#define MMU_REG_SIZE 256
150
151/*
152 * MMU Register bit definitions
153 */
154#define MMU_LOCK_BASE_SHIFT 10
155#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
156#define MMU_LOCK_BASE(x) \
157 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
158
159#define MMU_LOCK_VICT_SHIFT 4
160#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
161#define MMU_LOCK_VICT(x) \
162 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
163
164#define MMU_CAM_VATAG_SHIFT 12
165#define MMU_CAM_VATAG_MASK \
166 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
167#define MMU_CAM_P (1 << 3)
168#define MMU_CAM_V (1 << 2)
169#define MMU_CAM_PGSZ_MASK 3
170#define MMU_CAM_PGSZ_1M (0 << 0)
171#define MMU_CAM_PGSZ_64K (1 << 0)
172#define MMU_CAM_PGSZ_4K (2 << 0)
173#define MMU_CAM_PGSZ_16M (3 << 0)
174
175#define MMU_RAM_PADDR_SHIFT 12
176#define MMU_RAM_PADDR_MASK \
177 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
178
179#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
180#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
181
182#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
183#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
184#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
185#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
186#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
187#define MMU_RAM_MIXED_SHIFT 6
188#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
189#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
190
191/*
192 * utilities for super page(16MB, 1MB, 64KB and 4KB)
193 */
194
195#define iopgsz_max(bytes) \
196 (((bytes) >= SZ_16M) ? SZ_16M : \
197 ((bytes) >= SZ_1M) ? SZ_1M : \
198 ((bytes) >= SZ_64K) ? SZ_64K : \
199 ((bytes) >= SZ_4K) ? SZ_4K : 0)
200
201#define bytes_to_iopgsz(bytes) \
202 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
203 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
204 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
205 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
206
207#define iopgsz_to_bytes(iopgsz) \
208 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
209 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
210 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
211 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
212
213#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
214
215/*
216 * global functions
217 */
218extern u32 omap_iommu_arch_version(void);
219
220extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
221
222extern int
223omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
224
225extern int omap_iommu_set_isr(const char *name,
226 int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
227 void *priv),
228 void *isr_priv);
229
230extern void omap_iommu_save_ctx(struct device *dev);
231extern void omap_iommu_restore_ctx(struct device *dev);
232
233extern int omap_install_iommu_arch(const struct iommu_functions *ops);
234extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
235
236extern int omap_foreach_iommu_device(void *data,
237 int (*fn)(struct device *, void *));
238
239extern ssize_t
240omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
241extern size_t
242omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
243
244/*
245 * register accessors
246 */
247static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
248{
249 return __raw_readl(obj->regbase + offs);
250}
251
252static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
253{
254 __raw_writel(val, obj->regbase + offs);
255}
diff --git a/arch/arm/mach-omap2/iommu2.c b/drivers/iommu/omap-iommu2.c
index e8116cf58e15..f97c3863ef88 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/drivers/iommu/omap-iommu2.c
@@ -13,6 +13,7 @@
13 13
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/io.h>
16#include <linux/jiffies.h> 17#include <linux/jiffies.h>
17#include <linux/module.h> 18#include <linux/module.h>
18#include <linux/omap-iommu.h> 19#include <linux/omap-iommu.h>
@@ -20,6 +21,7 @@
20#include <linux/stringify.h> 21#include <linux/stringify.h>
21 22
22#include <plat/iommu.h> 23#include <plat/iommu.h>
24#include "omap-iommu.h"
23 25
24/* 26/*
25 * omap2 architecture specific register bit definitions 27 * omap2 architecture specific register bit definitions
diff --git a/drivers/iommu/omap-iopgtable.h b/drivers/iommu/omap-iopgtable.h
index 66a813977d52..cd4ae9e5b0c6 100644
--- a/drivers/iommu/omap-iopgtable.h
+++ b/drivers/iommu/omap-iopgtable.h
@@ -10,9 +10,6 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13#ifndef __PLAT_OMAP_IOMMU_H
14#define __PLAT_OMAP_IOMMU_H
15
16/* 13/*
17 * "L2 table" address mask and size definitions. 14 * "L2 table" address mask and size definitions.
18 */ 15 */
@@ -97,24 +94,5 @@ static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask)
97#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) 94#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
98#define iopte_offset(iopgd, da) (iopgd_page_vaddr(iopgd) + iopte_index(da)) 95#define iopte_offset(iopgd, da) (iopgd_page_vaddr(iopgd) + iopte_index(da))
99 96
100static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
101 u32 flags)
102{
103 memset(e, 0, sizeof(*e));
104
105 e->da = da;
106 e->pa = pa;
107 e->valid = 1;
108 /* FIXME: add OMAP1 support */
109 e->pgsz = flags & MMU_CAM_PGSZ_MASK;
110 e->endian = flags & MMU_RAM_ENDIAN_MASK;
111 e->elsz = flags & MMU_RAM_ELSZ_MASK;
112 e->mixed = flags & MMU_RAM_MIXED_MASK;
113
114 return iopgsz_to_bytes(e->pgsz);
115}
116
117#define to_iommu(dev) \ 97#define to_iommu(dev) \
118 (struct omap_iommu *)platform_get_drvdata(to_platform_device(dev)) 98 (struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))
119
120#endif /* __PLAT_OMAP_IOMMU_H */
diff --git a/drivers/iommu/omap-iovmm.c b/drivers/iommu/omap-iovmm.c
index 9852101cf042..3e3b2421b924 100644
--- a/drivers/iommu/omap-iovmm.c
+++ b/drivers/iommu/omap-iovmm.c
@@ -25,6 +25,7 @@
25#include <plat/iommu.h> 25#include <plat/iommu.h>
26 26
27#include "omap-iopgtable.h" 27#include "omap-iopgtable.h"
28#include "omap-iommu.h"
28 29
29/* 30/*
30 * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma) 31 * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 09:12:55 -0500