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-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/cm2_7xx.h4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c40
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_43xx_data.c100
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c260
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c55
-rw-r--r--arch/arm/mach-omap2/prcm43xx.h1
-rw-r--r--arch/arm/mach-omap2/prm7xx.h4
8 files changed, 425 insertions, 40 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8ca99e9321e3..863ec46e84a7 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -202,6 +202,7 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
202obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o 202obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
203 203
204# hwmod data 204# hwmod data
205obj-y += omap_hwmod_common_ipblock_data.o
205obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o 206obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
206obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o 207obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
207obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o 208obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594e7622..e966e3a3c931 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
357#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) 357#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
358#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 358#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
359#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 359#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
360#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0
361#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
362#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8
363#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
360#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 364#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
361#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 365#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
362#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 366#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 5da7a42a6d90..c6c6384de867 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -37,46 +37,6 @@ struct omap_hwmod_class omap2_uart_class = {
37}; 37};
38 38
39/* 39/*
40 * 'dss' class
41 * display sub-system
42 */
43
44static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
45 .rev_offs = 0x0000,
46 .sysc_offs = 0x0010,
47 .syss_offs = 0x0014,
48 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
49 SYSS_HAS_RESET_STATUS),
50 .sysc_fields = &omap_hwmod_sysc_type1,
51};
52
53struct omap_hwmod_class omap2_dss_hwmod_class = {
54 .name = "dss",
55 .sysc = &omap2_dss_sysc,
56 .reset = omap_dss_reset,
57};
58
59/*
60 * 'rfbi' class
61 * remote frame buffer interface
62 */
63
64static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
65 .rev_offs = 0x0000,
66 .sysc_offs = 0x0010,
67 .syss_offs = 0x0014,
68 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
69 SYSC_HAS_AUTOIDLE),
70 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
71 .sysc_fields = &omap_hwmod_sysc_type1,
72};
73
74struct omap_hwmod_class omap2_rfbi_hwmod_class = {
75 .name = "rfbi",
76 .sysc = &omap2_rfbi_sysc,
77};
78
79/*
80 * 'venc' class 40 * 'venc' class
81 * video encoder 41 * video encoder
82 */ 42 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 5c2cc8083fdd..fea01aa3ef42 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -19,6 +19,8 @@
19#include "omap_hwmod.h" 19#include "omap_hwmod.h"
20#include "omap_hwmod_33xx_43xx_common_data.h" 20#include "omap_hwmod_33xx_43xx_common_data.h"
21#include "prcm43xx.h" 21#include "prcm43xx.h"
22#include "omap_hwmod_common_data.h"
23
22 24
23/* IP blocks */ 25/* IP blocks */
24static struct omap_hwmod am43xx_l4_hs_hwmod = { 26static struct omap_hwmod am43xx_l4_hs_hwmod = {
@@ -415,6 +417,72 @@ static struct omap_hwmod am43xx_qspi_hwmod = {
415 }, 417 },
416}; 418};
417 419
420/* dss */
421
422static struct omap_hwmod am43xx_dss_core_hwmod = {
423 .name = "dss_core",
424 .class = &omap2_dss_hwmod_class,
425 .clkdm_name = "dss_clkdm",
426 .main_clk = "disp_clk",
427 .prcm = {
428 .omap4 = {
429 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
430 .modulemode = MODULEMODE_SWCTRL,
431 },
432 },
433};
434
435/* dispc */
436
437struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
438 .manager_count = 1,
439 .has_framedonetv_irq = 0
440};
441
442static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
443 .rev_offs = 0x0000,
444 .sysc_offs = 0x0010,
445 .syss_offs = 0x0014,
446 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
447 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
448 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
449 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
450 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
451 .sysc_fields = &omap_hwmod_sysc_type1,
452};
453
454static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
455 .name = "dispc",
456 .sysc = &am43xx_dispc_sysc,
457};
458
459static struct omap_hwmod am43xx_dss_dispc_hwmod = {
460 .name = "dss_dispc",
461 .class = &am43xx_dispc_hwmod_class,
462 .clkdm_name = "dss_clkdm",
463 .main_clk = "disp_clk",
464 .prcm = {
465 .omap4 = {
466 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
467 },
468 },
469 .dev_attr = &am43xx_dss_dispc_dev_attr,
470};
471
472/* rfbi */
473
474static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
475 .name = "dss_rfbi",
476 .class = &omap2_rfbi_hwmod_class,
477 .clkdm_name = "dss_clkdm",
478 .main_clk = "disp_clk",
479 .prcm = {
480 .omap4 = {
481 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
482 },
483 },
484};
485
418/* Interfaces */ 486/* Interfaces */
419static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { 487static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
420 .master = &am33xx_l3_main_hwmod, 488 .master = &am33xx_l3_main_hwmod,
@@ -654,6 +722,34 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
654 .user = OCP_USER_MPU | OCP_USER_SDMA, 722 .user = OCP_USER_MPU | OCP_USER_SDMA,
655}; 723};
656 724
725static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
726 .master = &am43xx_dss_core_hwmod,
727 .slave = &am33xx_l3_main_hwmod,
728 .clk = "l3_gclk",
729 .user = OCP_USER_MPU | OCP_USER_SDMA,
730};
731
732static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
733 .master = &am33xx_l4_ls_hwmod,
734 .slave = &am43xx_dss_core_hwmod,
735 .clk = "l4ls_gclk",
736 .user = OCP_USER_MPU | OCP_USER_SDMA,
737};
738
739static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
740 .master = &am33xx_l4_ls_hwmod,
741 .slave = &am43xx_dss_dispc_hwmod,
742 .clk = "l4ls_gclk",
743 .user = OCP_USER_MPU | OCP_USER_SDMA,
744};
745
746static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
747 .master = &am33xx_l4_ls_hwmod,
748 .slave = &am43xx_dss_rfbi_hwmod,
749 .clk = "l4ls_gclk",
750 .user = OCP_USER_MPU | OCP_USER_SDMA,
751};
752
657static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { 753static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
658 &am33xx_l4_wkup__synctimer, 754 &am33xx_l4_wkup__synctimer,
659 &am43xx_l4_ls__timer8, 755 &am43xx_l4_ls__timer8,
@@ -748,6 +844,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
748 &am43xx_l4_ls__ocp2scp1, 844 &am43xx_l4_ls__ocp2scp1,
749 &am43xx_l3_s__usbotgss0, 845 &am43xx_l3_s__usbotgss0,
750 &am43xx_l3_s__usbotgss1, 846 &am43xx_l3_s__usbotgss1,
847 &am43xx_dss__l3_main,
848 &am43xx_l4_ls__dss,
849 &am43xx_l4_ls__dss_dispc,
850 &am43xx_l4_ls__dss_rfbi,
751 NULL, 851 NULL,
752}; 852};
753 853
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 31fd26062535..e3562624ae48 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -273,6 +273,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
273}; 273};
274 274
275/* 275/*
276 * 'gmac' class
277 * cpsw/gmac sub system
278 */
279static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
280 .rev_offs = 0x0,
281 .sysc_offs = 0x8,
282 .syss_offs = 0x4,
283 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
284 SYSS_HAS_RESET_STATUS),
285 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
286 MSTANDBY_NO),
287 .sysc_fields = &omap_hwmod_sysc_type3,
288};
289
290static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
291 .name = "gmac",
292 .sysc = &dra7xx_gmac_sysc,
293};
294
295static struct omap_hwmod dra7xx_gmac_hwmod = {
296 .name = "gmac",
297 .class = &dra7xx_gmac_hwmod_class,
298 .clkdm_name = "gmac_clkdm",
299 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
300 .main_clk = "dpll_gmac_ck",
301 .mpu_rt_idx = 1,
302 .prcm = {
303 .omap4 = {
304 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
305 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
306 .modulemode = MODULEMODE_SWCTRL,
307 },
308 },
309};
310
311/*
312 * 'mdio' class
313 */
314static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
315 .name = "davinci_mdio",
316};
317
318static struct omap_hwmod dra7xx_mdio_hwmod = {
319 .name = "davinci_mdio",
320 .class = &dra7xx_mdio_hwmod_class,
321 .clkdm_name = "gmac_clkdm",
322 .main_clk = "dpll_gmac_ck",
323};
324
325/*
276 * 'dcan' class 326 * 'dcan' class
277 * 327 *
278 */ 328 */
@@ -1206,6 +1256,97 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1206 }, 1256 },
1207}; 1257};
1208 1258
1259/* ocp2scp3 */
1260static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1261 .name = "ocp2scp3",
1262 .class = &dra7xx_ocp2scp_hwmod_class,
1263 .clkdm_name = "l3init_clkdm",
1264 .main_clk = "l4_root_clk_div",
1265 .prcm = {
1266 .omap4 = {
1267 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1268 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1269 .modulemode = MODULEMODE_HWCTRL,
1270 },
1271 },
1272};
1273
1274/*
1275 * 'PCIE' class
1276 *
1277 */
1278
1279static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
1280 .name = "pcie",
1281};
1282
1283/* pcie1 */
1284static struct omap_hwmod dra7xx_pcie1_hwmod = {
1285 .name = "pcie1",
1286 .class = &dra7xx_pcie_hwmod_class,
1287 .clkdm_name = "pcie_clkdm",
1288 .main_clk = "l4_root_clk_div",
1289 .prcm = {
1290 .omap4 = {
1291 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1292 .modulemode = MODULEMODE_SWCTRL,
1293 },
1294 },
1295};
1296
1297/* pcie2 */
1298static struct omap_hwmod dra7xx_pcie2_hwmod = {
1299 .name = "pcie2",
1300 .class = &dra7xx_pcie_hwmod_class,
1301 .clkdm_name = "pcie_clkdm",
1302 .main_clk = "l4_root_clk_div",
1303 .prcm = {
1304 .omap4 = {
1305 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1306 .modulemode = MODULEMODE_SWCTRL,
1307 },
1308 },
1309};
1310
1311/*
1312 * 'PCIE PHY' class
1313 *
1314 */
1315
1316static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1317 .name = "pcie-phy",
1318};
1319
1320/* pcie1 phy */
1321static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1322 .name = "pcie1-phy",
1323 .class = &dra7xx_pcie_phy_hwmod_class,
1324 .clkdm_name = "l3init_clkdm",
1325 .main_clk = "l4_root_clk_div",
1326 .prcm = {
1327 .omap4 = {
1328 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1329 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1330 .modulemode = MODULEMODE_SWCTRL,
1331 },
1332 },
1333};
1334
1335/* pcie2 phy */
1336static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
1337 .name = "pcie2-phy",
1338 .class = &dra7xx_pcie_phy_hwmod_class,
1339 .clkdm_name = "l3init_clkdm",
1340 .main_clk = "l4_root_clk_div",
1341 .prcm = {
1342 .omap4 = {
1343 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1344 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1345 .modulemode = MODULEMODE_SWCTRL,
1346 },
1347 },
1348};
1349
1209/* 1350/*
1210 * 'qspi' class 1351 * 'qspi' class
1211 * 1352 *
@@ -1240,6 +1381,38 @@ static struct omap_hwmod dra7xx_qspi_hwmod = {
1240}; 1381};
1241 1382
1242/* 1383/*
1384 * 'rtcss' class
1385 *
1386 */
1387static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1388 .sysc_offs = 0x0078,
1389 .sysc_flags = SYSC_HAS_SIDLEMODE,
1390 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1391 SIDLE_SMART_WKUP),
1392 .sysc_fields = &omap_hwmod_sysc_type3,
1393};
1394
1395static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1396 .name = "rtcss",
1397 .sysc = &dra7xx_rtcss_sysc,
1398};
1399
1400/* rtcss */
1401static struct omap_hwmod dra7xx_rtcss_hwmod = {
1402 .name = "rtcss",
1403 .class = &dra7xx_rtcss_hwmod_class,
1404 .clkdm_name = "rtc_clkdm",
1405 .main_clk = "sys_32k_ck",
1406 .prcm = {
1407 .omap4 = {
1408 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1409 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1410 .modulemode = MODULEMODE_SWCTRL,
1411 },
1412 },
1413};
1414
1415/*
1243 * 'sata' class 1416 * 'sata' class
1244 * 1417 *
1245 */ 1418 */
@@ -1990,6 +2163,19 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1990 .user = OCP_USER_MPU | OCP_USER_SDMA, 2163 .user = OCP_USER_MPU | OCP_USER_SDMA,
1991}; 2164};
1992 2165
2166static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2167 .master = &dra7xx_l4_per2_hwmod,
2168 .slave = &dra7xx_gmac_hwmod,
2169 .clk = "dpll_gmac_ck",
2170 .user = OCP_USER_MPU,
2171};
2172
2173static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2174 .master = &dra7xx_gmac_hwmod,
2175 .slave = &dra7xx_mdio_hwmod,
2176 .user = OCP_USER_MPU,
2177};
2178
1993/* l4_wkup -> dcan1 */ 2179/* l4_wkup -> dcan1 */
1994static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = { 2180static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
1995 .master = &dra7xx_l4_wkup_hwmod, 2181 .master = &dra7xx_l4_wkup_hwmod,
@@ -2317,6 +2503,62 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2317 .user = OCP_USER_MPU | OCP_USER_SDMA, 2503 .user = OCP_USER_MPU | OCP_USER_SDMA,
2318}; 2504};
2319 2505
2506/* l4_cfg -> ocp2scp3 */
2507static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2508 .master = &dra7xx_l4_cfg_hwmod,
2509 .slave = &dra7xx_ocp2scp3_hwmod,
2510 .clk = "l4_root_clk_div",
2511 .user = OCP_USER_MPU | OCP_USER_SDMA,
2512};
2513
2514/* l3_main_1 -> pcie1 */
2515static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
2516 .master = &dra7xx_l3_main_1_hwmod,
2517 .slave = &dra7xx_pcie1_hwmod,
2518 .clk = "l3_iclk_div",
2519 .user = OCP_USER_MPU | OCP_USER_SDMA,
2520};
2521
2522/* l4_cfg -> pcie1 */
2523static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
2524 .master = &dra7xx_l4_cfg_hwmod,
2525 .slave = &dra7xx_pcie1_hwmod,
2526 .clk = "l4_root_clk_div",
2527 .user = OCP_USER_MPU | OCP_USER_SDMA,
2528};
2529
2530/* l3_main_1 -> pcie2 */
2531static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
2532 .master = &dra7xx_l3_main_1_hwmod,
2533 .slave = &dra7xx_pcie2_hwmod,
2534 .clk = "l3_iclk_div",
2535 .user = OCP_USER_MPU | OCP_USER_SDMA,
2536};
2537
2538/* l4_cfg -> pcie2 */
2539static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
2540 .master = &dra7xx_l4_cfg_hwmod,
2541 .slave = &dra7xx_pcie2_hwmod,
2542 .clk = "l4_root_clk_div",
2543 .user = OCP_USER_MPU | OCP_USER_SDMA,
2544};
2545
2546/* l4_cfg -> pcie1 phy */
2547static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2548 .master = &dra7xx_l4_cfg_hwmod,
2549 .slave = &dra7xx_pcie1_phy_hwmod,
2550 .clk = "l4_root_clk_div",
2551 .user = OCP_USER_MPU | OCP_USER_SDMA,
2552};
2553
2554/* l4_cfg -> pcie2 phy */
2555static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2556 .master = &dra7xx_l4_cfg_hwmod,
2557 .slave = &dra7xx_pcie2_phy_hwmod,
2558 .clk = "l4_root_clk_div",
2559 .user = OCP_USER_MPU | OCP_USER_SDMA,
2560};
2561
2320static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { 2562static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2321 { 2563 {
2322 .pa_start = 0x4b300000, 2564 .pa_start = 0x4b300000,
@@ -2335,6 +2577,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2335 .user = OCP_USER_MPU | OCP_USER_SDMA, 2577 .user = OCP_USER_MPU | OCP_USER_SDMA,
2336}; 2578};
2337 2579
2580/* l4_per3 -> rtcss */
2581static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2582 .master = &dra7xx_l4_per3_hwmod,
2583 .slave = &dra7xx_rtcss_hwmod,
2584 .clk = "l4_root_clk_div",
2585 .user = OCP_USER_MPU | OCP_USER_SDMA,
2586};
2587
2338static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = { 2588static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2339 { 2589 {
2340 .name = "sysc", 2590 .name = "sysc",
@@ -2633,6 +2883,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2633 &dra7xx_l4_wkup__ctrl_module_wkup, 2883 &dra7xx_l4_wkup__ctrl_module_wkup,
2634 &dra7xx_l4_wkup__dcan1, 2884 &dra7xx_l4_wkup__dcan1,
2635 &dra7xx_l4_per2__dcan2, 2885 &dra7xx_l4_per2__dcan2,
2886 &dra7xx_l4_per2__cpgmac0,
2887 &dra7xx_gmac__mdio,
2636 &dra7xx_l4_cfg__dma_system, 2888 &dra7xx_l4_cfg__dma_system,
2637 &dra7xx_l3_main_1__dss, 2889 &dra7xx_l3_main_1__dss,
2638 &dra7xx_l3_main_1__dispc, 2890 &dra7xx_l3_main_1__dispc,
@@ -2663,7 +2915,15 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2663 &dra7xx_l4_per1__mmc4, 2915 &dra7xx_l4_per1__mmc4,
2664 &dra7xx_l4_cfg__mpu, 2916 &dra7xx_l4_cfg__mpu,
2665 &dra7xx_l4_cfg__ocp2scp1, 2917 &dra7xx_l4_cfg__ocp2scp1,
2918 &dra7xx_l4_cfg__ocp2scp3,
2919 &dra7xx_l3_main_1__pcie1,
2920 &dra7xx_l4_cfg__pcie1,
2921 &dra7xx_l3_main_1__pcie2,
2922 &dra7xx_l4_cfg__pcie2,
2923 &dra7xx_l4_cfg__pcie1_phy,
2924 &dra7xx_l4_cfg__pcie2_phy,
2666 &dra7xx_l3_main_1__qspi, 2925 &dra7xx_l3_main_1__qspi,
2926 &dra7xx_l4_per3__rtcss,
2667 &dra7xx_l4_cfg__sata, 2927 &dra7xx_l4_cfg__sata,
2668 &dra7xx_l4_cfg__smartreflex_core, 2928 &dra7xx_l4_cfg__smartreflex_core,
2669 &dra7xx_l4_cfg__smartreflex_mpu, 2929 &dra7xx_l4_cfg__smartreflex_mpu,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c
new file mode 100644
index 000000000000..f21664da25a2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_common_ipblock_data.c
@@ -0,0 +1,55 @@
1/*
2 * omap_hwmod_common_ipblock_data.c - common IP block data for OMAP2+
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include "omap_hwmod.h"
14#include "omap_hwmod_common_data.h"
15
16/*
17 * 'dss' class
18 * display sub-system
19 */
20
21static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
22 .rev_offs = 0x0000,
23 .sysc_offs = 0x0010,
24 .syss_offs = 0x0014,
25 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
26 SYSS_HAS_RESET_STATUS),
27 .sysc_fields = &omap_hwmod_sysc_type1,
28};
29
30struct omap_hwmod_class omap2_dss_hwmod_class = {
31 .name = "dss",
32 .sysc = &omap2_dss_sysc,
33 .reset = omap_dss_reset,
34};
35
36/*
37 * 'rfbi' class
38 * remote frame buffer interface
39 */
40
41static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
42 .rev_offs = 0x0000,
43 .sysc_offs = 0x0010,
44 .syss_offs = 0x0014,
45 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
46 SYSC_HAS_AUTOIDLE),
47 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
48 .sysc_fields = &omap_hwmod_sysc_type1,
49};
50
51struct omap_hwmod_class omap2_rfbi_hwmod_class = {
52 .name = "rfbi",
53 .sysc = &omap2_rfbi_sysc,
54};
55
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index 7785be984edd..ad7b3e9977f8 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -142,5 +142,6 @@
142#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 142#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8
143#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 143#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268
144#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 144#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0
145#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20
145 146
146#endif 147#endif
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a8404edc7..4bb50fbf29be 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
374#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 374#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
375#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 375#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
376#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 376#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
377#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0
378#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4
379#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8
380#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc
377#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 381#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
378#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 382#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
379#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 383#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-01 18:24:55 -0500