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-rw-r--r--drivers/staging/rtl8192u/r819xU_phy.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/staging/rtl8192u/r819xU_phy.c b/drivers/staging/rtl8192u/r819xU_phy.c
index c5fe552ce4a7..1dceac4bcd6b 100644
--- a/drivers/staging/rtl8192u/r819xU_phy.c
+++ b/drivers/staging/rtl8192u/r819xU_phy.c
@@ -483,7 +483,7 @@ void rtl8192_phy_configmac(struct net_device *dev)
483 dwArrayLen = MACPHY_ArrayLength; 483 dwArrayLen = MACPHY_ArrayLength;
484 pdwArray = rtl819XMACPHY_Array; 484 pdwArray = rtl819XMACPHY_Array;
485 } 485 }
486 for(i = 0; i<dwArrayLen; i=i+3) { 486 for (i = 0; i<dwArrayLen; i=i+3) {
487 if (pdwArray[i] == 0x318) { 487 if (pdwArray[i] == 0x318) {
488 pdwArray[i+2] = 0x00000800; 488 pdwArray[i+2] = 0x00000800;
489 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", 489 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
@@ -672,7 +672,7 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, RF9
672 WriteAddr[HW90_BLOCK_PHY1] = 0x800; 672 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
673 WriteAddr[HW90_BLOCK_RF] = 0x3; 673 WriteAddr[HW90_BLOCK_RF] = 0x3;
674 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock); 674 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
675 for(i=0 ; i < CheckTimes ; i++) { 675 for (i=0 ; i < CheckTimes ; i++) {
676 676
677 // 677 //
678 // Write Data to register and readback 678 // Write Data to register and readback
@@ -744,7 +744,7 @@ void rtl8192_BB_Config_ParaFile(struct net_device *dev)
744 744
745 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ 745 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
746 // TODO: this function should be removed on ASIC , Emily 2007.2.2 746 // TODO: this function should be removed on ASIC , Emily 2007.2.2
747 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) { 747 for (eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) {
748 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path 748 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
749 if (rtStatus != 0) { 749 if (rtStatus != 0) {
750 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); 750 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
@@ -914,7 +914,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, RF90_RADIO_PATH_E
914 914
915 switch (eRFPath) { 915 switch (eRFPath) {
916 case RF90_PATH_A: 916 case RF90_PATH_A:
917 for(i = 0;i<RadioA_ArrayLength; i=i+2) { 917 for (i = 0;i<RadioA_ArrayLength; i=i+2) {
918 918
919 if (rtl819XRadioA_Array[i] == 0xfe) { 919 if (rtl819XRadioA_Array[i] == 0xfe) {
920 mdelay(100); 920 mdelay(100);
@@ -926,7 +926,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, RF90_RADIO_PATH_E
926 } 926 }
927 break; 927 break;
928 case RF90_PATH_B: 928 case RF90_PATH_B:
929 for(i = 0;i<RadioB_ArrayLength; i=i+2) { 929 for (i = 0;i<RadioB_ArrayLength; i=i+2) {
930 930
931 if (rtl819XRadioB_Array[i] == 0xfe) { 931 if (rtl819XRadioB_Array[i] == 0xfe) {
932 mdelay(100); 932 mdelay(100);
@@ -938,7 +938,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, RF90_RADIO_PATH_E
938 } 938 }
939 break; 939 break;
940 case RF90_PATH_C: 940 case RF90_PATH_C:
941 for(i = 0;i<RadioC_ArrayLength; i=i+2) { 941 for (i = 0;i<RadioC_ArrayLength; i=i+2) {
942 942
943 if (rtl819XRadioC_Array[i] == 0xfe) { 943 if (rtl819XRadioC_Array[i] == 0xfe) {
944 mdelay(100); 944 mdelay(100);
@@ -950,7 +950,7 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, RF90_RADIO_PATH_E
950 } 950 }
951 break; 951 break;
952 case RF90_PATH_D: 952 case RF90_PATH_D:
953 for(i = 0;i<RadioD_ArrayLength; i=i+2) { 953 for (i = 0;i<RadioD_ArrayLength; i=i+2) {
954 954
955 if (rtl819XRadioD_Array[i] == 0xfe) { 955 if (rtl819XRadioD_Array[i] == 0xfe) {
956 mdelay(100); 956 mdelay(100);
@@ -1295,7 +1295,7 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, u
1295 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); 1295 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
1296 break; 1296 break;
1297 case CmdID_RF_WriteReg: 1297 case CmdID_RF_WriteReg:
1298 for(eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) { 1298 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1299 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2); 1299 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2);
1300 } 1300 }
1301 break; 1301 break;
@@ -1304,7 +1304,7 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, u
1304 } 1304 }
1305 1305
1306 break; 1306 break;
1307 } while(true); 1307 } while (true);
1308// }/*for(Number of RF paths)*/ 1308// }/*for(Number of RF paths)*/
1309 1309
1310 (*delay)=CurrentCmd->msDelay; 1310 (*delay)=CurrentCmd->msDelay;
@@ -1325,7 +1325,7 @@ void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1325 struct r8192_priv *priv = ieee80211_priv(dev); 1325 struct r8192_priv *priv = ieee80211_priv(dev);
1326 u32 delay = 0; 1326 u32 delay = 0;
1327 1327
1328 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) { 1328 while (!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) {
1329 // if(delay>0) 1329 // if(delay>0)
1330 // msleep(delay);//or mdelay? need further consideration 1330 // msleep(delay);//or mdelay? need further consideration
1331 if (!priv->up) 1331 if (!priv->up)