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-rw-r--r--Documentation/arm/Atmel/README124
-rw-r--r--Documentation/arm/Samsung-S3C24XX/DMA.txt46
-rw-r--r--MAINTAINERS2
-rw-r--r--arch/arm/Kconfig.debug9
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts6
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts4
-rw-r--r--arch/arm/configs/lager_defconfig150
-rw-r--r--arch/arm/configs/shmobile_defconfig1
-rw-r--r--arch/arm/include/debug/at91.S (renamed from arch/arm/mach-at91/include/mach/debug-macro.S)19
-rw-r--r--arch/arm/mach-at91/Kconfig8
-rw-r--r--arch/arm/mach-at91/Makefile6
-rw-r--r--arch/arm/mach-at91/at91sam9260.c2
-rw-r--r--arch/arm/mach-at91/at91sam9261.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263.c3
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c4
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c6
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c4
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c10
-rw-r--r--arch/arm/mach-at91/board-dt-rm9200.c2
-rw-r--r--arch/arm/mach-at91/generic.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pio.h80
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rtt.h35
-rw-r--r--arch/arm/mach-at91/include/mach/memory.h26
-rw-r--r--arch/arm/mach-at91/sama5d3.c6
-rw-r--r--arch/arm/mach-at91/setup.c18
-rw-r--r--arch/arm/mach-at91/sysirq_mask.c75
-rw-r--r--arch/arm/mach-davinci/Makefile2
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c31
-rw-r--r--arch/arm/mach-davinci/cdce949.c295
-rw-r--r--arch/arm/mach-davinci/include/mach/cdce949.h19
-rw-r--r--arch/arm/mach-davinci/serial.c10
-rw-r--r--arch/arm/mach-exynos/exynos.c39
-rw-r--r--arch/arm/mach-exynos/include/mach/dma.h26
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h3
-rw-r--r--arch/arm/mach-exynos/pm.c3
-rw-r--r--arch/arm/mach-exynos/regs-sys.h22
-rw-r--r--arch/arm/mach-exynos/suspend.c7
-rw-r--r--arch/arm/mach-omap1/irq.c5
-rw-r--r--arch/arm/mach-omap1/timer32k.c5
-rw-r--r--arch/arm/mach-omap2/Kconfig12
-rw-r--r--arch/arm/mach-omap2/Makefile9
-rw-r--r--arch/arm/mach-omap2/am35xx-emac.c114
-rw-r--r--arch/arm/mach-omap2/am35xx-emac.h15
-rw-r--r--arch/arm/mach-omap2/am35xx.h46
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c150
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c373
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c335
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c6
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c142
-rw-r--r--arch/arm/mach-omap2/clock.h1
-rw-r--r--arch/arm/mach-omap2/clock2xxx.h11
-rw-r--r--arch/arm/mach-omap2/cm2xxx.c10
-rw-r--r--arch/arm/mach-omap2/cm2xxx.h2
-rw-r--r--arch/arm/mach-omap2/cm33xx.c21
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c20
-rw-r--r--arch/arm/mach-omap2/omap-pm-noop.c196
-rw-r--r--arch/arm/mach-omap2/omap-pm.h192
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c232
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h16
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c33
-rw-r--r--arch/arm/mach-omap2/omap_phy_internal.c35
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c1
-rw-r--r--arch/arm/mach-omap2/pmu.c5
-rw-r--r--arch/arm/mach-omap2/powerdomain.c82
-rw-r--r--arch/arm/mach-omap2/powerdomain.h5
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h1
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h1
-rw-r--r--arch/arm/mach-omap2/usb-musb.c12
-rw-r--r--arch/arm/mach-omap2/usb.h2
-rw-r--r--arch/arm/mach-omap2/voltage.c110
-rw-r--r--arch/arm/mach-omap2/voltage.h13
-rw-r--r--arch/arm/mach-prima2/common.h15
-rw-r--r--arch/arm/mach-pxa/devices.c2
-rw-r--r--arch/arm/mach-realview/realview_eb.c3
-rw-r--r--arch/arm/mach-realview/realview_pb1176.c2
-rw-r--r--arch/arm/mach-realview/realview_pb11mp.c2
-rw-r--r--arch/arm/mach-realview/realview_pba8.c2
-rw-r--r--arch/arm/mach-realview/realview_pbx.c2
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig42
-rw-r--r--arch/arm/mach-s3c24xx/Makefile7
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2410.c182
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2412.c150
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2440.c193
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2443.c179
-rw-r--r--arch/arm/mach-s3c24xx/dma.c1465
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/dma.h159
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/dma.h15
-rw-r--r--arch/arm/mach-shmobile/Kconfig20
-rw-r--r--arch/arm/mach-shmobile/Makefile3
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot1
-rw-r--r--arch/arm/mach-shmobile/board-lager-reference.c39
-rw-r--r--arch/arm/mach-shmobile/board-lager.c840
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c459
-rw-r--r--arch/arm/mach-shmobile/r8a7790.h28
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c2
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c284
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c2
-rw-r--r--arch/arm/mach-versatile/core.c37
-rw-r--r--arch/arm/plat-iop/pmu.c2
-rw-r--r--arch/arm/plat-omap/dma.c8
-rw-r--r--arch/arm/plat-samsung/Kconfig15
-rw-r--r--arch/arm/plat-samsung/Makefile6
-rw-r--r--arch/arm/plat-samsung/dma-ops.c146
-rw-r--r--arch/arm/plat-samsung/dma.c84
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-core.h22
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-ops.h69
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-pl330.h121
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-s3c24xx.h73
-rw-r--r--arch/arm/plat-samsung/include/plat/dma.h130
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-dma.h151
-rw-r--r--arch/arm/plat-samsung/s3c-dma-ops.c146
-rw-r--r--drivers/dma/Kconfig2
-rw-r--r--drivers/rtc/Kconfig28
114 files changed, 177 insertions, 8286 deletions
diff --git a/Documentation/arm/Atmel/README b/Documentation/arm/Atmel/README
new file mode 100644
index 000000000000..c53a19b4aab2
--- /dev/null
+++ b/Documentation/arm/Atmel/README
@@ -0,0 +1,124 @@
1ARM Atmel SoCs (aka AT91)
2=========================
3
4
5Introduction
6------------
7This document gives useful information about the ARM Atmel SoCs that are
8currently supported in Linux Mainline (you know, the one on kernel.org).
9
10It is important to note that the Atmel | SMART ARM-based MPU product line is
11historically named "AT91" or "at91" throughout the Linux kernel development
12process even if this product prefix has completely disappeared from the
13official Atmel product name. Anyway, files, directories, git trees,
14git branches/tags and email subject always contain this "at91" sub-string.
15
16
17AT91 SoCs
18---------
19Documentation and detailled datasheet for each product are available on
20the Atmel website: http://www.atmel.com.
21
22 Flavors:
23 * ARM 920 based SoC
24 - at91rm9200
25 + Datasheet
26 http://www.atmel.com/Images/doc1768.pdf
27
28 * ARM 926 based SoCs
29 - at91sam9260
30 + Datasheet
31 http://www.atmel.com/Images/doc6221.pdf
32
33 - at91sam9xe
34 + Datasheet
35 http://www.atmel.com/Images/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9XE_Datasheet.pdf
36
37 - at91sam9261
38 + Datasheet
39 http://www.atmel.com/Images/doc6062.pdf
40
41 - at91sam9263
42 + Datasheet
43 http://www.atmel.com/Images/Atmel_6249_32-bit-ARM926EJ-S-Microcontroller_SAM9263_Datasheet.pdf
44
45 - at91sam9rl
46 + Datasheet
47 http://www.atmel.com/Images/doc6289.pdf
48
49 - at91sam9g20
50 + Datasheet
51 http://www.atmel.com/Images/doc6384.pdf
52
53 - at91sam9g45 family
54 - at91sam9g45
55 - at91sam9g46
56 - at91sam9m10
57 - at91sam9m11 (device superset)
58 + Datasheet
59 http://www.atmel.com/Images/Atmel-6437-32-bit-ARM926-Embedded-Microprocessor-SAM9M11_Datasheet.pdf
60
61 - at91sam9x5 family (aka "The 5 series")
62 - at91sam9g15
63 - at91sam9g25
64 - at91sam9g35
65 - at91sam9x25
66 - at91sam9x35
67 + Datasheet (can be considered as covering the whole family)
68 http://www.atmel.com/Images/Atmel_11055_32-bit-ARM926EJ-S-Microcontroller_SAM9X35_Datasheet.pdf
69
70 - at91sam9n12
71 + Datasheet
72 http://www.atmel.com/Images/Atmel_11063_32-bit-ARM926EJ-S-Microcontroller_SAM9N12CN11CN12_Datasheet.pdf
73
74 * ARM Cortex-A5 based SoCs
75 - sama5d3 family
76 - sama5d31
77 - sama5d33
78 - sama5d34
79 - sama5d35
80 - sama5d36 (device superset)
81 + Datasheet
82 http://www.atmel.com/Images/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf
83
84 * ARM Cortex-A5 + NEON based SoCs
85 - sama5d4 family
86 - sama5d41
87 - sama5d42
88 - sama5d43
89 - sama5d44 (device superset)
90 + Datasheet
91 http://www.atmel.com/Images/Atmel-11238-32-bit-Cortex-A5-Microcontroller-SAMA5D4_Datasheet.pdf
92
93
94Linux kernel information
95------------------------
96Linux kernel mach directory: arch/arm/mach-at91
97MAINTAINERS entry is: "ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES"
98
99
100Device Tree for AT91 SoCs and boards
101------------------------------------
102All AT91 SoCs are converted to Device Tree. Since Linux 3.19, these products
103must use this method to boot the Linux kernel.
104
105Work In Progress statement:
106Device Tree files and Device Tree bindings that apply to AT91 SoCs and boards are
107considered as "Unstable". To be completely clear, any at91 binding can change at
108any time. So, be sure to use a Device Tree Binary and a Kernel Image generated from
109the same source tree.
110Please refer to the Documentation/devicetree/bindings/ABI.txt file for a
111definition of a "Stable" binding/ABI.
112This statement will be removed by AT91 MAINTAINERS when appropriate.
113
114Naming conventions and best practice:
115- SoCs Device Tree Source Include files are named after the official name of
116 the product (at91sam9g20.dtsi or sama5d33.dtsi for instance).
117- Device Tree Source Include files (.dtsi) are used to collect common nodes that can be
118 shared across SoCs or boards (sama5d3.dtsi or at91sam9x5cm.dtsi for instance).
119 When collecting nodes for a particular peripheral or topic, the identifier have to
120 be placed at the end of the file name, separated with a "_" (at91sam9x5_can.dtsi
121 or sama5d3_gmac.dtsi for example).
122- board Device Tree Source files (.dts) are prefixed by the string "at91-" so
123 that they can be identified easily. Note that some files are historical exceptions
124 to this rule (sama5d3[13456]ek.dts, usb_a9g20.dts or animeo_ip.dts for example).
diff --git a/Documentation/arm/Samsung-S3C24XX/DMA.txt b/Documentation/arm/Samsung-S3C24XX/DMA.txt
deleted file mode 100644
index 3ed82383efea..000000000000
--- a/Documentation/arm/Samsung-S3C24XX/DMA.txt
+++ /dev/null
@@ -1,46 +0,0 @@
1 S3C2410 DMA
2 ===========
3
4Introduction
5------------
6
7 The kernel provides an interface to manage DMA transfers
8 using the DMA channels in the CPU, so that the central
9 duty of managing channel mappings, and programming the
10 channel generators is in one place.
11
12
13DMA Channel Ordering
14--------------------
15
16 Many of the range do not have connections for the DMA
17 channels to all sources, which means that some devices
18 have a restricted number of channels that can be used.
19
20 To allow flexibility for each CPU type and board, the
21 DMA code can be given a DMA ordering structure which
22 allows the order of channel search to be specified, as
23 well as allowing the prohibition of certain claims.
24
25 struct s3c24xx_dma_order has a list of channels, and
26 each channel within has a slot for a list of DMA
27 channel numbers. The slots are searched in order for
28 the presence of a DMA channel number with DMA_CH_VALID
29 or-ed in.
30
31 If the order has the flag DMA_CH_NEVER set, then after
32 checking the channel list, the system will return no
33 found channel, thus denying the request.
34
35 A board support file can call s3c24xx_dma_order_set()
36 to register a complete ordering set. The routine will
37 copy the data, so the original can be discarded with
38 __initdata.
39
40
41Authour
42-------
43
44Ben Dooks,
45Copyright (c) 2007 Ben Dooks, Simtec Electronics
46Licensed under the GPL v2
diff --git a/MAINTAINERS b/MAINTAINERS
index b27178c87444..bfe852899647 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -895,6 +895,7 @@ F: arch/arm/boot/dts/at91*.dts
895F: arch/arm/boot/dts/at91*.dtsi 895F: arch/arm/boot/dts/at91*.dtsi
896F: arch/arm/boot/dts/sama*.dts 896F: arch/arm/boot/dts/sama*.dts
897F: arch/arm/boot/dts/sama*.dtsi 897F: arch/arm/boot/dts/sama*.dtsi
898F: arch/arm/include/debug/at91.S
898 899
899ARM/ATMEL AT91 Clock Support 900ARM/ATMEL AT91 Clock Support
900M: Boris Brezillon <boris.brezillon@free-electrons.com> 901M: Boris Brezillon <boris.brezillon@free-electrons.com>
@@ -1414,7 +1415,6 @@ F: arch/arm/configs/ape6evm_defconfig
1414F: arch/arm/configs/armadillo800eva_defconfig 1415F: arch/arm/configs/armadillo800eva_defconfig
1415F: arch/arm/configs/bockw_defconfig 1416F: arch/arm/configs/bockw_defconfig
1416F: arch/arm/configs/kzm9g_defconfig 1417F: arch/arm/configs/kzm9g_defconfig
1417F: arch/arm/configs/lager_defconfig
1418F: arch/arm/configs/mackerel_defconfig 1418F: arch/arm/configs/mackerel_defconfig
1419F: arch/arm/configs/marzen_defconfig 1419F: arch/arm/configs/marzen_defconfig
1420F: arch/arm/configs/shmobile_defconfig 1420F: arch/arm/configs/shmobile_defconfig
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a324ecdfeb21..8fecefe881cd 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -115,15 +115,18 @@ choice
115 0x80024000 | 0xf0024000 | UART9 115 0x80024000 | 0xf0024000 | UART9
116 116
117 config AT91_DEBUG_LL_DBGU0 117 config AT91_DEBUG_LL_DBGU0
118 bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl" 118 bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10, 9rl, 9x5, 9n12"
119 select DEBUG_AT91_UART
119 depends on HAVE_AT91_DBGU0 120 depends on HAVE_AT91_DBGU0
120 121
121 config AT91_DEBUG_LL_DBGU1 122 config AT91_DEBUG_LL_DBGU1
122 bool "Kernel low-level debugging on 9263 and 9g45" 123 bool "Kernel low-level debugging on 9263, 9g45 and sama5d3"
124 select DEBUG_AT91_UART
123 depends on HAVE_AT91_DBGU1 125 depends on HAVE_AT91_DBGU1
124 126
125 config AT91_DEBUG_LL_DBGU2 127 config AT91_DEBUG_LL_DBGU2
126 bool "Kernel low-level debugging on sama5d4" 128 bool "Kernel low-level debugging on sama5d4"
129 select DEBUG_AT91_UART
127 depends on HAVE_AT91_DBGU2 130 depends on HAVE_AT91_DBGU2
128 131
129 config DEBUG_BCM2835 132 config DEBUG_BCM2835
@@ -1218,6 +1221,8 @@ config DEBUG_LL_INCLUDE
1218 string 1221 string
1219 default "debug/sa1100.S" if DEBUG_SA1100 1222 default "debug/sa1100.S" if DEBUG_SA1100
1220 default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 1223 default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
1224 default "debug/at91.S" if AT91_DEBUG_LL_DBGU0 || AT91_DEBUG_LL_DBGU1 || \
1225 AT91_DEBUG_LL_DBGU2
1221 default "debug/asm9260.S" if DEBUG_ASM9260_UART 1226 default "debug/asm9260.S" if DEBUG_ASM9260_UART
1222 default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2 1227 default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
1223 default "debug/meson.S" if DEBUG_MESON_UARTAO 1228 default "debug/meson.S" if DEBUG_MESON_UARTAO
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 91bd5bd62857..19cb6fcecf89 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -410,7 +410,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
410 r8a7778-bockw.dtb \ 410 r8a7778-bockw.dtb \
411 r8a7778-bockw-reference.dtb \ 411 r8a7778-bockw-reference.dtb \
412 r8a7779-marzen.dtb \ 412 r8a7779-marzen.dtb \
413 r8a7790-lager.dtb \
414 sh7372-mackerel.dtb \ 413 sh7372-mackerel.dtb \
415 sh73a0-kzm9g.dtb \ 414 sh73a0-kzm9g.dtb \
416 sh73a0-kzm9g-reference.dtb 415 sh73a0-kzm9g-reference.dtb
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 636d53bb87a2..4118030f366d 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -47,12 +47,12 @@
47 compatible = "renesas,lager", "renesas,r8a7790"; 47 compatible = "renesas,lager", "renesas,r8a7790";
48 48
49 aliases { 49 aliases {
50 serial6 = &scifa0; 50 serial0 = &scifa0;
51 serial7 = &scifa1; 51 serial1 = &scifa1;
52 }; 52 };
53 53
54 chosen { 54 chosen {
55 bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; 55 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
56 stdout-path = &scifa0; 56 stdout-path = &scifa0;
57 }; 57 };
58 58
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 990af167c551..bf58c79a6554 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -48,8 +48,8 @@
48 compatible = "renesas,koelsch", "renesas,r8a7791"; 48 compatible = "renesas,koelsch", "renesas,r8a7791";
49 49
50 aliases { 50 aliases {
51 serial6 = &scif0; 51 serial0 = &scif0;
52 serial7 = &scif1; 52 serial1 = &scif1;
53 }; 53 };
54 54
55 chosen { 55 chosen {
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
deleted file mode 100644
index a82afc916a89..000000000000
--- a/arch/arm/configs/lager_defconfig
+++ /dev/null
@@ -1,150 +0,0 @@
1CONFIG_SYSVIPC=y
2CONFIG_NO_HZ=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6CONFIG_CC_OPTIMIZE_FOR_SIZE=y
7CONFIG_SYSCTL_SYSCALL=y
8CONFIG_EMBEDDED=y
9CONFIG_PERF_EVENTS=y
10CONFIG_SLAB=y
11# CONFIG_LBDAF is not set
12# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set
15CONFIG_ARCH_SHMOBILE_LEGACY=y
16CONFIG_ARCH_R8A7790=y
17CONFIG_MACH_LAGER=y
18# CONFIG_SH_TIMER_TMU is not set
19# CONFIG_EM_TIMER_STI is not set
20CONFIG_ARM_ERRATA_430973=y
21CONFIG_ARM_ERRATA_458693=y
22CONFIG_ARM_ERRATA_460075=y
23CONFIG_ARM_ERRATA_743622=y
24CONFIG_ARM_ERRATA_754322=y
25CONFIG_PCI=y
26CONFIG_PCI_RCAR_GEN2=y
27CONFIG_PCI_RCAR_GEN2_PCIE=y
28CONFIG_HAVE_ARM_ARCH_TIMER=y
29CONFIG_AEABI=y
30# CONFIG_OABI_COMPAT is not set
31CONFIG_FORCE_MAX_ZONEORDER=13
32CONFIG_ZBOOT_ROM_TEXT=0x0
33CONFIG_ZBOOT_ROM_BSS=0x0
34CONFIG_ARM_APPENDED_DTB=y
35CONFIG_KEXEC=y
36CONFIG_AUTO_ZRELADDR=y
37CONFIG_VFP=y
38CONFIG_NEON=y
39# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
40CONFIG_PM=y
41CONFIG_NET=y
42CONFIG_PACKET=y
43CONFIG_UNIX=y
44CONFIG_INET=y
45CONFIG_IP_PNP=y
46CONFIG_IP_PNP_DHCP=y
47# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
48# CONFIG_INET_XFRM_MODE_TUNNEL is not set
49# CONFIG_INET_XFRM_MODE_BEET is not set
50# CONFIG_INET_LRO is not set
51# CONFIG_INET_DIAG is not set
52# CONFIG_IPV6 is not set
53# CONFIG_WIRELESS is not set
54CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
55CONFIG_DEVTMPFS=y
56CONFIG_DEVTMPFS_MOUNT=y
57CONFIG_MTD=y
58CONFIG_MTD_M25P80=y
59CONFIG_MTD_SPI_NOR=y
60CONFIG_BLK_DEV_SD=y
61CONFIG_ATA=y
62CONFIG_SATA_RCAR=y
63CONFIG_NETDEVICES=y
64# CONFIG_NET_CORE is not set
65# CONFIG_NET_VENDOR_ARC is not set
66# CONFIG_NET_CADENCE is not set
67# CONFIG_NET_VENDOR_BROADCOM is not set
68# CONFIG_NET_VENDOR_CIRRUS is not set
69# CONFIG_NET_VENDOR_FARADAY is not set
70# CONFIG_NET_VENDOR_INTEL is not set
71# CONFIG_NET_VENDOR_MARVELL is not set
72# CONFIG_NET_VENDOR_MICREL is not set
73# CONFIG_NET_VENDOR_NATSEMI is not set
74CONFIG_SH_ETH=y
75# CONFIG_NET_VENDOR_SEEQ is not set
76# CONFIG_NET_VENDOR_SMSC is not set
77# CONFIG_NET_VENDOR_STMICRO is not set
78# CONFIG_NET_VENDOR_VIA is not set
79# CONFIG_NET_VENDOR_WIZNET is not set
80# CONFIG_WLAN is not set
81# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
82CONFIG_INPUT_EVDEV=y
83# CONFIG_KEYBOARD_ATKBD is not set
84CONFIG_KEYBOARD_GPIO=y
85# CONFIG_INPUT_MOUSE is not set
86# CONFIG_SERIO is not set
87# CONFIG_LEGACY_PTYS is not set
88CONFIG_SERIAL_SH_SCI=y
89CONFIG_SERIAL_SH_SCI_NR_UARTS=10
90CONFIG_SERIAL_SH_SCI_CONSOLE=y
91# CONFIG_HW_RANDOM is not set
92CONFIG_I2C_GPIO=y
93CONFIG_I2C_SH_MOBILE=y
94CONFIG_I2C_RCAR=y
95CONFIG_SPI=y
96CONFIG_SPI_RSPI=y
97CONFIG_SPI_SH_MSIOF=y
98CONFIG_GPIO_SH_PFC=y
99CONFIG_GPIOLIB=y
100CONFIG_GPIO_RCAR=y
101# CONFIG_HWMON is not set
102CONFIG_THERMAL=y
103CONFIG_RCAR_THERMAL=y
104CONFIG_REGULATOR=y
105CONFIG_REGULATOR_FIXED_VOLTAGE=y
106CONFIG_REGULATOR_DA9210=y
107CONFIG_REGULATOR_GPIO=y
108CONFIG_MEDIA_SUPPORT=y
109CONFIG_MEDIA_CAMERA_SUPPORT=y
110CONFIG_V4L_PLATFORM_DRIVERS=y
111CONFIG_SOC_CAMERA=y
112CONFIG_SOC_CAMERA_PLATFORM=y
113CONFIG_VIDEO_RCAR_VIN=y
114# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
115CONFIG_VIDEO_ADV7180=y
116CONFIG_DRM=y
117CONFIG_DRM_RCAR_DU=y
118CONFIG_SOUND=y
119CONFIG_SND=y
120CONFIG_SND_SOC=y
121CONFIG_SND_SOC_RCAR=y
122# CONFIG_USB_SUPPORT is not set
123CONFIG_MMC=y
124CONFIG_MMC_SDHI=y
125CONFIG_MMC_SH_MMCIF=y
126CONFIG_NEW_LEDS=y
127CONFIG_LEDS_CLASS=y
128CONFIG_LEDS_GPIO=y
129CONFIG_RTC_CLASS=y
130CONFIG_DMADEVICES=y
131CONFIG_SH_DMAE=y
132# CONFIG_IOMMU_SUPPORT is not set
133# CONFIG_DNOTIFY is not set
134CONFIG_MSDOS_FS=y
135CONFIG_VFAT_FS=y
136CONFIG_TMPFS=y
137CONFIG_CONFIGFS_FS=y
138# CONFIG_MISC_FILESYSTEMS is not set
139CONFIG_NFS_FS=y
140CONFIG_NFS_V3_ACL=y
141CONFIG_NFS_V4=y
142CONFIG_NFS_V4_1=y
143CONFIG_ROOT_NFS=y
144CONFIG_NLS_CODEPAGE_437=y
145CONFIG_NLS_ISO8859_1=y
146# CONFIG_ENABLE_WARN_DEPRECATED is not set
147# CONFIG_ENABLE_MUST_CHECK is not set
148# CONFIG_ARM_UNWIND is not set
149# CONFIG_CRYPTO_ANSI_CPRNG is not set
150# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 3df6ca0c1d1f..e4a6c5e9174d 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_R8A7779=y
17CONFIG_ARCH_R8A7790=y 17CONFIG_ARCH_R8A7790=y
18CONFIG_ARCH_R8A7791=y 18CONFIG_ARCH_R8A7791=y
19CONFIG_ARCH_R8A7794=y 19CONFIG_ARCH_R8A7794=y
20CONFIG_MACH_LAGER=y
21CONFIG_MACH_MARZEN=y 20CONFIG_MACH_MARZEN=y
22# CONFIG_SWP_EMULATE is not set 21# CONFIG_SWP_EMULATE is not set
23CONFIG_CPU_BPREDICT_DISABLE=y 22CONFIG_CPU_BPREDICT_DISABLE=y
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/include/debug/at91.S
index 2103a90f2261..80a6501b4d50 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/at91.S
@@ -1,6 +1,4 @@
1/* 1/*
2 * arch/arm/mach-at91/include/mach/debug-macro.S
3 *
4 * Copyright (C) 2003-2005 SAN People 2 * Copyright (C) 2003-2005 SAN People
5 * 3 *
6 * Debugging macro include header 4 * Debugging macro include header
@@ -11,18 +9,23 @@
11 * 9 *
12*/ 10*/
13 11
14#include <mach/hardware.h>
15#include <mach/at91_dbgu.h>
16
17#if defined(CONFIG_AT91_DEBUG_LL_DBGU0) 12#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
18#define AT91_DBGU AT91_BASE_DBGU0 13#define AT91_DBGU 0xfffff200 /* AT91_BASE_DBGU0 */
19#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1) 14#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
20#define AT91_DBGU AT91_BASE_DBGU1 15#define AT91_DBGU 0xffffee00 /* AT91_BASE_DBGU1 */
21#else 16#else
22/* On sama5d4, use USART3 as low level serial console */ 17/* On sama5d4, use USART3 as low level serial console */
23#define AT91_DBGU SAMA5D4_BASE_USART3 18#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */
24#endif 19#endif
25 20
21/* Keep in sync with mach-at91/include/mach/hardware.h */
22#define AT91_IO_P2V(x) ((x) - 0x01000000)
23
24#define AT91_DBGU_SR (0x14) /* Status Register */
25#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
26#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
27#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
28
26 .macro addruart, rp, rv, tmp 29 .macro addruart, rp, rv, tmp
27 ldr \rp, =AT91_DBGU @ System peripherals (phys address) 30 ldr \rp, =AT91_DBGU @ System peripherals (phys address)
28 ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address) 31 ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 2395c68b3e32..cec0fb5d621a 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -174,14 +174,6 @@ config SOC_AT91SAM9N12
174# ---------------------------------------------------------- 174# ----------------------------------------------------------
175endif # SOC_SAM_V4_V5 175endif # SOC_SAM_V4_V5
176 176
177config MACH_AT91RM9200_DT
178 def_bool SOC_AT91RM9200
179
180config MACH_AT91SAM9_DT
181 def_bool SOC_AT91SAM9
182
183# ----------------------------------------------------------
184
185comment "AT91 Feature Selections" 177comment "AT91 Feature Selections"
186 178
187config AT91_SLOW_CLOCK 179config AT91_SLOW_CLOCK
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 7b6424d40764..8ef7d9a2e855 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := setup.o sysirq_mask.o 5obj-y := setup.o
6 6
7obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o 7obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
8 8
@@ -19,8 +19,8 @@ obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
19obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o 19obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
20 20
21# AT91SAM board with device-tree 21# AT91SAM board with device-tree
22obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o 22obj-$(CONFIG_SOC_AT91RM9200) += board-dt-rm9200.o
23obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o 23obj-$(CONFIG_SOC_AT91SAM9) += board-dt-sam9.o
24 24
25# SAMA5 board with device-tree 25# SAMA5 board with device-tree
26obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o 26obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 78137c24d90b..34e2abe82ae4 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -51,8 +51,6 @@ static void __init at91sam9260_map_io(void)
51static void __init at91sam9260_initialize(void) 51static void __init at91sam9260_initialize(void)
52{ 52{
53 arm_pm_idle = at91sam9_idle; 53 arm_pm_idle = at91sam9_idle;
54
55 at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
56} 54}
57 55
58AT91_SOC_START(at91sam9260) 56AT91_SOC_START(at91sam9260)
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index d29953ecb0c4..47878b849975 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -32,8 +32,6 @@ static void __init at91sam9261_map_io(void)
32static void __init at91sam9261_initialize(void) 32static void __init at91sam9261_initialize(void)
33{ 33{
34 arm_pm_idle = at91sam9_idle; 34 arm_pm_idle = at91sam9_idle;
35
36 at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
37} 35}
38 36
39AT91_SOC_START(at91sam9261) 37AT91_SOC_START(at91sam9261)
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index e7ad14864083..aabcb66145d0 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -29,9 +29,6 @@ static void __init at91sam9263_map_io(void)
29static void __init at91sam9263_initialize(void) 29static void __init at91sam9263_initialize(void)
30{ 30{
31 arm_pm_idle = at91sam9_idle; 31 arm_pm_idle = at91sam9_idle;
32
33 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
34 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
35} 32}
36 33
37AT91_SOC_START(at91sam9263) 34AT91_SOC_START(at91sam9263)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index b6117bea9a6f..000166777a8d 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -11,7 +11,6 @@
11 */ 11 */
12 12
13#include <asm/system_misc.h> 13#include <asm/system_misc.h>
14#include <asm/irq.h>
15#include <mach/hardware.h> 14#include <mach/hardware.h>
16 15
17#include "soc.h" 16#include "soc.h"
@@ -29,9 +28,6 @@ static void __init at91sam9g45_map_io(void)
29static void __init at91sam9g45_initialize(void) 28static void __init at91sam9g45_initialize(void)
30{ 29{
31 arm_pm_idle = at91sam9_idle; 30 arm_pm_idle = at91sam9_idle;
32
33 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
34 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
35} 31}
36 32
37AT91_SOC_START(at91sam9g45) 33AT91_SOC_START(at91sam9g45)
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index dee569b1987e..0135f868ea4f 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -21,12 +21,6 @@ static void __init at91sam9n12_map_io(void)
21 at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); 21 at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
22} 22}
23 23
24static void __init at91sam9n12_initialize(void)
25{
26 at91_sysirq_mask_rtc(AT91SAM9N12_BASE_RTC);
27}
28
29AT91_SOC_START(at91sam9n12) 24AT91_SOC_START(at91sam9n12)
30 .map_io = at91sam9n12_map_io, 25 .map_io = at91sam9n12_map_io,
31 .init = at91sam9n12_initialize,
32AT91_SOC_END 26AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f25b9aec9c50..1babfb27694a 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,7 +10,6 @@
10 */ 10 */
11 11
12#include <asm/system_misc.h> 12#include <asm/system_misc.h>
13#include <asm/irq.h>
14#include <mach/cpu.h> 13#include <mach/cpu.h>
15#include <mach/at91_dbgu.h> 14#include <mach/at91_dbgu.h>
16#include <mach/hardware.h> 15#include <mach/hardware.h>
@@ -42,9 +41,6 @@ static void __init at91sam9rl_map_io(void)
42static void __init at91sam9rl_initialize(void) 41static void __init at91sam9rl_initialize(void)
43{ 42{
44 arm_pm_idle = at91sam9_idle; 43 arm_pm_idle = at91sam9_idle;
45
46 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
47 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
48} 44}
49 45
50AT91_SOC_START(at91sam9rl) 46AT91_SOC_START(at91sam9rl)
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index f0d5a69a7237..aa17520ccb0a 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -21,16 +21,6 @@ static void __init at91sam9x5_map_io(void)
21 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE); 21 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
22} 22}
23 23
24static void __init at91sam9x5_initialize(void)
25{
26 at91_sysirq_mask_rtc(AT91SAM9X5_BASE_RTC);
27}
28
29/* --------------------------------------------------------------------
30 * Interrupt initialization
31 * -------------------------------------------------------------------- */
32
33AT91_SOC_START(at91sam9x5) 24AT91_SOC_START(at91sam9x5)
34 .map_io = at91sam9x5_map_io, 25 .map_io = at91sam9x5_map_io,
35 .init = at91sam9x5_initialize,
36AT91_SOC_END 26AT91_SOC_END
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 76dfe8f9af50..a15ab6f8de00 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -38,6 +38,6 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
38DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)") 38DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
39 .init_time = at91rm9200_dt_timer_init, 39 .init_time = at91rm9200_dt_timer_init,
40 .map_io = at91_map_io, 40 .map_io = at91_map_io,
41 .init_early = at91rm9200_dt_initialize, 41 .init_early = at91_dt_initialize,
42 .dt_compat = at91rm9200_dt_board_compat, 42 .dt_compat = at91rm9200_dt_board_compat,
43MACHINE_END 43MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index d53324210adf..54f3837a0a4d 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -21,14 +21,8 @@ extern void __init at91_init_sram(int bank, unsigned long base,
21 unsigned int length); 21 unsigned int length);
22 22
23 /* Processors */ 23 /* Processors */
24extern void __init at91rm9200_set_type(int type);
25extern void __init at91rm9200_dt_initialize(void);
26extern void __init at91_dt_initialize(void); 24extern void __init at91_dt_initialize(void);
27 25
28 /* Interrupts */
29extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
30extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
31
32 /* Timer */ 26 /* Timer */
33extern void at91rm9200_timer_init(void); 27extern void at91rm9200_timer_init(void);
34 28
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
deleted file mode 100644
index 7b7366253ceb..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_pio.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Parallel I/O Controller (PIO) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_PIO_H
17#define AT91_PIO_H
18
19#define PIO_PER 0x00 /* Enable Register */
20#define PIO_PDR 0x04 /* Disable Register */
21#define PIO_PSR 0x08 /* Status Register */
22#define PIO_OER 0x10 /* Output Enable Register */
23#define PIO_ODR 0x14 /* Output Disable Register */
24#define PIO_OSR 0x18 /* Output Status Register */
25#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
26#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
27#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
28#define PIO_SODR 0x30 /* Set Output Data Register */
29#define PIO_CODR 0x34 /* Clear Output Data Register */
30#define PIO_ODSR 0x38 /* Output Data Status Register */
31#define PIO_PDSR 0x3c /* Pin Data Status Register */
32#define PIO_IER 0x40 /* Interrupt Enable Register */
33#define PIO_IDR 0x44 /* Interrupt Disable Register */
34#define PIO_IMR 0x48 /* Interrupt Mask Register */
35#define PIO_ISR 0x4c /* Interrupt Status Register */
36#define PIO_MDER 0x50 /* Multi-driver Enable Register */
37#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
38#define PIO_MDSR 0x58 /* Multi-driver Status Register */
39#define PIO_PUDR 0x60 /* Pull-up Disable Register */
40#define PIO_PUER 0x64 /* Pull-up Enable Register */
41#define PIO_PUSR 0x68 /* Pull-up Status Register */
42#define PIO_ASR 0x70 /* Peripheral A Select Register */
43#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */
44#define PIO_BSR 0x74 /* Peripheral B Select Register */
45#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */
46#define PIO_ABSR 0x78 /* AB Status Register */
47#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
48#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
49#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
50#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
51#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
52#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
53#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
54#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */
55#define PIO_OWER 0xa0 /* Output Write Enable Register */
56#define PIO_OWDR 0xa4 /* Output Write Disable Register */
57#define PIO_OWSR 0xa8 /* Output Write Status Register */
58#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */
59#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */
60#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */
61#define PIO_ESR 0xc0 /* Edge Select Register */
62#define PIO_LSR 0xc4 /* Level Select Register */
63#define PIO_ELSR 0xc8 /* Edge/Level Status Register */
64#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */
65#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */
66#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */
67#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */
68
69#define ABCDSR_PERIPH_A 0x0
70#define ABCDSR_PERIPH_B 0x1
71#define ABCDSR_PERIPH_C 0x2
72#define ABCDSR_PERIPH_D 0x3
73
74#define SAMA5D3_PIO_DRIVER1 0x118 /*PIO Driver 1 register offset*/
75#define SAMA5D3_PIO_DRIVER2 0x11C /*PIO Driver 2 register offset*/
76
77#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
78#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
79
80#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h
deleted file mode 100644
index 7ec75de8bbb6..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_rtt.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_rtt.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * Real-time Timer (RTT) - System peripherals regsters.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_RTT_H
17#define AT91_RTT_H
18
19#define AT91_RTT_MR 0x00 /* Real-time Mode Register */
20#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
21#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
22#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
23#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
24
25#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
26#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
27
28#define AT91_RTT_VR 0x08 /* Real-time Value Register */
29#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
30
31#define AT91_RTT_SR 0x0c /* Real-time Status Register */
32#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
33#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
34
35#endif
diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h
deleted file mode 100644
index 401c207f2f39..000000000000
--- a/arch/arm/mach-at91/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/memory.h
3 *
4 * Copyright (C) 2004 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_MEMORY_H
22#define __ASM_ARCH_MEMORY_H
23
24#include <mach/hardware.h>
25
26#endif
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 3d775d08de08..ae58feada72b 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -30,12 +30,6 @@ static void __init sama5d3_map_io(void)
30 at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); 30 at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
31} 31}
32 32
33static void __init sama5d3_initialize(void)
34{
35 at91_sysirq_mask_rtc(SAMA5D3_BASE_RTC);
36}
37
38AT91_SOC_START(sama5d3) 33AT91_SOC_START(sama5d3)
39 .map_io = sama5d3_map_io, 34 .map_io = sama5d3_map_io,
40 .init = sama5d3_initialize,
41AT91_SOC_END 35AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index ce25e85720fb..e3c21b458bb8 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -31,17 +31,6 @@ struct at91_init_soc __initdata at91_boot_soc;
31struct at91_socinfo at91_soc_initdata; 31struct at91_socinfo at91_soc_initdata;
32EXPORT_SYMBOL(at91_soc_initdata); 32EXPORT_SYMBOL(at91_soc_initdata);
33 33
34void __init at91rm9200_set_type(int type)
35{
36 if (type == ARCH_REVISON_9200_PQFP)
37 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
38 else
39 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
40
41 pr_info("filled in soc subtype: %s\n",
42 at91_get_soc_subtype(&at91_soc_initdata));
43}
44
45void __iomem *at91_ramc_base[2]; 34void __iomem *at91_ramc_base[2];
46EXPORT_SYMBOL_GPL(at91_ramc_base); 35EXPORT_SYMBOL_GPL(at91_ramc_base);
47 36
@@ -429,13 +418,6 @@ static void at91_dt_ramc(void)
429 at91_pm_set_standby(standby); 418 at91_pm_set_standby(standby);
430} 419}
431 420
432void __init at91rm9200_dt_initialize(void)
433{
434 at91_dt_ramc();
435
436 at91_boot_soc.init();
437}
438
439void __init at91_dt_initialize(void) 421void __init at91_dt_initialize(void)
440{ 422{
441 at91_dt_ramc(); 423 at91_dt_ramc();
diff --git a/arch/arm/mach-at91/sysirq_mask.c b/arch/arm/mach-at91/sysirq_mask.c
deleted file mode 100644
index f8bc3511a8c8..000000000000
--- a/arch/arm/mach-at91/sysirq_mask.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * sysirq_mask.c - System-interrupt masking
3 *
4 * Copyright (C) 2013 Johan Hovold <jhovold@gmail.com>
5 *
6 * Functions to disable system interrupts from backup-powered peripherals.
7 *
8 * The RTC and RTT-peripherals are generally powered by backup power (VDDBU)
9 * and are not reset on wake-up, user, watchdog or software reset. This means
10 * that their interrupts may be enabled during early boot (e.g. after a user
11 * reset).
12 *
13 * As the RTC and RTT share the system-interrupt line with the PIT, an
14 * interrupt occurring before a handler has been installed would lead to the
15 * system interrupt being disabled and prevent the system from booting.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 */
22
23#include <linux/io.h>
24#include <mach/at91_rtt.h>
25
26#include "generic.h"
27
28#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
29#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */
30#define AT91_RTC_IRQ_MASK 0x1f /* Available IRQs mask */
31
32void __init at91_sysirq_mask_rtc(u32 rtc_base)
33{
34 void __iomem *base;
35
36 base = ioremap(rtc_base, 64);
37 if (!base)
38 return;
39
40 /*
41 * sam9x5 SoCs have the following errata:
42 * "RTC: Interrupt Mask Register cannot be used
43 * Interrupt Mask Register read always returns 0."
44 *
45 * Hence we're not relying on IMR values to disable
46 * interrupts.
47 */
48 writel_relaxed(AT91_RTC_IRQ_MASK, base + AT91_RTC_IDR);
49 (void)readl_relaxed(base + AT91_RTC_IMR); /* flush */
50
51 iounmap(base);
52}
53
54void __init at91_sysirq_mask_rtt(u32 rtt_base)
55{
56 void __iomem *base;
57 void __iomem *reg;
58 u32 mode;
59
60 base = ioremap(rtt_base, 16);
61 if (!base)
62 return;
63
64 reg = base + AT91_RTT_MR;
65
66 mode = readl_relaxed(reg);
67 if (mode & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)) {
68 pr_info("AT91: Disabling rtt irq\n");
69 mode &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
70 writel_relaxed(mode, reg);
71 (void)readl_relaxed(reg); /* flush */
72 }
73
74 iounmap(base);
75}
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2204239ed243..2e3464b8bab4 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
27obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o 27obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
28obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o 28obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
29obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o 29obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
30obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o 30obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o
31obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o 31obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
32obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o 32obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
33obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o 33obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index ae129bc49273..846a84ddc28e 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -45,7 +45,6 @@
45#include <mach/irqs.h> 45#include <mach/irqs.h>
46#include <mach/serial.h> 46#include <mach/serial.h>
47#include <mach/clock.h> 47#include <mach/clock.h>
48#include <mach/cdce949.h>
49 48
50#include "davinci.h" 49#include "davinci.h"
51#include "clock.h" 50#include "clock.h"
@@ -399,9 +398,6 @@ static struct i2c_board_info __initdata i2c_info[] = {
399 { 398 {
400 I2C_BOARD_INFO("cpld_video", 0x3b), 399 I2C_BOARD_INFO("cpld_video", 0x3b),
401 }, 400 },
402 {
403 I2C_BOARD_INFO("cdce949", 0x6c),
404 },
405}; 401};
406 402
407static struct davinci_i2c_platform_data i2c_pdata = { 403static struct davinci_i2c_platform_data i2c_pdata = {
@@ -715,31 +711,6 @@ static void __init evm_init_i2c(void)
715 evm_init_video(); 711 evm_init_video();
716} 712}
717 713
718#define CDCE949_XIN_RATE 27000000
719
720/* CDCE949 support - "lpsc" field is overridden to work as clock number */
721static struct clk cdce_clk_in = {
722 .name = "cdce_xin",
723 .rate = CDCE949_XIN_RATE,
724};
725
726static struct clk_lookup cdce_clks[] = {
727 CLK(NULL, "xin", &cdce_clk_in),
728 CLK(NULL, NULL, NULL),
729};
730
731static void __init cdce_clk_init(void)
732{
733 struct clk_lookup *c;
734 struct clk *clk;
735
736 for (c = cdce_clks; c->clk; c++) {
737 clk = c->clk;
738 clkdev_add(c);
739 clk_register(clk);
740 }
741}
742
743#define DM6467T_EVM_REF_FREQ 33000000 714#define DM6467T_EVM_REF_FREQ 33000000
744 715
745static void __init davinci_map_io(void) 716static void __init davinci_map_io(void)
@@ -748,8 +719,6 @@ static void __init davinci_map_io(void)
748 719
749 if (machine_is_davinci_dm6467tevm()) 720 if (machine_is_davinci_dm6467tevm())
750 davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ); 721 davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
751
752 cdce_clk_init();
753} 722}
754 723
755#define DM646X_EVM_PHY_ID "davinci_mdio-0:01" 724#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
deleted file mode 100644
index abafb92031c0..000000000000
--- a/arch/arm/mach-davinci/cdce949.c
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * TI CDCE949 clock synthesizer driver
3 *
4 * Note: This implementation assumes an input of 27MHz to the CDCE.
5 * This is by no means constrained by CDCE hardware although the datasheet
6 * does use this as an example for all illustrations and more importantly:
7 * that is the crystal input on boards it is currently used on.
8 *
9 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21
22#include <mach/clock.h>
23#include <mach/cdce949.h>
24
25#include "clock.h"
26
27static struct i2c_client *cdce_i2c_client;
28static DEFINE_MUTEX(cdce_mutex);
29
30/* CDCE register descriptor */
31struct cdce_reg {
32 u8 addr;
33 u8 val;
34};
35
36/* Per-Output (Y1, Y2 etc.) frequency descriptor */
37struct cdce_freq {
38 /* Frequency in KHz */
39 unsigned long frequency;
40 /*
41 * List of registers to program to obtain a particular frequency.
42 * 0x0 in register address and value is the end of list marker.
43 */
44 struct cdce_reg *reglist;
45};
46
47#define CDCE_FREQ_TABLE_ENTRY(line, out) \
48{ \
49 .reglist = cdce_y ##line## _ ##out, \
50 .frequency = out, \
51}
52
53/* List of CDCE outputs */
54struct cdce_output {
55 /* List of frequencies on this output */
56 struct cdce_freq *freq_table;
57 /* Number of possible frequencies */
58 int size;
59};
60
61/*
62 * Finding out the values to program into CDCE949 registers for a particular
63 * frequency output is not a simple calculation. Have a look at the datasheet
64 * for the details. There is desktop software available to help users with
65 * the calculations. Here, we just depend on the output of that software
66 * (or hand calculations) instead trying to runtime calculate the register
67 * values and inflicting misery on ourselves.
68 */
69static struct cdce_reg cdce_y1_148500[] = {
70 { 0x13, 0x00 },
71 /* program PLL1_0 multiplier */
72 { 0x18, 0xaf },
73 { 0x19, 0x50 },
74 { 0x1a, 0x02 },
75 { 0x1b, 0xc9 },
76 /* program PLL1_11 multiplier */
77 { 0x1c, 0x00 },
78 { 0x1d, 0x40 },
79 { 0x1e, 0x02 },
80 { 0x1f, 0xc9 },
81 /* output state selection */
82 { 0x15, 0x00 },
83 { 0x14, 0xef },
84 /* switch MUX to PLL1 output */
85 { 0x14, 0x6f },
86 { 0x16, 0x06 },
87 /* set P2DIV divider, P3DIV and input crystal */
88 { 0x17, 0x06 },
89 { 0x01, 0x00 },
90 { 0x05, 0x48 },
91 { 0x02, 0x80 },
92 /* enable and disable PLL */
93 { 0x02, 0xbc },
94 { 0x03, 0x01 },
95 { },
96};
97
98static struct cdce_reg cdce_y1_74250[] = {
99 { 0x13, 0x00 },
100 { 0x18, 0xaf },
101 { 0x19, 0x50 },
102 { 0x1a, 0x02 },
103 { 0x1b, 0xc9 },
104 { 0x1c, 0x00 },
105 { 0x1d, 0x40 },
106 { 0x1e, 0x02 },
107 { 0x1f, 0xc9 },
108 /* output state selection */
109 { 0x15, 0x00 },
110 { 0x14, 0xef },
111 /* switch MUX to PLL1 output */
112 { 0x14, 0x6f },
113 { 0x16, 0x06 },
114 /* set P2DIV divider, P3DIV and input crystal */
115 { 0x17, 0x06 },
116 { 0x01, 0x00 },
117 { 0x05, 0x48 },
118 { 0x02, 0x80 },
119 /* enable and disable PLL */
120 { 0x02, 0xbc },
121 { 0x03, 0x02 },
122 { },
123};
124
125static struct cdce_reg cdce_y1_27000[] = {
126 { 0x13, 0x00 },
127 { 0x18, 0x00 },
128 { 0x19, 0x40 },
129 { 0x1a, 0x02 },
130 { 0x1b, 0x08 },
131 { 0x1c, 0x00 },
132 { 0x1d, 0x40 },
133 { 0x1e, 0x02 },
134 { 0x1f, 0x08 },
135 { 0x15, 0x02 },
136 { 0x14, 0xed },
137 { 0x16, 0x01 },
138 { 0x17, 0x01 },
139 { 0x01, 0x00 },
140 { 0x05, 0x50 },
141 { 0x02, 0xb4 },
142 { 0x03, 0x01 },
143 { },
144};
145
146static struct cdce_freq cdce_y1_freqs[] = {
147 CDCE_FREQ_TABLE_ENTRY(1, 148500),
148 CDCE_FREQ_TABLE_ENTRY(1, 74250),
149 CDCE_FREQ_TABLE_ENTRY(1, 27000),
150};
151
152static struct cdce_reg cdce_y5_13500[] = {
153 { 0x27, 0x08 },
154 { 0x28, 0x00 },
155 { 0x29, 0x40 },
156 { 0x2a, 0x02 },
157 { 0x2b, 0x08 },
158 { 0x24, 0x6f },
159 { },
160};
161
162static struct cdce_reg cdce_y5_16875[] = {
163 { 0x27, 0x08 },
164 { 0x28, 0x9f },
165 { 0x29, 0xb0 },
166 { 0x2a, 0x02 },
167 { 0x2b, 0x89 },
168 { 0x24, 0x6f },
169 { },
170};
171
172static struct cdce_reg cdce_y5_27000[] = {
173 { 0x27, 0x04 },
174 { 0x28, 0x00 },
175 { 0x29, 0x40 },
176 { 0x2a, 0x02 },
177 { 0x2b, 0x08 },
178 { 0x24, 0x6f },
179 { },
180};
181static struct cdce_reg cdce_y5_54000[] = {
182 { 0x27, 0x04 },
183 { 0x28, 0xff },
184 { 0x29, 0x80 },
185 { 0x2a, 0x02 },
186 { 0x2b, 0x07 },
187 { 0x24, 0x6f },
188 { },
189};
190
191static struct cdce_reg cdce_y5_81000[] = {
192 { 0x27, 0x02 },
193 { 0x28, 0xbf },
194 { 0x29, 0xa0 },
195 { 0x2a, 0x03 },
196 { 0x2b, 0x0a },
197 { 0x24, 0x6f },
198 { },
199};
200
201static struct cdce_freq cdce_y5_freqs[] = {
202 CDCE_FREQ_TABLE_ENTRY(5, 13500),
203 CDCE_FREQ_TABLE_ENTRY(5, 16875),
204 CDCE_FREQ_TABLE_ENTRY(5, 27000),
205 CDCE_FREQ_TABLE_ENTRY(5, 54000),
206 CDCE_FREQ_TABLE_ENTRY(5, 81000),
207};
208
209
210static struct cdce_output output_list[] = {
211 [1] = { cdce_y1_freqs, ARRAY_SIZE(cdce_y1_freqs) },
212 [5] = { cdce_y5_freqs, ARRAY_SIZE(cdce_y5_freqs) },
213};
214
215int cdce_set_rate(struct clk *clk, unsigned long rate)
216{
217 int i, ret = 0;
218 struct cdce_freq *freq_table = output_list[clk->lpsc].freq_table;
219 struct cdce_reg *regs = NULL;
220
221 if (!cdce_i2c_client)
222 return -ENODEV;
223
224 if (!freq_table)
225 return -EINVAL;
226
227 for (i = 0; i < output_list[clk->lpsc].size; i++) {
228 if (freq_table[i].frequency == rate / 1000) {
229 regs = freq_table[i].reglist;
230 break;
231 }
232 }
233
234 if (!regs)
235 return -EINVAL;
236
237 mutex_lock(&cdce_mutex);
238 for (i = 0; regs[i].addr; i++) {
239 ret = i2c_smbus_write_byte_data(cdce_i2c_client,
240 regs[i].addr | 0x80, regs[i].val);
241 if (ret)
242 break;
243 }
244 mutex_unlock(&cdce_mutex);
245
246 if (!ret)
247 clk->rate = rate;
248
249 return ret;
250}
251
252static int cdce_probe(struct i2c_client *client,
253 const struct i2c_device_id *id)
254{
255 cdce_i2c_client = client;
256 return 0;
257}
258
259static int cdce_remove(struct i2c_client *client)
260{
261 cdce_i2c_client = NULL;
262 return 0;
263}
264
265static const struct i2c_device_id cdce_id[] = {
266 {"cdce949", 0},
267 {},
268};
269MODULE_DEVICE_TABLE(i2c, cdce_id);
270
271static struct i2c_driver cdce_driver = {
272 .driver = {
273 .owner = THIS_MODULE,
274 .name = "cdce949",
275 },
276 .probe = cdce_probe,
277 .remove = cdce_remove,
278 .id_table = cdce_id,
279};
280
281static int __init cdce_init(void)
282{
283 return i2c_add_driver(&cdce_driver);
284}
285subsys_initcall(cdce_init);
286
287static void __exit cdce_exit(void)
288{
289 i2c_del_driver(&cdce_driver);
290}
291module_exit(cdce_exit);
292
293MODULE_AUTHOR("Texas Instruments");
294MODULE_DESCRIPTION("CDCE949 clock synthesizer driver");
295MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-davinci/include/mach/cdce949.h b/arch/arm/mach-davinci/include/mach/cdce949.h
deleted file mode 100644
index c73331fae341..000000000000
--- a/arch/arm/mach-davinci/include/mach/cdce949.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * TI CDCE949 off-chip clock synthesizer support
3 *
4 * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10#ifndef _MACH_DAVINCI_CDCE949_H
11#define _MACH_DAVINCI_CDCE949_H
12
13#include <linux/clk.h>
14
15#include <mach/clock.h>
16
17int cdce_set_rate(struct clk *clk, unsigned long rate);
18
19#endif
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 5e93a734c858..951b620bfa73 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -31,16 +31,6 @@
31#include <mach/serial.h> 31#include <mach/serial.h>
32#include <mach/cputype.h> 32#include <mach/cputype.h>
33 33
34static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
35 int offset)
36{
37 offset <<= up->regshift;
38
39 WARN_ONCE(!up->membase, "unmapped read: uart[%d]\n", offset);
40
41 return (unsigned int)__raw_readl(up->membase + offset);
42}
43
44static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, 34static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
45 int value) 35 int value)
46{ 36{
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d0837fa8c..2c844393cc4b 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -27,20 +27,16 @@
27#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28#include <asm/memory.h> 28#include <asm/memory.h>
29 29
30#include <mach/map.h>
31
30#include "common.h" 32#include "common.h"
31#include "mfc.h" 33#include "mfc.h"
32#include "regs-pmu.h" 34#include "regs-pmu.h"
33#include "regs-sys.h"
34 35
35void __iomem *pmu_base_addr; 36void __iomem *pmu_base_addr;
36 37
37static struct map_desc exynos4_iodesc[] __initdata = { 38static struct map_desc exynos4_iodesc[] __initdata = {
38 { 39 {
39 .virtual = (unsigned long)S3C_VA_SYS,
40 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
41 .length = SZ_64K,
42 .type = MT_DEVICE,
43 }, {
44 .virtual = (unsigned long)S5P_VA_SROMC, 40 .virtual = (unsigned long)S5P_VA_SROMC,
45 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), 41 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
46 .length = SZ_4K, 42 .length = SZ_4K,
@@ -70,11 +66,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
70 66
71static struct map_desc exynos5_iodesc[] __initdata = { 67static struct map_desc exynos5_iodesc[] __initdata = {
72 { 68 {
73 .virtual = (unsigned long)S3C_VA_SYS,
74 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
75 .length = SZ_64K,
76 .type = MT_DEVICE,
77 }, {
78 .virtual = (unsigned long)S5P_VA_SROMC, 69 .virtual = (unsigned long)S5P_VA_SROMC,
79 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), 70 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
80 .length = SZ_4K, 71 .length = SZ_4K,
@@ -213,32 +204,6 @@ static void __init exynos_init_irq(void)
213 204
214static void __init exynos_dt_machine_init(void) 205static void __init exynos_dt_machine_init(void)
215{ 206{
216 struct device_node *i2c_np;
217 const char *i2c_compat = "samsung,s3c2440-i2c";
218 unsigned int tmp;
219 int id;
220
221 /*
222 * Exynos5's legacy i2c controller and new high speed i2c
223 * controller have muxed interrupt sources. By default the
224 * interrupts for 4-channel HS-I2C controller are enabled.
225 * If node for first four channels of legacy i2c controller
226 * are available then re-configure the interrupts via the
227 * system register.
228 */
229 if (soc_is_exynos5()) {
230 for_each_compatible_node(i2c_np, NULL, i2c_compat) {
231 if (of_device_is_available(i2c_np)) {
232 id = of_alias_get_id(i2c_np, "i2c");
233 if (id < 4) {
234 tmp = readl(EXYNOS5_SYS_I2C_CFG);
235 writel(tmp & ~(0x1 << id),
236 EXYNOS5_SYS_I2C_CFG);
237 }
238 }
239 }
240 }
241
242 /* 207 /*
243 * This is called from smp_prepare_cpus if we've built for SMP, but 208 * This is called from smp_prepare_cpus if we've built for SMP, but
244 * we still need to set it up for PM and firmware ops if not. 209 * we still need to set it up for PM and firmware ops if not.
diff --git a/arch/arm/mach-exynos/include/mach/dma.h b/arch/arm/mach-exynos/include/mach/dma.h
deleted file mode 100644
index 201842a3769e..000000000000
--- a/arch/arm/mach-exynos/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common DMA API driver for PL330 */
24#include <plat/dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 1ad3f496ef56..de3ae59e1cfb 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -24,9 +24,6 @@
24 24
25#define EXYNOS_PA_CHIPID 0x10000000 25#define EXYNOS_PA_CHIPID 0x10000000
26 26
27#define EXYNOS4_PA_SYSCON 0x10010000
28#define EXYNOS5_PA_SYSCON 0x10050100
29
30#define EXYNOS4_PA_CMU 0x10030000 27#define EXYNOS4_PA_CMU 0x10030000
31#define EXYNOS5_PA_CMU 0x10010000 28#define EXYNOS5_PA_CMU 0x10010000
32 29
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 86f3ecd88f78..dfc8594e5b1f 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -23,12 +23,13 @@
23#include <asm/smp_scu.h> 23#include <asm/smp_scu.h>
24#include <asm/suspend.h> 24#include <asm/suspend.h>
25 25
26#include <mach/map.h>
27
26#include <plat/pm-common.h> 28#include <plat/pm-common.h>
27 29
28#include "common.h" 30#include "common.h"
29#include "exynos-pmu.h" 31#include "exynos-pmu.h"
30#include "regs-pmu.h" 32#include "regs-pmu.h"
31#include "regs-sys.h"
32 33
33static inline void __iomem *exynos_boot_vector_addr(void) 34static inline void __iomem *exynos_boot_vector_addr(void)
34{ 35{
diff --git a/arch/arm/mach-exynos/regs-sys.h b/arch/arm/mach-exynos/regs-sys.h
deleted file mode 100644
index 84332b0dd7a6..000000000000
--- a/arch/arm/mach-exynos/regs-sys.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - system register definition
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_REGS_SYS_H
13#define __ASM_ARCH_REGS_SYS_H __FILE__
14
15#include <mach/map.h>
16
17#define S5P_SYSREG(x) (S3C_VA_SYS + (x))
18
19/* For EXYNOS5 */
20#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234)
21
22#endif /* __ASM_ARCH_REGS_SYS_H */
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index f8e7dcd17055..342797b9bf3b 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -34,7 +34,6 @@
34 34
35#include "common.h" 35#include "common.h"
36#include "regs-pmu.h" 36#include "regs-pmu.h"
37#include "regs-sys.h"
38#include "exynos-pmu.h" 37#include "exynos-pmu.h"
39 38
40#define S5P_CHECK_SLEEP 0x00000BAD 39#define S5P_CHECK_SLEEP 0x00000BAD
@@ -53,10 +52,6 @@ struct exynos_wkup_irq {
53 u32 mask; 52 u32 mask;
54}; 53};
55 54
56static struct sleep_save exynos5_sys_save[] = {
57 SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
58};
59
60static struct sleep_save exynos_core_save[] = { 55static struct sleep_save exynos_core_save[] = {
61 /* SROM side */ 56 /* SROM side */
62 SAVE_ITEM(S5P_SROM_BW), 57 SAVE_ITEM(S5P_SROM_BW),
@@ -497,8 +492,6 @@ static const struct exynos_pm_data exynos5250_pm_data = {
497 .wkup_irq = exynos5250_wkup_irq, 492 .wkup_irq = exynos5250_wkup_irq,
498 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), 493 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
499 .release_ret_regs = exynos_release_ret_regs, 494 .release_ret_regs = exynos_release_ret_regs,
500 .extra_save = exynos5_sys_save,
501 .num_extra_save = ARRAY_SIZE(exynos5_sys_save),
502 .pm_suspend = exynos_pm_suspend, 495 .pm_suspend = exynos_pm_suspend,
503 .pm_resume = exynos_pm_resume, 496 .pm_resume = exynos_pm_resume,
504 .pm_prepare = exynos_pm_prepare, 497 .pm_prepare = exynos_pm_prepare,
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 122ef67939a2..a8a533df24e1 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -64,11 +64,6 @@ u32 omap_irq_flags;
64static unsigned int irq_bank_count; 64static unsigned int irq_bank_count;
65static struct omap_irq_bank *irq_banks; 65static struct omap_irq_bank *irq_banks;
66 66
67static inline unsigned int irq_bank_readl(int bank, int offset)
68{
69 return omap_readl(irq_banks[bank].base_reg + offset);
70}
71
72static inline void irq_bank_writel(unsigned long value, int bank, int offset) 67static inline void irq_bank_writel(unsigned long value, int bank, int offset)
73{ 68{
74 omap_writel(value, irq_banks[bank].base_reg + offset); 69 omap_writel(value, irq_banks[bank].base_reg + offset);
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 107e7ab3edba..36bf174b3fac 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -91,11 +91,6 @@ static inline void omap_32k_timer_write(int val, int reg)
91 omap_writew(val, OMAP1_32K_TIMER_BASE + reg); 91 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
92} 92}
93 93
94static inline unsigned long omap_32k_timer_read(int reg)
95{
96 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
97}
98
99static inline void omap_32k_timer_start(unsigned long load_val) 94static inline void omap_32k_timer_start(unsigned long load_val)
100{ 95{
101 if (!load_val) 96 if (!load_val)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 6ab656cc4f16..2b8e47788062 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -217,12 +217,6 @@ config MACH_OMAP3517EVM
217 bool "OMAP3517/ AM3517 EVM board" 217 bool "OMAP3517/ AM3517 EVM board"
218 depends on ARCH_OMAP3 218 depends on ARCH_OMAP3
219 default y 219 default y
220 select OMAP_PACKAGE_CBB
221
222config MACH_CRANEBOARD
223 bool "AM3517/05 CRANE board"
224 depends on ARCH_OMAP3
225 select OMAP_PACKAGE_CBB
226 220
227config MACH_OMAP3_PANDORA 221config MACH_OMAP3_PANDORA
228 bool "OMAP3 Pandora" 222 bool "OMAP3 Pandora"
@@ -263,12 +257,6 @@ config MACH_CM_T35
263 select MACH_CM_T3730 257 select MACH_CM_T3730
264 select OMAP_PACKAGE_CUS 258 select OMAP_PACKAGE_CUS
265 259
266config MACH_CM_T3517
267 bool "CompuLab CM-T3517 module"
268 depends on ARCH_OMAP3
269 default y
270 select OMAP_PACKAGE_CBB
271
272config MACH_CM_T3730 260config MACH_CM_T3730
273 bool 261 bool
274 262
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 3a6463f88ea2..fb78744f546b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -182,7 +182,6 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
182obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 182obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
183obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o 183obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
184obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o 184obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
185obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
186obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o 185obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
187obj-$(CONFIG_SOC_OMAP2430) += clock2430.o 186obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
188obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o 187obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
@@ -251,13 +250,8 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
251obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o 250obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
252obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o 251obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o
253obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o 252obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
254obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
255obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o 253obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o
256 254
257obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
258
259obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
260
261obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o 255obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o
262 256
263# Platform specific device init code 257# Platform specific device init code
@@ -287,7 +281,4 @@ ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
287obj-y += hwspinlock.o 281obj-y += hwspinlock.o
288endif 282endif
289 283
290emac-$(CONFIG_TI_DAVINCI_EMAC) := am35xx-emac.o
291obj-y += $(emac-m) $(emac-y)
292
293obj-y += common-board-devices.o twl-common.o dss-common.o 284obj-y += common-board-devices.o twl-common.o dss-common.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
deleted file mode 100644
index 6a6935caac1e..000000000000
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3 *
4 * Based on mach-omap2/board-am3517evm.c
5 * Copyright (C) 2009 Texas Instruments Incorporated
6 * Author: Ranjith Lohithakshan <ranjithl@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
13 * whether express or implied; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 */
17
18#include <linux/err.h>
19#include <linux/davinci_emac.h>
20#include "omap_device.h"
21#include "am35xx.h"
22#include "control.h"
23#include "am35xx-emac.h"
24
25static void am35xx_enable_emac_int(void)
26{
27 u32 v;
28
29 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
30 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
31 AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
32 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
33 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
34}
35
36static void am35xx_disable_emac_int(void)
37{
38 u32 v;
39
40 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
41 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
42 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
43 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
44}
45
46static struct emac_platform_data am35xx_emac_pdata = {
47 .ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET,
48 .ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET,
49 .ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET,
50 .ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE,
51 .hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR,
52 .version = EMAC_VERSION_2,
53 .interrupt_enable = am35xx_enable_emac_int,
54 .interrupt_disable = am35xx_disable_emac_int,
55};
56
57static struct mdio_platform_data am35xx_mdio_pdata;
58
59static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
60 void *pdata, int pdata_len)
61{
62 struct platform_device *pdev;
63
64 pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len);
65 if (IS_ERR(pdev)) {
66 WARN(1, "Can't build omap_device for %s:%s.\n",
67 oh->class->name, oh->name);
68 return PTR_ERR(pdev);
69 }
70
71 return 0;
72}
73
74void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
75{
76 struct omap_hwmod *oh;
77 u32 v;
78 int ret;
79
80 oh = omap_hwmod_lookup("davinci_mdio");
81 if (!oh) {
82 pr_err("Could not find davinci_mdio hwmod\n");
83 return;
84 }
85
86 am35xx_mdio_pdata.bus_freq = mdio_bus_freq;
87
88 ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata,
89 sizeof(am35xx_mdio_pdata));
90 if (ret) {
91 pr_err("Could not build davinci_mdio hwmod device\n");
92 return;
93 }
94
95 oh = omap_hwmod_lookup("davinci_emac");
96 if (!oh) {
97 pr_err("Could not find davinci_emac hwmod\n");
98 return;
99 }
100
101 am35xx_emac_pdata.rmii_en = rmii_en;
102
103 ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata,
104 sizeof(am35xx_emac_pdata));
105 if (ret) {
106 pr_err("Could not build davinci_emac hwmod device\n");
107 return;
108 }
109
110 v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
111 v &= ~AM35XX_CPGMACSS_SW_RST;
112 omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
113 omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
114}
diff --git a/arch/arm/mach-omap2/am35xx-emac.h b/arch/arm/mach-omap2/am35xx-emac.h
deleted file mode 100644
index 15c6f9ce59a2..000000000000
--- a/arch/arm/mach-omap2/am35xx-emac.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#define AM35XX_DEFAULT_MDIO_FREQUENCY 1000000
10
11#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
12void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en);
13#else
14static inline void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) {}
15#endif
diff --git a/arch/arm/mach-omap2/am35xx.h b/arch/arm/mach-omap2/am35xx.h
deleted file mode 100644
index 95594495fcf6..000000000000
--- a/arch/arm/mach-omap2/am35xx.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*:
2 * Address mappings and base address for AM35XX specific interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2009 Texas Instruments
6 *
7 * Author: Sriramakrishnan <srk@ti.com>
8 * Vaibhav Hiremath <hvaibhav@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#ifndef __ASM_ARCH_AM35XX_H
15#define __ASM_ARCH_AM35XX_H
16
17/*
18 * Base addresses
19 * Note: OMAP3430 IVA2 memory space is being used for AM35xx IPSS modules
20 */
21#define AM35XX_IPSS_EMAC_BASE 0x5C000000
22#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
23#define AM35XX_IPSS_HECC_BASE 0x5C050000
24#define AM35XX_IPSS_VPFE_BASE 0x5C060000
25
26
27/* HECC module specifc offset definitions */
28#define AM35XX_HECC_SCC_HECC_OFFSET (0x0)
29#define AM35XX_HECC_SCC_RAM_OFFSET (0x3000)
30#define AM35XX_HECC_RAM_OFFSET (0x3000)
31#define AM35XX_HECC_MBOX_OFFSET (0x2000)
32#define AM35XX_HECC_INT_LINE (0x0)
33#define AM35XX_HECC_VERSION (0x1)
34
35#define AM35XX_EMAC_CNTRL_OFFSET (0x10000)
36#define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0)
37#define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000)
38#define AM35XX_EMAC_MDIO_OFFSET (0x30000)
39#define AM35XX_IPSS_MDIO_BASE (AM35XX_IPSS_EMAC_BASE + \
40 AM35XX_EMAC_MDIO_OFFSET)
41#define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000)
42#define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \
43 AM3517_EMAC_CNTRL_RAM_OFFSET)
44#define AM35XX_EMAC_HW_RAM_ADDR (0x01E20000)
45
46#endif /* __ASM_ARCH_AM35XX_H */
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
deleted file mode 100644
index 8168ddabaeda..000000000000
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ /dev/null
@@ -1,150 +0,0 @@
1/*
2 * Support for AM3517/05 Craneboard
3 * http://www.mistralsolutions.com/products/craneboard.php
4 *
5 * Copyright (C) 2010 Mistral Solutions Pvt Ltd. <www.mistralsolutions.com>
6 * Author: R.Srinath <srinath@mistralsolutions.com>
7 *
8 * Based on mach-omap2/board-am3517evm.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation version 2.
13 *
14 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
15 * whether express or implied; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/gpio.h>
23#include <linux/mfd/tps65910.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h>
27#include <linux/omap-gpmc.h>
28
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32
33#include "common.h"
34#include "common-board-devices.h"
35#include "board-flash.h"
36
37#include "am35xx-emac.h"
38#include "mux.h"
39#include "control.h"
40
41#define GPIO_USB_POWER 35
42#define GPIO_USB_NRESET 38
43
44#ifdef CONFIG_OMAP_MUX
45static struct omap_board_mux board_mux[] __initdata = {
46 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
47 { .reg_offset = OMAP_MUX_TERMINATOR },
48};
49#endif
50
51static struct usbhs_phy_data phy_data[] __initdata = {
52 {
53 .port = 1,
54 .reset_gpio = GPIO_USB_NRESET,
55 .vcc_gpio = GPIO_USB_POWER,
56 .vcc_polarity = 1,
57 },
58};
59
60static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
61 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
62};
63
64static struct mtd_partition crane_nand_partitions[] = {
65 {
66 .name = "X-Loader",
67 .offset = 0,
68 .size = 4 * NAND_BLOCK_SIZE,
69 .mask_flags = MTD_WRITEABLE,
70 },
71 {
72 .name = "U-Boot",
73 .offset = MTDPART_OFS_APPEND,
74 .size = 14 * NAND_BLOCK_SIZE,
75 .mask_flags = MTD_WRITEABLE,
76 },
77 {
78 .name = "U-Boot Env",
79 .offset = MTDPART_OFS_APPEND,
80 .size = 2 * NAND_BLOCK_SIZE,
81 },
82 {
83 .name = "Kernel",
84 .offset = MTDPART_OFS_APPEND,
85 .size = 40 * NAND_BLOCK_SIZE,
86 },
87 {
88 .name = "File System",
89 .offset = MTDPART_OFS_APPEND,
90 .size = MTDPART_SIZ_FULL,
91 },
92};
93
94static struct tps65910_board tps65910_pdata = {
95 .irq = 7 + OMAP_INTC_START,
96 .en_ck32k_xtal = true,
97};
98
99static struct i2c_board_info __initdata tps65910_board_info[] = {
100 {
101 I2C_BOARD_INFO("tps65910", 0x2d),
102 .platform_data = &tps65910_pdata,
103 },
104};
105
106static void __init am3517_crane_i2c_init(void)
107{
108 omap_register_i2c_bus(1, 2600, tps65910_board_info,
109 ARRAY_SIZE(tps65910_board_info));
110}
111
112static void __init am3517_crane_init(void)
113{
114 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
115 omap_serial_init();
116 omap_sdrc_init(NULL, NULL);
117 board_nand_init(crane_nand_partitions,
118 ARRAY_SIZE(crane_nand_partitions), 0,
119 NAND_BUSWIDTH_16, NULL);
120 am3517_crane_i2c_init();
121
122 /* Configure GPIO for EHCI port */
123 if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
124 pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
125 GPIO_USB_NRESET);
126 return;
127 }
128
129 if (omap_mux_init_gpio(GPIO_USB_POWER, OMAP_PIN_OUTPUT)) {
130 pr_err("Can not configure mux for GPIO_USB_POWER %d\n",
131 GPIO_USB_POWER);
132 return;
133 }
134
135 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
136 usbhs_init(&usbhs_bdata);
137 am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
138}
139
140MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
141 .atag_offset = 0x100,
142 .reserve = omap_reserve,
143 .map_io = omap3_map_io,
144 .init_early = am35xx_init_early,
145 .init_irq = omap3_init_irq,
146 .init_machine = am3517_crane_init,
147 .init_late = am35xx_init_late,
148 .init_time = omap3_sync32k_timer_init,
149 .restart = omap3xxx_restart,
150MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
deleted file mode 100644
index 1c091b3fa312..000000000000
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ /dev/null
@@ -1,373 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-am3517evm.c
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated
5 * Author: Ranjith Lohithakshan <ranjithl@ti.com>
6 *
7 * Based on mach-omap2/board-omap3evm.c
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
14 * whether express or implied; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22#include <linux/platform_device.h>
23#include <linux/gpio.h>
24#include <linux/platform_data/pca953x.h>
25#include <linux/can/platform/ti_hecc.h>
26#include <linux/davinci_emac.h>
27#include <linux/mmc/host.h>
28#include <linux/usb/musb.h>
29#include <linux/platform_data/gpio-omap.h>
30
31#include "am35xx.h"
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35
36#include "common.h"
37#include <video/omapdss.h>
38#include <video/omap-panel-data.h>
39
40#include "am35xx-emac.h"
41#include "mux.h"
42#include "control.h"
43#include "hsmmc.h"
44
45#define LCD_PANEL_PWR 176
46#define LCD_PANEL_BKLIGHT_PWR 182
47#define LCD_PANEL_PWM 181
48
49static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = {
50 {
51 I2C_BOARD_INFO("s35390a", 0x30),
52 },
53};
54
55/*
56 * RTC - S35390A
57 */
58#define GPIO_RTCS35390A_IRQ 55
59
60static void __init am3517_evm_rtc_init(void)
61{
62 int r;
63
64 omap_mux_init_gpio(GPIO_RTCS35390A_IRQ, OMAP_PIN_INPUT_PULLUP);
65
66 r = gpio_request_one(GPIO_RTCS35390A_IRQ, GPIOF_IN, "rtcs35390a-irq");
67 if (r < 0) {
68 printk(KERN_WARNING "failed to request GPIO#%d\n",
69 GPIO_RTCS35390A_IRQ);
70 return;
71 }
72
73 am3517evm_i2c1_boardinfo[0].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ);
74}
75
76/*
77 * I2C GPIO Expander - TCA6416
78 */
79
80/* Mounted on Base-Board */
81static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = {
82 .gpio_base = OMAP_MAX_GPIO_LINES,
83};
84static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = {
85 {
86 I2C_BOARD_INFO("tlv320aic23", 0x1A),
87 },
88 {
89 I2C_BOARD_INFO("tca6416", 0x21),
90 .platform_data = &am3517evm_gpio_expander_info_0,
91 },
92};
93
94/* Mounted on UI Card */
95static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_1 = {
96 .gpio_base = OMAP_MAX_GPIO_LINES + 16,
97};
98static struct pca953x_platform_data am3517evm_ui_gpio_expander_info_2 = {
99 .gpio_base = OMAP_MAX_GPIO_LINES + 32,
100};
101static struct i2c_board_info __initdata am3517evm_i2c3_boardinfo[] = {
102 {
103 I2C_BOARD_INFO("tca6416", 0x20),
104 .platform_data = &am3517evm_ui_gpio_expander_info_1,
105 },
106 {
107 I2C_BOARD_INFO("tca6416", 0x21),
108 .platform_data = &am3517evm_ui_gpio_expander_info_2,
109 },
110};
111
112static int __init am3517_evm_i2c_init(void)
113{
114 omap_register_i2c_bus(1, 400, NULL, 0);
115 omap_register_i2c_bus(2, 400, am3517evm_i2c2_boardinfo,
116 ARRAY_SIZE(am3517evm_i2c2_boardinfo));
117 omap_register_i2c_bus(3, 400, am3517evm_i2c3_boardinfo,
118 ARRAY_SIZE(am3517evm_i2c3_boardinfo));
119
120 return 0;
121}
122
123static const struct display_timing am3517_evm_lcd_videomode = {
124 .pixelclock = { 0, 9000000, 0 },
125
126 .hactive = { 0, 480, 0 },
127 .hfront_porch = { 0, 3, 0 },
128 .hback_porch = { 0, 2, 0 },
129 .hsync_len = { 0, 42, 0 },
130
131 .vactive = { 0, 272, 0 },
132 .vfront_porch = { 0, 3, 0 },
133 .vback_porch = { 0, 2, 0 },
134 .vsync_len = { 0, 11, 0 },
135
136 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
137 DISPLAY_FLAGS_DE_LOW | DISPLAY_FLAGS_PIXDATA_POSEDGE,
138};
139
140static struct panel_dpi_platform_data am3517_evm_lcd_pdata = {
141 .name = "lcd",
142 .source = "dpi.0",
143
144 .data_lines = 16,
145
146 .display_timing = &am3517_evm_lcd_videomode,
147
148 .enable_gpio = LCD_PANEL_PWR,
149 .backlight_gpio = LCD_PANEL_BKLIGHT_PWR,
150};
151
152static struct platform_device am3517_evm_lcd_device = {
153 .name = "panel-dpi",
154 .id = 0,
155 .dev.platform_data = &am3517_evm_lcd_pdata,
156};
157
158static struct connector_dvi_platform_data am3517_evm_dvi_connector_pdata = {
159 .name = "dvi",
160 .source = "tfp410.0",
161 .i2c_bus_num = -1,
162};
163
164static struct platform_device am3517_evm_dvi_connector_device = {
165 .name = "connector-dvi",
166 .id = 0,
167 .dev.platform_data = &am3517_evm_dvi_connector_pdata,
168};
169
170static struct encoder_tfp410_platform_data am3517_evm_tfp410_pdata = {
171 .name = "tfp410.0",
172 .source = "dpi.0",
173 .data_lines = 24,
174 .power_down_gpio = -1,
175};
176
177static struct platform_device am3517_evm_tfp410_device = {
178 .name = "tfp410",
179 .id = 0,
180 .dev.platform_data = &am3517_evm_tfp410_pdata,
181};
182
183static struct connector_atv_platform_data am3517_evm_tv_pdata = {
184 .name = "tv",
185 .source = "venc.0",
186 .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
187 .invert_polarity = false,
188};
189
190static struct platform_device am3517_evm_tv_connector_device = {
191 .name = "connector-analog-tv",
192 .id = 0,
193 .dev.platform_data = &am3517_evm_tv_pdata,
194};
195
196static struct omap_dss_board_info am3517_evm_dss_data = {
197 .default_display_name = "lcd",
198};
199
200static void __init am3517_evm_display_init(void)
201{
202 gpio_request_one(LCD_PANEL_PWM, GPIOF_OUT_INIT_HIGH, "lcd panel pwm");
203
204 omap_display_init(&am3517_evm_dss_data);
205
206 platform_device_register(&am3517_evm_tfp410_device);
207 platform_device_register(&am3517_evm_dvi_connector_device);
208 platform_device_register(&am3517_evm_lcd_device);
209 platform_device_register(&am3517_evm_tv_connector_device);
210}
211
212/*
213 * Board initialization
214 */
215
216static struct omap_musb_board_data musb_board_data = {
217 .interface_type = MUSB_INTERFACE_ULPI,
218 .mode = MUSB_OTG,
219 .power = 500,
220 .set_phy_power = am35x_musb_phy_power,
221 .clear_irq = am35x_musb_clear_irq,
222 .set_mode = am35x_set_mode,
223 .reset = am35x_musb_reset,
224};
225
226static __init void am3517_evm_musb_init(void)
227{
228 u32 devconf2;
229
230 /*
231 * Set up USB clock/mode in the DEVCONF2 register.
232 */
233 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
234
235 /* USB2.0 PHY reference clock is 13 MHz */
236 devconf2 &= ~(CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE);
237 devconf2 |= CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | CONF2_VBDTCTEN
238 | CONF2_DATPOL;
239
240 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
241
242 usb_musb_init(&musb_board_data);
243}
244
245static __init void am3517_evm_mcbsp1_init(void)
246{
247 u32 devconf0;
248
249 /* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
250 devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
251 devconf0 |= OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
252 omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
253}
254
255static struct usbhs_phy_data phy_data[] __initdata = {
256 {
257 .port = 1,
258 .reset_gpio = 57,
259 .vcc_gpio = -EINVAL,
260 },
261};
262
263static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
264 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
265 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
266};
267
268#ifdef CONFIG_OMAP_MUX
269static struct omap_board_mux board_mux[] __initdata = {
270 /* USB OTG DRVVBUS offset = 0x212 */
271 OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
272 { .reg_offset = OMAP_MUX_TERMINATOR },
273};
274#endif
275
276
277static struct resource am3517_hecc_resources[] = {
278 {
279 .start = AM35XX_IPSS_HECC_BASE,
280 .end = AM35XX_IPSS_HECC_BASE + 0x3FFF,
281 .flags = IORESOURCE_MEM,
282 },
283 {
284 .start = 24 + OMAP_INTC_START,
285 .flags = IORESOURCE_IRQ,
286 },
287};
288
289static struct platform_device am3517_hecc_device = {
290 .name = "ti_hecc",
291 .id = -1,
292 .num_resources = ARRAY_SIZE(am3517_hecc_resources),
293 .resource = am3517_hecc_resources,
294};
295
296static struct ti_hecc_platform_data am3517_evm_hecc_pdata = {
297 .scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET,
298 .scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET,
299 .hecc_ram_offset = AM35XX_HECC_RAM_OFFSET,
300 .mbx_offset = AM35XX_HECC_MBOX_OFFSET,
301 .int_line = AM35XX_HECC_INT_LINE,
302 .version = AM35XX_HECC_VERSION,
303};
304
305static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
306{
307 am3517_hecc_device.dev.platform_data = pdata;
308 platform_device_register(&am3517_hecc_device);
309}
310
311static struct omap2_hsmmc_info mmc[] = {
312 {
313 .mmc = 1,
314 .caps = MMC_CAP_4_BIT_DATA,
315 .gpio_cd = 127,
316 .gpio_wp = 126,
317 },
318 {
319 .mmc = 2,
320 .caps = MMC_CAP_4_BIT_DATA,
321 .gpio_cd = 128,
322 .gpio_wp = 129,
323 },
324 {} /* Terminator */
325};
326
327static void __init am3517_evm_init(void)
328{
329 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
330
331 am3517_evm_i2c_init();
332
333 am3517_evm_display_init();
334
335 omap_serial_init();
336 omap_sdrc_init(NULL, NULL);
337
338 /* Configure GPIO for EHCI port */
339 omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
340
341 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
342 usbhs_init(&usbhs_bdata);
343 am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
344
345 /* RTC - S35390A */
346 am3517_evm_rtc_init();
347
348 i2c_register_board_info(1, am3517evm_i2c1_boardinfo,
349 ARRAY_SIZE(am3517evm_i2c1_boardinfo));
350 /*Ethernet*/
351 am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
352
353 /* MUSB */
354 am3517_evm_musb_init();
355
356 /* McBSP1 */
357 am3517_evm_mcbsp1_init();
358
359 /* MMC init function */
360 omap_hsmmc_init(mmc);
361}
362
363MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
364 .atag_offset = 0x100,
365 .reserve = omap_reserve,
366 .map_io = omap3_map_io,
367 .init_early = am35xx_init_early,
368 .init_irq = omap3_init_irq,
369 .init_machine = am3517_evm_init,
370 .init_late = am35xx_init_late,
371 .init_time = omap3_sync32k_timer_init,
372 .restart = omap3xxx_restart,
373MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
deleted file mode 100644
index 794756df8529..000000000000
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ /dev/null
@@ -1,335 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-cm-t3517.c
3 *
4 * Support for the CompuLab CM-T3517 modules
5 *
6 * Copyright (C) 2010 CompuLab, Ltd.
7 * Author: Igor Grinberg <grinberg@compulab.co.il>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/platform_device.h>
28#include <linux/delay.h>
29#include <linux/gpio.h>
30#include <linux/leds.h>
31#include <linux/omap-gpmc.h>
32#include <linux/rtc-v3020.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/nand.h>
35#include <linux/mtd/partitions.h>
36#include <linux/mmc/host.h>
37#include <linux/can/platform/ti_hecc.h>
38
39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42
43#include "common.h"
44#include <linux/platform_data/mtd-nand-omap2.h>
45
46#include "am35xx.h"
47
48#include "mux.h"
49#include "control.h"
50#include "hsmmc.h"
51#include "common-board-devices.h"
52#include "am35xx-emac.h"
53
54#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
55static struct gpio_led cm_t3517_leds[] = {
56 [0] = {
57 .gpio = 186,
58 .name = "cm-t3517:green",
59 .default_trigger = "heartbeat",
60 .active_low = 0,
61 },
62};
63
64static struct gpio_led_platform_data cm_t3517_led_pdata = {
65 .num_leds = ARRAY_SIZE(cm_t3517_leds),
66 .leds = cm_t3517_leds,
67};
68
69static struct platform_device cm_t3517_led_device = {
70 .name = "leds-gpio",
71 .id = -1,
72 .dev = {
73 .platform_data = &cm_t3517_led_pdata,
74 },
75};
76
77static void __init cm_t3517_init_leds(void)
78{
79 platform_device_register(&cm_t3517_led_device);
80}
81#else
82static inline void cm_t3517_init_leds(void) {}
83#endif
84
85#if defined(CONFIG_CAN_TI_HECC) || defined(CONFIG_CAN_TI_HECC_MODULE)
86static struct resource cm_t3517_hecc_resources[] = {
87 {
88 .start = AM35XX_IPSS_HECC_BASE,
89 .end = AM35XX_IPSS_HECC_BASE + SZ_16K - 1,
90 .flags = IORESOURCE_MEM,
91 },
92 {
93 .start = 24 + OMAP_INTC_START,
94 .flags = IORESOURCE_IRQ,
95 },
96};
97
98static struct ti_hecc_platform_data cm_t3517_hecc_pdata = {
99 .scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET,
100 .scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET,
101 .hecc_ram_offset = AM35XX_HECC_RAM_OFFSET,
102 .mbx_offset = AM35XX_HECC_MBOX_OFFSET,
103 .int_line = AM35XX_HECC_INT_LINE,
104 .version = AM35XX_HECC_VERSION,
105};
106
107static struct platform_device cm_t3517_hecc_device = {
108 .name = "ti_hecc",
109 .id = 1,
110 .num_resources = ARRAY_SIZE(cm_t3517_hecc_resources),
111 .resource = cm_t3517_hecc_resources,
112 .dev = {
113 .platform_data = &cm_t3517_hecc_pdata,
114 },
115};
116
117static void cm_t3517_init_hecc(void)
118{
119 platform_device_register(&cm_t3517_hecc_device);
120}
121#else
122static inline void cm_t3517_init_hecc(void) {}
123#endif
124
125#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
126static struct omap2_hsmmc_info cm_t3517_mmc[] = {
127 {
128 .mmc = 1,
129 .caps = MMC_CAP_4_BIT_DATA,
130 .gpio_cd = 144,
131 .gpio_wp = 59,
132 },
133 {
134 .mmc = 2,
135 .caps = MMC_CAP_4_BIT_DATA,
136 .gpio_cd = -EINVAL,
137 .gpio_wp = -EINVAL,
138 },
139 {} /* Terminator */
140};
141#else
142#define cm_t3517_mmc NULL
143#endif
144
145#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
146#define RTC_IO_GPIO (153)
147#define RTC_WR_GPIO (154)
148#define RTC_RD_GPIO (53)
149#define RTC_CS_GPIO (163)
150#define RTC_CS_EN_GPIO (160)
151
152struct v3020_platform_data cm_t3517_v3020_pdata = {
153 .use_gpio = 1,
154 .gpio_cs = RTC_CS_GPIO,
155 .gpio_wr = RTC_WR_GPIO,
156 .gpio_rd = RTC_RD_GPIO,
157 .gpio_io = RTC_IO_GPIO,
158};
159
160static struct platform_device cm_t3517_rtc_device = {
161 .name = "v3020",
162 .id = -1,
163 .dev = {
164 .platform_data = &cm_t3517_v3020_pdata,
165 }
166};
167
168static void __init cm_t3517_init_rtc(void)
169{
170 int err;
171
172 err = gpio_request_one(RTC_CS_EN_GPIO, GPIOF_OUT_INIT_HIGH,
173 "rtc cs en");
174 if (err) {
175 pr_err("CM-T3517: rtc cs en gpio request failed: %d\n", err);
176 return;
177 }
178
179 platform_device_register(&cm_t3517_rtc_device);
180}
181#else
182static inline void cm_t3517_init_rtc(void) {}
183#endif
184
185#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
186#define HSUSB1_RESET_GPIO (146)
187#define HSUSB2_RESET_GPIO (147)
188#define USB_HUB_RESET_GPIO (152)
189
190static struct usbhs_phy_data phy_data[] __initdata = {
191 {
192 .port = 1,
193 .reset_gpio = HSUSB1_RESET_GPIO,
194 .vcc_gpio = -EINVAL,
195 },
196 {
197 .port = 2,
198 .reset_gpio = HSUSB2_RESET_GPIO,
199 .vcc_gpio = -EINVAL,
200 },
201};
202
203static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = {
204 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
205 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
206};
207
208static int __init cm_t3517_init_usbh(void)
209{
210 int err;
211
212 err = gpio_request_one(USB_HUB_RESET_GPIO, GPIOF_OUT_INIT_LOW,
213 "usb hub rst");
214 if (err) {
215 pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err);
216 } else {
217 udelay(10);
218 gpio_set_value(USB_HUB_RESET_GPIO, 1);
219 msleep(1);
220 }
221
222 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
223 usbhs_init(&cm_t3517_ehci_pdata);
224
225 return 0;
226}
227#else
228static inline int cm_t3517_init_usbh(void)
229{
230 return 0;
231}
232#endif
233
234#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
235static struct mtd_partition cm_t3517_nand_partitions[] = {
236 {
237 .name = "xloader",
238 .offset = 0, /* Offset = 0x00000 */
239 .size = 4 * NAND_BLOCK_SIZE,
240 .mask_flags = MTD_WRITEABLE
241 },
242 {
243 .name = "uboot",
244 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
245 .size = 15 * NAND_BLOCK_SIZE,
246 },
247 {
248 .name = "uboot environment",
249 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
250 .size = 2 * NAND_BLOCK_SIZE,
251 },
252 {
253 .name = "linux",
254 .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */
255 .size = 32 * NAND_BLOCK_SIZE,
256 },
257 {
258 .name = "rootfs",
259 .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */
260 .size = MTDPART_SIZ_FULL,
261 },
262};
263
264static struct omap_nand_platform_data cm_t3517_nand_data = {
265 .parts = cm_t3517_nand_partitions,
266 .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions),
267 .cs = 0,
268};
269
270static void __init cm_t3517_init_nand(void)
271{
272 if (gpmc_nand_init(&cm_t3517_nand_data, NULL) < 0)
273 pr_err("CM-T3517: NAND initialization failed\n");
274}
275#else
276static inline void cm_t3517_init_nand(void) {}
277#endif
278
279#ifdef CONFIG_OMAP_MUX
280static struct omap_board_mux board_mux[] __initdata = {
281 /* GPIO186 - Green LED */
282 OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
283
284 /* RTC GPIOs: */
285 /* IO - GPIO153 */
286 OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
287 /* WR# - GPIO154 */
288 OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
289 /* RD# - GPIO53 */
290 OMAP3_MUX(GPMC_NCS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
291 /* CS# - GPIO163 */
292 OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
293 /* CS EN - GPIO160 */
294 OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
295
296 /* HSUSB1 RESET */
297 OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
298 /* HSUSB2 RESET */
299 OMAP3_MUX(UART2_RX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
300 /* CM-T3517 USB HUB nRESET */
301 OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
302
303 /* CD - GPIO144 and WP - GPIO59 for MMC1 - SB-T35 */
304 OMAP3_MUX(UART2_CTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
305 OMAP3_MUX(GPMC_CLK, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
306
307 { .reg_offset = OMAP_MUX_TERMINATOR },
308};
309#endif
310
311static void __init cm_t3517_init(void)
312{
313 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
314 omap_serial_init();
315 omap_sdrc_init(NULL, NULL);
316 cm_t3517_init_leds();
317 cm_t3517_init_nand();
318 cm_t3517_init_rtc();
319 cm_t3517_init_usbh();
320 cm_t3517_init_hecc();
321 am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
322 omap_hsmmc_init(cm_t3517_mmc);
323}
324
325MACHINE_START(CM_T3517, "Compulab CM-T3517")
326 .atag_offset = 0x100,
327 .reserve = omap_reserve,
328 .map_io = omap3_map_io,
329 .init_early = am35xx_init_early,
330 .init_irq = omap3_init_irq,
331 .init_machine = cm_t3517_init,
332 .init_late = am35xx_init_late,
333 .init_time = omap3_gptimer_timer_init,
334 .restart = omap3xxx_restart,
335MACHINE_END
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 644ff3231bb8..e79c80bbc755 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3634,10 +3634,6 @@ int __init omap3xxx_clk_init(void)
3634 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks, 3634 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3635 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks)); 3635 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3636 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks)); 3636 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3637 } else if (soc_is_am33xx()) {
3638 cpu_mask = RATE_IN_AM33XX;
3639 } else if (cpu_is_ti814x()) {
3640 cpu_mask = RATE_IN_TI814X;
3641 } else if (cpu_is_omap34xx()) { 3637 } else if (cpu_is_omap34xx()) {
3642 if (omap_rev() == OMAP3430_REV_ES1_0) { 3638 if (omap_rev() == OMAP3430_REV_ES1_0) {
3643 cpu_mask = RATE_IN_3430ES1; 3639 cpu_mask = RATE_IN_3430ES1;
@@ -3681,7 +3677,7 @@ int __init omap3xxx_clk_init(void)
3681 * Lock DPLL5 -- here only until other device init code can 3677 * Lock DPLL5 -- here only until other device init code can
3682 * handle this 3678 * handle this
3683 */ 3679 */
3684 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0)) 3680 if (omap_rev() >= OMAP3430_REV_ES2_0)
3685 omap3_clk_lock_dpll5(); 3681 omap3_clk_lock_dpll5();
3686 3682
3687 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ 3683 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
deleted file mode 100644
index c78e893eba7d..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/*
2 * OMAP2xxx APLL clock control functions
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#undef DEBUG
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23
24
25#include "clock.h"
26#include "clock2xxx.h"
27#include "cm2xxx.h"
28#include "cm-regbits-24xx.h"
29
30/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
31#define EN_APLL_STOPPED 0
32#define EN_APLL_LOCKED 3
33
34/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
35#define APLLS_CLKIN_19_2MHZ 0
36#define APLLS_CLKIN_13MHZ 2
37#define APLLS_CLKIN_12MHZ 3
38
39/* Private functions */
40
41/**
42 * omap2xxx_clk_apll_locked - is the APLL locked?
43 * @hw: struct clk_hw * of the APLL to check
44 *
45 * If the APLL IP block referred to by @hw indicates that it's locked,
46 * return true; otherwise, return false.
47 */
48static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
49{
50 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
51 u32 r, apll_mask;
52
53 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
54
55 r = omap2xxx_cm_get_pll_status();
56
57 return ((r & apll_mask) == apll_mask) ? true : false;
58}
59
60int omap2_clk_apll96_enable(struct clk_hw *hw)
61{
62 return omap2xxx_cm_apll96_enable();
63}
64
65int omap2_clk_apll54_enable(struct clk_hw *hw)
66{
67 return omap2xxx_cm_apll54_enable();
68}
69
70static void _apll96_allow_idle(struct clk_hw_omap *clk)
71{
72 omap2xxx_cm_set_apll96_auto_low_power_stop();
73}
74
75static void _apll96_deny_idle(struct clk_hw_omap *clk)
76{
77 omap2xxx_cm_set_apll96_disable_autoidle();
78}
79
80static void _apll54_allow_idle(struct clk_hw_omap *clk)
81{
82 omap2xxx_cm_set_apll54_auto_low_power_stop();
83}
84
85static void _apll54_deny_idle(struct clk_hw_omap *clk)
86{
87 omap2xxx_cm_set_apll54_disable_autoidle();
88}
89
90void omap2_clk_apll96_disable(struct clk_hw *hw)
91{
92 omap2xxx_cm_apll96_disable();
93}
94
95void omap2_clk_apll54_disable(struct clk_hw *hw)
96{
97 omap2xxx_cm_apll54_disable();
98}
99
100unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
101 unsigned long parent_rate)
102{
103 return (omap2xxx_clk_apll_locked(hw)) ? 54000000 : 0;
104}
105
106unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
107 unsigned long parent_rate)
108{
109 return (omap2xxx_clk_apll_locked(hw)) ? 96000000 : 0;
110}
111
112/* Public data */
113const struct clk_hw_omap_ops clkhwops_apll54 = {
114 .allow_idle = _apll54_allow_idle,
115 .deny_idle = _apll54_deny_idle,
116};
117
118const struct clk_hw_omap_ops clkhwops_apll96 = {
119 .allow_idle = _apll96_allow_idle,
120 .deny_idle = _apll96_deny_idle,
121};
122
123/* Public functions */
124
125u32 omap2xxx_get_apll_clkin(void)
126{
127 u32 aplls, srate = 0;
128
129 aplls = omap2xxx_cm_get_pll_config();
130 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
131 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
132
133 if (aplls == APLLS_CLKIN_19_2MHZ)
134 srate = 19200000;
135 else if (aplls == APLLS_CLKIN_13MHZ)
136 srate = 13000000;
137 else if (aplls == APLLS_CLKIN_12MHZ)
138 srate = 12000000;
139
140 return srate;
141}
142
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a4282e79143e..1cf9dd85248a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -177,7 +177,6 @@ struct clksel {
177u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); 177u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
178void omap3_dpll_allow_idle(struct clk_hw_omap *clk); 178void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
179void omap3_dpll_deny_idle(struct clk_hw_omap *clk); 179void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
180int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
181void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); 180void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
182void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); 181void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
183 182
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index a090225ceeba..125c37614848 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -22,12 +22,7 @@ unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
22unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, 22unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
23 unsigned long parent_rate); 23 unsigned long parent_rate);
24void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); 24void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
25unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
26 unsigned long parent_rate);
27unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
28 unsigned long parent_rate);
29unsigned long omap2xxx_clk_get_core_rate(void); 25unsigned long omap2xxx_clk_get_core_rate(void);
30u32 omap2xxx_get_apll_clkin(void);
31u32 omap2xxx_get_sysclkdiv(void); 26u32 omap2xxx_get_sysclkdiv(void);
32void omap2xxx_clk_prepare_for_reboot(void); 27void omap2xxx_clk_prepare_for_reboot(void);
33void omap2xxx_clkt_vps_check_bootloader_rates(void); 28void omap2xxx_clkt_vps_check_bootloader_rates(void);
@@ -46,11 +41,5 @@ int omap2430_clk_init(void);
46#endif 41#endif
47 42
48extern struct clk_hw *dclk_hw; 43extern struct clk_hw *dclk_hw;
49int omap2_enable_osc_ck(struct clk_hw *hw);
50void omap2_disable_osc_ck(struct clk_hw *hw);
51int omap2_clk_apll96_enable(struct clk_hw *hw);
52int omap2_clk_apll54_enable(struct clk_hw *hw);
53void omap2_clk_apll96_disable(struct clk_hw *hw);
54void omap2_clk_apll54_disable(struct clk_hw *hw);
55 44
56#endif 45#endif
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index a96d901b1d5d..ef62ac9dcd05 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -370,16 +370,6 @@ u32 omap2xxx_cm_get_core_pll_config(void)
370 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 370 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
371} 371}
372 372
373u32 omap2xxx_cm_get_pll_config(void)
374{
375 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
376}
377
378u32 omap2xxx_cm_get_pll_status(void)
379{
380 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
381}
382
383void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm) 373void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
384{ 374{
385 u32 tmp; 375 u32 tmp;
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index c89502b168ae..83b6c597b0e1 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -60,8 +60,6 @@ extern int omap2xxx_cm_fclks_active(void);
60extern int omap2xxx_cm_mpu_retention_allowed(void); 60extern int omap2xxx_cm_mpu_retention_allowed(void);
61extern u32 omap2xxx_cm_get_core_clk_src(void); 61extern u32 omap2xxx_cm_get_core_clk_src(void);
62extern u32 omap2xxx_cm_get_core_pll_config(void); 62extern u32 omap2xxx_cm_get_core_pll_config(void);
63extern u32 omap2xxx_cm_get_pll_config(void);
64extern u32 omap2xxx_cm_get_pll_status(void);
65extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, 63extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
66 u32 mdm); 64 u32 mdm);
67 65
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index b9ad463a368a..cc5aac784278 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -72,27 +72,6 @@ static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
72 return v; 72 return v;
73} 73}
74 74
75static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
76{
77 return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
78}
79
80static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
81{
82 return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
83}
84
85static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
86{
87 u32 v;
88
89 v = am33xx_cm_read_reg(inst, idx);
90 v &= mask;
91 v >>= __ffs(mask);
92
93 return v;
94}
95
96/** 75/**
97 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield 76 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
98 * @inst: CM instance register offset (*_INST macro) 77 * @inst: CM instance register offset (*_INST macro)
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 0e58e5a85d53..fc712240e5fd 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -36,26 +36,6 @@
36/* Static rate multiplier for OMAP4 REGM4XEN clocks */ 36/* Static rate multiplier for OMAP4 REGM4XEN clocks */
37#define OMAP4430_REGM4XEN_MULT 4 37#define OMAP4430_REGM4XEN_MULT 4
38 38
39/* Supported only on OMAP4 */
40int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
41{
42 u32 v;
43 u32 mask;
44
45 if (!clk || !clk->clksel_reg)
46 return -EINVAL;
47
48 mask = clk->flags & CLOCK_CLKOUTX2 ?
49 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
50 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
51
52 v = omap2_clk_readl(clk, clk->clksel_reg);
53 v &= mask;
54 v >>= __ffs(mask);
55
56 return v;
57}
58
59void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) 39void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
60{ 40{
61 u32 v; 41 u32 v;
diff --git a/arch/arm/mach-omap2/omap-pm-noop.c b/arch/arm/mach-omap2/omap-pm-noop.c
index 6a3be2bebddb..a1ee8066958e 100644
--- a/arch/arm/mach-omap2/omap-pm-noop.c
+++ b/arch/arm/mach-omap2/omap-pm-noop.c
@@ -86,200 +86,10 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
86 return 0; 86 return 0;
87} 87}
88 88
89int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
90 long t)
91{
92 if (!req_dev || !dev || t < -1) {
93 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
94 return -EINVAL;
95 }
96
97 if (t == -1)
98 pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
99 dev_name(dev));
100 else
101 pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
102 dev_name(dev), t);
103
104 /*
105 * For current Linux, this needs to map the device to a
106 * powerdomain, then go through the list of current max lat
107 * constraints on that powerdomain and find the smallest. If
108 * the latency constraint has changed, the code should
109 * recompute the state to enter for the next powerdomain
110 * state. Conceivably, this code should also determine
111 * whether to actually disable the device clocks or not,
112 * depending on how long it takes to re-enable the clocks.
113 *
114 * TI CDP code can call constraint_set here.
115 */
116
117 return 0;
118}
119
120int omap_pm_set_max_sdma_lat(struct device *dev, long t)
121{
122 if (!dev || t < -1) {
123 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
124 return -EINVAL;
125 }
126
127 if (t == -1)
128 pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
129 dev_name(dev));
130 else
131 pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
132 dev_name(dev), t);
133
134 /*
135 * For current Linux PM QOS params, this code should scan the
136 * list of maximum CPU and DMA latencies and select the
137 * smallest, then set cpu_dma_latency pm_qos_param
138 * accordingly.
139 *
140 * For future Linux PM QOS params, with separate CPU and DMA
141 * latency params, this code should just set the dma_latency param.
142 *
143 * TI CDP code can call constraint_set here.
144 */
145
146 return 0;
147}
148
149int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
150{
151 if (!dev || !c || r < 0) {
152 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
153 return -EINVAL;
154 }
155
156 if (r == 0)
157 pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
158 dev_name(dev));
159 else
160 pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
161 dev_name(dev), r);
162
163 /*
164 * Code in a real implementation should keep track of these
165 * constraints on the clock, and determine the highest minimum
166 * clock rate. It should iterate over each OPP and determine
167 * whether the OPP will result in a clock rate that would
168 * satisfy this constraint (and any other PM constraint in effect
169 * at that time). Once it finds the lowest-voltage OPP that
170 * meets those conditions, it should switch to it, or return
171 * an error if the code is not capable of doing so.
172 */
173
174 return 0;
175}
176
177/* 89/*
178 * DSP Bridge-specific constraints 90 * DSP Bridge-specific constraints
179 */ 91 */
180 92
181const struct omap_opp *omap_pm_dsp_get_opp_table(void)
182{
183 pr_debug("OMAP PM: DSP request for OPP table\n");
184
185 /*
186 * Return DSP frequency table here: The final item in the
187 * array should have .rate = .opp_id = 0.
188 */
189
190 return NULL;
191}
192
193void omap_pm_dsp_set_min_opp(u8 opp_id)
194{
195 if (opp_id == 0) {
196 WARN_ON(1);
197 return;
198 }
199
200 pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
201
202 /*
203 *
204 * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
205 * can just test to see which is higher, the CPU's desired OPP
206 * ID or the DSP's desired OPP ID, and use whichever is
207 * highest.
208 *
209 * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
210 * rate is keyed on MPU speed, not the OPP ID. So we need to
211 * map the OPP ID to the MPU speed for use with clk_set_rate()
212 * if it is higher than the current OPP clock rate.
213 *
214 */
215}
216
217
218u8 omap_pm_dsp_get_opp(void)
219{
220 pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
221
222 /*
223 * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
224 *
225 * CDP12.14+:
226 * Call clk_get_rate() on the OPP custom clock, map that to an
227 * OPP ID using the tables defined in board-*.c/chip-*.c files.
228 */
229
230 return 0;
231}
232
233/*
234 * CPUFreq-originated constraint
235 *
236 * In the future, this should be handled by custom OPP clocktype
237 * functions.
238 */
239
240struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
241{
242 pr_debug("OMAP PM: CPUFreq request for frequency table\n");
243
244 /*
245 * Return CPUFreq frequency table here: loop over
246 * all VDD1 clkrates, pull out the mpu_ck frequencies, build
247 * table
248 */
249
250 return NULL;
251}
252
253void omap_pm_cpu_set_freq(unsigned long f)
254{
255 if (f == 0) {
256 WARN_ON(1);
257 return;
258 }
259
260 pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
261 f);
262
263 /*
264 * For l-o dev tree, determine whether MPU freq or DSP OPP id
265 * freq is higher. Find the OPP ID corresponding to the
266 * higher frequency. Call clk_round_rate() and clk_set_rate()
267 * on the OPP custom clock.
268 *
269 * CDP should just be able to set the VDD1 OPP clock rate here.
270 */
271}
272
273unsigned long omap_pm_cpu_get_freq(void)
274{
275 pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
276
277 /*
278 * Call clk_get_rate() on the mpu_ck.
279 */
280
281 return 0;
282}
283 93
284/** 94/**
285 * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled 95 * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled
@@ -363,9 +173,3 @@ int __init omap_pm_if_init(void)
363{ 173{
364 return 0; 174 return 0;
365} 175}
366
367void omap_pm_if_exit(void)
368{
369 /* Deallocate CPUFreq frequency table here */
370}
371
diff --git a/arch/arm/mach-omap2/omap-pm.h b/arch/arm/mach-omap2/omap-pm.h
index 1d777e63e05c..109bef5538eb 100644
--- a/arch/arm/mach-omap2/omap-pm.h
+++ b/arch/arm/mach-omap2/omap-pm.h
@@ -50,14 +50,6 @@ int __init omap_pm_if_early_init(void);
50 */ 50 */
51int __init omap_pm_if_init(void); 51int __init omap_pm_if_init(void);
52 52
53/**
54 * omap_pm_if_exit - OMAP PM exit code
55 *
56 * Exit code; currently unused. The "_if_" is to avoid name
57 * collisions with the PM idle-loop code.
58 */
59void omap_pm_if_exit(void);
60
61/* 53/*
62 * Device-driver-originated constraints (via board-*.c files, platform_data) 54 * Device-driver-originated constraints (via board-*.c files, platform_data)
63 */ 55 */
@@ -132,163 +124,6 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
132int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r); 124int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
133 125
134 126
135/**
136 * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
137 * @req_dev: struct device * requesting the constraint, or NULL if none
138 * @dev: struct device * to set the constraint one
139 * @t: maximum device wakeup latency in microseconds
140 *
141 * Request that the maximum amount of time necessary for a device @dev
142 * to become accessible after its clocks are enabled should be no
143 * greater than @t microseconds. Specifically, this represents the
144 * time from when a device driver enables device clocks with
145 * clk_enable(), to when the register reads and writes on the device
146 * will succeed. This function should be called before clk_disable()
147 * is called, since the power state transition decision may be made
148 * during clk_disable().
149 *
150 * It is intended that underlying PM code will use this information to
151 * determine what power state to put the powerdomain enclosing this
152 * device into.
153 *
154 * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the
155 * previous wakeup latency values for this device. To remove the
156 * wakeup latency restriction for this device, call with t = -1.
157 *
158 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
159 * is not satisfiable, or 0 upon success.
160 */
161int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
162 long t);
163
164
165/**
166 * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
167 * @dev: struct device *
168 * @t: maximum DMA transfer start latency in microseconds
169 *
170 * Request that the maximum system DMA transfer start latency for this
171 * device 'dev' should be no greater than 't' microseconds. "DMA
172 * transfer start latency" here is defined as the elapsed time from
173 * when a device (e.g., McBSP) requests that a system DMA transfer
174 * start or continue, to the time at which data starts to flow into
175 * that device from the system DMA controller.
176 *
177 * It is intended that underlying PM code will use this information to
178 * determine what power state to put the CORE powerdomain into.
179 *
180 * Since system DMA transfers may not involve the MPU, this function
181 * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
182 * so. Similarly, this function will not affect device wakeup latency
183 * -- use set_max_dev_wakeup_lat() to affect that.
184 *
185 * Multiple calls to set_max_sdma_lat() will replace the previous t
186 * value for this device. To remove the maximum DMA latency for this
187 * device, call with t = -1.
188 *
189 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
190 * is not satisfiable, or 0 upon success.
191 */
192int omap_pm_set_max_sdma_lat(struct device *dev, long t);
193
194
195/**
196 * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev
197 * @dev: struct device * requesting the constraint
198 * @clk: struct clk * to set the minimum rate constraint on
199 * @r: minimum rate in Hz
200 *
201 * Request that the minimum clock rate on the device @dev's clk @clk
202 * be no less than @r Hz.
203 *
204 * It is expected that the OMAP PM code will use this information to
205 * find an OPP or clock setting that will satisfy this clock rate
206 * constraint, along with any other applicable system constraints on
207 * the clock rate or corresponding voltage, etc.
208 *
209 * omap_pm_set_min_clk_rate() differs from the clock code's
210 * clk_set_rate() in that it considers other constraints before taking
211 * any hardware action, and may change a system OPP rather than just a
212 * clock rate. clk_set_rate() is intended to be a low-level
213 * interface.
214 *
215 * omap_pm_set_min_clk_rate() is easily open to abuse. A better API
216 * would be something like "omap_pm_set_min_dev_performance()";
217 * however, there is no easily-generalizable concept of performance
218 * that applies to all devices. Only a device (and possibly the
219 * device subsystem) has both the subsystem-specific knowledge, and
220 * the hardware IP block-specific knowledge, to translate a constraint
221 * on "touchscreen sampling accuracy" or "number of pixels or polygons
222 * rendered per second" to a clock rate. This translation can be
223 * dependent on the hardware IP block's revision, or firmware version,
224 * and the driver is the only code on the system that has this
225 * information and can know how to translate that into a clock rate.
226 *
227 * The intended use-case for this function is for userspace or other
228 * kernel code to communicate a particular performance requirement to
229 * a subsystem; then for the subsystem to communicate that requirement
230 * to something that is meaningful to the device driver; then for the
231 * device driver to convert that requirement to a clock rate, and to
232 * then call omap_pm_set_min_clk_rate().
233 *
234 * Users of this function (such as device drivers) should not simply
235 * call this function with some high clock rate to ensure "high
236 * performance." Rather, the device driver should take a performance
237 * constraint from its subsystem, such as "render at least X polygons
238 * per second," and use some formula or table to convert that into a
239 * clock rate constraint given the hardware type and hardware
240 * revision. Device drivers or subsystems should not assume that they
241 * know how to make a power/performance tradeoff - some device use
242 * cases may tolerate a lower-fidelity device function for lower power
243 * consumption; others may demand a higher-fidelity device function,
244 * no matter what the power consumption.
245 *
246 * Multiple calls to omap_pm_set_min_clk_rate() will replace the
247 * previous rate value for the device @dev. To remove the minimum clock
248 * rate constraint for the device, call with r = 0.
249 *
250 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
251 * is not satisfiable, or 0 upon success.
252 */
253int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r);
254
255/*
256 * DSP Bridge-specific constraints
257 */
258
259/**
260 * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
261 *
262 * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
263 * frequency entries. The final item in the array should have .rate =
264 * .opp_id = 0.
265 */
266const struct omap_opp *omap_pm_dsp_get_opp_table(void);
267
268/**
269 * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
270 * @opp_id: target DSP OPP ID
271 *
272 * Set a minimum OPP ID for the DSP. This is intended to be called
273 * only from the DSP Bridge MPU-side driver. Unfortunately, the only
274 * information that code receives from the DSP/BIOS load estimator is the
275 * target OPP ID; hence, this interface. No return value.
276 */
277void omap_pm_dsp_set_min_opp(u8 opp_id);
278
279/**
280 * omap_pm_dsp_get_opp - report the current DSP OPP ID
281 *
282 * Report the current OPP for the DSP. Since on OMAP3, the DSP and
283 * MPU share a single voltage domain, the OPP ID returned back may
284 * represent a higher DSP speed than the OPP requested via
285 * omap_pm_dsp_set_min_opp().
286 *
287 * Returns the current VDD1 OPP ID, or 0 upon error.
288 */
289u8 omap_pm_dsp_get_opp(void);
290
291
292/* 127/*
293 * CPUFreq-originated constraint 128 * CPUFreq-originated constraint
294 * 129 *
@@ -296,33 +131,6 @@ u8 omap_pm_dsp_get_opp(void);
296 * functions. 131 * functions.
297 */ 132 */
298 133
299/**
300 * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
301 *
302 * Provide a frequency table usable by CPUFreq for the current chip/board.
303 * Returns a pointer to a struct cpufreq_frequency_table array or NULL
304 * upon error.
305 */
306struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
307
308/**
309 * omap_pm_cpu_set_freq - set the current minimum MPU frequency
310 * @f: MPU frequency in Hz
311 *
312 * Set the current minimum CPU frequency. The actual CPU frequency
313 * used could end up higher if the DSP requested a higher OPP.
314 * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
315 * return value.
316 */
317void omap_pm_cpu_set_freq(unsigned long f);
318
319/**
320 * omap_pm_cpu_get_freq - report the current CPU frequency
321 *
322 * Returns the current MPU frequency, or 0 upon error.
323 */
324unsigned long omap_pm_cpu_get_freq(void);
325
326 134
327/* 135/*
328 * Device context loss tracking 136 * Device context loss tracking
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2af58570cb65..bb41dc2b580e 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3384,91 +3384,6 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
3384 return 0; 3384 return 0;
3385} 3385}
3386 3386
3387/**
3388 * omap_hwmod_enable_clocks - enable main_clk, all interface clocks
3389 * @oh: struct omap_hwmod *oh
3390 *
3391 * Intended to be called by the omap_device code.
3392 */
3393int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
3394{
3395 unsigned long flags;
3396
3397 spin_lock_irqsave(&oh->_lock, flags);
3398 _enable_clocks(oh);
3399 spin_unlock_irqrestore(&oh->_lock, flags);
3400
3401 return 0;
3402}
3403
3404/**
3405 * omap_hwmod_disable_clocks - disable main_clk, all interface clocks
3406 * @oh: struct omap_hwmod *oh
3407 *
3408 * Intended to be called by the omap_device code.
3409 */
3410int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
3411{
3412 unsigned long flags;
3413
3414 spin_lock_irqsave(&oh->_lock, flags);
3415 _disable_clocks(oh);
3416 spin_unlock_irqrestore(&oh->_lock, flags);
3417
3418 return 0;
3419}
3420
3421/**
3422 * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete
3423 * @oh: struct omap_hwmod *oh
3424 *
3425 * Intended to be called by drivers and core code when all posted
3426 * writes to a device must complete before continuing further
3427 * execution (for example, after clearing some device IRQSTATUS
3428 * register bits)
3429 *
3430 * XXX what about targets with multiple OCP threads?
3431 */
3432void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
3433{
3434 BUG_ON(!oh);
3435
3436 if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
3437 WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n",
3438 oh->name);
3439 return;
3440 }
3441
3442 /*
3443 * Forces posted writes to complete on the OCP thread handling
3444 * register writes
3445 */
3446 omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
3447}
3448
3449/**
3450 * omap_hwmod_reset - reset the hwmod
3451 * @oh: struct omap_hwmod *
3452 *
3453 * Under some conditions, a driver may wish to reset the entire device.
3454 * Called from omap_device code. Returns -EINVAL on error or passes along
3455 * the return value from _reset().
3456 */
3457int omap_hwmod_reset(struct omap_hwmod *oh)
3458{
3459 int r;
3460 unsigned long flags;
3461
3462 if (!oh)
3463 return -EINVAL;
3464
3465 spin_lock_irqsave(&oh->_lock, flags);
3466 r = _reset(oh);
3467 spin_unlock_irqrestore(&oh->_lock, flags);
3468
3469 return r;
3470}
3471
3472/* 3387/*
3473 * IP block data retrieval functions 3388 * IP block data retrieval functions
3474 */ 3389 */
@@ -3729,52 +3644,12 @@ void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
3729 return oh->_mpu_rt_va; 3644 return oh->_mpu_rt_va;
3730} 3645}
3731 3646
3732/**
3733 * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh
3734 * @oh: struct omap_hwmod *
3735 * @init_oh: struct omap_hwmod * (initiator)
3736 *
3737 * Add a sleep dependency between the initiator @init_oh and @oh.
3738 * Intended to be called by DSP/Bridge code via platform_data for the
3739 * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge
3740 * code needs to add/del initiator dependencies dynamically
3741 * before/after accessing a device. Returns the return value from
3742 * _add_initiator_dep().
3743 *
3744 * XXX Keep a usecount in the clockdomain code
3745 */
3746int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
3747 struct omap_hwmod *init_oh)
3748{
3749 return _add_initiator_dep(oh, init_oh);
3750}
3751
3752/* 3647/*
3753 * XXX what about functions for drivers to save/restore ocp_sysconfig 3648 * XXX what about functions for drivers to save/restore ocp_sysconfig
3754 * for context save/restore operations? 3649 * for context save/restore operations?
3755 */ 3650 */
3756 3651
3757/** 3652/**
3758 * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh
3759 * @oh: struct omap_hwmod *
3760 * @init_oh: struct omap_hwmod * (initiator)
3761 *
3762 * Remove a sleep dependency between the initiator @init_oh and @oh.
3763 * Intended to be called by DSP/Bridge code via platform_data for the
3764 * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge
3765 * code needs to add/del initiator dependencies dynamically
3766 * before/after accessing a device. Returns the return value from
3767 * _del_initiator_dep().
3768 *
3769 * XXX Keep a usecount in the clockdomain code
3770 */
3771int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
3772 struct omap_hwmod *init_oh)
3773{
3774 return _del_initiator_dep(oh, init_oh);
3775}
3776
3777/**
3778 * omap_hwmod_enable_wakeup - allow device to wake up the system 3653 * omap_hwmod_enable_wakeup - allow device to wake up the system
3779 * @oh: struct omap_hwmod * 3654 * @oh: struct omap_hwmod *
3780 * 3655 *
@@ -3895,33 +3770,6 @@ int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
3895} 3770}
3896 3771
3897/** 3772/**
3898 * omap_hwmod_read_hardreset - read the HW reset line state of submodules
3899 * contained in the hwmod module
3900 * @oh: struct omap_hwmod *
3901 * @name: name of the reset line to look up and read
3902 *
3903 * Return the current state of the hwmod @oh's reset line named @name:
3904 * returns -EINVAL upon parameter error or if this operation
3905 * is unsupported on the current OMAP; otherwise, passes along the return
3906 * value from _read_hardreset().
3907 */
3908int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
3909{
3910 int ret;
3911 unsigned long flags;
3912
3913 if (!oh)
3914 return -EINVAL;
3915
3916 spin_lock_irqsave(&oh->_lock, flags);
3917 ret = _read_hardreset(oh, name);
3918 spin_unlock_irqrestore(&oh->_lock, flags);
3919
3920 return ret;
3921}
3922
3923
3924/**
3925 * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname 3773 * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
3926 * @classname: struct omap_hwmod_class name to search for 3774 * @classname: struct omap_hwmod_class name to search for
3927 * @fn: callback function pointer to call for each hwmod in class @classname 3775 * @fn: callback function pointer to call for each hwmod in class @classname
@@ -4031,86 +3879,6 @@ int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
4031} 3879}
4032 3880
4033/** 3881/**
4034 * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
4035 * @oh: struct omap_hwmod *
4036 *
4037 * Prevent the hwmod @oh from being reset during the setup process.
4038 * Intended for use by board-*.c files on boards with devices that
4039 * cannot tolerate being reset. Must be called before the hwmod has
4040 * been set up. Returns 0 upon success or negative error code upon
4041 * failure.
4042 */
4043int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
4044{
4045 if (!oh)
4046 return -EINVAL;
4047
4048 if (oh->_state != _HWMOD_STATE_REGISTERED) {
4049 pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
4050 oh->name);
4051 return -EINVAL;
4052 }
4053
4054 oh->flags |= HWMOD_INIT_NO_RESET;
4055
4056 return 0;
4057}
4058
4059/**
4060 * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ
4061 * @oh: struct omap_hwmod * containing hwmod mux entries
4062 * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup
4063 * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup
4064 *
4065 * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux
4066 * entry number @pad_idx for the hwmod @oh, trigger the interrupt
4067 * service routine for the hwmod's mpu_irqs array index @irq_idx. If
4068 * this function is not called for a given pad_idx, then the ISR
4069 * associated with @oh's first MPU IRQ will be triggered when an I/O
4070 * pad wakeup occurs on that pad. Note that @pad_idx is the index of
4071 * the _dynamic or wakeup_ entry: if there are other entries not
4072 * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these
4073 * entries are NOT COUNTED in the dynamic pad index. This function
4074 * must be called separately for each pad that requires its interrupt
4075 * to be re-routed this way. Returns -EINVAL if there is an argument
4076 * problem or if @oh does not have hwmod mux entries or MPU IRQs;
4077 * returns -ENOMEM if memory cannot be allocated; or 0 upon success.
4078 *
4079 * XXX This function interface is fragile. Rather than using array
4080 * indexes, which are subject to unpredictable change, it should be
4081 * using hwmod IRQ names, and some other stable key for the hwmod mux
4082 * pad records.
4083 */
4084int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
4085{
4086 int nr_irqs;
4087
4088 might_sleep();
4089
4090 if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 ||
4091 pad_idx >= oh->mux->nr_pads_dynamic)
4092 return -EINVAL;
4093
4094 /* Check the number of available mpu_irqs */
4095 for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++)
4096 ;
4097
4098 if (irq_idx >= nr_irqs)
4099 return -EINVAL;
4100
4101 if (!oh->mux->irqs) {
4102 /* XXX What frees this? */
4103 oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic,
4104 GFP_KERNEL);
4105 if (!oh->mux->irqs)
4106 return -ENOMEM;
4107 }
4108 oh->mux->irqs[pad_idx] = irq_idx;
4109
4110 return 0;
4111}
4112
4113/**
4114 * omap_hwmod_init - initialize the hwmod code 3882 * omap_hwmod_init - initialize the hwmod code
4115 * 3883 *
4116 * Sets up some function pointers needed by the hwmod code to operate on the 3884 * Sets up some function pointers needed by the hwmod code to operate on the
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 5b42fafcaf55..fcfdd85aad62 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -703,13 +703,6 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh);
703 703
704int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); 704int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
705int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); 705int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
706int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
707
708int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
709int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
710
711int omap_hwmod_reset(struct omap_hwmod *oh);
712void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
713 706
714void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); 707void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
715u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); 708u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
@@ -724,11 +717,6 @@ int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
724struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); 717struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
725void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); 718void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
726 719
727int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
728 struct omap_hwmod *init_oh);
729int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
730 struct omap_hwmod *init_oh);
731
732int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); 720int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
733int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); 721int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
734 722
@@ -740,10 +728,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
740int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); 728int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
741int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); 729int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
742 730
743int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
744
745int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
746
747extern void __init omap_hwmod_init(void); 731extern void __init omap_hwmod_init(void);
748 732
749const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); 733const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 11468eea3871..4e8e93c398db 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -29,8 +29,6 @@
29#include <linux/platform_data/mailbox-omap.h> 29#include <linux/platform_data/mailbox-omap.h>
30#include <plat/dmtimer.h> 30#include <plat/dmtimer.h>
31 31
32#include "am35xx.h"
33
34#include "soc.h" 32#include "soc.h"
35#include "omap_hwmod.h" 33#include "omap_hwmod.h"
36#include "omap_hwmod_common_data.h" 34#include "omap_hwmod_common_data.h"
@@ -50,6 +48,8 @@
50 * elsewhere. 48 * elsewhere.
51 */ 49 */
52 50
51#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
52
53/* 53/*
54 * IP blocks 54 * IP blocks
55 */ 55 */
@@ -3459,15 +3459,6 @@ static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3459 .user = OCP_USER_MPU, 3459 .user = OCP_USER_MPU,
3460}; 3460};
3461 3461
3462static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3463 {
3464 .pa_start = AM35XX_IPSS_MDIO_BASE,
3465 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3466 .flags = ADDR_TYPE_RT,
3467 },
3468 { }
3469};
3470
3471/* l4_core -> davinci mdio */ 3462/* l4_core -> davinci mdio */
3472/* 3463/*
3473 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 3464 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
@@ -3478,25 +3469,15 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3478 .master = &omap3xxx_l4_core_hwmod, 3469 .master = &omap3xxx_l4_core_hwmod,
3479 .slave = &am35xx_mdio_hwmod, 3470 .slave = &am35xx_mdio_hwmod,
3480 .clk = "emac_fck", 3471 .clk = "emac_fck",
3481 .addr = am35xx_mdio_addrs,
3482 .user = OCP_USER_MPU, 3472 .user = OCP_USER_MPU,
3483}; 3473};
3484 3474
3485static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3486 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
3487 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
3488 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
3489 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3490 { .irq = -1 },
3491};
3492
3493static struct omap_hwmod_class am35xx_emac_class = { 3475static struct omap_hwmod_class am35xx_emac_class = {
3494 .name = "davinci_emac", 3476 .name = "davinci_emac",
3495}; 3477};
3496 3478
3497static struct omap_hwmod am35xx_emac_hwmod = { 3479static struct omap_hwmod am35xx_emac_hwmod = {
3498 .name = "davinci_emac", 3480 .name = "davinci_emac",
3499 .mpu_irqs = am35xx_emac_mpu_irqs,
3500 .class = &am35xx_emac_class, 3481 .class = &am35xx_emac_class,
3501 /* 3482 /*
3502 * According to Mark Greer, the MPU will not return from WFI 3483 * According to Mark Greer, the MPU will not return from WFI
@@ -3519,15 +3500,6 @@ static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3519 .user = OCP_USER_MPU, 3500 .user = OCP_USER_MPU,
3520}; 3501};
3521 3502
3522static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3523 {
3524 .pa_start = AM35XX_IPSS_EMAC_BASE,
3525 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3526 .flags = ADDR_TYPE_RT,
3527 },
3528 { }
3529};
3530
3531/* l4_core -> davinci emac */ 3503/* l4_core -> davinci emac */
3532/* 3504/*
3533 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 3505 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
@@ -3538,7 +3510,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3538 .master = &omap3xxx_l4_core_hwmod, 3510 .master = &omap3xxx_l4_core_hwmod,
3539 .slave = &am35xx_emac_hwmod, 3511 .slave = &am35xx_emac_hwmod,
3540 .clk = "emac_ick", 3512 .clk = "emac_ick",
3541 .addr = am35xx_emac_addrs,
3542 .user = OCP_USER_MPU, 3513 .user = OCP_USER_MPU,
3543}; 3514};
3544 3515
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 1a19fa096bab..8e903564ede2 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -152,38 +152,3 @@ void am35x_set_mode(u8 musb_mode)
152 152
153 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); 153 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
154} 154}
155
156void ti81xx_musb_phy_power(u8 on)
157{
158 void __iomem *scm_base = NULL;
159 u32 usbphycfg;
160
161 scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
162 if (!scm_base) {
163 pr_err("system control module ioremap failed\n");
164 return;
165 }
166
167 usbphycfg = readl_relaxed(scm_base + USBCTRL0);
168
169 if (on) {
170 if (cpu_is_ti816x()) {
171 usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
172 usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
173 } else if (cpu_is_ti814x()) {
174 usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
175 | USBPHY_DPINPUT | USBPHY_DMINPUT);
176 usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
177 | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
178 }
179 } else {
180 if (cpu_is_ti816x())
181 usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
182 else if (cpu_is_ti814x())
183 usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
184
185 }
186 writel_relaxed(usbphycfg, scm_base + USBCTRL0);
187
188 iounmap(scm_base);
189}
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 3d7eee1d3cfa..190fa43e7479 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -19,7 +19,6 @@
19#include <linux/platform_data/pinctrl-single.h> 19#include <linux/platform_data/pinctrl-single.h>
20#include <linux/platform_data/iommu-omap.h> 20#include <linux/platform_data/iommu-omap.h>
21 21
22#include "am35xx.h"
23#include "common.h" 22#include "common.h"
24#include "common-board-devices.h" 23#include "common-board-devices.h"
25#include "dss-common.h" 24#include "dss-common.h"
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index 33c8846b4193..a69e9a33cb6d 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -13,7 +13,7 @@
13 */ 13 */
14#include <linux/of.h> 14#include <linux/of.h>
15 15
16#include <asm/pmu.h> 16#include <asm/system_info.h>
17 17
18#include "soc.h" 18#include "soc.h"
19#include "omap_hwmod.h" 19#include "omap_hwmod.h"
@@ -37,7 +37,8 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
37{ 37{
38 int i; 38 int i;
39 struct omap_hwmod *oh[3]; 39 struct omap_hwmod *oh[3];
40 char *dev_name = "arm-pmu"; 40 char *dev_name = cpu_architecture() == CPU_ARCH_ARMv6 ?
41 "armv6-pmu" : "armv7-pmu";
41 42
42 if ((!oh_num) || (oh_num > 3)) 43 if ((!oh_num) || (oh_num > 3))
43 return -EINVAL; 44 return -EINVAL;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 7fb033eca0a5..78af6d8cf2e2 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -115,7 +115,6 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
115 } 115 }
116 pwrdm->voltdm.ptr = voltdm; 116 pwrdm->voltdm.ptr = voltdm;
117 INIT_LIST_HEAD(&pwrdm->voltdm_node); 117 INIT_LIST_HEAD(&pwrdm->voltdm_node);
118 voltdm_add_pwrdm(voltdm, pwrdm);
119skip_voltdm: 118skip_voltdm:
120 spin_lock_init(&pwrdm->_lock); 119 spin_lock_init(&pwrdm->_lock);
121 120
@@ -484,87 +483,6 @@ pac_exit:
484} 483}
485 484
486/** 485/**
487 * pwrdm_del_clkdm - remove a clockdomain from a powerdomain
488 * @pwrdm: struct powerdomain * to add the clockdomain to
489 * @clkdm: struct clockdomain * to associate with a powerdomain
490 *
491 * Dissociate the clockdomain @clkdm from the powerdomain
492 * @pwrdm. Returns -EINVAL if presented with invalid pointers; -ENOENT
493 * if @clkdm was not associated with the powerdomain, or 0 upon
494 * success.
495 */
496int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
497{
498 int ret = -EINVAL;
499 int i;
500
501 if (!pwrdm || !clkdm)
502 return -EINVAL;
503
504 pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
505 pwrdm->name, clkdm->name);
506
507 for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
508 if (pwrdm->pwrdm_clkdms[i] == clkdm)
509 break;
510
511 if (i == PWRDM_MAX_CLKDMS) {
512 pr_debug("powerdomain: %s: clkdm %s not associated?!\n",
513 pwrdm->name, clkdm->name);
514 ret = -ENOENT;
515 goto pdc_exit;
516 }
517
518 pwrdm->pwrdm_clkdms[i] = NULL;
519
520 ret = 0;
521
522pdc_exit:
523 return ret;
524}
525
526/**
527 * pwrdm_for_each_clkdm - call function on each clkdm in a pwrdm
528 * @pwrdm: struct powerdomain * to iterate over
529 * @fn: callback function *
530 *
531 * Call the supplied function @fn for each clockdomain in the powerdomain
532 * @pwrdm. The callback function can return anything but 0 to bail
533 * out early from the iterator. Returns -EINVAL if presented with
534 * invalid pointers; or passes along the last return value of the
535 * callback function, which should be 0 for success or anything else
536 * to indicate failure.
537 */
538int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
539 int (*fn)(struct powerdomain *pwrdm,
540 struct clockdomain *clkdm))
541{
542 int ret = 0;
543 int i;
544
545 if (!fn)
546 return -EINVAL;
547
548 for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
549 if (pwrdm->pwrdm_clkdms[i])
550 ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
551
552 return ret;
553}
554
555/**
556 * pwrdm_get_voltdm - return a ptr to the voltdm that this pwrdm resides in
557 * @pwrdm: struct powerdomain *
558 *
559 * Return a pointer to the struct voltageomain that the specified powerdomain
560 * @pwrdm exists in.
561 */
562struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm)
563{
564 return pwrdm->voltdm.ptr;
565}
566
567/**
568 * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain 486 * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
569 * @pwrdm: struct powerdomain * 487 * @pwrdm: struct powerdomain *
570 * 488 *
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 11bd4dd7d8d6..28a796ce07d7 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -212,11 +212,6 @@ int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
212 void *user); 212 void *user);
213 213
214int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 214int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
215int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
216int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
217 int (*fn)(struct powerdomain *pwrdm,
218 struct clockdomain *clkdm));
219struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
220 215
221int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); 216int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
222 217
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index cfde3f4a03cc..ed8a3d8b739a 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -145,7 +145,6 @@ extern void omap3_prm_vcvp_write(u32 val, u8 offset);
145extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 145extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
146 146
147extern int __init omap3xxx_prm_init(void); 147extern int __init omap3xxx_prm_init(void);
148extern u32 omap3xxx_prm_get_reset_sources(void);
149int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits); 148int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
150void omap3xxx_prm_iva_idle(void); 149void omap3xxx_prm_iva_idle(void);
151void omap3_prm_reset_modem(void); 150void omap3_prm_reset_modem(void);
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index f7512515fde5..714329565b90 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -39,7 +39,6 @@ extern void omap4_prm_vcvp_write(u32 val, u8 offset);
39extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 39extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
40 40
41extern int __init omap44xx_prm_init(void); 41extern int __init omap44xx_prm_init(void);
42extern u32 omap44xx_prm_get_reset_sources(void);
43 42
44#endif 43#endif
45 44
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index bc897231bd10..e4562b2b973b 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -82,16 +82,8 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
82 musb_plat.mode = board_data->mode; 82 musb_plat.mode = board_data->mode;
83 musb_plat.extvbus = board_data->extvbus; 83 musb_plat.extvbus = board_data->extvbus;
84 84
85 if (soc_is_am35xx()) { 85 oh_name = "usb_otg_hs";
86 oh_name = "am35x_otg_hs"; 86 name = "musb-omap2430";
87 name = "musb-am35x";
88 } else if (cpu_is_ti81xx()) {
89 oh_name = "usb_otg_hs";
90 name = "musb-ti81xx";
91 } else {
92 oh_name = "usb_otg_hs";
93 name = "musb-omap2430";
94 }
95 87
96 oh = omap_hwmod_lookup(oh_name); 88 oh = omap_hwmod_lookup(oh_name);
97 if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", 89 if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
index 4ba2ae759895..3395365ef1db 100644
--- a/arch/arm/mach-omap2/usb.h
+++ b/arch/arm/mach-omap2/usb.h
@@ -68,5 +68,3 @@ extern void am35x_musb_reset(void);
68extern void am35x_musb_phy_power(u8 on); 68extern void am35x_musb_phy_power(u8 on);
69extern void am35x_musb_clear_irq(void); 69extern void am35x_musb_clear_irq(void);
70extern void am35x_set_mode(u8 musb_mode); 70extern void am35x_set_mode(u8 musb_mode);
71extern void ti81xx_musb_phy_power(u8 on);
72
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 3783b8625f0f..cba8cada8c81 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -224,37 +224,6 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
224} 224}
225 225
226/** 226/**
227 * omap_change_voltscale_method() - API to change the voltage scaling method.
228 * @voltdm: pointer to the VDD whose voltage scaling method
229 * has to be changed.
230 * @voltscale_method: the method to be used for voltage scaling.
231 *
232 * This API can be used by the board files to change the method of voltage
233 * scaling between vpforceupdate and vcbypass. The parameter values are
234 * defined in voltage.h
235 */
236void omap_change_voltscale_method(struct voltagedomain *voltdm,
237 int voltscale_method)
238{
239 if (!voltdm || IS_ERR(voltdm)) {
240 pr_warn("%s: VDD specified does not exist!\n", __func__);
241 return;
242 }
243
244 switch (voltscale_method) {
245 case VOLTSCALE_VPFORCEUPDATE:
246 voltdm->scale = omap_vp_forceupdate_scale;
247 return;
248 case VOLTSCALE_VCBYPASS:
249 voltdm->scale = omap_vc_bypass_scale;
250 return;
251 default:
252 pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n",
253 __func__);
254 }
255}
256
257/**
258 * omap_voltage_late_init() - Init the various voltage parameters 227 * omap_voltage_late_init() - Init the various voltage parameters
259 * 228 *
260 * This API is to be called in the later stages of the 229 * This API is to be called in the later stages of the
@@ -316,90 +285,11 @@ static struct voltagedomain *_voltdm_lookup(const char *name)
316 return voltdm; 285 return voltdm;
317} 286}
318 287
319/**
320 * voltdm_add_pwrdm - add a powerdomain to a voltagedomain
321 * @voltdm: struct voltagedomain * to add the powerdomain to
322 * @pwrdm: struct powerdomain * to associate with a voltagedomain
323 *
324 * Associate the powerdomain @pwrdm with a voltagedomain @voltdm. This
325 * enables the use of voltdm_for_each_pwrdm(). Returns -EINVAL if
326 * presented with invalid pointers; -ENOMEM if memory could not be allocated;
327 * or 0 upon success.
328 */
329int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm)
330{
331 if (!voltdm || !pwrdm)
332 return -EINVAL;
333
334 pr_debug("voltagedomain: %s: associating powerdomain %s\n",
335 voltdm->name, pwrdm->name);
336
337 list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
338
339 return 0;
340}
341
342/**
343 * voltdm_for_each_pwrdm - call function for each pwrdm in a voltdm
344 * @voltdm: struct voltagedomain * to iterate over
345 * @fn: callback function *
346 *
347 * Call the supplied function @fn for each powerdomain in the
348 * voltagedomain @voltdm. Returns -EINVAL if presented with invalid
349 * pointers; or passes along the last return value of the callback
350 * function, which should be 0 for success or anything else to
351 * indicate failure.
352 */
353int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
354 int (*fn)(struct voltagedomain *voltdm,
355 struct powerdomain *pwrdm))
356{
357 struct powerdomain *pwrdm;
358 int ret = 0;
359
360 if (!fn)
361 return -EINVAL;
362
363 list_for_each_entry(pwrdm, &voltdm->pwrdm_list, voltdm_node)
364 ret = (*fn)(voltdm, pwrdm);
365
366 return ret;
367}
368
369/**
370 * voltdm_for_each - call function on each registered voltagedomain
371 * @fn: callback function *
372 *
373 * Call the supplied function @fn for each registered voltagedomain.
374 * The callback function @fn can return anything but 0 to bail out
375 * early from the iterator. Returns the last return value of the
376 * callback function, which should be 0 for success or anything else
377 * to indicate failure; or -EINVAL if the function pointer is null.
378 */
379int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
380 void *user)
381{
382 struct voltagedomain *temp_voltdm;
383 int ret = 0;
384
385 if (!fn)
386 return -EINVAL;
387
388 list_for_each_entry(temp_voltdm, &voltdm_list, node) {
389 ret = (*fn)(temp_voltdm, user);
390 if (ret)
391 break;
392 }
393
394 return ret;
395}
396
397static int _voltdm_register(struct voltagedomain *voltdm) 288static int _voltdm_register(struct voltagedomain *voltdm)
398{ 289{
399 if (!voltdm || !voltdm->name) 290 if (!voltdm || !voltdm->name)
400 return -EINVAL; 291 return -EINVAL;
401 292
402 INIT_LIST_HEAD(&voltdm->pwrdm_list);
403 list_add(&voltdm->node, &voltdm_list); 293 list_add(&voltdm->node, &voltdm_list);
404 294
405 pr_debug("voltagedomain: registered %s\n", voltdm->name); 295 pr_debug("voltagedomain: registered %s\n", voltdm->name);
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index f7f2879b31b0..e64550321510 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -23,10 +23,6 @@
23 23
24struct powerdomain; 24struct powerdomain;
25 25
26/* XXX document */
27#define VOLTSCALE_VPFORCEUPDATE 1
28#define VOLTSCALE_VCBYPASS 2
29
30/* 26/*
31 * OMAP3 GENERIC setup times. Revisit to see if these needs to be 27 * OMAP3 GENERIC setup times. Revisit to see if these needs to be
32 * passed from board or PMIC file 28 * passed from board or PMIC file
@@ -55,7 +51,6 @@ struct omap_vfsm_instance {
55 * @name: Name of the voltage domain which can be used as a unique identifier. 51 * @name: Name of the voltage domain which can be used as a unique identifier.
56 * @scalable: Whether or not this voltage domain is scalable 52 * @scalable: Whether or not this voltage domain is scalable
57 * @node: list_head linking all voltage domains 53 * @node: list_head linking all voltage domains
58 * @pwrdm_list: list_head linking all powerdomains in this voltagedomain
59 * @vc: pointer to VC channel associated with this voltagedomain 54 * @vc: pointer to VC channel associated with this voltagedomain
60 * @vp: pointer to VP associated with this voltagedomain 55 * @vp: pointer to VP associated with this voltagedomain
61 * @read: read a VC/VP register 56 * @read: read a VC/VP register
@@ -71,7 +66,6 @@ struct voltagedomain {
71 char *name; 66 char *name;
72 bool scalable; 67 bool scalable;
73 struct list_head node; 68 struct list_head node;
74 struct list_head pwrdm_list;
75 struct omap_vc_channel *vc; 69 struct omap_vc_channel *vc;
76 const struct omap_vfsm_instance *vfsm; 70 const struct omap_vfsm_instance *vfsm;
77 struct omap_vp_instance *vp; 71 struct omap_vp_instance *vp;
@@ -163,8 +157,6 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
163 unsigned long volt); 157 unsigned long volt);
164int omap_voltage_register_pmic(struct voltagedomain *voltdm, 158int omap_voltage_register_pmic(struct voltagedomain *voltdm,
165 struct omap_voltdm_pmic *pmic); 159 struct omap_voltdm_pmic *pmic);
166void omap_change_voltscale_method(struct voltagedomain *voltdm,
167 int voltscale_method);
168int omap_voltage_late_init(void); 160int omap_voltage_late_init(void);
169 161
170extern void omap2xxx_voltagedomains_init(void); 162extern void omap2xxx_voltagedomains_init(void);
@@ -175,11 +167,6 @@ extern void omap54xx_voltagedomains_init(void);
175struct voltagedomain *voltdm_lookup(const char *name); 167struct voltagedomain *voltdm_lookup(const char *name);
176void voltdm_init(struct voltagedomain **voltdm_list); 168void voltdm_init(struct voltagedomain **voltdm_list);
177int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm); 169int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm);
178int voltdm_for_each(int (*fn)(struct voltagedomain *voltdm, void *user),
179 void *user);
180int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
181 int (*fn)(struct voltagedomain *voltdm,
182 struct powerdomain *pwrdm));
183int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt); 170int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
184void voltdm_reset(struct voltagedomain *voltdm); 171void voltdm_reset(struct voltagedomain *voltdm);
185unsigned long voltdm_get_voltage(struct voltagedomain *voltdm); 172unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 07d3e5ed9264..3916a6665100 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -15,9 +15,6 @@
15#include <asm/mach/time.h> 15#include <asm/mach/time.h>
16#include <asm/exception.h> 16#include <asm/exception.h>
17 17
18#define SIRFSOC_VA_BASE _AC(0xFEC00000, UL)
19#define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
20
21extern struct smp_operations sirfsoc_smp_ops; 18extern struct smp_operations sirfsoc_smp_ops;
22extern void sirfsoc_secondary_startup(void); 19extern void sirfsoc_secondary_startup(void);
23extern void sirfsoc_cpu_die(unsigned int cpu); 20extern void sirfsoc_cpu_die(unsigned int cpu);
@@ -25,18 +22,6 @@ extern void sirfsoc_cpu_die(unsigned int cpu);
25extern void __init sirfsoc_of_irq_init(void); 22extern void __init sirfsoc_of_irq_init(void);
26extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs); 23extern asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs);
27 24
28#ifndef CONFIG_DEBUG_LL
29static inline void sirfsoc_map_lluart(void) {}
30#else
31extern void __init sirfsoc_map_lluart(void);
32#endif
33
34#ifndef CONFIG_SMP
35static inline void sirfsoc_map_scu(void) {}
36#else
37extern void sirfsoc_map_scu(void);
38#endif
39
40#ifdef CONFIG_SUSPEND 25#ifdef CONFIG_SUSPEND
41extern int sirfsoc_pm_init(void); 26extern int sirfsoc_pm_init(void);
42#else 27#else
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index ac7b3eabbd85..35434662dc7c 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -40,7 +40,7 @@ static struct resource pxa_resource_pmu = {
40}; 40};
41 41
42struct platform_device pxa_device_pmu = { 42struct platform_device pxa_device_pmu = {
43 .name = "arm-pmu", 43 .name = "xscale-pmu",
44 .id = -1, 44 .id = -1,
45 .resource = &pxa_resource_pmu, 45 .resource = &pxa_resource_pmu,
46 .num_resources = 1, 46 .num_resources = 1,
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 739d4f113097..64c88d657f9e 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -37,6 +37,7 @@
37#include <asm/pgtable.h> 37#include <asm/pgtable.h>
38#include <asm/hardware/cache-l2x0.h> 38#include <asm/hardware/cache-l2x0.h>
39#include <asm/smp_twd.h> 39#include <asm/smp_twd.h>
40#include <asm/system_info.h>
40 41
41#include <asm/mach/arch.h> 42#include <asm/mach/arch.h>
42#include <asm/mach/map.h> 43#include <asm/mach/map.h>
@@ -296,7 +297,6 @@ static struct resource pmu_resources[] = {
296}; 297};
297 298
298static struct platform_device pmu_device = { 299static struct platform_device pmu_device = {
299 .name = "arm-pmu",
300 .id = -1, 300 .id = -1,
301 .num_resources = ARRAY_SIZE(pmu_resources), 301 .num_resources = ARRAY_SIZE(pmu_resources),
302 .resource = pmu_resources, 302 .resource = pmu_resources,
@@ -451,6 +451,7 @@ static void __init realview_eb_init(void)
451 */ 451 */
452 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff); 452 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
453#endif 453#endif
454 pmu_device.name = core_tile_a9mp() ? "armv7-pmu" : "armv6-pmu";
454 platform_device_register(&pmu_device); 455 platform_device_register(&pmu_device);
455 } 456 }
456 457
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b0e0dcaed944..ce92c1823494 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -280,7 +280,7 @@ static struct resource pmu_resource = {
280}; 280};
281 281
282static struct platform_device pmu_device = { 282static struct platform_device pmu_device = {
283 .name = "arm-pmu", 283 .name = "armv6-pmu",
284 .id = -1, 284 .id = -1,
285 .num_resources = 1, 285 .num_resources = 1,
286 .resource = &pmu_resource, 286 .resource = &pmu_resource,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 47bf55fdbf27..15c45e25095f 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -262,7 +262,7 @@ static struct resource pmu_resources[] = {
262}; 262};
263 263
264static struct platform_device pmu_device = { 264static struct platform_device pmu_device = {
265 .name = "arm-pmu", 265 .name = "armv6-pmu",
266 .id = -1, 266 .id = -1,
267 .num_resources = ARRAY_SIZE(pmu_resources), 267 .num_resources = ARRAY_SIZE(pmu_resources),
268 .resource = pmu_resources, 268 .resource = pmu_resources,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 4e57a8599265..4c64662f5437 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -240,7 +240,7 @@ static struct resource pmu_resource = {
240}; 240};
241 241
242static struct platform_device pmu_device = { 242static struct platform_device pmu_device = {
243 .name = "arm-pmu", 243 .name = "armv7-pmu",
244 .id = -1, 244 .id = -1,
245 .num_resources = 1, 245 .num_resources = 1,
246 .resource = &pmu_resource, 246 .resource = &pmu_resource,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index d89eb4023467..9a22b864219f 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -280,7 +280,7 @@ static struct resource pmu_resources[] = {
280}; 280};
281 281
282static struct platform_device pmu_device = { 282static struct platform_device pmu_device = {
283 .name = "arm-pmu", 283 .name = "armv7-pmu",
284 .id = -1, 284 .id = -1,
285 .num_resources = ARRAY_SIZE(pmu_resources), 285 .num_resources = ARRAY_SIZE(pmu_resources),
286 .resource = pmu_resources, 286 .resource = pmu_resources,
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 9eb22297cbe1..79c49ff77f6e 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -29,7 +29,6 @@ config CPU_S3C2410
29 default y 29 default y
30 select CPU_ARM920T 30 select CPU_ARM920T
31 select S3C2410_COMMON_CLK 31 select S3C2410_COMMON_CLK
32 select S3C2410_DMA if S3C24XX_DMA
33 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ 32 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
34 select S3C2410_PM if PM 33 select S3C2410_PM if PM
35 help 34 help
@@ -40,7 +39,6 @@ config CPU_S3C2412
40 bool "SAMSUNG S3C2412" 39 bool "SAMSUNG S3C2412"
41 select CPU_ARM926T 40 select CPU_ARM926T
42 select S3C2412_COMMON_CLK 41 select S3C2412_COMMON_CLK
43 select S3C2412_DMA if S3C24XX_DMA
44 select S3C2412_PM if PM 42 select S3C2412_PM if PM
45 help 43 help
46 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line 44 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
@@ -50,7 +48,6 @@ config CPU_S3C2416
50 select CPU_ARM926T 48 select CPU_ARM926T
51 select S3C2416_PM if PM 49 select S3C2416_PM if PM
52 select S3C2443_COMMON_CLK 50 select S3C2443_COMMON_CLK
53 select S3C2443_DMA if S3C24XX_DMA
54 help 51 help
55 Support for the S3C2416 SoC from the S3C24XX line 52 Support for the S3C2416 SoC from the S3C24XX line
56 53
@@ -59,7 +56,6 @@ config CPU_S3C2440
59 select CPU_ARM920T 56 select CPU_ARM920T
60 select S3C2410_COMMON_CLK 57 select S3C2410_COMMON_CLK
61 select S3C2410_PM if PM 58 select S3C2410_PM if PM
62 select S3C2440_DMA if S3C24XX_DMA
63 help 59 help
64 Support for S3C2440 Samsung Mobile CPU based systems. 60 Support for S3C2440 Samsung Mobile CPU based systems.
65 61
@@ -67,7 +63,6 @@ config CPU_S3C2442
67 bool "SAMSUNG S3C2442" 63 bool "SAMSUNG S3C2442"
68 select CPU_ARM920T 64 select CPU_ARM920T
69 select S3C2410_COMMON_CLK 65 select S3C2410_COMMON_CLK
70 select S3C2410_DMA if S3C24XX_DMA
71 select S3C2410_PM if PM 66 select S3C2410_PM if PM
72 help 67 help
73 Support for S3C2442 Samsung Mobile CPU based systems. 68 Support for S3C2442 Samsung Mobile CPU based systems.
@@ -80,7 +75,6 @@ config CPU_S3C2443
80 bool "SAMSUNG S3C2443" 75 bool "SAMSUNG S3C2443"
81 select CPU_ARM920T 76 select CPU_ARM920T
82 select S3C2443_COMMON_CLK 77 select S3C2443_COMMON_CLK
83 select S3C2443_DMA if S3C24XX_DMA
84 help 78 help
85 Support for the S3C2443 SoC from the S3C24XX line 79 Support for the S3C2443 SoC from the S3C24XX line
86 80
@@ -114,27 +108,6 @@ config S3C24XX_SETUP_TS
114 help 108 help
115 Compile in platform device definition for Samsung TouchScreen. 109 Compile in platform device definition for Samsung TouchScreen.
116 110
117config S3C24XX_DMA
118 bool "S3C2410 DMA support (deprecated)"
119 select S3C_DMA
120 help
121 S3C2410 DMA support. This is needed for drivers like sound which
122 use the S3C2410's DMA system to move data to and from the
123 peripheral blocks.
124
125config S3C2410_DMA_DEBUG
126 bool "S3C2410 DMA support debug"
127 depends on S3C2410_DMA
128 help
129 Enable debugging output for the DMA code. This option sends info
130 to the kernel log, at priority KERN_DEBUG.
131
132config S3C2410_DMA
133 bool
134 depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
135 help
136 DMA device selection for S3C2410 and compatible CPUs
137
138config S3C2410_PM 111config S3C2410_PM
139 bool 112 bool
140 help 113 help
@@ -325,11 +298,6 @@ config CPU_S3C2412_ONLY
325 !CPU_S3C2442 && !CPU_S3C2443 298 !CPU_S3C2442 && !CPU_S3C2443
326 default y 299 default y
327 300
328config S3C2412_DMA
329 bool
330 help
331 Internal config node for S3C2412 DMA support
332
333config S3C2412_PM 301config S3C2412_PM
334 bool 302 bool
335 select S3C2412_PM_SLEEP 303 select S3C2412_PM_SLEEP
@@ -438,11 +406,6 @@ endif # CPU_S3C2416
438 406
439if CPU_S3C2440 407if CPU_S3C2440
440 408
441config S3C2440_DMA
442 bool
443 help
444 Support for S3C2440 specific DMA code5A
445
446config S3C2440_XTAL_12000000 409config S3C2440_XTAL_12000000
447 bool 410 bool
448 help 411 help
@@ -601,11 +564,6 @@ endif # CPU_S3C2442
601 564
602if CPU_S3C2443 || CPU_S3C2416 565if CPU_S3C2443 || CPU_S3C2416
603 566
604config S3C2443_DMA
605 bool
606 help
607 Internal config node for S3C2443 DMA support
608
609config S3C2443_SETUP_SPI 567config S3C2443_SETUP_SPI
610 bool 568 bool
611 help 569 help
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index b92071638733..b40a22fe082a 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -12,12 +12,10 @@
12obj-y += common.o 12obj-y += common.o
13 13
14obj-$(CONFIG_CPU_S3C2410) += s3c2410.o 14obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
15obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o
16obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o 15obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
17obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o 16obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
18 17
19obj-$(CONFIG_CPU_S3C2412) += s3c2412.o 18obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
20obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
21obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o 19obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
22obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o 20obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
23 21
@@ -27,7 +25,6 @@ obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
27obj-$(CONFIG_CPU_S3C2440) += s3c2440.o 25obj-$(CONFIG_CPU_S3C2440) += s3c2440.o
28obj-$(CONFIG_CPU_S3C2442) += s3c2442.o 26obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
29obj-$(CONFIG_CPU_S3C244X) += s3c244x.o 27obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
30obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o
31obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o 28obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
32obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o 29obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
33 30
@@ -39,15 +36,11 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
39 36
40# common code 37# common code
41 38
42obj-$(CONFIG_S3C24XX_DMA) += dma.o
43
44obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o 39obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
45 40
46obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o 41obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
47obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o 42obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
48 43
49obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o
50
51# 44#
52# machine support 45# machine support
53# following is ordered alphabetically by option text. 46# following is ordered alphabetically by option text.
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
deleted file mode 100644
index 09aa12da1789..000000000000
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ /dev/null
@@ -1,182 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/serial_core.h>
19#include <linux/serial_s3c.h>
20
21#include <mach/map.h>
22#include <mach/dma.h>
23
24#include <plat/cpu.h>
25#include <plat/dma-s3c24xx.h>
26
27#include <mach/regs-gpio.h>
28#include <plat/regs-dma.h>
29#include <mach/regs-lcd.h>
30#include <plat/regs-spi.h>
31
32static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
33 [DMACH_XD0] = {
34 .name = "xdreq0",
35 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
36 },
37 [DMACH_XD1] = {
38 .name = "xdreq1",
39 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
40 },
41 [DMACH_SDI] = {
42 .name = "sdi",
43 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
44 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
45 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
46 },
47 [DMACH_SPI0] = {
48 .name = "spi0",
49 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
50 },
51 [DMACH_SPI1] = {
52 .name = "spi1",
53 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
54 },
55 [DMACH_UART0] = {
56 .name = "uart0",
57 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
58 },
59 [DMACH_UART1] = {
60 .name = "uart1",
61 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
62 },
63 [DMACH_UART2] = {
64 .name = "uart2",
65 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
66 },
67 [DMACH_TIMER] = {
68 .name = "timer",
69 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
70 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
71 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
72 },
73 [DMACH_I2S_IN] = {
74 .name = "i2s-sdi",
75 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
76 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
77 },
78 [DMACH_I2S_OUT] = {
79 .name = "i2s-sdo",
80 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
81 },
82 [DMACH_USB_EP1] = {
83 .name = "usb-ep1",
84 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
85 },
86 [DMACH_USB_EP2] = {
87 .name = "usb-ep2",
88 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
89 },
90 [DMACH_USB_EP3] = {
91 .name = "usb-ep3",
92 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
93 },
94 [DMACH_USB_EP4] = {
95 .name = "usb-ep4",
96 .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
97 },
98};
99
100static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
101 struct s3c24xx_dma_map *map)
102{
103 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
104}
105
106static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
107 .select = s3c2410_dma_select,
108 .dcon_mask = 7 << 24,
109 .map = s3c2410_dma_mappings,
110 .map_size = ARRAY_SIZE(s3c2410_dma_mappings),
111};
112
113static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
114 .channels = {
115 [DMACH_SDI] = {
116 .list = {
117 [0] = 3 | DMA_CH_VALID,
118 [1] = 2 | DMA_CH_VALID,
119 [2] = 0 | DMA_CH_VALID,
120 },
121 },
122 [DMACH_I2S_IN] = {
123 .list = {
124 [0] = 1 | DMA_CH_VALID,
125 [1] = 2 | DMA_CH_VALID,
126 },
127 },
128 },
129};
130
131static int __init s3c2410_dma_add(struct device *dev,
132 struct subsys_interface *sif)
133{
134 s3c2410_dma_init();
135 s3c24xx_dma_order_set(&s3c2410_dma_order);
136 return s3c24xx_dma_init_map(&s3c2410_dma_sel);
137}
138
139#if defined(CONFIG_CPU_S3C2410)
140static struct subsys_interface s3c2410_dma_interface = {
141 .name = "s3c2410_dma",
142 .subsys = &s3c2410_subsys,
143 .add_dev = s3c2410_dma_add,
144};
145
146static int __init s3c2410_dma_drvinit(void)
147{
148 return subsys_interface_register(&s3c2410_dma_interface);
149}
150
151arch_initcall(s3c2410_dma_drvinit);
152
153static struct subsys_interface s3c2410a_dma_interface = {
154 .name = "s3c2410a_dma",
155 .subsys = &s3c2410a_subsys,
156 .add_dev = s3c2410_dma_add,
157};
158
159static int __init s3c2410a_dma_drvinit(void)
160{
161 return subsys_interface_register(&s3c2410a_dma_interface);
162}
163
164arch_initcall(s3c2410a_dma_drvinit);
165#endif
166
167#if defined(CONFIG_CPU_S3C2442)
168/* S3C2442 DMA contains the same selection table as the S3C2410 */
169static struct subsys_interface s3c2442_dma_interface = {
170 .name = "s3c2442_dma",
171 .subsys = &s3c2442_subsys,
172 .add_dev = s3c2410_dma_add,
173};
174
175static int __init s3c2442_dma_drvinit(void)
176{
177 return subsys_interface_register(&s3c2442_dma_interface);
178}
179
180arch_initcall(s3c2442_dma_drvinit);
181#endif
182
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
deleted file mode 100644
index 0c0106d1a4d1..000000000000
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ /dev/null
@@ -1,150 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/serial_core.h>
19#include <linux/serial_s3c.h>
20#include <linux/io.h>
21
22#include <mach/dma.h>
23
24#include <plat/dma-s3c24xx.h>
25#include <plat/cpu.h>
26
27#include <mach/regs-gpio.h>
28#include <plat/regs-dma.h>
29#include <mach/regs-lcd.h>
30#include <plat/regs-spi.h>
31
32#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
33
34static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
35 [DMACH_XD0] = {
36 .name = "xdreq0",
37 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
38 },
39 [DMACH_XD1] = {
40 .name = "xdreq1",
41 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
42 },
43 [DMACH_SDI] = {
44 .name = "sdi",
45 .channels = MAP(S3C2412_DMAREQSEL_SDI),
46 },
47 [DMACH_SPI0_RX] = {
48 .name = "spi0-rx",
49 .channels = MAP(S3C2412_DMAREQSEL_SPI0RX),
50 },
51 [DMACH_SPI0_TX] = {
52 .name = "spi0-tx",
53 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
54 },
55 [DMACH_SPI1_RX] = {
56 .name = "spi1-rx",
57 .channels = MAP(S3C2412_DMAREQSEL_SPI1RX),
58 },
59 [DMACH_SPI1_TX] = {
60 .name = "spi1-tx",
61 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
62 },
63 [DMACH_UART0] = {
64 .name = "uart0",
65 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
66 },
67 [DMACH_UART1] = {
68 .name = "uart1",
69 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
70 },
71 [DMACH_UART2] = {
72 .name = "uart2",
73 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
74 },
75 [DMACH_UART0_SRC2] = {
76 .name = "uart0",
77 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
78 },
79 [DMACH_UART1_SRC2] = {
80 .name = "uart1",
81 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
82 },
83 [DMACH_UART2_SRC2] = {
84 .name = "uart2",
85 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
86 },
87 [DMACH_TIMER] = {
88 .name = "timer",
89 .channels = MAP(S3C2412_DMAREQSEL_TIMER),
90 },
91 [DMACH_I2S_IN] = {
92 .name = "i2s-sdi",
93 .channels = MAP(S3C2412_DMAREQSEL_I2SRX),
94 },
95 [DMACH_I2S_OUT] = {
96 .name = "i2s-sdo",
97 .channels = MAP(S3C2412_DMAREQSEL_I2STX),
98 },
99 [DMACH_USB_EP1] = {
100 .name = "usb-ep1",
101 .channels = MAP(S3C2412_DMAREQSEL_USBEP1),
102 },
103 [DMACH_USB_EP2] = {
104 .name = "usb-ep2",
105 .channels = MAP(S3C2412_DMAREQSEL_USBEP2),
106 },
107 [DMACH_USB_EP3] = {
108 .name = "usb-ep3",
109 .channels = MAP(S3C2412_DMAREQSEL_USBEP3),
110 },
111 [DMACH_USB_EP4] = {
112 .name = "usb-ep4",
113 .channels = MAP(S3C2412_DMAREQSEL_USBEP4),
114 },
115};
116
117static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
118 struct s3c24xx_dma_map *map)
119{
120 unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
121 writel(chsel | S3C2412_DMAREQSEL_HW,
122 chan->regs + S3C2412_DMA_DMAREQSEL);
123}
124
125static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
126 .select = s3c2412_dma_select,
127 .dcon_mask = 0,
128 .map = s3c2412_dma_mappings,
129 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
130};
131
132static int __init s3c2412_dma_add(struct device *dev,
133 struct subsys_interface *sif)
134{
135 s3c2410_dma_init();
136 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
137}
138
139static struct subsys_interface s3c2412_dma_interface = {
140 .name = "s3c2412_dma",
141 .subsys = &s3c2412_subsys,
142 .add_dev = s3c2412_dma_add,
143};
144
145static int __init s3c2412_dma_init(void)
146{
147 return subsys_interface_register(&s3c2412_dma_interface);
148}
149
150arch_initcall(s3c2412_dma_init);
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
deleted file mode 100644
index 2f8e8a3017df..000000000000
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ /dev/null
@@ -1,193 +0,0 @@
1/* linux/arch/arm/mach-s3c2440/dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2440 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/serial_core.h>
19#include <linux/serial_s3c.h>
20
21#include <mach/map.h>
22#include <mach/dma.h>
23
24#include <plat/dma-s3c24xx.h>
25#include <plat/cpu.h>
26
27#include <mach/regs-gpio.h>
28#include <plat/regs-dma.h>
29#include <mach/regs-lcd.h>
30#include <plat/regs-spi.h>
31
32static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
33 [DMACH_XD0] = {
34 .name = "xdreq0",
35 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
36 },
37 [DMACH_XD1] = {
38 .name = "xdreq1",
39 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
40 },
41 [DMACH_SDI] = {
42 .name = "sdi",
43 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
44 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
45 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
46 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
47 },
48 [DMACH_SPI0] = {
49 .name = "spi0",
50 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
51 },
52 [DMACH_SPI1] = {
53 .name = "spi1",
54 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
55 },
56 [DMACH_UART0] = {
57 .name = "uart0",
58 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
59 },
60 [DMACH_UART1] = {
61 .name = "uart1",
62 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
63 },
64 [DMACH_UART2] = {
65 .name = "uart2",
66 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
67 },
68 [DMACH_TIMER] = {
69 .name = "timer",
70 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
71 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
72 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
73 },
74 [DMACH_I2S_IN] = {
75 .name = "i2s-sdi",
76 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
77 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
78 },
79 [DMACH_I2S_OUT] = {
80 .name = "i2s-sdo",
81 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
82 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
83 },
84 [DMACH_PCM_IN] = {
85 .name = "pcm-in",
86 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
87 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
88 },
89 [DMACH_PCM_OUT] = {
90 .name = "pcm-out",
91 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
92 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
93 },
94 [DMACH_MIC_IN] = {
95 .name = "mic-in",
96 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
97 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
98 },
99 [DMACH_USB_EP1] = {
100 .name = "usb-ep1",
101 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
102 },
103 [DMACH_USB_EP2] = {
104 .name = "usb-ep2",
105 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
106 },
107 [DMACH_USB_EP3] = {
108 .name = "usb-ep3",
109 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
110 },
111 [DMACH_USB_EP4] = {
112 .name = "usb-ep4",
113 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
114 },
115};
116
117static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
118 struct s3c24xx_dma_map *map)
119{
120 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
121}
122
123static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
124 .select = s3c2440_dma_select,
125 .dcon_mask = 7 << 24,
126 .map = s3c2440_dma_mappings,
127 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
128};
129
130static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
131 .channels = {
132 [DMACH_SDI] = {
133 .list = {
134 [0] = 3 | DMA_CH_VALID,
135 [1] = 2 | DMA_CH_VALID,
136 [2] = 1 | DMA_CH_VALID,
137 [3] = 0 | DMA_CH_VALID,
138 },
139 },
140 [DMACH_I2S_IN] = {
141 .list = {
142 [0] = 1 | DMA_CH_VALID,
143 [1] = 2 | DMA_CH_VALID,
144 },
145 },
146 [DMACH_I2S_OUT] = {
147 .list = {
148 [0] = 2 | DMA_CH_VALID,
149 [1] = 1 | DMA_CH_VALID,
150 },
151 },
152 [DMACH_PCM_IN] = {
153 .list = {
154 [0] = 2 | DMA_CH_VALID,
155 [1] = 1 | DMA_CH_VALID,
156 },
157 },
158 [DMACH_PCM_OUT] = {
159 .list = {
160 [0] = 1 | DMA_CH_VALID,
161 [1] = 3 | DMA_CH_VALID,
162 },
163 },
164 [DMACH_MIC_IN] = {
165 .list = {
166 [0] = 3 | DMA_CH_VALID,
167 [1] = 2 | DMA_CH_VALID,
168 },
169 },
170 },
171};
172
173static int __init s3c2440_dma_add(struct device *dev,
174 struct subsys_interface *sif)
175{
176 s3c2410_dma_init();
177 s3c24xx_dma_order_set(&s3c2440_dma_order);
178 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
179}
180
181static struct subsys_interface s3c2440_dma_interface = {
182 .name = "s3c2440_dma",
183 .subsys = &s3c2440_subsys,
184 .add_dev = s3c2440_dma_add,
185};
186
187static int __init s3c2440_dma_init(void)
188{
189 return subsys_interface_register(&s3c2440_dma_interface);
190}
191
192arch_initcall(s3c2440_dma_init);
193
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
deleted file mode 100644
index f4096ec0700a..000000000000
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ /dev/null
@@ -1,179 +0,0 @@
1/* linux/arch/arm/mach-s3c2443/dma.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/serial_core.h>
19#include <linux/serial_s3c.h>
20#include <linux/io.h>
21
22#include <mach/dma.h>
23
24#include <plat/dma-s3c24xx.h>
25#include <plat/cpu.h>
26
27#include <mach/regs-gpio.h>
28#include <plat/regs-dma.h>
29#include <mach/regs-lcd.h>
30#include <plat/regs-spi.h>
31
32#define MAP(x) { \
33 [0] = (x) | DMA_CH_VALID, \
34 [1] = (x) | DMA_CH_VALID, \
35 [2] = (x) | DMA_CH_VALID, \
36 [3] = (x) | DMA_CH_VALID, \
37 [4] = (x) | DMA_CH_VALID, \
38 [5] = (x) | DMA_CH_VALID, \
39 }
40
41static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
42 [DMACH_XD0] = {
43 .name = "xdreq0",
44 .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
45 },
46 [DMACH_XD1] = {
47 .name = "xdreq1",
48 .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
49 },
50 [DMACH_SDI] = { /* only on S3C2443 */
51 .name = "sdi",
52 .channels = MAP(S3C2443_DMAREQSEL_SDI),
53 },
54 [DMACH_SPI0_RX] = {
55 .name = "spi0-rx",
56 .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
57 },
58 [DMACH_SPI0_TX] = {
59 .name = "spi0-tx",
60 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
61 },
62 [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
63 .name = "spi1-rx",
64 .channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
65 },
66 [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
67 .name = "spi1-tx",
68 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
69 },
70 [DMACH_UART0] = {
71 .name = "uart0",
72 .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
73 },
74 [DMACH_UART1] = {
75 .name = "uart1",
76 .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
77 },
78 [DMACH_UART2] = {
79 .name = "uart2",
80 .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
81 },
82 [DMACH_UART3] = {
83 .name = "uart3",
84 .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
85 },
86 [DMACH_UART0_SRC2] = {
87 .name = "uart0",
88 .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
89 },
90 [DMACH_UART1_SRC2] = {
91 .name = "uart1",
92 .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
93 },
94 [DMACH_UART2_SRC2] = {
95 .name = "uart2",
96 .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
97 },
98 [DMACH_UART3_SRC2] = {
99 .name = "uart3",
100 .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
101 },
102 [DMACH_TIMER] = {
103 .name = "timer",
104 .channels = MAP(S3C2443_DMAREQSEL_TIMER),
105 },
106 [DMACH_I2S_IN] = {
107 .name = "i2s-sdi",
108 .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
109 },
110 [DMACH_I2S_OUT] = {
111 .name = "i2s-sdo",
112 .channels = MAP(S3C2443_DMAREQSEL_I2STX),
113 },
114 [DMACH_PCM_IN] = {
115 .name = "pcm-in",
116 .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
117 },
118 [DMACH_PCM_OUT] = {
119 .name = "pcm-out",
120 .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
121 },
122 [DMACH_MIC_IN] = {
123 .name = "mic-in",
124 .channels = MAP(S3C2443_DMAREQSEL_MICIN),
125 },
126};
127
128static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
129 struct s3c24xx_dma_map *map)
130{
131 unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
132 writel(chsel | S3C2443_DMAREQSEL_HW,
133 chan->regs + S3C2443_DMA_DMAREQSEL);
134}
135
136static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
137 .select = s3c2443_dma_select,
138 .dcon_mask = 0,
139 .map = s3c2443_dma_mappings,
140 .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
141};
142
143static int __init s3c2443_dma_add(struct device *dev,
144 struct subsys_interface *sif)
145{
146 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
147 return s3c24xx_dma_init_map(&s3c2443_dma_sel);
148}
149
150#ifdef CONFIG_CPU_S3C2416
151/* S3C2416 DMA contains the same selection table as the S3C2443 */
152static struct subsys_interface s3c2416_dma_interface = {
153 .name = "s3c2416_dma",
154 .subsys = &s3c2416_subsys,
155 .add_dev = s3c2443_dma_add,
156};
157
158static int __init s3c2416_dma_init(void)
159{
160 return subsys_interface_register(&s3c2416_dma_interface);
161}
162
163arch_initcall(s3c2416_dma_init);
164#endif
165
166#ifdef CONFIG_CPU_S3C2443
167static struct subsys_interface s3c2443_dma_interface = {
168 .name = "s3c2443_dma",
169 .subsys = &s3c2443_subsys,
170 .add_dev = s3c2443_dma_add,
171};
172
173static int __init s3c2443_dma_init(void)
174{
175 return subsys_interface_register(&s3c2443_dma_interface);
176}
177
178arch_initcall(s3c2443_dma_init);
179#endif
diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
deleted file mode 100644
index a8dafc174fe3..000000000000
--- a/arch/arm/mach-s3c24xx/dma.c
+++ /dev/null
@@ -1,1465 +0,0 @@
1/*
2 * Copyright 2003-2006 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 *
5 * S3C2410 DMA core
6 *
7 * http://armlinux.simtec.co.uk/
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14
15#ifdef CONFIG_S3C2410_DMA_DEBUG
16#define DEBUG
17#endif
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/syscore_ops.h>
25#include <linux/slab.h>
26#include <linux/errno.h>
27#include <linux/io.h>
28
29#include <asm/irq.h>
30#include <mach/hardware.h>
31#include <mach/dma.h>
32#include <mach/map.h>
33
34#include <plat/dma-s3c24xx.h>
35#include <plat/regs-dma.h>
36
37/* io map for dma */
38static void __iomem *dma_base;
39static struct kmem_cache *dma_kmem;
40
41static int dma_channels;
42
43static struct s3c24xx_dma_selection dma_sel;
44
45
46/* debugging functions */
47
48#define BUF_MAGIC (0xcafebabe)
49
50#define dmawarn(fmt...) printk(KERN_DEBUG fmt)
51
52#define dma_regaddr(chan, reg) ((chan)->regs + (reg))
53
54#if 1
55#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
56#else
57static inline void
58dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
59{
60 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
61 writel(val, dma_regaddr(chan, reg));
62}
63#endif
64
65#define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
66
67/* captured register state for debug */
68
69struct s3c2410_dma_regstate {
70 unsigned long dcsrc;
71 unsigned long disrc;
72 unsigned long dstat;
73 unsigned long dcon;
74 unsigned long dmsktrig;
75};
76
77#ifdef CONFIG_S3C2410_DMA_DEBUG
78
79/* dmadbg_showregs
80 *
81 * simple debug routine to print the current state of the dma registers
82*/
83
84static void
85dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
86{
87 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
88 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
89 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
90 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
91 regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
92}
93
94static void
95dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
96 struct s3c2410_dma_regstate *regs)
97{
98 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
99 chan->number, fname, line,
100 regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
101 regs->dcon);
102}
103
104static void
105dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
106{
107 struct s3c2410_dma_regstate state;
108
109 dmadbg_capture(chan, &state);
110
111 printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
112 chan->number, fname, line, chan->load_state,
113 chan->curr, chan->next, chan->end);
114
115 dmadbg_dumpregs(fname, line, chan, &state);
116}
117
118static void
119dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
120{
121 struct s3c2410_dma_regstate state;
122
123 dmadbg_capture(chan, &state);
124 dmadbg_dumpregs(fname, line, chan, &state);
125}
126
127#define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
128#define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
129#else
130#define dbg_showregs(chan) do { } while(0)
131#define dbg_showchan(chan) do { } while(0)
132#endif /* CONFIG_S3C2410_DMA_DEBUG */
133
134/* s3c2410_dma_stats_timeout
135 *
136 * Update DMA stats from timeout info
137*/
138
139static void
140s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
141{
142 if (stats == NULL)
143 return;
144
145 if (val > stats->timeout_longest)
146 stats->timeout_longest = val;
147 if (val < stats->timeout_shortest)
148 stats->timeout_shortest = val;
149
150 stats->timeout_avg += val;
151}
152
153/* s3c2410_dma_waitforload
154 *
155 * wait for the DMA engine to load a buffer, and update the state accordingly
156*/
157
158static int
159s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
160{
161 int timeout = chan->load_timeout;
162 int took;
163
164 if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
165 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
166 return 0;
167 }
168
169 if (chan->stats != NULL)
170 chan->stats->loads++;
171
172 while (--timeout > 0) {
173 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
174 took = chan->load_timeout - timeout;
175
176 s3c2410_dma_stats_timeout(chan->stats, took);
177
178 switch (chan->load_state) {
179 case S3C2410_DMALOAD_1LOADED:
180 chan->load_state = S3C2410_DMALOAD_1RUNNING;
181 break;
182
183 default:
184 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
185 }
186
187 return 1;
188 }
189 }
190
191 if (chan->stats != NULL) {
192 chan->stats->timeout_failed++;
193 }
194
195 return 0;
196}
197
198/* s3c2410_dma_loadbuffer
199 *
200 * load a buffer, and update the channel state
201*/
202
203static inline int
204s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
205 struct s3c2410_dma_buf *buf)
206{
207 unsigned long reload;
208
209 if (buf == NULL) {
210 dmawarn("buffer is NULL\n");
211 return -EINVAL;
212 }
213
214 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
215 buf, (unsigned long)buf->data, buf->size);
216
217 /* check the state of the channel before we do anything */
218
219 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
220 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
221 }
222
223 if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
224 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
225 }
226
227 /* it would seem sensible if we are the last buffer to not bother
228 * with the auto-reload bit, so that the DMA engine will not try
229 * and load another transfer after this one has finished...
230 */
231 if (chan->load_state == S3C2410_DMALOAD_NONE) {
232 pr_debug("load_state is none, checking for noreload (next=%p)\n",
233 buf->next);
234 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
235 } else {
236 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
237 reload = S3C2410_DCON_AUTORELOAD;
238 }
239
240 if ((buf->data & 0xf0000000) != 0x30000000) {
241 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
242 }
243
244 writel(buf->data, chan->addr_reg);
245
246 dma_wrreg(chan, S3C2410_DMA_DCON,
247 chan->dcon | reload | (buf->size/chan->xfer_unit));
248
249 chan->next = buf->next;
250
251 /* update the state of the channel */
252
253 switch (chan->load_state) {
254 case S3C2410_DMALOAD_NONE:
255 chan->load_state = S3C2410_DMALOAD_1LOADED;
256 break;
257
258 case S3C2410_DMALOAD_1RUNNING:
259 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
260 break;
261
262 default:
263 dmawarn("dmaload: unknown state %d in loadbuffer\n",
264 chan->load_state);
265 break;
266 }
267
268 return 0;
269}
270
271/* s3c2410_dma_call_op
272 *
273 * small routine to call the op routine with the given op if it has been
274 * registered
275*/
276
277static void
278s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
279{
280 if (chan->op_fn != NULL) {
281 (chan->op_fn)(chan, op);
282 }
283}
284
285/* s3c2410_dma_buffdone
286 *
287 * small wrapper to check if callback routine needs to be called, and
288 * if so, call it
289*/
290
291static inline void
292s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
293 enum s3c2410_dma_buffresult result)
294{
295#if 0
296 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
297 chan->callback_fn, buf, buf->id, buf->size, result);
298#endif
299
300 if (chan->callback_fn != NULL) {
301 (chan->callback_fn)(chan, buf->id, buf->size, result);
302 }
303}
304
305/* s3c2410_dma_start
306 *
307 * start a dma channel going
308*/
309
310static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
311{
312 unsigned long tmp;
313 unsigned long flags;
314
315 pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
316
317 local_irq_save(flags);
318
319 if (chan->state == S3C2410_DMA_RUNNING) {
320 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
321 local_irq_restore(flags);
322 return 0;
323 }
324
325 chan->state = S3C2410_DMA_RUNNING;
326
327 /* check whether there is anything to load, and if not, see
328 * if we can find anything to load
329 */
330
331 if (chan->load_state == S3C2410_DMALOAD_NONE) {
332 if (chan->next == NULL) {
333 printk(KERN_ERR "dma%d: channel has nothing loaded\n",
334 chan->number);
335 chan->state = S3C2410_DMA_IDLE;
336 local_irq_restore(flags);
337 return -EINVAL;
338 }
339
340 s3c2410_dma_loadbuffer(chan, chan->next);
341 }
342
343 dbg_showchan(chan);
344
345 /* enable the channel */
346
347 if (!chan->irq_enabled) {
348 enable_irq(chan->irq);
349 chan->irq_enabled = 1;
350 }
351
352 /* start the channel going */
353
354 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
355 tmp &= ~S3C2410_DMASKTRIG_STOP;
356 tmp |= S3C2410_DMASKTRIG_ON;
357 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
358
359 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
360
361#if 0
362 /* the dma buffer loads should take care of clearing the AUTO
363 * reloading feature */
364 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
365 tmp &= ~S3C2410_DCON_NORELOAD;
366 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
367#endif
368
369 s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
370
371 dbg_showchan(chan);
372
373 /* if we've only loaded one buffer onto the channel, then chec
374 * to see if we have another, and if so, try and load it so when
375 * the first buffer is finished, the new one will be loaded onto
376 * the channel */
377
378 if (chan->next != NULL) {
379 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
380
381 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
382 pr_debug("%s: buff not yet loaded, no more todo\n",
383 __func__);
384 } else {
385 chan->load_state = S3C2410_DMALOAD_1RUNNING;
386 s3c2410_dma_loadbuffer(chan, chan->next);
387 }
388
389 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
390 s3c2410_dma_loadbuffer(chan, chan->next);
391 }
392 }
393
394
395 local_irq_restore(flags);
396
397 return 0;
398}
399
400/* s3c2410_dma_canload
401 *
402 * work out if we can queue another buffer into the DMA engine
403*/
404
405static int
406s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
407{
408 if (chan->load_state == S3C2410_DMALOAD_NONE ||
409 chan->load_state == S3C2410_DMALOAD_1RUNNING)
410 return 1;
411
412 return 0;
413}
414
415/* s3c2410_dma_enqueue
416 *
417 * queue an given buffer for dma transfer.
418 *
419 * id the device driver's id information for this buffer
420 * data the physical address of the buffer data
421 * size the size of the buffer in bytes
422 *
423 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
424 * is checked, and if set, the channel is started. If this flag isn't set,
425 * then an error will be returned.
426 *
427 * It is possible to queue more than one DMA buffer onto a channel at
428 * once, and the code will deal with the re-loading of the next buffer
429 * when necessary.
430*/
431
432int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
433 dma_addr_t data, int size)
434{
435 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
436 struct s3c2410_dma_buf *buf;
437 unsigned long flags;
438
439 if (chan == NULL)
440 return -EINVAL;
441
442 pr_debug("%s: id=%p, data=%08x, size=%d\n",
443 __func__, id, (unsigned int)data, size);
444
445 buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
446 if (buf == NULL) {
447 pr_debug("%s: out of memory (%ld alloc)\n",
448 __func__, (long)sizeof(*buf));
449 return -ENOMEM;
450 }
451
452 //pr_debug("%s: new buffer %p\n", __func__, buf);
453 //dbg_showchan(chan);
454
455 buf->next = NULL;
456 buf->data = buf->ptr = data;
457 buf->size = size;
458 buf->id = id;
459 buf->magic = BUF_MAGIC;
460
461 local_irq_save(flags);
462
463 if (chan->curr == NULL) {
464 /* we've got nothing loaded... */
465 pr_debug("%s: buffer %p queued onto empty channel\n",
466 __func__, buf);
467
468 chan->curr = buf;
469 chan->end = buf;
470 chan->next = NULL;
471 } else {
472 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
473 chan->number, __func__, buf);
474
475 if (chan->end == NULL) {
476 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
477 chan->number, __func__, chan);
478 } else {
479 chan->end->next = buf;
480 chan->end = buf;
481 }
482 }
483
484 /* if necessary, update the next buffer field */
485 if (chan->next == NULL)
486 chan->next = buf;
487
488 /* check to see if we can load a buffer */
489 if (chan->state == S3C2410_DMA_RUNNING) {
490 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
491 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
492 printk(KERN_ERR "dma%d: loadbuffer:"
493 "timeout loading buffer\n",
494 chan->number);
495 dbg_showchan(chan);
496 local_irq_restore(flags);
497 return -EINVAL;
498 }
499 }
500
501 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
502 s3c2410_dma_loadbuffer(chan, chan->next);
503 }
504 } else if (chan->state == S3C2410_DMA_IDLE) {
505 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
506 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
507 S3C2410_DMAOP_START);
508 }
509 }
510
511 local_irq_restore(flags);
512 return 0;
513}
514
515EXPORT_SYMBOL(s3c2410_dma_enqueue);
516
517static inline void
518s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
519{
520 int magicok = (buf->magic == BUF_MAGIC);
521
522 buf->magic = -1;
523
524 if (magicok) {
525 kmem_cache_free(dma_kmem, buf);
526 } else {
527 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
528 }
529}
530
531/* s3c2410_dma_lastxfer
532 *
533 * called when the system is out of buffers, to ensure that the channel
534 * is prepared for shutdown.
535*/
536
537static inline void
538s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
539{
540#if 0
541 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
542 chan->number, chan->load_state);
543#endif
544
545 switch (chan->load_state) {
546 case S3C2410_DMALOAD_NONE:
547 break;
548
549 case S3C2410_DMALOAD_1LOADED:
550 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
551 /* flag error? */
552 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
553 chan->number, __func__);
554 return;
555 }
556 break;
557
558 case S3C2410_DMALOAD_1LOADED_1RUNNING:
559 /* I believe in this case we do not have anything to do
560 * until the next buffer comes along, and we turn off the
561 * reload */
562 return;
563
564 default:
565 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
566 chan->number, chan->load_state);
567 return;
568
569 }
570
571 /* hopefully this'll shut the damned thing up after the transfer... */
572 dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
573}
574
575
576#define dmadbg2(x...)
577
578static irqreturn_t
579s3c2410_dma_irq(int irq, void *devpw)
580{
581 struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
582 struct s3c2410_dma_buf *buf;
583
584 buf = chan->curr;
585
586 dbg_showchan(chan);
587
588 /* modify the channel state */
589
590 switch (chan->load_state) {
591 case S3C2410_DMALOAD_1RUNNING:
592 /* TODO - if we are running only one buffer, we probably
593 * want to reload here, and then worry about the buffer
594 * callback */
595
596 chan->load_state = S3C2410_DMALOAD_NONE;
597 break;
598
599 case S3C2410_DMALOAD_1LOADED:
600 /* iirc, we should go back to NONE loaded here, we
601 * had a buffer, and it was never verified as being
602 * loaded.
603 */
604
605 chan->load_state = S3C2410_DMALOAD_NONE;
606 break;
607
608 case S3C2410_DMALOAD_1LOADED_1RUNNING:
609 /* we'll worry about checking to see if another buffer is
610 * ready after we've called back the owner. This should
611 * ensure we do not wait around too long for the DMA
612 * engine to start the next transfer
613 */
614
615 chan->load_state = S3C2410_DMALOAD_1LOADED;
616 break;
617
618 case S3C2410_DMALOAD_NONE:
619 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
620 chan->number);
621 break;
622
623 default:
624 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
625 chan->number, chan->load_state);
626 break;
627 }
628
629 if (buf != NULL) {
630 /* update the chain to make sure that if we load any more
631 * buffers when we call the callback function, things should
632 * work properly */
633
634 chan->curr = buf->next;
635 buf->next = NULL;
636
637 if (buf->magic != BUF_MAGIC) {
638 printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
639 chan->number, __func__, buf);
640 return IRQ_HANDLED;
641 }
642
643 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
644
645 /* free resouces */
646 s3c2410_dma_freebuf(buf);
647 } else {
648 }
649
650 /* only reload if the channel is still running... our buffer done
651 * routine may have altered the state by requesting the dma channel
652 * to stop or shutdown... */
653
654 /* todo: check that when the channel is shut-down from inside this
655 * function, we cope with unsetting reload, etc */
656
657 if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
658 unsigned long flags;
659
660 switch (chan->load_state) {
661 case S3C2410_DMALOAD_1RUNNING:
662 /* don't need to do anything for this state */
663 break;
664
665 case S3C2410_DMALOAD_NONE:
666 /* can load buffer immediately */
667 break;
668
669 case S3C2410_DMALOAD_1LOADED:
670 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
671 /* flag error? */
672 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
673 chan->number, __func__);
674 return IRQ_HANDLED;
675 }
676
677 break;
678
679 case S3C2410_DMALOAD_1LOADED_1RUNNING:
680 goto no_load;
681
682 default:
683 printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
684 chan->number, chan->load_state);
685 return IRQ_HANDLED;
686 }
687
688 local_irq_save(flags);
689 s3c2410_dma_loadbuffer(chan, chan->next);
690 local_irq_restore(flags);
691 } else {
692 s3c2410_dma_lastxfer(chan);
693
694 /* see if we can stop this channel.. */
695 if (chan->load_state == S3C2410_DMALOAD_NONE) {
696 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
697 chan->number, jiffies);
698 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
699 S3C2410_DMAOP_STOP);
700 }
701 }
702
703 no_load:
704 return IRQ_HANDLED;
705}
706
707static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
708
709/* s3c2410_request_dma
710 *
711 * get control of an dma channel
712*/
713
714int s3c2410_dma_request(enum dma_ch channel,
715 struct s3c2410_dma_client *client,
716 void *dev)
717{
718 struct s3c2410_dma_chan *chan;
719 unsigned long flags;
720 int err;
721
722 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
723 channel, client->name, dev);
724
725 local_irq_save(flags);
726
727 chan = s3c2410_dma_map_channel(channel);
728 if (chan == NULL) {
729 local_irq_restore(flags);
730 return -EBUSY;
731 }
732
733 dbg_showchan(chan);
734
735 chan->client = client;
736 chan->in_use = 1;
737
738 if (!chan->irq_claimed) {
739 pr_debug("dma%d: %s : requesting irq %d\n",
740 channel, __func__, chan->irq);
741
742 chan->irq_claimed = 1;
743 local_irq_restore(flags);
744
745 err = request_irq(chan->irq, s3c2410_dma_irq, 0,
746 client->name, (void *)chan);
747
748 local_irq_save(flags);
749
750 if (err) {
751 chan->in_use = 0;
752 chan->irq_claimed = 0;
753 local_irq_restore(flags);
754
755 printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
756 client->name, chan->irq, chan->number);
757 return err;
758 }
759
760 chan->irq_enabled = 1;
761 }
762
763 local_irq_restore(flags);
764
765 /* need to setup */
766
767 pr_debug("%s: channel initialised, %p\n", __func__, chan);
768
769 return chan->number | DMACH_LOW_LEVEL;
770}
771
772EXPORT_SYMBOL(s3c2410_dma_request);
773
774/* s3c2410_dma_free
775 *
776 * release the given channel back to the system, will stop and flush
777 * any outstanding transfers, and ensure the channel is ready for the
778 * next claimant.
779 *
780 * Note, although a warning is currently printed if the freeing client
781 * info is not the same as the registrant's client info, the free is still
782 * allowed to go through.
783*/
784
785int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client)
786{
787 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
788 unsigned long flags;
789
790 if (chan == NULL)
791 return -EINVAL;
792
793 local_irq_save(flags);
794
795 if (chan->client != client) {
796 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
797 channel, chan->client, client);
798 }
799
800 /* sort out stopping and freeing the channel */
801
802 if (chan->state != S3C2410_DMA_IDLE) {
803 pr_debug("%s: need to stop dma channel %p\n",
804 __func__, chan);
805
806 /* possibly flush the channel */
807 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
808 }
809
810 chan->client = NULL;
811 chan->in_use = 0;
812
813 if (chan->irq_claimed)
814 free_irq(chan->irq, (void *)chan);
815
816 chan->irq_claimed = 0;
817
818 if (!(channel & DMACH_LOW_LEVEL))
819 s3c_dma_chan_map[channel] = NULL;
820
821 local_irq_restore(flags);
822
823 return 0;
824}
825
826EXPORT_SYMBOL(s3c2410_dma_free);
827
828static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
829{
830 unsigned long flags;
831 unsigned long tmp;
832
833 pr_debug("%s:\n", __func__);
834
835 dbg_showchan(chan);
836
837 local_irq_save(flags);
838
839 s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
840
841 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
842 tmp |= S3C2410_DMASKTRIG_STOP;
843 //tmp &= ~S3C2410_DMASKTRIG_ON;
844 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
845
846#if 0
847 /* should also clear interrupts, according to WinCE BSP */
848 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
849 tmp |= S3C2410_DCON_NORELOAD;
850 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
851#endif
852
853 /* should stop do this, or should we wait for flush? */
854 chan->state = S3C2410_DMA_IDLE;
855 chan->load_state = S3C2410_DMALOAD_NONE;
856
857 local_irq_restore(flags);
858
859 return 0;
860}
861
862static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
863{
864 unsigned long tmp;
865 unsigned int timeout = 0x10000;
866
867 while (timeout-- > 0) {
868 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
869
870 if (!(tmp & S3C2410_DMASKTRIG_ON))
871 return;
872 }
873
874 pr_debug("dma%d: failed to stop?\n", chan->number);
875}
876
877
878/* s3c2410_dma_flush
879 *
880 * stop the channel, and remove all current and pending transfers
881*/
882
883static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
884{
885 struct s3c2410_dma_buf *buf, *next;
886 unsigned long flags;
887
888 pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
889
890 dbg_showchan(chan);
891
892 local_irq_save(flags);
893
894 if (chan->state != S3C2410_DMA_IDLE) {
895 pr_debug("%s: stopping channel...\n", __func__ );
896 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
897 }
898
899 buf = chan->curr;
900 if (buf == NULL)
901 buf = chan->next;
902
903 chan->curr = chan->next = chan->end = NULL;
904
905 if (buf != NULL) {
906 for ( ; buf != NULL; buf = next) {
907 next = buf->next;
908
909 pr_debug("%s: free buffer %p, next %p\n",
910 __func__, buf, buf->next);
911
912 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
913 s3c2410_dma_freebuf(buf);
914 }
915 }
916
917 dbg_showregs(chan);
918
919 s3c2410_dma_waitforstop(chan);
920
921#if 0
922 /* should also clear interrupts, according to WinCE BSP */
923 {
924 unsigned long tmp;
925
926 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
927 tmp |= S3C2410_DCON_NORELOAD;
928 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
929 }
930#endif
931
932 dbg_showregs(chan);
933
934 local_irq_restore(flags);
935
936 return 0;
937}
938
939static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
940{
941 unsigned long flags;
942
943 local_irq_save(flags);
944
945 dbg_showchan(chan);
946
947 /* if we've only loaded one buffer onto the channel, then chec
948 * to see if we have another, and if so, try and load it so when
949 * the first buffer is finished, the new one will be loaded onto
950 * the channel */
951
952 if (chan->next != NULL) {
953 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
954
955 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
956 pr_debug("%s: buff not yet loaded, no more todo\n",
957 __func__);
958 } else {
959 chan->load_state = S3C2410_DMALOAD_1RUNNING;
960 s3c2410_dma_loadbuffer(chan, chan->next);
961 }
962
963 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
964 s3c2410_dma_loadbuffer(chan, chan->next);
965 }
966 }
967
968
969 local_irq_restore(flags);
970
971 return 0;
972
973}
974
975int
976s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op)
977{
978 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
979
980 if (chan == NULL)
981 return -EINVAL;
982
983 switch (op) {
984 case S3C2410_DMAOP_START:
985 return s3c2410_dma_start(chan);
986
987 case S3C2410_DMAOP_STOP:
988 return s3c2410_dma_dostop(chan);
989
990 case S3C2410_DMAOP_PAUSE:
991 case S3C2410_DMAOP_RESUME:
992 return -ENOENT;
993
994 case S3C2410_DMAOP_FLUSH:
995 return s3c2410_dma_flush(chan);
996
997 case S3C2410_DMAOP_STARTED:
998 return s3c2410_dma_started(chan);
999
1000 case S3C2410_DMAOP_TIMEOUT:
1001 return 0;
1002
1003 }
1004
1005 return -ENOENT; /* unknown, don't bother */
1006}
1007
1008EXPORT_SYMBOL(s3c2410_dma_ctrl);
1009
1010/* DMA configuration for each channel
1011 *
1012 * DISRCC -> source of the DMA (AHB,APB)
1013 * DISRC -> source address of the DMA
1014 * DIDSTC -> destination of the DMA (AHB,APD)
1015 * DIDST -> destination address of the DMA
1016*/
1017
1018/* s3c2410_dma_config
1019 *
1020 * xfersize: size of unit in bytes (1,2,4)
1021*/
1022
1023int s3c2410_dma_config(enum dma_ch channel,
1024 int xferunit)
1025{
1026 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1027 unsigned int dcon;
1028
1029 pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit);
1030
1031 if (chan == NULL)
1032 return -EINVAL;
1033
1034 dcon = chan->dcon & dma_sel.dcon_mask;
1035 pr_debug("%s: dcon is %08x\n", __func__, dcon);
1036
1037 switch (chan->req_ch) {
1038 case DMACH_I2S_IN:
1039 case DMACH_I2S_OUT:
1040 case DMACH_PCM_IN:
1041 case DMACH_PCM_OUT:
1042 case DMACH_MIC_IN:
1043 default:
1044 dcon |= S3C2410_DCON_HANDSHAKE;
1045 dcon |= S3C2410_DCON_SYNC_PCLK;
1046 break;
1047
1048 case DMACH_SDI:
1049 /* note, ensure if need HANDSHAKE or not */
1050 dcon |= S3C2410_DCON_SYNC_PCLK;
1051 break;
1052
1053 case DMACH_XD0:
1054 case DMACH_XD1:
1055 dcon |= S3C2410_DCON_HANDSHAKE;
1056 dcon |= S3C2410_DCON_SYNC_HCLK;
1057 break;
1058 }
1059
1060 switch (xferunit) {
1061 case 1:
1062 dcon |= S3C2410_DCON_BYTE;
1063 break;
1064
1065 case 2:
1066 dcon |= S3C2410_DCON_HALFWORD;
1067 break;
1068
1069 case 4:
1070 dcon |= S3C2410_DCON_WORD;
1071 break;
1072
1073 default:
1074 pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
1075 return -EINVAL;
1076 }
1077
1078 dcon |= S3C2410_DCON_HWTRIG;
1079 dcon |= S3C2410_DCON_INTREQ;
1080
1081 pr_debug("%s: dcon now %08x\n", __func__, dcon);
1082
1083 chan->dcon = dcon;
1084 chan->xfer_unit = xferunit;
1085
1086 return 0;
1087}
1088
1089EXPORT_SYMBOL(s3c2410_dma_config);
1090
1091
1092/* s3c2410_dma_devconfig
1093 *
1094 * configure the dma source/destination hardware type and address
1095 *
1096 * source: DMA_FROM_DEVICE: source is hardware
1097 * DMA_TO_DEVICE: source is memory
1098 *
1099 * devaddr: physical address of the source
1100*/
1101
1102int s3c2410_dma_devconfig(enum dma_ch channel,
1103 enum dma_data_direction source,
1104 unsigned long devaddr)
1105{
1106 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1107 unsigned int hwcfg;
1108
1109 if (chan == NULL)
1110 return -EINVAL;
1111
1112 pr_debug("%s: source=%d, devaddr=%08lx\n",
1113 __func__, (int)source, devaddr);
1114
1115 chan->source = source;
1116 chan->dev_addr = devaddr;
1117
1118 switch (chan->req_ch) {
1119 case DMACH_XD0:
1120 case DMACH_XD1:
1121 hwcfg = 0; /* AHB */
1122 break;
1123
1124 default:
1125 hwcfg = S3C2410_DISRCC_APB;
1126 }
1127
1128 /* always assume our peripheral desintation is a fixed
1129 * address in memory. */
1130 hwcfg |= S3C2410_DISRCC_INC;
1131
1132 switch (source) {
1133 case DMA_FROM_DEVICE:
1134 /* source is hardware */
1135 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1136 __func__, devaddr, hwcfg);
1137 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1138 dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
1139 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1140
1141 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1142 break;
1143
1144 case DMA_TO_DEVICE:
1145 /* source is memory */
1146 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1147 __func__, devaddr, hwcfg);
1148 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1149 dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
1150 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1151
1152 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1153 break;
1154
1155 default:
1156 printk(KERN_ERR "dma%d: invalid source type (%d)\n",
1157 channel, source);
1158
1159 return -EINVAL;
1160 }
1161
1162 return 0;
1163}
1164
1165EXPORT_SYMBOL(s3c2410_dma_devconfig);
1166
1167/* s3c2410_dma_getposition
1168 *
1169 * returns the current transfer points for the dma source and destination
1170*/
1171
1172int s3c2410_dma_getposition(enum dma_ch channel, dma_addr_t *src, dma_addr_t *dst)
1173{
1174 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1175
1176 if (chan == NULL)
1177 return -EINVAL;
1178
1179 if (src != NULL)
1180 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1181
1182 if (dst != NULL)
1183 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1184
1185 return 0;
1186}
1187
1188EXPORT_SYMBOL(s3c2410_dma_getposition);
1189
1190/* system core operations */
1191
1192#ifdef CONFIG_PM
1193
1194static void s3c2410_dma_suspend_chan(struct s3c2410_dma_chan *cp)
1195{
1196 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1197
1198 if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1199 /* the dma channel is still working, which is probably
1200 * a bad thing to do over suspend/resume. We stop the
1201 * channel and assume that the client is either going to
1202 * retry after resume, or that it is broken.
1203 */
1204
1205 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1206 cp->number);
1207
1208 s3c2410_dma_dostop(cp);
1209 }
1210}
1211
1212static int s3c2410_dma_suspend(void)
1213{
1214 struct s3c2410_dma_chan *cp = s3c2410_chans;
1215 int channel;
1216
1217 for (channel = 0; channel < dma_channels; cp++, channel++)
1218 s3c2410_dma_suspend_chan(cp);
1219
1220 return 0;
1221}
1222
1223static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp)
1224{
1225 unsigned int no = cp->number | DMACH_LOW_LEVEL;
1226
1227 /* restore channel's hardware configuration */
1228
1229 if (!cp->in_use)
1230 return;
1231
1232 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1233
1234 s3c2410_dma_config(no, cp->xfer_unit);
1235 s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
1236
1237 /* re-select the dma source for this channel */
1238
1239 if (cp->map != NULL)
1240 dma_sel.select(cp, cp->map);
1241}
1242
1243static void s3c2410_dma_resume(void)
1244{
1245 struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
1246 int channel;
1247
1248 for (channel = dma_channels - 1; channel >= 0; cp--, channel--)
1249 s3c2410_dma_resume_chan(cp);
1250}
1251
1252#else
1253#define s3c2410_dma_suspend NULL
1254#define s3c2410_dma_resume NULL
1255#endif /* CONFIG_PM */
1256
1257struct syscore_ops dma_syscore_ops = {
1258 .suspend = s3c2410_dma_suspend,
1259 .resume = s3c2410_dma_resume,
1260};
1261
1262/* kmem cache implementation */
1263
1264static void s3c2410_dma_cache_ctor(void *p)
1265{
1266 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1267}
1268
1269/* initialisation code */
1270
1271static int __init s3c24xx_dma_syscore_init(void)
1272{
1273 register_syscore_ops(&dma_syscore_ops);
1274
1275 return 0;
1276}
1277
1278late_initcall(s3c24xx_dma_syscore_init);
1279
1280int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1281 unsigned int stride)
1282{
1283 struct s3c2410_dma_chan *cp;
1284 int channel;
1285 int ret;
1286
1287 printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
1288
1289 dma_channels = channels;
1290
1291 dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
1292 if (dma_base == NULL) {
1293 printk(KERN_ERR "dma failed to remap register block\n");
1294 return -ENOMEM;
1295 }
1296
1297 dma_kmem = kmem_cache_create("dma_desc",
1298 sizeof(struct s3c2410_dma_buf), 0,
1299 SLAB_HWCACHE_ALIGN,
1300 s3c2410_dma_cache_ctor);
1301
1302 if (dma_kmem == NULL) {
1303 printk(KERN_ERR "dma failed to make kmem cache\n");
1304 ret = -ENOMEM;
1305 goto err;
1306 }
1307
1308 for (channel = 0; channel < channels; channel++) {
1309 cp = &s3c2410_chans[channel];
1310
1311 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1312
1313 /* dma channel irqs are in order.. */
1314 cp->number = channel;
1315 cp->irq = channel + irq;
1316 cp->regs = dma_base + (channel * stride);
1317
1318 /* point current stats somewhere */
1319 cp->stats = &cp->stats_store;
1320 cp->stats_store.timeout_shortest = LONG_MAX;
1321
1322 /* basic channel configuration */
1323
1324 cp->load_timeout = 1<<18;
1325
1326 printk("DMA channel %d at %p, irq %d\n",
1327 cp->number, cp->regs, cp->irq);
1328 }
1329
1330 return 0;
1331
1332 err:
1333 kmem_cache_destroy(dma_kmem);
1334 iounmap(dma_base);
1335 dma_base = NULL;
1336 return ret;
1337}
1338
1339int __init s3c2410_dma_init(void)
1340{
1341 return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
1342}
1343
1344static inline int is_channel_valid(unsigned int channel)
1345{
1346 return (channel & DMA_CH_VALID);
1347}
1348
1349static struct s3c24xx_dma_order *dma_order;
1350
1351
1352/* s3c2410_dma_map_channel()
1353 *
1354 * turn the virtual channel number into a real, and un-used hardware
1355 * channel.
1356 *
1357 * first, try the dma ordering given to us by either the relevant
1358 * dma code, or the board. Then just find the first usable free
1359 * channel
1360*/
1361
1362static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1363{
1364 struct s3c24xx_dma_order_ch *ord = NULL;
1365 struct s3c24xx_dma_map *ch_map;
1366 struct s3c2410_dma_chan *dmach;
1367 int ch;
1368
1369 if (dma_sel.map == NULL || channel > dma_sel.map_size)
1370 return NULL;
1371
1372 ch_map = dma_sel.map + channel;
1373
1374 /* first, try the board mapping */
1375
1376 if (dma_order) {
1377 ord = &dma_order->channels[channel];
1378
1379 for (ch = 0; ch < dma_channels; ch++) {
1380 int tmp;
1381 if (!is_channel_valid(ord->list[ch]))
1382 continue;
1383
1384 tmp = ord->list[ch] & ~DMA_CH_VALID;
1385 if (s3c2410_chans[tmp].in_use == 0) {
1386 ch = tmp;
1387 goto found;
1388 }
1389 }
1390
1391 if (ord->flags & DMA_CH_NEVER)
1392 return NULL;
1393 }
1394
1395 /* second, search the channel map for first free */
1396
1397 for (ch = 0; ch < dma_channels; ch++) {
1398 if (!is_channel_valid(ch_map->channels[ch]))
1399 continue;
1400
1401 if (s3c2410_chans[ch].in_use == 0) {
1402 printk("mapped channel %d to %d\n", channel, ch);
1403 break;
1404 }
1405 }
1406
1407 if (ch >= dma_channels)
1408 return NULL;
1409
1410 /* update our channel mapping */
1411
1412 found:
1413 dmach = &s3c2410_chans[ch];
1414 dmach->map = ch_map;
1415 dmach->req_ch = channel;
1416 s3c_dma_chan_map[channel] = dmach;
1417
1418 /* select the channel */
1419
1420 (dma_sel.select)(dmach, ch_map);
1421
1422 return dmach;
1423}
1424
1425static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1426{
1427 return 0;
1428}
1429
1430int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1431{
1432 struct s3c24xx_dma_map *nmap;
1433 size_t map_sz = sizeof(*nmap) * sel->map_size;
1434 int ptr;
1435
1436 nmap = kmemdup(sel->map, map_sz, GFP_KERNEL);
1437 if (nmap == NULL)
1438 return -ENOMEM;
1439
1440 memcpy(&dma_sel, sel, sizeof(*sel));
1441
1442 dma_sel.map = nmap;
1443
1444 for (ptr = 0; ptr < sel->map_size; ptr++)
1445 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1446
1447 return 0;
1448}
1449
1450int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
1451{
1452 struct s3c24xx_dma_order *nord = dma_order;
1453
1454 if (nord == NULL)
1455 nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
1456
1457 if (nord == NULL) {
1458 printk(KERN_ERR "no memory to store dma channel order\n");
1459 return -ENOMEM;
1460 }
1461
1462 dma_order = nord;
1463 memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
1464 return 0;
1465}
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index b55da1d8cd8f..9e8117198e0c 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -15,8 +15,6 @@
15 15
16#include <linux/device.h> 16#include <linux/device.h>
17 17
18#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
19
20/* We use `virtual` dma channels to hide the fact we have only a limited 18/* We use `virtual` dma channels to hide the fact we have only a limited
21 * number of DMA channels, and not of all of them (dependent on the device) 19 * number of DMA channels, and not of all of them (dependent on the device)
22 * can be attached to any DMA source. We therefore let the DMA core handle 20 * can be attached to any DMA source. We therefore let the DMA core handle
@@ -54,161 +52,4 @@ enum dma_ch {
54 DMACH_MAX, /* the end entry */ 52 DMACH_MAX, /* the end entry */
55}; 53};
56 54
57static inline bool samsung_dma_has_circular(void)
58{
59 return false;
60}
61
62static inline bool samsung_dma_is_dmadev(void)
63{
64 return false;
65}
66
67#include <plat/dma.h>
68
69#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
70
71/* we have 4 dma channels */
72#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
73#define S3C_DMA_CHANNELS (4)
74#else
75#define S3C_DMA_CHANNELS (6)
76#endif
77
78/* types */
79
80enum s3c2410_dma_state {
81 S3C2410_DMA_IDLE,
82 S3C2410_DMA_RUNNING,
83 S3C2410_DMA_PAUSED
84};
85
86/* enum s3c2410_dma_loadst
87 *
88 * This represents the state of the DMA engine, wrt to the loaded / running
89 * transfers. Since we don't have any way of knowing exactly the state of
90 * the DMA transfers, we need to know the state to make decisions on whether
91 * we can
92 *
93 * S3C2410_DMA_NONE
94 *
95 * There are no buffers loaded (the channel should be inactive)
96 *
97 * S3C2410_DMA_1LOADED
98 *
99 * There is one buffer loaded, however it has not been confirmed to be
100 * loaded by the DMA engine. This may be because the channel is not
101 * yet running, or the DMA driver decided that it was too costly to
102 * sit and wait for it to happen.
103 *
104 * S3C2410_DMA_1RUNNING
105 *
106 * The buffer has been confirmed running, and not finisged
107 *
108 * S3C2410_DMA_1LOADED_1RUNNING
109 *
110 * There is a buffer waiting to be loaded by the DMA engine, and one
111 * currently running.
112*/
113
114enum s3c2410_dma_loadst {
115 S3C2410_DMALOAD_NONE,
116 S3C2410_DMALOAD_1LOADED,
117 S3C2410_DMALOAD_1RUNNING,
118 S3C2410_DMALOAD_1LOADED_1RUNNING,
119};
120
121
122/* flags */
123
124#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
125 * waiting for reloads */
126#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
127
128#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
129
130/* dma buffer */
131
132struct s3c2410_dma_buf;
133
134/* s3c2410_dma_buf
135 *
136 * internally used buffer structure to describe a queued or running
137 * buffer.
138*/
139
140struct s3c2410_dma_buf {
141 struct s3c2410_dma_buf *next;
142 int magic; /* magic */
143 int size; /* buffer size in bytes */
144 dma_addr_t data; /* start of DMA data */
145 dma_addr_t ptr; /* where the DMA got to [1] */
146 void *id; /* client's id */
147};
148
149/* [1] is this updated for both recv/send modes? */
150
151struct s3c2410_dma_stats {
152 unsigned long loads;
153 unsigned long timeout_longest;
154 unsigned long timeout_shortest;
155 unsigned long timeout_avg;
156 unsigned long timeout_failed;
157};
158
159struct s3c2410_dma_map;
160
161/* struct s3c2410_dma_chan
162 *
163 * full state information for each DMA channel
164*/
165
166struct s3c2410_dma_chan {
167 /* channel state flags and information */
168 unsigned char number; /* number of this dma channel */
169 unsigned char in_use; /* channel allocated */
170 unsigned char irq_claimed; /* irq claimed for channel */
171 unsigned char irq_enabled; /* irq enabled for channel */
172 unsigned char xfer_unit; /* size of an transfer */
173
174 /* channel state */
175
176 enum s3c2410_dma_state state;
177 enum s3c2410_dma_loadst load_state;
178 struct s3c2410_dma_client *client;
179
180 /* channel configuration */
181 enum dma_data_direction source;
182 enum dma_ch req_ch;
183 unsigned long dev_addr;
184 unsigned long load_timeout;
185 unsigned int flags; /* channel flags */
186
187 struct s3c24xx_dma_map *map; /* channel hw maps */
188
189 /* channel's hardware position and configuration */
190 void __iomem *regs; /* channels registers */
191 void __iomem *addr_reg; /* data address register */
192 unsigned int irq; /* channel irq */
193 unsigned long dcon; /* default value of DCON */
194
195 /* driver handles */
196 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
197 s3c2410_dma_opfn_t op_fn; /* channel op callback */
198
199 /* stats gathering */
200 struct s3c2410_dma_stats *stats;
201 struct s3c2410_dma_stats stats_store;
202
203 /* buffer list and information */
204 struct s3c2410_dma_buf *curr; /* current dma buffer */
205 struct s3c2410_dma_buf *next; /* next buffer to load */
206 struct s3c2410_dma_buf *end; /* end of queue */
207
208 /* system device */
209 struct device dev;
210};
211
212typedef unsigned long dma_device_t;
213
214#endif /* __ASM_ARCH_DMA_H */ 55#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index 059b1fc85037..096e14073bd9 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -51,21 +51,6 @@ enum dma_ch {
51 DMACH_MAX = 32 51 DMACH_MAX = 32
52}; 52};
53 53
54struct s3c2410_dma_client {
55 char *name;
56};
57
58static inline bool samsung_dma_has_circular(void)
59{
60 return true;
61}
62
63static inline bool samsung_dma_is_dmadev(void)
64{
65 return true;
66}
67
68#include <linux/amba/pl08x.h> 54#include <linux/amba/pl08x.h>
69#include <plat/dma-ops.h>
70 55
71#endif /* __ASM_ARCH_IRQ_H */ 56#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1b4fafe524ff..bb3d07504d8b 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -74,11 +74,6 @@ config ARCH_R8A7794
74 74
75comment "Renesas ARM SoCs Board Type" 75comment "Renesas ARM SoCs Board Type"
76 76
77config MACH_LAGER
78 bool "Lager board"
79 depends on ARCH_R8A7790
80 select MICREL_PHY if SH_ETH
81
82config MACH_MARZEN 77config MACH_MARZEN
83 bool "MARZEN board" 78 bool "MARZEN board"
84 depends on ARCH_R8A7779 79 depends on ARCH_R8A7779
@@ -133,14 +128,6 @@ config ARCH_R8A7779
133 select ARCH_WANT_OPTIONAL_GPIOLIB 128 select ARCH_WANT_OPTIONAL_GPIOLIB
134 select ARM_GIC 129 select ARM_GIC
135 130
136config ARCH_R8A7790
137 bool "R-Car H2 (R8A77900)"
138 select ARCH_RCAR_GEN2
139 select ARCH_WANT_OPTIONAL_GPIOLIB
140 select ARM_GIC
141 select MIGHT_HAVE_PCI
142 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
143
144comment "Renesas ARM SoCs Board Type" 131comment "Renesas ARM SoCs Board Type"
145 132
146config MACH_APE6EVM 133config MACH_APE6EVM
@@ -208,13 +195,6 @@ config MACH_MARZEN
208 select REGULATOR_FIXED_VOLTAGE if REGULATOR 195 select REGULATOR_FIXED_VOLTAGE if REGULATOR
209 select USE_OF 196 select USE_OF
210 197
211config MACH_LAGER
212 bool "Lager board"
213 depends on ARCH_R8A7790
214 select USE_OF
215 select MICREL_PHY if SH_ETH
216 select SND_SOC_AK4642 if SND_SIMPLE_CARD
217
218config MACH_KZM9G 198config MACH_KZM9G
219 bool "KZM-A9-GT board" 199 bool "KZM-A9-GT board"
220 depends on ARCH_SH73A0 200 depends on ARCH_SH73A0
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index b55cac0e5b2b..d53996e6da97 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
27obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o 27obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
28obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o 28obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o 29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
30obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
31endif 30endif
32 31
33# CPU reset vector handling objects 32# CPU reset vector handling objects
@@ -57,7 +56,6 @@ obj-$(CONFIG_ARCH_SH7372) += entry-intc.o sleep-sh7372.o
57 56
58# Board objects 57# Board objects
59ifdef CONFIG_ARCH_SHMOBILE_MULTI 58ifdef CONFIG_ARCH_SHMOBILE_MULTI
60obj-$(CONFIG_MACH_LAGER) += board-lager-reference.o
61obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o 59obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
62else 60else
63obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o 61obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
@@ -66,7 +64,6 @@ obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
66obj-$(CONFIG_MACH_BOCKW) += board-bockw.o 64obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
67obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o 65obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
68obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 66obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
69obj-$(CONFIG_MACH_LAGER) += board-lager.o
70obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 67obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
71obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 68obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
72obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o 69obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 57d00ed6ec0c..02532bea5300 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -7,7 +7,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
7loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 7loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
8loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 8loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
9loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 9loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
10loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
11loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000 10loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
12loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 11loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
13 12
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
deleted file mode 100644
index fa06bdba61df..000000000000
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Lager board support - Reference DT implementation
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/init.h>
18#include <linux/of_platform.h>
19
20#include <asm/mach/arch.h>
21
22#include "common.h"
23#include "r8a7790.h"
24#include "rcar-gen2.h"
25
26static const char *lager_boards_compat_dt[] __initdata = {
27 "renesas,lager",
28 "renesas,lager-reference",
29 NULL,
30};
31
32DT_MACHINE_START(LAGER_DT, "lager")
33 .smp = smp_ops(r8a7790_smp_ops),
34 .init_early = shmobile_init_delay,
35 .init_time = rcar_gen2_timer_init,
36 .init_late = shmobile_init_late,
37 .reserve = rcar_gen2_reserve,
38 .dt_compat = lager_boards_compat_dt,
39MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
deleted file mode 100644
index 65b128dd4072..000000000000
--- a/arch/arm/mach-shmobile/board-lager.c
+++ /dev/null
@@ -1,840 +0,0 @@
1/*
2 * Lager board support
3 *
4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2014 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/gpio.h>
19#include <linux/gpio_keys.h>
20#include <linux/i2c.h>
21#include <linux/input.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/irqchip.h>
25#include <linux/irqchip/arm-gic.h>
26#include <linux/kernel.h>
27#include <linux/leds.h>
28#include <linux/mfd/tmio.h>
29#include <linux/mmc/host.h>
30#include <linux/mmc/sh_mmcif.h>
31#include <linux/mmc/sh_mobile_sdhi.h>
32#include <linux/mtd/partitions.h>
33#include <linux/mtd/mtd.h>
34#include <linux/pinctrl/machine.h>
35#include <linux/platform_data/camera-rcar.h>
36#include <linux/platform_data/gpio-rcar.h>
37#include <linux/platform_data/usb-rcar-gen2-phy.h>
38#include <linux/platform_device.h>
39#include <linux/phy.h>
40#include <linux/regulator/driver.h>
41#include <linux/regulator/fixed.h>
42#include <linux/regulator/gpio-regulator.h>
43#include <linux/regulator/machine.h>
44#include <linux/sh_eth.h>
45#include <linux/spi/flash.h>
46#include <linux/spi/rspi.h>
47#include <linux/spi/spi.h>
48#include <linux/usb/phy.h>
49#include <linux/usb/renesas_usbhs.h>
50
51#include <media/soc_camera.h>
52#include <asm/mach-types.h>
53#include <asm/mach/arch.h>
54#include <sound/rcar_snd.h>
55#include <sound/simple_card.h>
56
57#include "common.h"
58#include "irqs.h"
59#include "r8a7790.h"
60#include "rcar-gen2.h"
61
62/*
63 * SSI-AK4643
64 *
65 * SW1: 1: AK4643
66 * 2: CN22
67 * 3: ADV7511
68 *
69 * this command is required when playback.
70 *
71 * # amixer set "LINEOUT Mixer DACL" on
72 */
73
74/*
75 * SDHI0 (CN8)
76 *
77 * JP3: pin1
78 * SW20: pin1
79
80 * GP5_24: 1: VDD 3.3V (defult)
81 * 0: VDD 0.0V
82 * GP5_29: 1: VccQ 3.3V (defult)
83 * 0: VccQ 1.8V
84 *
85 */
86
87/* LEDS */
88static struct gpio_led lager_leds[] = {
89 {
90 .name = "led8",
91 .gpio = RCAR_GP_PIN(5, 17),
92 .default_state = LEDS_GPIO_DEFSTATE_ON,
93 }, {
94 .name = "led7",
95 .gpio = RCAR_GP_PIN(4, 23),
96 .default_state = LEDS_GPIO_DEFSTATE_ON,
97 }, {
98 .name = "led6",
99 .gpio = RCAR_GP_PIN(4, 22),
100 .default_state = LEDS_GPIO_DEFSTATE_ON,
101 },
102};
103
104static const struct gpio_led_platform_data lager_leds_pdata __initconst = {
105 .leds = lager_leds,
106 .num_leds = ARRAY_SIZE(lager_leds),
107};
108
109/* GPIO KEY */
110#define GPIO_KEY(c, g, d, ...) \
111 { .code = c, .gpio = g, .desc = d, .active_low = 1, \
112 .wakeup = 1, .debounce_interval = 20 }
113
114static struct gpio_keys_button gpio_buttons[] = {
115 GPIO_KEY(KEY_4, RCAR_GP_PIN(1, 28), "SW2-pin4"),
116 GPIO_KEY(KEY_3, RCAR_GP_PIN(1, 26), "SW2-pin3"),
117 GPIO_KEY(KEY_2, RCAR_GP_PIN(1, 24), "SW2-pin2"),
118 GPIO_KEY(KEY_1, RCAR_GP_PIN(1, 14), "SW2-pin1"),
119};
120
121static const struct gpio_keys_platform_data lager_keys_pdata __initconst = {
122 .buttons = gpio_buttons,
123 .nbuttons = ARRAY_SIZE(gpio_buttons),
124};
125
126/* Fixed 3.3V regulator to be used by MMCIF */
127static struct regulator_consumer_supply fixed3v3_power_consumers[] =
128{
129 REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"),
130};
131
132/*
133 * SDHI regulator macro
134 *
135 ** FIXME**
136 * Lager board vqmmc is provided via DA9063 PMIC chip,
137 * and we should use ${LINK}/drivers/mfd/da9063-* driver for it.
138 * but, it doesn't have regulator support at this point.
139 * It uses gpio-regulator for vqmmc as quick-hack.
140 */
141#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin) \
142static struct regulator_consumer_supply vcc_sdhi##idx##_consumer = \
143 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx); \
144 \
145static struct regulator_init_data vcc_sdhi##idx##_init_data = { \
146 .constraints = { \
147 .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
148 }, \
149 .consumer_supplies = &vcc_sdhi##idx##_consumer, \
150 .num_consumer_supplies = 1, \
151}; \
152 \
153static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
154 .supply_name = "SDHI" #idx "Vcc", \
155 .microvolts = 3300000, \
156 .gpio = vdd_pin, \
157 .enable_high = 1, \
158 .init_data = &vcc_sdhi##idx##_init_data, \
159}; \
160 \
161static struct regulator_consumer_supply vccq_sdhi##idx##_consumer = \
162 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx); \
163 \
164static struct regulator_init_data vccq_sdhi##idx##_init_data = { \
165 .constraints = { \
166 .input_uV = 3300000, \
167 .min_uV = 1800000, \
168 .max_uV = 3300000, \
169 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \
170 REGULATOR_CHANGE_STATUS, \
171 }, \
172 .consumer_supplies = &vccq_sdhi##idx##_consumer, \
173 .num_consumer_supplies = 1, \
174}; \
175 \
176static struct gpio vccq_sdhi##idx##_gpio = \
177 { vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx }; \
178 \
179static struct gpio_regulator_state vccq_sdhi##idx##_states[] = { \
180 { .value = 1800000, .gpios = 0 }, \
181 { .value = 3300000, .gpios = 1 }, \
182}; \
183 \
184static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
185 .supply_name = "vqmmc", \
186 .gpios = &vccq_sdhi##idx##_gpio, \
187 .nr_gpios = 1, \
188 .states = vccq_sdhi##idx##_states, \
189 .nr_states = ARRAY_SIZE(vccq_sdhi##idx##_states), \
190 .type = REGULATOR_VOLTAGE, \
191 .init_data = &vccq_sdhi##idx##_init_data, \
192};
193
194SDHI_REGULATOR(0, RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 29));
195SDHI_REGULATOR(2, RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 30));
196
197/* MMCIF */
198static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = {
199 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
200 .clk_ctrl2_present = true,
201 .ccs_unsupported = true,
202};
203
204static const struct resource mmcif1_resources[] __initconst = {
205 DEFINE_RES_MEM(0xee220000, 0x80),
206 DEFINE_RES_IRQ(gic_spi(170)),
207};
208
209/* Ether */
210static const struct sh_eth_plat_data ether_pdata __initconst = {
211 .phy = 0x1,
212 .phy_irq = irq_pin(0),
213 .edmac_endian = EDMAC_LITTLE_ENDIAN,
214 .phy_interface = PHY_INTERFACE_MODE_RMII,
215 .ether_link_active_low = 1,
216};
217
218static const struct resource ether_resources[] __initconst = {
219 DEFINE_RES_MEM(0xee700000, 0x400),
220 DEFINE_RES_IRQ(gic_spi(162)),
221};
222
223static const struct platform_device_info ether_info __initconst = {
224 .name = "r8a7790-ether",
225 .id = -1,
226 .res = ether_resources,
227 .num_res = ARRAY_SIZE(ether_resources),
228 .data = &ether_pdata,
229 .size_data = sizeof(ether_pdata),
230 .dma_mask = DMA_BIT_MASK(32),
231};
232
233/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */
234static struct mtd_partition spi_flash_part[] = {
235 /* Reserved for user loader program, read-only */
236 {
237 .name = "loader",
238 .offset = 0,
239 .size = SZ_256K,
240 .mask_flags = MTD_WRITEABLE,
241 },
242 /* Reserved for user program, read-only */
243 {
244 .name = "user",
245 .offset = MTDPART_OFS_APPEND,
246 .size = SZ_4M,
247 .mask_flags = MTD_WRITEABLE,
248 },
249 /* All else is writable (e.g. JFFS2) */
250 {
251 .name = "flash",
252 .offset = MTDPART_OFS_APPEND,
253 .size = MTDPART_SIZ_FULL,
254 .mask_flags = 0,
255 },
256};
257
258static const struct flash_platform_data spi_flash_data = {
259 .name = "m25p80",
260 .parts = spi_flash_part,
261 .nr_parts = ARRAY_SIZE(spi_flash_part),
262 .type = "s25fl512s",
263};
264
265static const struct rspi_plat_data qspi_pdata __initconst = {
266 .num_chipselect = 1,
267};
268
269static const struct spi_board_info spi_info[] __initconst = {
270 {
271 .modalias = "m25p80",
272 .platform_data = &spi_flash_data,
273 .mode = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
274 .max_speed_hz = 30000000,
275 .bus_num = 0,
276 .chip_select = 0,
277 },
278};
279
280/* QSPI resource */
281static const struct resource qspi_resources[] __initconst = {
282 DEFINE_RES_MEM(0xe6b10000, 0x1000),
283 DEFINE_RES_IRQ_NAMED(gic_spi(184), "mux"),
284};
285
286/* VIN */
287static const struct resource vin_resources[] __initconst = {
288 /* VIN0 */
289 DEFINE_RES_MEM(0xe6ef0000, 0x1000),
290 DEFINE_RES_IRQ(gic_spi(188)),
291 /* VIN1 */
292 DEFINE_RES_MEM(0xe6ef1000, 0x1000),
293 DEFINE_RES_IRQ(gic_spi(189)),
294};
295
296static void __init lager_add_vin_device(unsigned idx,
297 struct rcar_vin_platform_data *pdata)
298{
299 struct platform_device_info vin_info = {
300 .name = "r8a7790-vin",
301 .id = idx,
302 .res = &vin_resources[idx * 2],
303 .num_res = 2,
304 .dma_mask = DMA_BIT_MASK(32),
305 .data = pdata,
306 .size_data = sizeof(*pdata),
307 };
308
309 BUG_ON(idx > 1);
310
311 platform_device_register_full(&vin_info);
312}
313
314#define LAGER_CAMERA(idx, name, addr, pdata, flag) \
315static struct i2c_board_info i2c_cam##idx##_device = { \
316 I2C_BOARD_INFO(name, addr), \
317}; \
318 \
319static struct rcar_vin_platform_data vin##idx##_pdata = { \
320 .flags = flag, \
321}; \
322 \
323static struct soc_camera_link cam##idx##_link = { \
324 .bus_id = idx, \
325 .board_info = &i2c_cam##idx##_device, \
326 .i2c_adapter_id = 2, \
327 .module_name = name, \
328 .priv = pdata, \
329}
330
331/* Camera 0 is not currently supported due to adv7612 support missing */
332LAGER_CAMERA(1, "adv7180", 0x20, NULL, RCAR_VIN_BT656);
333
334static void __init lager_add_camera1_device(void)
335{
336 platform_device_register_data(NULL, "soc-camera-pdrv", 1,
337 &cam1_link, sizeof(cam1_link));
338 lager_add_vin_device(1, &vin1_pdata);
339}
340
341/* SATA1 */
342static const struct resource sata1_resources[] __initconst = {
343 DEFINE_RES_MEM(0xee500000, 0x2000),
344 DEFINE_RES_IRQ(gic_spi(106)),
345};
346
347static const struct platform_device_info sata1_info __initconst = {
348 .name = "sata-r8a7790",
349 .id = 1,
350 .res = sata1_resources,
351 .num_res = ARRAY_SIZE(sata1_resources),
352 .dma_mask = DMA_BIT_MASK(32),
353};
354
355/* USBHS */
356static const struct resource usbhs_resources[] __initconst = {
357 DEFINE_RES_MEM(0xe6590000, 0x100),
358 DEFINE_RES_IRQ(gic_spi(107)),
359};
360
361struct usbhs_private {
362 struct renesas_usbhs_platform_info info;
363 struct usb_phy *phy;
364};
365
366#define usbhs_get_priv(pdev) \
367 container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info)
368
369static int usbhs_power_ctrl(struct platform_device *pdev,
370 void __iomem *base, int enable)
371{
372 struct usbhs_private *priv = usbhs_get_priv(pdev);
373
374 if (!priv->phy)
375 return -ENODEV;
376
377 if (enable) {
378 int retval = usb_phy_init(priv->phy);
379
380 if (!retval)
381 retval = usb_phy_set_suspend(priv->phy, 0);
382 return retval;
383 }
384
385 usb_phy_set_suspend(priv->phy, 1);
386 usb_phy_shutdown(priv->phy);
387 return 0;
388}
389
390static int usbhs_hardware_init(struct platform_device *pdev)
391{
392 struct usbhs_private *priv = usbhs_get_priv(pdev);
393 struct usb_phy *phy;
394 int ret;
395
396 /* USB0 Function - use PWEN as GPIO input to detect DIP Switch SW5
397 * setting to avoid VBUS short circuit due to wrong cable.
398 * PWEN should be pulled up high if USB Function is selected by SW5
399 */
400 gpio_request_one(RCAR_GP_PIN(5, 18), GPIOF_IN, NULL); /* USB0_PWEN */
401 if (!gpio_get_value(RCAR_GP_PIN(5, 18))) {
402 pr_warn("Error: USB Function not selected - check SW5 + SW6\n");
403 ret = -ENOTSUPP;
404 goto error;
405 }
406
407 phy = usb_get_phy_dev(&pdev->dev, 0);
408 if (IS_ERR(phy)) {
409 ret = PTR_ERR(phy);
410 goto error;
411 }
412
413 priv->phy = phy;
414 return 0;
415 error:
416 gpio_free(RCAR_GP_PIN(5, 18));
417 return ret;
418}
419
420static int usbhs_hardware_exit(struct platform_device *pdev)
421{
422 struct usbhs_private *priv = usbhs_get_priv(pdev);
423
424 if (!priv->phy)
425 return 0;
426
427 usb_put_phy(priv->phy);
428 priv->phy = NULL;
429
430 gpio_free(RCAR_GP_PIN(5, 18));
431 return 0;
432}
433
434static int usbhs_get_id(struct platform_device *pdev)
435{
436 return USBHS_GADGET;
437}
438
439static u32 lager_usbhs_pipe_type[] = {
440 USB_ENDPOINT_XFER_CONTROL,
441 USB_ENDPOINT_XFER_ISOC,
442 USB_ENDPOINT_XFER_ISOC,
443 USB_ENDPOINT_XFER_BULK,
444 USB_ENDPOINT_XFER_BULK,
445 USB_ENDPOINT_XFER_BULK,
446 USB_ENDPOINT_XFER_INT,
447 USB_ENDPOINT_XFER_INT,
448 USB_ENDPOINT_XFER_INT,
449 USB_ENDPOINT_XFER_BULK,
450 USB_ENDPOINT_XFER_BULK,
451 USB_ENDPOINT_XFER_BULK,
452 USB_ENDPOINT_XFER_BULK,
453 USB_ENDPOINT_XFER_BULK,
454 USB_ENDPOINT_XFER_BULK,
455 USB_ENDPOINT_XFER_BULK,
456};
457
458static struct usbhs_private usbhs_priv __initdata = {
459 .info = {
460 .platform_callback = {
461 .power_ctrl = usbhs_power_ctrl,
462 .hardware_init = usbhs_hardware_init,
463 .hardware_exit = usbhs_hardware_exit,
464 .get_id = usbhs_get_id,
465 },
466 .driver_param = {
467 .buswait_bwait = 4,
468 .pipe_type = lager_usbhs_pipe_type,
469 .pipe_size = ARRAY_SIZE(lager_usbhs_pipe_type),
470 },
471 }
472};
473
474static void __init lager_register_usbhs(void)
475{
476 usb_bind_phy("renesas_usbhs", 0, "usb_phy_rcar_gen2");
477 platform_device_register_resndata(NULL,
478 "renesas_usbhs", -1,
479 usbhs_resources,
480 ARRAY_SIZE(usbhs_resources),
481 &usbhs_priv.info,
482 sizeof(usbhs_priv.info));
483}
484
485/* USBHS PHY */
486static const struct rcar_gen2_phy_platform_data usbhs_phy_pdata __initconst = {
487 .chan0_pci = 0, /* Channel 0 is USBHS */
488 .chan2_pci = 1, /* Channel 2 is PCI USB */
489};
490
491static const struct resource usbhs_phy_resources[] __initconst = {
492 DEFINE_RES_MEM(0xe6590100, 0x100),
493};
494
495/* I2C */
496static struct i2c_board_info i2c2_devices[] = {
497 {
498 I2C_BOARD_INFO("ak4643", 0x12),
499 }
500};
501
502/* Sound */
503static struct resource rsnd_resources[] __initdata = {
504 [RSND_GEN2_SCU] = DEFINE_RES_MEM(0xec500000, 0x1000),
505 [RSND_GEN2_ADG] = DEFINE_RES_MEM(0xec5a0000, 0x100),
506 [RSND_GEN2_SSIU] = DEFINE_RES_MEM(0xec540000, 0x1000),
507 [RSND_GEN2_SSI] = DEFINE_RES_MEM(0xec541000, 0x1280),
508};
509
510static struct rsnd_ssi_platform_info rsnd_ssi[] = {
511 RSND_SSI(0, gic_spi(370), 0),
512 RSND_SSI(0, gic_spi(371), RSND_SSI_CLK_PIN_SHARE),
513};
514
515static struct rsnd_src_platform_info rsnd_src[2] = {
516 /* no member at this point */
517};
518
519static struct rsnd_dai_platform_info rsnd_dai = {
520 .playback = { .ssi = &rsnd_ssi[0], },
521 .capture = { .ssi = &rsnd_ssi[1], },
522};
523
524static struct rcar_snd_info rsnd_info = {
525 .flags = RSND_GEN2,
526 .ssi_info = rsnd_ssi,
527 .ssi_info_nr = ARRAY_SIZE(rsnd_ssi),
528 .src_info = rsnd_src,
529 .src_info_nr = ARRAY_SIZE(rsnd_src),
530 .dai_info = &rsnd_dai,
531 .dai_info_nr = 1,
532};
533
534static struct asoc_simple_card_info rsnd_card_info = {
535 .name = "AK4643",
536 .card = "SSI01-AK4643",
537 .codec = "ak4642-codec.2-0012",
538 .platform = "rcar_sound",
539 .daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
540 .cpu_dai = {
541 .name = "rcar_sound",
542 },
543 .codec_dai = {
544 .name = "ak4642-hifi",
545 .sysclk = 11289600,
546 },
547};
548
549static void __init lager_add_rsnd_device(void)
550{
551 struct platform_device_info cardinfo = {
552 .name = "asoc-simple-card",
553 .id = -1,
554 .data = &rsnd_card_info,
555 .size_data = sizeof(struct asoc_simple_card_info),
556 .dma_mask = DMA_BIT_MASK(32),
557 };
558
559 i2c_register_board_info(2, i2c2_devices,
560 ARRAY_SIZE(i2c2_devices));
561
562 platform_device_register_resndata(
563 NULL, "rcar_sound", -1,
564 rsnd_resources, ARRAY_SIZE(rsnd_resources),
565 &rsnd_info, sizeof(rsnd_info));
566
567 platform_device_register_full(&cardinfo);
568}
569
570/* SDHI0 */
571static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
572 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
573 MMC_CAP_POWER_OFF_CARD,
574 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
575 TMIO_MMC_WRPROTECT_DISABLE,
576};
577
578static struct resource sdhi0_resources[] __initdata = {
579 DEFINE_RES_MEM(0xee100000, 0x200),
580 DEFINE_RES_IRQ(gic_spi(165)),
581};
582
583/* SDHI2 */
584static struct sh_mobile_sdhi_info sdhi2_info __initdata = {
585 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
586 MMC_CAP_POWER_OFF_CARD,
587 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
588 TMIO_MMC_WRPROTECT_DISABLE,
589};
590
591static struct resource sdhi2_resources[] __initdata = {
592 DEFINE_RES_MEM(0xee140000, 0x100),
593 DEFINE_RES_IRQ(gic_spi(167)),
594};
595
596/* Internal PCI1 */
597static const struct resource pci1_resources[] __initconst = {
598 DEFINE_RES_MEM(0xee0b0000, 0x10000), /* CFG */
599 DEFINE_RES_MEM(0xee0a0000, 0x10000), /* MEM */
600 DEFINE_RES_IRQ(gic_spi(112)),
601};
602
603static const struct platform_device_info pci1_info __initconst = {
604 .name = "pci-rcar-gen2",
605 .id = 1,
606 .res = pci1_resources,
607 .num_res = ARRAY_SIZE(pci1_resources),
608 .dma_mask = DMA_BIT_MASK(32),
609};
610
611static void __init lager_add_usb1_device(void)
612{
613 platform_device_register_full(&pci1_info);
614}
615
616/* Internal PCI2 */
617static const struct resource pci2_resources[] __initconst = {
618 DEFINE_RES_MEM(0xee0d0000, 0x10000), /* CFG */
619 DEFINE_RES_MEM(0xee0c0000, 0x10000), /* MEM */
620 DEFINE_RES_IRQ(gic_spi(113)),
621};
622
623static const struct platform_device_info pci2_info __initconst = {
624 .name = "pci-rcar-gen2",
625 .id = 2,
626 .res = pci2_resources,
627 .num_res = ARRAY_SIZE(pci2_resources),
628 .dma_mask = DMA_BIT_MASK(32),
629};
630
631static void __init lager_add_usb2_device(void)
632{
633 platform_device_register_full(&pci2_info);
634}
635
636static const struct pinctrl_map lager_pinctrl_map[] = {
637 /* DU (CN10: ARGB0, CN13: LVDS) */
638 PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
639 "du_rgb666", "du"),
640 PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
641 "du_sync_1", "du"),
642 PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
643 "du_clk_out_0", "du"),
644 /* I2C2 */
645 PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar.2", "pfc-r8a7790",
646 "i2c2", "i2c2"),
647 /* QSPI */
648 PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
649 "qspi_ctrl", "qspi"),
650 PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7790",
651 "qspi_data4", "qspi"),
652 /* SCIF0 (CN19: DEBUG SERIAL0) */
653 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
654 "scif0_data", "scif0"),
655 /* SCIF1 (CN20: DEBUG SERIAL1) */
656 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
657 "scif1_data", "scif1"),
658 /* SDHI0 */
659 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
660 "sdhi0_data4", "sdhi0"),
661 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
662 "sdhi0_ctrl", "sdhi0"),
663 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7790",
664 "sdhi0_cd", "sdhi0"),
665 /* SDHI2 */
666 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
667 "sdhi2_data4", "sdhi2"),
668 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
669 "sdhi2_ctrl", "sdhi2"),
670 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7790",
671 "sdhi2_cd", "sdhi2"),
672 /* SSI (CN17: sound) */
673 PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
674 "ssi0129_ctrl", "ssi"),
675 PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
676 "ssi0_data", "ssi"),
677 PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
678 "ssi1_data", "ssi"),
679 PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7790",
680 "audio_clk_a", "audio_clk"),
681 /* MMCIF1 */
682 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
683 "mmc1_data8", "mmc1"),
684 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
685 "mmc1_ctrl", "mmc1"),
686 /* Ether */
687 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
688 "eth_link", "eth"),
689 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
690 "eth_mdio", "eth"),
691 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
692 "eth_rmii", "eth"),
693 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
694 "intc_irq0", "intc"),
695 /* VIN0 */
696 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
697 "vin0_data24", "vin0"),
698 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
699 "vin0_sync", "vin0"),
700 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
701 "vin0_field", "vin0"),
702 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
703 "vin0_clkenb", "vin0"),
704 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
705 "vin0_clk", "vin0"),
706 /* VIN1 */
707 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
708 "vin1_data8", "vin1"),
709 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
710 "vin1_clk", "vin1"),
711 /* USB0 */
712 PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790",
713 "usb0_ovc_vbus", "usb0"),
714 /* USB1 */
715 PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.1", "pfc-r8a7790",
716 "usb1", "usb1"),
717 /* USB2 */
718 PIN_MAP_MUX_GROUP_DEFAULT("pci-rcar-gen2.2", "pfc-r8a7790",
719 "usb2", "usb2"),
720};
721
722static void __init lager_add_standard_devices(void)
723{
724 int fixed_regulator_idx = 0;
725 int gpio_regulator_idx = 0;
726
727 r8a7790_clock_init();
728
729 pinctrl_register_mappings(lager_pinctrl_map,
730 ARRAY_SIZE(lager_pinctrl_map));
731 r8a7790_pinmux_init();
732
733 r8a7790_add_standard_devices();
734 platform_device_register_data(NULL, "leds-gpio", -1,
735 &lager_leds_pdata,
736 sizeof(lager_leds_pdata));
737 platform_device_register_data(NULL, "gpio-keys", -1,
738 &lager_keys_pdata,
739 sizeof(lager_keys_pdata));
740 regulator_register_always_on(fixed_regulator_idx++,
741 "fixed-3.3V", fixed3v3_power_consumers,
742 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
743 platform_device_register_resndata(NULL, "sh_mmcif", 1,
744 mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
745 &mmcif1_pdata, sizeof(mmcif1_pdata));
746
747 platform_device_register_full(&ether_info);
748
749 platform_device_register_resndata(NULL, "qspi", 0,
750 qspi_resources,
751 ARRAY_SIZE(qspi_resources),
752 &qspi_pdata, sizeof(qspi_pdata));
753 spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
754
755 platform_device_register_data(NULL, "reg-fixed-voltage", fixed_regulator_idx++,
756 &vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
757 platform_device_register_data(NULL, "reg-fixed-voltage", fixed_regulator_idx++,
758 &vcc_sdhi2_info, sizeof(struct fixed_voltage_config));
759
760 platform_device_register_data(NULL, "gpio-regulator", gpio_regulator_idx++,
761 &vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
762 platform_device_register_data(NULL, "gpio-regulator", gpio_regulator_idx++,
763 &vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
764
765 lager_add_camera1_device();
766
767 platform_device_register_full(&sata1_info);
768
769 platform_device_register_resndata(NULL, "usb_phy_rcar_gen2",
770 -1, usbhs_phy_resources,
771 ARRAY_SIZE(usbhs_phy_resources),
772 &usbhs_phy_pdata,
773 sizeof(usbhs_phy_pdata));
774 lager_register_usbhs();
775 lager_add_usb1_device();
776 lager_add_usb2_device();
777
778 lager_add_rsnd_device();
779
780 platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0,
781 sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
782 &sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
783 platform_device_register_resndata(NULL, "sh_mobile_sdhi", 2,
784 sdhi2_resources, ARRAY_SIZE(sdhi2_resources),
785 &sdhi2_info, sizeof(struct sh_mobile_sdhi_info));
786}
787
788/*
789 * Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
790 * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
791 * 14-15. We have to set them back to 01 from the default 00 value each time
792 * the PHY is reset. It's also important because the PHY's LED0 signal is
793 * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
794 * bounce on and off after each packet, which we apparently want to avoid.
795 */
796static int lager_ksz8041_fixup(struct phy_device *phydev)
797{
798 u16 phyctrl1 = phy_read(phydev, 0x1e);
799
800 phyctrl1 &= ~0xc000;
801 phyctrl1 |= 0x4000;
802 return phy_write(phydev, 0x1e, phyctrl1);
803}
804
805static void __init lager_init(void)
806{
807 lager_add_standard_devices();
808
809 irq_set_irq_type(irq_pin(0), IRQ_TYPE_LEVEL_LOW);
810
811 if (IS_ENABLED(CONFIG_PHYLIB))
812 phy_register_fixup_for_id("r8a7790-ether-ff:01",
813 lager_ksz8041_fixup);
814}
815
816static void __init lager_legacy_init_irq(void)
817{
818 void __iomem *gic_dist_base = ioremap_nocache(0xf1001000, 0x1000);
819 void __iomem *gic_cpu_base = ioremap_nocache(0xf1002000, 0x1000);
820
821 gic_init(0, 29, gic_dist_base, gic_cpu_base);
822
823 /* Do not invoke DT-based interrupt code via irqchip_init() */
824}
825
826static const char * const lager_boards_compat_dt[] __initconst = {
827 "renesas,lager",
828 NULL,
829};
830
831DT_MACHINE_START(LAGER_DT, "lager")
832 .smp = smp_ops(r8a7790_smp_ops),
833 .init_early = shmobile_init_delay,
834 .init_irq = lager_legacy_init_irq,
835 .init_time = rcar_gen2_timer_init,
836 .init_machine = lager_init,
837 .init_late = shmobile_init_late,
838 .reserve = rcar_gen2_reserve,
839 .dt_compat = lager_boards_compat_dt,
840MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
deleted file mode 100644
index f9bbc5f0a9a1..000000000000
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ /dev/null
@@ -1,459 +0,0 @@
1/*
2 * r8a7790 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/sh_clk.h>
20#include <linux/clkdev.h>
21
22#include "clock.h"
23#include "common.h"
24#include "r8a7790.h"
25#include "rcar-gen2.h"
26
27/*
28 * MD EXTAL PLL0 PLL1 PLL3
29 * 14 13 19 (MHz) *1 *1
30 *---------------------------------------------------
31 * 0 0 0 15 x 1 x172/2 x208/2 x106
32 * 0 0 1 15 x 1 x172/2 x208/2 x88
33 * 0 1 0 20 x 1 x130/2 x156/2 x80
34 * 0 1 1 20 x 1 x130/2 x156/2 x66
35 * 1 0 0 26 / 2 x200/2 x240/2 x122
36 * 1 0 1 26 / 2 x200/2 x240/2 x102
37 * 1 1 0 30 / 2 x172/2 x208/2 x106
38 * 1 1 1 30 / 2 x172/2 x208/2 x88
39 *
40 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
41 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
42 */
43
44#define CPG_BASE 0xe6150000
45#define CPG_LEN 0x1000
46
47#define SMSTPCR1 0xe6150134
48#define SMSTPCR2 0xe6150138
49#define SMSTPCR3 0xe615013c
50#define SMSTPCR5 0xe6150144
51#define SMSTPCR7 0xe615014c
52#define SMSTPCR8 0xe6150990
53#define SMSTPCR9 0xe6150994
54#define SMSTPCR10 0xe6150998
55
56#define MSTPSR1 IOMEM(0xe6150038)
57#define MSTPSR2 IOMEM(0xe6150040)
58#define MSTPSR3 IOMEM(0xe6150048)
59#define MSTPSR5 IOMEM(0xe615003c)
60#define MSTPSR7 IOMEM(0xe61501c4)
61#define MSTPSR8 IOMEM(0xe61509a0)
62#define MSTPSR9 IOMEM(0xe61509a4)
63#define MSTPSR10 IOMEM(0xe61509a8)
64
65#define SDCKCR 0xE6150074
66#define SD2CKCR 0xE6150078
67#define SD3CKCR 0xE615026C
68#define MMC0CKCR 0xE6150240
69#define MMC1CKCR 0xE6150244
70#define SSPCKCR 0xE6150248
71#define SSPRSCKCR 0xE615024C
72
73static struct clk_mapping cpg_mapping = {
74 .phys = CPG_BASE,
75 .len = CPG_LEN,
76};
77
78static struct clk extal_clk = {
79 /* .rate will be updated on r8a7790_clock_init() */
80 .mapping = &cpg_mapping,
81};
82
83static struct sh_clk_ops followparent_clk_ops = {
84 .recalc = followparent_recalc,
85};
86
87static struct clk main_clk = {
88 /* .parent will be set r8a7790_clock_init */
89 .ops = &followparent_clk_ops,
90};
91
92static struct clk audio_clk_a = {
93};
94
95static struct clk audio_clk_b = {
96};
97
98static struct clk audio_clk_c = {
99};
100
101/*
102 * clock ratio of these clock will be updated
103 * on r8a7790_clock_init()
104 */
105SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
106SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
107SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
108SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
109
110/* fixed ratio clock */
111SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
112SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
113
114SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
115SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
116SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
117SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
118SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
119SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
120SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
121SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
122SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
123SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
124SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
125SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
126SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
127
128SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
129SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
130SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
131SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
132
133static struct clk *main_clks[] = {
134 &audio_clk_a,
135 &audio_clk_b,
136 &audio_clk_c,
137 &extal_clk,
138 &extal_div2_clk,
139 &main_clk,
140 &pll1_clk,
141 &pll1_div2_clk,
142 &pll3_clk,
143 &lb_clk,
144 &qspi_clk,
145 &zg_clk,
146 &zx_clk,
147 &zs_clk,
148 &hp_clk,
149 &i_clk,
150 &b_clk,
151 &p_clk,
152 &cl_clk,
153 &m2_clk,
154 &imp_clk,
155 &rclk_clk,
156 &oscclk_clk,
157 &zb3_clk,
158 &zb3d2_clk,
159 &ddr_clk,
160 &mp_clk,
161 &cp_clk,
162};
163
164/* SDHI (DIV4) clock */
165static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
166
167static struct clk_div_mult_table div4_div_mult_table = {
168 .divisors = divisors,
169 .nr_divisors = ARRAY_SIZE(divisors),
170};
171
172static struct clk_div4_table div4_table = {
173 .div_mult_table = &div4_div_mult_table,
174};
175
176enum {
177 DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
178};
179
180static struct clk div4_clks[DIV4_NR] = {
181 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
182 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
183 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
184};
185
186/* DIV6 clocks */
187enum {
188 DIV6_SD2, DIV6_SD3,
189 DIV6_MMC0, DIV6_MMC1,
190 DIV6_SSP, DIV6_SSPRS,
191 DIV6_NR
192};
193
194static struct clk div6_clks[DIV6_NR] = {
195 [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
196 [DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
197 [DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
198 [DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
199 [DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
200 [DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
201};
202
203/* MSTP */
204enum {
205 MSTP1017, /* parent of SCU */
206
207 MSTP1031, MSTP1030,
208 MSTP1029, MSTP1028, MSTP1027, MSTP1026, MSTP1025, MSTP1024, MSTP1023, MSTP1022,
209 MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
210 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
211 MSTP931, MSTP930, MSTP929, MSTP928,
212 MSTP917,
213 MSTP815, MSTP814,
214 MSTP813,
215 MSTP811, MSTP810, MSTP809, MSTP808,
216 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
217 MSTP717, MSTP716,
218 MSTP704, MSTP703,
219 MSTP522,
220 MSTP502, MSTP501,
221 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
222 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
223 MSTP124,
224 MSTP_NR
225};
226
227static struct clk mstp_clks[MSTP_NR] = {
228 [MSTP1031] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 31, MSTPSR10, 0), /* SCU0 */
229 [MSTP1030] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 30, MSTPSR10, 0), /* SCU1 */
230 [MSTP1029] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 29, MSTPSR10, 0), /* SCU2 */
231 [MSTP1028] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 28, MSTPSR10, 0), /* SCU3 */
232 [MSTP1027] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 27, MSTPSR10, 0), /* SCU4 */
233 [MSTP1026] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 26, MSTPSR10, 0), /* SCU5 */
234 [MSTP1025] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 25, MSTPSR10, 0), /* SCU6 */
235 [MSTP1024] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 24, MSTPSR10, 0), /* SCU7 */
236 [MSTP1023] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 23, MSTPSR10, 0), /* SCU8 */
237 [MSTP1022] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 22, MSTPSR10, 0), /* SCU9 */
238 [MSTP1017] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 17, MSTPSR10, 0), /* SCU */
239 [MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
240 [MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
241 [MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
242 [MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
243 [MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
244 [MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
245 [MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
246 [MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
247 [MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
248 [MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
249 [MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
250 [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
251 [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
252 [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
253 [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
254 [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
255 [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
256 [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
257 [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
258 [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
259 [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
260 [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
261 [MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 8, MSTPSR8, 0), /* VIN3 */
262 [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
263 [MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
264 [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
265 [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
266 [MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
267 [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
268 [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
269 [MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
270 [MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
271 [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
272 [MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
273 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
274 [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
275 [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
276 [MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
277 [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
278 [MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
279 [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
280 [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
281 [MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
282 [MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
283 [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
284 [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
285 [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
286 [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
287 [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
288 [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
289 [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
290};
291
292static struct clk_lookup lookups[] = {
293
294 /* main clocks */
295 CLKDEV_CON_ID("extal", &extal_clk),
296 CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
297 CLKDEV_CON_ID("main", &main_clk),
298 CLKDEV_CON_ID("pll1", &pll1_clk),
299 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
300 CLKDEV_CON_ID("pll3", &pll3_clk),
301 CLKDEV_CON_ID("zg", &zg_clk),
302 CLKDEV_CON_ID("zx", &zx_clk),
303 CLKDEV_CON_ID("zs", &zs_clk),
304 CLKDEV_CON_ID("hp", &hp_clk),
305 CLKDEV_CON_ID("i", &i_clk),
306 CLKDEV_CON_ID("b", &b_clk),
307 CLKDEV_CON_ID("lb", &lb_clk),
308 CLKDEV_CON_ID("p", &p_clk),
309 CLKDEV_CON_ID("cl", &cl_clk),
310 CLKDEV_CON_ID("m2", &m2_clk),
311 CLKDEV_CON_ID("imp", &imp_clk),
312 CLKDEV_CON_ID("rclk", &rclk_clk),
313 CLKDEV_CON_ID("oscclk", &oscclk_clk),
314 CLKDEV_CON_ID("zb3", &zb3_clk),
315 CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
316 CLKDEV_CON_ID("ddr", &ddr_clk),
317 CLKDEV_CON_ID("mp", &mp_clk),
318 CLKDEV_CON_ID("qspi", &qspi_clk),
319 CLKDEV_CON_ID("cp", &cp_clk),
320
321 /* DIV4 */
322 CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
323
324 /* DIV6 */
325 CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
326 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
327
328 /* MSTP */
329 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
330 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
331 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
332 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
333 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
334 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
335 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
336 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
337 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
338 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
339 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
340 CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
341 CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
342 CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
343 CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
344 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
345 CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
346 CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
347 CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
348 CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
349 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
350 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
351 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
352 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
353 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
354 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
355 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
356 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
357 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
358 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
359 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
360 CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
361 CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
362 CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
363 CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
364 CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
365
366 /* ICK */
367 CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
368 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
369 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
370 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
371 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
372 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
373 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
374 CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
375 CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
376 CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
377 CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
378 CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
379 CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
380 CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
381 CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
382 CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
383 CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
384 CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
385 CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
386 CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
387 CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
388 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
389 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
390 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
391 CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
392 CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
393 CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
394 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
395 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
396 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
397 CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
398
399};
400
401#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
402 extal_clk.rate = e * 1000 * 1000; \
403 main_clk.parent = m; \
404 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
405 if (mode & MD(19)) \
406 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
407 else \
408 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
409
410
411void __init r8a7790_clock_init(void)
412{
413 u32 mode = rcar_gen2_read_mode_pins();
414 int k, ret = 0;
415
416 switch (mode & (MD(14) | MD(13))) {
417 case 0:
418 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
419 break;
420 case MD(13):
421 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
422 break;
423 case MD(14):
424 R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
425 break;
426 case MD(13) | MD(14):
427 R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
428 break;
429 }
430
431 if (mode & (MD(18)))
432 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
433 else
434 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
435
436 if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
437 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
438 else
439 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
440
441 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
442 ret = clk_register(main_clks[k]);
443
444 if (!ret)
445 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
446
447 if (!ret)
448 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
449
450 if (!ret)
451 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
452
453 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
454
455 if (!ret)
456 shmobile_clk_init();
457 else
458 panic("failed to setup r8a7790 clocks\n");
459}
diff --git a/arch/arm/mach-shmobile/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h
index 388f0514d931..bf73a850aaed 100644
--- a/arch/arm/mach-shmobile/r8a7790.h
+++ b/arch/arm/mach-shmobile/r8a7790.h
@@ -1,34 +1,6 @@
1#ifndef __ASM_R8A7790_H__ 1#ifndef __ASM_R8A7790_H__
2#define __ASM_R8A7790_H__ 2#define __ASM_R8A7790_H__
3 3
4/* DMA slave IDs */
5enum {
6 RCAR_DMA_SLAVE_INVALID,
7 AUDIO_DMAC_SLAVE_SSI0_TX,
8 AUDIO_DMAC_SLAVE_SSI0_RX,
9 AUDIO_DMAC_SLAVE_SSI1_TX,
10 AUDIO_DMAC_SLAVE_SSI1_RX,
11 AUDIO_DMAC_SLAVE_SSI2_TX,
12 AUDIO_DMAC_SLAVE_SSI2_RX,
13 AUDIO_DMAC_SLAVE_SSI3_TX,
14 AUDIO_DMAC_SLAVE_SSI3_RX,
15 AUDIO_DMAC_SLAVE_SSI4_TX,
16 AUDIO_DMAC_SLAVE_SSI4_RX,
17 AUDIO_DMAC_SLAVE_SSI5_TX,
18 AUDIO_DMAC_SLAVE_SSI5_RX,
19 AUDIO_DMAC_SLAVE_SSI6_TX,
20 AUDIO_DMAC_SLAVE_SSI6_RX,
21 AUDIO_DMAC_SLAVE_SSI7_TX,
22 AUDIO_DMAC_SLAVE_SSI7_RX,
23 AUDIO_DMAC_SLAVE_SSI8_TX,
24 AUDIO_DMAC_SLAVE_SSI8_RX,
25 AUDIO_DMAC_SLAVE_SSI9_TX,
26 AUDIO_DMAC_SLAVE_SSI9_RX,
27};
28
29void r8a7790_add_standard_devices(void);
30void r8a7790_clock_init(void);
31void r8a7790_pinmux_init(void);
32void r8a7790_pm_init(void); 4void r8a7790_pm_init(void);
33extern struct smp_operations r8a7790_smp_ops; 5extern struct smp_operations r8a7790_smp_ops;
34 6
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index d191cf419731..dd64caf79216 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -656,7 +656,7 @@ static struct resource pmu_resources[] = {
656}; 656};
657 657
658static struct platform_device pmu_device = { 658static struct platform_device pmu_device = {
659 .name = "arm-pmu", 659 .name = "armv7-pmu",
660 .id = -1, 660 .id = -1,
661 .num_resources = ARRAY_SIZE(pmu_resources), 661 .num_resources = ARRAY_SIZE(pmu_resources),
662 .resource = pmu_resources, 662 .resource = pmu_resources,
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index ec7d97dca4de..3a18af4922b4 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -14,295 +14,14 @@
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17#include <linux/irq.h> 17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/of_platform.h>
20#include <linux/platform_data/gpio-rcar.h>
21#include <linux/platform_data/irq-renesas-irqc.h>
22#include <linux/serial_sci.h>
23#include <linux/sh_dma.h>
24#include <linux/sh_timer.h>
25 18
26#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
27 20
28#include "common.h" 21#include "common.h"
29#include "dma-register.h"
30#include "irqs.h"
31#include "r8a7790.h" 22#include "r8a7790.h"
32#include "rcar-gen2.h" 23#include "rcar-gen2.h"
33 24
34/* Audio-DMAC */
35#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
36{ \
37 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
38 .addr = _addr + 0x8, \
39 .chcr = CHCR_TX(XMIT_SZ_32BIT), \
40 .mid_rid = t, \
41}, { \
42 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
43 .addr = _addr + 0xc, \
44 .chcr = CHCR_RX(XMIT_SZ_32BIT), \
45 .mid_rid = r, \
46}
47
48static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
49 AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
50 AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
51 AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
52 AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
53 AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
54 AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
55 AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
56 AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
57 AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
58 AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
59};
60
61#define DMAE_CHANNEL(a, b) \
62{ \
63 .offset = (a) - 0x20, \
64 .dmars = (a) - 0x20 + 0x40, \
65 .chclr_bit = (b), \
66 .chclr_offset = 0x80 - 0x20, \
67}
68
69static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
70 DMAE_CHANNEL(0x8000, 0),
71 DMAE_CHANNEL(0x8080, 1),
72 DMAE_CHANNEL(0x8100, 2),
73 DMAE_CHANNEL(0x8180, 3),
74 DMAE_CHANNEL(0x8200, 4),
75 DMAE_CHANNEL(0x8280, 5),
76 DMAE_CHANNEL(0x8300, 6),
77 DMAE_CHANNEL(0x8380, 7),
78 DMAE_CHANNEL(0x8400, 8),
79 DMAE_CHANNEL(0x8480, 9),
80 DMAE_CHANNEL(0x8500, 10),
81 DMAE_CHANNEL(0x8580, 11),
82 DMAE_CHANNEL(0x8600, 12),
83};
84
85static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
86 .slave = r8a7790_audio_dmac_slaves,
87 .slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
88 .channel = r8a7790_audio_dmac_channels,
89 .channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
90 .ts_low_shift = TS_LOW_SHIFT,
91 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
92 .ts_high_shift = TS_HI_SHIFT,
93 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
94 .ts_shift = dma_ts_shift,
95 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
96 .dmaor_init = DMAOR_DME,
97 .chclr_present = 1,
98 .chclr_bitwise = 1,
99};
100
101static struct resource r8a7790_audio_dmac_resources[] = {
102 /* Channel registers and DMAOR for low */
103 DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
104 DEFINE_RES_IRQ(gic_spi(346)),
105 DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
106
107 /* Channel registers and DMAOR for hi */
108 DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
109 DEFINE_RES_IRQ(gic_spi(347)),
110 DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
111};
112
113#define r8a7790_register_audio_dmac(id) \
114 platform_device_register_resndata( \
115 NULL, "sh-dma-engine", id, \
116 &r8a7790_audio_dmac_resources[id * 3], 3, \
117 &r8a7790_audio_dmac_platform_data, \
118 sizeof(r8a7790_audio_dmac_platform_data))
119
120static const struct resource pfc_resources[] __initconst = {
121 DEFINE_RES_MEM(0xe6060000, 0x250),
122};
123
124#define r8a7790_register_pfc() \
125 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
126 ARRAY_SIZE(pfc_resources))
127
128#define R8A7790_GPIO(idx) \
129static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
130 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
131 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
132}; \
133 \
134static const struct gpio_rcar_config \
135r8a7790_gpio##idx##_platform_data __initconst = { \
136 .gpio_base = 32 * (idx), \
137 .irq_base = 0, \
138 .number_of_pins = 32, \
139 .pctl_name = "pfc-r8a7790", \
140 .has_both_edge_trigger = 1, \
141}; \
142
143R8A7790_GPIO(0);
144R8A7790_GPIO(1);
145R8A7790_GPIO(2);
146R8A7790_GPIO(3);
147R8A7790_GPIO(4);
148R8A7790_GPIO(5);
149
150#define r8a7790_register_gpio(idx) \
151 platform_device_register_resndata(NULL, "gpio_rcar", idx, \
152 r8a7790_gpio##idx##_resources, \
153 ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
154 &r8a7790_gpio##idx##_platform_data, \
155 sizeof(r8a7790_gpio##idx##_platform_data))
156
157static struct resource i2c_resources[] __initdata = {
158 /* I2C0 */
159 DEFINE_RES_MEM(0xE6508000, 0x40),
160 DEFINE_RES_IRQ(gic_spi(287)),
161 /* I2C1 */
162 DEFINE_RES_MEM(0xE6518000, 0x40),
163 DEFINE_RES_IRQ(gic_spi(288)),
164 /* I2C2 */
165 DEFINE_RES_MEM(0xE6530000, 0x40),
166 DEFINE_RES_IRQ(gic_spi(286)),
167 /* I2C3 */
168 DEFINE_RES_MEM(0xE6540000, 0x40),
169 DEFINE_RES_IRQ(gic_spi(290)),
170
171};
172
173#define r8a7790_register_i2c(idx) \
174 platform_device_register_simple( \
175 "i2c-rcar_gen2", idx, \
176 i2c_resources + (2 * idx), 2); \
177
178void __init r8a7790_pinmux_init(void)
179{
180 r8a7790_register_pfc();
181 r8a7790_register_gpio(0);
182 r8a7790_register_gpio(1);
183 r8a7790_register_gpio(2);
184 r8a7790_register_gpio(3);
185 r8a7790_register_gpio(4);
186 r8a7790_register_gpio(5);
187}
188
189#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
190static struct plat_sci_port scif##index##_platform_data = { \
191 .type = scif_type, \
192 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
193 .scscr = _scscr, \
194}; \
195 \
196static struct resource scif##index##_resources[] = { \
197 DEFINE_RES_MEM(baseaddr, 0x100), \
198 DEFINE_RES_IRQ(irq), \
199}
200
201#define R8A7790_SCIF(index, baseaddr, irq) \
202 __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
203 index, baseaddr, irq)
204
205#define R8A7790_SCIFA(index, baseaddr, irq) \
206 __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
207 index, baseaddr, irq)
208
209#define R8A7790_SCIFB(index, baseaddr, irq) \
210 __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
211 index, baseaddr, irq)
212
213#define R8A7790_HSCIF(index, baseaddr, irq) \
214 __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
215 index, baseaddr, irq)
216
217R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
218R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
219R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
220R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
221R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
222R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
223R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
224R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
225R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
226R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
227
228#define r8a7790_register_scif(index) \
229 platform_device_register_resndata(NULL, "sh-sci", index, \
230 scif##index##_resources, \
231 ARRAY_SIZE(scif##index##_resources), \
232 &scif##index##_platform_data, \
233 sizeof(scif##index##_platform_data))
234
235static const struct renesas_irqc_config irqc0_data __initconst = {
236 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
237};
238
239static const struct resource irqc0_resources[] __initconst = {
240 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
241 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
242 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
243 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
244 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
245};
246
247#define r8a7790_register_irqc(idx) \
248 platform_device_register_resndata(NULL, "renesas_irqc", \
249 idx, irqc##idx##_resources, \
250 ARRAY_SIZE(irqc##idx##_resources), \
251 &irqc##idx##_data, \
252 sizeof(struct renesas_irqc_config))
253
254static const struct resource thermal_resources[] __initconst = {
255 DEFINE_RES_MEM(0xe61f0000, 0x14),
256 DEFINE_RES_MEM(0xe61f0100, 0x38),
257 DEFINE_RES_IRQ(gic_spi(69)),
258};
259
260#define r8a7790_register_thermal() \
261 platform_device_register_simple("rcar_thermal", -1, \
262 thermal_resources, \
263 ARRAY_SIZE(thermal_resources))
264
265static struct sh_timer_config cmt0_platform_data = {
266 .channels_mask = 0x60,
267};
268
269static struct resource cmt0_resources[] = {
270 DEFINE_RES_MEM(0xffca0000, 0x1004),
271 DEFINE_RES_IRQ(gic_spi(142)),
272};
273
274#define r8a7790_register_cmt(idx) \
275 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
276 idx, cmt##idx##_resources, \
277 ARRAY_SIZE(cmt##idx##_resources), \
278 &cmt##idx##_platform_data, \
279 sizeof(struct sh_timer_config))
280
281void __init r8a7790_add_standard_devices(void)
282{
283 r8a7790_register_scif(0);
284 r8a7790_register_scif(1);
285 r8a7790_register_scif(2);
286 r8a7790_register_scif(3);
287 r8a7790_register_scif(4);
288 r8a7790_register_scif(5);
289 r8a7790_register_scif(6);
290 r8a7790_register_scif(7);
291 r8a7790_register_scif(8);
292 r8a7790_register_scif(9);
293 r8a7790_register_cmt(0);
294 r8a7790_register_irqc(0);
295 r8a7790_register_thermal();
296 r8a7790_register_i2c(0);
297 r8a7790_register_i2c(1);
298 r8a7790_register_i2c(2);
299 r8a7790_register_i2c(3);
300 r8a7790_register_audio_dmac(0);
301 r8a7790_register_audio_dmac(1);
302}
303
304#ifdef CONFIG_USE_OF
305
306static const char * const r8a7790_boards_compat_dt[] __initconst = { 25static const char * const r8a7790_boards_compat_dt[] __initconst = {
307 "renesas,r8a7790", 26 "renesas,r8a7790",
308 NULL, 27 NULL,
@@ -316,4 +35,3 @@ DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
316 .reserve = rcar_gen2_reserve, 35 .reserve = rcar_gen2_reserve,
317 .dt_compat = r8a7790_boards_compat_dt, 36 .dt_compat = r8a7790_boards_compat_dt,
318MACHINE_END 37MACHINE_END
319#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index fb5e1bb34be8..a8593d1241be 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -563,7 +563,7 @@ static struct resource pmu_resources[] = {
563}; 563};
564 564
565static struct platform_device pmu_device = { 565static struct platform_device pmu_device = {
566 .name = "arm-pmu", 566 .name = "armv7-pmu",
567 .id = -1, 567 .id = -1,
568 .num_resources = ARRAY_SIZE(pmu_resources), 568 .num_resources = ARRAY_SIZE(pmu_resources),
569 .resource = pmu_resources, 569 .resource = pmu_resources,
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 08fb8c89f414..6ea09fe53426 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -728,43 +728,6 @@ struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
728}; 728};
729#endif 729#endif
730 730
731#ifdef CONFIG_LEDS
732#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
733
734static void versatile_leds_event(led_event_t ledevt)
735{
736 unsigned long flags;
737 u32 val;
738
739 local_irq_save(flags);
740 val = readl(VA_LEDS_BASE);
741
742 switch (ledevt) {
743 case led_idle_start:
744 val = val & ~VERSATILE_SYS_LED0;
745 break;
746
747 case led_idle_end:
748 val = val | VERSATILE_SYS_LED0;
749 break;
750
751 case led_timer:
752 val = val ^ VERSATILE_SYS_LED1;
753 break;
754
755 case led_halted:
756 val = 0;
757 break;
758
759 default:
760 break;
761 }
762
763 writel(val, VA_LEDS_BASE);
764 local_irq_restore(flags);
765}
766#endif /* CONFIG_LEDS */
767
768void versatile_restart(enum reboot_mode mode, const char *cmd) 731void versatile_restart(enum reboot_mode mode, const char *cmd)
769{ 732{
770 void __iomem *sys = __io_address(VERSATILE_SYS_BASE); 733 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/plat-iop/pmu.c
index ad9f9744a82d..c6d979ace524 100644
--- a/arch/arm/plat-iop/pmu.c
+++ b/arch/arm/plat-iop/pmu.c
@@ -24,7 +24,7 @@ static struct resource pmu_resource = {
24}; 24};
25 25
26static struct platform_device pmu_device = { 26static struct platform_device pmu_device = {
27 .name = "arm-pmu", 27 .name = "xscale-pmu",
28 .id = -1, 28 .id = -1,
29 .resource = &pmu_resource, 29 .resource = &pmu_resource,
30 .num_resources = 1, 30 .num_resources = 1,
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 24770e5a5081..6416e03b4482 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -151,14 +151,6 @@ static int omap_dma_in_1510_mode(void)
151#endif 151#endif
152 152
153#ifdef CONFIG_ARCH_OMAP1 153#ifdef CONFIG_ARCH_OMAP1
154static inline int get_gdma_dev(int req)
155{
156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157 int shift = ((req - 1) % 5) * 6;
158
159 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
160}
161
162static inline void set_gdma_dev(int req, int dev) 154static inline void set_gdma_dev(int req, int dev)
163{ 155{
164 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; 156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 9bd2776e7d05..cb8e3d655d1a 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -236,13 +236,6 @@ config S3C_SETUP_CAMIF
236 help 236 help
237 Compile in common setup code for S3C CAMIF devices 237 Compile in common setup code for S3C CAMIF devices
238 238
239# DMA
240
241config S3C_DMA
242 bool
243 help
244 Internal configuration for S3C DMA core
245
246config SAMSUNG_PM_GPIO 239config SAMSUNG_PM_GPIO
247 bool 240 bool
248 default y if GPIO_SAMSUNG && PM 241 default y if GPIO_SAMSUNG && PM
@@ -250,14 +243,6 @@ config SAMSUNG_PM_GPIO
250 Include legacy GPIO power management code for platforms not using 243 Include legacy GPIO power management code for platforms not using
251 pinctrl-samsung driver. 244 pinctrl-samsung driver.
252 245
253config SAMSUNG_DMADEV
254 bool "Use legacy Samsung DMA abstraction"
255 depends on CPU_S5PV210 || ARCH_S3C64XX
256 select DMADEVICES
257 default y
258 help
259 Use DMA device engine for PL330 DMAC.
260
261endif 246endif
262 247
263config S5P_DEV_MFC 248config S5P_DEV_MFC
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 87746c37f030..1a29ab1f446d 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -26,12 +26,6 @@ obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
26 26
27obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o 27obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o
28 28
29# DMA support
30
31obj-$(CONFIG_S3C_DMA) += dma.o s3c-dma-ops.o
32
33obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o
34
35# PM support 29# PM support
36 30
37obj-$(CONFIG_PM_SLEEP) += pm-common.o 31obj-$(CONFIG_PM_SLEEP) += pm-common.o
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
deleted file mode 100644
index 886326ee6f6c..000000000000
--- a/arch/arm/plat-samsung/dma-ops.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/* linux/arch/arm/plat-samsung/dma-ops.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung DMA Operations
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/amba/pl330.h>
16#include <linux/scatterlist.h>
17#include <linux/export.h>
18
19#include <mach/dma.h>
20
21#if defined(CONFIG_PL330_DMA)
22#define dma_filter pl330_filter
23#elif defined(CONFIG_S3C64XX_PL080)
24#define dma_filter pl08x_filter_id
25#endif
26
27static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
28 struct samsung_dma_req *param,
29 struct device *dev, char *ch_name)
30{
31 dma_cap_mask_t mask;
32
33 dma_cap_zero(mask);
34 dma_cap_set(param->cap, mask);
35
36 if (dev->of_node)
37 return (unsigned)dma_request_slave_channel(dev, ch_name);
38 else
39 return (unsigned)dma_request_channel(mask, dma_filter,
40 (void *)dma_ch);
41}
42
43static int samsung_dmadev_release(unsigned ch, void *param)
44{
45 dma_release_channel((struct dma_chan *)ch);
46
47 return 0;
48}
49
50static int samsung_dmadev_config(unsigned ch,
51 struct samsung_dma_config *param)
52{
53 struct dma_chan *chan = (struct dma_chan *)ch;
54 struct dma_slave_config slave_config;
55
56 if (param->direction == DMA_DEV_TO_MEM) {
57 memset(&slave_config, 0, sizeof(struct dma_slave_config));
58 slave_config.direction = param->direction;
59 slave_config.src_addr = param->fifo;
60 slave_config.src_addr_width = param->width;
61 slave_config.src_maxburst = 1;
62 dmaengine_slave_config(chan, &slave_config);
63 } else if (param->direction == DMA_MEM_TO_DEV) {
64 memset(&slave_config, 0, sizeof(struct dma_slave_config));
65 slave_config.direction = param->direction;
66 slave_config.dst_addr = param->fifo;
67 slave_config.dst_addr_width = param->width;
68 slave_config.dst_maxburst = 1;
69 dmaengine_slave_config(chan, &slave_config);
70 } else {
71 pr_warn("unsupported direction\n");
72 return -EINVAL;
73 }
74
75 return 0;
76}
77
78static int samsung_dmadev_prepare(unsigned ch,
79 struct samsung_dma_prep *param)
80{
81 struct scatterlist sg;
82 struct dma_chan *chan = (struct dma_chan *)ch;
83 struct dma_async_tx_descriptor *desc;
84
85 switch (param->cap) {
86 case DMA_SLAVE:
87 sg_init_table(&sg, 1);
88 sg_dma_len(&sg) = param->len;
89 sg_set_page(&sg, pfn_to_page(PFN_DOWN(param->buf)),
90 param->len, offset_in_page(param->buf));
91 sg_dma_address(&sg) = param->buf;
92
93 desc = dmaengine_prep_slave_sg(chan,
94 &sg, 1, param->direction, DMA_PREP_INTERRUPT);
95 break;
96 case DMA_CYCLIC:
97 desc = dmaengine_prep_dma_cyclic(chan, param->buf,
98 param->len, param->period, param->direction,
99 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
100 break;
101 default:
102 dev_err(&chan->dev->device, "unsupported format\n");
103 return -EFAULT;
104 }
105
106 if (!desc) {
107 dev_err(&chan->dev->device, "cannot prepare cyclic dma\n");
108 return -EFAULT;
109 }
110
111 desc->callback = param->fp;
112 desc->callback_param = param->fp_param;
113
114 dmaengine_submit((struct dma_async_tx_descriptor *)desc);
115
116 return 0;
117}
118
119static inline int samsung_dmadev_trigger(unsigned ch)
120{
121 dma_async_issue_pending((struct dma_chan *)ch);
122
123 return 0;
124}
125
126static inline int samsung_dmadev_flush(unsigned ch)
127{
128 return dmaengine_terminate_all((struct dma_chan *)ch);
129}
130
131static struct samsung_dma_ops dmadev_ops = {
132 .request = samsung_dmadev_request,
133 .release = samsung_dmadev_release,
134 .config = samsung_dmadev_config,
135 .prepare = samsung_dmadev_prepare,
136 .trigger = samsung_dmadev_trigger,
137 .started = NULL,
138 .flush = samsung_dmadev_flush,
139 .stop = samsung_dmadev_flush,
140};
141
142void *samsung_dmadev_get_ops(void)
143{
144 return &dmadev_ops;
145}
146EXPORT_SYMBOL(samsung_dmadev_get_ops);
diff --git a/arch/arm/plat-samsung/dma.c b/arch/arm/plat-samsung/dma.c
deleted file mode 100644
index 6143aa147688..000000000000
--- a/arch/arm/plat-samsung/dma.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/* linux/arch/arm/plat-samsung/dma.c
2 *
3 * Copyright (c) 2003-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C DMA core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14struct s3c2410_dma_buf;
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/errno.h>
19
20#include <mach/dma.h>
21#include <mach/irqs.h>
22
23/* dma channel state information */
24struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
25struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
26
27/* s3c_dma_lookup_channel
28 *
29 * change the dma channel number given into a real dma channel id
30*/
31
32struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
33{
34 if (channel & DMACH_LOW_LEVEL)
35 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
36 else
37 return s3c_dma_chan_map[channel];
38}
39
40/* do we need to protect the settings of the fields from
41 * irq?
42*/
43
44int s3c2410_dma_set_opfn(enum dma_ch channel, s3c2410_dma_opfn_t rtn)
45{
46 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
47
48 if (chan == NULL)
49 return -EINVAL;
50
51 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
52
53 chan->op_fn = rtn;
54
55 return 0;
56}
57EXPORT_SYMBOL(s3c2410_dma_set_opfn);
58
59int s3c2410_dma_set_buffdone_fn(enum dma_ch channel, s3c2410_dma_cbfn_t rtn)
60{
61 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
62
63 if (chan == NULL)
64 return -EINVAL;
65
66 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
67
68 chan->callback_fn = rtn;
69
70 return 0;
71}
72EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
73
74int s3c2410_dma_setflags(enum dma_ch channel, unsigned int flags)
75{
76 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
77
78 if (chan == NULL)
79 return -EINVAL;
80
81 chan->flags = flags;
82 return 0;
83}
84EXPORT_SYMBOL(s3c2410_dma_setflags);
diff --git a/arch/arm/plat-samsung/include/plat/dma-core.h b/arch/arm/plat-samsung/include/plat/dma-core.h
deleted file mode 100644
index 32ff2a92cb3c..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma-core.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Samsung S3C DMA core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
16
17extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
18
19/* the currently allocated channel information */
20extern struct s3c2410_dma_chan s3c2410_chans[];
21
22
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
deleted file mode 100644
index ce6d7634b6cb..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/dma-ops.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __SAMSUNG_DMA_OPS_H_
14#define __SAMSUNG_DMA_OPS_H_ __FILE__
15
16#include <linux/dmaengine.h>
17#include <mach/dma.h>
18
19struct samsung_dma_req {
20 enum dma_transaction_type cap;
21 struct s3c2410_dma_client *client;
22};
23
24struct samsung_dma_prep {
25 enum dma_transaction_type cap;
26 enum dma_transfer_direction direction;
27 dma_addr_t buf;
28 unsigned long period;
29 unsigned long len;
30 void (*fp)(void *data);
31 void *fp_param;
32};
33
34struct samsung_dma_config {
35 enum dma_transfer_direction direction;
36 enum dma_slave_buswidth width;
37 dma_addr_t fifo;
38};
39
40struct samsung_dma_ops {
41 unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param,
42 struct device *dev, char *ch_name);
43 int (*release)(unsigned ch, void *param);
44 int (*config)(unsigned ch, struct samsung_dma_config *param);
45 int (*prepare)(unsigned ch, struct samsung_dma_prep *param);
46 int (*trigger)(unsigned ch);
47 int (*started)(unsigned ch);
48 int (*flush)(unsigned ch);
49 int (*stop)(unsigned ch);
50};
51
52extern void *samsung_dmadev_get_ops(void);
53extern void *s3c_dma_get_ops(void);
54
55static inline void *__samsung_dma_get_ops(void)
56{
57 if (samsung_dma_is_dmadev())
58 return samsung_dmadev_get_ops();
59 else
60 return s3c_dma_get_ops();
61}
62
63/*
64 * samsung_dma_get_ops
65 * get the set of samsung dma operations
66 */
67#define samsung_dma_get_ops() __samsung_dma_get_ops()
68
69#endif /* __SAMSUNG_DMA_OPS_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
deleted file mode 100644
index abe07fae71db..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#ifndef __DMA_PL330_H_
12#define __DMA_PL330_H_ __FILE__
13
14/*
15 * PL330 can assign any channel to communicate with
16 * any of the peripherals attched to the DMAC.
17 * For the sake of consistency across client drivers,
18 * We keep the channel names unchanged and only add
19 * missing peripherals are added.
20 * Order is not important since DMA PL330 API driver
21 * use these just as IDs.
22 */
23enum dma_ch {
24 DMACH_UART0_RX = 0,
25 DMACH_UART0_TX,
26 DMACH_UART1_RX,
27 DMACH_UART1_TX,
28 DMACH_UART2_RX,
29 DMACH_UART2_TX,
30 DMACH_UART3_RX,
31 DMACH_UART3_TX,
32 DMACH_UART4_RX,
33 DMACH_UART4_TX,
34 DMACH_UART5_RX,
35 DMACH_UART5_TX,
36 DMACH_USI_RX,
37 DMACH_USI_TX,
38 DMACH_IRDA,
39 DMACH_I2S0_RX,
40 DMACH_I2S0_TX,
41 DMACH_I2S0S_TX,
42 DMACH_I2S1_RX,
43 DMACH_I2S1_TX,
44 DMACH_I2S2_RX,
45 DMACH_I2S2_TX,
46 DMACH_SPI0_RX,
47 DMACH_SPI0_TX,
48 DMACH_SPI1_RX,
49 DMACH_SPI1_TX,
50 DMACH_SPI2_RX,
51 DMACH_SPI2_TX,
52 DMACH_AC97_MICIN,
53 DMACH_AC97_PCMIN,
54 DMACH_AC97_PCMOUT,
55 DMACH_EXTERNAL,
56 DMACH_PWM,
57 DMACH_SPDIF,
58 DMACH_HSI_RX,
59 DMACH_HSI_TX,
60 DMACH_PCM0_TX,
61 DMACH_PCM0_RX,
62 DMACH_PCM1_TX,
63 DMACH_PCM1_RX,
64 DMACH_PCM2_TX,
65 DMACH_PCM2_RX,
66 DMACH_MSM_REQ3,
67 DMACH_MSM_REQ2,
68 DMACH_MSM_REQ1,
69 DMACH_MSM_REQ0,
70 DMACH_SLIMBUS0_RX,
71 DMACH_SLIMBUS0_TX,
72 DMACH_SLIMBUS0AUX_RX,
73 DMACH_SLIMBUS0AUX_TX,
74 DMACH_SLIMBUS1_RX,
75 DMACH_SLIMBUS1_TX,
76 DMACH_SLIMBUS2_RX,
77 DMACH_SLIMBUS2_TX,
78 DMACH_SLIMBUS3_RX,
79 DMACH_SLIMBUS3_TX,
80 DMACH_SLIMBUS4_RX,
81 DMACH_SLIMBUS4_TX,
82 DMACH_SLIMBUS5_RX,
83 DMACH_SLIMBUS5_TX,
84 DMACH_MIPI_HSI0,
85 DMACH_MIPI_HSI1,
86 DMACH_MIPI_HSI2,
87 DMACH_MIPI_HSI3,
88 DMACH_MIPI_HSI4,
89 DMACH_MIPI_HSI5,
90 DMACH_MIPI_HSI6,
91 DMACH_MIPI_HSI7,
92 DMACH_DISP1,
93 DMACH_MTOM_0,
94 DMACH_MTOM_1,
95 DMACH_MTOM_2,
96 DMACH_MTOM_3,
97 DMACH_MTOM_4,
98 DMACH_MTOM_5,
99 DMACH_MTOM_6,
100 DMACH_MTOM_7,
101 /* END Marker, also used to denote a reserved channel */
102 DMACH_MAX,
103};
104
105struct s3c2410_dma_client {
106 char *name;
107};
108
109static inline bool samsung_dma_has_circular(void)
110{
111 return true;
112}
113
114static inline bool samsung_dma_is_dmadev(void)
115{
116 return true;
117}
118
119#include <plat/dma-ops.h>
120
121#endif /* __DMA_PL330_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
deleted file mode 100644
index bd3a6db14cbb..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support - per SoC functions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <plat/dma-core.h>
14
15extern struct bus_type dma_subsys;
16extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
17
18#define DMA_CH_VALID (1<<31)
19#define DMA_CH_NEVER (1<<30)
20
21/* struct s3c24xx_dma_map
22 *
23 * this holds the mapping information for the channel selected
24 * to be connected to the specified device
25*/
26
27struct s3c24xx_dma_map {
28 const char *name;
29
30 unsigned long channels[S3C_DMA_CHANNELS];
31};
32
33struct s3c24xx_dma_selection {
34 struct s3c24xx_dma_map *map;
35 unsigned long map_size;
36 unsigned long dcon_mask;
37
38 void (*select)(struct s3c2410_dma_chan *chan,
39 struct s3c24xx_dma_map *map);
40};
41
42extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
43
44/* struct s3c24xx_dma_order_ch
45 *
46 * channel map for one of the `enum dma_ch` dma channels. the list
47 * entry contains a set of low-level channel numbers, orred with
48 * DMA_CH_VALID, which are checked in the order in the array.
49*/
50
51struct s3c24xx_dma_order_ch {
52 unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
53 unsigned int flags; /* flags */
54};
55
56/* struct s3c24xx_dma_order
57 *
58 * information provided by either the core or the board to give the
59 * dma system a hint on how to allocate channels
60*/
61
62struct s3c24xx_dma_order {
63 struct s3c24xx_dma_order_ch channels[DMACH_MAX];
64};
65
66extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
67
68/* DMA init code, called from the cpu support code */
69
70extern int s3c2410_dma_init(void);
71
72extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
73 unsigned int stride);
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
deleted file mode 100644
index 7b02143ccd9a..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma.h
+++ /dev/null
@@ -1,130 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_DMA_H
14#define __PLAT_DMA_H
15
16#include <linux/dma-mapping.h>
17
18enum s3c2410_dma_buffresult {
19 S3C2410_RES_OK,
20 S3C2410_RES_ERR,
21 S3C2410_RES_ABORT
22};
23
24/* enum s3c2410_chan_op
25 *
26 * operation codes passed to the DMA code by the user, and also used
27 * to inform the current channel owner of any changes to the system state
28*/
29
30enum s3c2410_chan_op {
31 S3C2410_DMAOP_START,
32 S3C2410_DMAOP_STOP,
33 S3C2410_DMAOP_PAUSE,
34 S3C2410_DMAOP_RESUME,
35 S3C2410_DMAOP_FLUSH,
36 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
37 S3C2410_DMAOP_STARTED, /* indicate channel started */
38};
39
40struct s3c2410_dma_client {
41 char *name;
42};
43
44struct s3c2410_dma_chan;
45enum dma_ch;
46
47/* s3c2410_dma_cbfn_t
48 *
49 * buffer callback routine type
50*/
51
52typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
53 void *buf, int size,
54 enum s3c2410_dma_buffresult result);
55
56typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
57 enum s3c2410_chan_op );
58
59
60
61/* s3c2410_dma_request
62 *
63 * request a dma channel exclusivley
64*/
65
66extern int s3c2410_dma_request(enum dma_ch channel,
67 struct s3c2410_dma_client *, void *dev);
68
69
70/* s3c2410_dma_ctrl
71 *
72 * change the state of the dma channel
73*/
74
75extern int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op);
76
77/* s3c2410_dma_setflags
78 *
79 * set the channel's flags to a given state
80*/
81
82extern int s3c2410_dma_setflags(enum dma_ch channel,
83 unsigned int flags);
84
85/* s3c2410_dma_free
86 *
87 * free the dma channel (will also abort any outstanding operations)
88*/
89
90extern int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *);
91
92/* s3c2410_dma_enqueue
93 *
94 * place the given buffer onto the queue of operations for the channel.
95 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
96 * drained before the buffer is given to the DMA system.
97*/
98
99extern int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
100 dma_addr_t data, int size);
101
102/* s3c2410_dma_config
103 *
104 * configure the dma channel
105*/
106
107extern int s3c2410_dma_config(enum dma_ch channel, int xferunit);
108
109/* s3c2410_dma_devconfig
110 *
111 * configure the device we're talking to
112*/
113
114extern int s3c2410_dma_devconfig(enum dma_ch channel,
115 enum dma_data_direction source, unsigned long devaddr);
116
117/* s3c2410_dma_getposition
118 *
119 * get the position that the dma transfer is currently at
120*/
121
122extern int s3c2410_dma_getposition(enum dma_ch channel,
123 dma_addr_t *src, dma_addr_t *dest);
124
125extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn);
126extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn);
127
128#include <plat/dma-ops.h>
129
130#endif
diff --git a/arch/arm/plat-samsung/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h
deleted file mode 100644
index a7d622ef16af..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-dma.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/regs-dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_REGS_DMA_H
14#define __ASM_PLAT_REGS_DMA_H __FILE__
15
16#define S3C2410_DMA_DISRC (0x00)
17#define S3C2410_DMA_DISRCC (0x04)
18#define S3C2410_DMA_DIDST (0x08)
19#define S3C2410_DMA_DIDSTC (0x0C)
20#define S3C2410_DMA_DCON (0x10)
21#define S3C2410_DMA_DSTAT (0x14)
22#define S3C2410_DMA_DCSRC (0x18)
23#define S3C2410_DMA_DCDST (0x1C)
24#define S3C2410_DMA_DMASKTRIG (0x20)
25#define S3C2412_DMA_DMAREQSEL (0x24)
26#define S3C2443_DMA_DMAREQSEL (0x24)
27
28#define S3C2410_DISRCC_INC (1 << 0)
29#define S3C2410_DISRCC_APB (1 << 1)
30
31#define S3C2410_DMASKTRIG_STOP (1 << 2)
32#define S3C2410_DMASKTRIG_ON (1 << 1)
33#define S3C2410_DMASKTRIG_SWTRIG (1 << 0)
34
35#define S3C2410_DCON_DEMAND (0 << 31)
36#define S3C2410_DCON_HANDSHAKE (1 << 31)
37#define S3C2410_DCON_SYNC_PCLK (0 << 30)
38#define S3C2410_DCON_SYNC_HCLK (1 << 30)
39
40#define S3C2410_DCON_INTREQ (1 << 29)
41
42#define S3C2410_DCON_CH0_XDREQ0 (0 << 24)
43#define S3C2410_DCON_CH0_UART0 (1 << 24)
44#define S3C2410_DCON_CH0_SDI (2 << 24)
45#define S3C2410_DCON_CH0_TIMER (3 << 24)
46#define S3C2410_DCON_CH0_USBEP1 (4 << 24)
47
48#define S3C2410_DCON_CH1_XDREQ1 (0 << 24)
49#define S3C2410_DCON_CH1_UART1 (1 << 24)
50#define S3C2410_DCON_CH1_I2SSDI (2 << 24)
51#define S3C2410_DCON_CH1_SPI (3 << 24)
52#define S3C2410_DCON_CH1_USBEP2 (4 << 24)
53
54#define S3C2410_DCON_CH2_I2SSDO (0 << 24)
55#define S3C2410_DCON_CH2_I2SSDI (1 << 24)
56#define S3C2410_DCON_CH2_SDI (2 << 24)
57#define S3C2410_DCON_CH2_TIMER (3 << 24)
58#define S3C2410_DCON_CH2_USBEP3 (4 << 24)
59
60#define S3C2410_DCON_CH3_UART2 (0 << 24)
61#define S3C2410_DCON_CH3_SDI (1 << 24)
62#define S3C2410_DCON_CH3_SPI (2 << 24)
63#define S3C2410_DCON_CH3_TIMER (3 << 24)
64#define S3C2410_DCON_CH3_USBEP4 (4 << 24)
65
66#define S3C2410_DCON_SRCSHIFT (24)
67#define S3C2410_DCON_SRCMASK (7 << 24)
68
69#define S3C2410_DCON_BYTE (0 << 20)
70#define S3C2410_DCON_HALFWORD (1 << 20)
71#define S3C2410_DCON_WORD (2 << 20)
72
73#define S3C2410_DCON_AUTORELOAD (0 << 22)
74#define S3C2410_DCON_NORELOAD (1 << 22)
75#define S3C2410_DCON_HWTRIG (1 << 23)
76
77#ifdef CONFIG_CPU_S3C2440
78
79#define S3C2440_DIDSTC_CHKINT (1 << 2)
80
81#define S3C2440_DCON_CH0_I2SSDO (5 << 24)
82#define S3C2440_DCON_CH0_PCMIN (6 << 24)
83
84#define S3C2440_DCON_CH1_PCMOUT (5 << 24)
85#define S3C2440_DCON_CH1_SDI (6 << 24)
86
87#define S3C2440_DCON_CH2_PCMIN (5 << 24)
88#define S3C2440_DCON_CH2_MICIN (6 << 24)
89
90#define S3C2440_DCON_CH3_MICIN (5 << 24)
91#define S3C2440_DCON_CH3_PCMOUT (6 << 24)
92#endif /* CONFIG_CPU_S3C2440 */
93
94#ifdef CONFIG_CPU_S3C2412
95
96#define S3C2412_DMAREQSEL_SRC(x) ((x) << 1)
97
98#define S3C2412_DMAREQSEL_HW (1)
99
100#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
101#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
102#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
103#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
104#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
105#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
106#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
107#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
108#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
109#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
110#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
111#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
112#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
113#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
114#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
115#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
116#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
117#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
118#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
119#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
120#endif /* CONFIG_CPU_S3C2412 */
121
122#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
123
124#define S3C2443_DMAREQSEL_SRC(x) ((x) << 1)
125
126#define S3C2443_DMAREQSEL_HW (1)
127
128#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
129#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
130#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
131#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
132#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
133#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
134#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
135#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
136#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
137#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
138#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
139#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
140#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
141#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
142#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
143#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
144#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
145#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
146#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
147#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
148#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
149#endif /* CONFIG_CPU_S3C2443 */
150
151#endif /* __ASM_PLAT_REGS_DMA_H */
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c
deleted file mode 100644
index 98b10ba67dc7..000000000000
--- a/arch/arm/plat-samsung/s3c-dma-ops.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/* linux/arch/arm/plat-samsung/s3c-dma-ops.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung S3C-DMA Operations
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/slab.h>
16#include <linux/types.h>
17#include <linux/export.h>
18
19#include <mach/dma.h>
20
21struct cb_data {
22 void (*fp) (void *);
23 void *fp_param;
24 unsigned ch;
25 struct list_head node;
26};
27
28static LIST_HEAD(dma_list);
29
30static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param,
31 int size, enum s3c2410_dma_buffresult res)
32{
33 struct cb_data *data = param;
34
35 data->fp(data->fp_param);
36}
37
38static unsigned s3c_dma_request(enum dma_ch dma_ch,
39 struct samsung_dma_req *param,
40 struct device *dev, char *ch_name)
41{
42 struct cb_data *data;
43
44 if (s3c2410_dma_request(dma_ch, param->client, NULL) < 0) {
45 s3c2410_dma_free(dma_ch, param->client);
46 return 0;
47 }
48
49 if (param->cap == DMA_CYCLIC)
50 s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR);
51
52 data = kzalloc(sizeof(struct cb_data), GFP_KERNEL);
53 data->ch = dma_ch;
54 list_add_tail(&data->node, &dma_list);
55
56 return (unsigned)dma_ch;
57}
58
59static int s3c_dma_release(unsigned ch, void *param)
60{
61 struct cb_data *data;
62
63 list_for_each_entry(data, &dma_list, node)
64 if (data->ch == ch)
65 break;
66 list_del(&data->node);
67
68 s3c2410_dma_free(ch, param);
69 kfree(data);
70
71 return 0;
72}
73
74static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param)
75{
76 s3c2410_dma_devconfig(ch, param->direction, param->fifo);
77 s3c2410_dma_config(ch, param->width);
78
79 return 0;
80}
81
82static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param)
83{
84 struct cb_data *data;
85 dma_addr_t pos = param->buf;
86 dma_addr_t end = param->buf + param->len;
87
88 list_for_each_entry(data, &dma_list, node)
89 if (data->ch == ch)
90 break;
91
92 if (!data->fp) {
93 s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb);
94 data->fp = param->fp;
95 data->fp_param = param->fp_param;
96 }
97
98 if (param->cap != DMA_CYCLIC) {
99 s3c2410_dma_enqueue(ch, (void *)data, param->buf, param->len);
100 return 0;
101 }
102
103 while (pos < end) {
104 s3c2410_dma_enqueue(ch, (void *)data, pos, param->period);
105 pos += param->period;
106 }
107
108 return 0;
109}
110
111static inline int s3c_dma_trigger(unsigned ch)
112{
113 return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_START);
114}
115
116static inline int s3c_dma_started(unsigned ch)
117{
118 return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STARTED);
119}
120
121static inline int s3c_dma_flush(unsigned ch)
122{
123 return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_FLUSH);
124}
125
126static inline int s3c_dma_stop(unsigned ch)
127{
128 return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STOP);
129}
130
131static struct samsung_dma_ops s3c_dma_ops = {
132 .request = s3c_dma_request,
133 .release = s3c_dma_release,
134 .config = s3c_dma_config,
135 .prepare = s3c_dma_prepare,
136 .trigger = s3c_dma_trigger,
137 .started = s3c_dma_started,
138 .flush = s3c_dma_flush,
139 .stop = s3c_dma_stop,
140};
141
142void *s3c_dma_get_ops(void)
143{
144 return &s3c_dma_ops;
145}
146EXPORT_SYMBOL(s3c_dma_get_ops);
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f2b2c4e87aef..faf30a4e642b 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -184,7 +184,7 @@ config TEGRA20_APB_DMA
184 184
185config S3C24XX_DMAC 185config S3C24XX_DMAC
186 tristate "Samsung S3C24XX DMA support" 186 tristate "Samsung S3C24XX DMA support"
187 depends on ARCH_S3C24XX && !S3C24XX_DMA 187 depends on ARCH_S3C24XX
188 select DMA_ENGINE 188 select DMA_ENGINE
189 select DMA_VIRTUAL_CHANNELS 189 select DMA_VIRTUAL_CHANNELS
190 help 190 help
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 0cf2e1d9cb17..cedb41c95dae 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1242,34 +1242,6 @@ config RTC_DRV_AT91SAM9
1242 probably want to use the real RTC block instead of the "RTT as an 1242 probably want to use the real RTC block instead of the "RTT as an
1243 RTC" driver. 1243 RTC" driver.
1244 1244
1245config RTC_DRV_AT91SAM9_RTT
1246 int
1247 range 0 1
1248 default 0
1249 depends on RTC_DRV_AT91SAM9
1250 help
1251 This option is only relevant for legacy board support and
1252 won't be used when booting a DT board.
1253
1254 More than one RTT module is available. You can choose which
1255 one will be used as an RTC. The default of zero is normally
1256 OK to use, though some systems use that for non-RTC purposes.
1257
1258config RTC_DRV_AT91SAM9_GPBR
1259 int
1260 range 0 3
1261 default 0
1262 prompt "Backup Register Number"
1263 depends on RTC_DRV_AT91SAM9
1264 help
1265 This option is only relevant for legacy board support and
1266 won't be used when booting a DT board.
1267
1268 The RTC driver needs to use one of the General Purpose Backup
1269 Registers (GPBRs) as well as the RTT. You can choose which one
1270 will be used. The default of zero is normally OK to use, but
1271 on some systems other software needs to use that register.
1272
1273config RTC_DRV_AU1XXX 1245config RTC_DRV_AU1XXX
1274 tristate "Au1xxx Counter0 RTC support" 1246 tristate "Au1xxx Counter0 RTC support"
1275 depends on MIPS_ALCHEMY 1247 depends on MIPS_ALCHEMY