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-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi5
-rw-r--r--arch/arm/boot/dts/tegra124-jetson-tk1.dts98
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-big.dts1136
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts18
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi100
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi5
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi5
8 files changed, 1357 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index efd089988454..9706262020f1 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -454,6 +454,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
454 tegra114-roth.dtb \ 454 tegra114-roth.dtb \
455 tegra114-tn7.dtb \ 455 tegra114-tn7.dtb \
456 tegra124-jetson-tk1.dtb \ 456 tegra124-jetson-tk1.dtb \
457 tegra124-nyan-big.dtb \
457 tegra124-venice2.dtb 458 tegra124-venice2.dtb
458dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb 459dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
459dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ 460dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 80b8eddb4105..2ca9c1807f72 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -157,6 +157,11 @@
157 #reset-cells = <1>; 157 #reset-cells = <1>;
158 }; 158 };
159 159
160 flow-controller@60007000 {
161 compatible = "nvidia,tegra114-flowctrl";
162 reg = <0x60007000 0x1000>;
163 };
164
160 apbdma: dma@6000a000 { 165 apbdma: dma@6000a000 {
161 compatible = "nvidia,tegra114-apbdma"; 166 compatible = "nvidia,tegra114-apbdma";
162 reg = <0x6000a000 0x1400>; 167 reg = <0x6000a000 0x1400>;
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 624b0fba2d0a..029c9a021541 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -16,6 +16,26 @@
16 reg = <0x0 0x80000000 0x0 0x80000000>; 16 reg = <0x0 0x80000000 0x0 0x80000000>;
17 }; 17 };
18 18
19 pcie-controller@0,01003000 {
20 status = "okay";
21
22 avddio-pex-supply = <&vdd_1v05_run>;
23 dvddio-pex-supply = <&vdd_1v05_run>;
24 avdd-pex-pll-supply = <&vdd_1v05_run>;
25 hvdd-pex-supply = <&vdd_3v3_lp0>;
26 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
27 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
28 avdd-pll-erefe-supply = <&avdd_1v05_run>;
29
30 pci@1,0 {
31 status = "okay";
32 };
33
34 pci@2,0 {
35 status = "okay";
36 };
37 };
38
19 host1x@0,50000000 { 39 host1x@0,50000000 {
20 hdmi@0,54280000 { 40 hdmi@0,54280000 {
21 status = "okay"; 41 status = "okay";
@@ -31,10 +51,10 @@
31 }; 51 };
32 52
33 pinmux: pinmux@0,70000868 { 53 pinmux: pinmux@0,70000868 {
34 pinctrl-names = "default"; 54 pinctrl-names = "boot";
35 pinctrl-0 = <&state_default>; 55 pinctrl-0 = <&state_boot>;
36 56
37 state_default: pinmux { 57 state_boot: pinmux {
38 clk_32k_out_pa0 { 58 clk_32k_out_pa0 {
39 nvidia,pins = "clk_32k_out_pa0"; 59 nvidia,pins = "clk_32k_out_pa0";
40 nvidia,function = "soc"; 60 nvidia,function = "soc";
@@ -1231,6 +1251,41 @@
1231 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1232 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1252 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1233 }; 1253 };
1254 pex_l0_rst_n_pdd1 {
1255 nvidia,pins = "pex_l0_rst_n_pdd1";
1256 nvidia,function = "pe0";
1257 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1259 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1260 };
1261 pex_l0_clkreq_n_pdd2 {
1262 nvidia,pins = "pex_l0_clkreq_n_pdd2";
1263 nvidia,function = "pe0";
1264 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1265 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1266 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1267 };
1268 pex_wake_n_pdd3 {
1269 nvidia,pins = "pex_wake_n_pdd3";
1270 nvidia,function = "pe";
1271 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1272 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1273 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1274 };
1275 pex_l1_rst_n_pdd5 {
1276 nvidia,pins = "pex_l1_rst_n_pdd5";
1277 nvidia,function = "pe1";
1278 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1280 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1281 };
1282 pex_l1_clkreq_n_pdd6 {
1283 nvidia,pins = "pex_l1_clkreq_n_pdd6";
1284 nvidia,function = "pe1";
1285 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1287 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1288 };
1234 clk3_out_pee0 { 1289 clk3_out_pee0 {
1235 nvidia,pins = "clk3_out_pee0"; 1290 nvidia,pins = "clk3_out_pee0";
1236 nvidia,function = "extperiph3"; 1291 nvidia,function = "extperiph3";
@@ -1515,7 +1570,7 @@
1515 regulator-always-on; 1570 regulator-always-on;
1516 }; 1571 };
1517 1572
1518 ldo0 { 1573 avdd_1v05_run: ldo0 {
1519 regulator-name = "+1.05V_RUN_AVDD"; 1574 regulator-name = "+1.05V_RUN_AVDD";
1520 regulator-min-microvolt = <1050000>; 1575 regulator-min-microvolt = <1050000>;
1521 regulator-max-microvolt = <1050000>; 1576 regulator-max-microvolt = <1050000>;
@@ -1619,6 +1674,18 @@
1619 nvidia,sys-clock-req-active-high; 1674 nvidia,sys-clock-req-active-high;
1620 }; 1675 };
1621 1676
1677 /* Serial ATA */
1678 sata@0,70020000 {
1679 status = "okay";
1680
1681 hvdd-supply = <&vdd_3v3_lp0>;
1682 vddio-supply = <&vdd_1v05_run>;
1683 avdd-supply = <&vdd_1v05_run>;
1684
1685 target-5v-supply = <&vdd_5v0_sata>;
1686 target-12v-supply = <&vdd_12v0_sata>;
1687 };
1688
1622 padctl@0,7009f000 { 1689 padctl@0,7009f000 {
1623 pinctrl-0 = <&padctl_default>; 1690 pinctrl-0 = <&padctl_default>;
1624 pinctrl-names = "default"; 1691 pinctrl-names = "default";
@@ -1828,6 +1895,29 @@
1828 enable-active-high; 1895 enable-active-high;
1829 vin-supply = <&vdd_5v0_sys>; 1896 vin-supply = <&vdd_5v0_sys>;
1830 }; 1897 };
1898
1899 /* Molex power connector */
1900 vdd_5v0_sata: regulator@13 {
1901 compatible = "regulator-fixed";
1902 reg = <13>;
1903 regulator-name = "+5V_SATA";
1904 regulator-min-microvolt = <5000000>;
1905 regulator-max-microvolt = <5000000>;
1906 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
1907 enable-active-high;
1908 vin-supply = <&vdd_5v0_sys>;
1909 };
1910
1911 vdd_12v0_sata: regulator@14 {
1912 compatible = "regulator-fixed";
1913 reg = <14>;
1914 regulator-name = "+12V_SATA";
1915 regulator-min-microvolt = <12000000>;
1916 regulator-max-microvolt = <12000000>;
1917 gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
1918 enable-active-high;
1919 vin-supply = <&vdd_mux>;
1920 };
1831 }; 1921 };
1832 1922
1833 sound { 1923 sound {
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
new file mode 100644
index 000000000000..7d0784ce4c74
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -0,0 +1,1136 @@
1/dts-v1/;
2
3#include <dt-bindings/input/input.h>
4#include "tegra124.dtsi"
5
6/ {
7 model = "Acer Chromebook 13 CB5-311";
8 compatible = "google,nyan-big", "nvidia,tegra124";
9
10 aliases {
11 rtc0 = "/i2c@0,7000d000/pmic@40";
12 rtc1 = "/rtc@0,7000e000";
13 };
14
15 memory {
16 reg = <0x0 0x80000000 0x0 0x80000000>;
17 };
18
19 host1x@0,50000000 {
20 hdmi@0,54280000 {
21 status = "okay";
22
23 vdd-supply = <&vdd_3v3_hdmi>;
24 pll-supply = <&vdd_hdmi_pll>;
25 hdmi-supply = <&vdd_5v0_hdmi>;
26
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio =
29 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
30 };
31
32 sor@0,54540000 {
33 status = "okay";
34
35 nvidia,dpaux = <&dpaux>;
36 nvidia,panel = <&panel>;
37 };
38
39 dpaux@0,545c0000 {
40 vdd-supply = <&vdd_3v3_panel>;
41 status = "okay";
42 };
43 };
44
45 pinmux@0,70000868 {
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinmux_default>;
48
49 pinmux_default: common {
50 dap_mclk1_pw4 {
51 nvidia,pins = "dap_mclk1_pw4";
52 nvidia,function = "extperiph1";
53 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
54 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
55 nvidia,tristate = <TEGRA_PIN_DISABLE>;
56 };
57 dap2_din_pa4 {
58 nvidia,pins = "dap2_din_pa4";
59 nvidia,function = "i2s1";
60 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
61 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
62 nvidia,tristate = <TEGRA_PIN_DISABLE>;
63 };
64 dap2_dout_pa5 {
65 nvidia,pins = "dap2_dout_pa5",
66 "dap2_fs_pa2",
67 "dap2_sclk_pa3";
68 nvidia,function = "i2s1";
69 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
70 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
71 nvidia,tristate = <TEGRA_PIN_DISABLE>;
72 };
73 dvfs_pwm_px0 {
74 nvidia,pins = "dvfs_pwm_px0",
75 "dvfs_clk_px2";
76 nvidia,function = "cldvfs";
77 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 };
81 ulpi_clk_py0 {
82 nvidia,pins = "ulpi_clk_py0",
83 "ulpi_nxt_py2",
84 "ulpi_stp_py3";
85 nvidia,function = "spi1";
86 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
87 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
89 };
90 ulpi_dir_py1 {
91 nvidia,pins = "ulpi_dir_py1";
92 nvidia,function = "spi1";
93 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
94 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
96 };
97 cam_i2c_scl_pbb1 {
98 nvidia,pins = "cam_i2c_scl_pbb1",
99 "cam_i2c_sda_pbb2";
100 nvidia,function = "i2c3";
101 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
102 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 nvidia,lock = <TEGRA_PIN_DISABLE>;
105 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
106 };
107 gen2_i2c_scl_pt5 {
108 nvidia,pins = "gen2_i2c_scl_pt5",
109 "gen2_i2c_sda_pt6";
110 nvidia,function = "i2c2";
111 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 nvidia,lock = <TEGRA_PIN_DISABLE>;
115 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
116 };
117 pg4 {
118 nvidia,pins = "pg4",
119 "pg5",
120 "pg6",
121 "pi3";
122 nvidia,function = "spi4";
123 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
124 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
125 nvidia,tristate = <TEGRA_PIN_DISABLE>;
126 };
127 pg7 {
128 nvidia,pins = "pg7";
129 nvidia,function = "spi4";
130 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 };
134 ph1 {
135 nvidia,pins = "ph1";
136 nvidia,function = "pwm1";
137 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
138 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
139 nvidia,tristate = <TEGRA_PIN_DISABLE>;
140 };
141 pk0 {
142 nvidia,pins = "pk0",
143 "kb_row15_ps7",
144 "clk_32k_out_pa0";
145 nvidia,function = "soc";
146 nvidia,pull = <TEGRA_PIN_PULL_UP>;
147 nvidia,tristate = <TEGRA_PIN_DISABLE>;
148 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 };
150 sdmmc1_clk_pz0 {
151 nvidia,pins = "sdmmc1_clk_pz0";
152 nvidia,function = "sdmmc1";
153 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 };
157 sdmmc1_cmd_pz1 {
158 nvidia,pins = "sdmmc1_cmd_pz1",
159 "sdmmc1_dat0_py7",
160 "sdmmc1_dat1_py6",
161 "sdmmc1_dat2_py5",
162 "sdmmc1_dat3_py4";
163 nvidia,function = "sdmmc1";
164 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
165 nvidia,pull = <TEGRA_PIN_PULL_UP>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 };
168 sdmmc3_clk_pa6 {
169 nvidia,pins = "sdmmc3_clk_pa6";
170 nvidia,function = "sdmmc3";
171 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
172 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173 nvidia,tristate = <TEGRA_PIN_DISABLE>;
174 };
175 sdmmc3_cmd_pa7 {
176 nvidia,pins = "sdmmc3_cmd_pa7",
177 "sdmmc3_dat0_pb7",
178 "sdmmc3_dat1_pb6",
179 "sdmmc3_dat2_pb5",
180 "sdmmc3_dat3_pb4",
181 "kb_col4_pq4",
182 "sdmmc3_clk_lb_out_pee4",
183 "sdmmc3_clk_lb_in_pee5",
184 "sdmmc3_cd_n_pv2";
185 nvidia,function = "sdmmc3";
186 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
187 nvidia,pull = <TEGRA_PIN_PULL_UP>;
188 nvidia,tristate = <TEGRA_PIN_DISABLE>;
189 };
190 sdmmc4_clk_pcc4 {
191 nvidia,pins = "sdmmc4_clk_pcc4";
192 nvidia,function = "sdmmc4";
193 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
194 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
195 nvidia,tristate = <TEGRA_PIN_DISABLE>;
196 };
197 sdmmc4_cmd_pt7 {
198 nvidia,pins = "sdmmc4_cmd_pt7",
199 "sdmmc4_dat0_paa0",
200 "sdmmc4_dat1_paa1",
201 "sdmmc4_dat2_paa2",
202 "sdmmc4_dat3_paa3",
203 "sdmmc4_dat4_paa4",
204 "sdmmc4_dat5_paa5",
205 "sdmmc4_dat6_paa6",
206 "sdmmc4_dat7_paa7";
207 nvidia,function = "sdmmc4";
208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 nvidia,pull = <TEGRA_PIN_PULL_UP>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 };
212 pwr_i2c_scl_pz6 {
213 nvidia,pins = "pwr_i2c_scl_pz6",
214 "pwr_i2c_sda_pz7";
215 nvidia,function = "i2cpwr";
216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 nvidia,lock = <TEGRA_PIN_DISABLE>;
220 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
221 };
222 jtag_rtck {
223 nvidia,pins = "jtag_rtck";
224 nvidia,function = "rtck";
225 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
226 nvidia,pull = <TEGRA_PIN_PULL_UP>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 };
229 clk_32k_in {
230 nvidia,pins = "clk_32k_in";
231 nvidia,function = "clk";
232 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
233 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 };
236 core_pwr_req {
237 nvidia,pins = "core_pwr_req";
238 nvidia,function = "pwron";
239 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
242 };
243 cpu_pwr_req {
244 nvidia,pins = "cpu_pwr_req";
245 nvidia,function = "cpu";
246 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
247 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 };
250 pwr_int_n {
251 nvidia,pins = "pwr_int_n";
252 nvidia,function = "pmi";
253 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
254 nvidia,pull = <TEGRA_PIN_PULL_UP>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
256 };
257 reset_out_n {
258 nvidia,pins = "reset_out_n";
259 nvidia,function = "reset_out_n";
260 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
261 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
263 };
264 clk3_out_pee0 {
265 nvidia,pins = "clk3_out_pee0";
266 nvidia,function = "extperiph3";
267 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
270 };
271 gen1_i2c_sda_pc5 {
272 nvidia,pins = "gen1_i2c_sda_pc5",
273 "gen1_i2c_scl_pc4";
274 nvidia,function = "i2c1";
275 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
276 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
277 nvidia,tristate = <TEGRA_PIN_DISABLE>;
278 nvidia,lock = <TEGRA_PIN_DISABLE>;
279 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
280 };
281 hdmi_cec_pee3 {
282 nvidia,pins = "hdmi_cec_pee3";
283 nvidia,function = "cec";
284 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
287 nvidia,lock = <TEGRA_PIN_DISABLE>;
288 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
289 };
290 hdmi_int_pn7 {
291 nvidia,pins = "hdmi_int_pn7";
292 nvidia,function = "rsvd1";
293 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
294 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
295 nvidia,tristate = <TEGRA_PIN_DISABLE>;
296 };
297 ddc_scl_pv4 {
298 nvidia,pins = "ddc_scl_pv4",
299 "ddc_sda_pv5";
300 nvidia,function = "i2c4";
301 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
302 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 nvidia,lock = <TEGRA_PIN_DISABLE>;
305 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
306 };
307 kb_row10_ps2 {
308 nvidia,pins = "kb_row10_ps2";
309 nvidia,function = "uarta";
310 nvidia,pull = <TEGRA_PIN_PULL_UP>;
311 nvidia,tristate = <TEGRA_PIN_DISABLE>;
312 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
313 };
314 kb_row9_ps1 {
315 nvidia,pins = "kb_row9_ps1";
316 nvidia,function = "uarta";
317 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
318 nvidia,tristate = <TEGRA_PIN_DISABLE>;
319 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
320 };
321 usb_vbus_en0_pn4 {
322 nvidia,pins = "usb_vbus_en0_pn4",
323 "usb_vbus_en1_pn5";
324 nvidia,function = "usb";
325 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
326 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
327 nvidia,tristate = <TEGRA_PIN_DISABLE>;
328 nvidia,lock = <TEGRA_PIN_DISABLE>;
329 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
330 };
331 drive_sdio1 {
332 nvidia,pins = "drive_sdio1";
333 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
334 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
335 nvidia,pull-down-strength = <36>;
336 nvidia,pull-up-strength = <20>;
337 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
338 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
339 };
340 drive_sdio3 {
341 nvidia,pins = "drive_sdio3";
342 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
343 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
344 nvidia,pull-down-strength = <22>;
345 nvidia,pull-up-strength = <36>;
346 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
347 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
348 };
349 drive_gma {
350 nvidia,pins = "drive_gma";
351 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
352 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
353 nvidia,pull-down-strength = <2>;
354 nvidia,pull-up-strength = <1>;
355 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
356 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
357 nvidia,drive-type = <1>;
358 };
359 codec_irq_l {
360 nvidia,pins = "ph4";
361 nvidia,function = "gmi";
362 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
363 nvidia,tristate = <TEGRA_PIN_DISABLE>;
364 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
365 };
366 lcd_bl_en {
367 nvidia,pins = "ph2";
368 nvidia,function = "gmi";
369 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
370 nvidia,tristate = <TEGRA_PIN_DISABLE>;
371 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
372 };
373 touch_irq_l {
374 nvidia,pins = "gpio_w3_aud_pw3";
375 nvidia,function = "spi6";
376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377 nvidia,tristate = <TEGRA_PIN_DISABLE>;
378 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
379 };
380 tpm_davint_l {
381 nvidia,pins = "ph6";
382 nvidia,function = "gmi";
383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384 nvidia,tristate = <TEGRA_PIN_DISABLE>;
385 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
386 };
387 ts_irq_l {
388 nvidia,pins = "pk2";
389 nvidia,function = "gmi";
390 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
391 nvidia,tristate = <TEGRA_PIN_DISABLE>;
392 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
393 };
394 ts_reset_l {
395 nvidia,pins = "pk4";
396 nvidia,function = "gmi";
397 nvidia,pull = <TEGRA_PIN_PULL_UP>;
398 nvidia,tristate = <TEGRA_PIN_DISABLE>;
399 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
400 };
401 ts_shdn_l {
402 nvidia,pins = "pk1";
403 nvidia,function = "gmi";
404 nvidia,pull = <TEGRA_PIN_PULL_UP>;
405 nvidia,tristate = <TEGRA_PIN_DISABLE>;
406 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
407 };
408 ph7 {
409 nvidia,pins = "ph7";
410 nvidia,function = "gmi";
411 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
414 };
415 kb_col0_ap {
416 nvidia,pins = "kb_col0_pq0";
417 nvidia,function = "rsvd4";
418 nvidia,pull = <TEGRA_PIN_PULL_UP>;
419 nvidia,tristate = <TEGRA_PIN_DISABLE>;
420 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
421 };
422 lid_open {
423 nvidia,pins = "kb_row4_pr4";
424 nvidia,function = "rsvd3";
425 nvidia,pull = <TEGRA_PIN_PULL_UP>;
426 nvidia,tristate = <TEGRA_PIN_DISABLE>;
427 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
428 };
429 en_vdd_sd {
430 nvidia,pins = "kb_row0_pr0";
431 nvidia,function = "rsvd4";
432 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
433 nvidia,tristate = <TEGRA_PIN_DISABLE>;
434 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
435 };
436 ac_ok {
437 nvidia,pins = "pj0";
438 nvidia,function = "gmi";
439 nvidia,pull = <TEGRA_PIN_PULL_UP>;
440 nvidia,tristate = <TEGRA_PIN_DISABLE>;
441 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
442 };
443 sensor_irq_l {
444 nvidia,pins = "pi6";
445 nvidia,function = "gmi";
446 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
447 nvidia,tristate = <TEGRA_PIN_DISABLE>;
448 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
449 };
450 wifi_en {
451 nvidia,pins = "gpio_x7_aud_px7";
452 nvidia,function = "rsvd4";
453 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454 nvidia,tristate = <TEGRA_PIN_DISABLE>;
455 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
456 };
457 en_vdd_bl {
458 nvidia,pins = "dap3_dout_pp2";
459 nvidia,function = "i2s2";
460 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
461 nvidia,tristate = <TEGRA_PIN_DISABLE>;
462 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
463 };
464 en_vdd_hdmi {
465 nvidia,pins = "spdif_in_pk6";
466 nvidia,function = "spdif";
467 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
468 nvidia,tristate = <TEGRA_PIN_DISABLE>;
469 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
470 };
471 soc_warm_reset_l {
472 nvidia,pins = "pi5";
473 nvidia,function = "gmi";
474 nvidia,pull = <TEGRA_PIN_PULL_UP>;
475 nvidia,tristate = <TEGRA_PIN_DISABLE>;
476 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
477 };
478 hp_det_l {
479 nvidia,pins = "pi7";
480 nvidia,function = "rsvd1";
481 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
482 nvidia,tristate = <TEGRA_PIN_DISABLE>;
483 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
484 };
485 mic_det_l {
486 nvidia,pins = "kb_row7_pr7";
487 nvidia,function = "rsvd2";
488 nvidia,pull = <TEGRA_PIN_PULL_UP>;
489 nvidia,tristate = <TEGRA_PIN_DISABLE>;
490 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
491 };
492 };
493 };
494
495 serial@0,70006000 {
496 /* Debug connector on the bottom of the board near SD card. */
497 status = "okay";
498 };
499
500 pwm@0,7000a000 {
501 status = "okay";
502 };
503
504 i2c@0,7000c000 {
505 status = "okay";
506 clock-frequency = <100000>;
507
508 acodec: audio-codec@10 {
509 compatible = "maxim,max98090";
510 reg = <0x10>;
511 interrupt-parent = <&gpio>;
512 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
513 };
514
515 temperature-sensor@4c {
516 compatible = "ti,tmp451";
517 reg = <0x4c>;
518 interrupt-parent = <&gpio>;
519 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
520
521 #thermal-sensor-cells = <1>;
522 };
523 };
524
525 i2c@0,7000c400 {
526 status = "okay";
527 clock-frequency = <100000>;
528 };
529
530 i2c@0,7000c500 {
531 status = "okay";
532 clock-frequency = <400000>;
533
534 tpm@20 {
535 compatible = "infineon,slb9645tt";
536 reg = <0x20>;
537 };
538 };
539
540 hdmi_ddc: i2c@0,7000c700 {
541 status = "okay";
542 clock-frequency = <100000>;
543 };
544
545 i2c@0,7000d000 {
546 status = "okay";
547 clock-frequency = <400000>;
548
549 pmic: pmic@40 {
550 compatible = "ams,as3722";
551 reg = <0x40>;
552 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
553
554 ams,system-power-controller;
555
556 #interrupt-cells = <2>;
557 interrupt-controller;
558
559 gpio-controller;
560 #gpio-cells = <2>;
561
562 pinctrl-names = "default";
563 pinctrl-0 = <&as3722_default>;
564
565 as3722_default: pinmux {
566 gpio0 {
567 pins = "gpio0";
568 function = "gpio";
569 bias-pull-down;
570 };
571
572 gpio1 {
573 pins = "gpio1";
574 function = "gpio";
575 bias-pull-up;
576 };
577
578 gpio2_4_7 {
579 pins = "gpio2", "gpio4", "gpio7";
580 function = "gpio";
581 bias-pull-up;
582 };
583
584 gpio3_6 {
585 pins = "gpio3", "gpio6";
586 bias-high-impedance;
587 };
588
589 gpio5 {
590 pins = "gpio5";
591 function = "clk32k-out";
592 bias-pull-down;
593 };
594 };
595
596 regulators {
597 vsup-sd2-supply = <&vdd_5v0_sys>;
598 vsup-sd3-supply = <&vdd_5v0_sys>;
599 vsup-sd4-supply = <&vdd_5v0_sys>;
600 vsup-sd5-supply = <&vdd_5v0_sys>;
601 vin-ldo0-supply = <&vdd_1v35_lp0>;
602 vin-ldo1-6-supply = <&vdd_3v3_run>;
603 vin-ldo2-5-7-supply = <&vddio_1v8>;
604 vin-ldo3-4-supply = <&vdd_3v3_sys>;
605 vin-ldo9-10-supply = <&vdd_5v0_sys>;
606 vin-ldo11-supply = <&vdd_3v3_run>;
607
608 sd0 {
609 regulator-name = "+VDD_CPU_AP";
610 regulator-min-microvolt = <700000>;
611 regulator-max-microvolt = <1350000>;
612 regulator-min-microamp = <3500000>;
613 regulator-max-microamp = <3500000>;
614 regulator-always-on;
615 regulator-boot-on;
616 ams,ext-control = <2>;
617 };
618
619 sd1 {
620 regulator-name = "+VDD_CORE";
621 regulator-min-microvolt = <700000>;
622 regulator-max-microvolt = <1350000>;
623 regulator-min-microamp = <2500000>;
624 regulator-max-microamp = <4000000>;
625 regulator-always-on;
626 regulator-boot-on;
627 ams,ext-control = <1>;
628 };
629
630 vdd_1v35_lp0: sd2 {
631 regulator-name = "+1.35V_LP0(sd2)";
632 regulator-min-microvolt = <1350000>;
633 regulator-max-microvolt = <1350000>;
634 regulator-always-on;
635 regulator-boot-on;
636 };
637
638 sd3 {
639 regulator-name = "+1.35V_LP0(sd3)";
640 regulator-min-microvolt = <1350000>;
641 regulator-max-microvolt = <1350000>;
642 regulator-always-on;
643 regulator-boot-on;
644 };
645
646 vdd_1v05_run: sd4 {
647 regulator-name = "+1.05V_RUN";
648 regulator-min-microvolt = <1050000>;
649 regulator-max-microvolt = <1050000>;
650 };
651
652 vddio_1v8: sd5 {
653 regulator-name = "+1.8V_VDDIO";
654 regulator-min-microvolt = <1800000>;
655 regulator-max-microvolt = <1800000>;
656 regulator-boot-on;
657 regulator-always-on;
658 };
659
660 sd6 {
661 regulator-name = "+VDD_GPU_AP";
662 regulator-min-microvolt = <650000>;
663 regulator-max-microvolt = <1200000>;
664 regulator-min-microamp = <3500000>;
665 regulator-max-microamp = <3500000>;
666 regulator-boot-on;
667 regulator-always-on;
668 };
669
670 ldo0 {
671 regulator-name = "+1.05V_RUN_AVDD";
672 regulator-min-microvolt = <1050000>;
673 regulator-max-microvolt = <1050000>;
674 regulator-boot-on;
675 regulator-always-on;
676 ams,ext-control = <1>;
677 };
678
679 ldo1 {
680 regulator-name = "+1.8V_RUN_CAM";
681 regulator-min-microvolt = <1800000>;
682 regulator-max-microvolt = <1800000>;
683 };
684
685 ldo2 {
686 regulator-name = "+1.2V_GEN_AVDD";
687 regulator-min-microvolt = <1200000>;
688 regulator-max-microvolt = <1200000>;
689 regulator-boot-on;
690 regulator-always-on;
691 };
692
693 ldo3 {
694 regulator-name = "+1.00V_LP0_VDD_RTC";
695 regulator-min-microvolt = <1000000>;
696 regulator-max-microvolt = <1000000>;
697 regulator-boot-on;
698 regulator-always-on;
699 ams,enable-tracking;
700 };
701
702 vdd_run_cam: ldo4 {
703 regulator-name = "+3.3V_RUN_CAM";
704 regulator-min-microvolt = <2800000>;
705 regulator-max-microvolt = <2800000>;
706 };
707
708 ldo5 {
709 regulator-name = "+1.2V_RUN_CAM_FRONT";
710 regulator-min-microvolt = <1200000>;
711 regulator-max-microvolt = <1200000>;
712 };
713
714 vddio_sdmmc3: ldo6 {
715 regulator-name = "+VDDIO_SDMMC3";
716 regulator-min-microvolt = <1800000>;
717 regulator-max-microvolt = <3300000>;
718 };
719
720 ldo7 {
721 regulator-name = "+1.05V_RUN_CAM_REAR";
722 regulator-min-microvolt = <1050000>;
723 regulator-max-microvolt = <1050000>;
724 };
725
726 ldo9 {
727 regulator-name = "+2.8V_RUN_TOUCH";
728 regulator-min-microvolt = <2800000>;
729 regulator-max-microvolt = <2800000>;
730 };
731
732 ldo10 {
733 regulator-name = "+2.8V_RUN_CAM_AF";
734 regulator-min-microvolt = <2800000>;
735 regulator-max-microvolt = <2800000>;
736 };
737
738 ldo11 {
739 regulator-name = "+1.8V_RUN_VPP_FUSE";
740 regulator-min-microvolt = <1800000>;
741 regulator-max-microvolt = <1800000>;
742 };
743 };
744 };
745 };
746
747 spi@0,7000d400 {
748 status = "okay";
749
750 cros_ec: cros-ec@0 {
751 compatible = "google,cros-ec-spi";
752 spi-max-frequency = <3000000>;
753 interrupt-parent = <&gpio>;
754 interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
755 reg = <0>;
756
757 google,cros-ec-spi-msg-delay = <2000>;
758
759 i2c-tunnel {
760 compatible = "google,cros-ec-i2c-tunnel";
761 #address-cells = <1>;
762 #size-cells = <0>;
763
764 google,remote-bus = <0>;
765
766 charger: bq24735@9 {
767 compatible = "ti,bq24735";
768 reg = <0x9>;
769 interrupt-parent = <&gpio>;
770 interrupts = <TEGRA_GPIO(J, 0)
771 GPIO_ACTIVE_HIGH>;
772 ti,ac-detect-gpios = <&gpio
773 TEGRA_GPIO(J, 0)
774 GPIO_ACTIVE_HIGH>;
775 };
776
777 battery: sbs-battery@b {
778 compatible = "sbs,sbs-battery";
779 reg = <0xb>;
780 sbs,i2c-retry-count = <2>;
781 sbs,poll-retry-count = <10>;
782 power-supplies = <&charger>;
783 };
784 };
785 };
786 };
787
788 spi@0,7000da00 {
789 status = "okay";
790 spi-max-frequency = <25000000>;
791
792 flash@0 {
793 compatible = "winbond,w25q32dw";
794 reg = <0>;
795 };
796 };
797
798 pmc@0,7000e400 {
799 nvidia,invert-interrupt;
800 nvidia,suspend-mode = <0>;
801 nvidia,cpu-pwr-good-time = <500>;
802 nvidia,cpu-pwr-off-time = <300>;
803 nvidia,core-pwr-good-time = <641 3845>;
804 nvidia,core-pwr-off-time = <61036>;
805 nvidia,core-power-req-active-high;
806 nvidia,sys-clock-req-active-high;
807 };
808
809 hda@0,70030000 {
810 status = "okay";
811 };
812
813 sdhci@0,700b0000 { /* WiFi/BT on this bus */
814 status = "okay";
815 power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
816 bus-width = <4>;
817 no-1-8-v;
818 non-removable;
819 };
820
821 sdhci@0,700b0400 { /* SD Card on this bus */
822 status = "okay";
823 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
824 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
825 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
826 bus-width = <4>;
827 no-1-8-v;
828 vqmmc-supply = <&vddio_sdmmc3>;
829 };
830
831 sdhci@0,700b0600 { /* eMMC on this bus */
832 status = "okay";
833 bus-width = <8>;
834 no-1-8-v;
835 non-removable;
836 };
837
838 ahub@0,70300000 {
839 i2s@0,70301100 {
840 status = "okay";
841 };
842 };
843
844 usb@0,7d000000 { /* Rear external USB port. */
845 status = "okay";
846 };
847
848 usb-phy@0,7d000000 {
849 status = "okay";
850 vbus-supply = <&vdd_usb1_vbus>;
851 };
852
853 usb@0,7d004000 { /* Internal webcam. */
854 status = "okay";
855 };
856
857 usb-phy@0,7d004000 {
858 status = "okay";
859 vbus-supply = <&vdd_run_cam>;
860 };
861
862 usb@0,7d008000 { /* Left external USB port. */
863 status = "okay";
864 };
865
866 usb-phy@0,7d008000 {
867 status = "okay";
868 vbus-supply = <&vdd_usb3_vbus>;
869 };
870
871 backlight: backlight {
872 compatible = "pwm-backlight";
873
874 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
875 power-supply = <&vdd_led>;
876 pwms = <&pwm 1 1000000>;
877
878 default-brightness-level = <224>;
879 brightness-levels =
880 < 0 1 2 3 4 5 6 7
881 8 9 10 11 12 13 14 15
882 16 17 18 19 20 21 22 23
883 24 25 26 27 28 29 30 31
884 32 33 34 35 36 37 38 39
885 40 41 42 43 44 45 46 47
886 48 49 50 51 52 53 54 55
887 56 57 58 59 60 61 62 63
888 64 65 66 67 68 69 70 71
889 72 73 74 75 76 77 78 79
890 80 81 82 83 84 85 86 87
891 88 89 90 91 92 93 94 95
892 96 97 98 99 100 101 102 103
893 104 105 106 107 108 109 110 111
894 112 113 114 115 116 117 118 119
895 120 121 122 123 124 125 126 127
896 128 129 130 131 132 133 134 135
897 136 137 138 139 140 141 142 143
898 144 145 146 147 148 149 150 151
899 152 153 154 155 156 157 158 159
900 160 161 162 163 164 165 166 167
901 168 169 170 171 172 173 174 175
902 176 177 178 179 180 181 182 183
903 184 185 186 187 188 189 190 191
904 192 193 194 195 196 197 198 199
905 200 201 202 203 204 205 206 207
906 208 209 210 211 212 213 214 215
907 216 217 218 219 220 221 222 223
908 224 225 226 227 228 229 230 231
909 232 233 234 235 236 237 238 239
910 240 241 242 243 244 245 246 247
911 248 249 250 251 252 253 254 255
912 256>;
913 };
914
915 clocks {
916 compatible = "simple-bus";
917 #address-cells = <1>;
918 #size-cells = <0>;
919
920 clk32k_in: clock@0 {
921 compatible = "fixed-clock";
922 reg = <0>;
923 #clock-cells = <0>;
924 clock-frequency = <32768>;
925 };
926 };
927
928 gpio-keys {
929 compatible = "gpio-keys";
930
931 lid {
932 label = "Lid";
933 gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
934 linux,input-type = <5>;
935 linux,code = <KEY_RESERVED>;
936 debounce-interval = <1>;
937 gpio-key,wakeup;
938 };
939
940 power {
941 label = "Power";
942 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
943 linux,code = <KEY_POWER>;
944 debounce-interval = <30>;
945 gpio-key,wakeup;
946 };
947 };
948
949 panel: panel {
950 compatible = "auo,b133xtn01";
951
952 backlight = <&backlight>;
953 ddc-i2c-bus = <&dpaux>;
954 };
955
956 regulators {
957 compatible = "simple-bus";
958 #address-cells = <1>;
959 #size-cells = <0>;
960
961 vdd_mux: regulator@0 {
962 compatible = "regulator-fixed";
963 reg = <0>;
964 regulator-name = "+VDD_MUX";
965 regulator-min-microvolt = <12000000>;
966 regulator-max-microvolt = <12000000>;
967 regulator-always-on;
968 regulator-boot-on;
969 };
970
971 vdd_5v0_sys: regulator@1 {
972 compatible = "regulator-fixed";
973 reg = <1>;
974 regulator-name = "+5V_SYS";
975 regulator-min-microvolt = <5000000>;
976 regulator-max-microvolt = <5000000>;
977 regulator-always-on;
978 regulator-boot-on;
979 vin-supply = <&vdd_mux>;
980 };
981
982 vdd_3v3_sys: regulator@2 {
983 compatible = "regulator-fixed";
984 reg = <2>;
985 regulator-name = "+3.3V_SYS";
986 regulator-min-microvolt = <3300000>;
987 regulator-max-microvolt = <3300000>;
988 regulator-always-on;
989 regulator-boot-on;
990 vin-supply = <&vdd_mux>;
991 };
992
993 vdd_3v3_run: regulator@3 {
994 compatible = "regulator-fixed";
995 reg = <3>;
996 regulator-name = "+3.3V_RUN";
997 regulator-min-microvolt = <3300000>;
998 regulator-max-microvolt = <3300000>;
999 regulator-always-on;
1000 regulator-boot-on;
1001 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
1002 enable-active-high;
1003 vin-supply = <&vdd_3v3_sys>;
1004 };
1005
1006 vdd_3v3_hdmi: regulator@4 {
1007 compatible = "regulator-fixed";
1008 reg = <4>;
1009 regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
1010 regulator-min-microvolt = <3300000>;
1011 regulator-max-microvolt = <3300000>;
1012 vin-supply = <&vdd_3v3_run>;
1013 };
1014
1015 vdd_led: regulator@5 {
1016 compatible = "regulator-fixed";
1017 reg = <5>;
1018 regulator-name = "+VDD_LED";
1019 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1020 enable-active-high;
1021 vin-supply = <&vdd_mux>;
1022 };
1023
1024 vdd_5v0_ts: regulator@6 {
1025 compatible = "regulator-fixed";
1026 reg = <6>;
1027 regulator-name = "+5V_VDD_TS_SW";
1028 regulator-min-microvolt = <5000000>;
1029 regulator-max-microvolt = <5000000>;
1030 regulator-boot-on;
1031 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
1032 enable-active-high;
1033 vin-supply = <&vdd_5v0_sys>;
1034 };
1035
1036 vdd_usb1_vbus: regulator@7 {
1037 compatible = "regulator-fixed";
1038 reg = <7>;
1039 regulator-name = "+5V_USB_HS";
1040 regulator-min-microvolt = <5000000>;
1041 regulator-max-microvolt = <5000000>;
1042 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1043 enable-active-high;
1044 gpio-open-drain;
1045 vin-supply = <&vdd_5v0_sys>;
1046 };
1047
1048 vdd_usb3_vbus: regulator@8 {
1049 compatible = "regulator-fixed";
1050 reg = <8>;
1051 regulator-name = "+5V_USB_SS";
1052 regulator-min-microvolt = <5000000>;
1053 regulator-max-microvolt = <5000000>;
1054 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1055 enable-active-high;
1056 gpio-open-drain;
1057 vin-supply = <&vdd_5v0_sys>;
1058 };
1059
1060 vdd_3v3_panel: regulator@9 {
1061 compatible = "regulator-fixed";
1062 reg = <9>;
1063 regulator-name = "+3.3V_PANEL";
1064 regulator-min-microvolt = <3300000>;
1065 regulator-max-microvolt = <3300000>;
1066 gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
1067 enable-active-high;
1068 vin-supply = <&vdd_3v3_run>;
1069 };
1070
1071 vdd_3v3_lp0: regulator@10 {
1072 compatible = "regulator-fixed";
1073 reg = <10>;
1074 regulator-name = "+3.3V_LP0";
1075 regulator-min-microvolt = <3300000>;
1076 regulator-max-microvolt = <3300000>;
1077 /*
1078 * TODO: find a way to wire this up with the USB EHCI
1079 * controllers so that it can be enabled on demand.
1080 */
1081 regulator-always-on;
1082 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1083 enable-active-high;
1084 vin-supply = <&vdd_3v3_sys>;
1085 };
1086
1087 vdd_hdmi_pll: regulator@11 {
1088 compatible = "regulator-fixed";
1089 reg = <11>;
1090 regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
1091 regulator-min-microvolt = <1050000>;
1092 regulator-max-microvolt = <1050000>;
1093 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1094 vin-supply = <&vdd_1v05_run>;
1095 };
1096
1097 vdd_5v0_hdmi: regulator@12 {
1098 compatible = "regulator-fixed";
1099 reg = <12>;
1100 regulator-name = "+5V_HDMI_CON";
1101 regulator-min-microvolt = <5000000>;
1102 regulator-max-microvolt = <5000000>;
1103 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
1104 enable-active-high;
1105 vin-supply = <&vdd_5v0_sys>;
1106 };
1107 };
1108
1109 sound {
1110 compatible = "nvidia,tegra-audio-max98090-nyan-big",
1111 "nvidia,tegra-audio-max98090";
1112 nvidia,model = "Acer Chromebook 13";
1113
1114 nvidia,audio-routing =
1115 "Headphones", "HPR",
1116 "Headphones", "HPL",
1117 "Speakers", "SPKR",
1118 "Speakers", "SPKL",
1119 "Mic Jack", "MICBIAS",
1120 "DMICL", "Int Mic",
1121 "DMICR", "Int Mic",
1122 "IN34", "Mic Jack";
1123
1124 nvidia,i2s-controller = <&tegra_i2s1>;
1125 nvidia,audio-codec = <&acodec>;
1126
1127 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1128 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1129 <&tegra_car TEGRA124_CLK_EXTERN1>;
1130 clock-names = "pll_a", "pll_a_out0", "mclk";
1131
1132 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
1133 };
1134};
1135
1136#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 70ad91d1a20b..13008858e967 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -36,17 +36,17 @@
36 nvidia,panel = <&panel>; 36 nvidia,panel = <&panel>;
37 }; 37 };
38 38
39 dpaux: dpaux@0,545c0000 { 39 dpaux@0,545c0000 {
40 vdd-supply = <&vdd_3v3_panel>; 40 vdd-supply = <&vdd_3v3_panel>;
41 status = "okay"; 41 status = "okay";
42 }; 42 };
43 }; 43 };
44 44
45 pinmux: pinmux@0,70000868 { 45 pinmux: pinmux@0,70000868 {
46 pinctrl-names = "default"; 46 pinctrl-names = "boot";
47 pinctrl-0 = <&pinmux_default>; 47 pinctrl-0 = <&pinmux_boot>;
48 48
49 pinmux_default: common { 49 pinmux_boot: common {
50 dap_mclk1_pw4 { 50 dap_mclk1_pw4 {
51 nvidia,pins = "dap_mclk1_pw4"; 51 nvidia,pins = "dap_mclk1_pw4";
52 nvidia,function = "extperiph1"; 52 nvidia,function = "extperiph1";
@@ -587,7 +587,7 @@
587 status = "okay"; 587 status = "okay";
588 }; 588 };
589 589
590 pwm: pwm@0,7000a000 { 590 pwm@0,7000a000 {
591 status = "okay"; 591 status = "okay";
592 }; 592 };
593 593
@@ -606,6 +606,14 @@
606 i2c@0,7000c400 { 606 i2c@0,7000c400 {
607 status = "okay"; 607 status = "okay";
608 clock-frequency = <100000>; 608 clock-frequency = <100000>;
609
610 trackpad@4b {
611 compatible = "atmel,maxtouch";
612 reg = <0x4b>;
613 interrupt-parent = <&gpio>;
614 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
615 linux,gpio-keymap = <0 0 0 BTN_LEFT>;
616 };
609 }; 617 };
610 618
611 i2c@0,7000c500 { 619 i2c@0,7000c500 {
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 03916efd6fa9..478c555ebd96 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -12,6 +12,72 @@
12 #address-cells = <2>; 12 #address-cells = <2>;
13 #size-cells = <2>; 13 #size-cells = <2>;
14 14
15 pcie-controller@0,01003000 {
16 compatible = "nvidia,tegra124-pcie";
17 device_type = "pci";
18 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
19 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
20 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
21 reg-names = "pads", "afi", "cs";
22 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
23 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
24 interrupt-names = "intr", "msi";
25
26 #interrupt-cells = <1>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
36 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
37 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
38 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
39
40 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
41 <&tegra_car TEGRA124_CLK_AFI>,
42 <&tegra_car TEGRA124_CLK_PLL_E>,
43 <&tegra_car TEGRA124_CLK_CML0>;
44 clock-names = "pex", "afi", "pll_e", "cml";
45 resets = <&tegra_car 70>,
46 <&tegra_car 72>,
47 <&tegra_car 74>;
48 reset-names = "pex", "afi", "pcie_x";
49 status = "disabled";
50
51 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
52 phy-names = "pcie";
53
54 pci@1,0 {
55 device_type = "pci";
56 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
57 reg = <0x000800 0 0 0 0>;
58 status = "disabled";
59
60 #address-cells = <3>;
61 #size-cells = <2>;
62 ranges;
63
64 nvidia,num-lanes = <2>;
65 };
66
67 pci@2,0 {
68 device_type = "pci";
69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
70 reg = <0x001000 0 0 0 0>;
71 status = "disabled";
72
73 #address-cells = <3>;
74 #size-cells = <2>;
75 ranges;
76
77 nvidia,num-lanes = <1>;
78 };
79 };
80
15 host1x@0,50000000 { 81 host1x@0,50000000 {
16 compatible = "nvidia,tegra124-host1x", "simple-bus"; 82 compatible = "nvidia,tegra124-host1x", "simple-bus";
17 reg = <0x0 0x50000000 0x0 0x00034000>; 83 reg = <0x0 0x50000000 0x0 0x00034000>;
@@ -78,7 +144,7 @@
78 status = "disabled"; 144 status = "disabled";
79 }; 145 };
80 146
81 dpaux@0,545c0000 { 147 dpaux: dpaux@0,545c0000 {
82 compatible = "nvidia,tegra124-dpaux"; 148 compatible = "nvidia,tegra124-dpaux";
83 reg = <0x0 0x545c0000 0x0 0x00040000>; 149 reg = <0x0 0x545c0000 0x0 0x00040000>;
84 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 150 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
@@ -137,6 +203,11 @@
137 #reset-cells = <1>; 203 #reset-cells = <1>;
138 }; 204 };
139 205
206 flow-controller@0,60007000 {
207 compatible = "nvidia,tegra124-flowctrl";
208 reg = <0x0 0x60007000 0x0 0x1000>;
209 };
210
140 gpio: gpio@0,6000d000 { 211 gpio: gpio@0,6000d000 {
141 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 212 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
142 reg = <0x0 0x6000d000 0x0 0x1000>; 213 reg = <0x0 0x6000d000 0x0 0x1000>;
@@ -267,7 +338,7 @@
267 status = "disabled"; 338 status = "disabled";
268 }; 339 };
269 340
270 pwm@0,7000a000 { 341 pwm: pwm@0,7000a000 {
271 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 342 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
272 reg = <0x0 0x7000a000 0x0 0x100>; 343 reg = <0x0 0x7000a000 0x0 0x100>;
273 #pwm-cells = <2>; 344 #pwm-cells = <2>;
@@ -480,6 +551,31 @@
480 reset-names = "fuse"; 551 reset-names = "fuse";
481 }; 552 };
482 553
554 sata@0,70020000 {
555 compatible = "nvidia,tegra124-ahci";
556
557 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
558 <0x0 0x70020000 0x0 0x7000>; /* SATA */
559
560 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
561
562 clocks = <&tegra_car TEGRA124_CLK_SATA>,
563 <&tegra_car TEGRA124_CLK_SATA_OOB>,
564 <&tegra_car TEGRA124_CLK_CML1>,
565 <&tegra_car TEGRA124_CLK_PLL_E>;
566 clock-names = "sata", "sata-oob", "cml1", "pll_e";
567
568 resets = <&tegra_car 124>,
569 <&tegra_car 123>,
570 <&tegra_car 129>;
571 reset-names = "sata", "sata-oob", "sata-cold";
572
573 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
574 phy-names = "sata-phy";
575
576 status = "disabled";
577 };
578
483 hda@0,70030000 { 579 hda@0,70030000 {
484 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 580 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
485 reg = <0x0 0x70030000 0x0 0x10000>; 581 reg = <0x0 0x70030000 0x0 0x10000>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 1908f6937e53..3b374c49d04d 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -190,6 +190,11 @@
190 #reset-cells = <1>; 190 #reset-cells = <1>;
191 }; 191 };
192 192
193 flow-controller@60007000 {
194 compatible = "nvidia,tegra20-flowctrl";
195 reg = <0x60007000 0x1000>;
196 };
197
193 apbdma: dma@6000a000 { 198 apbdma: dma@6000a000 {
194 compatible = "nvidia,tegra20-apbdma"; 199 compatible = "nvidia,tegra20-apbdma";
195 reg = <0x6000a000 0x1200>; 200 reg = <0x6000a000 0x1200>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 6b35c29278d7..aa6ccea13d30 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -272,6 +272,11 @@
272 #reset-cells = <1>; 272 #reset-cells = <1>;
273 }; 273 };
274 274
275 flow-controller@60007000 {
276 compatible = "nvidia,tegra30-flowctrl";
277 reg = <0x60007000 0x1000>;
278 };
279
275 apbdma: dma@6000a000 { 280 apbdma: dma@6000a000 {
276 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 281 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
277 reg = <0x6000a000 0x1400>; 282 reg = <0x6000a000 0x1400>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 22:41:31 -0400