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-rw-r--r--arch/x86/include/asm/apic.h2
-rw-r--r--arch/x86/include/asm/cpufeature.h409
-rw-r--r--arch/x86/include/asm/fpu-internal.h2
-rw-r--r--arch/x86/include/asm/mwait.h2
-rw-r--r--arch/x86/include/uapi/asm/msr-index.h2
-rw-r--r--arch/x86/kernel/cpu/amd.c341
-rw-r--r--arch/x86/kernel/cpu/common.c9
-rw-r--r--arch/x86/kernel/cpu/intel.c4
-rw-r--r--arch/x86/kernel/cpu/mkcapflags.sh51
-rw-r--r--arch/x86/kernel/cpu/proc.c8
-rw-r--r--arch/x86/kernel/cpu/scattered.c1
11 files changed, 433 insertions, 398 deletions
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 19b0ebafcd3e..79752f2bdec5 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -99,7 +99,7 @@ static inline void native_apic_mem_write(u32 reg, u32 v)
99{ 99{
100 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 100 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
101 101
102 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, 102 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP,
103 ASM_OUTPUT2("=r" (v), "=m" (*addr)), 103 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
104 ASM_OUTPUT2("0" (v), "m" (*addr))); 104 ASM_OUTPUT2("0" (v), "m" (*addr)));
105} 105}
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index e265ff95d16d..bb9b258d60e7 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -8,7 +8,7 @@
8#include <asm/required-features.h> 8#include <asm/required-features.h>
9#endif 9#endif
10 10
11#define NCAPINTS 10 /* N 32-bit words worth of info */ 11#define NCAPINTS 11 /* N 32-bit words worth of info */
12#define NBUGINTS 1 /* N 32-bit bug flags */ 12#define NBUGINTS 1 /* N 32-bit bug flags */
13 13
14/* 14/*
@@ -18,213 +18,218 @@
18 */ 18 */
19 19
20/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ 20/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
21#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ 21#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
22#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ 22#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
23#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ 23#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
24#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ 24#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
25#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ 25#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
26#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */ 26#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
27#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ 27#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
28#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */ 28#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
29#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ 29#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
30#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ 30#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
31#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ 31#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
32#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ 32#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
33#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ 33#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
34#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ 34#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
35#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */ 35#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */
36 /* (plus FCMOVcc, FCOMI with FPU) */ 36 /* (plus FCMOVcc, FCOMI with FPU) */
37#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ 37#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
38#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ 38#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
39#define X86_FEATURE_PN (0*32+18) /* Processor serial number */ 39#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
40#define X86_FEATURE_CLFLUSH (0*32+19) /* CLFLUSH instruction */ 40#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
41#define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */ 41#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
42#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ 42#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
43#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ 43#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
44#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ 44#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
45#define X86_FEATURE_XMM (0*32+25) /* "sse" */ 45#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
46#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */ 46#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
47#define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */ 47#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
48#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ 48#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
49#define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */ 49#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
50#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ 50#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
51#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */ 51#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
52 52
53/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ 53/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
54/* Don't duplicate feature flags which are redundant with Intel! */ 54/* Don't duplicate feature flags which are redundant with Intel! */
55#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ 55#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
56#define X86_FEATURE_MP (1*32+19) /* MP Capable. */ 56#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */
57#define X86_FEATURE_NX (1*32+20) /* Execute Disable */ 57#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
58#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ 58#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
59#define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */ 59#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
60#define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */ 60#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
61#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ 61#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
62#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ 62#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */
63#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ 63#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */
64#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ 64#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */
65 65
66/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ 66/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
67#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ 67#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
68#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ 68#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
69#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ 69#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
70 70
71/* Other features, Linux-defined mapping, word 3 */ 71/* Other features, Linux-defined mapping, word 3 */
72/* This range is used for feature bits which conflict or are synthesized */ 72/* This range is used for feature bits which conflict or are synthesized */
73#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ 73#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
74#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ 74#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
75#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ 75#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
76#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ 76#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
77/* cpu types for specific tunings: */ 77/* cpu types for specific tunings: */
78#define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */ 78#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
79#define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */ 79#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */
80#define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */ 80#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
81#define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */ 81#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
82#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ 82#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
83#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ 83#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */
84#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ 84/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */
85#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ 85#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
86#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ 86#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
87#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 87#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
88#define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ 88#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */
89#define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */ 89#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */
90#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */ 90#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */
91#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */ 91#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
92#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ 92#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
93#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ 93/* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */
94#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ 94#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
95#define X86_FEATURE_ALWAYS (3*32+21) /* "" Always-present feature */ 95#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
96#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ 96#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
97#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ 97#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
98#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ 98#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
99#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */ 99/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
100#define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */ 100#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
101#define X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */ 101#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
102#define X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */ 102#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
103#define X86_FEATURE_EAGER_FPU (3*32+29) /* "eagerfpu" Non lazy FPU restore */ 103#define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */
104#define X86_FEATURE_NONSTOP_TSC_S3 (3*32+30) /* TSC doesn't stop in S3 state */ 104#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
105 105
106/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 106/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
107#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ 107#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
108#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */ 108#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
109#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ 109#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
110#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */ 110#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */
111#define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ 111#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
112#define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */ 112#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
113#define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */ 113#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */
114#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ 114#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
115#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ 115#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
116#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ 116#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
117#define X86_FEATURE_CID (4*32+10) /* Context ID */ 117#define X86_FEATURE_CID ( 4*32+10) /* Context ID */
118#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */ 118#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
119#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ 119#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */
120#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ 120#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */
121#define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */ 121#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */
122#define X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */ 122#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */
123#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ 123#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */
124#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */ 124#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
125#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */ 125#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
126#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ 126#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */
127#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ 127#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */
128#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ 128#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */
129#define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */ 129#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */
130#define X86_FEATURE_AES (4*32+25) /* AES instructions */ 130#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */
131#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ 131#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
132#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ 132#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */
133#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ 133#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */
134#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */ 134#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */
135#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */ 135#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */
136#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ 136#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
137 137
138/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ 138/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
139#define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ 139#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
140#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */ 140#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
141#define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ 141#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
142#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */ 142#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
143#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ 143#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
144#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ 144#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */
145#define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */ 145#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */
146#define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */ 146#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
147#define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */ 147#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
148#define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */ 148#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
149 149
150/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ 150/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
151#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ 151#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
152#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ 152#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */
153#define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ 153#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */
154#define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ 154#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */
155#define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */ 155#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
156#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ 156#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
157#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ 157#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
158#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */ 158#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
159#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ 159#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
160#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ 160#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */
161#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ 161#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */
162#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */ 162#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */
163#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ 163#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */
164#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ 164#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */
165#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ 165#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */
166#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ 166#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */
167#define X86_FEATURE_TCE (6*32+17) /* translation cache extension */ 167#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */
168#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ 168#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */
169#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ 169#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */
170#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ 170#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */
171#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */ 171#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
172#define X86_FEATURE_PERFCTR_NB (6*32+24) /* NB performance counter extensions */ 172#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
173#define X86_FEATURE_PERFCTR_L2 (6*32+28) /* L2 performance counter extensions */ 173#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */
174 174
175/* 175/*
176 * Auxiliary flags: Linux defined - For features scattered in various 176 * Auxiliary flags: Linux defined - For features scattered in various
177 * CPUID levels like 0x6, 0xA etc, word 7 177 * CPUID levels like 0x6, 0xA etc, word 7
178 */ 178 */
179#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ 179#define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */
180#define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */ 180#define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */
181#define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */ 181#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
182#define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ 182#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
183#define X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */ 183#define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */
184#define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ 184#define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */
185#define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ 185#define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */
186#define X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */ 186#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
187#define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */ 187#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
188#define X86_FEATURE_PROC_FEEDBACK (7*32+ 9) /* AMD ProcFeedbackInterface */
189 188
190/* Virtualization flags: Linux defined, word 8 */ 189/* Virtualization flags: Linux defined, word 8 */
191#define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ 190#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
192#define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */ 191#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
193#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */ 192#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
194#define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */ 193#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
195#define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */ 194#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
196#define X86_FEATURE_NPT (8*32+ 5) /* AMD Nested Page Table support */ 195#define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */
197#define X86_FEATURE_LBRV (8*32+ 6) /* AMD LBR Virtualization support */ 196#define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */
198#define X86_FEATURE_SVML (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ 197#define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
199#define X86_FEATURE_NRIPS (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ 198#define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */
200#define X86_FEATURE_TSCRATEMSR (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ 199#define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
201#define X86_FEATURE_VMCBCLEAN (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ 200#define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */
202#define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */ 201#define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */
203#define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */ 202#define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */
204#define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */ 203#define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */
205#define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */ 204#define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */
206 205
207 206
208/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ 207/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
209#define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ 208#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
210#define X86_FEATURE_TSC_ADJUST (9*32+ 1) /* TSC adjustment MSR 0x3b */ 209#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
211#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */ 210#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
212#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ 211#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
213#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ 212#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
214#define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ 213#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
215#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */ 214#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
216#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ 215#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
217#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ 216#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
218#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ 217#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
219#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */ 218#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
220#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */ 219#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
221#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ 220#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
222#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ 221#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
223#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ 222#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
224#define X86_FEATURE_CLFLUSHOPT (9*32+23) /* CLFLUSHOPT instruction */ 223#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
225#define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */ 224#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
226#define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */ 225#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
227#define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */ 226#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
227
228/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
229#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
230#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */
231#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
232#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
228 233
229/* 234/*
230 * BUG word(s) 235 * BUG word(s)
@@ -234,8 +239,11 @@
234#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ 239#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
235#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ 240#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
236#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ 241#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
237#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* AMD Erratum 383 */ 242#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
238#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* AMD Erratum 400 */ 243#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
244#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
245#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
246#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
239 247
240#if defined(__KERNEL__) && !defined(__ASSEMBLY__) 248#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
241 249
@@ -245,6 +253,12 @@
245extern const char * const x86_cap_flags[NCAPINTS*32]; 253extern const char * const x86_cap_flags[NCAPINTS*32];
246extern const char * const x86_power_flags[32]; 254extern const char * const x86_power_flags[32];
247 255
256/*
257 * In order to save room, we index into this array by doing
258 * X86_BUG_<name> - NCAPINTS*32.
259 */
260extern const char * const x86_bug_flags[NBUGINTS*32];
261
248#define test_cpu_cap(c, bit) \ 262#define test_cpu_cap(c, bit) \
249 test_bit(bit, (unsigned long *)((c)->x86_capability)) 263 test_bit(bit, (unsigned long *)((c)->x86_capability))
250 264
@@ -301,7 +315,6 @@ extern const char * const x86_power_flags[32];
301#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) 315#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
302#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) 316#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
303#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) 317#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
304#define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
305#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) 318#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
306#define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR) 319#define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
307#define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) 320#define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
@@ -328,6 +341,7 @@ extern const char * const x86_power_flags[32];
328#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) 341#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
329#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) 342#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
330#define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) 343#define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT)
344#define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
331#define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) 345#define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE)
332#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) 346#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
333#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) 347#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
@@ -347,9 +361,6 @@ extern const char * const x86_power_flags[32];
347#undef cpu_has_pae 361#undef cpu_has_pae
348#define cpu_has_pae ___BUG___ 362#define cpu_has_pae ___BUG___
349 363
350#undef cpu_has_mp
351#define cpu_has_mp 1
352
353#undef cpu_has_k6_mtrr 364#undef cpu_has_k6_mtrr
354#define cpu_has_k6_mtrr 0 365#define cpu_has_k6_mtrr 0
355 366
@@ -539,20 +550,20 @@ static __always_inline __pure bool _static_cpu_has_safe(u16 bit)
539#define static_cpu_has_safe(bit) boot_cpu_has(bit) 550#define static_cpu_has_safe(bit) boot_cpu_has(bit)
540#endif 551#endif
541 552
542#define cpu_has_bug(c, bit) cpu_has(c, (bit)) 553#define cpu_has_bug(c, bit) cpu_has(c, (bit))
543#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) 554#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
544#define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)); 555#define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit))
545 556
546#define static_cpu_has_bug(bit) static_cpu_has((bit)) 557#define static_cpu_has_bug(bit) static_cpu_has((bit))
547#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) 558#define static_cpu_has_bug_safe(bit) static_cpu_has_safe((bit))
559#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
548 560
549#define MAX_CPU_FEATURES (NCAPINTS * 32) 561#define MAX_CPU_FEATURES (NCAPINTS * 32)
550#define cpu_have_feature boot_cpu_has 562#define cpu_have_feature boot_cpu_has
551 563
552#define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X" 564#define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X"
553#define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ 565#define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \
554 boot_cpu_data.x86_model 566 boot_cpu_data.x86_model
555 567
556#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ 568#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
557
558#endif /* _ASM_X86_CPUFEATURE_H */ 569#endif /* _ASM_X86_CPUFEATURE_H */
diff --git a/arch/x86/include/asm/fpu-internal.h b/arch/x86/include/asm/fpu-internal.h
index 115e3689cd53..e3b85422cf12 100644
--- a/arch/x86/include/asm/fpu-internal.h
+++ b/arch/x86/include/asm/fpu-internal.h
@@ -293,7 +293,7 @@ static inline int restore_fpu_checking(struct task_struct *tsk)
293 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception 293 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
294 is pending. Clear the x87 state here by setting it to fixed 294 is pending. Clear the x87 state here by setting it to fixed
295 values. "m" is a random variable that should be in L1 */ 295 values. "m" is a random variable that should be in L1 */
296 if (unlikely(static_cpu_has_safe(X86_FEATURE_FXSAVE_LEAK))) { 296 if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) {
297 asm volatile( 297 asm volatile(
298 "fnclex\n\t" 298 "fnclex\n\t"
299 "emms\n\t" 299 "emms\n\t"
diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h
index 1da25a5f96f9..a1410db38a1a 100644
--- a/arch/x86/include/asm/mwait.h
+++ b/arch/x86/include/asm/mwait.h
@@ -43,7 +43,7 @@ static inline void __mwait(unsigned long eax, unsigned long ecx)
43static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx) 43static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
44{ 44{
45 if (!current_set_polling_and_test()) { 45 if (!current_set_polling_and_test()) {
46 if (static_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) { 46 if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {
47 mb(); 47 mb();
48 clflush((void *)&current_thread_info()->flags); 48 clflush((void *)&current_thread_info()->flags);
49 mb(); 49 mb();
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index eaefcc66c855..eac9e92fe181 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -297,6 +297,8 @@
297#define MSR_IA32_TSC_ADJUST 0x0000003b 297#define MSR_IA32_TSC_ADJUST 0x0000003b
298#define MSR_IA32_BNDCFGS 0x00000d90 298#define MSR_IA32_BNDCFGS 0x00000d90
299 299
300#define MSR_IA32_XSS 0x00000da0
301
300#define FEATURE_CONTROL_LOCKED (1<<0) 302#define FEATURE_CONTROL_LOCKED (1<<0)
301#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 303#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
302#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 304#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index ce8b8ff0e0ef..bc360d3df60e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -8,6 +8,7 @@
8#include <asm/processor.h> 8#include <asm/processor.h>
9#include <asm/apic.h> 9#include <asm/apic.h>
10#include <asm/cpu.h> 10#include <asm/cpu.h>
11#include <asm/smp.h>
11#include <asm/pci-direct.h> 12#include <asm/pci-direct.h>
12 13
13#ifdef CONFIG_X86_64 14#ifdef CONFIG_X86_64
@@ -50,7 +51,6 @@ static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
50 return wrmsr_safe_regs(gprs); 51 return wrmsr_safe_regs(gprs);
51} 52}
52 53
53#ifdef CONFIG_X86_32
54/* 54/*
55 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 55 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
56 * misexecution of code under Linux. Owners of such processors should 56 * misexecution of code under Linux. Owners of such processors should
@@ -70,6 +70,7 @@ __asm__(".globl vide\n\t.align 4\nvide: ret");
70 70
71static void init_amd_k5(struct cpuinfo_x86 *c) 71static void init_amd_k5(struct cpuinfo_x86 *c)
72{ 72{
73#ifdef CONFIG_X86_32
73/* 74/*
74 * General Systems BIOSen alias the cpu frequency registers 75 * General Systems BIOSen alias the cpu frequency registers
75 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 76 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
@@ -83,11 +84,12 @@ static void init_amd_k5(struct cpuinfo_x86 *c)
83 if (inl(CBAR) & CBAR_ENB) 84 if (inl(CBAR) & CBAR_ENB)
84 outl(0 | CBAR_KEY, CBAR); 85 outl(0 | CBAR_KEY, CBAR);
85 } 86 }
87#endif
86} 88}
87 89
88
89static void init_amd_k6(struct cpuinfo_x86 *c) 90static void init_amd_k6(struct cpuinfo_x86 *c)
90{ 91{
92#ifdef CONFIG_X86_32
91 u32 l, h; 93 u32 l, h;
92 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 94 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
93 95
@@ -176,10 +178,44 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
176 /* placeholder for any needed mods */ 178 /* placeholder for any needed mods */
177 return; 179 return;
178 } 180 }
181#endif
179} 182}
180 183
181static void amd_k7_smp_check(struct cpuinfo_x86 *c) 184static void init_amd_k7(struct cpuinfo_x86 *c)
182{ 185{
186#ifdef CONFIG_X86_32
187 u32 l, h;
188
189 /*
190 * Bit 15 of Athlon specific MSR 15, needs to be 0
191 * to enable SSE on Palomino/Morgan/Barton CPU's.
192 * If the BIOS didn't enable it already, enable it here.
193 */
194 if (c->x86_model >= 6 && c->x86_model <= 10) {
195 if (!cpu_has(c, X86_FEATURE_XMM)) {
196 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
197 msr_clear_bit(MSR_K7_HWCR, 15);
198 set_cpu_cap(c, X86_FEATURE_XMM);
199 }
200 }
201
202 /*
203 * It's been determined by AMD that Athlons since model 8 stepping 1
204 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
205 * As per AMD technical note 27212 0.2
206 */
207 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
208 rdmsr(MSR_K7_CLK_CTL, l, h);
209 if ((l & 0xfff00000) != 0x20000000) {
210 printk(KERN_INFO
211 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
212 l, ((l & 0x000fffff)|0x20000000));
213 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
214 }
215 }
216
217 set_cpu_cap(c, X86_FEATURE_K7);
218
183 /* calling is from identify_secondary_cpu() ? */ 219 /* calling is from identify_secondary_cpu() ? */
184 if (!c->cpu_index) 220 if (!c->cpu_index)
185 return; 221 return;
@@ -207,7 +243,7 @@ static void amd_k7_smp_check(struct cpuinfo_x86 *c)
207 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 243 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
208 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 244 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
209 (c->x86_model > 7)) 245 (c->x86_model > 7))
210 if (cpu_has_mp) 246 if (cpu_has(c, X86_FEATURE_MP))
211 return; 247 return;
212 248
213 /* If we get here, not a certified SMP capable AMD system. */ 249 /* If we get here, not a certified SMP capable AMD system. */
@@ -219,45 +255,8 @@ static void amd_k7_smp_check(struct cpuinfo_x86 *c)
219 WARN_ONCE(1, "WARNING: This combination of AMD" 255 WARN_ONCE(1, "WARNING: This combination of AMD"
220 " processors is not suitable for SMP.\n"); 256 " processors is not suitable for SMP.\n");
221 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 257 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
222}
223
224static void init_amd_k7(struct cpuinfo_x86 *c)
225{
226 u32 l, h;
227
228 /*
229 * Bit 15 of Athlon specific MSR 15, needs to be 0
230 * to enable SSE on Palomino/Morgan/Barton CPU's.
231 * If the BIOS didn't enable it already, enable it here.
232 */
233 if (c->x86_model >= 6 && c->x86_model <= 10) {
234 if (!cpu_has(c, X86_FEATURE_XMM)) {
235 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
236 msr_clear_bit(MSR_K7_HWCR, 15);
237 set_cpu_cap(c, X86_FEATURE_XMM);
238 }
239 }
240
241 /*
242 * It's been determined by AMD that Athlons since model 8 stepping 1
243 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
244 * As per AMD technical note 27212 0.2
245 */
246 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
247 rdmsr(MSR_K7_CLK_CTL, l, h);
248 if ((l & 0xfff00000) != 0x20000000) {
249 printk(KERN_INFO
250 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
251 l, ((l & 0x000fffff)|0x20000000));
252 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
253 }
254 }
255
256 set_cpu_cap(c, X86_FEATURE_K7);
257
258 amd_k7_smp_check(c);
259}
260#endif 258#endif
259}
261 260
262#ifdef CONFIG_NUMA 261#ifdef CONFIG_NUMA
263/* 262/*
@@ -446,6 +445,26 @@ static void early_init_amd_mc(struct cpuinfo_x86 *c)
446 445
447static void bsp_init_amd(struct cpuinfo_x86 *c) 446static void bsp_init_amd(struct cpuinfo_x86 *c)
448{ 447{
448
449#ifdef CONFIG_X86_64
450 if (c->x86 >= 0xf) {
451 unsigned long long tseg;
452
453 /*
454 * Split up direct mapping around the TSEG SMM area.
455 * Don't do it for gbpages because there seems very little
456 * benefit in doing so.
457 */
458 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
459 unsigned long pfn = tseg >> PAGE_SHIFT;
460
461 printk(KERN_DEBUG "tseg: %010llx\n", tseg);
462 if (pfn_range_is_mapped(pfn, pfn + 1))
463 set_memory_4k((unsigned long)__va(tseg), 1);
464 }
465 }
466#endif
467
449 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 468 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
450 469
451 if (c->x86 > 0x10 || 470 if (c->x86 > 0x10 ||
@@ -515,101 +534,74 @@ static const int amd_erratum_383[];
515static const int amd_erratum_400[]; 534static const int amd_erratum_400[];
516static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 535static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
517 536
518static void init_amd(struct cpuinfo_x86 *c) 537static void init_amd_k8(struct cpuinfo_x86 *c)
519{ 538{
520 u32 dummy; 539 u32 level;
521 unsigned long long value; 540 u64 value;
522
523#ifdef CONFIG_SMP
524 /*
525 * Disable TLB flush filter by setting HWCR.FFDIS on K8
526 * bit 6 of msr C001_0015
527 *
528 * Errata 63 for SH-B3 steppings
529 * Errata 122 for all steppings (F+ have it disabled by default)
530 */
531 if (c->x86 == 0xf)
532 msr_set_bit(MSR_K7_HWCR, 6);
533#endif
534 541
535 early_init_amd(c); 542 /* On C+ stepping K8 rep microcode works well for copy/memset */
543 level = cpuid_eax(1);
544 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
545 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
536 546
537 /* 547 /*
538 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 548 * Some BIOSes incorrectly force this feature, but only K8 revision D
539 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 549 * (model = 0x14) and later actually support it.
550 * (AMD Erratum #110, docId: 25759).
540 */ 551 */
541 clear_cpu_cap(c, 0*32+31); 552 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
542 553 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
543#ifdef CONFIG_X86_64 554 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
544 /* On C+ stepping K8 rep microcode works well for copy/memset */ 555 value &= ~BIT_64(32);
545 if (c->x86 == 0xf) { 556 wrmsrl_amd_safe(0xc001100d, value);
546 u32 level;
547
548 level = cpuid_eax(1);
549 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
550 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
551
552 /*
553 * Some BIOSes incorrectly force this feature, but only K8
554 * revision D (model = 0x14) and later actually support it.
555 * (AMD Erratum #110, docId: 25759).
556 */
557 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
558 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
559 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
560 value &= ~(1ULL << 32);
561 wrmsrl_amd_safe(0xc001100d, value);
562 }
563 } 557 }
564
565 } 558 }
566 if (c->x86 >= 0x10)
567 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
568 559
569 /* get apicid instead of initial apic id from cpuid */ 560 if (!c->x86_model_id[0])
570 c->apicid = hard_smp_processor_id(); 561 strcpy(c->x86_model_id, "Hammer");
571#else 562}
563
564static void init_amd_gh(struct cpuinfo_x86 *c)
565{
566#ifdef CONFIG_X86_64
567 /* do this for boot cpu */
568 if (c == &boot_cpu_data)
569 check_enable_amd_mmconf_dmi();
570
571 fam10h_check_enable_mmcfg();
572#endif
572 573
573 /* 574 /*
574 * FIXME: We should handle the K5 here. Set up the write 575 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
575 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 576 * is always needed when GART is enabled, even in a kernel which has no
576 * no bus pipeline) 577 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
578 * If it doesn't, we do it here as suggested by the BKDG.
579 *
580 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
577 */ 581 */
582 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
578 583
579 switch (c->x86) { 584 /*
580 case 4: 585 * On family 10h BIOS may not have properly enabled WC+ support, causing
581 init_amd_k5(c); 586 * it to be converted to CD memtype. This may result in performance
582 break; 587 * degradation for certain nested-paging guests. Prevent this conversion
583 case 5: 588 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
584 init_amd_k6(c); 589 *
585 break; 590 * NOTE: we want to use the _safe accessors so as not to #GP kvm
586 case 6: /* An Athlon/Duron */ 591 * guests on older kvm hosts.
587 init_amd_k7(c); 592 */
588 break; 593 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
589 }
590 594
591 /* K6s reports MCEs but don't actually have all the MSRs */ 595 if (cpu_has_amd_erratum(c, amd_erratum_383))
592 if (c->x86 < 6) 596 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
593 clear_cpu_cap(c, X86_FEATURE_MCE); 597}
594#endif
595 598
596 /* Enable workaround for FXSAVE leak */ 599static void init_amd_bd(struct cpuinfo_x86 *c)
597 if (c->x86 >= 6) 600{
598 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 601 u64 value;
599
600 if (!c->x86_model_id[0]) {
601 switch (c->x86) {
602 case 0xf:
603 /* Should distinguish Models here, but this is only
604 a fallback anyways. */
605 strcpy(c->x86_model_id, "Hammer");
606 break;
607 }
608 }
609 602
610 /* re-enable TopologyExtensions if switched off by BIOS */ 603 /* re-enable TopologyExtensions if switched off by BIOS */
611 if ((c->x86 == 0x15) && 604 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
612 (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
613 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 605 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
614 606
615 if (msr_set_bit(0xc0011005, 54) > 0) { 607 if (msr_set_bit(0xc0011005, 54) > 0) {
@@ -625,14 +617,60 @@ static void init_amd(struct cpuinfo_x86 *c)
625 * The way access filter has a performance penalty on some workloads. 617 * The way access filter has a performance penalty on some workloads.
626 * Disable it on the affected CPUs. 618 * Disable it on the affected CPUs.
627 */ 619 */
628 if ((c->x86 == 0x15) && 620 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
629 (c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
630
631 if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) { 621 if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) {
632 value |= 0x1E; 622 value |= 0x1E;
633 wrmsrl_safe(0xc0011021, value); 623 wrmsrl_safe(0xc0011021, value);
634 } 624 }
635 } 625 }
626}
627
628static void init_amd(struct cpuinfo_x86 *c)
629{
630 u32 dummy;
631
632#ifdef CONFIG_SMP
633 /*
634 * Disable TLB flush filter by setting HWCR.FFDIS on K8
635 * bit 6 of msr C001_0015
636 *
637 * Errata 63 for SH-B3 steppings
638 * Errata 122 for all steppings (F+ have it disabled by default)
639 */
640 if (c->x86 == 0xf)
641 msr_set_bit(MSR_K7_HWCR, 6);
642#endif
643
644 early_init_amd(c);
645
646 /*
647 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
648 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
649 */
650 clear_cpu_cap(c, 0*32+31);
651
652 if (c->x86 >= 0x10)
653 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
654
655 /* get apicid instead of initial apic id from cpuid */
656 c->apicid = hard_smp_processor_id();
657
658 /* K6s reports MCEs but don't actually have all the MSRs */
659 if (c->x86 < 6)
660 clear_cpu_cap(c, X86_FEATURE_MCE);
661
662 switch (c->x86) {
663 case 4: init_amd_k5(c); break;
664 case 5: init_amd_k6(c); break;
665 case 6: init_amd_k7(c); break;
666 case 0xf: init_amd_k8(c); break;
667 case 0x10: init_amd_gh(c); break;
668 case 0x15: init_amd_bd(c); break;
669 }
670
671 /* Enable workaround for FXSAVE leak */
672 if (c->x86 >= 6)
673 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
636 674
637 cpu_detect_cache_sizes(c); 675 cpu_detect_cache_sizes(c);
638 676
@@ -656,33 +694,6 @@ static void init_amd(struct cpuinfo_x86 *c)
656 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 694 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
657 } 695 }
658 696
659#ifdef CONFIG_X86_64
660 if (c->x86 == 0x10) {
661 /* do this for boot cpu */
662 if (c == &boot_cpu_data)
663 check_enable_amd_mmconf_dmi();
664
665 fam10h_check_enable_mmcfg();
666 }
667
668 if (c == &boot_cpu_data && c->x86 >= 0xf) {
669 unsigned long long tseg;
670
671 /*
672 * Split up direct mapping around the TSEG SMM area.
673 * Don't do it for gbpages because there seems very little
674 * benefit in doing so.
675 */
676 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
677 unsigned long pfn = tseg >> PAGE_SHIFT;
678
679 printk(KERN_DEBUG "tseg: %010llx\n", tseg);
680 if (pfn_range_is_mapped(pfn, pfn + 1))
681 set_memory_4k((unsigned long)__va(tseg), 1);
682 }
683 }
684#endif
685
686 /* 697 /*
687 * Family 0x12 and above processors have APIC timer 698 * Family 0x12 and above processors have APIC timer
688 * running in deep C states. 699 * running in deep C states.
@@ -690,34 +701,6 @@ static void init_amd(struct cpuinfo_x86 *c)
690 if (c->x86 > 0x11) 701 if (c->x86 > 0x11)
691 set_cpu_cap(c, X86_FEATURE_ARAT); 702 set_cpu_cap(c, X86_FEATURE_ARAT);
692 703
693 if (c->x86 == 0x10) {
694 /*
695 * Disable GART TLB Walk Errors on Fam10h. We do this here
696 * because this is always needed when GART is enabled, even in a
697 * kernel which has no MCE support built in.
698 * BIOS should disable GartTlbWlk Errors already. If
699 * it doesn't, do it here as suggested by the BKDG.
700 *
701 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
702 */
703 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
704
705 /*
706 * On family 10h BIOS may not have properly enabled WC+ support,
707 * causing it to be converted to CD memtype. This may result in
708 * performance degradation for certain nested-paging guests.
709 * Prevent this conversion by clearing bit 24 in
710 * MSR_AMD64_BU_CFG2.
711 *
712 * NOTE: we want to use the _safe accessors so as not to #GP kvm
713 * guests on older kvm hosts.
714 */
715 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
716
717 if (cpu_has_amd_erratum(c, amd_erratum_383))
718 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
719 }
720
721 if (cpu_has_amd_erratum(c, amd_erratum_400)) 704 if (cpu_has_amd_erratum(c, amd_erratum_400))
722 set_cpu_bug(c, X86_BUG_AMD_APIC_C1E); 705 set_cpu_bug(c, X86_BUG_AMD_APIC_C1E);
723 706
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index ef1b93f18ed1..188a8c5cc094 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -634,6 +634,15 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
634 c->x86_capability[9] = ebx; 634 c->x86_capability[9] = ebx;
635 } 635 }
636 636
637 /* Extended state features: level 0x0000000d */
638 if (c->cpuid_level >= 0x0000000d) {
639 u32 eax, ebx, ecx, edx;
640
641 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
642
643 c->x86_capability[10] = eax;
644 }
645
637 /* AMD-defined flags: level 0x80000001 */ 646 /* AMD-defined flags: level 0x80000001 */
638 xlvl = cpuid_eax(0x80000000); 647 xlvl = cpuid_eax(0x80000000);
639 c->extended_cpuid_level = xlvl; 648 c->extended_cpuid_level = xlvl;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index f9e4fdd3b877..9483ee5b3991 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -253,7 +253,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
253 */ 253 */
254 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && 254 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
255 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 255 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
256 set_cpu_cap(c, X86_FEATURE_11AP); 256 set_cpu_bug(c, X86_BUG_11AP);
257 257
258 258
259#ifdef CONFIG_X86_INTEL_USERCOPY 259#ifdef CONFIG_X86_INTEL_USERCOPY
@@ -402,7 +402,7 @@ static void init_intel(struct cpuinfo_x86 *c)
402 402
403 if (c->x86 == 6 && cpu_has_clflush && 403 if (c->x86 == 6 && cpu_has_clflush &&
404 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 404 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
405 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR); 405 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
406 406
407#ifdef CONFIG_X86_64 407#ifdef CONFIG_X86_64
408 if (c->x86 == 15) 408 if (c->x86 == 15)
diff --git a/arch/x86/kernel/cpu/mkcapflags.sh b/arch/x86/kernel/cpu/mkcapflags.sh
index 2bf616505499..e2b22df964cd 100644
--- a/arch/x86/kernel/cpu/mkcapflags.sh
+++ b/arch/x86/kernel/cpu/mkcapflags.sh
@@ -1,23 +1,25 @@
1#!/bin/sh 1#!/bin/sh
2# 2#
3# Generate the x86_cap_flags[] array from include/asm/cpufeature.h 3# Generate the x86_cap/bug_flags[] arrays from include/asm/cpufeature.h
4# 4#
5 5
6IN=$1 6IN=$1
7OUT=$2 7OUT=$2
8 8
9TABS="$(printf '\t\t\t\t\t')" 9function dump_array()
10trap 'rm "$OUT"' EXIT 10{
11 ARRAY=$1
12 SIZE=$2
13 PFX=$3
14 POSTFIX=$4
11 15
12( 16 PFX_SZ=$(echo $PFX | wc -c)
13 echo "#ifndef _ASM_X86_CPUFEATURE_H" 17 TABS="$(printf '\t\t\t\t\t')"
14 echo "#include <asm/cpufeature.h>" 18
15 echo "#endif" 19 echo "const char * const $ARRAY[$SIZE] = {"
16 echo ""
17 echo "const char * const x86_cap_flags[NCAPINTS*32] = {"
18 20
19 # Iterate through any input lines starting with #define X86_FEATURE_ 21 # Iterate through any input lines starting with #define $PFX
20 sed -n -e 's/\t/ /g' -e 's/^ *# *define *X86_FEATURE_//p' $IN | 22 sed -n -e 's/\t/ /g' -e "s/^ *# *define *$PFX//p" $IN |
21 while read i 23 while read i
22 do 24 do
23 # Name is everything up to the first whitespace 25 # Name is everything up to the first whitespace
@@ -31,11 +33,32 @@ trap 'rm "$OUT"' EXIT
31 # Name is uppercase, VALUE is all lowercase 33 # Name is uppercase, VALUE is all lowercase
32 VALUE="$(echo "$VALUE" | tr A-Z a-z)" 34 VALUE="$(echo "$VALUE" | tr A-Z a-z)"
33 35
34 TABCOUNT=$(( ( 5*8 - 14 - $(echo "$NAME" | wc -c) ) / 8 )) 36 if [ -n "$POSTFIX" ]; then
35 printf "\t[%s]%.*s = %s,\n" \ 37 T=$(( $PFX_SZ + $(echo $POSTFIX | wc -c) + 2 ))
36 "X86_FEATURE_$NAME" "$TABCOUNT" "$TABS" "$VALUE" 38 TABS="$(printf '\t\t\t\t\t\t')"
39 TABCOUNT=$(( ( 6*8 - ($T + 1) - $(echo "$NAME" | wc -c) ) / 8 ))
40 printf "\t[%s - %s]%.*s = %s,\n" "$PFX$NAME" "$POSTFIX" "$TABCOUNT" "$TABS" "$VALUE"
41 else
42 TABCOUNT=$(( ( 5*8 - ($PFX_SZ + 1) - $(echo "$NAME" | wc -c) ) / 8 ))
43 printf "\t[%s]%.*s = %s,\n" "$PFX$NAME" "$TABCOUNT" "$TABS" "$VALUE"
44 fi
37 done 45 done
38 echo "};" 46 echo "};"
47}
48
49trap 'rm "$OUT"' EXIT
50
51(
52 echo "#ifndef _ASM_X86_CPUFEATURE_H"
53 echo "#include <asm/cpufeature.h>"
54 echo "#endif"
55 echo ""
56
57 dump_array "x86_cap_flags" "NCAPINTS*32" "X86_FEATURE_" ""
58 echo ""
59
60 dump_array "x86_bug_flags" "NBUGINTS*32" "X86_BUG_" "NCAPINTS*32"
61
39) > $OUT 62) > $OUT
40 63
41trap - EXIT 64trap - EXIT
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 06fe3ed8b851..5433658e598d 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -97,6 +97,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
97 if (cpu_has(c, i) && x86_cap_flags[i] != NULL) 97 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
98 seq_printf(m, " %s", x86_cap_flags[i]); 98 seq_printf(m, " %s", x86_cap_flags[i]);
99 99
100 seq_printf(m, "\nbugs\t\t:");
101 for (i = 0; i < 32*NBUGINTS; i++) {
102 unsigned int bug_bit = 32*NCAPINTS + i;
103
104 if (cpu_has_bug(c, bug_bit) && x86_bug_flags[i])
105 seq_printf(m, " %s", x86_bug_flags[i]);
106 }
107
100 seq_printf(m, "\nbogomips\t: %lu.%02lu\n", 108 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
101 c->loops_per_jiffy/(500000/HZ), 109 c->loops_per_jiffy/(500000/HZ),
102 (c->loops_per_jiffy/(5000/HZ)) % 100); 110 (c->loops_per_jiffy/(5000/HZ)) % 100);
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index b6f794aa1693..4a8013d55947 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -38,7 +38,6 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
38 { X86_FEATURE_PTS, CR_EAX, 6, 0x00000006, 0 }, 38 { X86_FEATURE_PTS, CR_EAX, 6, 0x00000006, 0 },
39 { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 }, 39 { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 },
40 { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, 40 { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 },
41 { X86_FEATURE_XSAVEOPT, CR_EAX, 0, 0x0000000d, 1 },
42 { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, 41 { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 },
43 { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, 42 { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 },
44 { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 }, 43 { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 },
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 14:53:28 -0500