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-rw-r--r--Documentation/devicetree/bindings/clock/exynos3250-clock.txt8
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5433-clock.txt462
-rw-r--r--Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt26
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-core-clock.txt9
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt15
-rw-r--r--Documentation/devicetree/bindings/clock/pwm-clock.txt26
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt3
-rw-r--r--MAINTAINERS3
-rw-r--r--drivers/clk/Kconfig7
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/at91/clk-usb.c64
-rw-r--r--drivers/clk/clk-cdce706.c2
-rw-r--r--drivers/clk/clk-conf.c7
-rw-r--r--drivers/clk/clk-fractional-divider.c3
-rw-r--r--drivers/clk/clk-gpio-gate.c31
-rw-r--r--drivers/clk/clk-mb86s7x.c386
-rw-r--r--drivers/clk/clk-palmas.c2
-rw-r--r--drivers/clk/clk-pwm.c136
-rw-r--r--drivers/clk/clk-si5351.c10
-rw-r--r--drivers/clk/clk-si570.c2
-rw-r--r--drivers/clk/clk.c157
-rw-r--r--drivers/clk/clk.h3
-rw-r--r--drivers/clk/clkdev.c30
-rw-r--r--drivers/clk/hisilicon/clk-hi3620.c70
-rw-r--r--drivers/clk/hisilicon/clk-hix5hd2.c6
-rw-r--r--drivers/clk/mvebu/Kconfig4
-rw-r--r--drivers/clk/mvebu/Makefile1
-rw-r--r--drivers/clk/mvebu/armada-39x.c156
-rw-r--r--drivers/clk/mvebu/common.c17
-rw-r--r--drivers/clk/mvebu/common.h1
-rw-r--r--drivers/clk/mxs/clk-imx23.c12
-rw-r--r--drivers/clk/mxs/clk-imx28.c18
-rw-r--r--drivers/clk/pxa/clk-pxa.h2
-rw-r--r--drivers/clk/pxa/clk-pxa3xx.c3
-rw-r--r--drivers/clk/qcom/Kconfig9
-rw-r--r--drivers/clk/qcom/Makefile1
-rw-r--r--drivers/clk/qcom/clk-pll.c6
-rw-r--r--drivers/clk/qcom/clk-rcg.c188
-rw-r--r--drivers/clk/qcom/clk-rcg.h15
-rw-r--r--drivers/clk/qcom/clk-rcg2.c43
-rw-r--r--drivers/clk/qcom/common.c12
-rw-r--r--drivers/clk/qcom/common.h4
-rw-r--r--drivers/clk/qcom/gcc-apq8084.c62
-rw-r--r--drivers/clk/qcom/gcc-ipq806x.c80
-rw-r--r--drivers/clk/qcom/gcc-msm8660.c22
-rw-r--r--drivers/clk/qcom/gcc-msm8916.c2868
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c32
-rw-r--r--drivers/clk/qcom/gcc-msm8974.c30
-rw-r--r--drivers/clk/qcom/lcc-ipq806x.c35
-rw-r--r--drivers/clk/qcom/lcc-msm8960.c12
-rw-r--r--drivers/clk/qcom/mmcc-apq8084.c168
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c49
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c134
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c2
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c2
-rw-r--r--drivers/clk/rockchip/clk.c3
-rw-r--r--drivers/clk/rockchip/clk.h4
-rw-r--r--drivers/clk/samsung/Makefile1
-rw-r--r--drivers/clk/samsung/clk-exynos-clkout.c4
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c163
-rw-r--r--drivers/clk/samsung/clk-exynos4.c11
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c5423
-rw-r--r--drivers/clk/samsung/clk-s5pv210.c56
-rw-r--r--drivers/clk/st/clkgen-fsyn.c2
-rw-r--r--drivers/clk/st/clkgen-mux.c8
-rw-r--r--drivers/clk/st/clkgen-pll.c4
-rw-r--r--drivers/clk/sunxi/Makefile1
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c185
-rw-r--r--drivers/clk/sunxi/clk-usb.c233
-rw-r--r--drivers/clk/tegra/clk-pll.c7
-rw-r--r--drivers/clk/tegra/clk-tegra-fixed.c24
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c2
-rw-r--r--drivers/clk/tegra/clk-tegra114.c36
-rw-r--r--drivers/clk/tegra/clk-tegra124.c22
-rw-r--r--drivers/clk/tegra/clk-tegra30.c23
-rw-r--r--drivers/clk/tegra/clk.c16
-rw-r--r--drivers/clk/tegra/clk.h10
-rw-r--r--drivers/clk/ti/apll.c5
-rw-r--r--drivers/clk/ti/autoidle.c2
-rw-r--r--drivers/clk/ti/clk-3xxx-legacy.c16
-rw-r--r--drivers/clk/ti/clk-3xxx.c19
-rw-r--r--drivers/clk/ti/clk-44xx.c11
-rw-r--r--drivers/clk/ti/clk-54xx.c22
-rw-r--r--drivers/clk/ti/clk-7xx.c18
-rw-r--r--drivers/clk/ti/clk-dra7-atl.c2
-rw-r--r--drivers/clk/ti/clk.c7
-rw-r--r--drivers/clk/ti/clockdomain.c2
-rw-r--r--drivers/clk/ti/composite.c2
-rw-r--r--drivers/clk/ti/divider.c4
-rw-r--r--drivers/clk/ti/dpll.c6
-rw-r--r--drivers/clk/ti/fapll.c270
-rw-r--r--drivers/clk/ti/gate.c4
-rw-r--r--drivers/clk/ti/interface.c2
-rw-r--r--drivers/clk/ti/mux.c4
-rw-r--r--drivers/clk/versatile/clk-versatile.c2
-rw-r--r--drivers/clk/versatile/clk-vexpress-osc.c2
-rw-r--r--drivers/clk/zynq/clkc.c24
-rw-r--r--include/dt-bindings/clock/exynos3250.h61
-rw-r--r--include/dt-bindings/clock/exynos5433.h1403
-rw-r--r--include/dt-bindings/clock/qcom,gcc-ipq806x.h1
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8916.h156
-rw-r--r--include/dt-bindings/clock/tegra124-car-common.h2
-rw-r--r--include/dt-bindings/reset/qcom,gcc-msm8916.h108
-rw-r--r--include/linux/clk-provider.h2
-rw-r--r--include/linux/clk/at91_pmc.h4
-rw-r--r--include/trace/events/clk.h198
107 files changed, 13217 insertions, 839 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
index f57d9dd9ea85..f1738b88c225 100644
--- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
@@ -9,6 +9,8 @@ Required Properties:
9 - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC. 9 - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
10 - "samsung,exynos3250-cmu-dmc" - controller compatible with 10 - "samsung,exynos3250-cmu-dmc" - controller compatible with
11 Exynos3250 SoC for Dynamic Memory Controller domain. 11 Exynos3250 SoC for Dynamic Memory Controller domain.
12 - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
13 with Exynos3250 SOC
12 14
13- reg: physical base address of the controller and length of memory mapped 15- reg: physical base address of the controller and length of memory mapped
14 region. 16 region.
@@ -36,6 +38,12 @@ Example 1: Examples of clock controller nodes are listed below.
36 #clock-cells = <1>; 38 #clock-cells = <1>;
37 }; 39 };
38 40
41 cmu_isp: clock-controller@10048000 {
42 compatible = "samsung,exynos3250-cmu-isp";
43 reg = <0x10048000 0x1000>;
44 #clock-cells = <1>;
45 };
46
39Example 2: UART controller node that consumes the clock generated by the clock 47Example 2: UART controller node that consumes the clock generated by the clock
40 controller. Refer to the standard clock bindings for information 48 controller. Refer to the standard clock bindings for information
41 about 'clocks' and 'clock-names' property. 49 about 'clocks' and 'clock-names' property.
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
new file mode 100644
index 000000000000..63379b04e052
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -0,0 +1,462 @@
1* Samsung Exynos5433 CMU (Clock Management Units)
2
3The Exynos5433 clock controller generates and supplies clock to various
4controllers within the Exynos5433 SoC.
5
6Required Properties:
7
8- compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
13 which generates clocks for LLI (Low Latency Interface) IP.
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
23 which generates clocks for G2D/MDMA IPs.
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
28 - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
29 and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
30 which generates global data buses clock and global peripheral buses clock.
31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
32 which generates clocks for 3D Graphics Engine IP.
33 - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
34 which generates clocks for GSCALER IPs.
35 - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
36 which generates clocks for Cortex-A53 Quad-core processor.
37 - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
38 which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
39 L2 cache controller.
40 - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
41 which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
42 - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
43 which generates clocks for MFC(Multi-Format Codec) IP.
44 - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
45 which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
46 - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
47 which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
48 - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
49 which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
50 IPs.
51 - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
52 which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
53
54- reg: physical base address of the controller and length of memory mapped
55 region.
56
57- #clock-cells: should be 1.
58
59- clocks: list of the clock controller input clock identifiers,
60 from common clock bindings. Please refer the next section
61 to find the input clocks for a given controller.
62
63- clock-names: list of the clock controller input clock names,
64 as described in clock-bindings.txt.
65
66 Input clocks for top clock controller:
67 - oscclk
68 - sclk_mphy_pll
69 - sclk_mfc_pll
70 - sclk_bus_pll
71
72 Input clocks for cpif clock controller:
73 - oscclk
74
75 Input clocks for mif clock controller:
76 - oscclk
77 - sclk_mphy_pll
78
79 Input clocks for fsys clock controller:
80 - oscclk
81 - sclk_ufs_mphy
82 - div_aclk_fsys_200
83 - sclk_pcie_100_fsys
84 - sclk_ufsunipro_fsys
85 - sclk_mmc2_fsys
86 - sclk_mmc1_fsys
87 - sclk_mmc0_fsys
88 - sclk_usbhost30_fsys
89 - sclk_usbdrd30_fsys
90
91 Input clocks for g2d clock controller:
92 - oscclk
93 - aclk_g2d_266
94 - aclk_g2d_400
95
96 Input clocks for disp clock controller:
97 - oscclk
98 - sclk_dsim1_disp
99 - sclk_dsim0_disp
100 - sclk_dsd_disp
101 - sclk_decon_tv_eclk_disp
102 - sclk_decon_vclk_disp
103 - sclk_decon_eclk_disp
104 - sclk_decon_tv_vclk_disp
105 - aclk_disp_333
106
107 Input clocks for bus0 clock controller:
108 - aclk_bus0_400
109
110 Input clocks for bus1 clock controller:
111 - aclk_bus1_400
112
113 Input clocks for bus2 clock controller:
114 - oscclk
115 - aclk_bus2_400
116
117 Input clocks for g3d clock controller:
118 - oscclk
119 - aclk_g3d_400
120
121 Input clocks for gscl clock controller:
122 - oscclk
123 - aclk_gscl_111
124 - aclk_gscl_333
125
126 Input clocks for apollo clock controller:
127 - oscclk
128 - sclk_bus_pll_apollo
129
130 Input clocks for atlas clock controller:
131 - oscclk
132 - sclk_bus_pll_atlas
133
134 Input clocks for mscl clock controller:
135 - oscclk
136 - sclk_jpeg_mscl
137 - aclk_mscl_400
138
139 Input clocks for mfc clock controller:
140 - oscclk
141 - aclk_mfc_400
142
143 Input clocks for hevc clock controller:
144 - oscclk
145 - aclk_hevc_400
146
147 Input clocks for isp clock controller:
148 - oscclk
149 - aclk_isp_dis_400
150 - aclk_isp_400
151
152 Input clocks for cam0 clock controller:
153 - oscclk
154 - aclk_cam0_333
155 - aclk_cam0_400
156 - aclk_cam0_552
157
158 Input clocks for cam1 clock controller:
159 - oscclk
160 - sclk_isp_uart_cam1
161 - sclk_isp_spi1_cam1
162 - sclk_isp_spi0_cam1
163 - aclk_cam1_333
164 - aclk_cam1_400
165 - aclk_cam1_552
166
167Each clock is assigned an identifier and client nodes can use this identifier
168to specify the clock which they consume.
169
170All available clocks are defined as preprocessor macros in
171dt-bindings/clock/exynos5433.h header and can be used in device
172tree sources.
173
174Example 1: Examples of 'oscclk' source clock node are listed below.
175
176 xxti: xxti {
177 compatible = "fixed-clock";
178 clock-output-names = "oscclk";
179 #clock-cells = <0>;
180 };
181
182Example 2: Examples of clock controller nodes are listed below.
183
184 cmu_top: clock-controller@10030000 {
185 compatible = "samsung,exynos5433-cmu-top";
186 reg = <0x10030000 0x0c04>;
187 #clock-cells = <1>;
188
189 clock-names = "oscclk",
190 "sclk_mphy_pll",
191 "sclk_mfc_pll",
192 "sclk_bus_pll";
193 clocks = <&xxti>,
194 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
195 <&cmu_mif CLK_SCLK_MFC_PLL>,
196 <&cmu_mif CLK_SCLK_BUS_PLL>;
197 };
198
199 cmu_cpif: clock-controller@10fc0000 {
200 compatible = "samsung,exynos5433-cmu-cpif";
201 reg = <0x10fc0000 0x0c04>;
202 #clock-cells = <1>;
203
204 clock-names = "oscclk";
205 clocks = <&xxti>;
206 };
207
208 cmu_mif: clock-controller@105b0000 {
209 compatible = "samsung,exynos5433-cmu-mif";
210 reg = <0x105b0000 0x100c>;
211 #clock-cells = <1>;
212
213 clock-names = "oscclk",
214 "sclk_mphy_pll";
215 clocks = <&xxti>,
216 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
217 };
218
219 cmu_peric: clock-controller@14c80000 {
220 compatible = "samsung,exynos5433-cmu-peric";
221 reg = <0x14c80000 0x0b08>;
222 #clock-cells = <1>;
223 };
224
225 cmu_peris: clock-controller@10040000 {
226 compatible = "samsung,exynos5433-cmu-peris";
227 reg = <0x10040000 0x0b20>;
228 #clock-cells = <1>;
229 };
230
231 cmu_fsys: clock-controller@156e0000 {
232 compatible = "samsung,exynos5433-cmu-fsys";
233 reg = <0x156e0000 0x0b04>;
234 #clock-cells = <1>;
235
236 clock-names = "oscclk",
237 "sclk_ufs_mphy",
238 "div_aclk_fsys_200",
239 "sclk_pcie_100_fsys",
240 "sclk_ufsunipro_fsys",
241 "sclk_mmc2_fsys",
242 "sclk_mmc1_fsys",
243 "sclk_mmc0_fsys",
244 "sclk_usbhost30_fsys",
245 "sclk_usbdrd30_fsys";
246 clocks = <&xxti>,
247 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
248 <&cmu_top CLK_DIV_ACLK_FSYS_200>,
249 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
250 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
251 <&cmu_top CLK_SCLK_MMC2_FSYS>,
252 <&cmu_top CLK_SCLK_MMC1_FSYS>,
253 <&cmu_top CLK_SCLK_MMC0_FSYS>,
254 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
255 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
256 };
257
258 cmu_g2d: clock-controller@12460000 {
259 compatible = "samsung,exynos5433-cmu-g2d";
260 reg = <0x12460000 0x0b08>;
261 #clock-cells = <1>;
262
263 clock-names = "oscclk",
264 "aclk_g2d_266",
265 "aclk_g2d_400";
266 clocks = <&xxti>,
267 <&cmu_top CLK_ACLK_G2D_266>,
268 <&cmu_top CLK_ACLK_G2D_400>;
269 };
270
271 cmu_disp: clock-controller@13b90000 {
272 compatible = "samsung,exynos5433-cmu-disp";
273 reg = <0x13b90000 0x0c04>;
274 #clock-cells = <1>;
275
276 clock-names = "oscclk",
277 "sclk_dsim1_disp",
278 "sclk_dsim0_disp",
279 "sclk_dsd_disp",
280 "sclk_decon_tv_eclk_disp",
281 "sclk_decon_vclk_disp",
282 "sclk_decon_eclk_disp",
283 "sclk_decon_tv_vclk_disp",
284 "aclk_disp_333";
285 clocks = <&xxti>,
286 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
287 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
288 <&cmu_mif CLK_SCLK_DSD_DISP>,
289 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
290 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
291 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
292 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
293 <&cmu_mif CLK_ACLK_DISP_333>;
294 };
295
296 cmu_aud: clock-controller@114c0000 {
297 compatible = "samsung,exynos5433-cmu-aud";
298 reg = <0x114c0000 0x0b04>;
299 #clock-cells = <1>;
300 };
301
302 cmu_bus0: clock-controller@13600000 {
303 compatible = "samsung,exynos5433-cmu-bus0";
304 reg = <0x13600000 0x0b04>;
305 #clock-cells = <1>;
306
307 clock-names = "aclk_bus0_400";
308 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
309 };
310
311 cmu_bus1: clock-controller@14800000 {
312 compatible = "samsung,exynos5433-cmu-bus1";
313 reg = <0x14800000 0x0b04>;
314 #clock-cells = <1>;
315
316 clock-names = "aclk_bus1_400";
317 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
318 };
319
320 cmu_bus2: clock-controller@13400000 {
321 compatible = "samsung,exynos5433-cmu-bus2";
322 reg = <0x13400000 0x0b04>;
323 #clock-cells = <1>;
324
325 clock-names = "oscclk", "aclk_bus2_400";
326 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
327 };
328
329 cmu_g3d: clock-controller@14aa0000 {
330 compatible = "samsung,exynos5433-cmu-g3d";
331 reg = <0x14aa0000 0x1000>;
332 #clock-cells = <1>;
333
334 clock-names = "oscclk", "aclk_g3d_400";
335 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
336 };
337
338 cmu_gscl: clock-controller@13cf0000 {
339 compatible = "samsung,exynos5433-cmu-gscl";
340 reg = <0x13cf0000 0x0b10>;
341 #clock-cells = <1>;
342
343 clock-names = "oscclk",
344 "aclk_gscl_111",
345 "aclk_gscl_333";
346 clocks = <&xxti>,
347 <&cmu_top CLK_ACLK_GSCL_111>,
348 <&cmu_top CLK_ACLK_GSCL_333>;
349 };
350
351 cmu_apollo: clock-controller@11900000 {
352 compatible = "samsung,exynos5433-cmu-apollo";
353 reg = <0x11900000 0x1088>;
354 #clock-cells = <1>;
355
356 clock-names = "oscclk", "sclk_bus_pll_apollo";
357 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
358 };
359
360 cmu_atlas: clock-controller@11800000 {
361 compatible = "samsung,exynos5433-cmu-atlas";
362 reg = <0x11800000 0x1088>;
363 #clock-cells = <1>;
364
365 clock-names = "oscclk", "sclk_bus_pll_atlas";
366 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
367 };
368
369 cmu_mscl: clock-controller@105d0000 {
370 compatible = "samsung,exynos5433-cmu-mscl";
371 reg = <0x105d0000 0x0b10>;
372 #clock-cells = <1>;
373
374 clock-names = "oscclk",
375 "sclk_jpeg_mscl",
376 "aclk_mscl_400";
377 clocks = <&xxti>,
378 <&cmu_top CLK_SCLK_JPEG_MSCL>,
379 <&cmu_top CLK_ACLK_MSCL_400>;
380 };
381
382 cmu_mfc: clock-controller@15280000 {
383 compatible = "samsung,exynos5433-cmu-mfc";
384 reg = <0x15280000 0x0b08>;
385 #clock-cells = <1>;
386
387 clock-names = "oscclk", "aclk_mfc_400";
388 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
389 };
390
391 cmu_hevc: clock-controller@14f80000 {
392 compatible = "samsung,exynos5433-cmu-hevc";
393 reg = <0x14f80000 0x0b08>;
394 #clock-cells = <1>;
395
396 clock-names = "oscclk", "aclk_hevc_400";
397 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
398 };
399
400 cmu_isp: clock-controller@146d0000 {
401 compatible = "samsung,exynos5433-cmu-isp";
402 reg = <0x146d0000 0x0b0c>;
403 #clock-cells = <1>;
404
405 clock-names = "oscclk",
406 "aclk_isp_dis_400",
407 "aclk_isp_400";
408 clocks = <&xxti>,
409 <&cmu_top CLK_ACLK_ISP_DIS_400>,
410 <&cmu_top CLK_ACLK_ISP_400>;
411 };
412
413 cmu_cam0: clock-controller@120d0000 {
414 compatible = "samsung,exynos5433-cmu-cam0";
415 reg = <0x120d0000 0x0b0c>;
416 #clock-cells = <1>;
417
418 clock-names = "oscclk",
419 "aclk_cam0_333",
420 "aclk_cam0_400",
421 "aclk_cam0_552";
422 clocks = <&xxti>,
423 <&cmu_top CLK_ACLK_CAM0_333>,
424 <&cmu_top CLK_ACLK_CAM0_400>,
425 <&cmu_top CLK_ACLK_CAM0_552>;
426 };
427
428 cmu_cam1: clock-controller@145d0000 {
429 compatible = "samsung,exynos5433-cmu-cam1";
430 reg = <0x145d0000 0x0b08>;
431 #clock-cells = <1>;
432
433 clock-names = "oscclk",
434 "sclk_isp_uart_cam1",
435 "sclk_isp_spi1_cam1",
436 "sclk_isp_spi0_cam1",
437 "aclk_cam1_333",
438 "aclk_cam1_400",
439 "aclk_cam1_552";
440 clocks = <&xxti>,
441 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
442 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
443 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
444 <&cmu_top CLK_ACLK_CAM1_333>,
445 <&cmu_top CLK_ACLK_CAM1_400>,
446 <&cmu_top CLK_ACLK_CAM1_552>;
447 };
448
449Example 3: UART controller node that consumes the clock generated by the clock
450 controller.
451
452 serial_0: serial@14C10000 {
453 compatible = "samsung,exynos5433-uart";
454 reg = <0x14C10000 0x100>;
455 interrupts = <0 421 0>;
456 clocks = <&cmu_peric CLK_PCLK_UART0>,
457 <&cmu_peric CLK_SCLK_UART0>;
458 clock-names = "uart", "clk_uart_baud0";
459 pinctrl-names = "default";
460 pinctrl-0 = <&uart0_bus>;
461 status = "disabled";
462 };
diff --git a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
new file mode 100644
index 000000000000..332396265689
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
@@ -0,0 +1,26 @@
1Fujitsu CRG11 clock driver bindings
2-----------------------------------
3
4Required properties :
5- compatible : Shall contain "fujitsu,mb86s70-crg11"
6- #clock-cells : Shall be 3 {cntrlr domain port}
7
8The consumer specifies the desired clock pointing to its phandle.
9
10Example:
11
12 clock: crg11 {
13 compatible = "fujitsu,mb86s70-crg11";
14 #clock-cells = <3>;
15 };
16
17 mhu: mhu0@2b1f0000 {
18 #mbox-cells = <1>;
19 compatible = "arm,mhu";
20 reg = <0 0x2B1F0000 0x1000>;
21 interrupts = <0 36 4>, /* LP Non-Sec */
22 <0 35 4>, /* HP Non-Sec */
23 <0 37 4>; /* Secure */
24 clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
25 clock-names = "clk";
26 };
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index dc5ea5b22da9..670c2af3e931 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -23,6 +23,14 @@ The following is a list of provided IDs and clock names on Armada 380/385:
23 2 = l2clk (L2 Cache clock) 23 2 = l2clk (L2 Cache clock)
24 3 = ddrclk (DDR clock) 24 3 = ddrclk (DDR clock)
25 25
26The following is a list of provided IDs and clock names on Armada 39x:
27 0 = tclk (Internal Bus clock)
28 1 = cpuclk (CPU clock)
29 2 = nbclk (Coherent Fabric clock)
30 3 = hclk (SDRAM Controller Internal Clock)
31 4 = dclk (SDRAM Interface Clock)
32 5 = refclk (Reference Clock)
33
26The following is a list of provided IDs and clock names on Kirkwood and Dove: 34The following is a list of provided IDs and clock names on Kirkwood and Dove:
27 0 = tclk (Internal Bus clock) 35 0 = tclk (Internal Bus clock)
28 1 = cpuclk (CPU0 clock) 36 1 = cpuclk (CPU0 clock)
@@ -39,6 +47,7 @@ Required properties:
39 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks 47 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
40 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks 48 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
41 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks 49 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
50 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
42 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks 51 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
43 "marvell,dove-core-clock" - for Dove SoC core clocks 52 "marvell,dove-core-clock" - for Dove SoC core clocks
44 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) 53 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 76477be742b2..31c7c0c1ce8f 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -1,6 +1,6 @@
1* Gated Clock bindings for Marvell EBU SoCs 1* Gated Clock bindings for Marvell EBU SoCs
2 2
3Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some 3Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
4peripheral clocks to be gated to save some power. The clock consumer 4peripheral clocks to be gated to save some power. The clock consumer
5should specify the desired clock by having the clock ID in its 5should specify the desired clock by having the clock ID in its
6"clocks" phandle cell. The clock ID is directly mapped to the 6"clocks" phandle cell. The clock ID is directly mapped to the
@@ -77,6 +77,18 @@ ID Clock Peripheral
7728 xor1 XOR 1 7728 xor1 XOR 1
7830 sata1 SATA 1 7830 sata1 SATA 1
79 79
80The following is a list of provided IDs for Armada 39x:
81ID Clock Peripheral
82-----------------------------------
835 pex1 PCIe 1
846 pex2 PCIe 2
857 pex3 PCIe 3
868 pex0 PCIe 0
879 usb3h0 USB3 Host 0
8817 sdio SDIO
8922 xor0 XOR 0
9028 xor1 XOR 1
91
80The following is a list of provided IDs for Armada XP: 92The following is a list of provided IDs for Armada XP:
81ID Clock Peripheral 93ID Clock Peripheral
82----------------------------------- 94-----------------------------------
@@ -152,6 +164,7 @@ Required properties:
152 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating 164 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
153 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating 165 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
154 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating 166 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
167 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
155 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating 168 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
156 "marvell,dove-gating-clock" - for Dove SoC clock gating 169 "marvell,dove-gating-clock" - for Dove SoC clock gating
157 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating 170 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
diff --git a/Documentation/devicetree/bindings/clock/pwm-clock.txt b/Documentation/devicetree/bindings/clock/pwm-clock.txt
new file mode 100644
index 000000000000..83db876b3b90
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/pwm-clock.txt
@@ -0,0 +1,26 @@
1Binding for an external clock signal driven by a PWM pin.
2
3This binding uses the common clock binding[1] and the common PWM binding[2].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6[2] Documentation/devicetree/bindings/pwm/pwm.txt
7
8Required properties:
9- compatible : shall be "pwm-clock".
10- #clock-cells : from common clock binding; shall be set to 0.
11- pwms : from common PWM binding; this determines the clock frequency
12 via the period given in the PWM specifier.
13
14Optional properties:
15- clock-output-names : From common clock binding.
16- clock-frequency : Exact output frequency, in case the PWM period
17 is not exact but was rounded to nanoseconds.
18
19Example:
20 clock {
21 compatible = "pwm-clock";
22 #clock-cells = <0>;
23 clock-frequency = <25000000>;
24 clock-output-names = "mipi_mclk";
25 pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */
26 };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index aba3d254e037..54c23f34f194 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -8,6 +8,7 @@ Required properties :
8 "qcom,gcc-apq8084" 8 "qcom,gcc-apq8084"
9 "qcom,gcc-ipq8064" 9 "qcom,gcc-ipq8064"
10 "qcom,gcc-msm8660" 10 "qcom,gcc-msm8660"
11 "qcom,gcc-msm8916"
11 "qcom,gcc-msm8960" 12 "qcom,gcc-msm8960"
12 "qcom,gcc-msm8974" 13 "qcom,gcc-msm8974"
13 "qcom,gcc-msm8974pro" 14 "qcom,gcc-msm8974pro"
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 60b44285250d..4fa11af3d378 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -20,6 +20,7 @@ Required properties:
20 "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 20 "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
21 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates 21 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
22 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock 22 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
23 "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
23 "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 24 "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
24 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 25 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
25 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 26 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
@@ -66,6 +67,8 @@ Required properties:
66 "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 67 "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
67 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 68 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
68 "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 69 "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
70 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
71 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
69 72
70Required properties for all clocks: 73Required properties for all clocks:
71- reg : shall be the control register address for the clock. 74- reg : shall be the control register address for the clock.
diff --git a/MAINTAINERS b/MAINTAINERS
index ce3eb0faffe6..3264719740f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2577,6 +2577,7 @@ F: include/linux/cleancache.h
2577 2577
2578CLK API 2578CLK API
2579M: Russell King <linux@arm.linux.org.uk> 2579M: Russell King <linux@arm.linux.org.uk>
2580L: linux-clk@vger.kernel.org
2580S: Maintained 2581S: Maintained
2581F: include/linux/clk.h 2582F: include/linux/clk.h
2582 2583
@@ -2637,7 +2638,7 @@ F: drivers/media/platform/coda/
2637COMMON CLK FRAMEWORK 2638COMMON CLK FRAMEWORK
2638M: Mike Turquette <mturquette@linaro.org> 2639M: Mike Turquette <mturquette@linaro.org>
2639M: Stephen Boyd <sboyd@codeaurora.org> 2640M: Stephen Boyd <sboyd@codeaurora.org>
2640L: linux-kernel@vger.kernel.org 2641L: linux-clk@vger.kernel.org
2641T: git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git 2642T: git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
2642S: Maintained 2643S: Maintained
2643F: drivers/clk/ 2644F: drivers/clk/
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 0b474a04730f..9897f353bf1a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -130,6 +130,13 @@ config COMMON_CLK_PALMAS
130 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO 130 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
131 using common clock framework. 131 using common clock framework.
132 132
133config COMMON_CLK_PWM
134 tristate "Clock driver for PWMs used as clock outputs"
135 depends on PWM
136 ---help---
137 Adapter driver so that any PWM output can be (mis)used as clock signal
138 at 50% duty cycle.
139
133config COMMON_CLK_PXA 140config COMMON_CLK_PXA
134 def_bool COMMON_CLK && ARCH_PXA 141 def_bool COMMON_CLK && ARCH_PXA
135 ---help--- 142 ---help---
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e43ff53f85a6..3d00c25382c5 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
28obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o 28obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o
29obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o 29obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
30obj-$(CONFIG_COMMON_CLK_MAX77802) += clk-max77802.o 30obj-$(CONFIG_COMMON_CLK_MAX77802) += clk-max77802.o
31obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o
31obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o 32obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
32obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o 33obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
33obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o 34obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
@@ -42,6 +43,7 @@ obj-$(CONFIG_ARCH_U300) += clk-u300.o
42obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 43obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
43obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 44obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
44obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o 45obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
46obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
45obj-$(CONFIG_COMMON_CLK_AT91) += at91/ 47obj-$(CONFIG_COMMON_CLK_AT91) += at91/
46obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/ 48obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
47obj-$(CONFIG_ARCH_BERLIN) += berlin/ 49obj-$(CONFIG_ARCH_BERLIN) += berlin/
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
index a23ac0c724f0..0b7c3e8840ba 100644
--- a/drivers/clk/at91/clk-usb.c
+++ b/drivers/clk/at91/clk-usb.c
@@ -56,22 +56,55 @@ static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
56 return DIV_ROUND_CLOSEST(parent_rate, (usbdiv + 1)); 56 return DIV_ROUND_CLOSEST(parent_rate, (usbdiv + 1));
57} 57}
58 58
59static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, 59static long at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw,
60 unsigned long *parent_rate) 60 unsigned long rate,
61 unsigned long min_rate,
62 unsigned long max_rate,
63 unsigned long *best_parent_rate,
64 struct clk_hw **best_parent_hw)
61{ 65{
62 unsigned long div; 66 struct clk *parent = NULL;
67 long best_rate = -EINVAL;
68 unsigned long tmp_rate;
69 int best_diff = -1;
70 int tmp_diff;
71 int i;
63 72
64 if (!rate) 73 for (i = 0; i < __clk_get_num_parents(hw->clk); i++) {
65 return -EINVAL; 74 int div;
66 75
67 if (rate >= *parent_rate) 76 parent = clk_get_parent_by_index(hw->clk, i);
68 return *parent_rate; 77 if (!parent)
78 continue;
79
80 for (div = 1; div < SAM9X5_USB_MAX_DIV + 2; div++) {
81 unsigned long tmp_parent_rate;
82
83 tmp_parent_rate = rate * div;
84 tmp_parent_rate = __clk_round_rate(parent,
85 tmp_parent_rate);
86 tmp_rate = DIV_ROUND_CLOSEST(tmp_parent_rate, div);
87 if (tmp_rate < rate)
88 tmp_diff = rate - tmp_rate;
89 else
90 tmp_diff = tmp_rate - rate;
91
92 if (best_diff < 0 || best_diff > tmp_diff) {
93 best_rate = tmp_rate;
94 best_diff = tmp_diff;
95 *best_parent_rate = tmp_parent_rate;
96 *best_parent_hw = __clk_get_hw(parent);
97 }
98
99 if (!best_diff || tmp_rate < rate)
100 break;
101 }
69 102
70 div = DIV_ROUND_CLOSEST(*parent_rate, rate); 103 if (!best_diff)
71 if (div > SAM9X5_USB_MAX_DIV + 1) 104 break;
72 div = SAM9X5_USB_MAX_DIV + 1; 105 }
73 106
74 return DIV_ROUND_CLOSEST(*parent_rate, div); 107 return best_rate;
75} 108}
76 109
77static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index) 110static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
@@ -121,7 +154,7 @@ static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
121 154
122static const struct clk_ops at91sam9x5_usb_ops = { 155static const struct clk_ops at91sam9x5_usb_ops = {
123 .recalc_rate = at91sam9x5_clk_usb_recalc_rate, 156 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
124 .round_rate = at91sam9x5_clk_usb_round_rate, 157 .determine_rate = at91sam9x5_clk_usb_determine_rate,
125 .get_parent = at91sam9x5_clk_usb_get_parent, 158 .get_parent = at91sam9x5_clk_usb_get_parent,
126 .set_parent = at91sam9x5_clk_usb_set_parent, 159 .set_parent = at91sam9x5_clk_usb_set_parent,
127 .set_rate = at91sam9x5_clk_usb_set_rate, 160 .set_rate = at91sam9x5_clk_usb_set_rate,
@@ -159,7 +192,7 @@ static const struct clk_ops at91sam9n12_usb_ops = {
159 .disable = at91sam9n12_clk_usb_disable, 192 .disable = at91sam9n12_clk_usb_disable,
160 .is_enabled = at91sam9n12_clk_usb_is_enabled, 193 .is_enabled = at91sam9n12_clk_usb_is_enabled,
161 .recalc_rate = at91sam9x5_clk_usb_recalc_rate, 194 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
162 .round_rate = at91sam9x5_clk_usb_round_rate, 195 .determine_rate = at91sam9x5_clk_usb_determine_rate,
163 .set_rate = at91sam9x5_clk_usb_set_rate, 196 .set_rate = at91sam9x5_clk_usb_set_rate,
164}; 197};
165 198
@@ -179,7 +212,8 @@ at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name,
179 init.ops = &at91sam9x5_usb_ops; 212 init.ops = &at91sam9x5_usb_ops;
180 init.parent_names = parent_names; 213 init.parent_names = parent_names;
181 init.num_parents = num_parents; 214 init.num_parents = num_parents;
182 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 215 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
216 CLK_SET_RATE_PARENT;
183 217
184 usb->hw.init = &init; 218 usb->hw.init = &init;
185 usb->pmc = pmc; 219 usb->pmc = pmc;
@@ -207,7 +241,7 @@ at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name,
207 init.ops = &at91sam9n12_usb_ops; 241 init.ops = &at91sam9n12_usb_ops;
208 init.parent_names = &parent_name; 242 init.parent_names = &parent_name;
209 init.num_parents = 1; 243 init.num_parents = 1;
210 init.flags = CLK_SET_RATE_GATE; 244 init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;
211 245
212 usb->hw.init = &init; 246 usb->hw.init = &init;
213 usb->pmc = pmc; 247 usb->pmc = pmc;
diff --git a/drivers/clk/clk-cdce706.c b/drivers/clk/clk-cdce706.c
index c386ad25beb4..b8e4f8a822e9 100644
--- a/drivers/clk/clk-cdce706.c
+++ b/drivers/clk/clk-cdce706.c
@@ -58,7 +58,7 @@
58#define CDCE706_CLKOUT_DIVIDER_MASK 0x7 58#define CDCE706_CLKOUT_DIVIDER_MASK 0x7
59#define CDCE706_CLKOUT_ENABLE_MASK 0x8 59#define CDCE706_CLKOUT_ENABLE_MASK 0x8
60 60
61static struct regmap_config cdce706_regmap_config = { 61static const struct regmap_config cdce706_regmap_config = {
62 .reg_bits = 8, 62 .reg_bits = 8,
63 .val_bits = 8, 63 .val_bits = 8,
64 .val_format_endian = REGMAP_ENDIAN_NATIVE, 64 .val_format_endian = REGMAP_ENDIAN_NATIVE,
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index aad4796aa3ed..48a65b2b4027 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -13,7 +13,6 @@
13#include <linux/device.h> 13#include <linux/device.h>
14#include <linux/of.h> 14#include <linux/of.h>
15#include <linux/printk.h> 15#include <linux/printk.h>
16#include "clk.h"
17 16
18static int __set_clk_parents(struct device_node *node, bool clk_supplier) 17static int __set_clk_parents(struct device_node *node, bool clk_supplier)
19{ 18{
@@ -39,7 +38,7 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
39 } 38 }
40 if (clkspec.np == node && !clk_supplier) 39 if (clkspec.np == node && !clk_supplier)
41 return 0; 40 return 0;
42 pclk = of_clk_get_by_clkspec(&clkspec); 41 pclk = of_clk_get_from_provider(&clkspec);
43 if (IS_ERR(pclk)) { 42 if (IS_ERR(pclk)) {
44 pr_warn("clk: couldn't get parent clock %d for %s\n", 43 pr_warn("clk: couldn't get parent clock %d for %s\n",
45 index, node->full_name); 44 index, node->full_name);
@@ -54,7 +53,7 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
54 rc = 0; 53 rc = 0;
55 goto err; 54 goto err;
56 } 55 }
57 clk = of_clk_get_by_clkspec(&clkspec); 56 clk = of_clk_get_from_provider(&clkspec);
58 if (IS_ERR(clk)) { 57 if (IS_ERR(clk)) {
59 pr_warn("clk: couldn't get parent clock %d for %s\n", 58 pr_warn("clk: couldn't get parent clock %d for %s\n",
60 index, node->full_name); 59 index, node->full_name);
@@ -98,7 +97,7 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier)
98 if (clkspec.np == node && !clk_supplier) 97 if (clkspec.np == node && !clk_supplier)
99 return 0; 98 return 0;
100 99
101 clk = of_clk_get_by_clkspec(&clkspec); 100 clk = of_clk_get_from_provider(&clkspec);
102 if (IS_ERR(clk)) { 101 if (IS_ERR(clk)) {
103 pr_warn("clk: couldn't get clock %d for %s\n", 102 pr_warn("clk: couldn't get clock %d for %s\n",
104 index, node->full_name); 103 index, node->full_name);
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index 82a59d0086cc..6aa72d9d79ba 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -36,6 +36,9 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
36 m = (val & fd->mmask) >> fd->mshift; 36 m = (val & fd->mmask) >> fd->mshift;
37 n = (val & fd->nmask) >> fd->nshift; 37 n = (val & fd->nmask) >> fd->nshift;
38 38
39 if (!n || !m)
40 return parent_rate;
41
39 ret = (u64)parent_rate * m; 42 ret = (u64)parent_rate * m;
40 do_div(ret, n); 43 do_div(ret, n);
41 44
diff --git a/drivers/clk/clk-gpio-gate.c b/drivers/clk/clk-gpio-gate.c
index 08e43224fd52..a71cabedda93 100644
--- a/drivers/clk/clk-gpio-gate.c
+++ b/drivers/clk/clk-gpio-gate.c
@@ -65,10 +65,12 @@ EXPORT_SYMBOL_GPL(clk_gpio_gate_ops);
65 * @dev: device that is registering this clock 65 * @dev: device that is registering this clock
66 * @name: name of this clock 66 * @name: name of this clock
67 * @parent_name: name of this clock's parent 67 * @parent_name: name of this clock's parent
68 * @gpiod: gpio descriptor to gate this clock 68 * @gpio: gpio number to gate this clock
69 * @active_low: true if gpio should be set to 0 to enable clock
70 * @flags: clock flags
69 */ 71 */
70struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 72struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
71 const char *parent_name, struct gpio_desc *gpiod, 73 const char *parent_name, unsigned gpio, bool active_low,
72 unsigned long flags) 74 unsigned long flags)
73{ 75{
74 struct clk_gpio *clk_gpio = NULL; 76 struct clk_gpio *clk_gpio = NULL;
@@ -77,20 +79,19 @@ struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
77 unsigned long gpio_flags; 79 unsigned long gpio_flags;
78 int err; 80 int err;
79 81
80 if (gpiod_is_active_low(gpiod)) 82 if (active_low)
81 gpio_flags = GPIOF_OUT_INIT_HIGH; 83 gpio_flags = GPIOF_ACTIVE_LOW | GPIOF_OUT_INIT_HIGH;
82 else 84 else
83 gpio_flags = GPIOF_OUT_INIT_LOW; 85 gpio_flags = GPIOF_OUT_INIT_LOW;
84 86
85 if (dev) 87 if (dev)
86 err = devm_gpio_request_one(dev, desc_to_gpio(gpiod), 88 err = devm_gpio_request_one(dev, gpio, gpio_flags, name);
87 gpio_flags, name);
88 else 89 else
89 err = gpio_request_one(desc_to_gpio(gpiod), gpio_flags, name); 90 err = gpio_request_one(gpio, gpio_flags, name);
90 91
91 if (err) { 92 if (err) {
92 pr_err("%s: %s: Error requesting clock control gpio %u\n", 93 pr_err("%s: %s: Error requesting clock control gpio %u\n",
93 __func__, name, desc_to_gpio(gpiod)); 94 __func__, name, gpio);
94 return ERR_PTR(err); 95 return ERR_PTR(err);
95 } 96 }
96 97
@@ -111,7 +112,7 @@ struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
111 init.parent_names = (parent_name ? &parent_name : NULL); 112 init.parent_names = (parent_name ? &parent_name : NULL);
112 init.num_parents = (parent_name ? 1 : 0); 113 init.num_parents = (parent_name ? 1 : 0);
113 114
114 clk_gpio->gpiod = gpiod; 115 clk_gpio->gpiod = gpio_to_desc(gpio);
115 clk_gpio->hw.init = &init; 116 clk_gpio->hw.init = &init;
116 117
117 clk = clk_register(dev, &clk_gpio->hw); 118 clk = clk_register(dev, &clk_gpio->hw);
@@ -123,7 +124,8 @@ struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
123 kfree(clk_gpio); 124 kfree(clk_gpio);
124 125
125clk_register_gpio_gate_err: 126clk_register_gpio_gate_err:
126 gpiod_put(gpiod); 127 if (!dev)
128 gpio_free(gpio);
127 129
128 return clk; 130 return clk;
129} 131}
@@ -149,8 +151,8 @@ static struct clk *of_clk_gpio_gate_delayed_register_get(
149 struct clk *clk; 151 struct clk *clk;
150 const char *clk_name = data->node->name; 152 const char *clk_name = data->node->name;
151 const char *parent_name; 153 const char *parent_name;
152 struct gpio_desc *gpiod;
153 int gpio; 154 int gpio;
155 enum of_gpio_flags of_flags;
154 156
155 mutex_lock(&data->lock); 157 mutex_lock(&data->lock);
156 158
@@ -159,7 +161,8 @@ static struct clk *of_clk_gpio_gate_delayed_register_get(
159 return data->clk; 161 return data->clk;
160 } 162 }
161 163
162 gpio = of_get_named_gpio_flags(data->node, "enable-gpios", 0, NULL); 164 gpio = of_get_named_gpio_flags(data->node, "enable-gpios", 0,
165 &of_flags);
163 if (gpio < 0) { 166 if (gpio < 0) {
164 mutex_unlock(&data->lock); 167 mutex_unlock(&data->lock);
165 if (gpio != -EPROBE_DEFER) 168 if (gpio != -EPROBE_DEFER)
@@ -167,11 +170,11 @@ static struct clk *of_clk_gpio_gate_delayed_register_get(
167 __func__, clk_name); 170 __func__, clk_name);
168 return ERR_PTR(gpio); 171 return ERR_PTR(gpio);
169 } 172 }
170 gpiod = gpio_to_desc(gpio);
171 173
172 parent_name = of_clk_get_parent_name(data->node, 0); 174 parent_name = of_clk_get_parent_name(data->node, 0);
173 175
174 clk = clk_register_gpio_gate(NULL, clk_name, parent_name, gpiod, 0); 176 clk = clk_register_gpio_gate(NULL, clk_name, parent_name, gpio,
177 of_flags & OF_GPIO_ACTIVE_LOW, 0);
175 if (IS_ERR(clk)) { 178 if (IS_ERR(clk)) {
176 mutex_unlock(&data->lock); 179 mutex_unlock(&data->lock);
177 return clk; 180 return clk;
diff --git a/drivers/clk/clk-mb86s7x.c b/drivers/clk/clk-mb86s7x.c
new file mode 100644
index 000000000000..f39c25a22f43
--- /dev/null
+++ b/drivers/clk/clk-mb86s7x.c
@@ -0,0 +1,386 @@
1/*
2 * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
3 * Copyright (C) 2015 Linaro Ltd.
4 *
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clkdev.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/of.h>
19#include <linux/cpu.h>
20#include <linux/clk-provider.h>
21#include <linux/spinlock.h>
22#include <linux/module.h>
23#include <linux/topology.h>
24#include <linux/mailbox_client.h>
25#include <linux/platform_device.h>
26
27#include <soc/mb86s7x/scb_mhu.h>
28
29#define to_crg_clk(p) container_of(p, struct crg_clk, hw)
30#define to_clc_clk(p) container_of(p, struct cl_clk, hw)
31
32struct mb86s7x_peri_clk {
33 u32 payload_size;
34 u32 cntrlr;
35 u32 domain;
36 u32 port;
37 u32 en;
38 u64 frequency;
39} __packed __aligned(4);
40
41struct hack_rate {
42 unsigned clk_id;
43 unsigned long rate;
44 int gated;
45};
46
47struct crg_clk {
48 struct clk_hw hw;
49 u8 cntrlr, domain, port;
50};
51
52static int crg_gate_control(struct clk_hw *hw, int en)
53{
54 struct crg_clk *crgclk = to_crg_clk(hw);
55 struct mb86s7x_peri_clk cmd;
56 int ret;
57
58 cmd.payload_size = sizeof(cmd);
59 cmd.cntrlr = crgclk->cntrlr;
60 cmd.domain = crgclk->domain;
61 cmd.port = crgclk->port;
62 cmd.en = en;
63
64 /* Port is UngatedCLK */
65 if (cmd.port == 8)
66 return en ? 0 : -EINVAL;
67
68 pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u En-%u}\n",
69 __func__, __LINE__, cmd.cntrlr,
70 cmd.domain, cmd.port, cmd.en);
71
72 ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
73 &cmd, sizeof(cmd));
74 if (ret < 0) {
75 pr_err("%s:%d failed!\n", __func__, __LINE__);
76 return ret;
77 }
78
79 pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u En-%u}\n",
80 __func__, __LINE__, cmd.cntrlr,
81 cmd.domain, cmd.port, cmd.en);
82
83 /* If the request was rejected */
84 if (cmd.en != en)
85 ret = -EINVAL;
86 else
87 ret = 0;
88
89 return ret;
90}
91
92static int crg_port_prepare(struct clk_hw *hw)
93{
94 return crg_gate_control(hw, 1);
95}
96
97static void crg_port_unprepare(struct clk_hw *hw)
98{
99 crg_gate_control(hw, 0);
100}
101
102static int
103crg_rate_control(struct clk_hw *hw, int set, unsigned long *rate)
104{
105 struct crg_clk *crgclk = to_crg_clk(hw);
106 struct mb86s7x_peri_clk cmd;
107 int code, ret;
108
109 cmd.payload_size = sizeof(cmd);
110 cmd.cntrlr = crgclk->cntrlr;
111 cmd.domain = crgclk->domain;
112 cmd.port = crgclk->port;
113 cmd.frequency = *rate;
114
115 if (set) {
116 code = CMD_PERI_CLOCK_RATE_SET_REQ;
117 pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
118 __func__, __LINE__, cmd.cntrlr,
119 cmd.domain, cmd.port, cmd.frequency);
120 } else {
121 code = CMD_PERI_CLOCK_RATE_GET_REQ;
122 pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-GET}\n",
123 __func__, __LINE__, cmd.cntrlr,
124 cmd.domain, cmd.port);
125 }
126
127 ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
128 if (ret < 0) {
129 pr_err("%s:%d failed!\n", __func__, __LINE__);
130 return ret;
131 }
132
133 if (set)
134 pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
135 __func__, __LINE__, cmd.cntrlr,
136 cmd.domain, cmd.port, cmd.frequency);
137 else
138 pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-GOT %lluHz}\n",
139 __func__, __LINE__, cmd.cntrlr,
140 cmd.domain, cmd.port, cmd.frequency);
141
142 *rate = cmd.frequency;
143 return 0;
144}
145
146static unsigned long
147crg_port_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
148{
149 unsigned long rate;
150
151 crg_rate_control(hw, 0, &rate);
152
153 return rate;
154}
155
156static long
157crg_port_round_rate(struct clk_hw *hw,
158 unsigned long rate, unsigned long *pr)
159{
160 return rate;
161}
162
163static int
164crg_port_set_rate(struct clk_hw *hw,
165 unsigned long rate, unsigned long parent_rate)
166{
167 return crg_rate_control(hw, 1, &rate);
168}
169
170const struct clk_ops crg_port_ops = {
171 .prepare = crg_port_prepare,
172 .unprepare = crg_port_unprepare,
173 .recalc_rate = crg_port_recalc_rate,
174 .round_rate = crg_port_round_rate,
175 .set_rate = crg_port_set_rate,
176};
177
178struct mb86s70_crg11 {
179 struct mutex lock; /* protects CLK populating and searching */
180};
181
182static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
183{
184 struct mb86s70_crg11 *crg11 = data;
185 struct clk_init_data init;
186 u32 cntrlr, domain, port;
187 struct crg_clk *crgclk;
188 struct clk *clk;
189 char clkp[20];
190
191 if (clkspec->args_count != 3)
192 return ERR_PTR(-EINVAL);
193
194 cntrlr = clkspec->args[0];
195 domain = clkspec->args[1];
196 port = clkspec->args[2];
197
198 if (port > 7)
199 snprintf(clkp, 20, "UngatedCLK%d_%X", cntrlr, domain);
200 else
201 snprintf(clkp, 20, "CLK%d_%X_%d", cntrlr, domain, port);
202
203 mutex_lock(&crg11->lock);
204
205 clk = __clk_lookup(clkp);
206 if (clk) {
207 mutex_unlock(&crg11->lock);
208 return clk;
209 }
210
211 crgclk = kzalloc(sizeof(*crgclk), GFP_KERNEL);
212 if (!crgclk) {
213 mutex_unlock(&crg11->lock);
214 return ERR_PTR(-ENOMEM);
215 }
216
217 init.name = clkp;
218 init.num_parents = 0;
219 init.ops = &crg_port_ops;
220 init.flags = CLK_IS_ROOT;
221 crgclk->hw.init = &init;
222 crgclk->cntrlr = cntrlr;
223 crgclk->domain = domain;
224 crgclk->port = port;
225 clk = clk_register(NULL, &crgclk->hw);
226 if (IS_ERR(clk))
227 pr_err("%s:%d Error!\n", __func__, __LINE__);
228 else
229 pr_debug("Registered %s\n", clkp);
230
231 clk_register_clkdev(clk, clkp, NULL);
232 mutex_unlock(&crg11->lock);
233 return clk;
234}
235
236static void __init crg_port_init(struct device_node *node)
237{
238 struct mb86s70_crg11 *crg11;
239
240 crg11 = kzalloc(sizeof(*crg11), GFP_KERNEL);
241 if (!crg11)
242 return;
243
244 mutex_init(&crg11->lock);
245
246 of_clk_add_provider(node, crg11_get, crg11);
247}
248CLK_OF_DECLARE(crg11_gate, "fujitsu,mb86s70-crg11", crg_port_init);
249
250struct cl_clk {
251 struct clk_hw hw;
252 int cluster;
253};
254
255struct mb86s7x_cpu_freq {
256 u32 payload_size;
257 u32 cluster_class;
258 u32 cluster_id;
259 u32 cpu_id;
260 u64 frequency;
261};
262
263static void mhu_cluster_rate(struct clk_hw *hw, unsigned long *rate, int get)
264{
265 struct cl_clk *clc = to_clc_clk(hw);
266 struct mb86s7x_cpu_freq cmd;
267 int code, ret;
268
269 cmd.payload_size = sizeof(cmd);
270 cmd.cluster_class = 0;
271 cmd.cluster_id = clc->cluster;
272 cmd.cpu_id = 0;
273 cmd.frequency = *rate;
274
275 if (get)
276 code = CMD_CPU_CLOCK_RATE_GET_REQ;
277 else
278 code = CMD_CPU_CLOCK_RATE_SET_REQ;
279
280 pr_debug("%s:%d CMD Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
281 __func__, __LINE__, cmd.cluster_class,
282 cmd.cluster_id, cmd.cpu_id, cmd.frequency);
283
284 ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
285 if (ret < 0) {
286 pr_err("%s:%d failed!\n", __func__, __LINE__);
287 return;
288 }
289
290 pr_debug("%s:%d REP Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
291 __func__, __LINE__, cmd.cluster_class,
292 cmd.cluster_id, cmd.cpu_id, cmd.frequency);
293
294 *rate = cmd.frequency;
295}
296
297static unsigned long
298clc_recalc_rate(struct clk_hw *hw, unsigned long unused)
299{
300 unsigned long rate;
301
302 mhu_cluster_rate(hw, &rate, 1);
303 return rate;
304}
305
306static long
307clc_round_rate(struct clk_hw *hw, unsigned long rate,
308 unsigned long *unused)
309{
310 return rate;
311}
312
313static int
314clc_set_rate(struct clk_hw *hw, unsigned long rate,
315 unsigned long unused)
316{
317 unsigned long res = rate;
318
319 mhu_cluster_rate(hw, &res, 0);
320
321 return (res == rate) ? 0 : -EINVAL;
322}
323
324static struct clk_ops clk_clc_ops = {
325 .recalc_rate = clc_recalc_rate,
326 .round_rate = clc_round_rate,
327 .set_rate = clc_set_rate,
328};
329
330struct clk *mb86s7x_clclk_register(struct device *cpu_dev)
331{
332 struct clk_init_data init;
333 struct cl_clk *clc;
334
335 clc = kzalloc(sizeof(*clc), GFP_KERNEL);
336 if (!clc)
337 return ERR_PTR(-ENOMEM);
338
339 clc->hw.init = &init;
340 clc->cluster = topology_physical_package_id(cpu_dev->id);
341
342 init.name = dev_name(cpu_dev);
343 init.ops = &clk_clc_ops;
344 init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
345 init.num_parents = 0;
346
347 return devm_clk_register(cpu_dev, &clc->hw);
348}
349
350static int mb86s7x_clclk_of_init(void)
351{
352 int cpu, ret = -ENODEV;
353 struct device_node *np;
354 struct clk *clk;
355
356 np = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
357 if (!np || !of_device_is_available(np))
358 goto exit;
359
360 for_each_possible_cpu(cpu) {
361 struct device *cpu_dev = get_cpu_device(cpu);
362
363 if (!cpu_dev) {
364 pr_err("failed to get cpu%d device\n", cpu);
365 continue;
366 }
367
368 clk = mb86s7x_clclk_register(cpu_dev);
369 if (IS_ERR(clk)) {
370 pr_err("failed to register cpu%d clock\n", cpu);
371 continue;
372 }
373 if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
374 pr_err("failed to register cpu%d clock lookup\n", cpu);
375 continue;
376 }
377 pr_debug("registered clk for %s\n", dev_name(cpu_dev));
378 }
379 ret = 0;
380
381 platform_device_register_simple("arm-bL-cpufreq-dt", -1, NULL, 0);
382exit:
383 of_node_put(np);
384 return ret;
385}
386module_init(mb86s7x_clclk_of_init);
diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c
index 8d459923a15f..45a535ab48aa 100644
--- a/drivers/clk/clk-palmas.c
+++ b/drivers/clk/clk-palmas.c
@@ -161,7 +161,7 @@ static struct palmas_clks_of_match_data palmas_of_clk32kgaudio = {
161 }, 161 },
162}; 162};
163 163
164static struct of_device_id palmas_clks_of_match[] = { 164static const struct of_device_id palmas_clks_of_match[] = {
165 { 165 {
166 .compatible = "ti,palmas-clk32kg", 166 .compatible = "ti,palmas-clk32kg",
167 .data = &palmas_of_clk32kg, 167 .data = &palmas_of_clk32kg,
diff --git a/drivers/clk/clk-pwm.c b/drivers/clk/clk-pwm.c
new file mode 100644
index 000000000000..328fcfcefd8c
--- /dev/null
+++ b/drivers/clk/clk-pwm.c
@@ -0,0 +1,136 @@
1/*
2 * Copyright (C) 2014 Philipp Zabel, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * PWM (mis)used as clock output
9 */
10#include <linux/clk-provider.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pwm.h>
16
17struct clk_pwm {
18 struct clk_hw hw;
19 struct pwm_device *pwm;
20 u32 fixed_rate;
21};
22
23static inline struct clk_pwm *to_clk_pwm(struct clk_hw *hw)
24{
25 return container_of(hw, struct clk_pwm, hw);
26}
27
28static int clk_pwm_prepare(struct clk_hw *hw)
29{
30 struct clk_pwm *clk_pwm = to_clk_pwm(hw);
31
32 return pwm_enable(clk_pwm->pwm);
33}
34
35static void clk_pwm_unprepare(struct clk_hw *hw)
36{
37 struct clk_pwm *clk_pwm = to_clk_pwm(hw);
38
39 pwm_disable(clk_pwm->pwm);
40}
41
42static unsigned long clk_pwm_recalc_rate(struct clk_hw *hw,
43 unsigned long parent_rate)
44{
45 struct clk_pwm *clk_pwm = to_clk_pwm(hw);
46
47 return clk_pwm->fixed_rate;
48}
49
50static const struct clk_ops clk_pwm_ops = {
51 .prepare = clk_pwm_prepare,
52 .unprepare = clk_pwm_unprepare,
53 .recalc_rate = clk_pwm_recalc_rate,
54};
55
56static int clk_pwm_probe(struct platform_device *pdev)
57{
58 struct device_node *node = pdev->dev.of_node;
59 struct clk_init_data init;
60 struct clk_pwm *clk_pwm;
61 struct pwm_device *pwm;
62 const char *clk_name;
63 struct clk *clk;
64 int ret;
65
66 clk_pwm = devm_kzalloc(&pdev->dev, sizeof(*clk_pwm), GFP_KERNEL);
67 if (!clk_pwm)
68 return -ENOMEM;
69
70 pwm = devm_pwm_get(&pdev->dev, NULL);
71 if (IS_ERR(pwm))
72 return PTR_ERR(pwm);
73
74 if (!pwm->period) {
75 dev_err(&pdev->dev, "invalid PWM period\n");
76 return -EINVAL;
77 }
78
79 if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
80 clk_pwm->fixed_rate = NSEC_PER_SEC / pwm->period;
81
82 if (pwm->period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
83 pwm->period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {
84 dev_err(&pdev->dev,
85 "clock-frequency does not match PWM period\n");
86 return -EINVAL;
87 }
88
89 ret = pwm_config(pwm, (pwm->period + 1) >> 1, pwm->period);
90 if (ret < 0)
91 return ret;
92
93 clk_name = node->name;
94 of_property_read_string(node, "clock-output-names", &clk_name);
95
96 init.name = clk_name;
97 init.ops = &clk_pwm_ops;
98 init.flags = CLK_IS_BASIC | CLK_IS_ROOT;
99 init.num_parents = 0;
100
101 clk_pwm->pwm = pwm;
102 clk_pwm->hw.init = &init;
103 clk = devm_clk_register(&pdev->dev, &clk_pwm->hw);
104 if (IS_ERR(clk))
105 return PTR_ERR(clk);
106
107 return of_clk_add_provider(node, of_clk_src_simple_get, clk);
108}
109
110static int clk_pwm_remove(struct platform_device *pdev)
111{
112 of_clk_del_provider(pdev->dev.of_node);
113
114 return 0;
115}
116
117static const struct of_device_id clk_pwm_dt_ids[] = {
118 { .compatible = "pwm-clock" },
119 { }
120};
121MODULE_DEVICE_TABLE(of, clk_pwm_dt_ids);
122
123static struct platform_driver clk_pwm_driver = {
124 .probe = clk_pwm_probe,
125 .remove = clk_pwm_remove,
126 .driver = {
127 .name = "pwm-clock",
128 .of_match_table = of_match_ptr(clk_pwm_dt_ids),
129 },
130};
131
132module_platform_driver(clk_pwm_driver);
133
134MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
135MODULE_DESCRIPTION("PWM clock driver");
136MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 3b2a66f78755..44ea107cfc67 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -68,16 +68,16 @@ struct si5351_driver_data {
68 struct si5351_hw_data *clkout; 68 struct si5351_hw_data *clkout;
69}; 69};
70 70
71static const char const *si5351_input_names[] = { 71static const char * const si5351_input_names[] = {
72 "xtal", "clkin" 72 "xtal", "clkin"
73}; 73};
74static const char const *si5351_pll_names[] = { 74static const char * const si5351_pll_names[] = {
75 "plla", "pllb", "vxco" 75 "plla", "pllb", "vxco"
76}; 76};
77static const char const *si5351_msynth_names[] = { 77static const char * const si5351_msynth_names[] = {
78 "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7" 78 "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
79}; 79};
80static const char const *si5351_clkout_names[] = { 80static const char * const si5351_clkout_names[] = {
81 "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7" 81 "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
82}; 82};
83 83
@@ -207,7 +207,7 @@ static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg)
207 return true; 207 return true;
208} 208}
209 209
210static struct regmap_config si5351_regmap_config = { 210static const struct regmap_config si5351_regmap_config = {
211 .reg_bits = 8, 211 .reg_bits = 8,
212 .val_bits = 8, 212 .val_bits = 8,
213 .cache_type = REGCACHE_RBTREE, 213 .cache_type = REGCACHE_RBTREE,
diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c
index fc167b3f8919..20a5aec98b1a 100644
--- a/drivers/clk/clk-si570.c
+++ b/drivers/clk/clk-si570.c
@@ -393,7 +393,7 @@ static bool si570_regmap_is_writeable(struct device *dev, unsigned int reg)
393 } 393 }
394} 394}
395 395
396static struct regmap_config si570_regmap_config = { 396static const struct regmap_config si570_regmap_config = {
397 .reg_bits = 8, 397 .reg_bits = 8,
398 .val_bits = 8, 398 .val_bits = 8,
399 .cache_type = REGCACHE_RBTREE, 399 .cache_type = REGCACHE_RBTREE,
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 237f23f68bfc..459ce9da13e0 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -77,13 +77,16 @@ struct clk_core {
77 struct kref ref; 77 struct kref ref;
78}; 78};
79 79
80#define CREATE_TRACE_POINTS
81#include <trace/events/clk.h>
82
80struct clk { 83struct clk {
81 struct clk_core *core; 84 struct clk_core *core;
82 const char *dev_id; 85 const char *dev_id;
83 const char *con_id; 86 const char *con_id;
84 unsigned long min_rate; 87 unsigned long min_rate;
85 unsigned long max_rate; 88 unsigned long max_rate;
86 struct hlist_node child_node; 89 struct hlist_node clks_node;
87}; 90};
88 91
89/*** locking ***/ 92/*** locking ***/
@@ -480,6 +483,8 @@ static void clk_unprepare_unused_subtree(struct clk_core *clk)
480{ 483{
481 struct clk_core *child; 484 struct clk_core *child;
482 485
486 lockdep_assert_held(&prepare_lock);
487
483 hlist_for_each_entry(child, &clk->children, child_node) 488 hlist_for_each_entry(child, &clk->children, child_node)
484 clk_unprepare_unused_subtree(child); 489 clk_unprepare_unused_subtree(child);
485 490
@@ -490,10 +495,12 @@ static void clk_unprepare_unused_subtree(struct clk_core *clk)
490 return; 495 return;
491 496
492 if (clk_core_is_prepared(clk)) { 497 if (clk_core_is_prepared(clk)) {
498 trace_clk_unprepare(clk);
493 if (clk->ops->unprepare_unused) 499 if (clk->ops->unprepare_unused)
494 clk->ops->unprepare_unused(clk->hw); 500 clk->ops->unprepare_unused(clk->hw);
495 else if (clk->ops->unprepare) 501 else if (clk->ops->unprepare)
496 clk->ops->unprepare(clk->hw); 502 clk->ops->unprepare(clk->hw);
503 trace_clk_unprepare_complete(clk);
497 } 504 }
498} 505}
499 506
@@ -503,6 +510,8 @@ static void clk_disable_unused_subtree(struct clk_core *clk)
503 struct clk_core *child; 510 struct clk_core *child;
504 unsigned long flags; 511 unsigned long flags;
505 512
513 lockdep_assert_held(&prepare_lock);
514
506 hlist_for_each_entry(child, &clk->children, child_node) 515 hlist_for_each_entry(child, &clk->children, child_node)
507 clk_disable_unused_subtree(child); 516 clk_disable_unused_subtree(child);
508 517
@@ -520,10 +529,12 @@ static void clk_disable_unused_subtree(struct clk_core *clk)
520 * back to .disable 529 * back to .disable
521 */ 530 */
522 if (clk_core_is_enabled(clk)) { 531 if (clk_core_is_enabled(clk)) {
532 trace_clk_disable(clk);
523 if (clk->ops->disable_unused) 533 if (clk->ops->disable_unused)
524 clk->ops->disable_unused(clk->hw); 534 clk->ops->disable_unused(clk->hw);
525 else if (clk->ops->disable) 535 else if (clk->ops->disable)
526 clk->ops->disable(clk->hw); 536 clk->ops->disable(clk->hw);
537 trace_clk_disable_complete(clk);
527 } 538 }
528 539
529unlock_out: 540unlock_out:
@@ -851,10 +862,10 @@ static void clk_core_get_boundaries(struct clk_core *clk,
851 *min_rate = 0; 862 *min_rate = 0;
852 *max_rate = ULONG_MAX; 863 *max_rate = ULONG_MAX;
853 864
854 hlist_for_each_entry(clk_user, &clk->clks, child_node) 865 hlist_for_each_entry(clk_user, &clk->clks, clks_node)
855 *min_rate = max(*min_rate, clk_user->min_rate); 866 *min_rate = max(*min_rate, clk_user->min_rate);
856 867
857 hlist_for_each_entry(clk_user, &clk->clks, child_node) 868 hlist_for_each_entry(clk_user, &clk->clks, clks_node)
858 *max_rate = min(*max_rate, clk_user->max_rate); 869 *max_rate = min(*max_rate, clk_user->max_rate);
859} 870}
860 871
@@ -903,9 +914,12 @@ static void clk_core_unprepare(struct clk_core *clk)
903 914
904 WARN_ON(clk->enable_count > 0); 915 WARN_ON(clk->enable_count > 0);
905 916
917 trace_clk_unprepare(clk);
918
906 if (clk->ops->unprepare) 919 if (clk->ops->unprepare)
907 clk->ops->unprepare(clk->hw); 920 clk->ops->unprepare(clk->hw);
908 921
922 trace_clk_unprepare_complete(clk);
909 clk_core_unprepare(clk->parent); 923 clk_core_unprepare(clk->parent);
910} 924}
911 925
@@ -943,12 +957,16 @@ static int clk_core_prepare(struct clk_core *clk)
943 if (ret) 957 if (ret)
944 return ret; 958 return ret;
945 959
946 if (clk->ops->prepare) { 960 trace_clk_prepare(clk);
961
962 if (clk->ops->prepare)
947 ret = clk->ops->prepare(clk->hw); 963 ret = clk->ops->prepare(clk->hw);
948 if (ret) { 964
949 clk_core_unprepare(clk->parent); 965 trace_clk_prepare_complete(clk);
950 return ret; 966
951 } 967 if (ret) {
968 clk_core_unprepare(clk->parent);
969 return ret;
952 } 970 }
953 } 971 }
954 972
@@ -995,9 +1013,13 @@ static void clk_core_disable(struct clk_core *clk)
995 if (--clk->enable_count > 0) 1013 if (--clk->enable_count > 0)
996 return; 1014 return;
997 1015
1016 trace_clk_disable(clk);
1017
998 if (clk->ops->disable) 1018 if (clk->ops->disable)
999 clk->ops->disable(clk->hw); 1019 clk->ops->disable(clk->hw);
1000 1020
1021 trace_clk_disable_complete(clk);
1022
1001 clk_core_disable(clk->parent); 1023 clk_core_disable(clk->parent);
1002} 1024}
1003 1025
@@ -1050,12 +1072,16 @@ static int clk_core_enable(struct clk_core *clk)
1050 if (ret) 1072 if (ret)
1051 return ret; 1073 return ret;
1052 1074
1053 if (clk->ops->enable) { 1075 trace_clk_enable(clk);
1076
1077 if (clk->ops->enable)
1054 ret = clk->ops->enable(clk->hw); 1078 ret = clk->ops->enable(clk->hw);
1055 if (ret) { 1079
1056 clk_core_disable(clk->parent); 1080 trace_clk_enable_complete(clk);
1057 return ret; 1081
1058 } 1082 if (ret) {
1083 clk_core_disable(clk->parent);
1084 return ret;
1059 } 1085 }
1060 } 1086 }
1061 1087
@@ -1106,6 +1132,8 @@ static unsigned long clk_core_round_rate_nolock(struct clk_core *clk,
1106 struct clk_core *parent; 1132 struct clk_core *parent;
1107 struct clk_hw *parent_hw; 1133 struct clk_hw *parent_hw;
1108 1134
1135 lockdep_assert_held(&prepare_lock);
1136
1109 if (!clk) 1137 if (!clk)
1110 return 0; 1138 return 0;
1111 1139
@@ -1245,6 +1273,8 @@ static void __clk_recalc_accuracies(struct clk_core *clk)
1245 unsigned long parent_accuracy = 0; 1273 unsigned long parent_accuracy = 0;
1246 struct clk_core *child; 1274 struct clk_core *child;
1247 1275
1276 lockdep_assert_held(&prepare_lock);
1277
1248 if (clk->parent) 1278 if (clk->parent)
1249 parent_accuracy = clk->parent->accuracy; 1279 parent_accuracy = clk->parent->accuracy;
1250 1280
@@ -1318,6 +1348,8 @@ static void __clk_recalc_rates(struct clk_core *clk, unsigned long msg)
1318 unsigned long parent_rate = 0; 1348 unsigned long parent_rate = 0;
1319 struct clk_core *child; 1349 struct clk_core *child;
1320 1350
1351 lockdep_assert_held(&prepare_lock);
1352
1321 old_rate = clk->rate; 1353 old_rate = clk->rate;
1322 1354
1323 if (clk->parent) 1355 if (clk->parent)
@@ -1479,10 +1511,14 @@ static int __clk_set_parent(struct clk_core *clk, struct clk_core *parent,
1479 1511
1480 old_parent = __clk_set_parent_before(clk, parent); 1512 old_parent = __clk_set_parent_before(clk, parent);
1481 1513
1514 trace_clk_set_parent(clk, parent);
1515
1482 /* change clock input source */ 1516 /* change clock input source */
1483 if (parent && clk->ops->set_parent) 1517 if (parent && clk->ops->set_parent)
1484 ret = clk->ops->set_parent(clk->hw, p_index); 1518 ret = clk->ops->set_parent(clk->hw, p_index);
1485 1519
1520 trace_clk_set_parent_complete(clk, parent);
1521
1486 if (ret) { 1522 if (ret) {
1487 flags = clk_enable_lock(); 1523 flags = clk_enable_lock();
1488 clk_reparent(clk, old_parent); 1524 clk_reparent(clk, old_parent);
@@ -1524,6 +1560,8 @@ static int __clk_speculate_rates(struct clk_core *clk,
1524 unsigned long new_rate; 1560 unsigned long new_rate;
1525 int ret = NOTIFY_DONE; 1561 int ret = NOTIFY_DONE;
1526 1562
1563 lockdep_assert_held(&prepare_lock);
1564
1527 new_rate = clk_recalc(clk, parent_rate); 1565 new_rate = clk_recalc(clk, parent_rate);
1528 1566
1529 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */ 1567 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
@@ -1580,6 +1618,7 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *clk,
1580 unsigned long min_rate; 1618 unsigned long min_rate;
1581 unsigned long max_rate; 1619 unsigned long max_rate;
1582 int p_index = 0; 1620 int p_index = 0;
1621 long ret;
1583 1622
1584 /* sanity */ 1623 /* sanity */
1585 if (IS_ERR_OR_NULL(clk)) 1624 if (IS_ERR_OR_NULL(clk))
@@ -1595,15 +1634,23 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *clk,
1595 /* find the closest rate and parent clk/rate */ 1634 /* find the closest rate and parent clk/rate */
1596 if (clk->ops->determine_rate) { 1635 if (clk->ops->determine_rate) {
1597 parent_hw = parent ? parent->hw : NULL; 1636 parent_hw = parent ? parent->hw : NULL;
1598 new_rate = clk->ops->determine_rate(clk->hw, rate, 1637 ret = clk->ops->determine_rate(clk->hw, rate,
1599 min_rate, 1638 min_rate,
1600 max_rate, 1639 max_rate,
1601 &best_parent_rate, 1640 &best_parent_rate,
1602 &parent_hw); 1641 &parent_hw);
1642 if (ret < 0)
1643 return NULL;
1644
1645 new_rate = ret;
1603 parent = parent_hw ? parent_hw->core : NULL; 1646 parent = parent_hw ? parent_hw->core : NULL;
1604 } else if (clk->ops->round_rate) { 1647 } else if (clk->ops->round_rate) {
1605 new_rate = clk->ops->round_rate(clk->hw, rate, 1648 ret = clk->ops->round_rate(clk->hw, rate,
1606 &best_parent_rate); 1649 &best_parent_rate);
1650 if (ret < 0)
1651 return NULL;
1652
1653 new_rate = ret;
1607 if (new_rate < min_rate || new_rate > max_rate) 1654 if (new_rate < min_rate || new_rate > max_rate)
1608 return NULL; 1655 return NULL;
1609 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) { 1656 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
@@ -1706,6 +1753,7 @@ static void clk_change_rate(struct clk_core *clk)
1706 1753
1707 if (clk->new_parent && clk->new_parent != clk->parent) { 1754 if (clk->new_parent && clk->new_parent != clk->parent) {
1708 old_parent = __clk_set_parent_before(clk, clk->new_parent); 1755 old_parent = __clk_set_parent_before(clk, clk->new_parent);
1756 trace_clk_set_parent(clk, clk->new_parent);
1709 1757
1710 if (clk->ops->set_rate_and_parent) { 1758 if (clk->ops->set_rate_and_parent) {
1711 skip_set_rate = true; 1759 skip_set_rate = true;
@@ -1716,12 +1764,17 @@ static void clk_change_rate(struct clk_core *clk)
1716 clk->ops->set_parent(clk->hw, clk->new_parent_index); 1764 clk->ops->set_parent(clk->hw, clk->new_parent_index);
1717 } 1765 }
1718 1766
1767 trace_clk_set_parent_complete(clk, clk->new_parent);
1719 __clk_set_parent_after(clk, clk->new_parent, old_parent); 1768 __clk_set_parent_after(clk, clk->new_parent, old_parent);
1720 } 1769 }
1721 1770
1771 trace_clk_set_rate(clk, clk->new_rate);
1772
1722 if (!skip_set_rate && clk->ops->set_rate) 1773 if (!skip_set_rate && clk->ops->set_rate)
1723 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate); 1774 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate);
1724 1775
1776 trace_clk_set_rate_complete(clk, clk->new_rate);
1777
1725 clk->rate = clk_recalc(clk, best_parent_rate); 1778 clk->rate = clk_recalc(clk, best_parent_rate);
1726 1779
1727 if (clk->notifier_count && old_rate != clk->rate) 1780 if (clk->notifier_count && old_rate != clk->rate)
@@ -2010,16 +2063,18 @@ static int clk_core_set_parent(struct clk_core *clk, struct clk_core *parent)
2010 if (!clk) 2063 if (!clk)
2011 return 0; 2064 return 0;
2012 2065
2013 /* verify ops for for multi-parent clks */
2014 if ((clk->num_parents > 1) && (!clk->ops->set_parent))
2015 return -ENOSYS;
2016
2017 /* prevent racing with updates to the clock topology */ 2066 /* prevent racing with updates to the clock topology */
2018 clk_prepare_lock(); 2067 clk_prepare_lock();
2019 2068
2020 if (clk->parent == parent) 2069 if (clk->parent == parent)
2021 goto out; 2070 goto out;
2022 2071
2072 /* verify ops for for multi-parent clks */
2073 if ((clk->num_parents > 1) && (!clk->ops->set_parent)) {
2074 ret = -ENOSYS;
2075 goto out;
2076 }
2077
2023 /* check that we are allowed to re-parent if the clock is in use */ 2078 /* check that we are allowed to re-parent if the clock is in use */
2024 if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) { 2079 if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
2025 ret = -EBUSY; 2080 ret = -EBUSY;
@@ -2110,10 +2165,10 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
2110 */ 2165 */
2111int clk_set_phase(struct clk *clk, int degrees) 2166int clk_set_phase(struct clk *clk, int degrees)
2112{ 2167{
2113 int ret = 0; 2168 int ret = -EINVAL;
2114 2169
2115 if (!clk) 2170 if (!clk)
2116 goto out; 2171 return 0;
2117 2172
2118 /* sanity check degrees */ 2173 /* sanity check degrees */
2119 degrees %= 360; 2174 degrees %= 360;
@@ -2122,18 +2177,18 @@ int clk_set_phase(struct clk *clk, int degrees)
2122 2177
2123 clk_prepare_lock(); 2178 clk_prepare_lock();
2124 2179
2125 if (!clk->core->ops->set_phase) 2180 trace_clk_set_phase(clk->core, degrees);
2126 goto out_unlock;
2127 2181
2128 ret = clk->core->ops->set_phase(clk->core->hw, degrees); 2182 if (clk->core->ops->set_phase)
2183 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
2184
2185 trace_clk_set_phase_complete(clk->core, degrees);
2129 2186
2130 if (!ret) 2187 if (!ret)
2131 clk->core->phase = degrees; 2188 clk->core->phase = degrees;
2132 2189
2133out_unlock:
2134 clk_prepare_unlock(); 2190 clk_prepare_unlock();
2135 2191
2136out:
2137 return ret; 2192 return ret;
2138} 2193}
2139EXPORT_SYMBOL_GPL(clk_set_phase); 2194EXPORT_SYMBOL_GPL(clk_set_phase);
@@ -2401,7 +2456,7 @@ struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2401 clk->max_rate = ULONG_MAX; 2456 clk->max_rate = ULONG_MAX;
2402 2457
2403 clk_prepare_lock(); 2458 clk_prepare_lock();
2404 hlist_add_head(&clk->child_node, &hw->core->clks); 2459 hlist_add_head(&clk->clks_node, &hw->core->clks);
2405 clk_prepare_unlock(); 2460 clk_prepare_unlock();
2406 2461
2407 return clk; 2462 return clk;
@@ -2410,7 +2465,7 @@ struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2410void __clk_free_clk(struct clk *clk) 2465void __clk_free_clk(struct clk *clk)
2411{ 2466{
2412 clk_prepare_lock(); 2467 clk_prepare_lock();
2413 hlist_del(&clk->child_node); 2468 hlist_del(&clk->clks_node);
2414 clk_prepare_unlock(); 2469 clk_prepare_unlock();
2415 2470
2416 kfree(clk); 2471 kfree(clk);
@@ -2513,6 +2568,8 @@ static void __clk_release(struct kref *ref)
2513 struct clk_core *clk = container_of(ref, struct clk_core, ref); 2568 struct clk_core *clk = container_of(ref, struct clk_core, ref);
2514 int i = clk->num_parents; 2569 int i = clk->num_parents;
2515 2570
2571 lockdep_assert_held(&prepare_lock);
2572
2516 kfree(clk->parents); 2573 kfree(clk->parents);
2517 while (--i >= 0) 2574 while (--i >= 0)
2518 kfree_const(clk->parent_names[i]); 2575 kfree_const(clk->parent_names[i]);
@@ -2688,7 +2745,7 @@ void __clk_put(struct clk *clk)
2688 2745
2689 clk_prepare_lock(); 2746 clk_prepare_lock();
2690 2747
2691 hlist_del(&clk->child_node); 2748 hlist_del(&clk->clks_node);
2692 if (clk->min_rate > clk->core->req_rate || 2749 if (clk->min_rate > clk->core->req_rate ||
2693 clk->max_rate < clk->core->req_rate) 2750 clk->max_rate < clk->core->req_rate)
2694 clk_core_set_rate_nolock(clk->core, clk->core->req_rate); 2751 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
@@ -2834,17 +2891,6 @@ static const struct of_device_id __clk_of_table_sentinel
2834static LIST_HEAD(of_clk_providers); 2891static LIST_HEAD(of_clk_providers);
2835static DEFINE_MUTEX(of_clk_mutex); 2892static DEFINE_MUTEX(of_clk_mutex);
2836 2893
2837/* of_clk_provider list locking helpers */
2838void of_clk_lock(void)
2839{
2840 mutex_lock(&of_clk_mutex);
2841}
2842
2843void of_clk_unlock(void)
2844{
2845 mutex_unlock(&of_clk_mutex);
2846}
2847
2848struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 2894struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
2849 void *data) 2895 void *data)
2850{ 2896{
@@ -2928,7 +2974,11 @@ struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
2928 struct of_clk_provider *provider; 2974 struct of_clk_provider *provider;
2929 struct clk *clk = ERR_PTR(-EPROBE_DEFER); 2975 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
2930 2976
2977 if (!clkspec)
2978 return ERR_PTR(-EINVAL);
2979
2931 /* Check if we have such a provider in our array */ 2980 /* Check if we have such a provider in our array */
2981 mutex_lock(&of_clk_mutex);
2932 list_for_each_entry(provider, &of_clk_providers, link) { 2982 list_for_each_entry(provider, &of_clk_providers, link) {
2933 if (provider->node == clkspec->np) 2983 if (provider->node == clkspec->np)
2934 clk = provider->get(clkspec, provider->data); 2984 clk = provider->get(clkspec, provider->data);
@@ -2944,19 +2994,22 @@ struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
2944 break; 2994 break;
2945 } 2995 }
2946 } 2996 }
2997 mutex_unlock(&of_clk_mutex);
2947 2998
2948 return clk; 2999 return clk;
2949} 3000}
2950 3001
3002/**
3003 * of_clk_get_from_provider() - Lookup a clock from a clock provider
3004 * @clkspec: pointer to a clock specifier data structure
3005 *
3006 * This function looks up a struct clk from the registered list of clock
3007 * providers, an input is a clock specifier data structure as returned
3008 * from the of_parse_phandle_with_args() function call.
3009 */
2951struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec) 3010struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
2952{ 3011{
2953 struct clk *clk; 3012 return __of_clk_get_from_provider(clkspec, NULL, __func__);
2954
2955 mutex_lock(&of_clk_mutex);
2956 clk = __of_clk_get_from_provider(clkspec, NULL, __func__);
2957 mutex_unlock(&of_clk_mutex);
2958
2959 return clk;
2960} 3013}
2961 3014
2962int of_clk_get_parent_count(struct device_node *np) 3015int of_clk_get_parent_count(struct device_node *np)
diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h
index ba845408cc3e..00b35a13cdf3 100644
--- a/drivers/clk/clk.h
+++ b/drivers/clk/clk.h
@@ -12,11 +12,8 @@
12struct clk_hw; 12struct clk_hw;
13 13
14#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) 14#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
15struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec);
16struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec, 15struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
17 const char *dev_id, const char *con_id); 16 const char *dev_id, const char *con_id);
18void of_clk_lock(void);
19void of_clk_unlock(void);
20#endif 17#endif
21 18
22#ifdef CONFIG_COMMON_CLK 19#ifdef CONFIG_COMMON_CLK
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 043fd3633373..1fcb6ef2cdac 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -28,34 +28,6 @@ static LIST_HEAD(clocks);
28static DEFINE_MUTEX(clocks_mutex); 28static DEFINE_MUTEX(clocks_mutex);
29 29
30#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) 30#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
31
32static struct clk *__of_clk_get_by_clkspec(struct of_phandle_args *clkspec,
33 const char *dev_id, const char *con_id)
34{
35 struct clk *clk;
36
37 if (!clkspec)
38 return ERR_PTR(-EINVAL);
39
40 of_clk_lock();
41 clk = __of_clk_get_from_provider(clkspec, dev_id, con_id);
42 of_clk_unlock();
43 return clk;
44}
45
46/**
47 * of_clk_get_by_clkspec() - Lookup a clock form a clock provider
48 * @clkspec: pointer to a clock specifier data structure
49 *
50 * This function looks up a struct clk from the registered list of clock
51 * providers, an input is a clock specifier data structure as returned
52 * from the of_parse_phandle_with_args() function call.
53 */
54struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec)
55{
56 return __of_clk_get_by_clkspec(clkspec, NULL, __func__);
57}
58
59static struct clk *__of_clk_get(struct device_node *np, int index, 31static struct clk *__of_clk_get(struct device_node *np, int index,
60 const char *dev_id, const char *con_id) 32 const char *dev_id, const char *con_id)
61{ 33{
@@ -71,7 +43,7 @@ static struct clk *__of_clk_get(struct device_node *np, int index,
71 if (rc) 43 if (rc)
72 return ERR_PTR(rc); 44 return ERR_PTR(rc);
73 45
74 clk = __of_clk_get_by_clkspec(&clkspec, dev_id, con_id); 46 clk = __of_clk_get_from_provider(&clkspec, dev_id, con_id);
75 of_node_put(clkspec.np); 47 of_node_put(clkspec.np);
76 48
77 return clk; 49 return clk;
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index 2e4f6d432beb..472dd2cb10b3 100644
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -38,44 +38,44 @@
38#include "clk.h" 38#include "clk.h"
39 39
40/* clock parent list */ 40/* clock parent list */
41static const char *timer0_mux_p[] __initconst = { "osc32k", "timerclk01", }; 41static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };
42static const char *timer1_mux_p[] __initconst = { "osc32k", "timerclk01", }; 42static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", };
43static const char *timer2_mux_p[] __initconst = { "osc32k", "timerclk23", }; 43static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", };
44static const char *timer3_mux_p[] __initconst = { "osc32k", "timerclk23", }; 44static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", };
45static const char *timer4_mux_p[] __initconst = { "osc32k", "timerclk45", }; 45static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", };
46static const char *timer5_mux_p[] __initconst = { "osc32k", "timerclk45", }; 46static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", };
47static const char *timer6_mux_p[] __initconst = { "osc32k", "timerclk67", }; 47static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", };
48static const char *timer7_mux_p[] __initconst = { "osc32k", "timerclk67", }; 48static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", };
49static const char *timer8_mux_p[] __initconst = { "osc32k", "timerclk89", }; 49static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", };
50static const char *timer9_mux_p[] __initconst = { "osc32k", "timerclk89", }; 50static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", };
51static const char *uart0_mux_p[] __initconst = { "osc26m", "pclk", }; 51static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", };
52static const char *uart1_mux_p[] __initconst = { "osc26m", "pclk", }; 52static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", };
53static const char *uart2_mux_p[] __initconst = { "osc26m", "pclk", }; 53static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", };
54static const char *uart3_mux_p[] __initconst = { "osc26m", "pclk", }; 54static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", };
55static const char *uart4_mux_p[] __initconst = { "osc26m", "pclk", }; 55static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", };
56static const char *spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; 56static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
57static const char *spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; 57static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
58static const char *spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", }; 58static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
59/* share axi parent */ 59/* share axi parent */
60static const char *saxi_mux_p[] __initconst = { "armpll3", "armpll2", }; 60static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", };
61static const char *pwm0_mux_p[] __initconst = { "osc32k", "osc26m", }; 61static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", };
62static const char *pwm1_mux_p[] __initconst = { "osc32k", "osc26m", }; 62static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", };
63static const char *sd_mux_p[] __initconst = { "armpll2", "armpll3", }; 63static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", };
64static const char *mmc1_mux_p[] __initconst = { "armpll2", "armpll3", }; 64static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", };
65static const char *mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", }; 65static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", };
66static const char *g2d_mux_p[] __initconst = { "armpll2", "armpll3", }; 66static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", };
67static const char *venc_mux_p[] __initconst = { "armpll2", "armpll3", }; 67static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", };
68static const char *vdec_mux_p[] __initconst = { "armpll2", "armpll3", }; 68static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", };
69static const char *vpp_mux_p[] __initconst = { "armpll2", "armpll3", }; 69static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", };
70static const char *edc0_mux_p[] __initconst = { "armpll2", "armpll3", }; 70static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", };
71static const char *ldi0_mux_p[] __initconst = { "armpll2", "armpll4", 71static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4",
72 "armpll3", "armpll5", }; 72 "armpll3", "armpll5", };
73static const char *edc1_mux_p[] __initconst = { "armpll2", "armpll3", }; 73static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", };
74static const char *ldi1_mux_p[] __initconst = { "armpll2", "armpll4", 74static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4",
75 "armpll3", "armpll5", }; 75 "armpll3", "armpll5", };
76static const char *rclk_hsic_p[] __initconst = { "armpll3", "armpll2", }; 76static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", };
77static const char *mmc2_mux_p[] __initconst = { "armpll2", "armpll3", }; 77static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", };
78static const char *mmc3_mux_p[] __initconst = { "armpll2", "armpll3", }; 78static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", };
79 79
80 80
81/* fixed rate clocks */ 81/* fixed rate clocks */
diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c
index 3f369c60fe56..f1d239435826 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -46,15 +46,15 @@ static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
46 { HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, }, 46 { HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, },
47}; 47};
48 48
49static const char *sfc_mux_p[] __initconst = { 49static const char *sfc_mux_p[] __initdata = {
50 "24m", "150m", "200m", "100m", "75m", }; 50 "24m", "150m", "200m", "100m", "75m", };
51static u32 sfc_mux_table[] = {0, 4, 5, 6, 7}; 51static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
52 52
53static const char *sdio_mux_p[] __initconst = { 53static const char *sdio_mux_p[] __initdata = {
54 "75m", "100m", "50m", "15m", }; 54 "75m", "100m", "50m", "15m", };
55static u32 sdio_mux_table[] = {0, 1, 2, 3}; 55static u32 sdio_mux_table[] = {0, 1, 2, 3};
56 56
57static const char *fephy_mux_p[] __initconst = { "25m", "125m"}; 57static const char *fephy_mux_p[] __initdata = { "25m", "125m"};
58static u32 fephy_mux_table[] = {0, 1}; 58static u32 fephy_mux_table[] = {0, 1};
59 59
60 60
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 3b34dba9178d..27696255486d 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -21,6 +21,10 @@ config ARMADA_38X_CLK
21 bool 21 bool
22 select MVEBU_CLK_COMMON 22 select MVEBU_CLK_COMMON
23 23
24config ARMADA_39X_CLK
25 bool
26 select MVEBU_CLK_COMMON
27
24config ARMADA_XP_CLK 28config ARMADA_XP_CLK
25 bool 29 bool
26 select MVEBU_CLK_COMMON 30 select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index a9a56fc01901..645ac7ea3565 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o
5obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o 5obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
6obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o 6obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o
7obj-$(CONFIG_ARMADA_38X_CLK) += armada-38x.o 7obj-$(CONFIG_ARMADA_38X_CLK) += armada-38x.o
8obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o
8obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o 9obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o
9obj-$(CONFIG_DOVE_CLK) += dove.o 10obj-$(CONFIG_DOVE_CLK) += dove.o
10obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o 11obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-39x.c b/drivers/clk/mvebu/armada-39x.c
new file mode 100644
index 000000000000..efb974df9822
--- /dev/null
+++ b/drivers/clk/mvebu/armada-39x.c
@@ -0,0 +1,156 @@
1/*
2 * Marvell Armada 39x SoC clocks
3 *
4 * Copyright (C) 2015 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk-provider.h>
18#include <linux/io.h>
19#include <linux/of.h>
20#include "common.h"
21
22/*
23 * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
24 *
25 * SARL[15] : TCLK frequency
26 * 0 = 250 MHz
27 * 1 = 200 MHz
28 *
29 * SARH[0] : Reference clock frequency
30 * 0 = 25 Mhz
31 * 1 = 40 Mhz
32 */
33
34#define SARL 0
35#define SARL_A390_TCLK_FREQ_OPT 15
36#define SARL_A390_TCLK_FREQ_OPT_MASK 0x1
37#define SARL_A390_CPU_DDR_L2_FREQ_OPT 10
38#define SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
39#define SARH 4
40#define SARH_A390_REFCLK_FREQ BIT(0)
41
42static const u32 armada_39x_tclk_frequencies[] __initconst = {
43 250000000,
44 200000000,
45};
46
47static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
48{
49 u8 tclk_freq_select;
50
51 tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
52 SARL_A390_TCLK_FREQ_OPT_MASK);
53 return armada_39x_tclk_frequencies[tclk_freq_select];
54}
55
56static const u32 armada_39x_cpu_frequencies[] __initconst = {
57 [0x0] = 666 * 1000 * 1000,
58 [0x2] = 800 * 1000 * 1000,
59 [0x3] = 800 * 1000 * 1000,
60 [0x4] = 1066 * 1000 * 1000,
61 [0x5] = 1066 * 1000 * 1000,
62 [0x6] = 1200 * 1000 * 1000,
63 [0x8] = 1332 * 1000 * 1000,
64 [0xB] = 1600 * 1000 * 1000,
65 [0xC] = 1600 * 1000 * 1000,
66 [0x12] = 1800 * 1000 * 1000,
67 [0x1E] = 1800 * 1000 * 1000,
68};
69
70static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
71{
72 u8 cpu_freq_select;
73
74 cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
75 SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
76 if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
77 pr_err("Selected CPU frequency (%d) unsupported\n",
78 cpu_freq_select);
79 return 0;
80 }
81
82 return armada_39x_cpu_frequencies[cpu_freq_select];
83}
84
85enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
86
87static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
88 { .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
89 { .id = A390_CPU_TO_HCLK, .name = "hclk" },
90 { .id = A390_CPU_TO_DCLK, .name = "dclk" },
91};
92
93static void __init armada_39x_get_clk_ratio(
94 void __iomem *sar, int id, int *mult, int *div)
95{
96 switch (id) {
97 case A390_CPU_TO_NBCLK:
98 *mult = 1;
99 *div = 2;
100 break;
101 case A390_CPU_TO_HCLK:
102 *mult = 1;
103 *div = 4;
104 break;
105 case A390_CPU_TO_DCLK:
106 *mult = 1;
107 *div = 2;
108 break;
109 }
110}
111
112static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
113{
114 if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
115 return 40 * 1000 * 1000;
116 else
117 return 25 * 1000 * 1000;
118}
119
120static const struct coreclk_soc_desc armada_39x_coreclks = {
121 .get_tclk_freq = armada_39x_get_tclk_freq,
122 .get_cpu_freq = armada_39x_get_cpu_freq,
123 .get_clk_ratio = armada_39x_get_clk_ratio,
124 .get_refclk_freq = armada_39x_refclk_ratio,
125 .ratios = armada_39x_coreclk_ratios,
126 .num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
127};
128
129static void __init armada_39x_coreclk_init(struct device_node *np)
130{
131 mvebu_coreclk_setup(np, &armada_39x_coreclks);
132}
133CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
134 armada_39x_coreclk_init);
135
136/*
137 * Clock Gating Control
138 */
139static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
140 { "pex1", NULL, 5 },
141 { "pex2", NULL, 6 },
142 { "pex3", NULL, 7 },
143 { "pex0", NULL, 8 },
144 { "usb3h0", NULL, 9 },
145 { "sdio", NULL, 17 },
146 { "xor0", NULL, 22 },
147 { "xor1", NULL, 28 },
148 { }
149};
150
151static void __init armada_39x_clk_gating_init(struct device_node *np)
152{
153 mvebu_clk_gating_setup(np, armada_39x_gating_desc);
154}
155CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
156 armada_39x_clk_gating_init);
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 0d4d1216f2dd..15b370ff3748 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
121 121
122 /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ 122 /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
123 clk_data.clk_num = 2 + desc->num_ratios; 123 clk_data.clk_num = 2 + desc->num_ratios;
124
125 /* One more clock for the optional refclk */
126 if (desc->get_refclk_freq)
127 clk_data.clk_num += 1;
128
124 clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), 129 clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
125 GFP_KERNEL); 130 GFP_KERNEL);
126 if (WARN_ON(!clk_data.clks)) { 131 if (WARN_ON(!clk_data.clks)) {
@@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
162 WARN_ON(IS_ERR(clk_data.clks[2+n])); 167 WARN_ON(IS_ERR(clk_data.clks[2+n]));
163 }; 168 };
164 169
170 /* Register optional refclk */
171 if (desc->get_refclk_freq) {
172 const char *name = "refclk";
173 of_property_read_string_index(np, "clock-output-names",
174 2 + desc->num_ratios, &name);
175 rate = desc->get_refclk_freq(base);
176 clk_data.clks[2 + desc->num_ratios] =
177 clk_register_fixed_rate(NULL, name, NULL,
178 CLK_IS_ROOT, rate);
179 WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
180 }
181
165 /* SAR register isn't needed anymore */ 182 /* SAR register isn't needed anymore */
166 iounmap(base); 183 iounmap(base);
167 184
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
index 783b5631a453..f0de6c8a494a 100644
--- a/drivers/clk/mvebu/common.h
+++ b/drivers/clk/mvebu/common.h
@@ -30,6 +30,7 @@ struct coreclk_soc_desc {
30 u32 (*get_tclk_freq)(void __iomem *sar); 30 u32 (*get_tclk_freq)(void __iomem *sar);
31 u32 (*get_cpu_freq)(void __iomem *sar); 31 u32 (*get_cpu_freq)(void __iomem *sar);
32 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); 32 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
33 u32 (*get_refclk_freq)(void __iomem *sar);
33 bool (*is_sscg_enabled)(void __iomem *sar); 34 bool (*is_sscg_enabled)(void __iomem *sar);
34 u32 (*fix_sscg_deviation)(u32 system_clk); 35 u32 (*fix_sscg_deviation)(u32 system_clk);
35 const struct coreclk_ratio *ratios; 36 const struct coreclk_ratio *ratios;
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 9fc9359f5133..22d136aa699f 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -77,12 +77,12 @@ static void __init clk_misc_init(void)
77 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); 77 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
78} 78}
79 79
80static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; 80static const char *sel_pll[] __initdata = { "pll", "ref_xtal", };
81static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; 81static const char *sel_cpu[] __initdata = { "ref_cpu", "ref_xtal", };
82static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; 82static const char *sel_pix[] __initdata = { "ref_pix", "ref_xtal", };
83static const char *sel_io[] __initconst = { "ref_io", "ref_xtal", }; 83static const char *sel_io[] __initdata = { "ref_io", "ref_xtal", };
84static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; 84static const char *cpu_sels[] __initdata = { "cpu_pll", "cpu_xtal", };
85static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; 85static const char *emi_sels[] __initdata = { "emi_pll", "emi_xtal", };
86 86
87enum imx23_clk { 87enum imx23_clk {
88 ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel, 88 ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index a6c35010e4e5..b1be3746ce95 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -125,15 +125,15 @@ static void __init clk_misc_init(void)
125 writel_relaxed(val, FRAC0); 125 writel_relaxed(val, FRAC0);
126} 126}
127 127
128static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; 128static const char *sel_cpu[] __initdata = { "ref_cpu", "ref_xtal", };
129static const char *sel_io0[] __initconst = { "ref_io0", "ref_xtal", }; 129static const char *sel_io0[] __initdata = { "ref_io0", "ref_xtal", };
130static const char *sel_io1[] __initconst = { "ref_io1", "ref_xtal", }; 130static const char *sel_io1[] __initdata = { "ref_io1", "ref_xtal", };
131static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; 131static const char *sel_pix[] __initdata = { "ref_pix", "ref_xtal", };
132static const char *sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", }; 132static const char *sel_gpmi[] __initdata = { "ref_gpmi", "ref_xtal", };
133static const char *sel_pll0[] __initconst = { "pll0", "ref_xtal", }; 133static const char *sel_pll0[] __initdata = { "pll0", "ref_xtal", };
134static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; 134static const char *cpu_sels[] __initdata = { "cpu_pll", "cpu_xtal", };
135static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; 135static const char *emi_sels[] __initdata = { "emi_pll", "emi_xtal", };
136static const char *ptp_sels[] __initconst = { "ref_xtal", "pll0", }; 136static const char *ptp_sels[] __initdata = { "ref_xtal", "pll0", };
137 137
138enum imx28_clk { 138enum imx28_clk {
139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, 139 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
diff --git a/drivers/clk/pxa/clk-pxa.h b/drivers/clk/pxa/clk-pxa.h
index 323965430111..b04c5b9c0ea8 100644
--- a/drivers/clk/pxa/clk-pxa.h
+++ b/drivers/clk/pxa/clk-pxa.h
@@ -14,7 +14,7 @@
14#define _CLK_PXA_ 14#define _CLK_PXA_
15 15
16#define PARENTS(name) \ 16#define PARENTS(name) \
17 static const char *name ## _parents[] __initconst 17 static const char *name ## _parents[] __initdata
18#define MUX_RO_RATE_RO_OPS(name, clk_name) \ 18#define MUX_RO_RATE_RO_OPS(name, clk_name) \
19 static struct clk_hw name ## _mux_hw; \ 19 static struct clk_hw name ## _mux_hw; \
20 static struct clk_hw name ## _rate_hw; \ 20 static struct clk_hw name ## _rate_hw; \
diff --git a/drivers/clk/pxa/clk-pxa3xx.c b/drivers/clk/pxa/clk-pxa3xx.c
index 39f891bba09a..4b93a1efb36d 100644
--- a/drivers/clk/pxa/clk-pxa3xx.c
+++ b/drivers/clk/pxa/clk-pxa3xx.c
@@ -336,6 +336,9 @@ static void __init pxa3xx_base_clocks_init(void)
336 clk_register_clk_pxa3xx_smemc(); 336 clk_register_clk_pxa3xx_smemc();
337 clk_register_gate(NULL, "CLK_POUT", "osc_13mhz", 0, 337 clk_register_gate(NULL, "CLK_POUT", "osc_13mhz", 0,
338 (void __iomem *)&OSCC, 11, 0, NULL); 338 (void __iomem *)&OSCC, 11, 0, NULL);
339 clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL,
340 clk_register_fixed_factor(NULL, "os-timer0",
341 "osc_13mhz", 0, 1, 4));
339} 342}
340 343
341int __init pxa3xx_clocks_init(void) 344int __init pxa3xx_clocks_init(void)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0d7ab52b7ab0..59d16668bdf5 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -1,6 +1,7 @@
1config COMMON_CLK_QCOM 1config COMMON_CLK_QCOM
2 tristate "Support for Qualcomm's clock controllers" 2 tristate "Support for Qualcomm's clock controllers"
3 depends on OF 3 depends on OF
4 depends on ARCH_QCOM || COMPILE_TEST
4 select REGMAP_MMIO 5 select REGMAP_MMIO
5 select RESET_CONTROLLER 6 select RESET_CONTROLLER
6 7
@@ -46,6 +47,14 @@ config MSM_GCC_8660
46 Say Y if you want to use peripheral devices such as UART, SPI, 47 Say Y if you want to use peripheral devices such as UART, SPI,
47 i2c, USB, SD/eMMC, etc. 48 i2c, USB, SD/eMMC, etc.
48 49
50config MSM_GCC_8916
51 tristate "MSM8916 Global Clock Controller"
52 depends on COMMON_CLK_QCOM
53 help
54 Support for the global clock controller on msm8916 devices.
55 Say Y if you want to use devices such as UART, SPI i2c, USB,
56 SD/eMMC, display, graphics, camera etc.
57
49config MSM_GCC_8960 58config MSM_GCC_8960
50 tristate "APQ8064/MSM8960 Global Clock Controller" 59 tristate "APQ8064/MSM8960 Global Clock Controller"
51 depends on COMMON_CLK_QCOM 60 depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 617826469595..50b337a24a87 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
15obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o 15obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
16obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o 16obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
17obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o 17obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
18obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
18obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 19obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
19obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o 20obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
20obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o 21obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index b4325f65a1bf..245d5063a385 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -71,12 +71,8 @@ static int clk_pll_enable(struct clk_hw *hw)
71 udelay(50); 71 udelay(50);
72 72
73 /* Enable PLL output. */ 73 /* Enable PLL output. */
74 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, 74 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
75 PLL_OUTCTRL); 75 PLL_OUTCTRL);
76 if (ret)
77 return ret;
78
79 return 0;
80} 76}
81 77
82static void clk_pll_disable(struct clk_hw *hw) 78static void clk_pll_disable(struct clk_hw *hw)
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 0039bd7d3965..7b3d62674203 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -47,15 +47,20 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw)
47 struct clk_rcg *rcg = to_clk_rcg(hw); 47 struct clk_rcg *rcg = to_clk_rcg(hw);
48 int num_parents = __clk_get_num_parents(hw->clk); 48 int num_parents = __clk_get_num_parents(hw->clk);
49 u32 ns; 49 u32 ns;
50 int i; 50 int i, ret;
51 51
52 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); 52 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
53 if (ret)
54 goto err;
53 ns = ns_to_src(&rcg->s, ns); 55 ns = ns_to_src(&rcg->s, ns);
54 for (i = 0; i < num_parents; i++) 56 for (i = 0; i < num_parents; i++)
55 if (ns == rcg->s.parent_map[i]) 57 if (ns == rcg->s.parent_map[i].cfg)
56 return i; 58 return i;
57 59
58 return -EINVAL; 60err:
61 pr_debug("%s: Clock %s has invalid parent, using default.\n",
62 __func__, __clk_get_name(hw->clk));
63 return 0;
59} 64}
60 65
61static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) 66static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
@@ -70,21 +75,28 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
70 int num_parents = __clk_get_num_parents(hw->clk); 75 int num_parents = __clk_get_num_parents(hw->clk);
71 u32 ns, reg; 76 u32 ns, reg;
72 int bank; 77 int bank;
73 int i; 78 int i, ret;
74 struct src_sel *s; 79 struct src_sel *s;
75 80
76 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); 81 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
82 if (ret)
83 goto err;
77 bank = reg_to_bank(rcg, reg); 84 bank = reg_to_bank(rcg, reg);
78 s = &rcg->s[bank]; 85 s = &rcg->s[bank];
79 86
80 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); 87 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
88 if (ret)
89 goto err;
81 ns = ns_to_src(s, ns); 90 ns = ns_to_src(s, ns);
82 91
83 for (i = 0; i < num_parents; i++) 92 for (i = 0; i < num_parents; i++)
84 if (ns == s->parent_map[i]) 93 if (ns == s->parent_map[i].cfg)
85 return i; 94 return i;
86 95
87 return -EINVAL; 96err:
97 pr_debug("%s: Clock %s has invalid parent, using default.\n",
98 __func__, __clk_get_name(hw->clk));
99 return 0;
88} 100}
89 101
90static int clk_rcg_set_parent(struct clk_hw *hw, u8 index) 102static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
@@ -93,7 +105,7 @@ static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
93 u32 ns; 105 u32 ns;
94 106
95 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); 107 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
96 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns); 108 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
97 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); 109 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
98 110
99 return 0; 111 return 0;
@@ -191,10 +203,10 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
191 return val; 203 return val;
192} 204}
193 205
194static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f) 206static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
195{ 207{
196 u32 ns, md, reg; 208 u32 ns, md, reg;
197 int bank, new_bank; 209 int bank, new_bank, ret, index;
198 struct mn *mn; 210 struct mn *mn;
199 struct pre_div *p; 211 struct pre_div *p;
200 struct src_sel *s; 212 struct src_sel *s;
@@ -206,38 +218,56 @@ static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
206 218
207 enabled = __clk_is_enabled(hw->clk); 219 enabled = __clk_is_enabled(hw->clk);
208 220
209 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); 221 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
222 if (ret)
223 return ret;
210 bank = reg_to_bank(rcg, reg); 224 bank = reg_to_bank(rcg, reg);
211 new_bank = enabled ? !bank : bank; 225 new_bank = enabled ? !bank : bank;
212 226
213 ns_reg = rcg->ns_reg[new_bank]; 227 ns_reg = rcg->ns_reg[new_bank];
214 regmap_read(rcg->clkr.regmap, ns_reg, &ns); 228 ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
229 if (ret)
230 return ret;
215 231
216 if (banked_mn) { 232 if (banked_mn) {
217 mn = &rcg->mn[new_bank]; 233 mn = &rcg->mn[new_bank];
218 md_reg = rcg->md_reg[new_bank]; 234 md_reg = rcg->md_reg[new_bank];
219 235
220 ns |= BIT(mn->mnctr_reset_bit); 236 ns |= BIT(mn->mnctr_reset_bit);
221 regmap_write(rcg->clkr.regmap, ns_reg, ns); 237 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
238 if (ret)
239 return ret;
222 240
223 regmap_read(rcg->clkr.regmap, md_reg, &md); 241 ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
242 if (ret)
243 return ret;
224 md = mn_to_md(mn, f->m, f->n, md); 244 md = mn_to_md(mn, f->m, f->n, md);
225 regmap_write(rcg->clkr.regmap, md_reg, md); 245 ret = regmap_write(rcg->clkr.regmap, md_reg, md);
226 246 if (ret)
247 return ret;
227 ns = mn_to_ns(mn, f->m, f->n, ns); 248 ns = mn_to_ns(mn, f->m, f->n, ns);
228 regmap_write(rcg->clkr.regmap, ns_reg, ns); 249 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
250 if (ret)
251 return ret;
229 252
230 /* Two NS registers means mode control is in NS register */ 253 /* Two NS registers means mode control is in NS register */
231 if (rcg->ns_reg[0] != rcg->ns_reg[1]) { 254 if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
232 ns = mn_to_reg(mn, f->m, f->n, ns); 255 ns = mn_to_reg(mn, f->m, f->n, ns);
233 regmap_write(rcg->clkr.regmap, ns_reg, ns); 256 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
257 if (ret)
258 return ret;
234 } else { 259 } else {
235 reg = mn_to_reg(mn, f->m, f->n, reg); 260 reg = mn_to_reg(mn, f->m, f->n, reg);
236 regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg); 261 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
262 reg);
263 if (ret)
264 return ret;
237 } 265 }
238 266
239 ns &= ~BIT(mn->mnctr_reset_bit); 267 ns &= ~BIT(mn->mnctr_reset_bit);
240 regmap_write(rcg->clkr.regmap, ns_reg, ns); 268 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
269 if (ret)
270 return ret;
241 } 271 }
242 272
243 if (banked_p) { 273 if (banked_p) {
@@ -246,14 +276,24 @@ static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
246 } 276 }
247 277
248 s = &rcg->s[new_bank]; 278 s = &rcg->s[new_bank];
249 ns = src_to_ns(s, s->parent_map[f->src], ns); 279 index = qcom_find_src_index(hw, s->parent_map, f->src);
250 regmap_write(rcg->clkr.regmap, ns_reg, ns); 280 if (index < 0)
281 return index;
282 ns = src_to_ns(s, s->parent_map[index].cfg, ns);
283 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
284 if (ret)
285 return ret;
251 286
252 if (enabled) { 287 if (enabled) {
253 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); 288 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
289 if (ret)
290 return ret;
254 reg ^= BIT(rcg->mux_sel_bit); 291 reg ^= BIT(rcg->mux_sel_bit);
255 regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg); 292 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
293 if (ret)
294 return ret;
256 } 295 }
296 return 0;
257} 297}
258 298
259static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index) 299static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
@@ -279,10 +319,8 @@ static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
279 if (banked_p) 319 if (banked_p)
280 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1; 320 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
281 321
282 f.src = index; 322 f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);
283 configure_bank(rcg, &f); 323 return configure_bank(rcg, &f);
284
285 return 0;
286} 324}
287 325
288/* 326/*
@@ -369,17 +407,23 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
369static long _freq_tbl_determine_rate(struct clk_hw *hw, 407static long _freq_tbl_determine_rate(struct clk_hw *hw,
370 const struct freq_tbl *f, unsigned long rate, 408 const struct freq_tbl *f, unsigned long rate,
371 unsigned long min_rate, unsigned long max_rate, 409 unsigned long min_rate, unsigned long max_rate,
372 unsigned long *p_rate, struct clk_hw **p_hw) 410 unsigned long *p_rate, struct clk_hw **p_hw,
411 const struct parent_map *parent_map)
373{ 412{
374 unsigned long clk_flags; 413 unsigned long clk_flags;
375 struct clk *p; 414 struct clk *p;
415 int index;
376 416
377 f = qcom_find_freq(f, rate); 417 f = qcom_find_freq(f, rate);
378 if (!f) 418 if (!f)
379 return -EINVAL; 419 return -EINVAL;
380 420
421 index = qcom_find_src_index(hw, parent_map, f->src);
422 if (index < 0)
423 return index;
424
381 clk_flags = __clk_get_flags(hw->clk); 425 clk_flags = __clk_get_flags(hw->clk);
382 p = clk_get_parent_by_index(hw->clk, f->src); 426 p = clk_get_parent_by_index(hw->clk, index);
383 if (clk_flags & CLK_SET_RATE_PARENT) { 427 if (clk_flags & CLK_SET_RATE_PARENT) {
384 rate = rate * f->pre_div; 428 rate = rate * f->pre_div;
385 if (f->n) { 429 if (f->n) {
@@ -404,7 +448,7 @@ static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
404 struct clk_rcg *rcg = to_clk_rcg(hw); 448 struct clk_rcg *rcg = to_clk_rcg(hw);
405 449
406 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate, 450 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,
407 max_rate, p_rate, p); 451 max_rate, p_rate, p, rcg->s.parent_map);
408} 452}
409 453
410static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, 454static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
@@ -412,9 +456,16 @@ static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
412 unsigned long *p_rate, struct clk_hw **p) 456 unsigned long *p_rate, struct clk_hw **p)
413{ 457{
414 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); 458 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
459 u32 reg;
460 int bank;
461 struct src_sel *s;
462
463 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
464 bank = reg_to_bank(rcg, reg);
465 s = &rcg->s[bank];
415 466
416 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate, 467 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,
417 max_rate, p_rate, p); 468 max_rate, p_rate, p, s->parent_map);
418} 469}
419 470
420static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate, 471static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
@@ -424,8 +475,9 @@ static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
424 struct clk_rcg *rcg = to_clk_rcg(hw); 475 struct clk_rcg *rcg = to_clk_rcg(hw);
425 const struct freq_tbl *f = rcg->freq_tbl; 476 const struct freq_tbl *f = rcg->freq_tbl;
426 struct clk *p; 477 struct clk *p;
478 int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);
427 479
428 p = clk_get_parent_by_index(hw->clk, f->src); 480 p = clk_get_parent_by_index(hw->clk, index);
429 *p_hw = __clk_get_hw(p); 481 *p_hw = __clk_get_hw(p);
430 *p_rate = __clk_round_rate(p, rate); 482 *p_rate = __clk_round_rate(p, rate);
431 483
@@ -495,6 +547,57 @@ static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
495 return __clk_rcg_set_rate(rcg, rcg->freq_tbl); 547 return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
496} 548}
497 549
550/*
551 * This type of clock has a glitch-free mux that switches between the output of
552 * the M/N counter and an always on clock source (XO). When clk_set_rate() is
553 * called we need to make sure that we don't switch to the M/N counter if it
554 * isn't clocking because the mux will get stuck and the clock will stop
555 * outputting a clock. This can happen if the framework isn't aware that this
556 * clock is on and so clk_set_rate() doesn't turn on the new parent. To fix
557 * this we switch the mux in the enable/disable ops and reprogram the M/N
558 * counter in the set_rate op. We also make sure to switch away from the M/N
559 * counter in set_rate if software thinks the clock is off.
560 */
561static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
562 unsigned long parent_rate)
563{
564 struct clk_rcg *rcg = to_clk_rcg(hw);
565 const struct freq_tbl *f;
566 int ret;
567 u32 gfm = BIT(10);
568
569 f = qcom_find_freq(rcg->freq_tbl, rate);
570 if (!f)
571 return -EINVAL;
572
573 /* Switch to XO to avoid glitches */
574 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
575 ret = __clk_rcg_set_rate(rcg, f);
576 /* Switch back to M/N if it's clocking */
577 if (__clk_is_enabled(hw->clk))
578 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
579
580 return ret;
581}
582
583static int clk_rcg_lcc_enable(struct clk_hw *hw)
584{
585 struct clk_rcg *rcg = to_clk_rcg(hw);
586 u32 gfm = BIT(10);
587
588 /* Use M/N */
589 return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
590}
591
592static void clk_rcg_lcc_disable(struct clk_hw *hw)
593{
594 struct clk_rcg *rcg = to_clk_rcg(hw);
595 u32 gfm = BIT(10);
596
597 /* Use XO */
598 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
599}
600
498static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate) 601static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
499{ 602{
500 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); 603 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
@@ -504,9 +607,7 @@ static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
504 if (!f) 607 if (!f)
505 return -EINVAL; 608 return -EINVAL;
506 609
507 configure_bank(rcg, f); 610 return configure_bank(rcg, f);
508
509 return 0;
510} 611}
511 612
512static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate, 613static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -543,6 +644,17 @@ const struct clk_ops clk_rcg_bypass_ops = {
543}; 644};
544EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops); 645EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);
545 646
647const struct clk_ops clk_rcg_lcc_ops = {
648 .enable = clk_rcg_lcc_enable,
649 .disable = clk_rcg_lcc_disable,
650 .get_parent = clk_rcg_get_parent,
651 .set_parent = clk_rcg_set_parent,
652 .recalc_rate = clk_rcg_recalc_rate,
653 .determine_rate = clk_rcg_determine_rate,
654 .set_rate = clk_rcg_lcc_set_rate,
655};
656EXPORT_SYMBOL_GPL(clk_rcg_lcc_ops);
657
546const struct clk_ops clk_dyn_rcg_ops = { 658const struct clk_ops clk_dyn_rcg_ops = {
547 .enable = clk_enable_regmap, 659 .enable = clk_enable_regmap,
548 .is_enabled = clk_is_enabled_regmap, 660 .is_enabled = clk_is_enabled_regmap,
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 687e41f91d7c..56028bb31d87 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -26,6 +26,16 @@ struct freq_tbl {
26}; 26};
27 27
28/** 28/**
29 * struct parent_map - map table for PLL source select configuration values
30 * @src: source PLL
31 * @cfg: configuration value
32 */
33struct parent_map {
34 u8 src;
35 u8 cfg;
36};
37
38/**
29 * struct mn - M/N:D counter 39 * struct mn - M/N:D counter
30 * @mnctr_en_bit: bit to enable mn counter 40 * @mnctr_en_bit: bit to enable mn counter
31 * @mnctr_reset_bit: bit to assert mn counter reset 41 * @mnctr_reset_bit: bit to assert mn counter reset
@@ -65,7 +75,7 @@ struct pre_div {
65struct src_sel { 75struct src_sel {
66 u8 src_sel_shift; 76 u8 src_sel_shift;
67#define SRC_SEL_MASK 0x7 77#define SRC_SEL_MASK 0x7
68 const u8 *parent_map; 78 const struct parent_map *parent_map;
69}; 79};
70 80
71/** 81/**
@@ -96,6 +106,7 @@ struct clk_rcg {
96 106
97extern const struct clk_ops clk_rcg_ops; 107extern const struct clk_ops clk_rcg_ops;
98extern const struct clk_ops clk_rcg_bypass_ops; 108extern const struct clk_ops clk_rcg_bypass_ops;
109extern const struct clk_ops clk_rcg_lcc_ops;
99 110
100#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) 111#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
101 112
@@ -150,7 +161,7 @@ struct clk_rcg2 {
150 u32 cmd_rcgr; 161 u32 cmd_rcgr;
151 u8 mnd_width; 162 u8 mnd_width;
152 u8 hid_width; 163 u8 hid_width;
153 const u8 *parent_map; 164 const struct parent_map *parent_map;
154 const struct freq_tbl *freq_tbl; 165 const struct freq_tbl *freq_tbl;
155 struct clk_regmap clkr; 166 struct clk_regmap clkr;
156}; 167};
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 742acfa18d63..b95d17fbb8d7 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -69,16 +69,19 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
69 69
70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); 70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
71 if (ret) 71 if (ret)
72 return ret; 72 goto err;
73 73
74 cfg &= CFG_SRC_SEL_MASK; 74 cfg &= CFG_SRC_SEL_MASK;
75 cfg >>= CFG_SRC_SEL_SHIFT; 75 cfg >>= CFG_SRC_SEL_SHIFT;
76 76
77 for (i = 0; i < num_parents; i++) 77 for (i = 0; i < num_parents; i++)
78 if (cfg == rcg->parent_map[i]) 78 if (cfg == rcg->parent_map[i].cfg)
79 return i; 79 return i;
80 80
81 return -EINVAL; 81err:
82 pr_debug("%s: Clock %s has invalid parent, using default.\n",
83 __func__, __clk_get_name(hw->clk));
84 return 0;
82} 85}
83 86
84static int update_config(struct clk_rcg2 *rcg) 87static int update_config(struct clk_rcg2 *rcg)
@@ -111,10 +114,10 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
111{ 114{
112 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 115 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
113 int ret; 116 int ret;
117 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
114 118
115 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 119 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
116 CFG_SRC_SEL_MASK, 120 CFG_SRC_SEL_MASK, cfg);
117 rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
118 if (ret) 121 if (ret)
119 return ret; 122 return ret;
120 123
@@ -179,13 +182,19 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
179{ 182{
180 unsigned long clk_flags; 183 unsigned long clk_flags;
181 struct clk *p; 184 struct clk *p;
185 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
186 int index;
182 187
183 f = qcom_find_freq(f, rate); 188 f = qcom_find_freq(f, rate);
184 if (!f) 189 if (!f)
185 return -EINVAL; 190 return -EINVAL;
186 191
192 index = qcom_find_src_index(hw, rcg->parent_map, f->src);
193 if (index < 0)
194 return index;
195
187 clk_flags = __clk_get_flags(hw->clk); 196 clk_flags = __clk_get_flags(hw->clk);
188 p = clk_get_parent_by_index(hw->clk, f->src); 197 p = clk_get_parent_by_index(hw->clk, index);
189 if (clk_flags & CLK_SET_RATE_PARENT) { 198 if (clk_flags & CLK_SET_RATE_PARENT) {
190 if (f->pre_div) { 199 if (f->pre_div) {
191 rate /= 2; 200 rate /= 2;
@@ -219,7 +228,11 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
219static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 228static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
220{ 229{
221 u32 cfg, mask; 230 u32 cfg, mask;
222 int ret; 231 struct clk_hw *hw = &rcg->clkr.hw;
232 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
233
234 if (index < 0)
235 return index;
223 236
224 if (rcg->mnd_width && f->n) { 237 if (rcg->mnd_width && f->n) {
225 mask = BIT(rcg->mnd_width) - 1; 238 mask = BIT(rcg->mnd_width) - 1;
@@ -242,8 +255,8 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
242 mask = BIT(rcg->hid_width) - 1; 255 mask = BIT(rcg->hid_width) - 1;
243 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK; 256 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
244 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; 257 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
245 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT; 258 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
246 if (rcg->mnd_width && f->n) 259 if (rcg->mnd_width && f->n && (f->m != f->n))
247 cfg |= CFG_MODE_DUAL_EDGE; 260 cfg |= CFG_MODE_DUAL_EDGE;
248 ret = regmap_update_bits(rcg->clkr.regmap, 261 ret = regmap_update_bits(rcg->clkr.regmap,
249 rcg->cmd_rcgr + CFG_REG, mask, cfg); 262 rcg->cmd_rcgr + CFG_REG, mask, cfg);
@@ -374,9 +387,10 @@ static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
374 s64 request; 387 s64 request;
375 u32 mask = BIT(rcg->hid_width) - 1; 388 u32 mask = BIT(rcg->hid_width) - 1;
376 u32 hid_div; 389 u32 hid_div;
390 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
377 391
378 /* Force the correct parent */ 392 /* Force the correct parent */
379 *p = __clk_get_hw(clk_get_parent_by_index(hw->clk, f->src)); 393 *p = __clk_get_hw(clk_get_parent_by_index(hw->clk, index));
380 394
381 if (src_rate == 810000000) 395 if (src_rate == 810000000)
382 frac = frac_table_810m; 396 frac = frac_table_810m;
@@ -420,6 +434,7 @@ static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
420{ 434{
421 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 435 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
422 const struct freq_tbl *f = rcg->freq_tbl; 436 const struct freq_tbl *f = rcg->freq_tbl;
437 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
423 unsigned long parent_rate, div; 438 unsigned long parent_rate, div;
424 u32 mask = BIT(rcg->hid_width) - 1; 439 u32 mask = BIT(rcg->hid_width) - 1;
425 struct clk *p; 440 struct clk *p;
@@ -427,7 +442,7 @@ static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
427 if (rate == 0) 442 if (rate == 0)
428 return -EINVAL; 443 return -EINVAL;
429 444
430 p = clk_get_parent_by_index(hw->clk, f->src); 445 p = clk_get_parent_by_index(hw->clk, index);
431 *p_hw = __clk_get_hw(p); 446 *p_hw = __clk_get_hw(p);
432 *p_rate = parent_rate = __clk_round_rate(p, rate); 447 *p_rate = parent_rate = __clk_round_rate(p, rate);
433 448
@@ -489,7 +504,8 @@ static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
489 int delta = 100000; 504 int delta = 100000;
490 const struct freq_tbl *f = rcg->freq_tbl; 505 const struct freq_tbl *f = rcg->freq_tbl;
491 const struct frac_entry *frac = frac_table_pixel; 506 const struct frac_entry *frac = frac_table_pixel;
492 struct clk *parent = clk_get_parent_by_index(hw->clk, f->src); 507 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
508 struct clk *parent = clk_get_parent_by_index(hw->clk, index);
493 509
494 *p = __clk_get_hw(parent); 510 *p = __clk_get_hw(parent);
495 511
@@ -518,7 +534,8 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
518 int delta = 100000; 534 int delta = 100000;
519 u32 mask = BIT(rcg->hid_width) - 1; 535 u32 mask = BIT(rcg->hid_width) - 1;
520 u32 hid_div; 536 u32 hid_div;
521 struct clk *parent = clk_get_parent_by_index(hw->clk, f.src); 537 int index = qcom_find_src_index(hw, rcg->parent_map, f.src);
538 struct clk *parent = clk_get_parent_by_index(hw->clk, index);
522 539
523 for (; frac->num; frac++) { 540 for (; frac->num; frac++) {
524 request = (rate * frac->den) / frac->num; 541 request = (rate * frac->den) / frac->num;
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index e20d947db3e5..f7101e330b1d 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -43,6 +43,18 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
43} 43}
44EXPORT_SYMBOL_GPL(qcom_find_freq); 44EXPORT_SYMBOL_GPL(qcom_find_freq);
45 45
46int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
47{
48 int i, num_parents = __clk_get_num_parents(hw->clk);
49
50 for (i = 0; i < num_parents; i++)
51 if (src == map[i].src)
52 return i;
53
54 return -ENOENT;
55}
56EXPORT_SYMBOL_GPL(qcom_find_src_index);
57
46struct regmap * 58struct regmap *
47qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc) 59qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
48{ 60{
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index f519322acdf3..7a0e73713063 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -19,6 +19,8 @@ struct clk_regmap;
19struct qcom_reset_map; 19struct qcom_reset_map;
20struct regmap; 20struct regmap;
21struct freq_tbl; 21struct freq_tbl;
22struct clk_hw;
23struct parent_map;
22 24
23struct qcom_cc_desc { 25struct qcom_cc_desc {
24 const struct regmap_config *config; 26 const struct regmap_config *config;
@@ -30,6 +32,8 @@ struct qcom_cc_desc {
30 32
31extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, 33extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
32 unsigned long rate); 34 unsigned long rate);
35extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
36 u8 src);
33 37
34extern struct regmap *qcom_cc_map(struct platform_device *pdev, 38extern struct regmap *qcom_cc_map(struct platform_device *pdev,
35 const struct qcom_cc_desc *desc); 39 const struct qcom_cc_desc *desc);
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index e3ef90264214..54a756b90a37 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -32,18 +32,20 @@
32#include "clk-branch.h" 32#include "clk-branch.h"
33#include "reset.h" 33#include "reset.h"
34 34
35#define P_XO 0 35enum {
36#define P_GPLL0 1 36 P_XO,
37#define P_GPLL1 1 37 P_GPLL0,
38#define P_GPLL4 2 38 P_GPLL1,
39#define P_PCIE_0_1_PIPE_CLK 1 39 P_GPLL4,
40#define P_SATA_ASIC0_CLK 1 40 P_PCIE_0_1_PIPE_CLK,
41#define P_SATA_RX_CLK 1 41 P_SATA_ASIC0_CLK,
42#define P_SLEEP_CLK 1 42 P_SATA_RX_CLK,
43 P_SLEEP_CLK,
44};
43 45
44static const u8 gcc_xo_gpll0_map[] = { 46static const struct parent_map gcc_xo_gpll0_map[] = {
45 [P_XO] = 0, 47 { P_XO, 0 },
46 [P_GPLL0] = 1, 48 { P_GPLL0, 1 }
47}; 49};
48 50
49static const char *gcc_xo_gpll0[] = { 51static const char *gcc_xo_gpll0[] = {
@@ -51,10 +53,10 @@ static const char *gcc_xo_gpll0[] = {
51 "gpll0_vote", 53 "gpll0_vote",
52}; 54};
53 55
54static const u8 gcc_xo_gpll0_gpll4_map[] = { 56static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
55 [P_XO] = 0, 57 { P_XO, 0 },
56 [P_GPLL0] = 1, 58 { P_GPLL0, 1 },
57 [P_GPLL4] = 5, 59 { P_GPLL4, 5 }
58}; 60};
59 61
60static const char *gcc_xo_gpll0_gpll4[] = { 62static const char *gcc_xo_gpll0_gpll4[] = {
@@ -63,9 +65,9 @@ static const char *gcc_xo_gpll0_gpll4[] = {
63 "gpll4_vote", 65 "gpll4_vote",
64}; 66};
65 67
66static const u8 gcc_xo_sata_asic0_map[] = { 68static const struct parent_map gcc_xo_sata_asic0_map[] = {
67 [P_XO] = 0, 69 { P_XO, 0 },
68 [P_SATA_ASIC0_CLK] = 2, 70 { P_SATA_ASIC0_CLK, 2 }
69}; 71};
70 72
71static const char *gcc_xo_sata_asic0[] = { 73static const char *gcc_xo_sata_asic0[] = {
@@ -73,9 +75,9 @@ static const char *gcc_xo_sata_asic0[] = {
73 "sata_asic0_clk", 75 "sata_asic0_clk",
74}; 76};
75 77
76static const u8 gcc_xo_sata_rx_map[] = { 78static const struct parent_map gcc_xo_sata_rx_map[] = {
77 [P_XO] = 0, 79 { P_XO, 0 },
78 [P_SATA_RX_CLK] = 2, 80 { P_SATA_RX_CLK, 2}
79}; 81};
80 82
81static const char *gcc_xo_sata_rx[] = { 83static const char *gcc_xo_sata_rx[] = {
@@ -83,9 +85,9 @@ static const char *gcc_xo_sata_rx[] = {
83 "sata_rx_clk", 85 "sata_rx_clk",
84}; 86};
85 87
86static const u8 gcc_xo_pcie_map[] = { 88static const struct parent_map gcc_xo_pcie_map[] = {
87 [P_XO] = 0, 89 { P_XO, 0 },
88 [P_PCIE_0_1_PIPE_CLK] = 2, 90 { P_PCIE_0_1_PIPE_CLK, 2 }
89}; 91};
90 92
91static const char *gcc_xo_pcie[] = { 93static const char *gcc_xo_pcie[] = {
@@ -93,9 +95,9 @@ static const char *gcc_xo_pcie[] = {
93 "pcie_pipe", 95 "pcie_pipe",
94}; 96};
95 97
96static const u8 gcc_xo_pcie_sleep_map[] = { 98static const struct parent_map gcc_xo_pcie_sleep_map[] = {
97 [P_XO] = 0, 99 { P_XO, 0 },
98 [P_SLEEP_CLK] = 6, 100 { P_SLEEP_CLK, 6 }
99}; 101};
100 102
101static const char *gcc_xo_pcie_sleep[] = { 103static const char *gcc_xo_pcie_sleep[] = {
@@ -1263,9 +1265,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1263 { } 1265 { }
1264}; 1266};
1265 1267
1266static u8 usb_hsic_clk_src_map[] = { 1268static const struct parent_map usb_hsic_clk_src_map[] = {
1267 [P_XO] = 0, 1269 { P_XO, 0 },
1268 [P_GPLL1] = 4, 1270 { P_GPLL1, 4 }
1269}; 1271};
1270 1272
1271static struct clk_rcg2 usb_hsic_clk_src = { 1273static struct clk_rcg2 usb_hsic_clk_src = {
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index cbdc31dea7f4..a50936a17376 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -140,15 +140,17 @@ static struct clk_regmap pll14_vote = {
140 }, 140 },
141}; 141};
142 142
143#define P_PXO 0 143enum {
144#define P_PLL8 1 144 P_PXO,
145#define P_PLL3 1 145 P_PLL8,
146#define P_PLL0 2 146 P_PLL3,
147#define P_CXO 2 147 P_PLL0,
148 P_CXO,
149};
148 150
149static const u8 gcc_pxo_pll8_map[] = { 151static const struct parent_map gcc_pxo_pll8_map[] = {
150 [P_PXO] = 0, 152 { P_PXO, 0 },
151 [P_PLL8] = 3, 153 { P_PLL8, 3 }
152}; 154};
153 155
154static const char *gcc_pxo_pll8[] = { 156static const char *gcc_pxo_pll8[] = {
@@ -156,10 +158,10 @@ static const char *gcc_pxo_pll8[] = {
156 "pll8_vote", 158 "pll8_vote",
157}; 159};
158 160
159static const u8 gcc_pxo_pll8_cxo_map[] = { 161static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
160 [P_PXO] = 0, 162 { P_PXO, 0 },
161 [P_PLL8] = 3, 163 { P_PLL8, 3 },
162 [P_CXO] = 5, 164 { P_CXO, 5 }
163}; 165};
164 166
165static const char *gcc_pxo_pll8_cxo[] = { 167static const char *gcc_pxo_pll8_cxo[] = {
@@ -168,14 +170,14 @@ static const char *gcc_pxo_pll8_cxo[] = {
168 "cxo", 170 "cxo",
169}; 171};
170 172
171static const u8 gcc_pxo_pll3_map[] = { 173static const struct parent_map gcc_pxo_pll3_map[] = {
172 [P_PXO] = 0, 174 { P_PXO, 0 },
173 [P_PLL3] = 1, 175 { P_PLL3, 1 }
174}; 176};
175 177
176static const u8 gcc_pxo_pll3_sata_map[] = { 178static const struct parent_map gcc_pxo_pll3_sata_map[] = {
177 [P_PXO] = 0, 179 { P_PXO, 0 },
178 [P_PLL3] = 6, 180 { P_PLL3, 6 }
179}; 181};
180 182
181static const char *gcc_pxo_pll3[] = { 183static const char *gcc_pxo_pll3[] = {
@@ -183,10 +185,10 @@ static const char *gcc_pxo_pll3[] = {
183 "pll3", 185 "pll3",
184}; 186};
185 187
186static const u8 gcc_pxo_pll8_pll0[] = { 188static const struct parent_map gcc_pxo_pll8_pll0[] = {
187 [P_PXO] = 0, 189 { P_PXO, 0 },
188 [P_PLL8] = 3, 190 { P_PLL8, 3 },
189 [P_PLL0] = 2, 191 { P_PLL0, 2 }
190}; 192};
191 193
192static const char *gcc_pxo_pll8_pll0_map[] = { 194static const char *gcc_pxo_pll8_pll0_map[] = {
@@ -525,8 +527,8 @@ static struct freq_tbl clk_tbl_gsbi_qup[] = {
525 { 10800000, P_PXO, 1, 2, 5 }, 527 { 10800000, P_PXO, 1, 2, 5 },
526 { 15060000, P_PLL8, 1, 2, 51 }, 528 { 15060000, P_PLL8, 1, 2, 51 },
527 { 24000000, P_PLL8, 4, 1, 4 }, 529 { 24000000, P_PLL8, 4, 1, 4 },
530 { 25000000, P_PXO, 1, 0, 0 },
528 { 25600000, P_PLL8, 1, 1, 15 }, 531 { 25600000, P_PLL8, 1, 1, 15 },
529 { 27000000, P_PXO, 1, 0, 0 },
530 { 48000000, P_PLL8, 4, 1, 2 }, 532 { 48000000, P_PLL8, 4, 1, 2 },
531 { 51200000, P_PLL8, 1, 2, 15 }, 533 { 51200000, P_PLL8, 1, 2, 15 },
532 { } 534 { }
@@ -2170,6 +2172,36 @@ static struct clk_branch usb_fs1_h_clk = {
2170 }, 2172 },
2171}; 2173};
2172 2174
2175static struct clk_branch ebi2_clk = {
2176 .hwcg_reg = 0x3b00,
2177 .hwcg_bit = 6,
2178 .halt_reg = 0x2fcc,
2179 .halt_bit = 1,
2180 .clkr = {
2181 .enable_reg = 0x3b00,
2182 .enable_mask = BIT(4),
2183 .hw.init = &(struct clk_init_data){
2184 .name = "ebi2_clk",
2185 .ops = &clk_branch_ops,
2186 .flags = CLK_IS_ROOT,
2187 },
2188 },
2189};
2190
2191static struct clk_branch ebi2_aon_clk = {
2192 .halt_reg = 0x2fcc,
2193 .halt_bit = 0,
2194 .clkr = {
2195 .enable_reg = 0x3b00,
2196 .enable_mask = BIT(8),
2197 .hw.init = &(struct clk_init_data){
2198 .name = "ebi2_always_on_clk",
2199 .ops = &clk_branch_ops,
2200 .flags = CLK_IS_ROOT,
2201 },
2202 },
2203};
2204
2173static struct clk_regmap *gcc_ipq806x_clks[] = { 2205static struct clk_regmap *gcc_ipq806x_clks[] = {
2174 [PLL0] = &pll0.clkr, 2206 [PLL0] = &pll0.clkr,
2175 [PLL0_VOTE] = &pll0_vote, 2207 [PLL0_VOTE] = &pll0_vote,
@@ -2273,6 +2305,8 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
2273 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, 2305 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2274 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, 2306 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2275 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, 2307 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2308 [EBI2_CLK] = &ebi2_clk.clkr,
2309 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
2276}; 2310};
2277 2311
2278static const struct qcom_reset_map gcc_ipq806x_resets[] = { 2312static const struct qcom_reset_map gcc_ipq806x_resets[] = {
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index f366e68f7316..fc6b12da5b30 100644
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -59,13 +59,15 @@ static struct clk_regmap pll8_vote = {
59 }, 59 },
60}; 60};
61 61
62#define P_PXO 0 62enum {
63#define P_PLL8 1 63 P_PXO,
64#define P_CXO 2 64 P_PLL8,
65 P_CXO,
66};
65 67
66static const u8 gcc_pxo_pll8_map[] = { 68static const struct parent_map gcc_pxo_pll8_map[] = {
67 [P_PXO] = 0, 69 { P_PXO, 0 },
68 [P_PLL8] = 3, 70 { P_PLL8, 3 }
69}; 71};
70 72
71static const char *gcc_pxo_pll8[] = { 73static const char *gcc_pxo_pll8[] = {
@@ -73,10 +75,10 @@ static const char *gcc_pxo_pll8[] = {
73 "pll8_vote", 75 "pll8_vote",
74}; 76};
75 77
76static const u8 gcc_pxo_pll8_cxo_map[] = { 78static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
77 [P_PXO] = 0, 79 { P_PXO, 0 },
78 [P_PLL8] = 3, 80 { P_PLL8, 3 },
79 [P_CXO] = 5, 81 { P_CXO, 5 }
80}; 82};
81 83
82static const char *gcc_pxo_pll8_cxo[] = { 84static const char *gcc_pxo_pll8_cxo[] = {
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
new file mode 100644
index 000000000000..d3458474eb3a
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -0,0 +1,2868 @@
1/*
2 * Copyright 2015 Linaro Limited
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8916.h>
26#include <dt-bindings/reset/qcom,gcc-msm8916.h>
27
28#include "common.h"
29#include "clk-regmap.h"
30#include "clk-pll.h"
31#include "clk-rcg.h"
32#include "clk-branch.h"
33#include "reset.h"
34
35enum {
36 P_XO,
37 P_GPLL0,
38 P_GPLL0_AUX,
39 P_BIMC,
40 P_GPLL1,
41 P_GPLL1_AUX,
42 P_GPLL2,
43 P_GPLL2_AUX,
44 P_SLEEP_CLK,
45 P_DSI0_PHYPLL_BYTE,
46 P_DSI0_PHYPLL_DSI,
47};
48
49static const struct parent_map gcc_xo_gpll0_map[] = {
50 { P_XO, 0 },
51 { P_GPLL0, 1 },
52};
53
54static const char *gcc_xo_gpll0[] = {
55 "xo",
56 "gpll0_vote",
57};
58
59static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
60 { P_XO, 0 },
61 { P_GPLL0, 1 },
62 { P_BIMC, 2 },
63};
64
65static const char *gcc_xo_gpll0_bimc[] = {
66 "xo",
67 "gpll0_vote",
68 "bimc_pll_vote",
69};
70
71static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
72 { P_XO, 0 },
73 { P_GPLL0_AUX, 3 },
74 { P_GPLL2_AUX, 2 },
75 { P_GPLL1, 1 },
76};
77
78static const char *gcc_xo_gpll0a_gpll1_gpll2a[] = {
79 "xo",
80 "gpll0_vote",
81 "gpll1_vote",
82 "gpll2_vote",
83};
84
85static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
86 { P_XO, 0 },
87 { P_GPLL0, 1 },
88 { P_GPLL2, 2 },
89};
90
91static const char *gcc_xo_gpll0_gpll2[] = {
92 "xo",
93 "gpll0_vote",
94 "gpll2_vote",
95};
96
97static const struct parent_map gcc_xo_gpll0a_map[] = {
98 { P_XO, 0 },
99 { P_GPLL0_AUX, 2 },
100};
101
102static const char *gcc_xo_gpll0a[] = {
103 "xo",
104 "gpll0_vote",
105};
106
107static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
108 { P_XO, 0 },
109 { P_GPLL0, 1 },
110 { P_GPLL1_AUX, 2 },
111 { P_SLEEP_CLK, 6 },
112};
113
114static const char *gcc_xo_gpll0_gpll1a_sleep[] = {
115 "xo",
116 "gpll0_vote",
117 "gpll1_vote",
118 "sleep_clk",
119};
120
121static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
122 { P_XO, 0 },
123 { P_GPLL0, 1 },
124 { P_GPLL1_AUX, 2 },
125};
126
127static const char *gcc_xo_gpll0_gpll1a[] = {
128 "xo",
129 "gpll0_vote",
130 "gpll1_vote",
131};
132
133static const struct parent_map gcc_xo_dsibyte_map[] = {
134 { P_XO, 0, },
135 { P_DSI0_PHYPLL_BYTE, 2 },
136};
137
138static const char *gcc_xo_dsibyte[] = {
139 "xo",
140 "dsi0pllbyte",
141};
142
143static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
144 { P_XO, 0 },
145 { P_GPLL0_AUX, 2 },
146 { P_DSI0_PHYPLL_BYTE, 1 },
147};
148
149static const char *gcc_xo_gpll0a_dsibyte[] = {
150 "xo",
151 "gpll0_vote",
152 "dsi0pllbyte",
153};
154
155static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
156 { P_XO, 0 },
157 { P_GPLL0, 1 },
158 { P_DSI0_PHYPLL_DSI, 2 },
159};
160
161static const char *gcc_xo_gpll0_dsiphy[] = {
162 "xo",
163 "gpll0_vote",
164 "dsi0pll",
165};
166
167static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
168 { P_XO, 0 },
169 { P_GPLL0_AUX, 2 },
170 { P_DSI0_PHYPLL_DSI, 1 },
171};
172
173static const char *gcc_xo_gpll0a_dsiphy[] = {
174 "xo",
175 "gpll0_vote",
176 "dsi0pll",
177};
178
179static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
180 { P_XO, 0 },
181 { P_GPLL0_AUX, 1 },
182 { P_GPLL1, 3 },
183 { P_GPLL2, 2 },
184};
185
186static const char *gcc_xo_gpll0a_gpll1_gpll2[] = {
187 "xo",
188 "gpll0_vote",
189 "gpll1_vote",
190 "gpll2_vote",
191};
192
193#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
194
195static struct clk_pll gpll0 = {
196 .l_reg = 0x21004,
197 .m_reg = 0x21008,
198 .n_reg = 0x2100c,
199 .config_reg = 0x21014,
200 .mode_reg = 0x21000,
201 .status_reg = 0x2101c,
202 .status_bit = 17,
203 .clkr.hw.init = &(struct clk_init_data){
204 .name = "gpll0",
205 .parent_names = (const char *[]){ "xo" },
206 .num_parents = 1,
207 .ops = &clk_pll_ops,
208 },
209};
210
211static struct clk_regmap gpll0_vote = {
212 .enable_reg = 0x45000,
213 .enable_mask = BIT(0),
214 .hw.init = &(struct clk_init_data){
215 .name = "gpll0_vote",
216 .parent_names = (const char *[]){ "gpll0" },
217 .num_parents = 1,
218 .ops = &clk_pll_vote_ops,
219 },
220};
221
222static struct clk_pll gpll1 = {
223 .l_reg = 0x20004,
224 .m_reg = 0x20008,
225 .n_reg = 0x2000c,
226 .config_reg = 0x20014,
227 .mode_reg = 0x20000,
228 .status_reg = 0x2001c,
229 .status_bit = 17,
230 .clkr.hw.init = &(struct clk_init_data){
231 .name = "gpll1",
232 .parent_names = (const char *[]){ "xo" },
233 .num_parents = 1,
234 .ops = &clk_pll_ops,
235 },
236};
237
238static struct clk_regmap gpll1_vote = {
239 .enable_reg = 0x45000,
240 .enable_mask = BIT(1),
241 .hw.init = &(struct clk_init_data){
242 .name = "gpll1_vote",
243 .parent_names = (const char *[]){ "gpll1" },
244 .num_parents = 1,
245 .ops = &clk_pll_vote_ops,
246 },
247};
248
249static struct clk_pll gpll2 = {
250 .l_reg = 0x4a004,
251 .m_reg = 0x4a008,
252 .n_reg = 0x4a00c,
253 .config_reg = 0x4a014,
254 .mode_reg = 0x4a000,
255 .status_reg = 0x4a01c,
256 .status_bit = 17,
257 .clkr.hw.init = &(struct clk_init_data){
258 .name = "gpll2",
259 .parent_names = (const char *[]){ "xo" },
260 .num_parents = 1,
261 .ops = &clk_pll_ops,
262 },
263};
264
265static struct clk_regmap gpll2_vote = {
266 .enable_reg = 0x45000,
267 .enable_mask = BIT(2),
268 .hw.init = &(struct clk_init_data){
269 .name = "gpll2_vote",
270 .parent_names = (const char *[]){ "gpll2" },
271 .num_parents = 1,
272 .ops = &clk_pll_vote_ops,
273 },
274};
275
276static struct clk_pll bimc_pll = {
277 .l_reg = 0x23004,
278 .m_reg = 0x23008,
279 .n_reg = 0x2300c,
280 .config_reg = 0x23014,
281 .mode_reg = 0x23000,
282 .status_reg = 0x2301c,
283 .status_bit = 17,
284 .clkr.hw.init = &(struct clk_init_data){
285 .name = "bimc_pll",
286 .parent_names = (const char *[]){ "xo" },
287 .num_parents = 1,
288 .ops = &clk_pll_ops,
289 },
290};
291
292static struct clk_regmap bimc_pll_vote = {
293 .enable_reg = 0x45000,
294 .enable_mask = BIT(3),
295 .hw.init = &(struct clk_init_data){
296 .name = "bimc_pll_vote",
297 .parent_names = (const char *[]){ "bimc_pll" },
298 .num_parents = 1,
299 .ops = &clk_pll_vote_ops,
300 },
301};
302
303static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
304 .cmd_rcgr = 0x27000,
305 .hid_width = 5,
306 .parent_map = gcc_xo_gpll0_bimc_map,
307 .clkr.hw.init = &(struct clk_init_data){
308 .name = "pcnoc_bfdcd_clk_src",
309 .parent_names = gcc_xo_gpll0_bimc,
310 .num_parents = 3,
311 .ops = &clk_rcg2_ops,
312 },
313};
314
315static struct clk_rcg2 system_noc_bfdcd_clk_src = {
316 .cmd_rcgr = 0x26004,
317 .hid_width = 5,
318 .parent_map = gcc_xo_gpll0_bimc_map,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "system_noc_bfdcd_clk_src",
321 .parent_names = gcc_xo_gpll0_bimc,
322 .num_parents = 3,
323 .ops = &clk_rcg2_ops,
324 },
325};
326
327static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
328 F(40000000, P_GPLL0, 10, 1, 2),
329 F(80000000, P_GPLL0, 10, 0, 0),
330 { }
331};
332
333static struct clk_rcg2 camss_ahb_clk_src = {
334 .cmd_rcgr = 0x5a000,
335 .mnd_width = 8,
336 .hid_width = 5,
337 .parent_map = gcc_xo_gpll0_map,
338 .freq_tbl = ftbl_gcc_camss_ahb_clk,
339 .clkr.hw.init = &(struct clk_init_data){
340 .name = "camss_ahb_clk_src",
341 .parent_names = gcc_xo_gpll0,
342 .num_parents = 2,
343 .ops = &clk_rcg2_ops,
344 },
345};
346
347static const struct freq_tbl ftbl_apss_ahb_clk[] = {
348 F(19200000, P_XO, 1, 0, 0),
349 F(50000000, P_GPLL0, 16, 0, 0),
350 F(100000000, P_GPLL0, 8, 0, 0),
351 F(133330000, P_GPLL0, 6, 0, 0),
352 { }
353};
354
355static struct clk_rcg2 apss_ahb_clk_src = {
356 .cmd_rcgr = 0x46000,
357 .hid_width = 5,
358 .parent_map = gcc_xo_gpll0_map,
359 .freq_tbl = ftbl_apss_ahb_clk,
360 .clkr.hw.init = &(struct clk_init_data){
361 .name = "apss_ahb_clk_src",
362 .parent_names = gcc_xo_gpll0,
363 .num_parents = 2,
364 .ops = &clk_rcg2_ops,
365 },
366};
367
368static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
369 F(100000000, P_GPLL0, 8, 0, 0),
370 F(200000000, P_GPLL0, 4, 0, 0),
371 { }
372};
373
374static struct clk_rcg2 csi0_clk_src = {
375 .cmd_rcgr = 0x4e020,
376 .hid_width = 5,
377 .parent_map = gcc_xo_gpll0_map,
378 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
379 .clkr.hw.init = &(struct clk_init_data){
380 .name = "csi0_clk_src",
381 .parent_names = gcc_xo_gpll0,
382 .num_parents = 2,
383 .ops = &clk_rcg2_ops,
384 },
385};
386
387static struct clk_rcg2 csi1_clk_src = {
388 .cmd_rcgr = 0x4f020,
389 .hid_width = 5,
390 .parent_map = gcc_xo_gpll0_map,
391 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
392 .clkr.hw.init = &(struct clk_init_data){
393 .name = "csi1_clk_src",
394 .parent_names = gcc_xo_gpll0,
395 .num_parents = 2,
396 .ops = &clk_rcg2_ops,
397 },
398};
399
400static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
401 F(19200000, P_XO, 1, 0, 0),
402 F(50000000, P_GPLL0_AUX, 16, 0, 0),
403 F(80000000, P_GPLL0_AUX, 10, 0, 0),
404 F(100000000, P_GPLL0_AUX, 8, 0, 0),
405 F(160000000, P_GPLL0_AUX, 5, 0, 0),
406 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
407 F(200000000, P_GPLL0_AUX, 4, 0, 0),
408 F(266670000, P_GPLL0_AUX, 3, 0, 0),
409 F(294912000, P_GPLL1, 3, 0, 0),
410 F(310000000, P_GPLL2, 3, 0, 0),
411 F(400000000, P_GPLL0_AUX, 2, 0, 0),
412 { }
413};
414
415static struct clk_rcg2 gfx3d_clk_src = {
416 .cmd_rcgr = 0x59000,
417 .hid_width = 5,
418 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
419 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
420 .clkr.hw.init = &(struct clk_init_data){
421 .name = "gfx3d_clk_src",
422 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
423 .num_parents = 4,
424 .ops = &clk_rcg2_ops,
425 },
426};
427
428static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
429 F(50000000, P_GPLL0, 16, 0, 0),
430 F(80000000, P_GPLL0, 10, 0, 0),
431 F(100000000, P_GPLL0, 8, 0, 0),
432 F(160000000, P_GPLL0, 5, 0, 0),
433 F(177780000, P_GPLL0, 4.5, 0, 0),
434 F(200000000, P_GPLL0, 4, 0, 0),
435 F(266670000, P_GPLL0, 3, 0, 0),
436 F(320000000, P_GPLL0, 2.5, 0, 0),
437 F(400000000, P_GPLL0, 2, 0, 0),
438 F(465000000, P_GPLL2, 2, 0, 0),
439 { }
440};
441
442static struct clk_rcg2 vfe0_clk_src = {
443 .cmd_rcgr = 0x58000,
444 .hid_width = 5,
445 .parent_map = gcc_xo_gpll0_gpll2_map,
446 .freq_tbl = ftbl_gcc_camss_vfe0_clk,
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "vfe0_clk_src",
449 .parent_names = gcc_xo_gpll0_gpll2,
450 .num_parents = 3,
451 .ops = &clk_rcg2_ops,
452 },
453};
454
455static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
456 F(19200000, P_XO, 1, 0, 0),
457 F(50000000, P_GPLL0, 16, 0, 0),
458 { }
459};
460
461static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
462 .cmd_rcgr = 0x0200c,
463 .hid_width = 5,
464 .parent_map = gcc_xo_gpll0_map,
465 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
466 .clkr.hw.init = &(struct clk_init_data){
467 .name = "blsp1_qup1_i2c_apps_clk_src",
468 .parent_names = gcc_xo_gpll0,
469 .num_parents = 2,
470 .ops = &clk_rcg2_ops,
471 },
472};
473
474static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
475 F(960000, P_XO, 10, 1, 2),
476 F(4800000, P_XO, 4, 0, 0),
477 F(9600000, P_XO, 2, 0, 0),
478 F(16000000, P_GPLL0, 10, 1, 5),
479 F(19200000, P_XO, 1, 0, 0),
480 F(25000000, P_GPLL0, 16, 1, 2),
481 F(50000000, P_GPLL0, 16, 0, 0),
482 { }
483};
484
485static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
486 .cmd_rcgr = 0x02024,
487 .mnd_width = 8,
488 .hid_width = 5,
489 .parent_map = gcc_xo_gpll0_map,
490 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
491 .clkr.hw.init = &(struct clk_init_data){
492 .name = "blsp1_qup1_spi_apps_clk_src",
493 .parent_names = gcc_xo_gpll0,
494 .num_parents = 2,
495 .ops = &clk_rcg2_ops,
496 },
497};
498
499static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
500 .cmd_rcgr = 0x03000,
501 .hid_width = 5,
502 .parent_map = gcc_xo_gpll0_map,
503 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
504 .clkr.hw.init = &(struct clk_init_data){
505 .name = "blsp1_qup2_i2c_apps_clk_src",
506 .parent_names = gcc_xo_gpll0,
507 .num_parents = 2,
508 .ops = &clk_rcg2_ops,
509 },
510};
511
512static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
513 .cmd_rcgr = 0x03014,
514 .mnd_width = 8,
515 .hid_width = 5,
516 .parent_map = gcc_xo_gpll0_map,
517 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
518 .clkr.hw.init = &(struct clk_init_data){
519 .name = "blsp1_qup2_spi_apps_clk_src",
520 .parent_names = gcc_xo_gpll0,
521 .num_parents = 2,
522 .ops = &clk_rcg2_ops,
523 },
524};
525
526static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
527 .cmd_rcgr = 0x04000,
528 .hid_width = 5,
529 .parent_map = gcc_xo_gpll0_map,
530 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "blsp1_qup3_i2c_apps_clk_src",
533 .parent_names = gcc_xo_gpll0,
534 .num_parents = 2,
535 .ops = &clk_rcg2_ops,
536 },
537};
538
539static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
540 .cmd_rcgr = 0x04024,
541 .mnd_width = 8,
542 .hid_width = 5,
543 .parent_map = gcc_xo_gpll0_map,
544 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
545 .clkr.hw.init = &(struct clk_init_data){
546 .name = "blsp1_qup3_spi_apps_clk_src",
547 .parent_names = gcc_xo_gpll0,
548 .num_parents = 2,
549 .ops = &clk_rcg2_ops,
550 },
551};
552
553static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
554 .cmd_rcgr = 0x05000,
555 .hid_width = 5,
556 .parent_map = gcc_xo_gpll0_map,
557 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
558 .clkr.hw.init = &(struct clk_init_data){
559 .name = "blsp1_qup4_i2c_apps_clk_src",
560 .parent_names = gcc_xo_gpll0,
561 .num_parents = 2,
562 .ops = &clk_rcg2_ops,
563 },
564};
565
566static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
567 .cmd_rcgr = 0x05024,
568 .mnd_width = 8,
569 .hid_width = 5,
570 .parent_map = gcc_xo_gpll0_map,
571 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
572 .clkr.hw.init = &(struct clk_init_data){
573 .name = "blsp1_qup4_spi_apps_clk_src",
574 .parent_names = gcc_xo_gpll0,
575 .num_parents = 2,
576 .ops = &clk_rcg2_ops,
577 },
578};
579
580static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
581 .cmd_rcgr = 0x06000,
582 .hid_width = 5,
583 .parent_map = gcc_xo_gpll0_map,
584 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
585 .clkr.hw.init = &(struct clk_init_data){
586 .name = "blsp1_qup5_i2c_apps_clk_src",
587 .parent_names = gcc_xo_gpll0,
588 .num_parents = 2,
589 .ops = &clk_rcg2_ops,
590 },
591};
592
593static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
594 .cmd_rcgr = 0x06024,
595 .mnd_width = 8,
596 .hid_width = 5,
597 .parent_map = gcc_xo_gpll0_map,
598 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
599 .clkr.hw.init = &(struct clk_init_data){
600 .name = "blsp1_qup5_spi_apps_clk_src",
601 .parent_names = gcc_xo_gpll0,
602 .num_parents = 2,
603 .ops = &clk_rcg2_ops,
604 },
605};
606
607static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
608 .cmd_rcgr = 0x07000,
609 .hid_width = 5,
610 .parent_map = gcc_xo_gpll0_map,
611 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
612 .clkr.hw.init = &(struct clk_init_data){
613 .name = "blsp1_qup6_i2c_apps_clk_src",
614 .parent_names = gcc_xo_gpll0,
615 .num_parents = 2,
616 .ops = &clk_rcg2_ops,
617 },
618};
619
620static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
621 .cmd_rcgr = 0x07024,
622 .mnd_width = 8,
623 .hid_width = 5,
624 .parent_map = gcc_xo_gpll0_map,
625 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
626 .clkr.hw.init = &(struct clk_init_data){
627 .name = "blsp1_qup6_spi_apps_clk_src",
628 .parent_names = gcc_xo_gpll0,
629 .num_parents = 2,
630 .ops = &clk_rcg2_ops,
631 },
632};
633
634static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
635 F(3686400, P_GPLL0, 1, 72, 15625),
636 F(7372800, P_GPLL0, 1, 144, 15625),
637 F(14745600, P_GPLL0, 1, 288, 15625),
638 F(16000000, P_GPLL0, 10, 1, 5),
639 F(19200000, P_XO, 1, 0, 0),
640 F(24000000, P_GPLL0, 1, 3, 100),
641 F(25000000, P_GPLL0, 16, 1, 2),
642 F(32000000, P_GPLL0, 1, 1, 25),
643 F(40000000, P_GPLL0, 1, 1, 20),
644 F(46400000, P_GPLL0, 1, 29, 500),
645 F(48000000, P_GPLL0, 1, 3, 50),
646 F(51200000, P_GPLL0, 1, 8, 125),
647 F(56000000, P_GPLL0, 1, 7, 100),
648 F(58982400, P_GPLL0, 1, 1152, 15625),
649 F(60000000, P_GPLL0, 1, 3, 40),
650 { }
651};
652
653static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
654 .cmd_rcgr = 0x02044,
655 .mnd_width = 16,
656 .hid_width = 5,
657 .parent_map = gcc_xo_gpll0_map,
658 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
659 .clkr.hw.init = &(struct clk_init_data){
660 .name = "blsp1_uart1_apps_clk_src",
661 .parent_names = gcc_xo_gpll0,
662 .num_parents = 2,
663 .ops = &clk_rcg2_ops,
664 },
665};
666
667static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
668 .cmd_rcgr = 0x03034,
669 .mnd_width = 16,
670 .hid_width = 5,
671 .parent_map = gcc_xo_gpll0_map,
672 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "blsp1_uart2_apps_clk_src",
675 .parent_names = gcc_xo_gpll0,
676 .num_parents = 2,
677 .ops = &clk_rcg2_ops,
678 },
679};
680
681static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
682 F(19200000, P_XO, 1, 0, 0),
683 { }
684};
685
686static struct clk_rcg2 cci_clk_src = {
687 .cmd_rcgr = 0x51000,
688 .mnd_width = 8,
689 .hid_width = 5,
690 .parent_map = gcc_xo_gpll0a_map,
691 .freq_tbl = ftbl_gcc_camss_cci_clk,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "cci_clk_src",
694 .parent_names = gcc_xo_gpll0a,
695 .num_parents = 2,
696 .ops = &clk_rcg2_ops,
697 },
698};
699
700static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
701 F(100000000, P_GPLL0, 8, 0, 0),
702 F(200000000, P_GPLL0, 4, 0, 0),
703 { }
704};
705
706static struct clk_rcg2 camss_gp0_clk_src = {
707 .cmd_rcgr = 0x54000,
708 .mnd_width = 8,
709 .hid_width = 5,
710 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
711 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
712 .clkr.hw.init = &(struct clk_init_data){
713 .name = "camss_gp0_clk_src",
714 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
715 .num_parents = 4,
716 .ops = &clk_rcg2_ops,
717 },
718};
719
720static struct clk_rcg2 camss_gp1_clk_src = {
721 .cmd_rcgr = 0x55000,
722 .mnd_width = 8,
723 .hid_width = 5,
724 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
725 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
726 .clkr.hw.init = &(struct clk_init_data){
727 .name = "camss_gp1_clk_src",
728 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
729 .num_parents = 4,
730 .ops = &clk_rcg2_ops,
731 },
732};
733
734static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
735 F(133330000, P_GPLL0, 6, 0, 0),
736 F(266670000, P_GPLL0, 3, 0, 0),
737 F(320000000, P_GPLL0, 2.5, 0, 0),
738 { }
739};
740
741static struct clk_rcg2 jpeg0_clk_src = {
742 .cmd_rcgr = 0x57000,
743 .hid_width = 5,
744 .parent_map = gcc_xo_gpll0_map,
745 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
746 .clkr.hw.init = &(struct clk_init_data){
747 .name = "jpeg0_clk_src",
748 .parent_names = gcc_xo_gpll0,
749 .num_parents = 2,
750 .ops = &clk_rcg2_ops,
751 },
752};
753
754static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
755 F(9600000, P_XO, 2, 0, 0),
756 F(23880000, P_GPLL0, 1, 2, 67),
757 F(66670000, P_GPLL0, 12, 0, 0),
758 { }
759};
760
761static struct clk_rcg2 mclk0_clk_src = {
762 .cmd_rcgr = 0x52000,
763 .mnd_width = 8,
764 .hid_width = 5,
765 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
766 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
767 .clkr.hw.init = &(struct clk_init_data){
768 .name = "mclk0_clk_src",
769 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
770 .num_parents = 4,
771 .ops = &clk_rcg2_ops,
772 },
773};
774
775static struct clk_rcg2 mclk1_clk_src = {
776 .cmd_rcgr = 0x53000,
777 .mnd_width = 8,
778 .hid_width = 5,
779 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
780 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
781 .clkr.hw.init = &(struct clk_init_data){
782 .name = "mclk1_clk_src",
783 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
784 .num_parents = 4,
785 .ops = &clk_rcg2_ops,
786 },
787};
788
789static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
790 F(100000000, P_GPLL0, 8, 0, 0),
791 F(200000000, P_GPLL0, 4, 0, 0),
792 { }
793};
794
795static struct clk_rcg2 csi0phytimer_clk_src = {
796 .cmd_rcgr = 0x4e000,
797 .hid_width = 5,
798 .parent_map = gcc_xo_gpll0_gpll1a_map,
799 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
800 .clkr.hw.init = &(struct clk_init_data){
801 .name = "csi0phytimer_clk_src",
802 .parent_names = gcc_xo_gpll0_gpll1a,
803 .num_parents = 3,
804 .ops = &clk_rcg2_ops,
805 },
806};
807
808static struct clk_rcg2 csi1phytimer_clk_src = {
809 .cmd_rcgr = 0x4f000,
810 .hid_width = 5,
811 .parent_map = gcc_xo_gpll0_gpll1a_map,
812 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
813 .clkr.hw.init = &(struct clk_init_data){
814 .name = "csi1phytimer_clk_src",
815 .parent_names = gcc_xo_gpll0_gpll1a,
816 .num_parents = 3,
817 .ops = &clk_rcg2_ops,
818 },
819};
820
821static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
822 F(160000000, P_GPLL0, 5, 0, 0),
823 F(320000000, P_GPLL0, 2.5, 0, 0),
824 F(465000000, P_GPLL2, 2, 0, 0),
825 { }
826};
827
828static struct clk_rcg2 cpp_clk_src = {
829 .cmd_rcgr = 0x58018,
830 .hid_width = 5,
831 .parent_map = gcc_xo_gpll0_gpll2_map,
832 .freq_tbl = ftbl_gcc_camss_cpp_clk,
833 .clkr.hw.init = &(struct clk_init_data){
834 .name = "cpp_clk_src",
835 .parent_names = gcc_xo_gpll0_gpll2,
836 .num_parents = 3,
837 .ops = &clk_rcg2_ops,
838 },
839};
840
841static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
842 F(50000000, P_GPLL0, 16, 0, 0),
843 F(80000000, P_GPLL0, 10, 0, 0),
844 F(100000000, P_GPLL0, 8, 0, 0),
845 F(160000000, P_GPLL0, 5, 0, 0),
846 { }
847};
848
849static struct clk_rcg2 crypto_clk_src = {
850 .cmd_rcgr = 0x16004,
851 .hid_width = 5,
852 .parent_map = gcc_xo_gpll0_map,
853 .freq_tbl = ftbl_gcc_crypto_clk,
854 .clkr.hw.init = &(struct clk_init_data){
855 .name = "crypto_clk_src",
856 .parent_names = gcc_xo_gpll0,
857 .num_parents = 2,
858 .ops = &clk_rcg2_ops,
859 },
860};
861
862static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
863 F(19200000, P_XO, 1, 0, 0),
864 { }
865};
866
867static struct clk_rcg2 gp1_clk_src = {
868 .cmd_rcgr = 0x08004,
869 .mnd_width = 8,
870 .hid_width = 5,
871 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
872 .freq_tbl = ftbl_gcc_gp1_3_clk,
873 .clkr.hw.init = &(struct clk_init_data){
874 .name = "gp1_clk_src",
875 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
876 .num_parents = 3,
877 .ops = &clk_rcg2_ops,
878 },
879};
880
881static struct clk_rcg2 gp2_clk_src = {
882 .cmd_rcgr = 0x09004,
883 .mnd_width = 8,
884 .hid_width = 5,
885 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
886 .freq_tbl = ftbl_gcc_gp1_3_clk,
887 .clkr.hw.init = &(struct clk_init_data){
888 .name = "gp2_clk_src",
889 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
890 .num_parents = 3,
891 .ops = &clk_rcg2_ops,
892 },
893};
894
895static struct clk_rcg2 gp3_clk_src = {
896 .cmd_rcgr = 0x0a004,
897 .mnd_width = 8,
898 .hid_width = 5,
899 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
900 .freq_tbl = ftbl_gcc_gp1_3_clk,
901 .clkr.hw.init = &(struct clk_init_data){
902 .name = "gp3_clk_src",
903 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
904 .num_parents = 3,
905 .ops = &clk_rcg2_ops,
906 },
907};
908
909static struct freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
910 { .src = P_DSI0_PHYPLL_BYTE },
911 { }
912};
913
914static struct clk_rcg2 byte0_clk_src = {
915 .cmd_rcgr = 0x4d044,
916 .hid_width = 5,
917 .parent_map = gcc_xo_gpll0a_dsibyte_map,
918 .freq_tbl = ftbl_gcc_mdss_byte0_clk,
919 .clkr.hw.init = &(struct clk_init_data){
920 .name = "byte0_clk_src",
921 .parent_names = gcc_xo_gpll0a_dsibyte,
922 .num_parents = 3,
923 .ops = &clk_byte_ops,
924 .flags = CLK_SET_RATE_PARENT,
925 },
926};
927
928static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
929 F(19200000, P_XO, 1, 0, 0),
930 { }
931};
932
933static struct clk_rcg2 esc0_clk_src = {
934 .cmd_rcgr = 0x4d05c,
935 .hid_width = 5,
936 .parent_map = gcc_xo_dsibyte_map,
937 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "esc0_clk_src",
940 .parent_names = gcc_xo_dsibyte,
941 .num_parents = 2,
942 .ops = &clk_rcg2_ops,
943 },
944};
945
946static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
947 F(50000000, P_GPLL0, 16, 0, 0),
948 F(80000000, P_GPLL0, 10, 0, 0),
949 F(100000000, P_GPLL0, 8, 0, 0),
950 F(160000000, P_GPLL0, 5, 0, 0),
951 F(177780000, P_GPLL0, 4.5, 0, 0),
952 F(200000000, P_GPLL0, 4, 0, 0),
953 F(266670000, P_GPLL0, 3, 0, 0),
954 F(320000000, P_GPLL0, 2.5, 0, 0),
955 { }
956};
957
958static struct clk_rcg2 mdp_clk_src = {
959 .cmd_rcgr = 0x4d014,
960 .hid_width = 5,
961 .parent_map = gcc_xo_gpll0_dsiphy_map,
962 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
963 .clkr.hw.init = &(struct clk_init_data){
964 .name = "mdp_clk_src",
965 .parent_names = gcc_xo_gpll0_dsiphy,
966 .num_parents = 3,
967 .ops = &clk_rcg2_ops,
968 },
969};
970
971static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
972 { .src = P_DSI0_PHYPLL_DSI },
973 { }
974};
975
976static struct clk_rcg2 pclk0_clk_src = {
977 .cmd_rcgr = 0x4d000,
978 .mnd_width = 8,
979 .hid_width = 5,
980 .parent_map = gcc_xo_gpll0a_dsiphy_map,
981 .freq_tbl = ftbl_gcc_mdss_pclk,
982 .clkr.hw.init = &(struct clk_init_data){
983 .name = "pclk0_clk_src",
984 .parent_names = gcc_xo_gpll0a_dsiphy,
985 .num_parents = 3,
986 .ops = &clk_pixel_ops,
987 .flags = CLK_SET_RATE_PARENT,
988 },
989};
990
991static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
992 F(19200000, P_XO, 1, 0, 0),
993 { }
994};
995
996static struct clk_rcg2 vsync_clk_src = {
997 .cmd_rcgr = 0x4d02c,
998 .hid_width = 5,
999 .parent_map = gcc_xo_gpll0a_map,
1000 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1001 .clkr.hw.init = &(struct clk_init_data){
1002 .name = "vsync_clk_src",
1003 .parent_names = gcc_xo_gpll0a,
1004 .num_parents = 2,
1005 .ops = &clk_rcg2_ops,
1006 },
1007};
1008
1009static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1010 F(64000000, P_GPLL0, 12.5, 0, 0),
1011 { }
1012};
1013
1014static struct clk_rcg2 pdm2_clk_src = {
1015 .cmd_rcgr = 0x44010,
1016 .hid_width = 5,
1017 .parent_map = gcc_xo_gpll0_map,
1018 .freq_tbl = ftbl_gcc_pdm2_clk,
1019 .clkr.hw.init = &(struct clk_init_data){
1020 .name = "pdm2_clk_src",
1021 .parent_names = gcc_xo_gpll0,
1022 .num_parents = 2,
1023 .ops = &clk_rcg2_ops,
1024 },
1025};
1026
1027static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1028 F(144000, P_XO, 16, 3, 25),
1029 F(400000, P_XO, 12, 1, 4),
1030 F(20000000, P_GPLL0, 10, 1, 4),
1031 F(25000000, P_GPLL0, 16, 1, 2),
1032 F(50000000, P_GPLL0, 16, 0, 0),
1033 F(100000000, P_GPLL0, 8, 0, 0),
1034 F(177770000, P_GPLL0, 4.5, 0, 0),
1035 { }
1036};
1037
1038static struct clk_rcg2 sdcc1_apps_clk_src = {
1039 .cmd_rcgr = 0x42004,
1040 .mnd_width = 8,
1041 .hid_width = 5,
1042 .parent_map = gcc_xo_gpll0_map,
1043 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1044 .clkr.hw.init = &(struct clk_init_data){
1045 .name = "sdcc1_apps_clk_src",
1046 .parent_names = gcc_xo_gpll0,
1047 .num_parents = 2,
1048 .ops = &clk_rcg2_ops,
1049 },
1050};
1051
1052static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1053 F(144000, P_XO, 16, 3, 25),
1054 F(400000, P_XO, 12, 1, 4),
1055 F(20000000, P_GPLL0, 10, 1, 4),
1056 F(25000000, P_GPLL0, 16, 1, 2),
1057 F(50000000, P_GPLL0, 16, 0, 0),
1058 F(100000000, P_GPLL0, 8, 0, 0),
1059 F(200000000, P_GPLL0, 4, 0, 0),
1060 { }
1061};
1062
1063static struct clk_rcg2 sdcc2_apps_clk_src = {
1064 .cmd_rcgr = 0x43004,
1065 .mnd_width = 8,
1066 .hid_width = 5,
1067 .parent_map = gcc_xo_gpll0_map,
1068 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1069 .clkr.hw.init = &(struct clk_init_data){
1070 .name = "sdcc2_apps_clk_src",
1071 .parent_names = gcc_xo_gpll0,
1072 .num_parents = 2,
1073 .ops = &clk_rcg2_ops,
1074 },
1075};
1076
1077static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1078 F(155000000, P_GPLL2, 6, 0, 0),
1079 F(310000000, P_GPLL2, 3, 0, 0),
1080 F(400000000, P_GPLL0, 2, 0, 0),
1081 { }
1082};
1083
1084static struct clk_rcg2 apss_tcu_clk_src = {
1085 .cmd_rcgr = 0x1207c,
1086 .hid_width = 5,
1087 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1088 .freq_tbl = ftbl_gcc_apss_tcu_clk,
1089 .clkr.hw.init = &(struct clk_init_data){
1090 .name = "apss_tcu_clk_src",
1091 .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
1092 .num_parents = 4,
1093 .ops = &clk_rcg2_ops,
1094 },
1095};
1096
1097static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1098 F(80000000, P_GPLL0, 10, 0, 0),
1099 { }
1100};
1101
1102static struct clk_rcg2 usb_hs_system_clk_src = {
1103 .cmd_rcgr = 0x41010,
1104 .hid_width = 5,
1105 .parent_map = gcc_xo_gpll0_map,
1106 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1107 .clkr.hw.init = &(struct clk_init_data){
1108 .name = "usb_hs_system_clk_src",
1109 .parent_names = gcc_xo_gpll0,
1110 .num_parents = 2,
1111 .ops = &clk_rcg2_ops,
1112 },
1113};
1114
1115static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1116 F(100000000, P_GPLL0, 8, 0, 0),
1117 F(160000000, P_GPLL0, 5, 0, 0),
1118 F(228570000, P_GPLL0, 5, 0, 0),
1119 { }
1120};
1121
1122static struct clk_rcg2 vcodec0_clk_src = {
1123 .cmd_rcgr = 0x4C000,
1124 .mnd_width = 8,
1125 .hid_width = 5,
1126 .parent_map = gcc_xo_gpll0_map,
1127 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1128 .clkr.hw.init = &(struct clk_init_data){
1129 .name = "vcodec0_clk_src",
1130 .parent_names = gcc_xo_gpll0,
1131 .num_parents = 2,
1132 .ops = &clk_rcg2_ops,
1133 },
1134};
1135
1136static struct clk_branch gcc_blsp1_ahb_clk = {
1137 .halt_reg = 0x01008,
1138 .halt_check = BRANCH_HALT_VOTED,
1139 .clkr = {
1140 .enable_reg = 0x45004,
1141 .enable_mask = BIT(10),
1142 .hw.init = &(struct clk_init_data){
1143 .name = "gcc_blsp1_ahb_clk",
1144 .parent_names = (const char *[]){
1145 "pcnoc_bfdcd_clk_src",
1146 },
1147 .num_parents = 1,
1148 .ops = &clk_branch2_ops,
1149 },
1150 },
1151};
1152
1153static struct clk_branch gcc_blsp1_sleep_clk = {
1154 .halt_reg = 0x01004,
1155 .clkr = {
1156 .enable_reg = 0x01004,
1157 .enable_mask = BIT(0),
1158 .hw.init = &(struct clk_init_data){
1159 .name = "gcc_blsp1_sleep_clk",
1160 .parent_names = (const char *[]){
1161 "sleep_clk_src",
1162 },
1163 .num_parents = 1,
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch2_ops,
1166 },
1167 },
1168};
1169
1170static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1171 .halt_reg = 0x02008,
1172 .clkr = {
1173 .enable_reg = 0x02008,
1174 .enable_mask = BIT(0),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1177 .parent_names = (const char *[]){
1178 "blsp1_qup1_i2c_apps_clk_src",
1179 },
1180 .num_parents = 1,
1181 .flags = CLK_SET_RATE_PARENT,
1182 .ops = &clk_branch2_ops,
1183 },
1184 },
1185};
1186
1187static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1188 .halt_reg = 0x02004,
1189 .clkr = {
1190 .enable_reg = 0x02004,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "gcc_blsp1_qup1_spi_apps_clk",
1194 .parent_names = (const char *[]){
1195 "blsp1_qup1_spi_apps_clk_src",
1196 },
1197 .num_parents = 1,
1198 .flags = CLK_SET_RATE_PARENT,
1199 .ops = &clk_branch2_ops,
1200 },
1201 },
1202};
1203
1204static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1205 .halt_reg = 0x03010,
1206 .clkr = {
1207 .enable_reg = 0x03010,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1211 .parent_names = (const char *[]){
1212 "blsp1_qup2_i2c_apps_clk_src",
1213 },
1214 .num_parents = 1,
1215 .flags = CLK_SET_RATE_PARENT,
1216 .ops = &clk_branch2_ops,
1217 },
1218 },
1219};
1220
1221static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1222 .halt_reg = 0x0300c,
1223 .clkr = {
1224 .enable_reg = 0x0300c,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data){
1227 .name = "gcc_blsp1_qup2_spi_apps_clk",
1228 .parent_names = (const char *[]){
1229 "blsp1_qup2_spi_apps_clk_src",
1230 },
1231 .num_parents = 1,
1232 .flags = CLK_SET_RATE_PARENT,
1233 .ops = &clk_branch2_ops,
1234 },
1235 },
1236};
1237
1238static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1239 .halt_reg = 0x04020,
1240 .clkr = {
1241 .enable_reg = 0x04020,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1245 .parent_names = (const char *[]){
1246 "blsp1_qup3_i2c_apps_clk_src",
1247 },
1248 .num_parents = 1,
1249 .flags = CLK_SET_RATE_PARENT,
1250 .ops = &clk_branch2_ops,
1251 },
1252 },
1253};
1254
1255static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1256 .halt_reg = 0x0401c,
1257 .clkr = {
1258 .enable_reg = 0x0401c,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "gcc_blsp1_qup3_spi_apps_clk",
1262 .parent_names = (const char *[]){
1263 "blsp1_qup3_spi_apps_clk_src",
1264 },
1265 .num_parents = 1,
1266 .flags = CLK_SET_RATE_PARENT,
1267 .ops = &clk_branch2_ops,
1268 },
1269 },
1270};
1271
1272static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1273 .halt_reg = 0x05020,
1274 .clkr = {
1275 .enable_reg = 0x05020,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1279 .parent_names = (const char *[]){
1280 "blsp1_qup4_i2c_apps_clk_src",
1281 },
1282 .num_parents = 1,
1283 .flags = CLK_SET_RATE_PARENT,
1284 .ops = &clk_branch2_ops,
1285 },
1286 },
1287};
1288
1289static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1290 .halt_reg = 0x0501c,
1291 .clkr = {
1292 .enable_reg = 0x0501c,
1293 .enable_mask = BIT(0),
1294 .hw.init = &(struct clk_init_data){
1295 .name = "gcc_blsp1_qup4_spi_apps_clk",
1296 .parent_names = (const char *[]){
1297 "blsp1_qup4_spi_apps_clk_src",
1298 },
1299 .num_parents = 1,
1300 .flags = CLK_SET_RATE_PARENT,
1301 .ops = &clk_branch2_ops,
1302 },
1303 },
1304};
1305
1306static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1307 .halt_reg = 0x06020,
1308 .clkr = {
1309 .enable_reg = 0x06020,
1310 .enable_mask = BIT(0),
1311 .hw.init = &(struct clk_init_data){
1312 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1313 .parent_names = (const char *[]){
1314 "blsp1_qup5_i2c_apps_clk_src",
1315 },
1316 .num_parents = 1,
1317 .flags = CLK_SET_RATE_PARENT,
1318 .ops = &clk_branch2_ops,
1319 },
1320 },
1321};
1322
1323static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1324 .halt_reg = 0x0601c,
1325 .clkr = {
1326 .enable_reg = 0x0601c,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(struct clk_init_data){
1329 .name = "gcc_blsp1_qup5_spi_apps_clk",
1330 .parent_names = (const char *[]){
1331 "blsp1_qup5_spi_apps_clk_src",
1332 },
1333 .num_parents = 1,
1334 .flags = CLK_SET_RATE_PARENT,
1335 .ops = &clk_branch2_ops,
1336 },
1337 },
1338};
1339
1340static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1341 .halt_reg = 0x07020,
1342 .clkr = {
1343 .enable_reg = 0x07020,
1344 .enable_mask = BIT(0),
1345 .hw.init = &(struct clk_init_data){
1346 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1347 .parent_names = (const char *[]){
1348 "blsp1_qup6_i2c_apps_clk_src",
1349 },
1350 .num_parents = 1,
1351 .flags = CLK_SET_RATE_PARENT,
1352 .ops = &clk_branch2_ops,
1353 },
1354 },
1355};
1356
1357static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1358 .halt_reg = 0x0701c,
1359 .clkr = {
1360 .enable_reg = 0x0701c,
1361 .enable_mask = BIT(0),
1362 .hw.init = &(struct clk_init_data){
1363 .name = "gcc_blsp1_qup6_spi_apps_clk",
1364 .parent_names = (const char *[]){
1365 "blsp1_qup6_spi_apps_clk_src",
1366 },
1367 .num_parents = 1,
1368 .flags = CLK_SET_RATE_PARENT,
1369 .ops = &clk_branch2_ops,
1370 },
1371 },
1372};
1373
1374static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1375 .halt_reg = 0x0203c,
1376 .clkr = {
1377 .enable_reg = 0x0203c,
1378 .enable_mask = BIT(0),
1379 .hw.init = &(struct clk_init_data){
1380 .name = "gcc_blsp1_uart1_apps_clk",
1381 .parent_names = (const char *[]){
1382 "blsp1_uart1_apps_clk_src",
1383 },
1384 .num_parents = 1,
1385 .flags = CLK_SET_RATE_PARENT,
1386 .ops = &clk_branch2_ops,
1387 },
1388 },
1389};
1390
1391static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1392 .halt_reg = 0x0302c,
1393 .clkr = {
1394 .enable_reg = 0x0302c,
1395 .enable_mask = BIT(0),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "gcc_blsp1_uart2_apps_clk",
1398 .parent_names = (const char *[]){
1399 "blsp1_uart2_apps_clk_src",
1400 },
1401 .num_parents = 1,
1402 .flags = CLK_SET_RATE_PARENT,
1403 .ops = &clk_branch2_ops,
1404 },
1405 },
1406};
1407
1408static struct clk_branch gcc_boot_rom_ahb_clk = {
1409 .halt_reg = 0x1300c,
1410 .halt_check = BRANCH_HALT_VOTED,
1411 .clkr = {
1412 .enable_reg = 0x45004,
1413 .enable_mask = BIT(7),
1414 .hw.init = &(struct clk_init_data){
1415 .name = "gcc_boot_rom_ahb_clk",
1416 .parent_names = (const char *[]){
1417 "pcnoc_bfdcd_clk_src",
1418 },
1419 .num_parents = 1,
1420 .ops = &clk_branch2_ops,
1421 },
1422 },
1423};
1424
1425static struct clk_branch gcc_camss_cci_ahb_clk = {
1426 .halt_reg = 0x5101c,
1427 .clkr = {
1428 .enable_reg = 0x5101c,
1429 .enable_mask = BIT(0),
1430 .hw.init = &(struct clk_init_data){
1431 .name = "gcc_camss_cci_ahb_clk",
1432 .parent_names = (const char *[]){
1433 "camss_ahb_clk_src",
1434 },
1435 .num_parents = 1,
1436 .flags = CLK_SET_RATE_PARENT,
1437 .ops = &clk_branch2_ops,
1438 },
1439 },
1440};
1441
1442static struct clk_branch gcc_camss_cci_clk = {
1443 .halt_reg = 0x51018,
1444 .clkr = {
1445 .enable_reg = 0x51018,
1446 .enable_mask = BIT(0),
1447 .hw.init = &(struct clk_init_data){
1448 .name = "gcc_camss_cci_clk",
1449 .parent_names = (const char *[]){
1450 "cci_clk_src",
1451 },
1452 .num_parents = 1,
1453 .flags = CLK_SET_RATE_PARENT,
1454 .ops = &clk_branch2_ops,
1455 },
1456 },
1457};
1458
1459static struct clk_branch gcc_camss_csi0_ahb_clk = {
1460 .halt_reg = 0x4e040,
1461 .clkr = {
1462 .enable_reg = 0x4e040,
1463 .enable_mask = BIT(0),
1464 .hw.init = &(struct clk_init_data){
1465 .name = "gcc_camss_csi0_ahb_clk",
1466 .parent_names = (const char *[]){
1467 "camss_ahb_clk_src",
1468 },
1469 .num_parents = 1,
1470 .flags = CLK_SET_RATE_PARENT,
1471 .ops = &clk_branch2_ops,
1472 },
1473 },
1474};
1475
1476static struct clk_branch gcc_camss_csi0_clk = {
1477 .halt_reg = 0x4e03c,
1478 .clkr = {
1479 .enable_reg = 0x4e03c,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "gcc_camss_csi0_clk",
1483 .parent_names = (const char *[]){
1484 "csi0_clk_src",
1485 },
1486 .num_parents = 1,
1487 .flags = CLK_SET_RATE_PARENT,
1488 .ops = &clk_branch2_ops,
1489 },
1490 },
1491};
1492
1493static struct clk_branch gcc_camss_csi0phy_clk = {
1494 .halt_reg = 0x4e048,
1495 .clkr = {
1496 .enable_reg = 0x4e048,
1497 .enable_mask = BIT(0),
1498 .hw.init = &(struct clk_init_data){
1499 .name = "gcc_camss_csi0phy_clk",
1500 .parent_names = (const char *[]){
1501 "csi0_clk_src",
1502 },
1503 .num_parents = 1,
1504 .flags = CLK_SET_RATE_PARENT,
1505 .ops = &clk_branch2_ops,
1506 },
1507 },
1508};
1509
1510static struct clk_branch gcc_camss_csi0pix_clk = {
1511 .halt_reg = 0x4e058,
1512 .clkr = {
1513 .enable_reg = 0x4e058,
1514 .enable_mask = BIT(0),
1515 .hw.init = &(struct clk_init_data){
1516 .name = "gcc_camss_csi0pix_clk",
1517 .parent_names = (const char *[]){
1518 "csi0_clk_src",
1519 },
1520 .num_parents = 1,
1521 .flags = CLK_SET_RATE_PARENT,
1522 .ops = &clk_branch2_ops,
1523 },
1524 },
1525};
1526
1527static struct clk_branch gcc_camss_csi0rdi_clk = {
1528 .halt_reg = 0x4e050,
1529 .clkr = {
1530 .enable_reg = 0x4e050,
1531 .enable_mask = BIT(0),
1532 .hw.init = &(struct clk_init_data){
1533 .name = "gcc_camss_csi0rdi_clk",
1534 .parent_names = (const char *[]){
1535 "csi0_clk_src",
1536 },
1537 .num_parents = 1,
1538 .flags = CLK_SET_RATE_PARENT,
1539 .ops = &clk_branch2_ops,
1540 },
1541 },
1542};
1543
1544static struct clk_branch gcc_camss_csi1_ahb_clk = {
1545 .halt_reg = 0x4f040,
1546 .clkr = {
1547 .enable_reg = 0x4f040,
1548 .enable_mask = BIT(0),
1549 .hw.init = &(struct clk_init_data){
1550 .name = "gcc_camss_csi1_ahb_clk",
1551 .parent_names = (const char *[]){
1552 "camss_ahb_clk_src",
1553 },
1554 .num_parents = 1,
1555 .flags = CLK_SET_RATE_PARENT,
1556 .ops = &clk_branch2_ops,
1557 },
1558 },
1559};
1560
1561static struct clk_branch gcc_camss_csi1_clk = {
1562 .halt_reg = 0x4f03c,
1563 .clkr = {
1564 .enable_reg = 0x4f03c,
1565 .enable_mask = BIT(0),
1566 .hw.init = &(struct clk_init_data){
1567 .name = "gcc_camss_csi1_clk",
1568 .parent_names = (const char *[]){
1569 "csi1_clk_src",
1570 },
1571 .num_parents = 1,
1572 .flags = CLK_SET_RATE_PARENT,
1573 .ops = &clk_branch2_ops,
1574 },
1575 },
1576};
1577
1578static struct clk_branch gcc_camss_csi1phy_clk = {
1579 .halt_reg = 0x4f048,
1580 .clkr = {
1581 .enable_reg = 0x4f048,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "gcc_camss_csi1phy_clk",
1585 .parent_names = (const char *[]){
1586 "csi1_clk_src",
1587 },
1588 .num_parents = 1,
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1591 },
1592 },
1593};
1594
1595static struct clk_branch gcc_camss_csi1pix_clk = {
1596 .halt_reg = 0x4f058,
1597 .clkr = {
1598 .enable_reg = 0x4f058,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "gcc_camss_csi1pix_clk",
1602 .parent_names = (const char *[]){
1603 "csi1_clk_src",
1604 },
1605 .num_parents = 1,
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1608 },
1609 },
1610};
1611
1612static struct clk_branch gcc_camss_csi1rdi_clk = {
1613 .halt_reg = 0x4f050,
1614 .clkr = {
1615 .enable_reg = 0x4f050,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "gcc_camss_csi1rdi_clk",
1619 .parent_names = (const char *[]){
1620 "csi1_clk_src",
1621 },
1622 .num_parents = 1,
1623 .flags = CLK_SET_RATE_PARENT,
1624 .ops = &clk_branch2_ops,
1625 },
1626 },
1627};
1628
1629static struct clk_branch gcc_camss_csi_vfe0_clk = {
1630 .halt_reg = 0x58050,
1631 .clkr = {
1632 .enable_reg = 0x58050,
1633 .enable_mask = BIT(0),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "gcc_camss_csi_vfe0_clk",
1636 .parent_names = (const char *[]){
1637 "vfe0_clk_src",
1638 },
1639 .num_parents = 1,
1640 .flags = CLK_SET_RATE_PARENT,
1641 .ops = &clk_branch2_ops,
1642 },
1643 },
1644};
1645
1646static struct clk_branch gcc_camss_gp0_clk = {
1647 .halt_reg = 0x54018,
1648 .clkr = {
1649 .enable_reg = 0x54018,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_camss_gp0_clk",
1653 .parent_names = (const char *[]){
1654 "camss_gp0_clk_src",
1655 },
1656 .num_parents = 1,
1657 .flags = CLK_SET_RATE_PARENT,
1658 .ops = &clk_branch2_ops,
1659 },
1660 },
1661};
1662
1663static struct clk_branch gcc_camss_gp1_clk = {
1664 .halt_reg = 0x55018,
1665 .clkr = {
1666 .enable_reg = 0x55018,
1667 .enable_mask = BIT(0),
1668 .hw.init = &(struct clk_init_data){
1669 .name = "gcc_camss_gp1_clk",
1670 .parent_names = (const char *[]){
1671 "camss_gp1_clk_src",
1672 },
1673 .num_parents = 1,
1674 .flags = CLK_SET_RATE_PARENT,
1675 .ops = &clk_branch2_ops,
1676 },
1677 },
1678};
1679
1680static struct clk_branch gcc_camss_ispif_ahb_clk = {
1681 .halt_reg = 0x50004,
1682 .clkr = {
1683 .enable_reg = 0x50004,
1684 .enable_mask = BIT(0),
1685 .hw.init = &(struct clk_init_data){
1686 .name = "gcc_camss_ispif_ahb_clk",
1687 .parent_names = (const char *[]){
1688 "camss_ahb_clk_src",
1689 },
1690 .num_parents = 1,
1691 .flags = CLK_SET_RATE_PARENT,
1692 .ops = &clk_branch2_ops,
1693 },
1694 },
1695};
1696
1697static struct clk_branch gcc_camss_jpeg0_clk = {
1698 .halt_reg = 0x57020,
1699 .clkr = {
1700 .enable_reg = 0x57020,
1701 .enable_mask = BIT(0),
1702 .hw.init = &(struct clk_init_data){
1703 .name = "gcc_camss_jpeg0_clk",
1704 .parent_names = (const char *[]){
1705 "jpeg0_clk_src",
1706 },
1707 .num_parents = 1,
1708 .flags = CLK_SET_RATE_PARENT,
1709 .ops = &clk_branch2_ops,
1710 },
1711 },
1712};
1713
1714static struct clk_branch gcc_camss_jpeg_ahb_clk = {
1715 .halt_reg = 0x57024,
1716 .clkr = {
1717 .enable_reg = 0x57024,
1718 .enable_mask = BIT(0),
1719 .hw.init = &(struct clk_init_data){
1720 .name = "gcc_camss_jpeg_ahb_clk",
1721 .parent_names = (const char *[]){
1722 "camss_ahb_clk_src",
1723 },
1724 .num_parents = 1,
1725 .flags = CLK_SET_RATE_PARENT,
1726 .ops = &clk_branch2_ops,
1727 },
1728 },
1729};
1730
1731static struct clk_branch gcc_camss_jpeg_axi_clk = {
1732 .halt_reg = 0x57028,
1733 .clkr = {
1734 .enable_reg = 0x57028,
1735 .enable_mask = BIT(0),
1736 .hw.init = &(struct clk_init_data){
1737 .name = "gcc_camss_jpeg_axi_clk",
1738 .parent_names = (const char *[]){
1739 "system_noc_bfdcd_clk_src",
1740 },
1741 .num_parents = 1,
1742 .flags = CLK_SET_RATE_PARENT,
1743 .ops = &clk_branch2_ops,
1744 },
1745 },
1746};
1747
1748static struct clk_branch gcc_camss_mclk0_clk = {
1749 .halt_reg = 0x52018,
1750 .clkr = {
1751 .enable_reg = 0x52018,
1752 .enable_mask = BIT(0),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "gcc_camss_mclk0_clk",
1755 .parent_names = (const char *[]){
1756 "mclk0_clk_src",
1757 },
1758 .num_parents = 1,
1759 .flags = CLK_SET_RATE_PARENT,
1760 .ops = &clk_branch2_ops,
1761 },
1762 },
1763};
1764
1765static struct clk_branch gcc_camss_mclk1_clk = {
1766 .halt_reg = 0x53018,
1767 .clkr = {
1768 .enable_reg = 0x53018,
1769 .enable_mask = BIT(0),
1770 .hw.init = &(struct clk_init_data){
1771 .name = "gcc_camss_mclk1_clk",
1772 .parent_names = (const char *[]){
1773 "mclk1_clk_src",
1774 },
1775 .num_parents = 1,
1776 .flags = CLK_SET_RATE_PARENT,
1777 .ops = &clk_branch2_ops,
1778 },
1779 },
1780};
1781
1782static struct clk_branch gcc_camss_micro_ahb_clk = {
1783 .halt_reg = 0x5600c,
1784 .clkr = {
1785 .enable_reg = 0x5600c,
1786 .enable_mask = BIT(0),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "gcc_camss_micro_ahb_clk",
1789 .parent_names = (const char *[]){
1790 "camss_ahb_clk_src",
1791 },
1792 .num_parents = 1,
1793 .flags = CLK_SET_RATE_PARENT,
1794 .ops = &clk_branch2_ops,
1795 },
1796 },
1797};
1798
1799static struct clk_branch gcc_camss_csi0phytimer_clk = {
1800 .halt_reg = 0x4e01c,
1801 .clkr = {
1802 .enable_reg = 0x4e01c,
1803 .enable_mask = BIT(0),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "gcc_camss_csi0phytimer_clk",
1806 .parent_names = (const char *[]){
1807 "csi0phytimer_clk_src",
1808 },
1809 .num_parents = 1,
1810 .flags = CLK_SET_RATE_PARENT,
1811 .ops = &clk_branch2_ops,
1812 },
1813 },
1814};
1815
1816static struct clk_branch gcc_camss_csi1phytimer_clk = {
1817 .halt_reg = 0x4f01c,
1818 .clkr = {
1819 .enable_reg = 0x4f01c,
1820 .enable_mask = BIT(0),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "gcc_camss_csi1phytimer_clk",
1823 .parent_names = (const char *[]){
1824 "csi1phytimer_clk_src",
1825 },
1826 .num_parents = 1,
1827 .flags = CLK_SET_RATE_PARENT,
1828 .ops = &clk_branch2_ops,
1829 },
1830 },
1831};
1832
1833static struct clk_branch gcc_camss_ahb_clk = {
1834 .halt_reg = 0x5a014,
1835 .clkr = {
1836 .enable_reg = 0x5a014,
1837 .enable_mask = BIT(0),
1838 .hw.init = &(struct clk_init_data){
1839 .name = "gcc_camss_ahb_clk",
1840 .parent_names = (const char *[]){
1841 "camss_ahb_clk_src",
1842 },
1843 .num_parents = 1,
1844 .flags = CLK_SET_RATE_PARENT,
1845 .ops = &clk_branch2_ops,
1846 },
1847 },
1848};
1849
1850static struct clk_branch gcc_camss_top_ahb_clk = {
1851 .halt_reg = 0x56004,
1852 .clkr = {
1853 .enable_reg = 0x56004,
1854 .enable_mask = BIT(0),
1855 .hw.init = &(struct clk_init_data){
1856 .name = "gcc_camss_top_ahb_clk",
1857 .parent_names = (const char *[]){
1858 "pcnoc_bfdcd_clk_src",
1859 },
1860 .num_parents = 1,
1861 .flags = CLK_SET_RATE_PARENT,
1862 .ops = &clk_branch2_ops,
1863 },
1864 },
1865};
1866
1867static struct clk_branch gcc_camss_cpp_ahb_clk = {
1868 .halt_reg = 0x58040,
1869 .clkr = {
1870 .enable_reg = 0x58040,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "gcc_camss_cpp_ahb_clk",
1874 .parent_names = (const char *[]){
1875 "camss_ahb_clk_src",
1876 },
1877 .num_parents = 1,
1878 .flags = CLK_SET_RATE_PARENT,
1879 .ops = &clk_branch2_ops,
1880 },
1881 },
1882};
1883
1884static struct clk_branch gcc_camss_cpp_clk = {
1885 .halt_reg = 0x5803c,
1886 .clkr = {
1887 .enable_reg = 0x5803c,
1888 .enable_mask = BIT(0),
1889 .hw.init = &(struct clk_init_data){
1890 .name = "gcc_camss_cpp_clk",
1891 .parent_names = (const char *[]){
1892 "cpp_clk_src",
1893 },
1894 .num_parents = 1,
1895 .flags = CLK_SET_RATE_PARENT,
1896 .ops = &clk_branch2_ops,
1897 },
1898 },
1899};
1900
1901static struct clk_branch gcc_camss_vfe0_clk = {
1902 .halt_reg = 0x58038,
1903 .clkr = {
1904 .enable_reg = 0x58038,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "gcc_camss_vfe0_clk",
1908 .parent_names = (const char *[]){
1909 "vfe0_clk_src",
1910 },
1911 .num_parents = 1,
1912 .flags = CLK_SET_RATE_PARENT,
1913 .ops = &clk_branch2_ops,
1914 },
1915 },
1916};
1917
1918static struct clk_branch gcc_camss_vfe_ahb_clk = {
1919 .halt_reg = 0x58044,
1920 .clkr = {
1921 .enable_reg = 0x58044,
1922 .enable_mask = BIT(0),
1923 .hw.init = &(struct clk_init_data){
1924 .name = "gcc_camss_vfe_ahb_clk",
1925 .parent_names = (const char *[]){
1926 "camss_ahb_clk_src",
1927 },
1928 .num_parents = 1,
1929 .flags = CLK_SET_RATE_PARENT,
1930 .ops = &clk_branch2_ops,
1931 },
1932 },
1933};
1934
1935static struct clk_branch gcc_camss_vfe_axi_clk = {
1936 .halt_reg = 0x58048,
1937 .clkr = {
1938 .enable_reg = 0x58048,
1939 .enable_mask = BIT(0),
1940 .hw.init = &(struct clk_init_data){
1941 .name = "gcc_camss_vfe_axi_clk",
1942 .parent_names = (const char *[]){
1943 "system_noc_bfdcd_clk_src",
1944 },
1945 .num_parents = 1,
1946 .flags = CLK_SET_RATE_PARENT,
1947 .ops = &clk_branch2_ops,
1948 },
1949 },
1950};
1951
1952static struct clk_branch gcc_crypto_ahb_clk = {
1953 .halt_reg = 0x16024,
1954 .halt_check = BRANCH_HALT_VOTED,
1955 .clkr = {
1956 .enable_reg = 0x45004,
1957 .enable_mask = BIT(0),
1958 .hw.init = &(struct clk_init_data){
1959 .name = "gcc_crypto_ahb_clk",
1960 .parent_names = (const char *[]){
1961 "pcnoc_bfdcd_clk_src",
1962 },
1963 .num_parents = 1,
1964 .ops = &clk_branch2_ops,
1965 },
1966 },
1967};
1968
1969static struct clk_branch gcc_crypto_axi_clk = {
1970 .halt_reg = 0x16020,
1971 .halt_check = BRANCH_HALT_VOTED,
1972 .clkr = {
1973 .enable_reg = 0x45004,
1974 .enable_mask = BIT(1),
1975 .hw.init = &(struct clk_init_data){
1976 .name = "gcc_crypto_axi_clk",
1977 .parent_names = (const char *[]){
1978 "pcnoc_bfdcd_clk_src",
1979 },
1980 .num_parents = 1,
1981 .flags = CLK_SET_RATE_PARENT,
1982 .ops = &clk_branch2_ops,
1983 },
1984 },
1985};
1986
1987static struct clk_branch gcc_crypto_clk = {
1988 .halt_reg = 0x1601c,
1989 .halt_check = BRANCH_HALT_VOTED,
1990 .clkr = {
1991 .enable_reg = 0x45004,
1992 .enable_mask = BIT(2),
1993 .hw.init = &(struct clk_init_data){
1994 .name = "gcc_crypto_clk",
1995 .parent_names = (const char *[]){
1996 "crypto_clk_src",
1997 },
1998 .num_parents = 1,
1999 .ops = &clk_branch2_ops,
2000 },
2001 },
2002};
2003
2004static struct clk_branch gcc_oxili_gmem_clk = {
2005 .halt_reg = 0x59024,
2006 .clkr = {
2007 .enable_reg = 0x59024,
2008 .enable_mask = BIT(0),
2009 .hw.init = &(struct clk_init_data){
2010 .name = "gcc_oxili_gmem_clk",
2011 .parent_names = (const char *[]){
2012 "gfx3d_clk_src",
2013 },
2014 .num_parents = 1,
2015 .flags = CLK_SET_RATE_PARENT,
2016 .ops = &clk_branch2_ops,
2017 },
2018 },
2019};
2020
2021static struct clk_branch gcc_gp1_clk = {
2022 .halt_reg = 0x08000,
2023 .clkr = {
2024 .enable_reg = 0x08000,
2025 .enable_mask = BIT(0),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "gcc_gp1_clk",
2028 .parent_names = (const char *[]){
2029 "gp1_clk_src",
2030 },
2031 .num_parents = 1,
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch gcc_gp2_clk = {
2039 .halt_reg = 0x09000,
2040 .clkr = {
2041 .enable_reg = 0x09000,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(struct clk_init_data){
2044 .name = "gcc_gp2_clk",
2045 .parent_names = (const char *[]){
2046 "gp2_clk_src",
2047 },
2048 .num_parents = 1,
2049 .flags = CLK_SET_RATE_PARENT,
2050 .ops = &clk_branch2_ops,
2051 },
2052 },
2053};
2054
2055static struct clk_branch gcc_gp3_clk = {
2056 .halt_reg = 0x0a000,
2057 .clkr = {
2058 .enable_reg = 0x0a000,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data){
2061 .name = "gcc_gp3_clk",
2062 .parent_names = (const char *[]){
2063 "gp3_clk_src",
2064 },
2065 .num_parents = 1,
2066 .flags = CLK_SET_RATE_PARENT,
2067 .ops = &clk_branch2_ops,
2068 },
2069 },
2070};
2071
2072static struct clk_branch gcc_mdss_ahb_clk = {
2073 .halt_reg = 0x4d07c,
2074 .clkr = {
2075 .enable_reg = 0x4d07c,
2076 .enable_mask = BIT(0),
2077 .hw.init = &(struct clk_init_data){
2078 .name = "gcc_mdss_ahb_clk",
2079 .parent_names = (const char *[]){
2080 "pcnoc_bfdcd_clk_src",
2081 },
2082 .num_parents = 1,
2083 .flags = CLK_SET_RATE_PARENT,
2084 .ops = &clk_branch2_ops,
2085 },
2086 },
2087};
2088
2089static struct clk_branch gcc_mdss_axi_clk = {
2090 .halt_reg = 0x4d080,
2091 .clkr = {
2092 .enable_reg = 0x4d080,
2093 .enable_mask = BIT(0),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "gcc_mdss_axi_clk",
2096 .parent_names = (const char *[]){
2097 "system_noc_bfdcd_clk_src",
2098 },
2099 .num_parents = 1,
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_branch2_ops,
2102 },
2103 },
2104};
2105
2106static struct clk_branch gcc_mdss_byte0_clk = {
2107 .halt_reg = 0x4d094,
2108 .clkr = {
2109 .enable_reg = 0x4d094,
2110 .enable_mask = BIT(0),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "gcc_mdss_byte0_clk",
2113 .parent_names = (const char *[]){
2114 "byte0_clk_src",
2115 },
2116 .num_parents = 1,
2117 .flags = CLK_SET_RATE_PARENT,
2118 .ops = &clk_branch2_ops,
2119 },
2120 },
2121};
2122
2123static struct clk_branch gcc_mdss_esc0_clk = {
2124 .halt_reg = 0x4d098,
2125 .clkr = {
2126 .enable_reg = 0x4d098,
2127 .enable_mask = BIT(0),
2128 .hw.init = &(struct clk_init_data){
2129 .name = "gcc_mdss_esc0_clk",
2130 .parent_names = (const char *[]){
2131 "esc0_clk_src",
2132 },
2133 .num_parents = 1,
2134 .flags = CLK_SET_RATE_PARENT,
2135 .ops = &clk_branch2_ops,
2136 },
2137 },
2138};
2139
2140static struct clk_branch gcc_mdss_mdp_clk = {
2141 .halt_reg = 0x4D088,
2142 .clkr = {
2143 .enable_reg = 0x4D088,
2144 .enable_mask = BIT(0),
2145 .hw.init = &(struct clk_init_data){
2146 .name = "gcc_mdss_mdp_clk",
2147 .parent_names = (const char *[]){
2148 "mdp_clk_src",
2149 },
2150 .num_parents = 1,
2151 .flags = CLK_SET_RATE_PARENT,
2152 .ops = &clk_branch2_ops,
2153 },
2154 },
2155};
2156
2157static struct clk_branch gcc_mdss_pclk0_clk = {
2158 .halt_reg = 0x4d084,
2159 .clkr = {
2160 .enable_reg = 0x4d084,
2161 .enable_mask = BIT(0),
2162 .hw.init = &(struct clk_init_data){
2163 .name = "gcc_mdss_pclk0_clk",
2164 .parent_names = (const char *[]){
2165 "pclk0_clk_src",
2166 },
2167 .num_parents = 1,
2168 .flags = CLK_SET_RATE_PARENT,
2169 .ops = &clk_branch2_ops,
2170 },
2171 },
2172};
2173
2174static struct clk_branch gcc_mdss_vsync_clk = {
2175 .halt_reg = 0x4d090,
2176 .clkr = {
2177 .enable_reg = 0x4d090,
2178 .enable_mask = BIT(0),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "gcc_mdss_vsync_clk",
2181 .parent_names = (const char *[]){
2182 "vsync_clk_src",
2183 },
2184 .num_parents = 1,
2185 .flags = CLK_SET_RATE_PARENT,
2186 .ops = &clk_branch2_ops,
2187 },
2188 },
2189};
2190
2191static struct clk_branch gcc_mss_cfg_ahb_clk = {
2192 .halt_reg = 0x49000,
2193 .clkr = {
2194 .enable_reg = 0x49000,
2195 .enable_mask = BIT(0),
2196 .hw.init = &(struct clk_init_data){
2197 .name = "gcc_mss_cfg_ahb_clk",
2198 .parent_names = (const char *[]){
2199 "pcnoc_bfdcd_clk_src",
2200 },
2201 .num_parents = 1,
2202 .flags = CLK_SET_RATE_PARENT,
2203 .ops = &clk_branch2_ops,
2204 },
2205 },
2206};
2207
2208static struct clk_branch gcc_oxili_ahb_clk = {
2209 .halt_reg = 0x59028,
2210 .clkr = {
2211 .enable_reg = 0x59028,
2212 .enable_mask = BIT(0),
2213 .hw.init = &(struct clk_init_data){
2214 .name = "gcc_oxili_ahb_clk",
2215 .parent_names = (const char *[]){
2216 "pcnoc_bfdcd_clk_src",
2217 },
2218 .num_parents = 1,
2219 .flags = CLK_SET_RATE_PARENT,
2220 .ops = &clk_branch2_ops,
2221 },
2222 },
2223};
2224
2225static struct clk_branch gcc_oxili_gfx3d_clk = {
2226 .halt_reg = 0x59020,
2227 .clkr = {
2228 .enable_reg = 0x59020,
2229 .enable_mask = BIT(0),
2230 .hw.init = &(struct clk_init_data){
2231 .name = "gcc_oxili_gfx3d_clk",
2232 .parent_names = (const char *[]){
2233 "gfx3d_clk_src",
2234 },
2235 .num_parents = 1,
2236 .flags = CLK_SET_RATE_PARENT,
2237 .ops = &clk_branch2_ops,
2238 },
2239 },
2240};
2241
2242static struct clk_branch gcc_pdm2_clk = {
2243 .halt_reg = 0x4400c,
2244 .clkr = {
2245 .enable_reg = 0x4400c,
2246 .enable_mask = BIT(0),
2247 .hw.init = &(struct clk_init_data){
2248 .name = "gcc_pdm2_clk",
2249 .parent_names = (const char *[]){
2250 "pdm2_clk_src",
2251 },
2252 .num_parents = 1,
2253 .flags = CLK_SET_RATE_PARENT,
2254 .ops = &clk_branch2_ops,
2255 },
2256 },
2257};
2258
2259static struct clk_branch gcc_pdm_ahb_clk = {
2260 .halt_reg = 0x44004,
2261 .clkr = {
2262 .enable_reg = 0x44004,
2263 .enable_mask = BIT(0),
2264 .hw.init = &(struct clk_init_data){
2265 .name = "gcc_pdm_ahb_clk",
2266 .parent_names = (const char *[]){
2267 "pcnoc_bfdcd_clk_src",
2268 },
2269 .num_parents = 1,
2270 .flags = CLK_SET_RATE_PARENT,
2271 .ops = &clk_branch2_ops,
2272 },
2273 },
2274};
2275
2276static struct clk_branch gcc_prng_ahb_clk = {
2277 .halt_reg = 0x13004,
2278 .halt_check = BRANCH_HALT_VOTED,
2279 .clkr = {
2280 .enable_reg = 0x45004,
2281 .enable_mask = BIT(0),
2282 .hw.init = &(struct clk_init_data){
2283 .name = "gcc_prng_ahb_clk",
2284 .parent_names = (const char *[]){
2285 "pcnoc_bfdcd_clk_src",
2286 },
2287 .num_parents = 1,
2288 .ops = &clk_branch2_ops,
2289 },
2290 },
2291};
2292
2293static struct clk_branch gcc_sdcc1_ahb_clk = {
2294 .halt_reg = 0x4201c,
2295 .clkr = {
2296 .enable_reg = 0x4201c,
2297 .enable_mask = BIT(0),
2298 .hw.init = &(struct clk_init_data){
2299 .name = "gcc_sdcc1_ahb_clk",
2300 .parent_names = (const char *[]){
2301 "pcnoc_bfdcd_clk_src",
2302 },
2303 .num_parents = 1,
2304 .flags = CLK_SET_RATE_PARENT,
2305 .ops = &clk_branch2_ops,
2306 },
2307 },
2308};
2309
2310static struct clk_branch gcc_sdcc1_apps_clk = {
2311 .halt_reg = 0x42018,
2312 .clkr = {
2313 .enable_reg = 0x42018,
2314 .enable_mask = BIT(0),
2315 .hw.init = &(struct clk_init_data){
2316 .name = "gcc_sdcc1_apps_clk",
2317 .parent_names = (const char *[]){
2318 "sdcc1_apps_clk_src",
2319 },
2320 .num_parents = 1,
2321 .flags = CLK_SET_RATE_PARENT,
2322 .ops = &clk_branch2_ops,
2323 },
2324 },
2325};
2326
2327static struct clk_branch gcc_sdcc2_ahb_clk = {
2328 .halt_reg = 0x4301c,
2329 .clkr = {
2330 .enable_reg = 0x4301c,
2331 .enable_mask = BIT(0),
2332 .hw.init = &(struct clk_init_data){
2333 .name = "gcc_sdcc2_ahb_clk",
2334 .parent_names = (const char *[]){
2335 "pcnoc_bfdcd_clk_src",
2336 },
2337 .num_parents = 1,
2338 .flags = CLK_SET_RATE_PARENT,
2339 .ops = &clk_branch2_ops,
2340 },
2341 },
2342};
2343
2344static struct clk_branch gcc_sdcc2_apps_clk = {
2345 .halt_reg = 0x43018,
2346 .clkr = {
2347 .enable_reg = 0x43018,
2348 .enable_mask = BIT(0),
2349 .hw.init = &(struct clk_init_data){
2350 .name = "gcc_sdcc2_apps_clk",
2351 .parent_names = (const char *[]){
2352 "sdcc2_apps_clk_src",
2353 },
2354 .num_parents = 1,
2355 .flags = CLK_SET_RATE_PARENT,
2356 .ops = &clk_branch2_ops,
2357 },
2358 },
2359};
2360
2361static struct clk_branch gcc_gtcu_ahb_clk = {
2362 .halt_reg = 0x12044,
2363 .clkr = {
2364 .enable_reg = 0x4500c,
2365 .enable_mask = BIT(13),
2366 .hw.init = &(struct clk_init_data){
2367 .name = "gcc_gtcu_ahb_clk",
2368 .parent_names = (const char *[]){
2369 "pcnoc_bfdcd_clk_src",
2370 },
2371 .num_parents = 1,
2372 .flags = CLK_SET_RATE_PARENT,
2373 .ops = &clk_branch2_ops,
2374 },
2375 },
2376};
2377
2378static struct clk_branch gcc_jpeg_tbu_clk = {
2379 .halt_reg = 0x12034,
2380 .clkr = {
2381 .enable_reg = 0x4500c,
2382 .enable_mask = BIT(10),
2383 .hw.init = &(struct clk_init_data){
2384 .name = "gcc_jpeg_tbu_clk",
2385 .parent_names = (const char *[]){
2386 "system_noc_bfdcd_clk_src",
2387 },
2388 .num_parents = 1,
2389 .flags = CLK_SET_RATE_PARENT,
2390 .ops = &clk_branch2_ops,
2391 },
2392 },
2393};
2394
2395static struct clk_branch gcc_mdp_tbu_clk = {
2396 .halt_reg = 0x1201c,
2397 .clkr = {
2398 .enable_reg = 0x4500c,
2399 .enable_mask = BIT(4),
2400 .hw.init = &(struct clk_init_data){
2401 .name = "gcc_mdp_tbu_clk",
2402 .parent_names = (const char *[]){
2403 "system_noc_bfdcd_clk_src",
2404 },
2405 .num_parents = 1,
2406 .flags = CLK_SET_RATE_PARENT,
2407 .ops = &clk_branch2_ops,
2408 },
2409 },
2410};
2411
2412static struct clk_branch gcc_smmu_cfg_clk = {
2413 .halt_reg = 0x12038,
2414 .clkr = {
2415 .enable_reg = 0x4500c,
2416 .enable_mask = BIT(12),
2417 .hw.init = &(struct clk_init_data){
2418 .name = "gcc_smmu_cfg_clk",
2419 .parent_names = (const char *[]){
2420 "pcnoc_bfdcd_clk_src",
2421 },
2422 .num_parents = 1,
2423 .flags = CLK_SET_RATE_PARENT,
2424 .ops = &clk_branch2_ops,
2425 },
2426 },
2427};
2428
2429static struct clk_branch gcc_venus_tbu_clk = {
2430 .halt_reg = 0x12014,
2431 .clkr = {
2432 .enable_reg = 0x4500c,
2433 .enable_mask = BIT(5),
2434 .hw.init = &(struct clk_init_data){
2435 .name = "gcc_venus_tbu_clk",
2436 .parent_names = (const char *[]){
2437 "system_noc_bfdcd_clk_src",
2438 },
2439 .num_parents = 1,
2440 .flags = CLK_SET_RATE_PARENT,
2441 .ops = &clk_branch2_ops,
2442 },
2443 },
2444};
2445
2446static struct clk_branch gcc_vfe_tbu_clk = {
2447 .halt_reg = 0x1203c,
2448 .clkr = {
2449 .enable_reg = 0x4500c,
2450 .enable_mask = BIT(9),
2451 .hw.init = &(struct clk_init_data){
2452 .name = "gcc_vfe_tbu_clk",
2453 .parent_names = (const char *[]){
2454 "system_noc_bfdcd_clk_src",
2455 },
2456 .num_parents = 1,
2457 .flags = CLK_SET_RATE_PARENT,
2458 .ops = &clk_branch2_ops,
2459 },
2460 },
2461};
2462
2463static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2464 .halt_reg = 0x4102c,
2465 .clkr = {
2466 .enable_reg = 0x4102c,
2467 .enable_mask = BIT(0),
2468 .hw.init = &(struct clk_init_data){
2469 .name = "gcc_usb2a_phy_sleep_clk",
2470 .parent_names = (const char *[]){
2471 "sleep_clk_src",
2472 },
2473 .num_parents = 1,
2474 .flags = CLK_SET_RATE_PARENT,
2475 .ops = &clk_branch2_ops,
2476 },
2477 },
2478};
2479
2480static struct clk_branch gcc_usb_hs_ahb_clk = {
2481 .halt_reg = 0x41008,
2482 .clkr = {
2483 .enable_reg = 0x41008,
2484 .enable_mask = BIT(0),
2485 .hw.init = &(struct clk_init_data){
2486 .name = "gcc_usb_hs_ahb_clk",
2487 .parent_names = (const char *[]){
2488 "pcnoc_bfdcd_clk_src",
2489 },
2490 .num_parents = 1,
2491 .flags = CLK_SET_RATE_PARENT,
2492 .ops = &clk_branch2_ops,
2493 },
2494 },
2495};
2496
2497static struct clk_branch gcc_usb_hs_system_clk = {
2498 .halt_reg = 0x41004,
2499 .clkr = {
2500 .enable_reg = 0x41004,
2501 .enable_mask = BIT(0),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "gcc_usb_hs_system_clk",
2504 .parent_names = (const char *[]){
2505 "usb_hs_system_clk_src",
2506 },
2507 .num_parents = 1,
2508 .flags = CLK_SET_RATE_PARENT,
2509 .ops = &clk_branch2_ops,
2510 },
2511 },
2512};
2513
2514static struct clk_branch gcc_venus0_ahb_clk = {
2515 .halt_reg = 0x4c020,
2516 .clkr = {
2517 .enable_reg = 0x4c020,
2518 .enable_mask = BIT(0),
2519 .hw.init = &(struct clk_init_data){
2520 .name = "gcc_venus0_ahb_clk",
2521 .parent_names = (const char *[]){
2522 "pcnoc_bfdcd_clk_src",
2523 },
2524 .num_parents = 1,
2525 .flags = CLK_SET_RATE_PARENT,
2526 .ops = &clk_branch2_ops,
2527 },
2528 },
2529};
2530
2531static struct clk_branch gcc_venus0_axi_clk = {
2532 .halt_reg = 0x4c024,
2533 .clkr = {
2534 .enable_reg = 0x4c024,
2535 .enable_mask = BIT(0),
2536 .hw.init = &(struct clk_init_data){
2537 .name = "gcc_venus0_axi_clk",
2538 .parent_names = (const char *[]){
2539 "system_noc_bfdcd_clk_src",
2540 },
2541 .num_parents = 1,
2542 .flags = CLK_SET_RATE_PARENT,
2543 .ops = &clk_branch2_ops,
2544 },
2545 },
2546};
2547
2548static struct clk_branch gcc_venus0_vcodec0_clk = {
2549 .halt_reg = 0x4c01c,
2550 .clkr = {
2551 .enable_reg = 0x4c01c,
2552 .enable_mask = BIT(0),
2553 .hw.init = &(struct clk_init_data){
2554 .name = "gcc_venus0_vcodec0_clk",
2555 .parent_names = (const char *[]){
2556 "vcodec0_clk_src",
2557 },
2558 .num_parents = 1,
2559 .flags = CLK_SET_RATE_PARENT,
2560 .ops = &clk_branch2_ops,
2561 },
2562 },
2563};
2564
2565static struct clk_regmap *gcc_msm8916_clocks[] = {
2566 [GPLL0] = &gpll0.clkr,
2567 [GPLL0_VOTE] = &gpll0_vote,
2568 [BIMC_PLL] = &bimc_pll.clkr,
2569 [BIMC_PLL_VOTE] = &bimc_pll_vote,
2570 [GPLL1] = &gpll1.clkr,
2571 [GPLL1_VOTE] = &gpll1_vote,
2572 [GPLL2] = &gpll2.clkr,
2573 [GPLL2_VOTE] = &gpll2_vote,
2574 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
2575 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
2576 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
2577 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2578 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2579 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2580 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2581 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2582 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2583 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2584 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2585 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2586 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2587 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2588 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2589 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2590 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2591 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2592 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2593 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2594 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2595 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2596 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2597 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2598 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2599 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2600 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2601 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2602 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2603 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2604 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2605 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
2606 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2607 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2608 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2609 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2610 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2611 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2612 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2613 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2614 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2615 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2616 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2617 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
2618 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2619 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2620 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2621 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2622 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2623 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2624 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2625 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2626 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2627 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2628 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2629 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2630 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2631 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2632 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2633 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2634 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2635 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2636 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2637 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
2638 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
2639 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
2640 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
2641 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
2642 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
2643 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
2644 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
2645 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
2646 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
2647 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
2648 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
2649 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
2650 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
2651 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
2652 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
2653 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
2654 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
2655 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
2656 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
2657 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
2658 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
2659 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
2660 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
2661 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
2662 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
2663 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
2664 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
2665 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
2666 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
2667 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
2668 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2669 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2670 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2671 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
2672 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2673 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2674 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2675 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2676 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2677 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2678 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2679 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2680 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2681 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2682 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2683 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2684 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2685 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2686 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2687 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2688 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2689 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2690 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2691 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2692 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2693 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
2694 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2695 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2696 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
2697 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
2698 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2699 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2700 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2701 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
2702 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
2703 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
2704};
2705
2706static const struct qcom_reset_map gcc_msm8916_resets[] = {
2707 [GCC_BLSP1_BCR] = { 0x01000 },
2708 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
2709 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
2710 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
2711 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
2712 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
2713 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
2714 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
2715 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
2716 [GCC_IMEM_BCR] = { 0x0e000 },
2717 [GCC_SMMU_BCR] = { 0x12000 },
2718 [GCC_APSS_TCU_BCR] = { 0x12050 },
2719 [GCC_SMMU_XPU_BCR] = { 0x12054 },
2720 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
2721 [GCC_PRNG_BCR] = { 0x13000 },
2722 [GCC_BOOT_ROM_BCR] = { 0x13008 },
2723 [GCC_CRYPTO_BCR] = { 0x16000 },
2724 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
2725 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
2726 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
2727 [GCC_DEHR_BCR] = { 0x1f000 },
2728 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
2729 [GCC_PCNOC_BCR] = { 0x27018 },
2730 [GCC_TCSR_BCR] = { 0x28000 },
2731 [GCC_QDSS_BCR] = { 0x29000 },
2732 [GCC_DCD_BCR] = { 0x2a000 },
2733 [GCC_MSG_RAM_BCR] = { 0x2b000 },
2734 [GCC_MPM_BCR] = { 0x2c000 },
2735 [GCC_SPMI_BCR] = { 0x2e000 },
2736 [GCC_SPDM_BCR] = { 0x2f000 },
2737 [GCC_MM_SPDM_BCR] = { 0x2f024 },
2738 [GCC_BIMC_BCR] = { 0x31000 },
2739 [GCC_RBCPR_BCR] = { 0x33000 },
2740 [GCC_TLMM_BCR] = { 0x34000 },
2741 [GCC_USB_HS_BCR] = { 0x41000 },
2742 [GCC_USB2A_PHY_BCR] = { 0x41028 },
2743 [GCC_SDCC1_BCR] = { 0x42000 },
2744 [GCC_SDCC2_BCR] = { 0x43000 },
2745 [GCC_PDM_BCR] = { 0x44000 },
2746 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
2747 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
2748 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
2749 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
2750 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
2751 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
2752 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
2753 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
2754 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
2755 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
2756 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
2757 [GCC_MMSS_BCR] = { 0x4b000 },
2758 [GCC_VENUS0_BCR] = { 0x4c014 },
2759 [GCC_MDSS_BCR] = { 0x4d074 },
2760 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
2761 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
2762 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
2763 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
2764 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
2765 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
2766 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
2767 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
2768 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
2769 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
2770 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
2771 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
2772 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
2773 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
2774 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
2775 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
2776 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
2777 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
2778 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
2779 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
2780 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
2781 [GCC_OXILI_BCR] = { 0x59018 },
2782 [GCC_GMEM_BCR] = { 0x5902c },
2783 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
2784 [GCC_MDP_TBU_BCR] = { 0x62000 },
2785 [GCC_GFX_TBU_BCR] = { 0x63000 },
2786 [GCC_GFX_TCU_BCR] = { 0x64000 },
2787 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
2788 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
2789 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
2790 [GCC_GTCU_AHB_BCR] = { 0x68000 },
2791 [GCC_SMMU_CFG_BCR] = { 0x69000 },
2792 [GCC_VFE_TBU_BCR] = { 0x6a000 },
2793 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
2794 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
2795 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
2796 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
2797};
2798
2799static const struct regmap_config gcc_msm8916_regmap_config = {
2800 .reg_bits = 32,
2801 .reg_stride = 4,
2802 .val_bits = 32,
2803 .max_register = 0x80000,
2804 .fast_io = true,
2805};
2806
2807static const struct qcom_cc_desc gcc_msm8916_desc = {
2808 .config = &gcc_msm8916_regmap_config,
2809 .clks = gcc_msm8916_clocks,
2810 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
2811 .resets = gcc_msm8916_resets,
2812 .num_resets = ARRAY_SIZE(gcc_msm8916_resets),
2813};
2814
2815static const struct of_device_id gcc_msm8916_match_table[] = {
2816 { .compatible = "qcom,gcc-msm8916" },
2817 { }
2818};
2819MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
2820
2821static int gcc_msm8916_probe(struct platform_device *pdev)
2822{
2823 struct clk *clk;
2824 struct device *dev = &pdev->dev;
2825
2826 /* Temporary until RPM clocks supported */
2827 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2828 if (IS_ERR(clk))
2829 return PTR_ERR(clk);
2830
2831 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2832 CLK_IS_ROOT, 32768);
2833 if (IS_ERR(clk))
2834 return PTR_ERR(clk);
2835
2836 return qcom_cc_probe(pdev, &gcc_msm8916_desc);
2837}
2838
2839static int gcc_msm8916_remove(struct platform_device *pdev)
2840{
2841 qcom_cc_remove(pdev);
2842 return 0;
2843}
2844
2845static struct platform_driver gcc_msm8916_driver = {
2846 .probe = gcc_msm8916_probe,
2847 .remove = gcc_msm8916_remove,
2848 .driver = {
2849 .name = "gcc-msm8916",
2850 .of_match_table = gcc_msm8916_match_table,
2851 },
2852};
2853
2854static int __init gcc_msm8916_init(void)
2855{
2856 return platform_driver_register(&gcc_msm8916_driver);
2857}
2858core_initcall(gcc_msm8916_init);
2859
2860static void __exit gcc_msm8916_exit(void)
2861{
2862 platform_driver_unregister(&gcc_msm8916_driver);
2863}
2864module_exit(gcc_msm8916_exit);
2865
2866MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
2867MODULE_LICENSE("GPL v2");
2868MODULE_ALIAS("platform:gcc-msm8916");
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index e60feffc10a1..eb6a4f9fa107 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -113,14 +113,16 @@ static struct clk_regmap pll14_vote = {
113 }, 113 },
114}; 114};
115 115
116#define P_PXO 0 116enum {
117#define P_PLL8 1 117 P_PXO,
118#define P_PLL3 2 118 P_PLL8,
119#define P_CXO 2 119 P_PLL3,
120 P_CXO,
121};
120 122
121static const u8 gcc_pxo_pll8_map[] = { 123static const struct parent_map gcc_pxo_pll8_map[] = {
122 [P_PXO] = 0, 124 { P_PXO, 0 },
123 [P_PLL8] = 3, 125 { P_PLL8, 3 }
124}; 126};
125 127
126static const char *gcc_pxo_pll8[] = { 128static const char *gcc_pxo_pll8[] = {
@@ -128,10 +130,10 @@ static const char *gcc_pxo_pll8[] = {
128 "pll8_vote", 130 "pll8_vote",
129}; 131};
130 132
131static const u8 gcc_pxo_pll8_cxo_map[] = { 133static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
132 [P_PXO] = 0, 134 { P_PXO, 0 },
133 [P_PLL8] = 3, 135 { P_PLL8, 3 },
134 [P_CXO] = 5, 136 { P_CXO, 5 }
135}; 137};
136 138
137static const char *gcc_pxo_pll8_cxo[] = { 139static const char *gcc_pxo_pll8_cxo[] = {
@@ -140,10 +142,10 @@ static const char *gcc_pxo_pll8_cxo[] = {
140 "cxo", 142 "cxo",
141}; 143};
142 144
143static const u8 gcc_pxo_pll8_pll3_map[] = { 145static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
144 [P_PXO] = 0, 146 { P_PXO, 0 },
145 [P_PLL8] = 3, 147 { P_PLL8, 3 },
146 [P_PLL3] = 6, 148 { P_PLL3, 6 }
147}; 149};
148 150
149static const char *gcc_pxo_pll8_pll3[] = { 151static const char *gcc_pxo_pll8_pll3[] = {
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index a6937fe78d8a..c39d09874e74 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -32,14 +32,16 @@
32#include "clk-branch.h" 32#include "clk-branch.h"
33#include "reset.h" 33#include "reset.h"
34 34
35#define P_XO 0 35enum {
36#define P_GPLL0 1 36 P_XO,
37#define P_GPLL1 1 37 P_GPLL0,
38#define P_GPLL4 2 38 P_GPLL1,
39 P_GPLL4,
40};
39 41
40static const u8 gcc_xo_gpll0_map[] = { 42static const struct parent_map gcc_xo_gpll0_map[] = {
41 [P_XO] = 0, 43 { P_XO, 0 },
42 [P_GPLL0] = 1, 44 { P_GPLL0, 1 }
43}; 45};
44 46
45static const char *gcc_xo_gpll0[] = { 47static const char *gcc_xo_gpll0[] = {
@@ -47,10 +49,10 @@ static const char *gcc_xo_gpll0[] = {
47 "gpll0_vote", 49 "gpll0_vote",
48}; 50};
49 51
50static const u8 gcc_xo_gpll0_gpll4_map[] = { 52static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
51 [P_XO] = 0, 53 { P_XO, 0 },
52 [P_GPLL0] = 1, 54 { P_GPLL0, 1 },
53 [P_GPLL4] = 5, 55 { P_GPLL4, 5 }
54}; 56};
55 57
56static const char *gcc_xo_gpll0_gpll4[] = { 58static const char *gcc_xo_gpll0_gpll4[] = {
@@ -984,9 +986,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
984 { } 986 { }
985}; 987};
986 988
987static u8 usb_hsic_clk_src_map[] = { 989static const struct parent_map usb_hsic_clk_src_map[] = {
988 [P_XO] = 0, 990 { P_XO, 0 },
989 [P_GPLL1] = 4, 991 { P_GPLL1, 4 }
990}; 992};
991 993
992static struct clk_rcg2 usb_hsic_clk_src = { 994static struct clk_rcg2 usb_hsic_clk_src = {
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
index c9ff27b4648b..47f0ac16d149 100644
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -61,12 +61,14 @@ static const struct pll_config pll4_config = {
61 .main_output_mask = BIT(23), 61 .main_output_mask = BIT(23),
62}; 62};
63 63
64#define P_PXO 0 64enum {
65#define P_PLL4 1 65 P_PXO,
66 P_PLL4,
67};
66 68
67static const u8 lcc_pxo_pll4_map[] = { 69static const struct parent_map lcc_pxo_pll4_map[] = {
68 [P_PXO] = 0, 70 { P_PXO, 0 },
69 [P_PLL4] = 2, 71 { P_PLL4, 2 }
70}; 72};
71 73
72static const char *lcc_pxo_pll4[] = { 74static const char *lcc_pxo_pll4[] = {
@@ -294,14 +296,14 @@ static struct clk_regmap_mux pcm_clk = {
294}; 296};
295 297
296static struct freq_tbl clk_tbl_aif_osr[] = { 298static struct freq_tbl clk_tbl_aif_osr[] = {
297 { 22050, P_PLL4, 1, 147, 20480 }, 299 { 2822400, P_PLL4, 1, 147, 20480 },
298 { 32000, P_PLL4, 1, 1, 96 }, 300 { 4096000, P_PLL4, 1, 1, 96 },
299 { 44100, P_PLL4, 1, 147, 10240 }, 301 { 5644800, P_PLL4, 1, 147, 10240 },
300 { 48000, P_PLL4, 1, 1, 64 }, 302 { 6144000, P_PLL4, 1, 1, 64 },
301 { 88200, P_PLL4, 1, 147, 5120 }, 303 { 11289600, P_PLL4, 1, 147, 5120 },
302 { 96000, P_PLL4, 1, 1, 32 }, 304 { 12288000, P_PLL4, 1, 1, 32 },
303 { 176400, P_PLL4, 1, 147, 2560 }, 305 { 22579200, P_PLL4, 1, 147, 2560 },
304 { 192000, P_PLL4, 1, 1, 16 }, 306 { 24576000, P_PLL4, 1, 1, 16 },
305 { }, 307 { },
306}; 308};
307 309
@@ -360,7 +362,7 @@ static struct clk_branch spdif_clk = {
360}; 362};
361 363
362static struct freq_tbl clk_tbl_ahbix[] = { 364static struct freq_tbl clk_tbl_ahbix[] = {
363 { 131072, P_PLL4, 1, 1, 3 }, 365 { 131072000, P_PLL4, 1, 1, 3 },
364 { }, 366 { },
365}; 367};
366 368
@@ -386,13 +388,12 @@ static struct clk_rcg ahbix_clk = {
386 .freq_tbl = clk_tbl_ahbix, 388 .freq_tbl = clk_tbl_ahbix,
387 .clkr = { 389 .clkr = {
388 .enable_reg = 0x38, 390 .enable_reg = 0x38,
389 .enable_mask = BIT(10), /* toggle the gfmux to select mn/pxo */ 391 .enable_mask = BIT(11),
390 .hw.init = &(struct clk_init_data){ 392 .hw.init = &(struct clk_init_data){
391 .name = "ahbix", 393 .name = "ahbix",
392 .parent_names = lcc_pxo_pll4, 394 .parent_names = lcc_pxo_pll4,
393 .num_parents = 2, 395 .num_parents = 2,
394 .ops = &clk_rcg_ops, 396 .ops = &clk_rcg_lcc_ops,
395 .flags = CLK_SET_RATE_GATE,
396 }, 397 },
397 }, 398 },
398}; 399};
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index e2c863295f00..d0df9d5fc3af 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -47,12 +47,14 @@ static struct clk_pll pll4 = {
47 }, 47 },
48}; 48};
49 49
50#define P_PXO 0 50enum {
51#define P_PLL4 1 51 P_PXO,
52 P_PLL4,
53};
52 54
53static const u8 lcc_pxo_pll4_map[] = { 55static const struct parent_map lcc_pxo_pll4_map[] = {
54 [P_PXO] = 0, 56 { P_PXO, 0 },
55 [P_PLL4] = 2, 57 { P_PLL4, 2 }
56}; 58};
57 59
58static const char *lcc_pxo_pll4[] = { 60static const char *lcc_pxo_pll4[] = {
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 157139a5c1ca..1b17df2cb0af 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -27,28 +27,30 @@
27#include "clk-branch.h" 27#include "clk-branch.h"
28#include "reset.h" 28#include "reset.h"
29 29
30#define P_XO 0 30enum {
31#define P_MMPLL0 1 31 P_XO,
32#define P_EDPLINK 1 32 P_MMPLL0,
33#define P_MMPLL1 2 33 P_EDPLINK,
34#define P_HDMIPLL 2 34 P_MMPLL1,
35#define P_GPLL0 3 35 P_HDMIPLL,
36#define P_EDPVCO 3 36 P_GPLL0,
37#define P_MMPLL4 4 37 P_EDPVCO,
38#define P_DSI0PLL 4 38 P_MMPLL4,
39#define P_DSI0PLL_BYTE 4 39 P_DSI0PLL,
40#define P_MMPLL2 4 40 P_DSI0PLL_BYTE,
41#define P_MMPLL3 4 41 P_MMPLL2,
42#define P_GPLL1 5 42 P_MMPLL3,
43#define P_DSI1PLL 5 43 P_GPLL1,
44#define P_DSI1PLL_BYTE 5 44 P_DSI1PLL,
45#define P_MMSLEEP 6 45 P_DSI1PLL_BYTE,
46 46 P_MMSLEEP,
47static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { 47};
48 [P_XO] = 0, 48
49 [P_MMPLL0] = 1, 49static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
50 [P_MMPLL1] = 2, 50 { P_XO, 0 },
51 [P_GPLL0] = 5, 51 { P_MMPLL0, 1 },
52 { P_MMPLL1, 2 },
53 { P_GPLL0, 5 }
52}; 54};
53 55
54static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = { 56static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
@@ -58,13 +60,13 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
58 "mmss_gpll0_vote", 60 "mmss_gpll0_vote",
59}; 61};
60 62
61static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { 63static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
62 [P_XO] = 0, 64 { P_XO, 0 },
63 [P_MMPLL0] = 1, 65 { P_MMPLL0, 1 },
64 [P_HDMIPLL] = 4, 66 { P_HDMIPLL, 4 },
65 [P_GPLL0] = 5, 67 { P_GPLL0, 5 },
66 [P_DSI0PLL] = 2, 68 { P_DSI0PLL, 2 },
67 [P_DSI1PLL] = 3, 69 { P_DSI1PLL, 3 }
68}; 70};
69 71
70static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { 72static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
@@ -76,12 +78,12 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
76 "dsi1pll", 78 "dsi1pll",
77}; 79};
78 80
79static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = { 81static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
80 [P_XO] = 0, 82 { P_XO, 0 },
81 [P_MMPLL0] = 1, 83 { P_MMPLL0, 1 },
82 [P_MMPLL1] = 2, 84 { P_MMPLL1, 2 },
83 [P_GPLL0] = 5, 85 { P_GPLL0, 5 },
84 [P_MMPLL2] = 3, 86 { P_MMPLL2, 3 }
85}; 87};
86 88
87static const char *mmcc_xo_mmpll0_1_2_gpll0[] = { 89static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
@@ -92,12 +94,12 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
92 "mmpll2", 94 "mmpll2",
93}; 95};
94 96
95static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = { 97static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
96 [P_XO] = 0, 98 { P_XO, 0 },
97 [P_MMPLL0] = 1, 99 { P_MMPLL0, 1 },
98 [P_MMPLL1] = 2, 100 { P_MMPLL1, 2 },
99 [P_GPLL0] = 5, 101 { P_GPLL0, 5 },
100 [P_MMPLL3] = 3, 102 { P_MMPLL3, 3 }
101}; 103};
102 104
103static const char *mmcc_xo_mmpll0_1_3_gpll0[] = { 105static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
@@ -108,13 +110,13 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
108 "mmpll3", 110 "mmpll3",
109}; 111};
110 112
111static const u8 mmcc_xo_dsi_hdmi_edp_map[] = { 113static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
112 [P_XO] = 0, 114 { P_XO, 0 },
113 [P_EDPLINK] = 4, 115 { P_EDPLINK, 4 },
114 [P_HDMIPLL] = 3, 116 { P_HDMIPLL, 3 },
115 [P_EDPVCO] = 5, 117 { P_EDPVCO, 5 },
116 [P_DSI0PLL] = 1, 118 { P_DSI0PLL, 1 },
117 [P_DSI1PLL] = 2, 119 { P_DSI1PLL, 2 }
118}; 120};
119 121
120static const char *mmcc_xo_dsi_hdmi_edp[] = { 122static const char *mmcc_xo_dsi_hdmi_edp[] = {
@@ -126,13 +128,13 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
126 "dsi1pll", 128 "dsi1pll",
127}; 129};
128 130
129static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { 131static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
130 [P_XO] = 0, 132 { P_XO, 0 },
131 [P_EDPLINK] = 4, 133 { P_EDPLINK, 4 },
132 [P_HDMIPLL] = 3, 134 { P_HDMIPLL, 3 },
133 [P_GPLL0] = 5, 135 { P_GPLL0, 5 },
134 [P_DSI0PLL] = 1, 136 { P_DSI0PLL, 1 },
135 [P_DSI1PLL] = 2, 137 { P_DSI1PLL, 2 }
136}; 138};
137 139
138static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = { 140static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
@@ -144,13 +146,13 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
144 "dsi1pll", 146 "dsi1pll",
145}; 147};
146 148
147static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { 149static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
148 [P_XO] = 0, 150 { P_XO, 0 },
149 [P_EDPLINK] = 4, 151 { P_EDPLINK, 4 },
150 [P_HDMIPLL] = 3, 152 { P_HDMIPLL, 3 },
151 [P_GPLL0] = 5, 153 { P_GPLL0, 5 },
152 [P_DSI0PLL_BYTE] = 1, 154 { P_DSI0PLL_BYTE, 1 },
153 [P_DSI1PLL_BYTE] = 2, 155 { P_DSI1PLL_BYTE, 2 }
154}; 156};
155 157
156static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { 158static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
@@ -162,12 +164,12 @@ static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
162 "dsi1pllbyte", 164 "dsi1pllbyte",
163}; 165};
164 166
165static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = { 167static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
166 [P_XO] = 0, 168 { P_XO, 0 },
167 [P_MMPLL0] = 1, 169 { P_MMPLL0, 1 },
168 [P_MMPLL1] = 2, 170 { P_MMPLL1, 2 },
169 [P_GPLL0] = 5, 171 { P_GPLL0, 5 },
170 [P_MMPLL4] = 3, 172 { P_MMPLL4, 3 }
171}; 173};
172 174
173static const char *mmcc_xo_mmpll0_1_4_gpll0[] = { 175static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
@@ -178,13 +180,13 @@ static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
178 "gpll0", 180 "gpll0",
179}; 181};
180 182
181static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = { 183static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
182 [P_XO] = 0, 184 { P_XO, 0 },
183 [P_MMPLL0] = 1, 185 { P_MMPLL0, 1 },
184 [P_MMPLL1] = 2, 186 { P_MMPLL1, 2 },
185 [P_MMPLL4] = 3, 187 { P_MMPLL4, 3 },
186 [P_GPLL0] = 5, 188 { P_GPLL0, 5 },
187 [P_GPLL1] = 4, 189 { P_GPLL1, 4 }
188}; 190};
189 191
190static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = { 192static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
@@ -196,14 +198,14 @@ static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
196 "gpll0", 198 "gpll0",
197}; 199};
198 200
199static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = { 201static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
200 [P_XO] = 0, 202 { P_XO, 0 },
201 [P_MMPLL0] = 1, 203 { P_MMPLL0, 1 },
202 [P_MMPLL1] = 2, 204 { P_MMPLL1, 2 },
203 [P_MMPLL4] = 3, 205 { P_MMPLL4, 3 },
204 [P_GPLL0] = 5, 206 { P_GPLL0, 5 },
205 [P_GPLL1] = 4, 207 { P_GPLL1, 4 },
206 [P_MMSLEEP] = 6, 208 { P_MMSLEEP, 6 }
207}; 209};
208 210
209static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = { 211static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index e8b33bbc362f..9711bca9cc06 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -33,18 +33,21 @@
33#include "clk-branch.h" 33#include "clk-branch.h"
34#include "reset.h" 34#include "reset.h"
35 35
36#define P_PXO 0 36enum {
37#define P_PLL8 1 37 P_PXO,
38#define P_PLL2 2 38 P_PLL8,
39#define P_PLL3 3 39 P_PLL2,
40#define P_PLL15 3 40 P_PLL3,
41 P_PLL15,
42 P_HDMI_PLL,
43};
41 44
42#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } 45#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
43 46
44static u8 mmcc_pxo_pll8_pll2_map[] = { 47static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
45 [P_PXO] = 0, 48 { P_PXO, 0 },
46 [P_PLL8] = 2, 49 { P_PLL8, 2 },
47 [P_PLL2] = 1, 50 { P_PLL2, 1 }
48}; 51};
49 52
50static const char *mmcc_pxo_pll8_pll2[] = { 53static const char *mmcc_pxo_pll8_pll2[] = {
@@ -53,11 +56,11 @@ static const char *mmcc_pxo_pll8_pll2[] = {
53 "pll2", 56 "pll2",
54}; 57};
55 58
56static u8 mmcc_pxo_pll8_pll2_pll3_map[] = { 59static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
57 [P_PXO] = 0, 60 { P_PXO, 0 },
58 [P_PLL8] = 2, 61 { P_PLL8, 2 },
59 [P_PLL2] = 1, 62 { P_PLL2, 1 },
60 [P_PLL3] = 3, 63 { P_PLL3, 3 }
61}; 64};
62 65
63static const char *mmcc_pxo_pll8_pll2_pll15[] = { 66static const char *mmcc_pxo_pll8_pll2_pll15[] = {
@@ -67,11 +70,11 @@ static const char *mmcc_pxo_pll8_pll2_pll15[] = {
67 "pll15", 70 "pll15",
68}; 71};
69 72
70static u8 mmcc_pxo_pll8_pll2_pll15_map[] = { 73static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
71 [P_PXO] = 0, 74 { P_PXO, 0 },
72 [P_PLL8] = 2, 75 { P_PLL8, 2 },
73 [P_PLL2] = 1, 76 { P_PLL2, 1 },
74 [P_PLL15] = 3, 77 { P_PLL15, 3 }
75}; 78};
76 79
77static const char *mmcc_pxo_pll8_pll2_pll3[] = { 80static const char *mmcc_pxo_pll8_pll2_pll3[] = {
@@ -1377,11 +1380,9 @@ static struct clk_branch rot_clk = {
1377 }, 1380 },
1378}; 1381};
1379 1382
1380#define P_HDMI_PLL 1 1383static const struct parent_map mmcc_pxo_hdmi_map[] = {
1381 1384 { P_PXO, 0 },
1382static u8 mmcc_pxo_hdmi_map[] = { 1385 { P_HDMI_PLL, 3 }
1383 [P_PXO] = 0,
1384 [P_HDMI_PLL] = 3,
1385}; 1386};
1386 1387
1387static const char *mmcc_pxo_hdmi[] = { 1388static const char *mmcc_pxo_hdmi[] = {
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index be94c54a9a4f..07f4cc159ad3 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -32,26 +32,28 @@
32#include "clk-branch.h" 32#include "clk-branch.h"
33#include "reset.h" 33#include "reset.h"
34 34
35#define P_XO 0 35enum {
36#define P_MMPLL0 1 36 P_XO,
37#define P_EDPLINK 1 37 P_MMPLL0,
38#define P_MMPLL1 2 38 P_EDPLINK,
39#define P_HDMIPLL 2 39 P_MMPLL1,
40#define P_GPLL0 3 40 P_HDMIPLL,
41#define P_EDPVCO 3 41 P_GPLL0,
42#define P_GPLL1 4 42 P_EDPVCO,
43#define P_DSI0PLL 4 43 P_GPLL1,
44#define P_DSI0PLL_BYTE 4 44 P_DSI0PLL,
45#define P_MMPLL2 4 45 P_DSI0PLL_BYTE,
46#define P_MMPLL3 4 46 P_MMPLL2,
47#define P_DSI1PLL 5 47 P_MMPLL3,
48#define P_DSI1PLL_BYTE 5 48 P_DSI1PLL,
49 49 P_DSI1PLL_BYTE,
50static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { 50};
51 [P_XO] = 0, 51
52 [P_MMPLL0] = 1, 52static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
53 [P_MMPLL1] = 2, 53 { P_XO, 0 },
54 [P_GPLL0] = 5, 54 { P_MMPLL0, 1 },
55 { P_MMPLL1, 2 },
56 { P_GPLL0, 5 }
55}; 57};
56 58
57static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = { 59static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
@@ -61,13 +63,13 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
61 "mmss_gpll0_vote", 63 "mmss_gpll0_vote",
62}; 64};
63 65
64static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { 66static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
65 [P_XO] = 0, 67 { P_XO, 0 },
66 [P_MMPLL0] = 1, 68 { P_MMPLL0, 1 },
67 [P_HDMIPLL] = 4, 69 { P_HDMIPLL, 4 },
68 [P_GPLL0] = 5, 70 { P_GPLL0, 5 },
69 [P_DSI0PLL] = 2, 71 { P_DSI0PLL, 2 },
70 [P_DSI1PLL] = 3, 72 { P_DSI1PLL, 3 }
71}; 73};
72 74
73static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { 75static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
@@ -79,12 +81,12 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
79 "dsi1pll", 81 "dsi1pll",
80}; 82};
81 83
82static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = { 84static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
83 [P_XO] = 0, 85 { P_XO, 0 },
84 [P_MMPLL0] = 1, 86 { P_MMPLL0, 1 },
85 [P_MMPLL1] = 2, 87 { P_MMPLL1, 2 },
86 [P_GPLL0] = 5, 88 { P_GPLL0, 5 },
87 [P_MMPLL2] = 3, 89 { P_MMPLL2, 3 }
88}; 90};
89 91
90static const char *mmcc_xo_mmpll0_1_2_gpll0[] = { 92static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
@@ -95,12 +97,12 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
95 "mmpll2", 97 "mmpll2",
96}; 98};
97 99
98static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = { 100static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
99 [P_XO] = 0, 101 { P_XO, 0 },
100 [P_MMPLL0] = 1, 102 { P_MMPLL0, 1 },
101 [P_MMPLL1] = 2, 103 { P_MMPLL1, 2 },
102 [P_GPLL0] = 5, 104 { P_GPLL0, 5 },
103 [P_MMPLL3] = 3, 105 { P_MMPLL3, 3 }
104}; 106};
105 107
106static const char *mmcc_xo_mmpll0_1_3_gpll0[] = { 108static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
@@ -111,12 +113,12 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
111 "mmpll3", 113 "mmpll3",
112}; 114};
113 115
114static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = { 116static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
115 [P_XO] = 0, 117 { P_XO, 0 },
116 [P_MMPLL0] = 1, 118 { P_MMPLL0, 1 },
117 [P_MMPLL1] = 2, 119 { P_MMPLL1, 2 },
118 [P_GPLL0] = 5, 120 { P_GPLL0, 5 },
119 [P_GPLL1] = 4, 121 { P_GPLL1, 4 }
120}; 122};
121 123
122static const char *mmcc_xo_mmpll0_1_gpll1_0[] = { 124static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
@@ -127,13 +129,13 @@ static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
127 "gpll1_vote", 129 "gpll1_vote",
128}; 130};
129 131
130static const u8 mmcc_xo_dsi_hdmi_edp_map[] = { 132static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
131 [P_XO] = 0, 133 { P_XO, 0 },
132 [P_EDPLINK] = 4, 134 { P_EDPLINK, 4 },
133 [P_HDMIPLL] = 3, 135 { P_HDMIPLL, 3 },
134 [P_EDPVCO] = 5, 136 { P_EDPVCO, 5 },
135 [P_DSI0PLL] = 1, 137 { P_DSI0PLL, 1 },
136 [P_DSI1PLL] = 2, 138 { P_DSI1PLL, 2 }
137}; 139};
138 140
139static const char *mmcc_xo_dsi_hdmi_edp[] = { 141static const char *mmcc_xo_dsi_hdmi_edp[] = {
@@ -145,13 +147,13 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
145 "dsi1pll", 147 "dsi1pll",
146}; 148};
147 149
148static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { 150static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
149 [P_XO] = 0, 151 { P_XO, 0 },
150 [P_EDPLINK] = 4, 152 { P_EDPLINK, 4 },
151 [P_HDMIPLL] = 3, 153 { P_HDMIPLL, 3 },
152 [P_GPLL0] = 5, 154 { P_GPLL0, 5 },
153 [P_DSI0PLL] = 1, 155 { P_DSI0PLL, 1 },
154 [P_DSI1PLL] = 2, 156 { P_DSI1PLL, 2 }
155}; 157};
156 158
157static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = { 159static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
@@ -163,13 +165,13 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
163 "dsi1pll", 165 "dsi1pll",
164}; 166};
165 167
166static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { 168static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
167 [P_XO] = 0, 169 { P_XO, 0 },
168 [P_EDPLINK] = 4, 170 { P_EDPLINK, 4 },
169 [P_HDMIPLL] = 3, 171 { P_HDMIPLL, 3 },
170 [P_GPLL0] = 5, 172 { P_GPLL0, 5 },
171 [P_DSI0PLL_BYTE] = 1, 173 { P_DSI0PLL_BYTE, 1 },
172 [P_DSI1PLL_BYTE] = 2, 174 { P_DSI1PLL_BYTE, 2 }
173}; 175};
174 176
175static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { 177static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 7eb684c50d42..556ce041d371 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -704,7 +704,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
704 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), 704 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
705}; 705};
706 706
707static const char *rk3188_critical_clocks[] __initconst = { 707static const char *const rk3188_critical_clocks[] __initconst = {
708 "aclk_cpu", 708 "aclk_cpu",
709 "aclk_peri", 709 "aclk_peri",
710 "hclk_peri", 710 "hclk_peri",
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 05d7a0bc0599..d17eb4528a28 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -771,7 +771,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
771 GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS), 771 GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
772}; 772};
773 773
774static const char *rk3288_critical_clocks[] __initconst = { 774static const char *const rk3288_critical_clocks[] __initconst = {
775 "aclk_cpu", 775 "aclk_cpu",
776 "aclk_peri", 776 "aclk_peri",
777 "hclk_peri", 777 "hclk_peri",
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 20e05bbb3a67..edb5d489ae61 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -317,7 +317,8 @@ void __init rockchip_clk_register_armclk(unsigned int lookup_id,
317 rockchip_clk_add_lookup(clk, lookup_id); 317 rockchip_clk_add_lookup(clk, lookup_id);
318} 318}
319 319
320void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks) 320void __init rockchip_clk_protect_critical(const char *const clocks[],
321 int nclocks)
321{ 322{
322 int i; 323 int i;
323 324
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 58d2e3bdf22f..e63cafe893e1 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -182,7 +182,7 @@ struct clk *rockchip_clk_register_mmc(const char *name,
182 const char **parent_names, u8 num_parents, 182 const char **parent_names, u8 num_parents,
183 void __iomem *reg, int shift); 183 void __iomem *reg, int shift);
184 184
185#define PNAME(x) static const char *x[] __initconst 185#define PNAME(x) static const char *x[] __initdata
186 186
187enum rockchip_clk_branch_type { 187enum rockchip_clk_branch_type {
188 branch_composite, 188 branch_composite,
@@ -407,7 +407,7 @@ void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
407 const struct rockchip_cpuclk_reg_data *reg_data, 407 const struct rockchip_cpuclk_reg_data *reg_data,
408 const struct rockchip_cpuclk_rate_table *rates, 408 const struct rockchip_cpuclk_rate_table *rates,
409 int nrates); 409 int nrates);
410void rockchip_clk_protect_critical(const char *clocks[], int nclocks); 410void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
411void rockchip_register_restart_notifier(unsigned int reg); 411void rockchip_register_restart_notifier(unsigned int reg);
412 412
413#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) 413#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 006c6f294310..17e9af7fe81f 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
10obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o 10obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
11obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o 11obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
12obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o 12obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
13obj-$(CONFIG_ARCH_EXYNOS5433) += clk-exynos5433.o
13obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 14obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
14obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 15obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
15obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o 16obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
index 3a7cb2506731..03a52228b6d1 100644
--- a/drivers/clk/samsung/clk-exynos-clkout.c
+++ b/drivers/clk/samsung/clk-exynos-clkout.c
@@ -142,6 +142,8 @@ CLK_OF_DECLARE(exynos4212_clkout, "samsung,exynos4212-pmu",
142 exynos4_clkout_init); 142 exynos4_clkout_init);
143CLK_OF_DECLARE(exynos4412_clkout, "samsung,exynos4412-pmu", 143CLK_OF_DECLARE(exynos4412_clkout, "samsung,exynos4412-pmu",
144 exynos4_clkout_init); 144 exynos4_clkout_init);
145CLK_OF_DECLARE(exynos3250_clkout, "samsung,exynos3250-pmu",
146 exynos4_clkout_init);
145 147
146static void __init exynos5_clkout_init(struct device_node *node) 148static void __init exynos5_clkout_init(struct device_node *node)
147{ 149{
@@ -151,3 +153,5 @@ CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",
151 exynos5_clkout_init); 153 exynos5_clkout_init);
152CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu", 154CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",
153 exynos5_clkout_init); 155 exynos5_clkout_init);
156CLK_OF_DECLARE(exynos5433_clkout, "samsung,exynos5433-pmu",
157 exynos5_clkout_init);
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index cc4c348d8a24..538de66a759e 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -894,3 +894,166 @@ static void __init exynos3250_cmu_dmc_init(struct device_node *np)
894} 894}
895CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", 895CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
896 exynos3250_cmu_dmc_init); 896 exynos3250_cmu_dmc_init);
897
898
899/*
900 * CMU ISP
901 */
902
903#define DIV_ISP0 0x300
904#define DIV_ISP1 0x304
905#define GATE_IP_ISP0 0x800
906#define GATE_IP_ISP1 0x804
907#define GATE_SCLK_ISP 0x900
908
909static struct samsung_div_clock isp_div_clks[] __initdata = {
910 /*
911 * NOTE: Following table is sorted by register address in ascending
912 * order and then bitfield shift in descending order, as it is done
913 * in the User's Manual. When adding new entries, please make sure
914 * that the order is preserved, to avoid merge conflicts and make
915 * further work with defined data easier.
916 */
917 /* DIV_ISP0 */
918 DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3),
919 DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3),
920
921 /* DIV_ISP1 */
922 DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub",
923 DIV_ISP1, 8, 3),
924 DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub",
925 DIV_ISP1, 4, 3),
926 DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),
927};
928
929static struct samsung_gate_clock isp_gate_clks[] __initdata = {
930 /*
931 * NOTE: Following table is sorted by register address in ascending
932 * order and then bitfield shift in descending order, as it is done
933 * in the User's Manual. When adding new entries, please make sure
934 * that the order is preserved, to avoid merge conflicts and make
935 * further work with defined data easier.
936 */
937
938 /* GATE_IP_ISP0 */
939 GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
940 GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0),
941 GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
942 GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0),
943 GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
944 GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0),
945 GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
946 GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0),
947 GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
948 GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0),
949 GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
950 GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0),
951 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
952 GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0),
953 GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
954 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
955 GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
956 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
957 GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
958 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
959 GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
960 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
961 GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
962 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
963 GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
964 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
965 GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
966 GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0),
967 GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
968 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
969 GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
970 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
971 GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
972 GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0),
973 GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
974 GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0),
975 GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
976 GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0),
977 GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
978 GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0),
979 GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
980 GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0),
981 GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
982 GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0),
983 GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
984 GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0),
985 GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
986 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
987 GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
988 GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0),
989 GATE(CLK_FD, "fd", "mout_aclk_266_sub",
990 GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),
991 GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
992 GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),
993 GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
994 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
995
996 /* GATE_IP_ISP1 */
997 GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
998 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
999 GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
1000 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
1001 GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
1002 GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0),
1003 GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
1004 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
1005 GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
1006 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
1007 GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
1008 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
1009 GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
1010 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
1011 GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
1012 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
1013 GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
1014 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
1015 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
1016 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
1017 GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
1018 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
1019
1020 /* GATE_SCLK_ISP */
1021 GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",
1022 GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
1023};
1024
1025static struct samsung_cmu_info isp_cmu_info __initdata = {
1026 .div_clks = isp_div_clks,
1027 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
1028 .gate_clks = isp_gate_clks,
1029 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
1030 .nr_clk_ids = NR_CLKS_ISP,
1031};
1032
1033static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
1034{
1035 struct device_node *np = pdev->dev.of_node;
1036
1037 samsung_cmu_register_one(np, &isp_cmu_info);
1038 return 0;
1039}
1040
1041static const struct of_device_id exynos3250_cmu_isp_of_match[] = {
1042 { .compatible = "samsung,exynos3250-cmu-isp", },
1043 { /* sentinel */ }
1044};
1045
1046static struct platform_driver exynos3250_cmu_isp_driver = {
1047 .driver = {
1048 .name = "exynos3250-cmu-isp",
1049 .of_match_table = exynos3250_cmu_isp_of_match,
1050 },
1051};
1052
1053static int __init exynos3250_cmu_platform_init(void)
1054{
1055 return platform_driver_probe(&exynos3250_cmu_isp_driver,
1056 exynos3250_cmu_isp_probe);
1057}
1058subsys_initcall(exynos3250_cmu_platform_init);
1059
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 51462e85675f..714d6ba782c8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1354,7 +1354,7 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1354 VPLL_LOCK, VPLL_CON0, NULL), 1354 VPLL_LOCK, VPLL_CON0, NULL),
1355}; 1355};
1356 1356
1357static void __init exynos4_core_down_clock(enum exynos4_soc soc) 1357static void __init exynos4x12_core_down_clock(void)
1358{ 1358{
1359 unsigned int tmp; 1359 unsigned int tmp;
1360 1360
@@ -1373,11 +1373,9 @@ static void __init exynos4_core_down_clock(enum exynos4_soc soc)
1373 __raw_writel(tmp, reg_base + PWR_CTRL1); 1373 __raw_writel(tmp, reg_base + PWR_CTRL1);
1374 1374
1375 /* 1375 /*
1376 * Disable the clock up feature on Exynos4x12, in case it was 1376 * Disable the clock up feature in case it was enabled by bootloader.
1377 * enabled by bootloader.
1378 */ 1377 */
1379 if (exynos4_soc == EXYNOS4X12) 1378 __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
1380 __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
1381} 1379}
1382 1380
1383/* register exynos4 clocks */ 1381/* register exynos4 clocks */
@@ -1474,7 +1472,8 @@ static void __init exynos4_clk_init(struct device_node *np,
1474 samsung_clk_register_alias(ctx, exynos4_aliases, 1472 samsung_clk_register_alias(ctx, exynos4_aliases,
1475 ARRAY_SIZE(exynos4_aliases)); 1473 ARRAY_SIZE(exynos4_aliases));
1476 1474
1477 exynos4_core_down_clock(soc); 1475 if (soc == EXYNOS4X12)
1476 exynos4x12_core_down_clock();
1478 exynos4_clk_sleep_init(); 1477 exynos4_clk_sleep_init();
1479 1478
1480 samsung_clk_of_add_provider(np, ctx); 1479 samsung_clk_of_add_provider(np, ctx);
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
new file mode 100644
index 000000000000..387e3e39e635
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -0,0 +1,5423 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5443 SoC.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16
17#include <dt-bindings/clock/exynos5433.h>
18
19#include "clk.h"
20#include "clk-pll.h"
21
22/*
23 * Register offset definitions for CMU_TOP
24 */
25#define ISP_PLL_LOCK 0x0000
26#define AUD_PLL_LOCK 0x0004
27#define ISP_PLL_CON0 0x0100
28#define ISP_PLL_CON1 0x0104
29#define ISP_PLL_FREQ_DET 0x0108
30#define AUD_PLL_CON0 0x0110
31#define AUD_PLL_CON1 0x0114
32#define AUD_PLL_CON2 0x0118
33#define AUD_PLL_FREQ_DET 0x011c
34#define MUX_SEL_TOP0 0x0200
35#define MUX_SEL_TOP1 0x0204
36#define MUX_SEL_TOP2 0x0208
37#define MUX_SEL_TOP3 0x020c
38#define MUX_SEL_TOP4 0x0210
39#define MUX_SEL_TOP_MSCL 0x0220
40#define MUX_SEL_TOP_CAM1 0x0224
41#define MUX_SEL_TOP_DISP 0x0228
42#define MUX_SEL_TOP_FSYS0 0x0230
43#define MUX_SEL_TOP_FSYS1 0x0234
44#define MUX_SEL_TOP_PERIC0 0x0238
45#define MUX_SEL_TOP_PERIC1 0x023c
46#define MUX_ENABLE_TOP0 0x0300
47#define MUX_ENABLE_TOP1 0x0304
48#define MUX_ENABLE_TOP2 0x0308
49#define MUX_ENABLE_TOP3 0x030c
50#define MUX_ENABLE_TOP4 0x0310
51#define MUX_ENABLE_TOP_MSCL 0x0320
52#define MUX_ENABLE_TOP_CAM1 0x0324
53#define MUX_ENABLE_TOP_DISP 0x0328
54#define MUX_ENABLE_TOP_FSYS0 0x0330
55#define MUX_ENABLE_TOP_FSYS1 0x0334
56#define MUX_ENABLE_TOP_PERIC0 0x0338
57#define MUX_ENABLE_TOP_PERIC1 0x033c
58#define MUX_STAT_TOP0 0x0400
59#define MUX_STAT_TOP1 0x0404
60#define MUX_STAT_TOP2 0x0408
61#define MUX_STAT_TOP3 0x040c
62#define MUX_STAT_TOP4 0x0410
63#define MUX_STAT_TOP_MSCL 0x0420
64#define MUX_STAT_TOP_CAM1 0x0424
65#define MUX_STAT_TOP_FSYS0 0x0430
66#define MUX_STAT_TOP_FSYS1 0x0434
67#define MUX_STAT_TOP_PERIC0 0x0438
68#define MUX_STAT_TOP_PERIC1 0x043c
69#define DIV_TOP0 0x0600
70#define DIV_TOP1 0x0604
71#define DIV_TOP2 0x0608
72#define DIV_TOP3 0x060c
73#define DIV_TOP4 0x0610
74#define DIV_TOP_MSCL 0x0618
75#define DIV_TOP_CAM10 0x061c
76#define DIV_TOP_CAM11 0x0620
77#define DIV_TOP_FSYS0 0x062c
78#define DIV_TOP_FSYS1 0x0630
79#define DIV_TOP_FSYS2 0x0634
80#define DIV_TOP_PERIC0 0x0638
81#define DIV_TOP_PERIC1 0x063c
82#define DIV_TOP_PERIC2 0x0640
83#define DIV_TOP_PERIC3 0x0644
84#define DIV_TOP_PERIC4 0x0648
85#define DIV_TOP_PLL_FREQ_DET 0x064c
86#define DIV_STAT_TOP0 0x0700
87#define DIV_STAT_TOP1 0x0704
88#define DIV_STAT_TOP2 0x0708
89#define DIV_STAT_TOP3 0x070c
90#define DIV_STAT_TOP4 0x0710
91#define DIV_STAT_TOP_MSCL 0x0718
92#define DIV_STAT_TOP_CAM10 0x071c
93#define DIV_STAT_TOP_CAM11 0x0720
94#define DIV_STAT_TOP_FSYS0 0x072c
95#define DIV_STAT_TOP_FSYS1 0x0730
96#define DIV_STAT_TOP_FSYS2 0x0734
97#define DIV_STAT_TOP_PERIC0 0x0738
98#define DIV_STAT_TOP_PERIC1 0x073c
99#define DIV_STAT_TOP_PERIC2 0x0740
100#define DIV_STAT_TOP_PERIC3 0x0744
101#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
102#define ENABLE_ACLK_TOP 0x0800
103#define ENABLE_SCLK_TOP 0x0a00
104#define ENABLE_SCLK_TOP_MSCL 0x0a04
105#define ENABLE_SCLK_TOP_CAM1 0x0a08
106#define ENABLE_SCLK_TOP_DISP 0x0a0c
107#define ENABLE_SCLK_TOP_FSYS 0x0a10
108#define ENABLE_SCLK_TOP_PERIC 0x0a14
109#define ENABLE_IP_TOP 0x0b00
110#define ENABLE_CMU_TOP 0x0c00
111#define ENABLE_CMU_TOP_DIV_STAT 0x0c04
112
113static unsigned long top_clk_regs[] __initdata = {
114 ISP_PLL_LOCK,
115 AUD_PLL_LOCK,
116 ISP_PLL_CON0,
117 ISP_PLL_CON1,
118 ISP_PLL_FREQ_DET,
119 AUD_PLL_CON0,
120 AUD_PLL_CON1,
121 AUD_PLL_CON2,
122 AUD_PLL_FREQ_DET,
123 MUX_SEL_TOP0,
124 MUX_SEL_TOP1,
125 MUX_SEL_TOP2,
126 MUX_SEL_TOP3,
127 MUX_SEL_TOP4,
128 MUX_SEL_TOP_MSCL,
129 MUX_SEL_TOP_CAM1,
130 MUX_SEL_TOP_DISP,
131 MUX_SEL_TOP_FSYS0,
132 MUX_SEL_TOP_FSYS1,
133 MUX_SEL_TOP_PERIC0,
134 MUX_SEL_TOP_PERIC1,
135 MUX_ENABLE_TOP0,
136 MUX_ENABLE_TOP1,
137 MUX_ENABLE_TOP2,
138 MUX_ENABLE_TOP3,
139 MUX_ENABLE_TOP4,
140 MUX_ENABLE_TOP_MSCL,
141 MUX_ENABLE_TOP_CAM1,
142 MUX_ENABLE_TOP_DISP,
143 MUX_ENABLE_TOP_FSYS0,
144 MUX_ENABLE_TOP_FSYS1,
145 MUX_ENABLE_TOP_PERIC0,
146 MUX_ENABLE_TOP_PERIC1,
147 MUX_STAT_TOP0,
148 MUX_STAT_TOP1,
149 MUX_STAT_TOP2,
150 MUX_STAT_TOP3,
151 MUX_STAT_TOP4,
152 MUX_STAT_TOP_MSCL,
153 MUX_STAT_TOP_CAM1,
154 MUX_STAT_TOP_FSYS0,
155 MUX_STAT_TOP_FSYS1,
156 MUX_STAT_TOP_PERIC0,
157 MUX_STAT_TOP_PERIC1,
158 DIV_TOP0,
159 DIV_TOP1,
160 DIV_TOP2,
161 DIV_TOP3,
162 DIV_TOP4,
163 DIV_TOP_MSCL,
164 DIV_TOP_CAM10,
165 DIV_TOP_CAM11,
166 DIV_TOP_FSYS0,
167 DIV_TOP_FSYS1,
168 DIV_TOP_FSYS2,
169 DIV_TOP_PERIC0,
170 DIV_TOP_PERIC1,
171 DIV_TOP_PERIC2,
172 DIV_TOP_PERIC3,
173 DIV_TOP_PERIC4,
174 DIV_TOP_PLL_FREQ_DET,
175 DIV_STAT_TOP0,
176 DIV_STAT_TOP1,
177 DIV_STAT_TOP2,
178 DIV_STAT_TOP3,
179 DIV_STAT_TOP4,
180 DIV_STAT_TOP_MSCL,
181 DIV_STAT_TOP_CAM10,
182 DIV_STAT_TOP_CAM11,
183 DIV_STAT_TOP_FSYS0,
184 DIV_STAT_TOP_FSYS1,
185 DIV_STAT_TOP_FSYS2,
186 DIV_STAT_TOP_PERIC0,
187 DIV_STAT_TOP_PERIC1,
188 DIV_STAT_TOP_PERIC2,
189 DIV_STAT_TOP_PERIC3,
190 DIV_STAT_TOP_PLL_FREQ_DET,
191 ENABLE_ACLK_TOP,
192 ENABLE_SCLK_TOP,
193 ENABLE_SCLK_TOP_MSCL,
194 ENABLE_SCLK_TOP_CAM1,
195 ENABLE_SCLK_TOP_DISP,
196 ENABLE_SCLK_TOP_FSYS,
197 ENABLE_SCLK_TOP_PERIC,
198 ENABLE_IP_TOP,
199 ENABLE_CMU_TOP,
200 ENABLE_CMU_TOP_DIV_STAT,
201};
202
203/* list of all parent clock list */
204PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
205PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
206PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
207PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
208PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
209PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
210PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
211PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
212
213PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
214PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
215PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
216 "mout_mfc_pll_user", };
217PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
218
219PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
220 "mout_mphy_pll_user", };
221PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
222 "mout_bus_pll_user", };
223PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
224
225PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
226 "mout_mphy_pll_user", };
227PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
228 "mout_mphy_pll_user", };
229PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
230 "mout_mphy_pll_user", };
231
232PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
233PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
234
235PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
236PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
237PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
238PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
239PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
240
241PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
242 "oscclk", "ioclk_spdif_extclk", };
243PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
244 "mout_aud_pll_user_t",};
245PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
246 "mout_aud_pll_user_t",};
247
248PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
249
250static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
251 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
252};
253
254static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
255 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
256 FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
257 FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
258 /* Xi2s1SDI input clock for SPDIF */
259 FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
260 /* XspiCLK[4:0] input clock for SPI */
261 FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
262 FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
263 FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
264 FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
265 FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
266 /* Xi2s1SCLK input clock for I2S1_BCLK */
267 FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
268};
269
270static struct samsung_mux_clock top_mux_clks[] __initdata = {
271 /* MUX_SEL_TOP0 */
272 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
273 4, 1),
274 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
275 0, 1),
276
277 /* MUX_SEL_TOP1 */
278 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
279 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
280 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
281 MUX_SEL_TOP1, 8, 1),
282 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
283 MUX_SEL_TOP1, 4, 1),
284 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
285 MUX_SEL_TOP1, 0, 1),
286
287 /* MUX_SEL_TOP2 */
288 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
289 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
290 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
291 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
292 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
293 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
294 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
295 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
296 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
297 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
298 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
299 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
300
301 /* MUX_SEL_TOP3 */
302 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
303 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
304 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
305 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
306 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
307 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
308 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
309 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
310 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
311 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
312 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
313 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
314
315 /* MUX_SEL_TOP4 */
316 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
317 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
318 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
319 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
320 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
321 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
322
323 /* MUX_SEL_TOP_MSCL */
324 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
325 MUX_SEL_TOP_MSCL, 8, 1),
326 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
327 MUX_SEL_TOP_MSCL, 4, 1),
328 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
329 MUX_SEL_TOP_MSCL, 0, 1),
330
331 /* MUX_SEL_TOP_CAM1 */
332 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
333 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
334 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
335 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
336 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
337 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
338 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
339 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
340 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
341 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
342 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
343 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
344
345 /* MUX_SEL_TOP_FSYS0 */
346 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
347 MUX_SEL_TOP_FSYS0, 28, 1),
348 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
349 MUX_SEL_TOP_FSYS0, 24, 1),
350 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
351 MUX_SEL_TOP_FSYS0, 20, 1),
352 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
353 MUX_SEL_TOP_FSYS0, 16, 1),
354 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
355 MUX_SEL_TOP_FSYS0, 12, 1),
356 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
357 MUX_SEL_TOP_FSYS0, 8, 1),
358 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
359 MUX_SEL_TOP_FSYS0, 4, 1),
360 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
361 MUX_SEL_TOP_FSYS0, 0, 1),
362
363 /* MUX_SEL_TOP_FSYS1 */
364 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
365 MUX_SEL_TOP_FSYS1, 12, 1),
366 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
367 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
368 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
369 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
370 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
371 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
372
373 /* MUX_SEL_TOP_PERIC0 */
374 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
375 MUX_SEL_TOP_PERIC0, 28, 1),
376 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
377 MUX_SEL_TOP_PERIC0, 24, 1),
378 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
379 MUX_SEL_TOP_PERIC0, 20, 1),
380 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
381 MUX_SEL_TOP_PERIC0, 16, 1),
382 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
383 MUX_SEL_TOP_PERIC0, 12, 1),
384 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
385 MUX_SEL_TOP_PERIC0, 8, 1),
386 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
387 MUX_SEL_TOP_PERIC0, 4, 1),
388 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
389 MUX_SEL_TOP_PERIC0, 0, 1),
390
391 /* MUX_SEL_TOP_PERIC1 */
392 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
393 MUX_SEL_TOP_PERIC1, 16, 1),
394 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
395 MUX_SEL_TOP_PERIC1, 12, 2),
396 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
397 MUX_SEL_TOP_PERIC1, 4, 2),
398 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
399 MUX_SEL_TOP_PERIC1, 0, 2),
400
401 /* MUX_SEL_TOP_DISP */
402 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
403 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
404};
405
406static struct samsung_div_clock top_div_clks[] __initdata = {
407 /* DIV_TOP0 */
408 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
409 DIV_TOP0, 28, 3),
410 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
411 DIV_TOP0, 24, 3),
412 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
413 DIV_TOP0, 20, 3),
414 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
415 DIV_TOP0, 16, 3),
416 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
417 DIV_TOP0, 12, 3),
418 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
419 DIV_TOP0, 8, 3),
420 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
421 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
422 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
423 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
424
425 /* DIV_TOP1 */
426 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
427 DIV_TOP1, 28, 3),
428 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
429 DIV_TOP1, 24, 3),
430 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
431 DIV_TOP1, 20, 3),
432 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
433 DIV_TOP1, 12, 3),
434 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
435 DIV_TOP1, 8, 3),
436 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
437 DIV_TOP1, 0, 3),
438
439 /* DIV_TOP2 */
440 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
441 DIV_TOP2, 4, 3),
442 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
443 DIV_TOP2, 0, 3),
444
445 /* DIV_TOP3 */
446 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
447 "mout_bus_pll_user", DIV_TOP3, 24, 3),
448 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
449 "mout_bus_pll_user", DIV_TOP3, 20, 3),
450 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
451 "mout_bus_pll_user", DIV_TOP3, 16, 3),
452 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
453 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
454 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
455 "mout_bus_pll_user", DIV_TOP3, 8, 3),
456 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
457 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
458 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
459 "mout_bus_pll_user", DIV_TOP3, 0, 3),
460
461 /* DIV_TOP4 */
462 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
463 DIV_TOP4, 8, 3),
464 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
465 DIV_TOP4, 4, 3),
466 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
467 DIV_TOP4, 0, 3),
468
469 /* DIV_TOP_MSCL */
470 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
471 DIV_TOP_MSCL, 0, 4),
472
473 /* DIV_TOP_CAM10 */
474 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
475 DIV_TOP_CAM10, 24, 5),
476 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
477 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
478 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
479 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
480 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
481 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
482 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
483 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
484
485 /* DIV_TOP_CAM11 */
486 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
487 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
488 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
489 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
490 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
491 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
492 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
493 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
494 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
495 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 12, 4),
496 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
497 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 8, 4),
498
499 /* DIV_TOP_FSYS0 */
500 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
501 DIV_TOP_FSYS0, 16, 8),
502 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
503 DIV_TOP_FSYS0, 12, 4),
504 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
505 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
506 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
507 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
508
509 /* DIV_TOP_FSYS1 */
510 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
511 DIV_TOP_FSYS1, 4, 8),
512 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
513 DIV_TOP_FSYS1, 0, 4),
514
515 /* DIV_TOP_FSYS2 */
516 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
517 DIV_TOP_FSYS2, 12, 3),
518 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
519 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
520 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
521 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
522 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
523 DIV_TOP_FSYS2, 0, 4),
524
525 /* DIV_TOP_PERIC0 */
526 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
527 DIV_TOP_PERIC0, 16, 8),
528 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
529 DIV_TOP_PERIC0, 12, 4),
530 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
531 DIV_TOP_PERIC0, 4, 8),
532 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
533 DIV_TOP_PERIC0, 0, 4),
534
535 /* DIV_TOP_PERIC1 */
536 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
537 DIV_TOP_PERIC1, 4, 8),
538 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
539 DIV_TOP_PERIC1, 0, 4),
540
541 /* DIV_TOP_PERIC2 */
542 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
543 DIV_TOP_PERIC2, 8, 4),
544 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
545 DIV_TOP_PERIC2, 4, 4),
546 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
547 DIV_TOP_PERIC2, 0, 4),
548
549 /* DIV_TOP_PERIC3 */
550 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
551 DIV_TOP_PERIC3, 16, 6),
552 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
553 DIV_TOP_PERIC3, 8, 8),
554 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
555 DIV_TOP_PERIC3, 4, 4),
556 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
557 DIV_TOP_PERIC3, 0, 4),
558
559 /* DIV_TOP_PERIC4 */
560 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
561 DIV_TOP_PERIC4, 16, 8),
562 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
563 DIV_TOP_PERIC4, 12, 4),
564 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
565 DIV_TOP_PERIC4, 4, 8),
566 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
567 DIV_TOP_PERIC4, 0, 4),
568};
569
570static struct samsung_gate_clock top_gate_clks[] __initdata = {
571 /* ENABLE_ACLK_TOP */
572 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
573 ENABLE_ACLK_TOP, 30, 0, 0),
574 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
575 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
576 29, CLK_IGNORE_UNUSED, 0),
577 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
578 ENABLE_ACLK_TOP, 26,
579 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
580 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
581 ENABLE_ACLK_TOP, 25,
582 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
583 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
584 ENABLE_ACLK_TOP, 24,
585 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
586 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
587 ENABLE_ACLK_TOP, 23,
588 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
589 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
590 ENABLE_ACLK_TOP, 22,
591 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
592 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
593 ENABLE_ACLK_TOP, 21,
594 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
595 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
596 ENABLE_ACLK_TOP, 19,
597 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
598 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
599 ENABLE_ACLK_TOP, 18,
600 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
601 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
602 ENABLE_ACLK_TOP, 15,
603 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
604 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
605 ENABLE_ACLK_TOP, 14,
606 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
607 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
608 ENABLE_ACLK_TOP, 13,
609 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
610 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
611 ENABLE_ACLK_TOP, 12,
612 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
613 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
614 ENABLE_ACLK_TOP, 11,
615 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
616 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
617 ENABLE_ACLK_TOP, 10,
618 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
619 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
620 ENABLE_ACLK_TOP, 9,
621 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
622 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
623 ENABLE_ACLK_TOP, 8,
624 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
625 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
626 ENABLE_ACLK_TOP, 7,
627 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
628 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
629 ENABLE_ACLK_TOP, 6,
630 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
631 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
632 ENABLE_ACLK_TOP, 5,
633 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
634 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
635 ENABLE_ACLK_TOP, 3,
636 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
637 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
638 ENABLE_ACLK_TOP, 2,
639 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
640 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
641 ENABLE_ACLK_TOP, 0,
642 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
643
644 /* ENABLE_SCLK_TOP_MSCL */
645 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
646 ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
647
648 /* ENABLE_SCLK_TOP_CAM1 */
649 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
650 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
651 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
652 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
653 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
654 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
655 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
656 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
657 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
658 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
659 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
660 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
661 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
662 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
663
664 /* ENABLE_SCLK_TOP_DISP */
665 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
666 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
667 CLK_IGNORE_UNUSED, 0),
668
669 /* ENABLE_SCLK_TOP_FSYS */
670 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
671 ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
672 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
673 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
674 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
675 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
676 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
677 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
678 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
679 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
680 3, CLK_SET_RATE_PARENT, 0),
681 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
682 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
683 1, CLK_SET_RATE_PARENT, 0),
684 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
685 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
686 0, CLK_SET_RATE_PARENT, 0),
687
688 /* ENABLE_SCLK_TOP_PERIC */
689 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
690 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
691 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
692 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
693 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
694 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
695 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
696 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
697 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
698 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
699 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
700 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
701 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
702 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
703 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
704 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
705 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
706 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
707 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
708 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
709 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
710 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
711
712 /* MUX_ENABLE_TOP_PERIC1 */
713 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
714 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
715 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
716 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
717 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
718 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
719};
720
721/*
722 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
723 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
724 */
725static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
726 PLL_35XX_RATE(2500000000U, 625, 6, 0),
727 PLL_35XX_RATE(2400000000U, 500, 5, 0),
728 PLL_35XX_RATE(2300000000U, 575, 6, 0),
729 PLL_35XX_RATE(2200000000U, 550, 6, 0),
730 PLL_35XX_RATE(2100000000U, 350, 4, 0),
731 PLL_35XX_RATE(2000000000U, 500, 6, 0),
732 PLL_35XX_RATE(1900000000U, 475, 6, 0),
733 PLL_35XX_RATE(1800000000U, 375, 5, 0),
734 PLL_35XX_RATE(1700000000U, 425, 6, 0),
735 PLL_35XX_RATE(1600000000U, 400, 6, 0),
736 PLL_35XX_RATE(1500000000U, 250, 4, 0),
737 PLL_35XX_RATE(1400000000U, 350, 6, 0),
738 PLL_35XX_RATE(1332000000U, 222, 4, 0),
739 PLL_35XX_RATE(1300000000U, 325, 6, 0),
740 PLL_35XX_RATE(1200000000U, 500, 5, 1),
741 PLL_35XX_RATE(1100000000U, 550, 6, 1),
742 PLL_35XX_RATE(1086000000U, 362, 4, 1),
743 PLL_35XX_RATE(1066000000U, 533, 6, 1),
744 PLL_35XX_RATE(1000000000U, 500, 6, 1),
745 PLL_35XX_RATE(933000000U, 311, 4, 1),
746 PLL_35XX_RATE(921000000U, 307, 4, 1),
747 PLL_35XX_RATE(900000000U, 375, 5, 1),
748 PLL_35XX_RATE(825000000U, 275, 4, 1),
749 PLL_35XX_RATE(800000000U, 400, 6, 1),
750 PLL_35XX_RATE(733000000U, 733, 12, 1),
751 PLL_35XX_RATE(700000000U, 360, 6, 1),
752 PLL_35XX_RATE(667000000U, 222, 4, 1),
753 PLL_35XX_RATE(633000000U, 211, 4, 1),
754 PLL_35XX_RATE(600000000U, 500, 5, 2),
755 PLL_35XX_RATE(552000000U, 460, 5, 2),
756 PLL_35XX_RATE(550000000U, 550, 6, 2),
757 PLL_35XX_RATE(543000000U, 362, 4, 2),
758 PLL_35XX_RATE(533000000U, 533, 6, 2),
759 PLL_35XX_RATE(500000000U, 500, 6, 2),
760 PLL_35XX_RATE(444000000U, 370, 5, 2),
761 PLL_35XX_RATE(420000000U, 350, 5, 2),
762 PLL_35XX_RATE(400000000U, 400, 6, 2),
763 PLL_35XX_RATE(350000000U, 360, 6, 2),
764 PLL_35XX_RATE(333000000U, 222, 4, 2),
765 PLL_35XX_RATE(300000000U, 500, 5, 3),
766 PLL_35XX_RATE(266000000U, 532, 6, 3),
767 PLL_35XX_RATE(200000000U, 400, 6, 3),
768 PLL_35XX_RATE(166000000U, 332, 6, 3),
769 PLL_35XX_RATE(160000000U, 320, 6, 3),
770 PLL_35XX_RATE(133000000U, 552, 6, 4),
771 PLL_35XX_RATE(100000000U, 400, 6, 4),
772 { /* sentinel */ }
773};
774
775/* AUD_PLL */
776static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
777 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
778 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
779 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
780 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
781 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
782 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
783 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
784 PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
785 PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
786 { /* sentinel */ }
787};
788
789static struct samsung_pll_clock top_pll_clks[] __initdata = {
790 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
791 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
792 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
793 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
794};
795
796static struct samsung_cmu_info top_cmu_info __initdata = {
797 .pll_clks = top_pll_clks,
798 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
799 .mux_clks = top_mux_clks,
800 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
801 .div_clks = top_div_clks,
802 .nr_div_clks = ARRAY_SIZE(top_div_clks),
803 .gate_clks = top_gate_clks,
804 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
805 .fixed_clks = top_fixed_clks,
806 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
807 .fixed_factor_clks = top_fixed_factor_clks,
808 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
809 .nr_clk_ids = TOP_NR_CLK,
810 .clk_regs = top_clk_regs,
811 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
812};
813
814static void __init exynos5433_cmu_top_init(struct device_node *np)
815{
816 samsung_cmu_register_one(np, &top_cmu_info);
817}
818CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
819 exynos5433_cmu_top_init);
820
821/*
822 * Register offset definitions for CMU_CPIF
823 */
824#define MPHY_PLL_LOCK 0x0000
825#define MPHY_PLL_CON0 0x0100
826#define MPHY_PLL_CON1 0x0104
827#define MPHY_PLL_FREQ_DET 0x010c
828#define MUX_SEL_CPIF0 0x0200
829#define DIV_CPIF 0x0600
830#define ENABLE_SCLK_CPIF 0x0a00
831
832static unsigned long cpif_clk_regs[] __initdata = {
833 MPHY_PLL_LOCK,
834 MPHY_PLL_CON0,
835 MPHY_PLL_CON1,
836 MPHY_PLL_FREQ_DET,
837 MUX_SEL_CPIF0,
838 ENABLE_SCLK_CPIF,
839};
840
841/* list of all parent clock list */
842PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
843
844static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
845 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
846 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
847};
848
849static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
850 /* MUX_SEL_CPIF0 */
851 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
852 0, 1),
853};
854
855static struct samsung_div_clock cpif_div_clks[] __initdata = {
856 /* DIV_CPIF */
857 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
858 0, 6),
859};
860
861static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
862 /* ENABLE_SCLK_CPIF */
863 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
864 ENABLE_SCLK_CPIF, 9, 0, 0),
865 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
866 ENABLE_SCLK_CPIF, 4, 0, 0),
867};
868
869static struct samsung_cmu_info cpif_cmu_info __initdata = {
870 .pll_clks = cpif_pll_clks,
871 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
872 .mux_clks = cpif_mux_clks,
873 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
874 .div_clks = cpif_div_clks,
875 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
876 .gate_clks = cpif_gate_clks,
877 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
878 .nr_clk_ids = CPIF_NR_CLK,
879 .clk_regs = cpif_clk_regs,
880 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
881};
882
883static void __init exynos5433_cmu_cpif_init(struct device_node *np)
884{
885 samsung_cmu_register_one(np, &cpif_cmu_info);
886}
887CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
888 exynos5433_cmu_cpif_init);
889
890/*
891 * Register offset definitions for CMU_MIF
892 */
893#define MEM0_PLL_LOCK 0x0000
894#define MEM1_PLL_LOCK 0x0004
895#define BUS_PLL_LOCK 0x0008
896#define MFC_PLL_LOCK 0x000c
897#define MEM0_PLL_CON0 0x0100
898#define MEM0_PLL_CON1 0x0104
899#define MEM0_PLL_FREQ_DET 0x010c
900#define MEM1_PLL_CON0 0x0110
901#define MEM1_PLL_CON1 0x0114
902#define MEM1_PLL_FREQ_DET 0x011c
903#define BUS_PLL_CON0 0x0120
904#define BUS_PLL_CON1 0x0124
905#define BUS_PLL_FREQ_DET 0x012c
906#define MFC_PLL_CON0 0x0130
907#define MFC_PLL_CON1 0x0134
908#define MFC_PLL_FREQ_DET 0x013c
909#define MUX_SEL_MIF0 0x0200
910#define MUX_SEL_MIF1 0x0204
911#define MUX_SEL_MIF2 0x0208
912#define MUX_SEL_MIF3 0x020c
913#define MUX_SEL_MIF4 0x0210
914#define MUX_SEL_MIF5 0x0214
915#define MUX_SEL_MIF6 0x0218
916#define MUX_SEL_MIF7 0x021c
917#define MUX_ENABLE_MIF0 0x0300
918#define MUX_ENABLE_MIF1 0x0304
919#define MUX_ENABLE_MIF2 0x0308
920#define MUX_ENABLE_MIF3 0x030c
921#define MUX_ENABLE_MIF4 0x0310
922#define MUX_ENABLE_MIF5 0x0314
923#define MUX_ENABLE_MIF6 0x0318
924#define MUX_ENABLE_MIF7 0x031c
925#define MUX_STAT_MIF0 0x0400
926#define MUX_STAT_MIF1 0x0404
927#define MUX_STAT_MIF2 0x0408
928#define MUX_STAT_MIF3 0x040c
929#define MUX_STAT_MIF4 0x0410
930#define MUX_STAT_MIF5 0x0414
931#define MUX_STAT_MIF6 0x0418
932#define MUX_STAT_MIF7 0x041c
933#define DIV_MIF1 0x0604
934#define DIV_MIF2 0x0608
935#define DIV_MIF3 0x060c
936#define DIV_MIF4 0x0610
937#define DIV_MIF5 0x0614
938#define DIV_MIF_PLL_FREQ_DET 0x0618
939#define DIV_STAT_MIF1 0x0704
940#define DIV_STAT_MIF2 0x0708
941#define DIV_STAT_MIF3 0x070c
942#define DIV_STAT_MIF4 0x0710
943#define DIV_STAT_MIF5 0x0714
944#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
945#define ENABLE_ACLK_MIF0 0x0800
946#define ENABLE_ACLK_MIF1 0x0804
947#define ENABLE_ACLK_MIF2 0x0808
948#define ENABLE_ACLK_MIF3 0x080c
949#define ENABLE_PCLK_MIF 0x0900
950#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
951#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
952#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
953#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
954#define ENABLE_SCLK_MIF 0x0a00
955#define ENABLE_IP_MIF0 0x0b00
956#define ENABLE_IP_MIF1 0x0b04
957#define ENABLE_IP_MIF2 0x0b08
958#define ENABLE_IP_MIF3 0x0b0c
959#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
960#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
961#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
962#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
963#define CLKOUT_CMU_MIF 0x0c00
964#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
965#define DREX_FREQ_CTRL0 0x1000
966#define DREX_FREQ_CTRL1 0x1004
967#define PAUSE 0x1008
968#define DDRPHY_LOCK_CTRL 0x100c
969
970static unsigned long mif_clk_regs[] __initdata = {
971 MEM0_PLL_LOCK,
972 MEM1_PLL_LOCK,
973 BUS_PLL_LOCK,
974 MFC_PLL_LOCK,
975 MEM0_PLL_CON0,
976 MEM0_PLL_CON1,
977 MEM0_PLL_FREQ_DET,
978 MEM1_PLL_CON0,
979 MEM1_PLL_CON1,
980 MEM1_PLL_FREQ_DET,
981 BUS_PLL_CON0,
982 BUS_PLL_CON1,
983 BUS_PLL_FREQ_DET,
984 MFC_PLL_CON0,
985 MFC_PLL_CON1,
986 MFC_PLL_FREQ_DET,
987 MUX_SEL_MIF0,
988 MUX_SEL_MIF1,
989 MUX_SEL_MIF2,
990 MUX_SEL_MIF3,
991 MUX_SEL_MIF4,
992 MUX_SEL_MIF5,
993 MUX_SEL_MIF6,
994 MUX_SEL_MIF7,
995 MUX_ENABLE_MIF0,
996 MUX_ENABLE_MIF1,
997 MUX_ENABLE_MIF2,
998 MUX_ENABLE_MIF3,
999 MUX_ENABLE_MIF4,
1000 MUX_ENABLE_MIF5,
1001 MUX_ENABLE_MIF6,
1002 MUX_ENABLE_MIF7,
1003 MUX_STAT_MIF0,
1004 MUX_STAT_MIF1,
1005 MUX_STAT_MIF2,
1006 MUX_STAT_MIF3,
1007 MUX_STAT_MIF4,
1008 MUX_STAT_MIF5,
1009 MUX_STAT_MIF6,
1010 MUX_STAT_MIF7,
1011 DIV_MIF1,
1012 DIV_MIF2,
1013 DIV_MIF3,
1014 DIV_MIF4,
1015 DIV_MIF5,
1016 DIV_MIF_PLL_FREQ_DET,
1017 DIV_STAT_MIF1,
1018 DIV_STAT_MIF2,
1019 DIV_STAT_MIF3,
1020 DIV_STAT_MIF4,
1021 DIV_STAT_MIF5,
1022 DIV_STAT_MIF_PLL_FREQ_DET,
1023 ENABLE_ACLK_MIF0,
1024 ENABLE_ACLK_MIF1,
1025 ENABLE_ACLK_MIF2,
1026 ENABLE_ACLK_MIF3,
1027 ENABLE_PCLK_MIF,
1028 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
1029 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1030 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1031 ENABLE_PCLK_MIF_SECURE_RTC,
1032 ENABLE_SCLK_MIF,
1033 ENABLE_IP_MIF0,
1034 ENABLE_IP_MIF1,
1035 ENABLE_IP_MIF2,
1036 ENABLE_IP_MIF3,
1037 ENABLE_IP_MIF_SECURE_DREX0_TZ,
1038 ENABLE_IP_MIF_SECURE_DREX1_TZ,
1039 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1040 ENABLE_IP_MIF_SECURE_RTC,
1041 CLKOUT_CMU_MIF,
1042 CLKOUT_CMU_MIF_DIV_STAT,
1043 DREX_FREQ_CTRL0,
1044 DREX_FREQ_CTRL1,
1045 PAUSE,
1046 DDRPHY_LOCK_CTRL,
1047};
1048
1049static struct samsung_pll_clock mif_pll_clks[] __initdata = {
1050 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1051 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
1052 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1053 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
1054 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1055 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
1056 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1057 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
1058};
1059
1060/* list of all parent clock list */
1061PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
1062PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
1063PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
1064PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
1065PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
1066PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
1067PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
1068PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
1069
1070PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1071PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1072PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1073PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1074
1075PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
1076PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1077
1078PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
1079 "mout_bus_pll_div2", };
1080PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1081
1082PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1083 "sclk_mphy_pll", };
1084PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1085 "mout_mfc_pll_div2", };
1086PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
1087PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1088 "sclk_mphy_pll", };
1089PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1090 "mout_mfc_pll_div2", };
1091
1092PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1093 "sclk_mphy_pll", };
1094PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1095 "mout_mfc_pll_div2", };
1096PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1097PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1098PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1099
1100PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1101PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1102
1103PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1104 "sclk_mphy_pll", };
1105PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1106 "mout_mfc_pll_div2", };
1107PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1108PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1109
1110static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
1111 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1112 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1113 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1114 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1115 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1116};
1117
1118static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1119 /* MUX_SEL_MIF0 */
1120 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1121 MUX_SEL_MIF0, 28, 1),
1122 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1123 MUX_SEL_MIF0, 24, 1),
1124 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1125 MUX_SEL_MIF0, 20, 1),
1126 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1127 MUX_SEL_MIF0, 16, 1),
1128 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1129 12, 1),
1130 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1131 8, 1),
1132 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1133 4, 1),
1134 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1135 0, 1),
1136
1137 /* MUX_SEL_MIF1 */
1138 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1139 MUX_SEL_MIF1, 24, 1),
1140 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1141 MUX_SEL_MIF1, 20, 1),
1142 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1143 MUX_SEL_MIF1, 16, 1),
1144 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1145 MUX_SEL_MIF1, 12, 1),
1146 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1147 MUX_SEL_MIF1, 8, 1),
1148 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1149 MUX_SEL_MIF1, 4, 1),
1150
1151 /* MUX_SEL_MIF2 */
1152 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1153 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1154 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1155 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1156
1157 /* MUX_SEL_MIF3 */
1158 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1159 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1160 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1161 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1162
1163 /* MUX_SEL_MIF4 */
1164 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1165 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1166 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1167 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1168 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1169 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1170 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1171 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1172 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1173 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1174 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1175 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1176
1177 /* MUX_SEL_MIF5 */
1178 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1179 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1180 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1181 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1182 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1183 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1184 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1185 MUX_SEL_MIF5, 8, 1),
1186 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1187 MUX_SEL_MIF5, 4, 1),
1188 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1189 MUX_SEL_MIF5, 0, 1),
1190
1191 /* MUX_SEL_MIF6 */
1192 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1193 MUX_SEL_MIF6, 8, 1),
1194 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1195 MUX_SEL_MIF6, 4, 1),
1196 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1197 MUX_SEL_MIF6, 0, 1),
1198
1199 /* MUX_SEL_MIF7 */
1200 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1201 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1202 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1203 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1204 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1205 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1206 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1207 MUX_SEL_MIF7, 8, 1),
1208 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1209 MUX_SEL_MIF7, 4, 1),
1210 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1211 MUX_SEL_MIF7, 0, 1),
1212};
1213
1214static struct samsung_div_clock mif_div_clks[] __initdata = {
1215 /* DIV_MIF1 */
1216 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1217 DIV_MIF1, 16, 2),
1218 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1219 12, 2),
1220 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1221 8, 2),
1222 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1223 4, 4),
1224
1225 /* DIV_MIF2 */
1226 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1227 DIV_MIF2, 20, 3),
1228 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1229 DIV_MIF2, 16, 4),
1230 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1231 DIV_MIF2, 12, 4),
1232 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1233 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1234 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1235 DIV_MIF2, 4, 2),
1236 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1237 DIV_MIF2, 0, 3),
1238
1239 /* DIV_MIF3 */
1240 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1241 DIV_MIF3, 16, 4),
1242 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1243 DIV_MIF3, 4, 3),
1244 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1245 DIV_MIF3, 0, 3),
1246
1247 /* DIV_MIF4 */
1248 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1249 DIV_MIF4, 24, 4),
1250 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1251 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1252 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1253 DIV_MIF4, 16, 4),
1254 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1255 DIV_MIF4, 12, 4),
1256 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1257 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1258 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1259 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1260 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1261 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1262
1263 /* DIV_MIF5 */
1264 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1265 0, 3),
1266};
1267
1268static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1269 /* ENABLE_ACLK_MIF0 */
1270 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1271 19, CLK_IGNORE_UNUSED, 0),
1272 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1273 18, CLK_IGNORE_UNUSED, 0),
1274 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1275 17, CLK_IGNORE_UNUSED, 0),
1276 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1277 16, CLK_IGNORE_UNUSED, 0),
1278 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1279 15, CLK_IGNORE_UNUSED, 0),
1280 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1281 14, CLK_IGNORE_UNUSED, 0),
1282 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1283 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1284 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1285 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1286 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1287 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1288 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1289 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1290 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1291 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1292 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1293 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1294 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1295 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1296 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1297 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1298 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1299 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1300 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1301 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1302 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1303 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1304 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1305 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1306 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1307 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1308 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1309 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1310
1311 /* ENABLE_ACLK_MIF1 */
1312 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1313 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1314 CLK_IGNORE_UNUSED, 0),
1315 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1316 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1317 27, CLK_IGNORE_UNUSED, 0),
1318 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1319 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1320 26, CLK_IGNORE_UNUSED, 0),
1321 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1322 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1323 25, CLK_IGNORE_UNUSED, 0),
1324 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1325 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1326 24, CLK_IGNORE_UNUSED, 0),
1327 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1328 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1329 23, CLK_IGNORE_UNUSED, 0),
1330 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1331 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1332 22, CLK_IGNORE_UNUSED, 0),
1333 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1334 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1335 21, CLK_IGNORE_UNUSED, 0),
1336 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1337 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1338 20, CLK_IGNORE_UNUSED, 0),
1339 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1340 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1341 19, CLK_IGNORE_UNUSED, 0),
1342 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1343 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1344 18, CLK_IGNORE_UNUSED, 0),
1345 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1346 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1347 17, CLK_IGNORE_UNUSED, 0),
1348 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1349 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1350 16, CLK_IGNORE_UNUSED, 0),
1351 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1352 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1353 15, CLK_IGNORE_UNUSED, 0),
1354 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1355 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1356 14, CLK_IGNORE_UNUSED, 0),
1357 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1358 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1359 13, CLK_IGNORE_UNUSED, 0),
1360 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1361 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1362 12, CLK_IGNORE_UNUSED, 0),
1363 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1364 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1365 11, CLK_IGNORE_UNUSED, 0),
1366 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1367 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1368 10, CLK_IGNORE_UNUSED, 0),
1369 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1370 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1371 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1372 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1373 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1374 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1375 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1376 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1377 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1378 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1379 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1380 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1381 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1382 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1383 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1384 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1385 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1386 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1387 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1388 0, CLK_IGNORE_UNUSED, 0),
1389
1390 /* ENABLE_ACLK_MIF2 */
1391 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1392 ENABLE_ACLK_MIF2, 20, 0, 0),
1393 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1394 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1395 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1396 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1397 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1398 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1399 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1400 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1401 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1402 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1403 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1404 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1405 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1406 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1407 CLK_IGNORE_UNUSED, 0),
1408 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1409 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1410 5, CLK_IGNORE_UNUSED, 0),
1411 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1412 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1413 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1414 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1415 3, CLK_IGNORE_UNUSED, 0),
1416 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1417 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1418
1419 /* ENABLE_ACLK_MIF3 */
1420 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1421 ENABLE_ACLK_MIF3, 4,
1422 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1423 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1424 ENABLE_ACLK_MIF3, 1,
1425 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1426 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1427 ENABLE_ACLK_MIF3, 0,
1428 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1429
1430 /* ENABLE_PCLK_MIF */
1431 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1432 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1433 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1434 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1435 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1436 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1437 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1438 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1439 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1440 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1441 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1442 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1443 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1444 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1445 CLK_IGNORE_UNUSED, 0),
1446 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1447 ENABLE_PCLK_MIF, 19, 0, 0),
1448 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1449 ENABLE_PCLK_MIF, 18, 0, 0),
1450 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1451 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1452 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1453 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1454 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1455 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1456 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1457 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1458 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1459 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1460 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1461 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1462 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1463 ENABLE_PCLK_MIF, 11, 0, 0),
1464 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1465 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1466 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1467 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1468 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1469 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1470 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1471 ENABLE_PCLK_MIF, 7, 0, 0),
1472 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1473 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1474 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1475 ENABLE_PCLK_MIF, 5, 0, 0),
1476 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1477 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1478 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1479 ENABLE_PCLK_MIF, 2, 0, 0),
1480 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1481 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1482
1483 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1484 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1485 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
1486
1487 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1488 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1489 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
1490
1491 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1492 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1493 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1494
1495 /* ENABLE_PCLK_MIF_SECURE_RTC */
1496 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1497 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1498
1499 /* ENABLE_SCLK_MIF */
1500 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1501 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1502 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1503 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1504 14, CLK_IGNORE_UNUSED, 0),
1505 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1506 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1507 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1508 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1509 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1510 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1511 7, CLK_IGNORE_UNUSED, 0),
1512 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1513 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1514 6, CLK_IGNORE_UNUSED, 0),
1515 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1516 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1517 5, CLK_IGNORE_UNUSED, 0),
1518 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1519 ENABLE_SCLK_MIF, 4,
1520 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1521 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1522 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1523 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1524 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1525 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1526 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1527 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1528 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1529};
1530
1531static struct samsung_cmu_info mif_cmu_info __initdata = {
1532 .pll_clks = mif_pll_clks,
1533 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1534 .mux_clks = mif_mux_clks,
1535 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1536 .div_clks = mif_div_clks,
1537 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1538 .gate_clks = mif_gate_clks,
1539 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1540 .fixed_factor_clks = mif_fixed_factor_clks,
1541 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
1542 .nr_clk_ids = MIF_NR_CLK,
1543 .clk_regs = mif_clk_regs,
1544 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1545};
1546
1547static void __init exynos5433_cmu_mif_init(struct device_node *np)
1548{
1549 samsung_cmu_register_one(np, &mif_cmu_info);
1550}
1551CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1552 exynos5433_cmu_mif_init);
1553
1554/*
1555 * Register offset definitions for CMU_PERIC
1556 */
1557#define DIV_PERIC 0x0600
1558#define DIV_STAT_PERIC 0x0700
1559#define ENABLE_ACLK_PERIC 0x0800
1560#define ENABLE_PCLK_PERIC0 0x0900
1561#define ENABLE_PCLK_PERIC1 0x0904
1562#define ENABLE_SCLK_PERIC 0x0A00
1563#define ENABLE_IP_PERIC0 0x0B00
1564#define ENABLE_IP_PERIC1 0x0B04
1565#define ENABLE_IP_PERIC2 0x0B08
1566
1567static unsigned long peric_clk_regs[] __initdata = {
1568 DIV_PERIC,
1569 DIV_STAT_PERIC,
1570 ENABLE_ACLK_PERIC,
1571 ENABLE_PCLK_PERIC0,
1572 ENABLE_PCLK_PERIC1,
1573 ENABLE_SCLK_PERIC,
1574 ENABLE_IP_PERIC0,
1575 ENABLE_IP_PERIC1,
1576 ENABLE_IP_PERIC2,
1577};
1578
1579static struct samsung_div_clock peric_div_clks[] __initdata = {
1580 /* DIV_PERIC */
1581 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1582 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1583};
1584
1585static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1586 /* ENABLE_ACLK_PERIC */
1587 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1588 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1589 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1590 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1591 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1592 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1593 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1594 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1595
1596 /* ENABLE_PCLK_PERIC0 */
1597 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1598 31, CLK_SET_RATE_PARENT, 0),
1599 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1600 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1601 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1602 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1603 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1604 28, CLK_SET_RATE_PARENT, 0),
1605 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1606 26, CLK_SET_RATE_PARENT, 0),
1607 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1608 25, CLK_SET_RATE_PARENT, 0),
1609 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1610 24, CLK_SET_RATE_PARENT, 0),
1611 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1612 23, CLK_SET_RATE_PARENT, 0),
1613 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1614 22, CLK_SET_RATE_PARENT, 0),
1615 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1616 21, CLK_SET_RATE_PARENT, 0),
1617 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1618 20, CLK_SET_RATE_PARENT, 0),
1619 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1620 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1621 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1622 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1623 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1624 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1625 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1626 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1627 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1628 ENABLE_PCLK_PERIC0, 15,
1629 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1630 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1631 14, CLK_SET_RATE_PARENT, 0),
1632 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1633 13, CLK_SET_RATE_PARENT, 0),
1634 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1635 12, CLK_SET_RATE_PARENT, 0),
1636 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1637 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1638 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1639 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1640 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1641 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1642 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1643 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1644 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1645 7, CLK_SET_RATE_PARENT, 0),
1646 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1647 6, CLK_SET_RATE_PARENT, 0),
1648 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1649 5, CLK_SET_RATE_PARENT, 0),
1650 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1651 4, CLK_SET_RATE_PARENT, 0),
1652 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1653 3, CLK_SET_RATE_PARENT, 0),
1654 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1655 2, CLK_SET_RATE_PARENT, 0),
1656 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1657 1, CLK_SET_RATE_PARENT, 0),
1658 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1659 0, CLK_SET_RATE_PARENT, 0),
1660
1661 /* ENABLE_PCLK_PERIC1 */
1662 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1663 9, CLK_SET_RATE_PARENT, 0),
1664 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1665 8, CLK_SET_RATE_PARENT, 0),
1666 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1667 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1668 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1669 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1670 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1671 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1672 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1673 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1674 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1675 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1676 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1677 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1678 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1679 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1680 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1681 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1682
1683 /* ENABLE_SCLK_PERIC */
1684 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1685 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1686 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1687 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1688 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1689 19, CLK_SET_RATE_PARENT, 0),
1690 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1691 18, CLK_SET_RATE_PARENT, 0),
1692 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1693 17, 0, 0),
1694 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1695 16, 0, 0),
1696 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1697 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1698 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1699 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1700 ENABLE_SCLK_PERIC, 12,
1701 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1702 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1703 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1704 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1705 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1706 CLK_SET_RATE_PARENT, 0),
1707 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1708 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1709 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1710 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1711 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1712 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1713 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1714 5, CLK_SET_RATE_PARENT, 0),
1715 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1716 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1717 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1718 3, CLK_SET_RATE_PARENT, 0),
1719 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1720 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1721 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1722 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1723 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1724 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1725};
1726
1727static struct samsung_cmu_info peric_cmu_info __initdata = {
1728 .div_clks = peric_div_clks,
1729 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1730 .gate_clks = peric_gate_clks,
1731 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1732 .nr_clk_ids = PERIC_NR_CLK,
1733 .clk_regs = peric_clk_regs,
1734 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1735};
1736
1737static void __init exynos5433_cmu_peric_init(struct device_node *np)
1738{
1739 samsung_cmu_register_one(np, &peric_cmu_info);
1740}
1741
1742CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1743 exynos5433_cmu_peric_init);
1744
1745/*
1746 * Register offset definitions for CMU_PERIS
1747 */
1748#define ENABLE_ACLK_PERIS 0x0800
1749#define ENABLE_PCLK_PERIS 0x0900
1750#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1751#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1752#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1753#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1754#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1755#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1756#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1757#define ENABLE_SCLK_PERIS 0x0a00
1758#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1759#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1760#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1761#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1762#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1763#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1764#define ENABLE_IP_PERIS0 0x0b00
1765#define ENABLE_IP_PERIS1 0x0b04
1766#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1767#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1768#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1769#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1770#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1771#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1772#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1773
1774static unsigned long peris_clk_regs[] __initdata = {
1775 ENABLE_ACLK_PERIS,
1776 ENABLE_PCLK_PERIS,
1777 ENABLE_PCLK_PERIS_SECURE_TZPC,
1778 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1779 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1780 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1781 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1782 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1783 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1784 ENABLE_SCLK_PERIS,
1785 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1786 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1787 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1788 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1789 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1790 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1791 ENABLE_IP_PERIS0,
1792 ENABLE_IP_PERIS1,
1793 ENABLE_IP_PERIS_SECURE_TZPC,
1794 ENABLE_IP_PERIS_SECURE_SECKEY,
1795 ENABLE_IP_PERIS_SECURE_CHIPID,
1796 ENABLE_IP_PERIS_SECURE_TOPRTC,
1797 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1798 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1799 ENABLE_IP_PERIS_SECURE_OTP_CON,
1800};
1801
1802static struct samsung_gate_clock peris_gate_clks[] __initdata = {
1803 /* ENABLE_ACLK_PERIS */
1804 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1805 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1806 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1807 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1808 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1809 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1810
1811 /* ENABLE_PCLK_PERIS */
1812 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1813 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1814 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1815 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1816 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1817 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1818 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1819 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1820 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1821 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1822 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1823 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1824 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1825 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1826 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1827 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1828 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1829 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1830 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1831 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1832
1833 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1834 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1835 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0),
1836 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1837 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0),
1838 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1839 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0),
1840 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1841 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0),
1842 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1843 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0),
1844 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1845 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0),
1846 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1847 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0),
1848 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1849 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0),
1850 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1851 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0),
1852 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1853 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0),
1854 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1855 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0),
1856 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1857 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0),
1858 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1859 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0),
1860
1861 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1862 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1863 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0),
1864
1865 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1866 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1867 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0),
1868
1869 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1870 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1871 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1872
1873 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1874 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1875 "aclk_peris_66",
1876 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1877
1878 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1879 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1880 "aclk_peris_66",
1881 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1882
1883 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1884 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1885 "aclk_peris_66",
1886 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1887
1888 /* ENABLE_SCLK_PERIS */
1889 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1890 ENABLE_SCLK_PERIS, 10, 0, 0),
1891 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1892 ENABLE_SCLK_PERIS, 4, 0, 0),
1893 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1894 ENABLE_SCLK_PERIS, 3, 0, 0),
1895
1896 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1897 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1898 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0),
1899
1900 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1901 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1902 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
1903
1904 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1905 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1906 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1907
1908 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1909 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1910 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1911
1912 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1913 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1914 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1915
1916 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1917 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1918 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1919};
1920
1921static struct samsung_cmu_info peris_cmu_info __initdata = {
1922 .gate_clks = peris_gate_clks,
1923 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1924 .nr_clk_ids = PERIS_NR_CLK,
1925 .clk_regs = peris_clk_regs,
1926 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1927};
1928
1929static void __init exynos5433_cmu_peris_init(struct device_node *np)
1930{
1931 samsung_cmu_register_one(np, &peris_cmu_info);
1932}
1933
1934CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1935 exynos5433_cmu_peris_init);
1936
1937/*
1938 * Register offset definitions for CMU_FSYS
1939 */
1940#define MUX_SEL_FSYS0 0x0200
1941#define MUX_SEL_FSYS1 0x0204
1942#define MUX_SEL_FSYS2 0x0208
1943#define MUX_SEL_FSYS3 0x020c
1944#define MUX_SEL_FSYS4 0x0210
1945#define MUX_ENABLE_FSYS0 0x0300
1946#define MUX_ENABLE_FSYS1 0x0304
1947#define MUX_ENABLE_FSYS2 0x0308
1948#define MUX_ENABLE_FSYS3 0x030c
1949#define MUX_ENABLE_FSYS4 0x0310
1950#define MUX_STAT_FSYS0 0x0400
1951#define MUX_STAT_FSYS1 0x0404
1952#define MUX_STAT_FSYS2 0x0408
1953#define MUX_STAT_FSYS3 0x040c
1954#define MUX_STAT_FSYS4 0x0410
1955#define MUX_IGNORE_FSYS2 0x0508
1956#define MUX_IGNORE_FSYS3 0x050c
1957#define ENABLE_ACLK_FSYS0 0x0800
1958#define ENABLE_ACLK_FSYS1 0x0804
1959#define ENABLE_PCLK_FSYS 0x0900
1960#define ENABLE_SCLK_FSYS 0x0a00
1961#define ENABLE_IP_FSYS0 0x0b00
1962#define ENABLE_IP_FSYS1 0x0b04
1963
1964/* list of all parent clock list */
1965PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
1966PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
1967PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1968PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
1969PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1970PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1971PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1972PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1973PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1974
1975PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1976 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1977PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1978 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1979PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1980 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1981PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1982 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1983PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1984 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1985PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1986 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1987PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1988 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1989PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1990 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1991PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1992 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1993PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1994 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1995PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1996 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1997PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1998 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1999PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
2000 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
2001PNAME(mout_sclk_mphy_p)
2002 = { "mout_sclk_ufs_mphy_user",
2003 "mout_phyclk_lli_mphy_to_ufs_user", };
2004
2005static unsigned long fsys_clk_regs[] __initdata = {
2006 MUX_SEL_FSYS0,
2007 MUX_SEL_FSYS1,
2008 MUX_SEL_FSYS2,
2009 MUX_SEL_FSYS3,
2010 MUX_SEL_FSYS4,
2011 MUX_ENABLE_FSYS0,
2012 MUX_ENABLE_FSYS1,
2013 MUX_ENABLE_FSYS2,
2014 MUX_ENABLE_FSYS3,
2015 MUX_ENABLE_FSYS4,
2016 MUX_STAT_FSYS0,
2017 MUX_STAT_FSYS1,
2018 MUX_STAT_FSYS2,
2019 MUX_STAT_FSYS3,
2020 MUX_STAT_FSYS4,
2021 MUX_IGNORE_FSYS2,
2022 MUX_IGNORE_FSYS3,
2023 ENABLE_ACLK_FSYS0,
2024 ENABLE_ACLK_FSYS1,
2025 ENABLE_PCLK_FSYS,
2026 ENABLE_SCLK_FSYS,
2027 ENABLE_IP_FSYS0,
2028 ENABLE_IP_FSYS1,
2029};
2030
2031static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
2032 /* PHY clocks from USBDRD30_PHY */
2033 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2034 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2035 CLK_IS_ROOT, 60000000),
2036 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2037 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2038 CLK_IS_ROOT, 125000000),
2039 /* PHY clocks from USBHOST30_PHY */
2040 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2041 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2042 CLK_IS_ROOT, 60000000),
2043 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2044 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2045 CLK_IS_ROOT, 125000000),
2046 /* PHY clocks from USBHOST20_PHY */
2047 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2048 "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
2049 60000000),
2050 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2051 "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
2052 60000000),
2053 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2054 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2055 CLK_IS_ROOT, 48000000),
2056 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2057 "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
2058 60000000),
2059 /* PHY clocks from UFS_PHY */
2060 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2061 NULL, CLK_IS_ROOT, 300000000),
2062 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2063 NULL, CLK_IS_ROOT, 300000000),
2064 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2065 NULL, CLK_IS_ROOT, 300000000),
2066 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2067 NULL, CLK_IS_ROOT, 300000000),
2068 /* PHY clocks from LLI_PHY */
2069 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2070 NULL, CLK_IS_ROOT, 26000000),
2071};
2072
2073static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
2074 /* MUX_SEL_FSYS0 */
2075 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2076 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2077 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2078 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2079
2080 /* MUX_SEL_FSYS1 */
2081 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2082 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2083 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2084 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2085 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2086 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2087 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2088 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2089 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2090 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2091 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2092 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2093 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2094 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2095
2096 /* MUX_SEL_FSYS2 */
2097 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2098 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2099 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2100 MUX_SEL_FSYS2, 28, 1),
2101 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2102 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2103 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2104 MUX_SEL_FSYS2, 24, 1),
2105 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2106 "mout_phyclk_usbhost20_phy_hsic1",
2107 mout_phyclk_usbhost20_phy_hsic1_p,
2108 MUX_SEL_FSYS2, 20, 1),
2109 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2110 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2111 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2112 MUX_SEL_FSYS2, 16, 1),
2113 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2114 "mout_phyclk_usbhost20_phy_phyclock_user",
2115 mout_phyclk_usbhost20_phy_phyclock_user_p,
2116 MUX_SEL_FSYS2, 12, 1),
2117 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2118 "mout_phyclk_usbhost20_phy_freeclk_user",
2119 mout_phyclk_usbhost20_phy_freeclk_user_p,
2120 MUX_SEL_FSYS2, 8, 1),
2121 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2122 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2123 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2124 MUX_SEL_FSYS2, 4, 1),
2125 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2126 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2127 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2128 MUX_SEL_FSYS2, 0, 1),
2129
2130 /* MUX_SEL_FSYS3 */
2131 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2132 "mout_phyclk_ufs_rx1_symbol_user",
2133 mout_phyclk_ufs_rx1_symbol_user_p,
2134 MUX_SEL_FSYS3, 16, 1),
2135 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2136 "mout_phyclk_ufs_rx0_symbol_user",
2137 mout_phyclk_ufs_rx0_symbol_user_p,
2138 MUX_SEL_FSYS3, 12, 1),
2139 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2140 "mout_phyclk_ufs_tx1_symbol_user",
2141 mout_phyclk_ufs_tx1_symbol_user_p,
2142 MUX_SEL_FSYS3, 8, 1),
2143 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2144 "mout_phyclk_ufs_tx0_symbol_user",
2145 mout_phyclk_ufs_tx0_symbol_user_p,
2146 MUX_SEL_FSYS3, 4, 1),
2147 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2148 "mout_phyclk_lli_mphy_to_ufs_user",
2149 mout_phyclk_lli_mphy_to_ufs_user_p,
2150 MUX_SEL_FSYS3, 0, 1),
2151
2152 /* MUX_SEL_FSYS4 */
2153 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2154 MUX_SEL_FSYS4, 0, 1),
2155};
2156
2157static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2158 /* ENABLE_ACLK_FSYS0 */
2159 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2160 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2161 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2162 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2163 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2164 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2165 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2166 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2167 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2168 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2169 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2170 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2171 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2172 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2173 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2174 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2175 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2176 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2177 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2178 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2179 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2180 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2181
2182 /* ENABLE_ACLK_FSYS1 */
2183 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2184 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2185 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2186 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2187 26, CLK_IGNORE_UNUSED, 0),
2188 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2189 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2190 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2191 ENABLE_ACLK_FSYS1, 24, 0, 0),
2192 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2193 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2194 22, CLK_IGNORE_UNUSED, 0),
2195 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2196 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2197 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2198 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2199 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2200 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2201 13, 0, 0),
2202 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2203 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2204 12, 0, 0),
2205 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2206 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2207 11, CLK_IGNORE_UNUSED, 0),
2208 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2209 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2210 10, CLK_IGNORE_UNUSED, 0),
2211 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2212 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2213 9, CLK_IGNORE_UNUSED, 0),
2214 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2215 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2216 8, CLK_IGNORE_UNUSED, 0),
2217 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2218 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2219 7, CLK_IGNORE_UNUSED, 0),
2220 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2221 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2222 6, CLK_IGNORE_UNUSED, 0),
2223 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2224 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2225 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2226 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2227 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2228 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2229 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2230 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2231 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2232 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2233 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2234 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2235
2236 /* ENABLE_PCLK_FSYS */
2237 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2238 ENABLE_PCLK_FSYS, 17, 0, 0),
2239 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2240 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2241 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2242 ENABLE_PCLK_FSYS, 14, 0, 0),
2243 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2244 ENABLE_PCLK_FSYS, 13, 0, 0),
2245 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2246 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2247 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2248 ENABLE_PCLK_FSYS, 5, 0, 0),
2249 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2250 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2251 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2252 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2253 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2254 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2255 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2256 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2257 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2258 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2259 0, CLK_IGNORE_UNUSED, 0),
2260
2261 /* ENABLE_SCLK_FSYS */
2262 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2263 ENABLE_SCLK_FSYS, 21, 0, 0),
2264 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2265 "phyclk_usbhost30_uhost30_pipe_pclk",
2266 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2267 ENABLE_SCLK_FSYS, 18, 0, 0),
2268 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2269 "phyclk_usbhost30_uhost30_phyclock",
2270 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2271 ENABLE_SCLK_FSYS, 17, 0, 0),
2272 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2273 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2274 16, 0, 0),
2275 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2276 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2277 15, 0, 0),
2278 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2279 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2280 14, 0, 0),
2281 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2282 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2283 13, 0, 0),
2284 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2285 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2286 12, 0, 0),
2287 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2288 "phyclk_usbhost20_phy_clk48mohci",
2289 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2290 ENABLE_SCLK_FSYS, 11, 0, 0),
2291 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2292 "phyclk_usbhost20_phy_phyclock",
2293 "mout_phyclk_usbhost20_phy_phyclock_user",
2294 ENABLE_SCLK_FSYS, 10, 0, 0),
2295 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2296 "phyclk_usbhost20_phy_freeclk",
2297 "mout_phyclk_usbhost20_phy_freeclk_user",
2298 ENABLE_SCLK_FSYS, 9, 0, 0),
2299 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2300 "phyclk_usbdrd30_udrd30_pipe_pclk",
2301 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2302 ENABLE_SCLK_FSYS, 8, 0, 0),
2303 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2304 "phyclk_usbdrd30_udrd30_phyclock",
2305 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2306 ENABLE_SCLK_FSYS, 7, 0, 0),
2307 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2308 ENABLE_SCLK_FSYS, 6, 0, 0),
2309 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2310 ENABLE_SCLK_FSYS, 5, 0, 0),
2311 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2312 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2313 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2314 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2315 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2316 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2317 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2318 ENABLE_SCLK_FSYS, 1, 0, 0),
2319 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2320 ENABLE_SCLK_FSYS, 0, 0, 0),
2321
2322 /* ENABLE_IP_FSYS0 */
2323 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2324 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2325};
2326
2327static struct samsung_cmu_info fsys_cmu_info __initdata = {
2328 .mux_clks = fsys_mux_clks,
2329 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2330 .gate_clks = fsys_gate_clks,
2331 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
2332 .fixed_clks = fsys_fixed_clks,
2333 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
2334 .nr_clk_ids = FSYS_NR_CLK,
2335 .clk_regs = fsys_clk_regs,
2336 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2337};
2338
2339static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2340{
2341 samsung_cmu_register_one(np, &fsys_cmu_info);
2342}
2343
2344CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2345 exynos5433_cmu_fsys_init);
2346
2347/*
2348 * Register offset definitions for CMU_G2D
2349 */
2350#define MUX_SEL_G2D0 0x0200
2351#define MUX_SEL_ENABLE_G2D0 0x0300
2352#define MUX_SEL_STAT_G2D0 0x0400
2353#define DIV_G2D 0x0600
2354#define DIV_STAT_G2D 0x0700
2355#define DIV_ENABLE_ACLK_G2D 0x0800
2356#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2357#define DIV_ENABLE_PCLK_G2D 0x0900
2358#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2359#define DIV_ENABLE_IP_G2D0 0x0b00
2360#define DIV_ENABLE_IP_G2D1 0x0b04
2361#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2362
2363static unsigned long g2d_clk_regs[] __initdata = {
2364 MUX_SEL_G2D0,
2365 MUX_SEL_ENABLE_G2D0,
2366 MUX_SEL_STAT_G2D0,
2367 DIV_G2D,
2368 DIV_STAT_G2D,
2369 DIV_ENABLE_ACLK_G2D,
2370 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2371 DIV_ENABLE_PCLK_G2D,
2372 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2373 DIV_ENABLE_IP_G2D0,
2374 DIV_ENABLE_IP_G2D1,
2375 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2376};
2377
2378/* list of all parent clock list */
2379PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2380PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2381
2382static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
2383 /* MUX_SEL_G2D0 */
2384 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2385 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2386 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2387 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2388};
2389
2390static struct samsung_div_clock g2d_div_clks[] __initdata = {
2391 /* DIV_G2D */
2392 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2393 DIV_G2D, 0, 2),
2394};
2395
2396static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
2397 /* DIV_ENABLE_ACLK_G2D */
2398 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2399 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2400 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2401 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2402 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2403 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2404 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2405 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2406 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2407 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2408 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2409 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2410 7, 0, 0),
2411 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2412 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2413 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2414 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2415 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2416 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2417 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2418 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2419 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2420 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2421 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2422 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2423 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2424 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2425
2426 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2427 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2428 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2429
2430 /* DIV_ENABLE_PCLK_G2D */
2431 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2432 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2433 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2434 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2435 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2436 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2437 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2438 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2439 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2440 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2441 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2442 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2443 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2444 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2445 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2446 0, 0, 0),
2447
2448 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2449 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2450 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2451};
2452
2453static struct samsung_cmu_info g2d_cmu_info __initdata = {
2454 .mux_clks = g2d_mux_clks,
2455 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2456 .div_clks = g2d_div_clks,
2457 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2458 .gate_clks = g2d_gate_clks,
2459 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2460 .nr_clk_ids = G2D_NR_CLK,
2461 .clk_regs = g2d_clk_regs,
2462 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2463};
2464
2465static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2466{
2467 samsung_cmu_register_one(np, &g2d_cmu_info);
2468}
2469
2470CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2471 exynos5433_cmu_g2d_init);
2472
2473/*
2474 * Register offset definitions for CMU_DISP
2475 */
2476#define DISP_PLL_LOCK 0x0000
2477#define DISP_PLL_CON0 0x0100
2478#define DISP_PLL_CON1 0x0104
2479#define DISP_PLL_FREQ_DET 0x0108
2480#define MUX_SEL_DISP0 0x0200
2481#define MUX_SEL_DISP1 0x0204
2482#define MUX_SEL_DISP2 0x0208
2483#define MUX_SEL_DISP3 0x020c
2484#define MUX_SEL_DISP4 0x0210
2485#define MUX_ENABLE_DISP0 0x0300
2486#define MUX_ENABLE_DISP1 0x0304
2487#define MUX_ENABLE_DISP2 0x0308
2488#define MUX_ENABLE_DISP3 0x030c
2489#define MUX_ENABLE_DISP4 0x0310
2490#define MUX_STAT_DISP0 0x0400
2491#define MUX_STAT_DISP1 0x0404
2492#define MUX_STAT_DISP2 0x0408
2493#define MUX_STAT_DISP3 0x040c
2494#define MUX_STAT_DISP4 0x0410
2495#define MUX_IGNORE_DISP2 0x0508
2496#define DIV_DISP 0x0600
2497#define DIV_DISP_PLL_FREQ_DET 0x0604
2498#define DIV_STAT_DISP 0x0700
2499#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2500#define ENABLE_ACLK_DISP0 0x0800
2501#define ENABLE_ACLK_DISP1 0x0804
2502#define ENABLE_PCLK_DISP 0x0900
2503#define ENABLE_SCLK_DISP 0x0a00
2504#define ENABLE_IP_DISP0 0x0b00
2505#define ENABLE_IP_DISP1 0x0b04
2506#define CLKOUT_CMU_DISP 0x0c00
2507#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2508
2509static unsigned long disp_clk_regs[] __initdata = {
2510 DISP_PLL_LOCK,
2511 DISP_PLL_CON0,
2512 DISP_PLL_CON1,
2513 DISP_PLL_FREQ_DET,
2514 MUX_SEL_DISP0,
2515 MUX_SEL_DISP1,
2516 MUX_SEL_DISP2,
2517 MUX_SEL_DISP3,
2518 MUX_SEL_DISP4,
2519 MUX_ENABLE_DISP0,
2520 MUX_ENABLE_DISP1,
2521 MUX_ENABLE_DISP2,
2522 MUX_ENABLE_DISP3,
2523 MUX_ENABLE_DISP4,
2524 MUX_STAT_DISP0,
2525 MUX_STAT_DISP1,
2526 MUX_STAT_DISP2,
2527 MUX_STAT_DISP3,
2528 MUX_STAT_DISP4,
2529 MUX_IGNORE_DISP2,
2530 DIV_DISP,
2531 DIV_DISP_PLL_FREQ_DET,
2532 DIV_STAT_DISP,
2533 DIV_STAT_DISP_PLL_FREQ_DET,
2534 ENABLE_ACLK_DISP0,
2535 ENABLE_ACLK_DISP1,
2536 ENABLE_PCLK_DISP,
2537 ENABLE_SCLK_DISP,
2538 ENABLE_IP_DISP0,
2539 ENABLE_IP_DISP1,
2540 CLKOUT_CMU_DISP,
2541 CLKOUT_CMU_DISP_DIV_STAT,
2542};
2543
2544/* list of all parent clock list */
2545PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2546PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2547PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2548PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2549PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2550 "sclk_decon_tv_eclk_disp", };
2551PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2552 "sclk_decon_vclk_disp", };
2553PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2554 "sclk_decon_eclk_disp", };
2555PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2556 "sclk_decon_tv_vclk_disp", };
2557PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2558
2559PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2560 "phyclk_mipidphy1_bitclkdiv8_phy", };
2561PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2562 "phyclk_mipidphy1_rxclkesc0_phy", };
2563PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2564 "phyclk_mipidphy0_bitclkdiv8_phy", };
2565PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2566 "phyclk_mipidphy0_rxclkesc0_phy", };
2567PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2568 "phyclk_hdmiphy_tmds_clko_phy", };
2569PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2570 "phyclk_hdmiphy_pixel_clko_phy", };
2571
2572PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2573 "mout_sclk_dsim0_user", };
2574PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2575 "mout_sclk_decon_tv_eclk_user", };
2576PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2577 "mout_sclk_decon_vclk_user", };
2578PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2579 "mout_sclk_decon_eclk_user", };
2580
2581PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2582 "mout_sclk_dsim1_user", };
2583PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2584 "mout_phyclk_hdmiphy_pixel_clko_user",
2585 "mout_sclk_decon_tv_vclk_b_disp", };
2586PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2587 "mout_sclk_decon_tv_vclk_user", };
2588
2589static struct samsung_pll_clock disp_pll_clks[] __initdata = {
2590 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2591 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2592};
2593
2594static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2595 /*
2596 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2597 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2598 * and sclk_decon_{vclk|tv_vclk}.
2599 */
2600 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2601 1, 2, 0),
2602 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2603 1, 2, 0),
2604};
2605
2606static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2607 /* PHY clocks from MIPI_DPHY1 */
2608 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2609 188000000),
2610 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2611 100000000),
2612 /* PHY clocks from MIPI_DPHY0 */
2613 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2614 188000000),
2615 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2616 100000000),
2617 /* PHY clocks from HDMI_PHY */
2618 FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
2619 FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
2620};
2621
2622static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2623 /* MUX_SEL_DISP0 */
2624 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2625 0, 1),
2626
2627 /* MUX_SEL_DISP1 */
2628 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2629 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2630 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2631 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2632 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2633 MUX_SEL_DISP1, 20, 1),
2634 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2635 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2636 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2637 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2638 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2639 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2640 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2641 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2642 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2643 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2644
2645 /* MUX_SEL_DISP2 */
2646 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2647 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2648 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2649 20, 1),
2650 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2651 "mout_phyclk_mipidphy1_rxclkesc0_user",
2652 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2653 16, 1),
2654 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2655 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2656 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2657 12, 1),
2658 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2659 "mout_phyclk_mipidphy0_rxclkesc0_user",
2660 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2661 8, 1),
2662 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2663 "mout_phyclk_hdmiphy_tmds_clko_user",
2664 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2665 4, 1),
2666 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2667 "mout_phyclk_hdmiphy_pixel_clko_user",
2668 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2669 0, 1),
2670
2671 /* MUX_SEL_DISP3 */
2672 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2673 MUX_SEL_DISP3, 12, 1),
2674 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2675 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2676 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2677 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2678 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2679 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2680
2681 /* MUX_SEL_DISP4 */
2682 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2683 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2684 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2685 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2686 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2687 "mout_sclk_decon_tv_vclk_c_disp",
2688 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2689 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2690 "mout_sclk_decon_tv_vclk_b_disp",
2691 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2692 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2693 "mout_sclk_decon_tv_vclk_a_disp",
2694 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2695};
2696
2697static struct samsung_div_clock disp_div_clks[] __initdata = {
2698 /* DIV_DISP */
2699 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2700 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2701 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2702 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2703 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2704 DIV_DISP, 16, 3),
2705 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2706 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2707 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2708 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2709 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2710 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2711 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2712 DIV_DISP, 0, 2),
2713};
2714
2715static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2716 /* ENABLE_ACLK_DISP0 */
2717 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2718 ENABLE_ACLK_DISP0, 2, 0, 0),
2719 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2720 ENABLE_ACLK_DISP0, 0, 0, 0),
2721
2722 /* ENABLE_ACLK_DISP1 */
2723 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2724 ENABLE_ACLK_DISP1, 25, 0, 0),
2725 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2726 ENABLE_ACLK_DISP1, 24, 0, 0),
2727 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2728 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2729 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2730 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2731 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2732 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2733 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2734 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2735 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2736 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2737 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2738 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2739 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2740 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2741 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2742 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2743 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2744 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2745 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2746 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2747 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2748 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2749 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2750 "div_pclk_disp", ENABLE_ACLK_DISP1,
2751 12, CLK_IGNORE_UNUSED, 0),
2752 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2753 "div_pclk_disp", ENABLE_ACLK_DISP1,
2754 11, CLK_IGNORE_UNUSED, 0),
2755 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2756 "div_pclk_disp", ENABLE_ACLK_DISP1,
2757 10, CLK_IGNORE_UNUSED, 0),
2758 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2759 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2760 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2761 ENABLE_ACLK_DISP1, 7, 0, 0),
2762 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2763 ENABLE_ACLK_DISP1, 6, 0, 0),
2764 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2765 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2766 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2767 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2768 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2769 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2770 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2771 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2772 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2773 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2774 CLK_IGNORE_UNUSED, 0),
2775 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2776 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2777 0, CLK_IGNORE_UNUSED, 0),
2778
2779 /* ENABLE_PCLK_DISP */
2780 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2781 ENABLE_PCLK_DISP, 23, 0, 0),
2782 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2783 ENABLE_PCLK_DISP, 22, 0, 0),
2784 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2785 ENABLE_PCLK_DISP, 21, 0, 0),
2786 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2787 ENABLE_PCLK_DISP, 20, 0, 0),
2788 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2789 ENABLE_PCLK_DISP, 19, 0, 0),
2790 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2791 ENABLE_PCLK_DISP, 18, 0, 0),
2792 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2793 ENABLE_PCLK_DISP, 17, 0, 0),
2794 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2795 ENABLE_PCLK_DISP, 16, 0, 0),
2796 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2797 ENABLE_PCLK_DISP, 15, 0, 0),
2798 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2799 ENABLE_PCLK_DISP, 14, 0, 0),
2800 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2801 ENABLE_PCLK_DISP, 13, 0, 0),
2802 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2803 ENABLE_PCLK_DISP, 12, 0, 0),
2804 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2805 ENABLE_PCLK_DISP, 11, 0, 0),
2806 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2807 ENABLE_PCLK_DISP, 10, 0, 0),
2808 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2809 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2810 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2811 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2812 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2813 ENABLE_PCLK_DISP, 7, 0, 0),
2814 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2815 ENABLE_PCLK_DISP, 6, 0, 0),
2816 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2817 ENABLE_PCLK_DISP, 5, 0, 0),
2818 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2819 ENABLE_PCLK_DISP, 3, 0, 0),
2820 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2821 ENABLE_PCLK_DISP, 2, 0, 0),
2822 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2823 ENABLE_PCLK_DISP, 1, 0, 0),
2824
2825 /* ENABLE_SCLK_DISP */
2826 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2827 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2828 ENABLE_SCLK_DISP, 26, 0, 0),
2829 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2830 "mout_phyclk_mipidphy1_rxclkesc0_user",
2831 ENABLE_SCLK_DISP, 25, 0, 0),
2832 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2833 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2834 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2835 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2836 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2837 ENABLE_SCLK_DISP, 22, 0, 0),
2838 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2839 "div_sclk_decon_tv_vclk_disp",
2840 ENABLE_SCLK_DISP, 21, 0, 0),
2841 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2842 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2843 ENABLE_SCLK_DISP, 15, 0, 0),
2844 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2845 "mout_phyclk_mipidphy0_rxclkesc0_user",
2846 ENABLE_SCLK_DISP, 14, 0, 0),
2847 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2848 "mout_phyclk_hdmiphy_tmds_clko_user",
2849 ENABLE_SCLK_DISP, 13, 0, 0),
2850 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2851 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2852 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2853 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2854 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2855 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2856 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2857 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2858 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2859 ENABLE_SCLK_DISP, 7, 0, 0),
2860 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2861 ENABLE_SCLK_DISP, 6, 0, 0),
2862 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2863 ENABLE_SCLK_DISP, 5, 0, 0),
2864 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2865 "div_sclk_decon_tv_eclk_disp",
2866 ENABLE_SCLK_DISP, 4, 0, 0),
2867 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2868 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2869 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2870 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2871};
2872
2873static struct samsung_cmu_info disp_cmu_info __initdata = {
2874 .pll_clks = disp_pll_clks,
2875 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2876 .mux_clks = disp_mux_clks,
2877 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2878 .div_clks = disp_div_clks,
2879 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2880 .gate_clks = disp_gate_clks,
2881 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2882 .fixed_clks = disp_fixed_clks,
2883 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2884 .fixed_factor_clks = disp_fixed_factor_clks,
2885 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2886 .nr_clk_ids = DISP_NR_CLK,
2887 .clk_regs = disp_clk_regs,
2888 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2889};
2890
2891static void __init exynos5433_cmu_disp_init(struct device_node *np)
2892{
2893 samsung_cmu_register_one(np, &disp_cmu_info);
2894}
2895
2896CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2897 exynos5433_cmu_disp_init);
2898
2899/*
2900 * Register offset definitions for CMU_AUD
2901 */
2902#define MUX_SEL_AUD0 0x0200
2903#define MUX_SEL_AUD1 0x0204
2904#define MUX_ENABLE_AUD0 0x0300
2905#define MUX_ENABLE_AUD1 0x0304
2906#define MUX_STAT_AUD0 0x0400
2907#define DIV_AUD0 0x0600
2908#define DIV_AUD1 0x0604
2909#define DIV_STAT_AUD0 0x0700
2910#define DIV_STAT_AUD1 0x0704
2911#define ENABLE_ACLK_AUD 0x0800
2912#define ENABLE_PCLK_AUD 0x0900
2913#define ENABLE_SCLK_AUD0 0x0a00
2914#define ENABLE_SCLK_AUD1 0x0a04
2915#define ENABLE_IP_AUD0 0x0b00
2916#define ENABLE_IP_AUD1 0x0b04
2917
2918static unsigned long aud_clk_regs[] __initdata = {
2919 MUX_SEL_AUD0,
2920 MUX_SEL_AUD1,
2921 MUX_ENABLE_AUD0,
2922 MUX_ENABLE_AUD1,
2923 MUX_STAT_AUD0,
2924 DIV_AUD0,
2925 DIV_AUD1,
2926 DIV_STAT_AUD0,
2927 DIV_STAT_AUD1,
2928 ENABLE_ACLK_AUD,
2929 ENABLE_PCLK_AUD,
2930 ENABLE_SCLK_AUD0,
2931 ENABLE_SCLK_AUD1,
2932 ENABLE_IP_AUD0,
2933 ENABLE_IP_AUD1,
2934};
2935
2936/* list of all parent clock list */
2937PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2938PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2939
2940static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
2941 FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
2942 FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
2943 FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
2944};
2945
2946static struct samsung_mux_clock aud_mux_clks[] __initdata = {
2947 /* MUX_SEL_AUD0 */
2948 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2949 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2950
2951 /* MUX_SEL_AUD1 */
2952 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2953 MUX_SEL_AUD1, 8, 1),
2954 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2955 MUX_SEL_AUD1, 0, 1),
2956};
2957
2958static struct samsung_div_clock aud_div_clks[] __initdata = {
2959 /* DIV_AUD0 */
2960 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2961 12, 4),
2962 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2963 8, 4),
2964 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2965 4, 4),
2966 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2967 0, 4),
2968
2969 /* DIV_AUD1 */
2970 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2971 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2972 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2973 DIV_AUD1, 12, 4),
2974 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2975 DIV_AUD1, 4, 8),
2976 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2977 DIV_AUD1, 0, 4),
2978};
2979
2980static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2981 /* ENABLE_ACLK_AUD */
2982 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2983 ENABLE_ACLK_AUD, 12, 0, 0),
2984 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2985 ENABLE_ACLK_AUD, 7, 0, 0),
2986 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2987 ENABLE_ACLK_AUD, 0, 4, 0),
2988 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2989 ENABLE_ACLK_AUD, 0, 3, 0),
2990 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2991 ENABLE_ACLK_AUD, 0, 2, 0),
2992 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2993 0, 1, 0),
2994 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2995 0, CLK_IGNORE_UNUSED, 0),
2996
2997 /* ENABLE_PCLK_AUD */
2998 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2999 13, 0, 0),
3000 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3001 12, 0, 0),
3002 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3003 11, 0, 0),
3004 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
3005 ENABLE_PCLK_AUD, 10, 0, 0),
3006 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
3007 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3008 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
3009 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3010 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
3011 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3012 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
3013 ENABLE_PCLK_AUD, 6, 0, 0),
3014 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
3015 ENABLE_PCLK_AUD, 5, 0, 0),
3016 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
3017 ENABLE_PCLK_AUD, 4, 0, 0),
3018 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
3019 ENABLE_PCLK_AUD, 3, 0, 0),
3020 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3021 2, 0, 0),
3022 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
3023 ENABLE_PCLK_AUD, 0, 0, 0),
3024
3025 /* ENABLE_SCLK_AUD0 */
3026 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
3027 2, 0, 0),
3028 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3029 ENABLE_SCLK_AUD0, 1, 0, 0),
3030 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3031 0, 0, 0),
3032
3033 /* ENABLE_SCLK_AUD1 */
3034 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3035 ENABLE_SCLK_AUD1, 6, 0, 0),
3036 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3037 ENABLE_SCLK_AUD1, 5, 0, 0),
3038 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3039 ENABLE_SCLK_AUD1, 4, 0, 0),
3040 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3041 ENABLE_SCLK_AUD1, 3, 0, 0),
3042 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3043 ENABLE_SCLK_AUD1, 2, 0, 0),
3044 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3045 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3046 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3047 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3048};
3049
3050static struct samsung_cmu_info aud_cmu_info __initdata = {
3051 .mux_clks = aud_mux_clks,
3052 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
3053 .div_clks = aud_div_clks,
3054 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
3055 .gate_clks = aud_gate_clks,
3056 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
3057 .fixed_clks = aud_fixed_clks,
3058 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
3059 .nr_clk_ids = AUD_NR_CLK,
3060 .clk_regs = aud_clk_regs,
3061 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
3062};
3063
3064static void __init exynos5433_cmu_aud_init(struct device_node *np)
3065{
3066 samsung_cmu_register_one(np, &aud_cmu_info);
3067}
3068CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
3069 exynos5433_cmu_aud_init);
3070
3071
3072/*
3073 * Register offset definitions for CMU_BUS{0|1|2}
3074 */
3075#define DIV_BUS 0x0600
3076#define DIV_STAT_BUS 0x0700
3077#define ENABLE_ACLK_BUS 0x0800
3078#define ENABLE_PCLK_BUS 0x0900
3079#define ENABLE_IP_BUS0 0x0b00
3080#define ENABLE_IP_BUS1 0x0b04
3081
3082#define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3083#define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3084#define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3085
3086/* list of all parent clock list */
3087PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3088
3089#define CMU_BUS_COMMON_CLK_REGS \
3090 DIV_BUS, \
3091 DIV_STAT_BUS, \
3092 ENABLE_ACLK_BUS, \
3093 ENABLE_PCLK_BUS, \
3094 ENABLE_IP_BUS0, \
3095 ENABLE_IP_BUS1
3096
3097static unsigned long bus01_clk_regs[] __initdata = {
3098 CMU_BUS_COMMON_CLK_REGS,
3099};
3100
3101static unsigned long bus2_clk_regs[] __initdata = {
3102 MUX_SEL_BUS2,
3103 MUX_ENABLE_BUS2,
3104 MUX_STAT_BUS2,
3105 CMU_BUS_COMMON_CLK_REGS,
3106};
3107
3108static struct samsung_div_clock bus0_div_clks[] __initdata = {
3109 /* DIV_BUS0 */
3110 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3111 DIV_BUS, 0, 3),
3112};
3113
3114/* CMU_BUS0 clocks */
3115static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
3116 /* ENABLE_ACLK_BUS0 */
3117 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3118 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3119 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3120 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3121 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3122 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3123
3124 /* ENABLE_PCLK_BUS0 */
3125 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3126 ENABLE_PCLK_BUS, 2, 0, 0),
3127 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3128 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3129 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3130 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3131};
3132
3133/* CMU_BUS1 clocks */
3134static struct samsung_div_clock bus1_div_clks[] __initdata = {
3135 /* DIV_BUS1 */
3136 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3137 DIV_BUS, 0, 3),
3138};
3139
3140static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
3141 /* ENABLE_ACLK_BUS1 */
3142 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3143 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3144 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3145 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3146 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3147 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3148
3149 /* ENABLE_PCLK_BUS1 */
3150 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3151 ENABLE_PCLK_BUS, 2, 0, 0),
3152 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3153 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3154 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3155 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3156};
3157
3158/* CMU_BUS2 clocks */
3159static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
3160 /* MUX_SEL_BUS2 */
3161 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3162 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3163};
3164
3165static struct samsung_div_clock bus2_div_clks[] __initdata = {
3166 /* DIV_BUS2 */
3167 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3168 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3169};
3170
3171static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
3172 /* ENABLE_ACLK_BUS2 */
3173 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3174 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3175 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3176 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3177 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3178 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3179 1, CLK_IGNORE_UNUSED, 0),
3180 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3181 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3182 0, CLK_IGNORE_UNUSED, 0),
3183
3184 /* ENABLE_PCLK_BUS2 */
3185 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3186 ENABLE_PCLK_BUS, 2, 0, 0),
3187 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3188 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3189 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3190 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3191};
3192
3193#define CMU_BUS_INFO_CLKS(id) \
3194 .div_clks = bus##id##_div_clks, \
3195 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3196 .gate_clks = bus##id##_gate_clks, \
3197 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3198 .nr_clk_ids = BUSx_NR_CLK
3199
3200static struct samsung_cmu_info bus0_cmu_info __initdata = {
3201 CMU_BUS_INFO_CLKS(0),
3202 .clk_regs = bus01_clk_regs,
3203 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3204};
3205
3206static struct samsung_cmu_info bus1_cmu_info __initdata = {
3207 CMU_BUS_INFO_CLKS(1),
3208 .clk_regs = bus01_clk_regs,
3209 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3210};
3211
3212static struct samsung_cmu_info bus2_cmu_info __initdata = {
3213 CMU_BUS_INFO_CLKS(2),
3214 .mux_clks = bus2_mux_clks,
3215 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3216 .clk_regs = bus2_clk_regs,
3217 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3218};
3219
3220#define exynos5433_cmu_bus_init(id) \
3221static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3222{ \
3223 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3224} \
3225CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3226 "samsung,exynos5433-cmu-bus"#id, \
3227 exynos5433_cmu_bus##id##_init)
3228
3229exynos5433_cmu_bus_init(0);
3230exynos5433_cmu_bus_init(1);
3231exynos5433_cmu_bus_init(2);
3232
3233/*
3234 * Register offset definitions for CMU_G3D
3235 */
3236#define G3D_PLL_LOCK 0x0000
3237#define G3D_PLL_CON0 0x0100
3238#define G3D_PLL_CON1 0x0104
3239#define G3D_PLL_FREQ_DET 0x010c
3240#define MUX_SEL_G3D 0x0200
3241#define MUX_ENABLE_G3D 0x0300
3242#define MUX_STAT_G3D 0x0400
3243#define DIV_G3D 0x0600
3244#define DIV_G3D_PLL_FREQ_DET 0x0604
3245#define DIV_STAT_G3D 0x0700
3246#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3247#define ENABLE_ACLK_G3D 0x0800
3248#define ENABLE_PCLK_G3D 0x0900
3249#define ENABLE_SCLK_G3D 0x0a00
3250#define ENABLE_IP_G3D0 0x0b00
3251#define ENABLE_IP_G3D1 0x0b04
3252#define CLKOUT_CMU_G3D 0x0c00
3253#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3254#define CLK_STOPCTRL 0x1000
3255
3256static unsigned long g3d_clk_regs[] __initdata = {
3257 G3D_PLL_LOCK,
3258 G3D_PLL_CON0,
3259 G3D_PLL_CON1,
3260 G3D_PLL_FREQ_DET,
3261 MUX_SEL_G3D,
3262 MUX_ENABLE_G3D,
3263 MUX_STAT_G3D,
3264 DIV_G3D,
3265 DIV_G3D_PLL_FREQ_DET,
3266 DIV_STAT_G3D,
3267 DIV_STAT_G3D_PLL_FREQ_DET,
3268 ENABLE_ACLK_G3D,
3269 ENABLE_PCLK_G3D,
3270 ENABLE_SCLK_G3D,
3271 ENABLE_IP_G3D0,
3272 ENABLE_IP_G3D1,
3273 CLKOUT_CMU_G3D,
3274 CLKOUT_CMU_G3D_DIV_STAT,
3275 CLK_STOPCTRL,
3276};
3277
3278/* list of all parent clock list */
3279PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3280PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3281
3282static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
3283 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3284 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3285};
3286
3287static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
3288 /* MUX_SEL_G3D */
3289 MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3290 MUX_SEL_G3D, 8, 1),
3291 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3292 MUX_SEL_G3D, 0, 1),
3293};
3294
3295static struct samsung_div_clock g3d_div_clks[] __initdata = {
3296 /* DIV_G3D */
3297 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3298 8, 2),
3299 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3300 4, 3),
3301 DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3302 0, 3),
3303};
3304
3305static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
3306 /* ENABLE_ACLK_G3D */
3307 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3308 ENABLE_ACLK_G3D, 7, 0, 0),
3309 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3310 ENABLE_ACLK_G3D, 6, 0, 0),
3311 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3312 ENABLE_ACLK_G3D, 5, 0, 0),
3313 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3314 ENABLE_ACLK_G3D, 4, 0, 0),
3315 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3316 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3317 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3318 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3319 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3320 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3321 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3322 ENABLE_ACLK_G3D, 0, 0, 0),
3323
3324 /* ENABLE_PCLK_G3D */
3325 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3326 ENABLE_PCLK_G3D, 3, 0, 0),
3327 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3328 ENABLE_PCLK_G3D, 2, 0, 0),
3329 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3330 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3331 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3332 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3333
3334 /* ENABLE_SCLK_G3D */
3335 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3336 ENABLE_SCLK_G3D, 0, 0, 0),
3337};
3338
3339static struct samsung_cmu_info g3d_cmu_info __initdata = {
3340 .pll_clks = g3d_pll_clks,
3341 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3342 .mux_clks = g3d_mux_clks,
3343 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3344 .div_clks = g3d_div_clks,
3345 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3346 .gate_clks = g3d_gate_clks,
3347 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3348 .nr_clk_ids = G3D_NR_CLK,
3349 .clk_regs = g3d_clk_regs,
3350 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3351};
3352
3353static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3354{
3355 samsung_cmu_register_one(np, &g3d_cmu_info);
3356}
3357CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3358 exynos5433_cmu_g3d_init);
3359
3360/*
3361 * Register offset definitions for CMU_GSCL
3362 */
3363#define MUX_SEL_GSCL 0x0200
3364#define MUX_ENABLE_GSCL 0x0300
3365#define MUX_STAT_GSCL 0x0400
3366#define ENABLE_ACLK_GSCL 0x0800
3367#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3368#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3369#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3370#define ENABLE_PCLK_GSCL 0x0900
3371#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3372#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3373#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3374#define ENABLE_IP_GSCL0 0x0b00
3375#define ENABLE_IP_GSCL1 0x0b04
3376#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3377#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3378#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3379
3380static unsigned long gscl_clk_regs[] __initdata = {
3381 MUX_SEL_GSCL,
3382 MUX_ENABLE_GSCL,
3383 MUX_STAT_GSCL,
3384 ENABLE_ACLK_GSCL,
3385 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3386 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3387 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3388 ENABLE_PCLK_GSCL,
3389 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3390 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3391 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3392 ENABLE_IP_GSCL0,
3393 ENABLE_IP_GSCL1,
3394 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3395 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3396 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3397};
3398
3399/* list of all parent clock list */
3400PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3401PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3402
3403static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
3404 /* MUX_SEL_GSCL */
3405 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3406 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3407 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3408 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3409};
3410
3411static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3412 /* ENABLE_ACLK_GSCL */
3413 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3414 ENABLE_ACLK_GSCL, 11, 0, 0),
3415 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3416 ENABLE_ACLK_GSCL, 10, 0, 0),
3417 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3418 ENABLE_ACLK_GSCL, 9, 0, 0),
3419 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3420 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3421 8, CLK_IGNORE_UNUSED, 0),
3422 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3423 ENABLE_ACLK_GSCL, 7, 0, 0),
3424 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3425 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3426 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3427 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
3428 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3429 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
3430 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3431 ENABLE_ACLK_GSCL, 3, 0, 0),
3432 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3433 ENABLE_ACLK_GSCL, 2, 0, 0),
3434 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3435 ENABLE_ACLK_GSCL, 1, 0, 0),
3436 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3437 ENABLE_ACLK_GSCL, 0, 0, 0),
3438
3439 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3440 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3441 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3442
3443 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3444 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3445 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3446
3447 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3448 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3449 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3450
3451 /* ENABLE_PCLK_GSCL */
3452 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3453 ENABLE_PCLK_GSCL, 7, 0, 0),
3454 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3455 ENABLE_PCLK_GSCL, 6, 0, 0),
3456 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3457 ENABLE_PCLK_GSCL, 5, 0, 0),
3458 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3459 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3460 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3461 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3462 3, CLK_IGNORE_UNUSED, 0),
3463 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3464 ENABLE_PCLK_GSCL, 2, 0, 0),
3465 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3466 ENABLE_PCLK_GSCL, 1, 0, 0),
3467 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3468 ENABLE_PCLK_GSCL, 0, 0, 0),
3469
3470 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3471 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3472 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3473
3474 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3475 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3476 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3477
3478 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3479 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3480 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3481};
3482
3483static struct samsung_cmu_info gscl_cmu_info __initdata = {
3484 .mux_clks = gscl_mux_clks,
3485 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3486 .gate_clks = gscl_gate_clks,
3487 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3488 .nr_clk_ids = GSCL_NR_CLK,
3489 .clk_regs = gscl_clk_regs,
3490 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3491};
3492
3493static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3494{
3495 samsung_cmu_register_one(np, &gscl_cmu_info);
3496}
3497CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3498 exynos5433_cmu_gscl_init);
3499
3500/*
3501 * Register offset definitions for CMU_APOLLO
3502 */
3503#define APOLLO_PLL_LOCK 0x0000
3504#define APOLLO_PLL_CON0 0x0100
3505#define APOLLO_PLL_CON1 0x0104
3506#define APOLLO_PLL_FREQ_DET 0x010c
3507#define MUX_SEL_APOLLO0 0x0200
3508#define MUX_SEL_APOLLO1 0x0204
3509#define MUX_SEL_APOLLO2 0x0208
3510#define MUX_ENABLE_APOLLO0 0x0300
3511#define MUX_ENABLE_APOLLO1 0x0304
3512#define MUX_ENABLE_APOLLO2 0x0308
3513#define MUX_STAT_APOLLO0 0x0400
3514#define MUX_STAT_APOLLO1 0x0404
3515#define MUX_STAT_APOLLO2 0x0408
3516#define DIV_APOLLO0 0x0600
3517#define DIV_APOLLO1 0x0604
3518#define DIV_APOLLO_PLL_FREQ_DET 0x0608
3519#define DIV_STAT_APOLLO0 0x0700
3520#define DIV_STAT_APOLLO1 0x0704
3521#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3522#define ENABLE_ACLK_APOLLO 0x0800
3523#define ENABLE_PCLK_APOLLO 0x0900
3524#define ENABLE_SCLK_APOLLO 0x0a00
3525#define ENABLE_IP_APOLLO0 0x0b00
3526#define ENABLE_IP_APOLLO1 0x0b04
3527#define CLKOUT_CMU_APOLLO 0x0c00
3528#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3529#define ARMCLK_STOPCTRL 0x1000
3530#define APOLLO_PWR_CTRL 0x1020
3531#define APOLLO_PWR_CTRL2 0x1024
3532#define APOLLO_INTR_SPREAD_ENABLE 0x1080
3533#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3534#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3535
3536static unsigned long apollo_clk_regs[] __initdata = {
3537 APOLLO_PLL_LOCK,
3538 APOLLO_PLL_CON0,
3539 APOLLO_PLL_CON1,
3540 APOLLO_PLL_FREQ_DET,
3541 MUX_SEL_APOLLO0,
3542 MUX_SEL_APOLLO1,
3543 MUX_SEL_APOLLO2,
3544 MUX_ENABLE_APOLLO0,
3545 MUX_ENABLE_APOLLO1,
3546 MUX_ENABLE_APOLLO2,
3547 MUX_STAT_APOLLO0,
3548 MUX_STAT_APOLLO1,
3549 MUX_STAT_APOLLO2,
3550 DIV_APOLLO0,
3551 DIV_APOLLO1,
3552 DIV_APOLLO_PLL_FREQ_DET,
3553 DIV_STAT_APOLLO0,
3554 DIV_STAT_APOLLO1,
3555 DIV_STAT_APOLLO_PLL_FREQ_DET,
3556 ENABLE_ACLK_APOLLO,
3557 ENABLE_PCLK_APOLLO,
3558 ENABLE_SCLK_APOLLO,
3559 ENABLE_IP_APOLLO0,
3560 ENABLE_IP_APOLLO1,
3561 CLKOUT_CMU_APOLLO,
3562 CLKOUT_CMU_APOLLO_DIV_STAT,
3563 ARMCLK_STOPCTRL,
3564 APOLLO_PWR_CTRL,
3565 APOLLO_PWR_CTRL2,
3566 APOLLO_INTR_SPREAD_ENABLE,
3567 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3568 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3569};
3570
3571/* list of all parent clock list */
3572PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3573PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3574PNAME(mout_apollo_p) = { "mout_apollo_pll",
3575 "mout_bus_pll_apollo_user", };
3576
3577static struct samsung_pll_clock apollo_pll_clks[] __initdata = {
3578 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3579 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3580};
3581
3582static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
3583 /* MUX_SEL_APOLLO0 */
3584 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3585 MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY),
3586
3587 /* MUX_SEL_APOLLO1 */
3588 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3589 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3590
3591 /* MUX_SEL_APOLLO2 */
3592 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3593 0, 1, 0, CLK_MUX_READ_ONLY),
3594};
3595
3596static struct samsung_div_clock apollo_div_clks[] __initdata = {
3597 /* DIV_APOLLO0 */
3598 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3599 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3600 CLK_DIVIDER_READ_ONLY),
3601 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3602 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3603 CLK_DIVIDER_READ_ONLY),
3604 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3605 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3606 CLK_DIVIDER_READ_ONLY),
3607 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3608 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3609 CLK_DIVIDER_READ_ONLY),
3610 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3611 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3612 CLK_DIVIDER_READ_ONLY),
3613 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3614 DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE,
3615 CLK_DIVIDER_READ_ONLY),
3616 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3617 DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE,
3618 CLK_DIVIDER_READ_ONLY),
3619
3620 /* DIV_APOLLO1 */
3621 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3622 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3623 CLK_DIVIDER_READ_ONLY),
3624 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3625 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3626 CLK_DIVIDER_READ_ONLY),
3627};
3628
3629static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
3630 /* ENABLE_ACLK_APOLLO */
3631 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3632 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3633 6, CLK_IGNORE_UNUSED, 0),
3634 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3635 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3636 5, CLK_IGNORE_UNUSED, 0),
3637 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3638 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3639 4, CLK_IGNORE_UNUSED, 0),
3640 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3641 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3642 3, CLK_IGNORE_UNUSED, 0),
3643 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3644 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3645 2, CLK_IGNORE_UNUSED, 0),
3646 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3647 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3648 1, CLK_IGNORE_UNUSED, 0),
3649 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3650 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3651 0, CLK_IGNORE_UNUSED, 0),
3652
3653 /* ENABLE_PCLK_APOLLO */
3654 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3655 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3656 2, CLK_IGNORE_UNUSED, 0),
3657 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3658 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3659 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3660 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3661 0, CLK_IGNORE_UNUSED, 0),
3662
3663 /* ENABLE_SCLK_APOLLO */
3664 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3665 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3666 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3667 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3668 GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll",
3669 ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0),
3670};
3671
3672static struct samsung_cmu_info apollo_cmu_info __initdata = {
3673 .pll_clks = apollo_pll_clks,
3674 .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks),
3675 .mux_clks = apollo_mux_clks,
3676 .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks),
3677 .div_clks = apollo_div_clks,
3678 .nr_div_clks = ARRAY_SIZE(apollo_div_clks),
3679 .gate_clks = apollo_gate_clks,
3680 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
3681 .nr_clk_ids = APOLLO_NR_CLK,
3682 .clk_regs = apollo_clk_regs,
3683 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
3684};
3685
3686static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3687{
3688 samsung_cmu_register_one(np, &apollo_cmu_info);
3689}
3690CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3691 exynos5433_cmu_apollo_init);
3692
3693/*
3694 * Register offset definitions for CMU_ATLAS
3695 */
3696#define ATLAS_PLL_LOCK 0x0000
3697#define ATLAS_PLL_CON0 0x0100
3698#define ATLAS_PLL_CON1 0x0104
3699#define ATLAS_PLL_FREQ_DET 0x010c
3700#define MUX_SEL_ATLAS0 0x0200
3701#define MUX_SEL_ATLAS1 0x0204
3702#define MUX_SEL_ATLAS2 0x0208
3703#define MUX_ENABLE_ATLAS0 0x0300
3704#define MUX_ENABLE_ATLAS1 0x0304
3705#define MUX_ENABLE_ATLAS2 0x0308
3706#define MUX_STAT_ATLAS0 0x0400
3707#define MUX_STAT_ATLAS1 0x0404
3708#define MUX_STAT_ATLAS2 0x0408
3709#define DIV_ATLAS0 0x0600
3710#define DIV_ATLAS1 0x0604
3711#define DIV_ATLAS_PLL_FREQ_DET 0x0608
3712#define DIV_STAT_ATLAS0 0x0700
3713#define DIV_STAT_ATLAS1 0x0704
3714#define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3715#define ENABLE_ACLK_ATLAS 0x0800
3716#define ENABLE_PCLK_ATLAS 0x0900
3717#define ENABLE_SCLK_ATLAS 0x0a00
3718#define ENABLE_IP_ATLAS0 0x0b00
3719#define ENABLE_IP_ATLAS1 0x0b04
3720#define CLKOUT_CMU_ATLAS 0x0c00
3721#define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3722#define ARMCLK_STOPCTRL 0x1000
3723#define ATLAS_PWR_CTRL 0x1020
3724#define ATLAS_PWR_CTRL2 0x1024
3725#define ATLAS_INTR_SPREAD_ENABLE 0x1080
3726#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3727#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3728
3729static unsigned long atlas_clk_regs[] __initdata = {
3730 ATLAS_PLL_LOCK,
3731 ATLAS_PLL_CON0,
3732 ATLAS_PLL_CON1,
3733 ATLAS_PLL_FREQ_DET,
3734 MUX_SEL_ATLAS0,
3735 MUX_SEL_ATLAS1,
3736 MUX_SEL_ATLAS2,
3737 MUX_ENABLE_ATLAS0,
3738 MUX_ENABLE_ATLAS1,
3739 MUX_ENABLE_ATLAS2,
3740 MUX_STAT_ATLAS0,
3741 MUX_STAT_ATLAS1,
3742 MUX_STAT_ATLAS2,
3743 DIV_ATLAS0,
3744 DIV_ATLAS1,
3745 DIV_ATLAS_PLL_FREQ_DET,
3746 DIV_STAT_ATLAS0,
3747 DIV_STAT_ATLAS1,
3748 DIV_STAT_ATLAS_PLL_FREQ_DET,
3749 ENABLE_ACLK_ATLAS,
3750 ENABLE_PCLK_ATLAS,
3751 ENABLE_SCLK_ATLAS,
3752 ENABLE_IP_ATLAS0,
3753 ENABLE_IP_ATLAS1,
3754 CLKOUT_CMU_ATLAS,
3755 CLKOUT_CMU_ATLAS_DIV_STAT,
3756 ARMCLK_STOPCTRL,
3757 ATLAS_PWR_CTRL,
3758 ATLAS_PWR_CTRL2,
3759 ATLAS_INTR_SPREAD_ENABLE,
3760 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3761 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3762};
3763
3764/* list of all parent clock list */
3765PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3766PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3767PNAME(mout_atlas_p) = { "mout_atlas_pll",
3768 "mout_bus_pll_atlas_user", };
3769
3770static struct samsung_pll_clock atlas_pll_clks[] __initdata = {
3771 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3772 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3773};
3774
3775static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
3776 /* MUX_SEL_ATLAS0 */
3777 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3778 MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY),
3779
3780 /* MUX_SEL_ATLAS1 */
3781 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3782 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3783
3784 /* MUX_SEL_ATLAS2 */
3785 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3786 0, 1, 0, CLK_MUX_READ_ONLY),
3787};
3788
3789static struct samsung_div_clock atlas_div_clks[] __initdata = {
3790 /* DIV_ATLAS0 */
3791 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3792 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3793 CLK_DIVIDER_READ_ONLY),
3794 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3795 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3796 CLK_DIVIDER_READ_ONLY),
3797 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3798 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3799 CLK_DIVIDER_READ_ONLY),
3800 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3801 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3802 CLK_DIVIDER_READ_ONLY),
3803 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3804 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3805 CLK_DIVIDER_READ_ONLY),
3806 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3807 DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE,
3808 CLK_DIVIDER_READ_ONLY),
3809 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3810 DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE,
3811 CLK_DIVIDER_READ_ONLY),
3812
3813 /* DIV_ATLAS1 */
3814 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3815 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3816 CLK_DIVIDER_READ_ONLY),
3817 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3818 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3819 CLK_DIVIDER_READ_ONLY),
3820};
3821
3822static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
3823 /* ENABLE_ACLK_ATLAS */
3824 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3825 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3826 9, CLK_IGNORE_UNUSED, 0),
3827 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3828 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3829 8, CLK_IGNORE_UNUSED, 0),
3830 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3831 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3832 7, CLK_IGNORE_UNUSED, 0),
3833 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3834 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3835 6, CLK_IGNORE_UNUSED, 0),
3836 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3837 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3838 5, CLK_IGNORE_UNUSED, 0),
3839 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3840 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3841 4, CLK_IGNORE_UNUSED, 0),
3842 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3843 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3844 3, CLK_IGNORE_UNUSED, 0),
3845 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3846 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3847 2, CLK_IGNORE_UNUSED, 0),
3848 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3849 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3850 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3851 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3852
3853 /* ENABLE_PCLK_ATLAS */
3854 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3855 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3856 5, CLK_IGNORE_UNUSED, 0),
3857 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3858 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3859 4, CLK_IGNORE_UNUSED, 0),
3860 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3861 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3862 3, CLK_IGNORE_UNUSED, 0),
3863 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3864 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3865 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3866 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3867 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3868 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3869
3870 /* ENABLE_SCLK_ATLAS */
3871 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3872 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3873 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3874 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3875 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3876 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3877 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3878 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3879 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3880 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3881 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3882 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3883 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3884 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3885 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3886 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3887 GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3888 ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3889};
3890
3891static struct samsung_cmu_info atlas_cmu_info __initdata = {
3892 .pll_clks = atlas_pll_clks,
3893 .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks),
3894 .mux_clks = atlas_mux_clks,
3895 .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks),
3896 .div_clks = atlas_div_clks,
3897 .nr_div_clks = ARRAY_SIZE(atlas_div_clks),
3898 .gate_clks = atlas_gate_clks,
3899 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
3900 .nr_clk_ids = ATLAS_NR_CLK,
3901 .clk_regs = atlas_clk_regs,
3902 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
3903};
3904
3905static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3906{
3907 samsung_cmu_register_one(np, &atlas_cmu_info);
3908}
3909CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3910 exynos5433_cmu_atlas_init);
3911
3912/*
3913 * Register offset definitions for CMU_MSCL
3914 */
3915#define MUX_SEL_MSCL0 0x0200
3916#define MUX_SEL_MSCL1 0x0204
3917#define MUX_ENABLE_MSCL0 0x0300
3918#define MUX_ENABLE_MSCL1 0x0304
3919#define MUX_STAT_MSCL0 0x0400
3920#define MUX_STAT_MSCL1 0x0404
3921#define DIV_MSCL 0x0600
3922#define DIV_STAT_MSCL 0x0700
3923#define ENABLE_ACLK_MSCL 0x0800
3924#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3925#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3926#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3927#define ENABLE_PCLK_MSCL 0x0900
3928#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3929#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3930#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x000c
3931#define ENABLE_SCLK_MSCL 0x0a00
3932#define ENABLE_IP_MSCL0 0x0b00
3933#define ENABLE_IP_MSCL1 0x0b04
3934#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3935#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3936#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3937
3938static unsigned long mscl_clk_regs[] __initdata = {
3939 MUX_SEL_MSCL0,
3940 MUX_SEL_MSCL1,
3941 MUX_ENABLE_MSCL0,
3942 MUX_ENABLE_MSCL1,
3943 MUX_STAT_MSCL0,
3944 MUX_STAT_MSCL1,
3945 DIV_MSCL,
3946 DIV_STAT_MSCL,
3947 ENABLE_ACLK_MSCL,
3948 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3949 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3950 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3951 ENABLE_PCLK_MSCL,
3952 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3953 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3954 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3955 ENABLE_SCLK_MSCL,
3956 ENABLE_IP_MSCL0,
3957 ENABLE_IP_MSCL1,
3958 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3959 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3960 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3961};
3962
3963/* list of all parent clock list */
3964PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3965PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3966PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3967 "mout_aclk_mscl_400_user", };
3968
3969static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
3970 /* MUX_SEL_MSCL0 */
3971 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3972 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
3973 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
3974 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
3975
3976 /* MUX_SEL_MSCL1 */
3977 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
3978 MUX_SEL_MSCL1, 0, 1),
3979};
3980
3981static struct samsung_div_clock mscl_div_clks[] __initdata = {
3982 /* DIV_MSCL */
3983 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3984 DIV_MSCL, 0, 3),
3985};
3986
3987static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
3988 /* ENABLE_ACLK_MSCL */
3989 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3990 ENABLE_ACLK_MSCL, 9, 0, 0),
3991 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
3992 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
3993 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
3994 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
3995 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
3996 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
3997 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
3998 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
3999 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4000 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4001 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4002 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4003 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4004 ENABLE_ACLK_MSCL, 2, 0, 0),
4005 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4006 ENABLE_ACLK_MSCL, 1, 0, 0),
4007 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4008 ENABLE_ACLK_MSCL, 0, 0, 0),
4009
4010 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4011 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4012 "mout_aclk_mscl_400_user",
4013 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4014 0, CLK_IGNORE_UNUSED, 0),
4015
4016 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4017 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4018 "mout_aclk_mscl_400_user",
4019 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4020 0, CLK_IGNORE_UNUSED, 0),
4021
4022 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4023 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4024 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4025 0, CLK_IGNORE_UNUSED, 0),
4026
4027 /* ENABLE_PCLK_MSCL */
4028 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4029 ENABLE_PCLK_MSCL, 7, 0, 0),
4030 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4031 ENABLE_PCLK_MSCL, 6, 0, 0),
4032 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4033 ENABLE_PCLK_MSCL, 5, 0, 0),
4034 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4035 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4036 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4037 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4038 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4039 ENABLE_PCLK_MSCL, 2, 0, 0),
4040 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4041 ENABLE_PCLK_MSCL, 1, 0, 0),
4042 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4043 ENABLE_PCLK_MSCL, 0, 0, 0),
4044
4045 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4046 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4047 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4048 0, CLK_IGNORE_UNUSED, 0),
4049
4050 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4051 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4052 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4053 0, CLK_IGNORE_UNUSED, 0),
4054
4055 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4056 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4057 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4058 0, CLK_IGNORE_UNUSED, 0),
4059
4060 /* ENABLE_SCLK_MSCL */
4061 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4062 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4063};
4064
4065static struct samsung_cmu_info mscl_cmu_info __initdata = {
4066 .mux_clks = mscl_mux_clks,
4067 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
4068 .div_clks = mscl_div_clks,
4069 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
4070 .gate_clks = mscl_gate_clks,
4071 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
4072 .nr_clk_ids = MSCL_NR_CLK,
4073 .clk_regs = mscl_clk_regs,
4074 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
4075};
4076
4077static void __init exynos5433_cmu_mscl_init(struct device_node *np)
4078{
4079 samsung_cmu_register_one(np, &mscl_cmu_info);
4080}
4081CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
4082 exynos5433_cmu_mscl_init);
4083
4084/*
4085 * Register offset definitions for CMU_MFC
4086 */
4087#define MUX_SEL_MFC 0x0200
4088#define MUX_ENABLE_MFC 0x0300
4089#define MUX_STAT_MFC 0x0400
4090#define DIV_MFC 0x0600
4091#define DIV_STAT_MFC 0x0700
4092#define ENABLE_ACLK_MFC 0x0800
4093#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4094#define ENABLE_PCLK_MFC 0x0900
4095#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4096#define ENABLE_IP_MFC0 0x0b00
4097#define ENABLE_IP_MFC1 0x0b04
4098#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4099
4100static unsigned long mfc_clk_regs[] __initdata = {
4101 MUX_SEL_MFC,
4102 MUX_ENABLE_MFC,
4103 MUX_STAT_MFC,
4104 DIV_MFC,
4105 DIV_STAT_MFC,
4106 ENABLE_ACLK_MFC,
4107 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4108 ENABLE_PCLK_MFC,
4109 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4110 ENABLE_IP_MFC0,
4111 ENABLE_IP_MFC1,
4112 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4113};
4114
4115PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4116
4117static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
4118 /* MUX_SEL_MFC */
4119 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4120 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4121};
4122
4123static struct samsung_div_clock mfc_div_clks[] __initdata = {
4124 /* DIV_MFC */
4125 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4126 DIV_MFC, 0, 2),
4127};
4128
4129static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
4130 /* ENABLE_ACLK_MFC */
4131 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4132 ENABLE_ACLK_MFC, 6, 0, 0),
4133 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4134 ENABLE_ACLK_MFC, 5, 0, 0),
4135 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4136 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4137 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4138 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4139 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4140 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4141 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4142 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4143 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4144 ENABLE_ACLK_MFC, 0, 0, 0),
4145
4146 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4147 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4148 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4149 1, CLK_IGNORE_UNUSED, 0),
4150 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4151 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4152 0, CLK_IGNORE_UNUSED, 0),
4153
4154 /* ENABLE_PCLK_MFC */
4155 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4156 ENABLE_PCLK_MFC, 4, 0, 0),
4157 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4158 ENABLE_PCLK_MFC, 3, 0, 0),
4159 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4160 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4161 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4162 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4163 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4164 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4165
4166 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4167 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4168 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4169 1, CLK_IGNORE_UNUSED, 0),
4170 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4171 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4172 0, CLK_IGNORE_UNUSED, 0),
4173};
4174
4175static struct samsung_cmu_info mfc_cmu_info __initdata = {
4176 .mux_clks = mfc_mux_clks,
4177 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4178 .div_clks = mfc_div_clks,
4179 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4180 .gate_clks = mfc_gate_clks,
4181 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4182 .nr_clk_ids = MFC_NR_CLK,
4183 .clk_regs = mfc_clk_regs,
4184 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4185};
4186
4187static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4188{
4189 samsung_cmu_register_one(np, &mfc_cmu_info);
4190}
4191CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4192 exynos5433_cmu_mfc_init);
4193
4194/*
4195 * Register offset definitions for CMU_HEVC
4196 */
4197#define MUX_SEL_HEVC 0x0200
4198#define MUX_ENABLE_HEVC 0x0300
4199#define MUX_STAT_HEVC 0x0400
4200#define DIV_HEVC 0x0600
4201#define DIV_STAT_HEVC 0x0700
4202#define ENABLE_ACLK_HEVC 0x0800
4203#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4204#define ENABLE_PCLK_HEVC 0x0900
4205#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4206#define ENABLE_IP_HEVC0 0x0b00
4207#define ENABLE_IP_HEVC1 0x0b04
4208#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4209
4210static unsigned long hevc_clk_regs[] __initdata = {
4211 MUX_SEL_HEVC,
4212 MUX_ENABLE_HEVC,
4213 MUX_STAT_HEVC,
4214 DIV_HEVC,
4215 DIV_STAT_HEVC,
4216 ENABLE_ACLK_HEVC,
4217 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4218 ENABLE_PCLK_HEVC,
4219 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4220 ENABLE_IP_HEVC0,
4221 ENABLE_IP_HEVC1,
4222 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4223};
4224
4225PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4226
4227static struct samsung_mux_clock hevc_mux_clks[] __initdata = {
4228 /* MUX_SEL_HEVC */
4229 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4230 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4231};
4232
4233static struct samsung_div_clock hevc_div_clks[] __initdata = {
4234 /* DIV_HEVC */
4235 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4236 DIV_HEVC, 0, 2),
4237};
4238
4239static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
4240 /* ENABLE_ACLK_HEVC */
4241 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4242 ENABLE_ACLK_HEVC, 6, 0, 0),
4243 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4244 ENABLE_ACLK_HEVC, 5, 0, 0),
4245 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4246 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4247 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4248 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4249 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4250 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4251 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4252 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4253 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4254 ENABLE_ACLK_HEVC, 0, 0, 0),
4255
4256 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4257 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4258 "mout_aclk_hevc_400_user",
4259 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4260 1, CLK_IGNORE_UNUSED, 0),
4261 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4262 "mout_aclk_hevc_400_user",
4263 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4264 0, CLK_IGNORE_UNUSED, 0),
4265
4266 /* ENABLE_PCLK_HEVC */
4267 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4268 ENABLE_PCLK_HEVC, 4, 0, 0),
4269 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4270 ENABLE_PCLK_HEVC, 3, 0, 0),
4271 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4272 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4273 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4274 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4275 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4276 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4277
4278 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4279 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4280 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4281 1, CLK_IGNORE_UNUSED, 0),
4282 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4283 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4284 0, CLK_IGNORE_UNUSED, 0),
4285};
4286
4287static struct samsung_cmu_info hevc_cmu_info __initdata = {
4288 .mux_clks = hevc_mux_clks,
4289 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4290 .div_clks = hevc_div_clks,
4291 .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
4292 .gate_clks = hevc_gate_clks,
4293 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
4294 .nr_clk_ids = HEVC_NR_CLK,
4295 .clk_regs = hevc_clk_regs,
4296 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4297};
4298
4299static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4300{
4301 samsung_cmu_register_one(np, &hevc_cmu_info);
4302}
4303CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4304 exynos5433_cmu_hevc_init);
4305
4306/*
4307 * Register offset definitions for CMU_ISP
4308 */
4309#define MUX_SEL_ISP 0x0200
4310#define MUX_ENABLE_ISP 0x0300
4311#define MUX_STAT_ISP 0x0400
4312#define DIV_ISP 0x0600
4313#define DIV_STAT_ISP 0x0700
4314#define ENABLE_ACLK_ISP0 0x0800
4315#define ENABLE_ACLK_ISP1 0x0804
4316#define ENABLE_ACLK_ISP2 0x0808
4317#define ENABLE_PCLK_ISP 0x0900
4318#define ENABLE_SCLK_ISP 0x0a00
4319#define ENABLE_IP_ISP0 0x0b00
4320#define ENABLE_IP_ISP1 0x0b04
4321#define ENABLE_IP_ISP2 0x0b08
4322#define ENABLE_IP_ISP3 0x0b0c
4323
4324static unsigned long isp_clk_regs[] __initdata = {
4325 MUX_SEL_ISP,
4326 MUX_ENABLE_ISP,
4327 MUX_STAT_ISP,
4328 DIV_ISP,
4329 DIV_STAT_ISP,
4330 ENABLE_ACLK_ISP0,
4331 ENABLE_ACLK_ISP1,
4332 ENABLE_ACLK_ISP2,
4333 ENABLE_PCLK_ISP,
4334 ENABLE_SCLK_ISP,
4335 ENABLE_IP_ISP0,
4336 ENABLE_IP_ISP1,
4337 ENABLE_IP_ISP2,
4338 ENABLE_IP_ISP3,
4339};
4340
4341PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4342PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4343
4344static struct samsung_mux_clock isp_mux_clks[] __initdata = {
4345 /* MUX_SEL_ISP */
4346 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4347 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4348 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4349 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4350};
4351
4352static struct samsung_div_clock isp_div_clks[] __initdata = {
4353 /* DIV_ISP */
4354 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4355 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4356 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4357 DIV_ISP, 8, 3),
4358 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4359 "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4360 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4361 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4362};
4363
4364static struct samsung_gate_clock isp_gate_clks[] __initdata = {
4365 /* ENABLE_ACLK_ISP0 */
4366 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4367 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4368 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4369 ENABLE_ACLK_ISP0, 5, 0, 0),
4370 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4371 ENABLE_ACLK_ISP0, 4, 0, 0),
4372 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4373 ENABLE_ACLK_ISP0, 3, 0, 0),
4374 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4375 ENABLE_ACLK_ISP0, 2, 0, 0),
4376 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4377 ENABLE_ACLK_ISP0, 1, 0, 0),
4378 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4379 ENABLE_ACLK_ISP0, 0, 0, 0),
4380
4381 /* ENABLE_ACLK_ISP1 */
4382 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4383 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4384 17, CLK_IGNORE_UNUSED, 0),
4385 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4386 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4387 16, CLK_IGNORE_UNUSED, 0),
4388 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4389 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4390 15, CLK_IGNORE_UNUSED, 0),
4391 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4392 "div_pclk_isp", ENABLE_ACLK_ISP1,
4393 14, CLK_IGNORE_UNUSED, 0),
4394 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4395 "div_pclk_isp", ENABLE_ACLK_ISP1,
4396 13, CLK_IGNORE_UNUSED, 0),
4397 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4398 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4399 12, CLK_IGNORE_UNUSED, 0),
4400 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4401 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4402 11, CLK_IGNORE_UNUSED, 0),
4403 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4404 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4405 10, CLK_IGNORE_UNUSED, 0),
4406 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4407 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4408 9, CLK_IGNORE_UNUSED, 0),
4409 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4410 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4411 8, CLK_IGNORE_UNUSED, 0),
4412 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4413 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4414 7, CLK_IGNORE_UNUSED, 0),
4415 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4416 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4417 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4418 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4419 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4420 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4421 4, CLK_IGNORE_UNUSED, 0),
4422 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4423 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4424 3, CLK_IGNORE_UNUSED, 0),
4425 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4426 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4427 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4428 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4429 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4430 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4431
4432 /* ENABLE_ACLK_ISP2 */
4433 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4434 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4435 13, CLK_IGNORE_UNUSED, 0),
4436 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4437 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4438 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4439 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4440 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4441 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4442 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4443 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4444 9, CLK_IGNORE_UNUSED, 0),
4445 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4446 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4447 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4448 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4449 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4450 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4451 6, CLK_IGNORE_UNUSED, 0),
4452 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4453 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4454 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4455 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4456 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4457 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4458 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4459 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4460 2, CLK_IGNORE_UNUSED, 0),
4461 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4462 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4463 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4464 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4465
4466 /* ENABLE_PCLK_ISP */
4467 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4468 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4469 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4470 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4471 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4472 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4473 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4474 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4475 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4476 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4477 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4478 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4479 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4480 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4481 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4482 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4483 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4484 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4485 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4486 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4487 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4488 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4489 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4490 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4491 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4492 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4493 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4494 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4495 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4496 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4497 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4498 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4499 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4500 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4501 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4502 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4503 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4504 "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4505 7, CLK_IGNORE_UNUSED, 0),
4506 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4507 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4508 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4509 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4510 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4511 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4512 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4513 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4514 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4515 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4516 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4517 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4518 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4519 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4520
4521 /* ENABLE_SCLK_ISP */
4522 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4523 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4524 5, CLK_IGNORE_UNUSED, 0),
4525 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4526 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4527 4, CLK_IGNORE_UNUSED, 0),
4528 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4529 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4530 3, CLK_IGNORE_UNUSED, 0),
4531 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4532 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4533 2, CLK_IGNORE_UNUSED, 0),
4534 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4535 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4536 1, CLK_IGNORE_UNUSED, 0),
4537 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4538 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4539 0, CLK_IGNORE_UNUSED, 0),
4540};
4541
4542static struct samsung_cmu_info isp_cmu_info __initdata = {
4543 .mux_clks = isp_mux_clks,
4544 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4545 .div_clks = isp_div_clks,
4546 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
4547 .gate_clks = isp_gate_clks,
4548 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
4549 .nr_clk_ids = ISP_NR_CLK,
4550 .clk_regs = isp_clk_regs,
4551 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
4552};
4553
4554static void __init exynos5433_cmu_isp_init(struct device_node *np)
4555{
4556 samsung_cmu_register_one(np, &isp_cmu_info);
4557}
4558CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4559 exynos5433_cmu_isp_init);
4560
4561/*
4562 * Register offset definitions for CMU_CAM0
4563 */
4564#define MUX_SEL_CAM00 0x0200
4565#define MUX_SEL_CAM01 0x0204
4566#define MUX_SEL_CAM02 0x0208
4567#define MUX_SEL_CAM03 0x020c
4568#define MUX_SEL_CAM04 0x0210
4569#define MUX_ENABLE_CAM00 0x0300
4570#define MUX_ENABLE_CAM01 0x0304
4571#define MUX_ENABLE_CAM02 0x0308
4572#define MUX_ENABLE_CAM03 0x030c
4573#define MUX_ENABLE_CAM04 0x0310
4574#define MUX_STAT_CAM00 0x0400
4575#define MUX_STAT_CAM01 0x0404
4576#define MUX_STAT_CAM02 0x0408
4577#define MUX_STAT_CAM03 0x040c
4578#define MUX_STAT_CAM04 0x0410
4579#define MUX_IGNORE_CAM01 0x0504
4580#define DIV_CAM00 0x0600
4581#define DIV_CAM01 0x0604
4582#define DIV_CAM02 0x0608
4583#define DIV_CAM03 0x060c
4584#define DIV_STAT_CAM00 0x0700
4585#define DIV_STAT_CAM01 0x0704
4586#define DIV_STAT_CAM02 0x0708
4587#define DIV_STAT_CAM03 0x070c
4588#define ENABLE_ACLK_CAM00 0X0800
4589#define ENABLE_ACLK_CAM01 0X0804
4590#define ENABLE_ACLK_CAM02 0X0808
4591#define ENABLE_PCLK_CAM0 0X0900
4592#define ENABLE_SCLK_CAM0 0X0a00
4593#define ENABLE_IP_CAM00 0X0b00
4594#define ENABLE_IP_CAM01 0X0b04
4595#define ENABLE_IP_CAM02 0X0b08
4596#define ENABLE_IP_CAM03 0X0b0C
4597
4598static unsigned long cam0_clk_regs[] __initdata = {
4599 MUX_SEL_CAM00,
4600 MUX_SEL_CAM01,
4601 MUX_SEL_CAM02,
4602 MUX_SEL_CAM03,
4603 MUX_SEL_CAM04,
4604 MUX_ENABLE_CAM00,
4605 MUX_ENABLE_CAM01,
4606 MUX_ENABLE_CAM02,
4607 MUX_ENABLE_CAM03,
4608 MUX_ENABLE_CAM04,
4609 MUX_STAT_CAM00,
4610 MUX_STAT_CAM01,
4611 MUX_STAT_CAM02,
4612 MUX_STAT_CAM03,
4613 MUX_STAT_CAM04,
4614 MUX_IGNORE_CAM01,
4615 DIV_CAM00,
4616 DIV_CAM01,
4617 DIV_CAM02,
4618 DIV_CAM03,
4619 DIV_STAT_CAM00,
4620 DIV_STAT_CAM01,
4621 DIV_STAT_CAM02,
4622 DIV_STAT_CAM03,
4623 ENABLE_ACLK_CAM00,
4624 ENABLE_ACLK_CAM01,
4625 ENABLE_ACLK_CAM02,
4626 ENABLE_PCLK_CAM0,
4627 ENABLE_SCLK_CAM0,
4628 ENABLE_IP_CAM00,
4629 ENABLE_IP_CAM01,
4630 ENABLE_IP_CAM02,
4631 ENABLE_IP_CAM03,
4632};
4633PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
4634PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
4635PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
4636
4637PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4638 "phyclk_rxbyteclkhs0_s4_phy", };
4639PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4640 "phyclk_rxbyteclkhs0_s2a_phy", };
4641
4642PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
4643 "mout_aclk_cam0_333_user", };
4644PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
4645 "mout_aclk_cam0_400_user", };
4646PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
4647 "mout_aclk_cam0_333_user", };
4648PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
4649 "mout_aclk_cam0_400_user", };
4650PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
4651 "mout_aclk_cam0_333_user", };
4652PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
4653 "mout_aclk_cam0_400_user", };
4654PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
4655 "mout_aclk_cam0_333_user", };
4656
4657PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
4658 "mout_aclk_cam0_333_user" };
4659PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
4660 "mout_aclk_cam0_400_user", };
4661PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
4662 "mout_aclk_cam0_333_user", };
4663PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
4664 "mout_aclk-cam0_400_user", };
4665PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
4666 "mout_aclk_cam0_333_user", };
4667PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
4668 "mout_aclk_cam0_400_user", };
4669PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
4670 "mout_aclk_cam0_333_user", };
4671PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
4672 "mout_aclk_cam0_400_user", };
4673
4674PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
4675 "div_pclk_lite_d", };
4676PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
4677 "div_pclk_pixelasync_lite_c", };
4678PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
4679 "div_pclk_lite_b", };
4680PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
4681 "mout_aclk_cam0_333_user", };
4682PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
4683 "mout_aclk_cam0_400_user", };
4684PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4685 "mout_sclk_pixelasync_lite_c_init_a",
4686 "mout_aclk_cam0_400_user", };
4687PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4688 "mout_aclk_cam0_552_user",
4689 "mout_aclk_cam0_400_user", };
4690
4691static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = {
4692 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4693 NULL, CLK_IS_ROOT, 100000000),
4694 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4695 NULL, CLK_IS_ROOT, 100000000),
4696};
4697
4698static struct samsung_mux_clock cam0_mux_clks[] __initdata = {
4699 /* MUX_SEL_CAM00 */
4700 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4701 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4702 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4703 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4704 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4705 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4706
4707 /* MUX_SEL_CAM01 */
4708 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4709 "mout_phyclk_rxbyteclkhs0_s4_user",
4710 mout_phyclk_rxbyteclkhs0_s4_user_p,
4711 MUX_SEL_CAM01, 4, 1),
4712 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4713 "mout_phyclk_rxbyteclkhs0_s2a_user",
4714 mout_phyclk_rxbyteclkhs0_s2a_user_p,
4715 MUX_SEL_CAM01, 0, 1),
4716
4717 /* MUX_SEL_CAM02 */
4718 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4719 MUX_SEL_CAM02, 24, 1),
4720 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4721 MUX_SEL_CAM02, 20, 1),
4722 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4723 MUX_SEL_CAM02, 16, 1),
4724 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4725 MUX_SEL_CAM02, 12, 1),
4726 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4727 MUX_SEL_CAM02, 8, 1),
4728 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4729 MUX_SEL_CAM02, 4, 1),
4730 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4731 MUX_SEL_CAM02, 0, 1),
4732
4733 /* MUX_SEL_CAM03 */
4734 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4735 MUX_SEL_CAM03, 28, 1),
4736 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4737 MUX_SEL_CAM03, 24, 1),
4738 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4739 MUX_SEL_CAM03, 20, 1),
4740 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4741 MUX_SEL_CAM03, 16, 1),
4742 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4743 MUX_SEL_CAM03, 12, 1),
4744 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4745 MUX_SEL_CAM03, 8, 1),
4746 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4747 MUX_SEL_CAM03, 4, 1),
4748 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4749 MUX_SEL_CAM03, 0, 1),
4750
4751 /* MUX_SEL_CAM04 */
4752 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4753 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4754 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4755 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 24, 1),
4756 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4757 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 24, 1),
4758 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4759 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 24, 1),
4760 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4761 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 24, 1),
4762 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4763 "mout_sclk_pixelasync_lite_c_init_b",
4764 mout_sclk_pixelasync_lite_c_init_b_p,
4765 MUX_SEL_CAM04, 24, 1),
4766 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4767 "mout_sclk_pixelasync_lite_c_init_a",
4768 mout_sclk_pixelasync_lite_c_init_a_p,
4769 MUX_SEL_CAM04, 24, 1),
4770};
4771
4772static struct samsung_div_clock cam0_div_clks[] __initdata = {
4773 /* DIV_CAM00 */
4774 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4775 DIV_CAM00, 8, 2),
4776 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4777 DIV_CAM00, 4, 3),
4778 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4779 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4780
4781 /* DIV_CAM01 */
4782 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4783 DIV_CAM01, 20, 2),
4784 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4785 DIV_CAM01, 16, 3),
4786 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4787 DIV_CAM01, 12, 2),
4788 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4789 DIV_CAM01, 8, 3),
4790 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4791 DIV_CAM01, 4, 2),
4792 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4793 DIV_CAM01, 0, 3),
4794
4795 /* DIV_CAM02 */
4796 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4797 DIV_CAM02, 20, 3),
4798 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4799 DIV_CAM02, 16, 3),
4800 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4801 DIV_CAM02, 12, 2),
4802 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4803 DIV_CAM02, 8, 3),
4804 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4805 DIV_CAM02, 4, 2),
4806 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4807 DIV_CAM02, 0, 3),
4808
4809 /* DIV_CAM03 */
4810 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4811 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4812 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4813 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4814 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4815 "div_sclk_pixelasync_lite_c_init",
4816 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4817};
4818
4819static struct samsung_gate_clock cam0_gate_clks[] __initdata = {
4820 /* ENABLE_ACLK_CAM00 */
4821 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4822 6, 0, 0),
4823 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4824 5, 0, 0),
4825 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4826 4, 0, 0),
4827 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4828 3, 0, 0),
4829 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4830 ENABLE_ACLK_CAM00, 2, 0, 0),
4831 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4832 ENABLE_ACLK_CAM00, 1, 0, 0),
4833 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4834 ENABLE_ACLK_CAM00, 0, 0, 0),
4835
4836 /* ENABLE_ACLK_CAM01 */
4837 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4838 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4839 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4840 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4841 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4842 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4843 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4844 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4845 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4846 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4847 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4848 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4849 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4850 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4851 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4852 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4853 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4854 "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4855 23, CLK_IGNORE_UNUSED, 0),
4856 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4857 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4858 22, CLK_IGNORE_UNUSED, 0),
4859 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4860 "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4861 21, CLK_IGNORE_UNUSED, 0),
4862 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4863 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4864 20, CLK_IGNORE_UNUSED, 0),
4865 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4866 "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4867 19, CLK_IGNORE_UNUSED, 0),
4868 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4869 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4870 18, CLK_IGNORE_UNUSED, 0),
4871 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4872 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4873 17, CLK_IGNORE_UNUSED, 0),
4874 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4875 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4876 16, CLK_IGNORE_UNUSED, 0),
4877 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4878 "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4879 15, CLK_IGNORE_UNUSED, 0),
4880 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4881 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4882 14, CLK_IGNORE_UNUSED, 0),
4883 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4884 "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4885 13, CLK_IGNORE_UNUSED, 0),
4886 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4887 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4888 12, CLK_IGNORE_UNUSED, 0),
4889 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4890 "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4891 11, CLK_IGNORE_UNUSED, 0),
4892 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4893 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4894 10, CLK_IGNORE_UNUSED, 0),
4895 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4896 "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4897 9, CLK_IGNORE_UNUSED, 0),
4898 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4899 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4900 8, CLK_IGNORE_UNUSED, 0),
4901 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4902 "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4903 7, CLK_IGNORE_UNUSED, 0),
4904 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4905 "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4906 6, CLK_IGNORE_UNUSED, 0),
4907 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4908 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4909 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4910 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4911 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4912 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4913 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4914 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4915 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4916 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4917 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4918 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4919
4920 /* ENABLE_ACLK_CAM02 */
4921 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4922 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4923 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4924 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4925 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4926 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4927 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4928 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4929 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4930 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4931 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4932 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4933 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4934 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4935 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4936 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4937 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4938 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4939 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4940 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4941
4942 /* ENABLE_PCLK_CAM0 */
4943 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4944 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4945 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4946 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4947 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4948 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
4949 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
4950 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
4951 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
4952 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
4953 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
4954 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
4955 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
4956 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
4957 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
4958 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
4959 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
4960 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
4961 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
4962 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
4963 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
4964 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
4965 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
4966 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
4967 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
4968 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
4969 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
4970 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4971 12, CLK_IGNORE_UNUSED, 0),
4972 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
4973 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4974 11, CLK_IGNORE_UNUSED, 0),
4975 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
4976 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4977 10, CLK_IGNORE_UNUSED, 0),
4978 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
4979 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
4980 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
4981 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
4982 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
4983 "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
4984 7, CLK_IGNORE_UNUSED, 0),
4985 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
4986 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
4987 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
4988 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
4989 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
4990 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
4991 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
4992 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
4993 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
4994 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
4995 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
4996 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
4997 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
4998 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
4999
5000 /* ENABLE_SCLK_CAM0 */
5001 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
5002 "mout_phyclk_rxbyteclkhs0_s4_user",
5003 ENABLE_SCLK_CAM0, 8, 0, 0),
5004 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5005 "mout_phyclk_rxbyteclkhs0_s2a_user",
5006 ENABLE_SCLK_CAM0, 7, 0, 0),
5007 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5008 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5009 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5010 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5011 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5012 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5013 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5014 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5015 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5016 "div_sclk_pixelasync_lite_c",
5017 ENABLE_SCLK_CAM0, 2, 0, 0),
5018 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5019 "div_sclk_pixelasync_lite_c_init",
5020 ENABLE_SCLK_CAM0, 1, 0, 0),
5021 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5022 "div_sclk_pixelasync_lite_c",
5023 ENABLE_SCLK_CAM0, 0, 0, 0),
5024};
5025
5026static struct samsung_cmu_info cam0_cmu_info __initdata = {
5027 .mux_clks = cam0_mux_clks,
5028 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
5029 .div_clks = cam0_div_clks,
5030 .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
5031 .gate_clks = cam0_gate_clks,
5032 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
5033 .fixed_clks = cam0_fixed_clks,
5034 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
5035 .nr_clk_ids = CAM0_NR_CLK,
5036 .clk_regs = cam0_clk_regs,
5037 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
5038};
5039
5040static void __init exynos5433_cmu_cam0_init(struct device_node *np)
5041{
5042 samsung_cmu_register_one(np, &cam0_cmu_info);
5043}
5044CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
5045 exynos5433_cmu_cam0_init);
5046
5047/*
5048 * Register offset definitions for CMU_CAM1
5049 */
5050#define MUX_SEL_CAM10 0x0200
5051#define MUX_SEL_CAM11 0x0204
5052#define MUX_SEL_CAM12 0x0208
5053#define MUX_ENABLE_CAM10 0x0300
5054#define MUX_ENABLE_CAM11 0x0304
5055#define MUX_ENABLE_CAM12 0x0308
5056#define MUX_STAT_CAM10 0x0400
5057#define MUX_STAT_CAM11 0x0404
5058#define MUX_STAT_CAM12 0x0408
5059#define MUX_IGNORE_CAM11 0x0504
5060#define DIV_CAM10 0x0600
5061#define DIV_CAM11 0x0604
5062#define DIV_STAT_CAM10 0x0700
5063#define DIV_STAT_CAM11 0x0704
5064#define ENABLE_ACLK_CAM10 0X0800
5065#define ENABLE_ACLK_CAM11 0X0804
5066#define ENABLE_ACLK_CAM12 0X0808
5067#define ENABLE_PCLK_CAM1 0X0900
5068#define ENABLE_SCLK_CAM1 0X0a00
5069#define ENABLE_IP_CAM10 0X0b00
5070#define ENABLE_IP_CAM11 0X0b04
5071#define ENABLE_IP_CAM12 0X0b08
5072
5073static unsigned long cam1_clk_regs[] __initdata = {
5074 MUX_SEL_CAM10,
5075 MUX_SEL_CAM11,
5076 MUX_SEL_CAM12,
5077 MUX_ENABLE_CAM10,
5078 MUX_ENABLE_CAM11,
5079 MUX_ENABLE_CAM12,
5080 MUX_STAT_CAM10,
5081 MUX_STAT_CAM11,
5082 MUX_STAT_CAM12,
5083 MUX_IGNORE_CAM11,
5084 DIV_CAM10,
5085 DIV_CAM11,
5086 DIV_STAT_CAM10,
5087 DIV_STAT_CAM11,
5088 ENABLE_ACLK_CAM10,
5089 ENABLE_ACLK_CAM11,
5090 ENABLE_ACLK_CAM12,
5091 ENABLE_PCLK_CAM1,
5092 ENABLE_SCLK_CAM1,
5093 ENABLE_IP_CAM10,
5094 ENABLE_IP_CAM11,
5095 ENABLE_IP_CAM12,
5096};
5097
5098PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
5099PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
5100PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
5101
5102PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
5103PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
5104PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
5105
5106PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5107 "phyclk_rxbyteclkhs0_s2b_phy", };
5108
5109PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
5110 "mout_aclk_cam1_333_user", };
5111PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
5112 "mout_aclk_cam1_400_user", };
5113
5114PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
5115 "mout_aclk_cam1_333_user", };
5116PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
5117 "mout_aclk_cam1_400_user", };
5118
5119PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5120 "mout_aclk_cam1_333_user", };
5121PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5122 "mout_aclk_cam1_400_user", };
5123
5124static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = {
5125 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5126 CLK_IS_ROOT, 100000000),
5127};
5128
5129static struct samsung_mux_clock cam1_mux_clks[] __initdata = {
5130 /* MUX_SEL_CAM10 */
5131 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5132 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5133 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5134 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5135 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5136 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5137 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5138 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5139 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5140 mout_aclk_cam1_400_user_p, MUX_SEL_CAM01, 4, 1),
5141 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5142 mout_aclk_cam1_552_user_p, MUX_SEL_CAM01, 0, 1),
5143
5144 /* MUX_SEL_CAM11 */
5145 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5146 "mout_phyclk_rxbyteclkhs0_s2b_user",
5147 mout_phyclk_rxbyteclkhs0_s2b_user_p,
5148 MUX_SEL_CAM11, 0, 1),
5149
5150 /* MUX_SEL_CAM12 */
5151 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5152 MUX_SEL_CAM12, 20, 1),
5153 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5154 MUX_SEL_CAM12, 16, 1),
5155 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5156 MUX_SEL_CAM12, 12, 1),
5157 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5158 MUX_SEL_CAM12, 8, 1),
5159 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5160 MUX_SEL_CAM12, 4, 1),
5161 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5162 MUX_SEL_CAM12, 0, 1),
5163};
5164
5165static struct samsung_div_clock cam1_div_clks[] __initdata = {
5166 /* DIV_CAM10 */
5167 DIV(CLK_DIV_SCLK_ISP_WPWM, "div_sclk_isp_wpwm",
5168 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5169 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5170 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5171 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5172 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5173 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5174 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5175 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5176 DIV_CAM10, 0, 3),
5177
5178 /* DIV_CAM11 */
5179 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5180 DIV_CAM11, 16, 3),
5181 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5182 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5183 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5184 DIV_CAM11, 4, 2),
5185 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5186 DIV_CAM11, 0, 3),
5187};
5188
5189static struct samsung_gate_clock cam1_gate_clks[] __initdata = {
5190 /* ENABLE_ACLK_CAM10 */
5191 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5192 ENABLE_ACLK_CAM10, 4, 0, 0),
5193 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5194 ENABLE_ACLK_CAM10, 3, 0, 0),
5195 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5196 ENABLE_ACLK_CAM10, 1, 0, 0),
5197 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5198 ENABLE_ACLK_CAM10, 0, 0, 0),
5199
5200 /* ENABLE_ACLK_CAM11 */
5201 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5202 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5203 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5204 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5205 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5206 "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5207 27, CLK_IGNORE_UNUSED, 0),
5208 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5209 "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5210 26, CLK_IGNORE_UNUSED, 0),
5211 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5212 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5213 25, CLK_IGNORE_UNUSED, 0),
5214 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5215 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5216 24, CLK_IGNORE_UNUSED, 0),
5217 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5218 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5219 23, CLK_IGNORE_UNUSED, 0),
5220 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5221 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5222 22, CLK_IGNORE_UNUSED, 0),
5223 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5224 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5225 21, CLK_IGNORE_UNUSED, 0),
5226 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5227 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5228 20, CLK_IGNORE_UNUSED, 0),
5229 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5230 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5231 19, CLK_IGNORE_UNUSED, 0),
5232 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5233 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5234 18, CLK_IGNORE_UNUSED, 0),
5235 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5236 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5237 17, CLK_IGNORE_UNUSED, 0),
5238 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5239 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5240 16, CLK_IGNORE_UNUSED, 0),
5241 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5242 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5243 15, CLK_IGNORE_UNUSED, 0),
5244 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5245 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5246 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5247 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5248 13, CLK_IGNORE_UNUSED, 0),
5249 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5250 "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5251 12, CLK_IGNORE_UNUSED, 0),
5252 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5253 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5254 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5255 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5256 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5257 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5258 9, CLK_IGNORE_UNUSED, 0),
5259 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5260 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5261 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5262 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5263 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5264 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5265 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5266 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5267 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5268 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5269 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5270 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5271 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5272 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5273 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5274 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5275 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5276 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5277
5278 /* ENABLE_ACLK_CAM12 */
5279 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5280 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5281 10, CLK_IGNORE_UNUSED, 0),
5282 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5283 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5284 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5285 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5286 8, CLK_IGNORE_UNUSED, 0),
5287 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5288 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5289 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5290 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5291 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5292 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5293 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5294 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5295 4, CLK_IGNORE_UNUSED, 0),
5296 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5297 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5298 3, CLK_IGNORE_UNUSED, 0),
5299 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5300 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5301 2, CLK_IGNORE_UNUSED, 0),
5302 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5303 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5304 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5305 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5306 0, CLK_IGNORE_UNUSED, 0),
5307
5308 /* ENABLE_PCLK_CAM1 */
5309 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5310 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5311 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5312 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5313 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5314 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5315 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5316 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5317 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5318 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5319 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5320 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5321 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5322 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5323 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5324 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5325 20, CLK_IGNORE_UNUSED, 0),
5326 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5327 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5328 19, CLK_IGNORE_UNUSED, 0),
5329 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5330 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5331 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5332 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5333 17, CLK_IGNORE_UNUSED, 0),
5334 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5335 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5336 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5337 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5338 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5339 "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5340 14, CLK_IGNORE_UNUSED, 0),
5341 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5342 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5343 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5344 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5345 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5346 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5347 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5348 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5349 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5350 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5351 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5352 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5353 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5354 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5355 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5356 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5357 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5358 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5359 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5360 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5361 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_wpwm", "div_pclk_cam1_83",
5362 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5363 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5364 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5365 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5366 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5367 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5368 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5369
5370 /* ENABLE_SCLK_CAM1 */
5371 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5372 15, 0, 0),
5373 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5374 14, 0, 0),
5375 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5376 13, 0, 0),
5377 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5378 12, 0, 0),
5379 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5380 "mout_phyclk_rxbyteclkhs0_s2b_user",
5381 ENABLE_SCLK_CAM1, 11, 0, 0),
5382 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5383 ENABLE_SCLK_CAM1, 10, 0, 0),
5384 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5385 ENABLE_SCLK_CAM1, 9, 0, 0),
5386 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5387 ENABLE_SCLK_CAM1, 7, 0, 0),
5388 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5389 ENABLE_SCLK_CAM1, 6, 0, 0),
5390 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5391 ENABLE_SCLK_CAM1, 5, 0, 0),
5392 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5393 ENABLE_SCLK_CAM1, 4, 0, 0),
5394 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_wpwm", "div_sclk_isp_wpwm",
5395 ENABLE_SCLK_CAM1, 3, 0, 0),
5396 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5397 ENABLE_SCLK_CAM1, 2, 0, 0),
5398 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5399 ENABLE_SCLK_CAM1, 1, 0, 0),
5400 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5401 ENABLE_SCLK_CAM1, 0, 0, 0),
5402};
5403
5404static struct samsung_cmu_info cam1_cmu_info __initdata = {
5405 .mux_clks = cam1_mux_clks,
5406 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5407 .div_clks = cam1_div_clks,
5408 .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
5409 .gate_clks = cam1_gate_clks,
5410 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
5411 .fixed_clks = cam1_fixed_clks,
5412 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
5413 .nr_clk_ids = CAM1_NR_CLK,
5414 .clk_regs = cam1_clk_regs,
5415 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
5416};
5417
5418static void __init exynos5433_cmu_cam1_init(struct device_node *np)
5419{
5420 samsung_cmu_register_one(np, &cam1_cmu_info);
5421}
5422CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1",
5423 exynos5433_cmu_cam1_init);
diff --git a/drivers/clk/samsung/clk-s5pv210.c b/drivers/clk/samsung/clk-s5pv210.c
index d270a2084644..e668e479a697 100644
--- a/drivers/clk/samsung/clk-s5pv210.c
+++ b/drivers/clk/samsung/clk-s5pv210.c
@@ -169,44 +169,44 @@ static inline void s5pv210_clk_sleep_init(void) { }
169#endif 169#endif
170 170
171/* Mux parent lists. */ 171/* Mux parent lists. */
172static const char *fin_pll_p[] __initconst = { 172static const char *fin_pll_p[] __initdata = {
173 "xxti", 173 "xxti",
174 "xusbxti" 174 "xusbxti"
175}; 175};
176 176
177static const char *mout_apll_p[] __initconst = { 177static const char *mout_apll_p[] __initdata = {
178 "fin_pll", 178 "fin_pll",
179 "fout_apll" 179 "fout_apll"
180}; 180};
181 181
182static const char *mout_mpll_p[] __initconst = { 182static const char *mout_mpll_p[] __initdata = {
183 "fin_pll", 183 "fin_pll",
184 "fout_mpll" 184 "fout_mpll"
185}; 185};
186 186
187static const char *mout_epll_p[] __initconst = { 187static const char *mout_epll_p[] __initdata = {
188 "fin_pll", 188 "fin_pll",
189 "fout_epll" 189 "fout_epll"
190}; 190};
191 191
192static const char *mout_vpllsrc_p[] __initconst = { 192static const char *mout_vpllsrc_p[] __initdata = {
193 "fin_pll", 193 "fin_pll",
194 "sclk_hdmi27m" 194 "sclk_hdmi27m"
195}; 195};
196 196
197static const char *mout_vpll_p[] __initconst = { 197static const char *mout_vpll_p[] __initdata = {
198 "mout_vpllsrc", 198 "mout_vpllsrc",
199 "fout_vpll" 199 "fout_vpll"
200}; 200};
201 201
202static const char *mout_group1_p[] __initconst = { 202static const char *mout_group1_p[] __initdata = {
203 "dout_a2m", 203 "dout_a2m",
204 "mout_mpll", 204 "mout_mpll",
205 "mout_epll", 205 "mout_epll",
206 "mout_vpll" 206 "mout_vpll"
207}; 207};
208 208
209static const char *mout_group2_p[] __initconst = { 209static const char *mout_group2_p[] __initdata = {
210 "xxti", 210 "xxti",
211 "xusbxti", 211 "xusbxti",
212 "sclk_hdmi27m", 212 "sclk_hdmi27m",
@@ -218,7 +218,7 @@ static const char *mout_group2_p[] __initconst = {
218 "mout_vpll", 218 "mout_vpll",
219}; 219};
220 220
221static const char *mout_audio0_p[] __initconst = { 221static const char *mout_audio0_p[] __initdata = {
222 "xxti", 222 "xxti",
223 "pcmcdclk0", 223 "pcmcdclk0",
224 "sclk_hdmi27m", 224 "sclk_hdmi27m",
@@ -230,7 +230,7 @@ static const char *mout_audio0_p[] __initconst = {
230 "mout_vpll", 230 "mout_vpll",
231}; 231};
232 232
233static const char *mout_audio1_p[] __initconst = { 233static const char *mout_audio1_p[] __initdata = {
234 "i2scdclk1", 234 "i2scdclk1",
235 "pcmcdclk1", 235 "pcmcdclk1",
236 "sclk_hdmi27m", 236 "sclk_hdmi27m",
@@ -242,7 +242,7 @@ static const char *mout_audio1_p[] __initconst = {
242 "mout_vpll", 242 "mout_vpll",
243}; 243};
244 244
245static const char *mout_audio2_p[] __initconst = { 245static const char *mout_audio2_p[] __initdata = {
246 "i2scdclk2", 246 "i2scdclk2",
247 "pcmcdclk2", 247 "pcmcdclk2",
248 "sclk_hdmi27m", 248 "sclk_hdmi27m",
@@ -254,63 +254,63 @@ static const char *mout_audio2_p[] __initconst = {
254 "mout_vpll", 254 "mout_vpll",
255}; 255};
256 256
257static const char *mout_spdif_p[] __initconst = { 257static const char *mout_spdif_p[] __initdata = {
258 "dout_audio0", 258 "dout_audio0",
259 "dout_audio1", 259 "dout_audio1",
260 "dout_audio3", 260 "dout_audio3",
261}; 261};
262 262
263static const char *mout_group3_p[] __initconst = { 263static const char *mout_group3_p[] __initdata = {
264 "mout_apll", 264 "mout_apll",
265 "mout_mpll" 265 "mout_mpll"
266}; 266};
267 267
268static const char *mout_group4_p[] __initconst = { 268static const char *mout_group4_p[] __initdata = {
269 "mout_mpll", 269 "mout_mpll",
270 "dout_a2m" 270 "dout_a2m"
271}; 271};
272 272
273static const char *mout_flash_p[] __initconst = { 273static const char *mout_flash_p[] __initdata = {
274 "dout_hclkd", 274 "dout_hclkd",
275 "dout_hclkp" 275 "dout_hclkp"
276}; 276};
277 277
278static const char *mout_dac_p[] __initconst = { 278static const char *mout_dac_p[] __initdata = {
279 "mout_vpll", 279 "mout_vpll",
280 "sclk_hdmiphy" 280 "sclk_hdmiphy"
281}; 281};
282 282
283static const char *mout_hdmi_p[] __initconst = { 283static const char *mout_hdmi_p[] __initdata = {
284 "sclk_hdmiphy", 284 "sclk_hdmiphy",
285 "dout_tblk" 285 "dout_tblk"
286}; 286};
287 287
288static const char *mout_mixer_p[] __initconst = { 288static const char *mout_mixer_p[] __initdata = {
289 "mout_dac", 289 "mout_dac",
290 "mout_hdmi" 290 "mout_hdmi"
291}; 291};
292 292
293static const char *mout_vpll_6442_p[] __initconst = { 293static const char *mout_vpll_6442_p[] __initdata = {
294 "fin_pll", 294 "fin_pll",
295 "fout_vpll" 295 "fout_vpll"
296}; 296};
297 297
298static const char *mout_mixer_6442_p[] __initconst = { 298static const char *mout_mixer_6442_p[] __initdata = {
299 "mout_vpll", 299 "mout_vpll",
300 "dout_mixer" 300 "dout_mixer"
301}; 301};
302 302
303static const char *mout_d0sync_6442_p[] __initconst = { 303static const char *mout_d0sync_6442_p[] __initdata = {
304 "mout_dsys", 304 "mout_dsys",
305 "div_apll" 305 "div_apll"
306}; 306};
307 307
308static const char *mout_d1sync_6442_p[] __initconst = { 308static const char *mout_d1sync_6442_p[] __initdata = {
309 "mout_psys", 309 "mout_psys",
310 "div_apll" 310 "div_apll"
311}; 311};
312 312
313static const char *mout_group2_6442_p[] __initconst = { 313static const char *mout_group2_6442_p[] __initdata = {
314 "fin_pll", 314 "fin_pll",
315 "none", 315 "none",
316 "none", 316 "none",
@@ -322,7 +322,7 @@ static const char *mout_group2_6442_p[] __initconst = {
322 "mout_vpll", 322 "mout_vpll",
323}; 323};
324 324
325static const char *mout_audio0_6442_p[] __initconst = { 325static const char *mout_audio0_6442_p[] __initdata = {
326 "fin_pll", 326 "fin_pll",
327 "pcmcdclk0", 327 "pcmcdclk0",
328 "none", 328 "none",
@@ -334,7 +334,7 @@ static const char *mout_audio0_6442_p[] __initconst = {
334 "mout_vpll", 334 "mout_vpll",
335}; 335};
336 336
337static const char *mout_audio1_6442_p[] __initconst = { 337static const char *mout_audio1_6442_p[] __initdata = {
338 "i2scdclk1", 338 "i2scdclk1",
339 "pcmcdclk1", 339 "pcmcdclk1",
340 "none", 340 "none",
@@ -347,7 +347,7 @@ static const char *mout_audio1_6442_p[] __initconst = {
347 "fin_pll", 347 "fin_pll",
348}; 348};
349 349
350static const char *mout_clksel_p[] __initconst = { 350static const char *mout_clksel_p[] __initdata = {
351 "fout_apll_clkout", 351 "fout_apll_clkout",
352 "fout_mpll_clkout", 352 "fout_mpll_clkout",
353 "fout_epll", 353 "fout_epll",
@@ -370,7 +370,7 @@ static const char *mout_clksel_p[] __initconst = {
370 "div_dclk" 370 "div_dclk"
371}; 371};
372 372
373static const char *mout_clksel_6442_p[] __initconst = { 373static const char *mout_clksel_6442_p[] __initdata = {
374 "fout_apll_clkout", 374 "fout_apll_clkout",
375 "fout_mpll_clkout", 375 "fout_mpll_clkout",
376 "fout_epll", 376 "fout_epll",
@@ -393,7 +393,7 @@ static const char *mout_clksel_6442_p[] __initconst = {
393 "div_dclk" 393 "div_dclk"
394}; 394};
395 395
396static const char *mout_clkout_p[] __initconst = { 396static const char *mout_clkout_p[] __initdata = {
397 "dout_clkout", 397 "dout_clkout",
398 "none", 398 "none",
399 "xxti", 399 "xxti",
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index af94ed82cfcb..a917c4c7eaa9 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -1057,7 +1057,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
1057 return clk; 1057 return clk;
1058} 1058}
1059 1059
1060static struct of_device_id quadfs_of_match[] = { 1060static const struct of_device_id quadfs_of_match[] = {
1061 { 1061 {
1062 .compatible = "st,stih416-quadfs216", 1062 .compatible = "st,stih416-quadfs216",
1063 .data = &st_fs216c65_416 1063 .data = &st_fs216c65_416
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 9a15ec344a85..fdcff10f6d30 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -341,7 +341,7 @@ static struct clkgena_divmux_data st_divmux_c32odf3 = {
341 .fb_start_bit_idx = 24, 341 .fb_start_bit_idx = 24,
342}; 342};
343 343
344static struct of_device_id clkgena_divmux_of_match[] = { 344static const struct of_device_id clkgena_divmux_of_match[] = {
345 { 345 {
346 .compatible = "st,clkgena-divmux-c65-hs", 346 .compatible = "st,clkgena-divmux-c65-hs",
347 .data = &st_divmux_c65hs, 347 .data = &st_divmux_c65hs,
@@ -479,7 +479,7 @@ static struct clkgena_prediv_data prediv_c32_data = {
479 .table = prediv_table16, 479 .table = prediv_table16,
480}; 480};
481 481
482static struct of_device_id clkgena_prediv_of_match[] = { 482static const struct of_device_id clkgena_prediv_of_match[] = {
483 { .compatible = "st,clkgena-prediv-c65", .data = &prediv_c65_data }, 483 { .compatible = "st,clkgena-prediv-c65", .data = &prediv_c65_data },
484 { .compatible = "st,clkgena-prediv-c32", .data = &prediv_c32_data }, 484 { .compatible = "st,clkgena-prediv-c32", .data = &prediv_c32_data },
485 {} 485 {}
@@ -586,7 +586,7 @@ static struct clkgen_mux_data stih407_a9_mux_data = {
586 .width = 2, 586 .width = 2,
587}; 587};
588 588
589static struct of_device_id mux_of_match[] = { 589static const struct of_device_id mux_of_match[] = {
590 { 590 {
591 .compatible = "st,stih416-clkgenc-vcc-hd", 591 .compatible = "st,stih416-clkgenc-vcc-hd",
592 .data = &clkgen_mux_c_vcc_hd_416, 592 .data = &clkgen_mux_c_vcc_hd_416,
@@ -693,7 +693,7 @@ static struct clkgen_vcc_data st_clkgenf_vcc_416 = {
693 .lock = &clkgenf_lock, 693 .lock = &clkgenf_lock,
694}; 694};
695 695
696static struct of_device_id vcc_of_match[] = { 696static const struct of_device_id vcc_of_match[] = {
697 { .compatible = "st,stih416-clkgenc", .data = &st_clkgenc_vcc_416 }, 697 { .compatible = "st,stih416-clkgenc", .data = &st_clkgenc_vcc_416 },
698 { .compatible = "st,stih416-clkgenf", .data = &st_clkgenf_vcc_416 }, 698 { .compatible = "st,stih416-clkgenf", .data = &st_clkgenf_vcc_416 },
699 {} 699 {}
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 29769d79e306..d204ba85db3a 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -593,7 +593,7 @@ static struct clk * __init clkgen_odf_register(const char *parent_name,
593 return clk; 593 return clk;
594} 594}
595 595
596static struct of_device_id c32_pll_of_match[] = { 596static const struct of_device_id c32_pll_of_match[] = {
597 { 597 {
598 .compatible = "st,plls-c32-a1x-0", 598 .compatible = "st,plls-c32-a1x-0",
599 .data = &st_pll3200c32_a1x_0, 599 .data = &st_pll3200c32_a1x_0,
@@ -708,7 +708,7 @@ err:
708} 708}
709CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup); 709CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup);
710 710
711static struct of_device_id c32_gpu_pll_of_match[] = { 711static const struct of_device_id c32_gpu_pll_of_match[] = {
712 { 712 {
713 .compatible = "st,stih415-gpu-pll-c32", 713 .compatible = "st,stih415-gpu-pll-c32",
714 .data = &st_pll1200c32_gpu_415, 714 .data = &st_pll1200c32_gpu_415,
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 3a5292e3fcf8..058f273d6154 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -9,6 +9,7 @@ obj-y += clk-mod0.o
9obj-y += clk-sun8i-mbus.o 9obj-y += clk-sun8i-mbus.o
10obj-y += clk-sun9i-core.o 10obj-y += clk-sun9i-core.o
11obj-y += clk-sun9i-mmc.o 11obj-y += clk-sun9i-mmc.o
12obj-y += clk-usb.o
12 13
13obj-$(CONFIG_MFD_SUN6I_PRCM) += \ 14obj-$(CONFIG_MFD_SUN6I_PRCM) += \
14 clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \ 15 clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 379324eb5486..7e1e2bd189b6 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -482,6 +482,45 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
482} 482}
483 483
484/** 484/**
485 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
486 * AHB rate is calculated as follows
487 * rate = parent_rate >> p
488 */
489
490static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
491 u8 *n, u8 *k, u8 *m, u8 *p)
492{
493 u32 div;
494
495 /* divide only */
496 if (parent_rate < *freq)
497 *freq = parent_rate;
498
499 /*
500 * user manual says valid speed is 8k ~ 276M, but tests show it
501 * can work at speeds up to 300M, just after reparenting to pll6
502 */
503 if (*freq < 8000)
504 *freq = 8000;
505 if (*freq > 300000000)
506 *freq = 300000000;
507
508 div = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
509
510 /* p = 0 ~ 3 */
511 if (div > 3)
512 div = 3;
513
514 *freq = parent_rate >> div;
515
516 /* we were called to round the frequency, we can now return */
517 if (p == NULL)
518 return;
519
520 *p = div;
521}
522
523/**
485 * sun4i_get_apb1_factors() - calculates m, p factors for APB1 524 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
486 * APB1 rate is calculated as follows 525 * APB1 rate is calculated as follows
487 * rate = (parent_rate >> p) / (m + 1); 526 * rate = (parent_rate >> p) / (m + 1);
@@ -616,6 +655,11 @@ static struct clk_factors_config sun6i_a31_pll6_config = {
616 .n_start = 1, 655 .n_start = 1,
617}; 656};
618 657
658static struct clk_factors_config sun5i_a13_ahb_config = {
659 .pshift = 4,
660 .pwidth = 2,
661};
662
619static struct clk_factors_config sun4i_apb1_config = { 663static struct clk_factors_config sun4i_apb1_config = {
620 .mshift = 0, 664 .mshift = 0,
621 .mwidth = 5, 665 .mwidth = 5,
@@ -676,6 +720,13 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
676 .name = "pll6x2", 720 .name = "pll6x2",
677}; 721};
678 722
723static const struct factors_data sun5i_a13_ahb_data __initconst = {
724 .mux = 6,
725 .muxmask = BIT(1) | BIT(0),
726 .table = &sun5i_a13_ahb_config,
727 .getter = sun5i_a13_get_ahb_factors,
728};
729
679static const struct factors_data sun4i_apb1_data __initconst = { 730static const struct factors_data sun4i_apb1_data __initconst = {
680 .mux = 24, 731 .mux = 24,
681 .muxmask = BIT(1) | BIT(0), 732 .muxmask = BIT(1) | BIT(0),
@@ -838,59 +889,6 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
838 889
839 890
840/** 891/**
841 * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
842 */
843
844struct gates_reset_data {
845 void __iomem *reg;
846 spinlock_t *lock;
847 struct reset_controller_dev rcdev;
848};
849
850static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
851 unsigned long id)
852{
853 struct gates_reset_data *data = container_of(rcdev,
854 struct gates_reset_data,
855 rcdev);
856 unsigned long flags;
857 u32 reg;
858
859 spin_lock_irqsave(data->lock, flags);
860
861 reg = readl(data->reg);
862 writel(reg & ~BIT(id), data->reg);
863
864 spin_unlock_irqrestore(data->lock, flags);
865
866 return 0;
867}
868
869static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
870 unsigned long id)
871{
872 struct gates_reset_data *data = container_of(rcdev,
873 struct gates_reset_data,
874 rcdev);
875 unsigned long flags;
876 u32 reg;
877
878 spin_lock_irqsave(data->lock, flags);
879
880 reg = readl(data->reg);
881 writel(reg | BIT(id), data->reg);
882
883 spin_unlock_irqrestore(data->lock, flags);
884
885 return 0;
886}
887
888static struct reset_control_ops sunxi_gates_reset_ops = {
889 .assert = sunxi_gates_reset_assert,
890 .deassert = sunxi_gates_reset_deassert,
891};
892
893/**
894 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks 892 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
895 */ 893 */
896 894
@@ -898,7 +896,6 @@ static struct reset_control_ops sunxi_gates_reset_ops = {
898 896
899struct gates_data { 897struct gates_data {
900 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); 898 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
901 u32 reset_mask;
902}; 899};
903 900
904static const struct gates_data sun4i_axi_gates_data __initconst = { 901static const struct gates_data sun4i_axi_gates_data __initconst = {
@@ -997,26 +994,10 @@ static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
997 .mask = {0x1F0007}, 994 .mask = {0x1F0007},
998}; 995};
999 996
1000static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
1001 .mask = {0x1C0},
1002 .reset_mask = 0x07,
1003};
1004
1005static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
1006 .mask = {0x140},
1007 .reset_mask = 0x03,
1008};
1009
1010static const struct gates_data sun6i_a31_usb_gates_data __initconst = {
1011 .mask = { BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8) },
1012 .reset_mask = BIT(2) | BIT(1) | BIT(0),
1013};
1014
1015static void __init sunxi_gates_clk_setup(struct device_node *node, 997static void __init sunxi_gates_clk_setup(struct device_node *node,
1016 struct gates_data *data) 998 struct gates_data *data)
1017{ 999{
1018 struct clk_onecell_data *clk_data; 1000 struct clk_onecell_data *clk_data;
1019 struct gates_reset_data *reset_data;
1020 const char *clk_parent; 1001 const char *clk_parent;
1021 const char *clk_name; 1002 const char *clk_name;
1022 void __iomem *reg; 1003 void __iomem *reg;
@@ -1057,21 +1038,6 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
1057 clk_data->clk_num = i; 1038 clk_data->clk_num = i;
1058 1039
1059 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1040 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1060
1061 /* Register a reset controler for gates with reset bits */
1062 if (data->reset_mask == 0)
1063 return;
1064
1065 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
1066 if (!reset_data)
1067 return;
1068
1069 reset_data->reg = reg;
1070 reset_data->lock = &clk_lock;
1071 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
1072 reset_data->rcdev.ops = &sunxi_gates_reset_ops;
1073 reset_data->rcdev.of_node = node;
1074 reset_controller_register(&reset_data->rcdev);
1075} 1041}
1076 1042
1077 1043
@@ -1080,13 +1046,20 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
1080 * sunxi_divs_clk_setup() helper data 1046 * sunxi_divs_clk_setup() helper data
1081 */ 1047 */
1082 1048
1083#define SUNXI_DIVS_MAX_QTY 2 1049#define SUNXI_DIVS_MAX_QTY 4
1084#define SUNXI_DIVISOR_WIDTH 2 1050#define SUNXI_DIVISOR_WIDTH 2
1085 1051
1086struct divs_data { 1052struct divs_data {
1087 const struct factors_data *factors; /* data for the factor clock */ 1053 const struct factors_data *factors; /* data for the factor clock */
1088 int ndivs; /* number of children */ 1054 int ndivs; /* number of outputs */
1055 /*
1056 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
1057 * self or base factor clock refers to the output from the pll
1058 * itself. The remaining refer to fixed or configurable divider
1059 * outputs.
1060 */
1089 struct { 1061 struct {
1062 u8 self; /* is it the base factor clock? (only one) */
1090 u8 fixed; /* is it a fixed divisor? if not... */ 1063 u8 fixed; /* is it a fixed divisor? if not... */
1091 struct clk_div_table *table; /* is it a table based divisor? */ 1064 struct clk_div_table *table; /* is it a table based divisor? */
1092 u8 shift; /* otherwise it's a normal divisor with this shift */ 1065 u8 shift; /* otherwise it's a normal divisor with this shift */
@@ -1109,23 +1082,27 @@ static const struct divs_data pll5_divs_data __initconst = {
1109 .div = { 1082 .div = {
1110 { .shift = 0, .pow = 0, }, /* M, DDR */ 1083 { .shift = 0, .pow = 0, }, /* M, DDR */
1111 { .shift = 16, .pow = 1, }, /* P, other */ 1084 { .shift = 16, .pow = 1, }, /* P, other */
1085 /* No output for the base factor clock */
1112 } 1086 }
1113}; 1087};
1114 1088
1115static const struct divs_data pll6_divs_data __initconst = { 1089static const struct divs_data pll6_divs_data __initconst = {
1116 .factors = &sun4i_pll6_data, 1090 .factors = &sun4i_pll6_data,
1117 .ndivs = 2, 1091 .ndivs = 4,
1118 .div = { 1092 .div = {
1119 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ 1093 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1120 { .fixed = 2 }, /* P, other */ 1094 { .fixed = 2 }, /* P, other */
1095 { .self = 1 }, /* base factor clock, 2x */
1096 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1121 } 1097 }
1122}; 1098};
1123 1099
1124static const struct divs_data sun6i_a31_pll6_divs_data __initconst = { 1100static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
1125 .factors = &sun6i_a31_pll6_data, 1101 .factors = &sun6i_a31_pll6_data,
1126 .ndivs = 1, 1102 .ndivs = 2,
1127 .div = { 1103 .div = {
1128 { .fixed = 2 }, /* normal output */ 1104 { .fixed = 2 }, /* normal output */
1105 { .self = 1 }, /* base factor clock, 2x */
1129 } 1106 }
1130}; 1107};
1131 1108
@@ -1156,6 +1133,10 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
1156 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0; 1133 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
1157 int flags, clkflags; 1134 int flags, clkflags;
1158 1135
1136 /* if number of children known, use it */
1137 if (data->ndivs)
1138 ndivs = data->ndivs;
1139
1159 /* Set up factor clock that we will be dividing */ 1140 /* Set up factor clock that we will be dividing */
1160 pclk = sunxi_factors_clk_setup(node, data->factors); 1141 pclk = sunxi_factors_clk_setup(node, data->factors);
1161 parent = __clk_get_name(pclk); 1142 parent = __clk_get_name(pclk);
@@ -1166,7 +1147,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
1166 if (!clk_data) 1147 if (!clk_data)
1167 return; 1148 return;
1168 1149
1169 clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL); 1150 clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
1170 if (!clks) 1151 if (!clks)
1171 goto free_clkdata; 1152 goto free_clkdata;
1172 1153
@@ -1176,15 +1157,17 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
1176 * our RAM clock! */ 1157 * our RAM clock! */
1177 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; 1158 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1178 1159
1179 /* if number of children known, use it */
1180 if (data->ndivs)
1181 ndivs = data->ndivs;
1182
1183 for (i = 0; i < ndivs; i++) { 1160 for (i = 0; i < ndivs; i++) {
1184 if (of_property_read_string_index(node, "clock-output-names", 1161 if (of_property_read_string_index(node, "clock-output-names",
1185 i, &clk_name) != 0) 1162 i, &clk_name) != 0)
1186 break; 1163 break;
1187 1164
1165 /* If this is the base factor clock, only update clks */
1166 if (data->div[i].self) {
1167 clk_data->clks[i] = pclk;
1168 continue;
1169 }
1170
1188 gate_hw = NULL; 1171 gate_hw = NULL;
1189 rate_hw = NULL; 1172 rate_hw = NULL;
1190 rate_ops = NULL; 1173 rate_ops = NULL;
@@ -1243,9 +1226,6 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
1243 clk_register_clkdev(clks[i], clk_name, NULL); 1226 clk_register_clkdev(clks[i], clk_name, NULL);
1244 } 1227 }
1245 1228
1246 /* The last clock available on the getter is the parent */
1247 clks[i++] = pclk;
1248
1249 /* Adjust to the real max */ 1229 /* Adjust to the real max */
1250 clk_data->clk_num = i; 1230 clk_data->clk_num = i;
1251 1231
@@ -1269,6 +1249,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
1269 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, 1249 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1270 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,}, 1250 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1271 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,}, 1251 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1252 {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
1272 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,}, 1253 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1273 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,}, 1254 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1274 {} 1255 {}
@@ -1324,9 +1305,6 @@ static const struct of_device_id clk_gates_match[] __initconst = {
1324 {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,}, 1305 {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1325 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, 1306 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1326 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,}, 1307 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1327 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1328 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1329 {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
1330 {} 1308 {}
1331}; 1309};
1332 1310
@@ -1348,15 +1326,15 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1348{ 1326{
1349 unsigned int i; 1327 unsigned int i;
1350 1328
1329 /* Register divided output clocks */
1330 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1331
1351 /* Register factor clocks */ 1332 /* Register factor clocks */
1352 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); 1333 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1353 1334
1354 /* Register divider clocks */ 1335 /* Register divider clocks */
1355 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); 1336 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1356 1337
1357 /* Register divided output clocks */
1358 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1359
1360 /* Register mux clocks */ 1338 /* Register mux clocks */
1361 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); 1339 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1362 1340
@@ -1385,6 +1363,7 @@ static void __init sun4i_a10_init_clocks(struct device_node *node)
1385CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks); 1363CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1386 1364
1387static const char *sun5i_critical_clocks[] __initdata = { 1365static const char *sun5i_critical_clocks[] __initdata = {
1366 "cpu",
1388 "pll5_ddr", 1367 "pll5_ddr",
1389 "ahb_sdram", 1368 "ahb_sdram",
1390}; 1369};
diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c
new file mode 100644
index 000000000000..a86ed2f8d7af
--- /dev/null
+++ b/drivers/clk/sunxi/clk-usb.c
@@ -0,0 +1,233 @@
1/*
2 * Copyright 2013-2015 Emilio López
3 *
4 * Emilio López <emilio@elopez.com.ar>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/reset-controller.h>
22#include <linux/spinlock.h>
23
24
25/**
26 * sunxi_usb_reset... - reset bits in usb clk registers handling
27 */
28
29struct usb_reset_data {
30 void __iomem *reg;
31 spinlock_t *lock;
32 struct clk *clk;
33 struct reset_controller_dev rcdev;
34};
35
36static int sunxi_usb_reset_assert(struct reset_controller_dev *rcdev,
37 unsigned long id)
38{
39 struct usb_reset_data *data = container_of(rcdev,
40 struct usb_reset_data,
41 rcdev);
42 unsigned long flags;
43 u32 reg;
44
45 clk_prepare_enable(data->clk);
46 spin_lock_irqsave(data->lock, flags);
47
48 reg = readl(data->reg);
49 writel(reg & ~BIT(id), data->reg);
50
51 spin_unlock_irqrestore(data->lock, flags);
52 clk_disable_unprepare(data->clk);
53
54 return 0;
55}
56
57static int sunxi_usb_reset_deassert(struct reset_controller_dev *rcdev,
58 unsigned long id)
59{
60 struct usb_reset_data *data = container_of(rcdev,
61 struct usb_reset_data,
62 rcdev);
63 unsigned long flags;
64 u32 reg;
65
66 clk_prepare_enable(data->clk);
67 spin_lock_irqsave(data->lock, flags);
68
69 reg = readl(data->reg);
70 writel(reg | BIT(id), data->reg);
71
72 spin_unlock_irqrestore(data->lock, flags);
73 clk_disable_unprepare(data->clk);
74
75 return 0;
76}
77
78static struct reset_control_ops sunxi_usb_reset_ops = {
79 .assert = sunxi_usb_reset_assert,
80 .deassert = sunxi_usb_reset_deassert,
81};
82
83/**
84 * sunxi_usb_clk_setup() - Setup function for usb gate clocks
85 */
86
87#define SUNXI_USB_MAX_SIZE 32
88
89struct usb_clk_data {
90 u32 clk_mask;
91 u32 reset_mask;
92 bool reset_needs_clk;
93};
94
95static void __init sunxi_usb_clk_setup(struct device_node *node,
96 const struct usb_clk_data *data,
97 spinlock_t *lock)
98{
99 struct clk_onecell_data *clk_data;
100 struct usb_reset_data *reset_data;
101 const char *clk_parent;
102 const char *clk_name;
103 void __iomem *reg;
104 int qty;
105 int i = 0;
106 int j = 0;
107
108 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
109 if (IS_ERR(reg))
110 return;
111
112 clk_parent = of_clk_get_parent_name(node, 0);
113 if (!clk_parent)
114 return;
115
116 /* Worst-case size approximation and memory allocation */
117 qty = find_last_bit((unsigned long *)&data->clk_mask,
118 SUNXI_USB_MAX_SIZE);
119
120 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
121 if (!clk_data)
122 return;
123
124 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
125 if (!clk_data->clks) {
126 kfree(clk_data);
127 return;
128 }
129
130 for_each_set_bit(i, (unsigned long *)&data->clk_mask,
131 SUNXI_USB_MAX_SIZE) {
132 of_property_read_string_index(node, "clock-output-names",
133 j, &clk_name);
134 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
135 clk_parent, 0,
136 reg, i, 0, lock);
137 WARN_ON(IS_ERR(clk_data->clks[i]));
138
139 j++;
140 }
141
142 /* Adjust to the real max */
143 clk_data->clk_num = i;
144
145 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
146
147 /* Register a reset controller for usb with reset bits */
148 if (data->reset_mask == 0)
149 return;
150
151 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
152 if (!reset_data)
153 return;
154
155 if (data->reset_needs_clk) {
156 reset_data->clk = of_clk_get(node, 0);
157 if (IS_ERR(reset_data->clk)) {
158 pr_err("Could not get clock for reset controls\n");
159 kfree(reset_data);
160 return;
161 }
162 }
163
164 reset_data->reg = reg;
165 reset_data->lock = lock;
166 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
167 reset_data->rcdev.ops = &sunxi_usb_reset_ops;
168 reset_data->rcdev.of_node = node;
169 reset_controller_register(&reset_data->rcdev);
170}
171
172static const struct usb_clk_data sun4i_a10_usb_clk_data __initconst = {
173 .clk_mask = BIT(8) | BIT(7) | BIT(6),
174 .reset_mask = BIT(2) | BIT(1) | BIT(0),
175};
176
177static DEFINE_SPINLOCK(sun4i_a10_usb_lock);
178
179static void __init sun4i_a10_usb_setup(struct device_node *node)
180{
181 sunxi_usb_clk_setup(node, &sun4i_a10_usb_clk_data, &sun4i_a10_usb_lock);
182}
183CLK_OF_DECLARE(sun4i_a10_usb, "allwinner,sun4i-a10-usb-clk", sun4i_a10_usb_setup);
184
185static const struct usb_clk_data sun5i_a13_usb_clk_data __initconst = {
186 .clk_mask = BIT(8) | BIT(6),
187 .reset_mask = BIT(1) | BIT(0),
188};
189
190static void __init sun5i_a13_usb_setup(struct device_node *node)
191{
192 sunxi_usb_clk_setup(node, &sun5i_a13_usb_clk_data, &sun4i_a10_usb_lock);
193}
194CLK_OF_DECLARE(sun5i_a13_usb, "allwinner,sun5i-a13-usb-clk", sun5i_a13_usb_setup);
195
196static const struct usb_clk_data sun6i_a31_usb_clk_data __initconst = {
197 .clk_mask = BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8),
198 .reset_mask = BIT(2) | BIT(1) | BIT(0),
199};
200
201static void __init sun6i_a31_usb_setup(struct device_node *node)
202{
203 sunxi_usb_clk_setup(node, &sun6i_a31_usb_clk_data, &sun4i_a10_usb_lock);
204}
205CLK_OF_DECLARE(sun6i_a31_usb, "allwinner,sun6i-a31-usb-clk", sun6i_a31_usb_setup);
206
207static const struct usb_clk_data sun9i_a80_usb_mod_data __initconst = {
208 .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
209 .reset_mask = BIT(19) | BIT(18) | BIT(17),
210 .reset_needs_clk = 1,
211};
212
213static DEFINE_SPINLOCK(a80_usb_mod_lock);
214
215static void __init sun9i_a80_usb_mod_setup(struct device_node *node)
216{
217 sunxi_usb_clk_setup(node, &sun9i_a80_usb_mod_data, &a80_usb_mod_lock);
218}
219CLK_OF_DECLARE(sun9i_a80_usb_mod, "allwinner,sun9i-a80-usb-mod-clk", sun9i_a80_usb_mod_setup);
220
221static const struct usb_clk_data sun9i_a80_usb_phy_data __initconst = {
222 .clk_mask = BIT(10) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
223 .reset_mask = BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17),
224 .reset_needs_clk = 1,
225};
226
227static DEFINE_SPINLOCK(a80_usb_phy_lock);
228
229static void __init sun9i_a80_usb_phy_setup(struct device_node *node)
230{
231 sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
232}
233CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index bfef9abdf232..05c6d08a6695 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -981,7 +981,7 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
981 struct tegra_clk_pll *pll = to_clk_pll(hw); 981 struct tegra_clk_pll *pll = to_clk_pll(hw);
982 struct tegra_clk_pll_freq_table cfg, old_cfg; 982 struct tegra_clk_pll_freq_table cfg, old_cfg;
983 unsigned long flags = 0; 983 unsigned long flags = 0;
984 int ret = 0; 984 int ret;
985 985
986 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 986 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
987 if (ret < 0) 987 if (ret < 0)
@@ -1005,7 +1005,7 @@ static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1005 unsigned long *prate) 1005 unsigned long *prate)
1006{ 1006{
1007 struct tegra_clk_pll_freq_table cfg; 1007 struct tegra_clk_pll_freq_table cfg;
1008 int ret = 0, p_div; 1008 int ret, p_div;
1009 u64 output_rate = *prate; 1009 u64 output_rate = *prate;
1010 1010
1011 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 1011 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
@@ -1073,7 +1073,7 @@ static int clk_pllc_enable(struct clk_hw *hw)
1073{ 1073{
1074 struct tegra_clk_pll *pll = to_clk_pll(hw); 1074 struct tegra_clk_pll *pll = to_clk_pll(hw);
1075 u32 val; 1075 u32 val;
1076 int ret = 0; 1076 int ret;
1077 unsigned long flags = 0; 1077 unsigned long flags = 0;
1078 1078
1079 if (pll->lock) 1079 if (pll->lock)
@@ -1223,6 +1223,7 @@ static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1223 1223
1224 return output_rate; 1224 return output_rate;
1225} 1225}
1226
1226static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1227static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1227 unsigned long parent_rate) 1228 unsigned long parent_rate)
1228{ 1229{
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
index f3b773833429..605676d368eb 100644
--- a/drivers/clk/tegra/clk-tegra-fixed.c
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -30,13 +30,12 @@
30#define OSC_CTRL_OSC_FREQ_SHIFT 28 30#define OSC_CTRL_OSC_FREQ_SHIFT 28
31#define OSC_CTRL_PLL_REF_DIV_SHIFT 26 31#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
32 32
33int __init tegra_osc_clk_init(void __iomem *clk_base, 33int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
34 struct tegra_clk *tegra_clks, 34 unsigned long *input_freqs, unsigned int num,
35 unsigned long *input_freqs, int num, 35 unsigned int clk_m_div, unsigned long *osc_freq,
36 unsigned long *osc_freq, 36 unsigned long *pll_ref_freq)
37 unsigned long *pll_ref_freq)
38{ 37{
39 struct clk *clk; 38 struct clk *clk, *osc;
40 struct clk **dt_clk; 39 struct clk **dt_clk;
41 u32 val, pll_ref_div; 40 u32 val, pll_ref_div;
42 unsigned osc_idx; 41 unsigned osc_idx;
@@ -54,22 +53,25 @@ int __init tegra_osc_clk_init(void __iomem *clk_base,
54 return -EINVAL; 53 return -EINVAL;
55 } 54 }
56 55
57 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, tegra_clks); 56 osc = clk_register_fixed_rate(NULL, "osc", NULL, CLK_IS_ROOT,
57 *osc_freq);
58
59 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
58 if (!dt_clk) 60 if (!dt_clk)
59 return 0; 61 return 0;
60 62
61 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 63 clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
62 *osc_freq); 64 0, 1, clk_m_div);
63 *dt_clk = clk; 65 *dt_clk = clk;
64 66
65 /* pll_ref */ 67 /* pll_ref */
66 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 68 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
67 pll_ref_div = 1 << val; 69 pll_ref_div = 1 << val;
68 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, tegra_clks); 70 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
69 if (!dt_clk) 71 if (!dt_clk)
70 return 0; 72 return 0;
71 73
72 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 74 clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
73 0, 1, pll_ref_div); 75 0, 1, pll_ref_div);
74 *dt_clk = clk; 76 *dt_clk = clk;
75 77
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index cef0727b9eec..46af9244ba74 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -218,7 +218,7 @@
218 .clk_id = _clk_id, \ 218 .clk_id = _clk_id, \
219 .p.parent_name = _parent_name, \ 219 .p.parent_name = _parent_name, \
220 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \ 220 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
221 _clk_num, _gate_flags, 0, NULL), \ 221 _clk_num, _gate_flags, NULL, NULL), \
222 .flags = _flags \ 222 .flags = _flags \
223 } 223 }
224 224
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d0766423a5d6..8237d16b4075 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -940,36 +940,6 @@ static struct clk **clks;
940static unsigned long osc_freq; 940static unsigned long osc_freq;
941static unsigned long pll_ref_freq; 941static unsigned long pll_ref_freq;
942 942
943static int __init tegra114_osc_clk_init(void __iomem *clk_base)
944{
945 struct clk *clk;
946 u32 val, pll_ref_div;
947
948 val = readl_relaxed(clk_base + OSC_CTRL);
949
950 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
951 if (!osc_freq) {
952 WARN_ON(1);
953 return -EINVAL;
954 }
955
956 /* clk_m */
957 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
958 osc_freq);
959 clks[TEGRA114_CLK_CLK_M] = clk;
960
961 /* pll_ref */
962 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
963 pll_ref_div = 1 << val;
964 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
965 CLK_SET_RATE_PARENT, 1, pll_ref_div);
966 clks[TEGRA114_CLK_PLL_REF] = clk;
967
968 pll_ref_freq = osc_freq / pll_ref_div;
969
970 return 0;
971}
972
973static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 943static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
974{ 944{
975 struct clk *clk; 945 struct clk *clk;
@@ -1263,6 +1233,7 @@ static void tegra114_wait_cpu_in_reset(u32 cpu)
1263 cpu_relax(); 1233 cpu_relax();
1264 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1234 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1265} 1235}
1236
1266static void tegra114_disable_cpu_clock(u32 cpu) 1237static void tegra114_disable_cpu_clock(u32 cpu)
1267{ 1238{
1268 /* flow controller would take care in the power sequence. */ 1239 /* flow controller would take care in the power sequence. */
@@ -1351,7 +1322,6 @@ static void __init tegra114_clock_apply_init_table(void)
1351 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX); 1322 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
1352} 1323}
1353 1324
1354
1355/** 1325/**
1356 * tegra114_car_barrier - wait for pending writes to the CAR to complete 1326 * tegra114_car_barrier - wait for pending writes to the CAR to complete
1357 * 1327 *
@@ -1505,7 +1475,9 @@ static void __init tegra114_clock_init(struct device_node *np)
1505 if (!clks) 1475 if (!clks)
1506 return; 1476 return;
1507 1477
1508 if (tegra114_osc_clk_init(clk_base) < 0) 1478 if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
1479 ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
1480 &pll_ref_freq) < 0)
1509 return; 1481 return;
1510 1482
1511 tegra114_fixed_clk_init(clk_base); 1483 tegra114_fixed_clk_init(clk_base);
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 9a893f2fe8e9..11f857cd5f6a 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1014,6 +1014,9 @@ static struct tegra_devclk devclks[] __initdata = {
1014 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE }, 1014 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
1015 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC }, 1015 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1016 { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, 1016 { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
1017 { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },
1018 { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },
1019 { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
1017}; 1020};
1018 1021
1019static struct clk **clks; 1022static struct clk **clks;
@@ -1110,16 +1113,18 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1110 1, 2); 1113 1, 2);
1111 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; 1114 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1112 1115
1113 clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0, 1116 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
1114 clk_base + PLLD_MISC, 30, 0, &pll_d_lock); 1117 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1115 clks[TEGRA124_CLK_PLLD_DSI] = clk; 1118 clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
1116 1119
1117 clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base, 1120 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
1118 0, 48, periph_clk_enb_refcnt); 1121 clk_base, 0, 48,
1122 periph_clk_enb_refcnt);
1119 clks[TEGRA124_CLK_DSIA] = clk; 1123 clks[TEGRA124_CLK_DSIA] = clk;
1120 1124
1121 clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base, 1125 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
1122 0, 82, periph_clk_enb_refcnt); 1126 clk_base, 0, 82,
1127 periph_clk_enb_refcnt);
1123 clks[TEGRA124_CLK_DSIB] = clk; 1128 clks[TEGRA124_CLK_DSIB] = clk;
1124 1129
1125 /* emc mux */ 1130 /* emc mux */
@@ -1395,6 +1400,8 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
1395static struct tegra_clk_init_table tegra124_init_table[] __initdata = { 1400static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1396 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0}, 1401 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
1397 {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1}, 1402 {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1403 {TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0},
1404 {TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0},
1398 /* This MUST be the last entry. */ 1405 /* This MUST be the last entry. */
1399 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, 1406 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1400}; 1407};
@@ -1475,7 +1482,8 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
1475 return; 1482 return;
1476 1483
1477 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq, 1484 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1478 ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0) 1485 ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,
1486 &pll_ref_freq) < 0)
1479 return; 1487 return;
1480 1488
1481 tegra_fixed_clk_init(tegra124_clks); 1489 tegra_fixed_clk_init(tegra124_clks);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 4b9d8bd3d0bf..4b26509fc218 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -657,16 +657,16 @@ static struct tegra_devclk devclks[] __initdata = {
657 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN }, 657 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
658 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF }, 658 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
659 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI }, 659 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
660 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA }, 660 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
661 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC }, 661 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
662 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER }, 662 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
663 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC }, 663 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
664 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD }, 664 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
665 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 }, 665 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
666 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 }, 666 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
667 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE }, 667 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
668 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD }, 668 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
669 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV }, 669 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
670 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 }, 670 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
671 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 }, 671 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
672 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 }, 672 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
@@ -1434,7 +1434,8 @@ static void __init tegra30_clock_init(struct device_node *np)
1434 return; 1434 return;
1435 1435
1436 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq, 1436 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1437 ARRAY_SIZE(tegra30_input_freq), &input_freq, NULL) < 0) 1437 ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,
1438 NULL) < 0)
1438 return; 1439 return;
1439 1440
1440 1441
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 9ddb7547cb43..41cd87c67be6 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -30,6 +30,7 @@
30#define CLK_OUT_ENB_V 0x360 30#define CLK_OUT_ENB_V 0x360
31#define CLK_OUT_ENB_W 0x364 31#define CLK_OUT_ENB_W 0x364
32#define CLK_OUT_ENB_X 0x280 32#define CLK_OUT_ENB_X 0x280
33#define CLK_OUT_ENB_Y 0x298
33#define CLK_OUT_ENB_SET_L 0x320 34#define CLK_OUT_ENB_SET_L 0x320
34#define CLK_OUT_ENB_CLR_L 0x324 35#define CLK_OUT_ENB_CLR_L 0x324
35#define CLK_OUT_ENB_SET_H 0x328 36#define CLK_OUT_ENB_SET_H 0x328
@@ -42,6 +43,8 @@
42#define CLK_OUT_ENB_CLR_W 0x44c 43#define CLK_OUT_ENB_CLR_W 0x44c
43#define CLK_OUT_ENB_SET_X 0x284 44#define CLK_OUT_ENB_SET_X 0x284
44#define CLK_OUT_ENB_CLR_X 0x288 45#define CLK_OUT_ENB_CLR_X 0x288
46#define CLK_OUT_ENB_SET_Y 0x29c
47#define CLK_OUT_ENB_CLR_Y 0x2a0
45 48
46#define RST_DEVICES_L 0x004 49#define RST_DEVICES_L 0x004
47#define RST_DEVICES_H 0x008 50#define RST_DEVICES_H 0x008
@@ -50,6 +53,7 @@
50#define RST_DEVICES_V 0x358 53#define RST_DEVICES_V 0x358
51#define RST_DEVICES_W 0x35C 54#define RST_DEVICES_W 0x35C
52#define RST_DEVICES_X 0x28C 55#define RST_DEVICES_X 0x28C
56#define RST_DEVICES_Y 0x2a4
53#define RST_DEVICES_SET_L 0x300 57#define RST_DEVICES_SET_L 0x300
54#define RST_DEVICES_CLR_L 0x304 58#define RST_DEVICES_CLR_L 0x304
55#define RST_DEVICES_SET_H 0x308 59#define RST_DEVICES_SET_H 0x308
@@ -62,6 +66,8 @@
62#define RST_DEVICES_CLR_W 0x43c 66#define RST_DEVICES_CLR_W 0x43c
63#define RST_DEVICES_SET_X 0x290 67#define RST_DEVICES_SET_X 0x290
64#define RST_DEVICES_CLR_X 0x294 68#define RST_DEVICES_CLR_X 0x294
69#define RST_DEVICES_SET_Y 0x2a8
70#define RST_DEVICES_CLR_Y 0x2ac
65 71
66/* Global data of Tegra CPU CAR ops */ 72/* Global data of Tegra CPU CAR ops */
67static struct tegra_cpu_car_ops dummy_car_ops; 73static struct tegra_cpu_car_ops dummy_car_ops;
@@ -122,6 +128,14 @@ static struct tegra_clk_periph_regs periph_regs[] = {
122 .rst_set_reg = RST_DEVICES_SET_X, 128 .rst_set_reg = RST_DEVICES_SET_X,
123 .rst_clr_reg = RST_DEVICES_CLR_X, 129 .rst_clr_reg = RST_DEVICES_CLR_X,
124 }, 130 },
131 [6] = {
132 .enb_reg = CLK_OUT_ENB_Y,
133 .enb_set_reg = CLK_OUT_ENB_SET_Y,
134 .enb_clr_reg = CLK_OUT_ENB_CLR_Y,
135 .rst_reg = RST_DEVICES_Y,
136 .rst_set_reg = RST_DEVICES_SET_Y,
137 .rst_clr_reg = RST_DEVICES_CLR_Y,
138 },
125}; 139};
126 140
127static void __iomem *clk_base; 141static void __iomem *clk_base;
@@ -272,7 +286,7 @@ void __init tegra_add_of_provider(struct device_node *np)
272 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 286 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
273 287
274 rst_ctlr.of_node = np; 288 rst_ctlr.of_node = np;
275 rst_ctlr.nr_resets = clk_num * 32; 289 rst_ctlr.nr_resets = periph_banks * 32;
276 reset_controller_register(&rst_ctlr); 290 reset_controller_register(&rst_ctlr);
277} 291}
278 292
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 4e458aa8d45c..d6ac00647faf 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -548,7 +548,7 @@ struct clk *tegra_clk_register_super_mux(const char *name,
548 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 548 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
549 549
550/** 550/**
551 * struct clk_init_tabel - clock initialization table 551 * struct clk_init_table - clock initialization table
552 * @clk_id: clock id as mentioned in device tree bindings 552 * @clk_id: clock id as mentioned in device tree bindings
553 * @parent_id: parent clock id as mentioned in device tree bindings 553 * @parent_id: parent clock id as mentioned in device tree bindings
554 * @rate: rate to set 554 * @rate: rate to set
@@ -615,10 +615,10 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
615 615
616void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks); 616void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
617void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); 617void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
618int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks, 618int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
619 unsigned long *input_freqs, int num, 619 unsigned long *input_freqs, unsigned int num,
620 unsigned long *osc_freq, 620 unsigned int clk_m_div, unsigned long *osc_freq,
621 unsigned long *pll_ref_freq); 621 unsigned long *pll_ref_freq);
622void tegra_super_clk_gen4_init(void __iomem *clk_base, 622void tegra_super_clk_gen4_init(void __iomem *clk_base,
623 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 623 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
624 struct tegra_clk_pll_params *pll_params); 624 struct tegra_clk_pll_params *pll_params);
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 72d97279eae1..49baf3831546 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -203,7 +203,7 @@ static void __init of_dra7_apll_setup(struct device_node *node)
203 ad->control_reg = ti_clk_get_reg_addr(node, 0); 203 ad->control_reg = ti_clk_get_reg_addr(node, 0);
204 ad->idlest_reg = ti_clk_get_reg_addr(node, 1); 204 ad->idlest_reg = ti_clk_get_reg_addr(node, 1);
205 205
206 if (!ad->control_reg || !ad->idlest_reg) 206 if (IS_ERR(ad->control_reg) || IS_ERR(ad->idlest_reg))
207 goto cleanup; 207 goto cleanup;
208 208
209 ad->idlest_mask = 0x1; 209 ad->idlest_mask = 0x1;
@@ -384,7 +384,8 @@ static void __init of_omap2_apll_setup(struct device_node *node)
384 ad->autoidle_reg = ti_clk_get_reg_addr(node, 1); 384 ad->autoidle_reg = ti_clk_get_reg_addr(node, 1);
385 ad->idlest_reg = ti_clk_get_reg_addr(node, 2); 385 ad->idlest_reg = ti_clk_get_reg_addr(node, 2);
386 386
387 if (!ad->control_reg || !ad->autoidle_reg || !ad->idlest_reg) 387 if (IS_ERR(ad->control_reg) || IS_ERR(ad->autoidle_reg) ||
388 IS_ERR(ad->idlest_reg))
388 goto cleanup; 389 goto cleanup;
389 390
390 clk = clk_register(NULL, &clk_hw->hw); 391 clk = clk_register(NULL, &clk_hw->hw);
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
index 8912ff80af34..e75c64c9e81c 100644
--- a/drivers/clk/ti/autoidle.c
+++ b/drivers/clk/ti/autoidle.c
@@ -119,7 +119,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)
119 clk->name = node->name; 119 clk->name = node->name;
120 clk->reg = ti_clk_get_reg_addr(node, 0); 120 clk->reg = ti_clk_get_reg_addr(node, 0);
121 121
122 if (!clk->reg) { 122 if (IS_ERR(clk->reg)) {
123 kfree(clk); 123 kfree(clk);
124 return -EINVAL; 124 return -EINVAL;
125 } 125 }
diff --git a/drivers/clk/ti/clk-3xxx-legacy.c b/drivers/clk/ti/clk-3xxx-legacy.c
index e0732a4c8f26..0b61548d569b 100644
--- a/drivers/clk/ti/clk-3xxx-legacy.c
+++ b/drivers/clk/ti/clk-3xxx-legacy.c
@@ -4320,7 +4320,6 @@ static struct ti_clk_alias omap3xxx_clks[] = {
4320 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck), 4320 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
4321 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck), 4321 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
4322 CLK(NULL, "sys_altclk", &sys_altclk), 4322 CLK(NULL, "sys_altclk", &sys_altclk),
4323 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
4324 CLK(NULL, "sys_clkout1", &sys_clkout1), 4323 CLK(NULL, "sys_clkout1", &sys_clkout1),
4325 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck), 4324 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
4326 CLK(NULL, "core_ck", &core_ck), 4325 CLK(NULL, "core_ck", &core_ck),
@@ -4369,8 +4368,6 @@ static struct ti_clk_alias omap3xxx_clks[] = {
4369 CLK(NULL, "i2c3_fck", &i2c3_fck), 4368 CLK(NULL, "i2c3_fck", &i2c3_fck),
4370 CLK(NULL, "i2c2_fck", &i2c2_fck), 4369 CLK(NULL, "i2c2_fck", &i2c2_fck),
4371 CLK(NULL, "i2c1_fck", &i2c1_fck), 4370 CLK(NULL, "i2c1_fck", &i2c1_fck),
4372 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
4373 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
4374 CLK(NULL, "core_48m_fck", &core_48m_fck), 4371 CLK(NULL, "core_48m_fck", &core_48m_fck),
4375 CLK(NULL, "mcspi4_fck", &mcspi4_fck), 4372 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
4376 CLK(NULL, "mcspi3_fck", &mcspi3_fck), 4373 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
@@ -4409,8 +4406,6 @@ static struct ti_clk_alias omap3xxx_clks[] = {
4409 CLK(NULL, "uart1_ick", &uart1_ick), 4406 CLK(NULL, "uart1_ick", &uart1_ick),
4410 CLK(NULL, "gpt11_ick", &gpt11_ick), 4407 CLK(NULL, "gpt11_ick", &gpt11_ick),
4411 CLK(NULL, "gpt10_ick", &gpt10_ick), 4408 CLK(NULL, "gpt10_ick", &gpt10_ick),
4412 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
4413 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
4414 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick), 4409 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
4415 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick), 4410 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
4416 CLK(NULL, "omapctrl_ick", &omapctrl_ick), 4411 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
@@ -4467,15 +4462,22 @@ static struct ti_clk_alias omap3xxx_clks[] = {
4467 CLK(NULL, "gpt4_ick", &gpt4_ick), 4462 CLK(NULL, "gpt4_ick", &gpt4_ick),
4468 CLK(NULL, "gpt3_ick", &gpt3_ick), 4463 CLK(NULL, "gpt3_ick", &gpt3_ick),
4469 CLK(NULL, "gpt2_ick", &gpt2_ick), 4464 CLK(NULL, "gpt2_ick", &gpt2_ick),
4465 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
4466 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
4470 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick), 4467 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
4471 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick), 4468 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
4472 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick), 4469 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
4473 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick), 4470 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
4471 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
4472 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
4474 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick), 4473 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
4475 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick), 4474 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
4475 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
4476 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
4476 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck), 4477 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
4477 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck), 4478 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
4478 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck), 4479 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
4480 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
4479 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck), 4481 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
4480 CLK("etb", "emu_src_ck", &emu_src_ck), 4482 CLK("etb", "emu_src_ck", &emu_src_ck),
4481 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck), 4483 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index 383a06e49b09..757636d166cf 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -34,7 +34,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
34 DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"), 34 DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
35 DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"), 35 DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
36 DT_CLK(NULL, "sys_altclk", "sys_altclk"), 36 DT_CLK(NULL, "sys_altclk", "sys_altclk"),
37 DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
38 DT_CLK(NULL, "sys_clkout1", "sys_clkout1"), 37 DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
39 DT_CLK(NULL, "dpll1_ck", "dpll1_ck"), 38 DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
40 DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"), 39 DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
@@ -82,8 +81,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
82 DT_CLK(NULL, "i2c3_fck", "i2c3_fck"), 81 DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
83 DT_CLK(NULL, "i2c2_fck", "i2c2_fck"), 82 DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
84 DT_CLK(NULL, "i2c1_fck", "i2c1_fck"), 83 DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
85 DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
86 DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
87 DT_CLK(NULL, "core_48m_fck", "core_48m_fck"), 84 DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
88 DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"), 85 DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
89 DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"), 86 DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
@@ -122,10 +119,6 @@ static struct ti_dt_clk omap3xxx_clks[] = {
122 DT_CLK(NULL, "uart1_ick", "uart1_ick"), 119 DT_CLK(NULL, "uart1_ick", "uart1_ick"),
123 DT_CLK(NULL, "gpt11_ick", "gpt11_ick"), 120 DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
124 DT_CLK(NULL, "gpt10_ick", "gpt10_ick"), 121 DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
125 DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
126 DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
127 DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
128 DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
129 DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"), 122 DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
130 DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"), 123 DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
131 DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"), 124 DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
@@ -179,15 +172,17 @@ static struct ti_dt_clk omap3xxx_clks[] = {
179 DT_CLK(NULL, "gpt4_ick", "gpt4_ick"), 172 DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
180 DT_CLK(NULL, "gpt3_ick", "gpt3_ick"), 173 DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
181 DT_CLK(NULL, "gpt2_ick", "gpt2_ick"), 174 DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
182 DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"), 175 DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
183 DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"), 176 DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
184 DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"), 177 DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
185 DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"),
186 DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"), 178 DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
187 DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"), 179 DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
180 DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
181 DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
188 DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"), 182 DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
189 DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"), 183 DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
190 DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"), 184 DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
185 DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
191 DT_CLK("etb", "emu_src_ck", "emu_src_ck"), 186 DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
192 DT_CLK(NULL, "emu_src_ck", "emu_src_ck"), 187 DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
193 DT_CLK(NULL, "pclk_fck", "pclk_fck"), 188 DT_CLK(NULL, "pclk_fck", "pclk_fck"),
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 4f4c87751db5..581db7711f51 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -249,17 +249,6 @@ static struct ti_dt_clk omap44xx_clks[] = {
249 DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"), 249 DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
250 DT_CLK("omap_wdt", "ick", "dummy_ck"), 250 DT_CLK("omap_wdt", "ick", "dummy_ck"),
251 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 251 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
252 DT_CLK("omap_timer.1", "timer_sys_ck", "sys_clkin_ck"),
253 DT_CLK("omap_timer.2", "timer_sys_ck", "sys_clkin_ck"),
254 DT_CLK("omap_timer.3", "timer_sys_ck", "sys_clkin_ck"),
255 DT_CLK("omap_timer.4", "timer_sys_ck", "sys_clkin_ck"),
256 DT_CLK("omap_timer.9", "timer_sys_ck", "sys_clkin_ck"),
257 DT_CLK("omap_timer.10", "timer_sys_ck", "sys_clkin_ck"),
258 DT_CLK("omap_timer.11", "timer_sys_ck", "sys_clkin_ck"),
259 DT_CLK("omap_timer.5", "timer_sys_ck", "syc_clk_div_ck"),
260 DT_CLK("omap_timer.6", "timer_sys_ck", "syc_clk_div_ck"),
261 DT_CLK("omap_timer.7", "timer_sys_ck", "syc_clk_div_ck"),
262 DT_CLK("omap_timer.8", "timer_sys_ck", "syc_clk_div_ck"),
263 DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"), 252 DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
264 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"), 253 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
265 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"), 254 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index 14160b223548..96c69a335975 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -208,17 +208,17 @@ static struct ti_dt_clk omap54xx_clks[] = {
208 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), 208 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
209 DT_CLK("omap_wdt", "ick", "dummy_ck"), 209 DT_CLK("omap_wdt", "ick", "dummy_ck"),
210 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 210 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
211 DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"), 211 DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin"),
212 DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"), 212 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin"),
213 DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"), 213 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin"),
214 DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"), 214 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin"),
215 DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"), 215 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin"),
216 DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"), 216 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin"),
217 DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"), 217 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin"),
218 DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"), 218 DT_CLK("40138000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
219 DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"), 219 DT_CLK("4013a000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
220 DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"), 220 DT_CLK("4013c000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
221 DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"), 221 DT_CLK("4013e000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
222 { .node_name = NULL }, 222 { .node_name = NULL },
223}; 223};
224 224
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index ee32f4deebf4..5d2217ae4478 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -289,17 +289,21 @@ static struct ti_dt_clk dra7xx_clks[] = {
289 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), 289 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
290 DT_CLK("omap_wdt", "ick", "dummy_ck"), 290 DT_CLK("omap_wdt", "ick", "dummy_ck"),
291 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 291 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
292 DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"), 292 DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"),
293 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"), 293 DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"),
294 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"), 294 DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"),
295 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"), 295 DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"),
296 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"), 296 DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
297 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"), 297 DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"),
298 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"), 298 DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"),
299 DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"), 299 DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
300 DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"), 300 DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
301 DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"), 301 DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
302 DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"), 302 DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
303 DT_CLK("48828000.timer", "timer_sys_ck", "timer_sys_clk_div"),
304 DT_CLK("4882a000.timer", "timer_sys_ck", "timer_sys_clk_div"),
305 DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
306 DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
303 DT_CLK(NULL, "sys_clkin", "sys_clkin1"), 307 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
304 { .node_name = NULL }, 308 { .node_name = NULL },
305}; 309};
diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
index 59bb4b39d12e..d86bc46b93bd 100644
--- a/drivers/clk/ti/clk-dra7-atl.c
+++ b/drivers/clk/ti/clk-dra7-atl.c
@@ -294,7 +294,7 @@ static int of_dra7_atl_clk_remove(struct platform_device *pdev)
294 return 0; 294 return 0;
295} 295}
296 296
297static struct of_device_id of_dra7_atl_clk_match_tbl[] = { 297static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
298 { .compatible = "ti,dra7-atl", }, 298 { .compatible = "ti,dra7-atl", },
299 {}, 299 {},
300}; 300};
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index e22b95646e09..0ebe5c51062b 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -103,7 +103,8 @@ int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
103 * @index: register index from the clock node 103 * @index: register index from the clock node
104 * 104 *
105 * Builds clock register address from device tree information. This 105 * Builds clock register address from device tree information. This
106 * is a struct of type clk_omap_reg. 106 * is a struct of type clk_omap_reg. Returns a pointer to the register
107 * address, or a pointer error value in failure.
107 */ 108 */
108void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index) 109void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
109{ 110{
@@ -121,14 +122,14 @@ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
121 122
122 if (i == CLK_MAX_MEMMAPS) { 123 if (i == CLK_MAX_MEMMAPS) {
123 pr_err("clk-provider not found for %s!\n", node->name); 124 pr_err("clk-provider not found for %s!\n", node->name);
124 return NULL; 125 return ERR_PTR(-ENOENT);
125 } 126 }
126 127
127 reg->index = i; 128 reg->index = i;
128 129
129 if (of_property_read_u32_index(node, "reg", index, &val)) { 130 if (of_property_read_u32_index(node, "reg", index, &val)) {
130 pr_err("%s must have reg[%d]!\n", node->name, index); 131 pr_err("%s must have reg[%d]!\n", node->name, index);
131 return NULL; 132 return ERR_PTR(-EINVAL);
132 } 133 }
133 134
134 reg->offset = val; 135 reg->offset = val;
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
index b4c5faccaece..35fe1085480c 100644
--- a/drivers/clk/ti/clockdomain.c
+++ b/drivers/clk/ti/clockdomain.c
@@ -52,7 +52,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node)
52 } 52 }
53} 53}
54 54
55static struct of_device_id ti_clkdm_match_table[] __initdata = { 55static const struct of_device_id ti_clkdm_match_table[] __initconst = {
56 { .compatible = "ti,clockdomain" }, 56 { .compatible = "ti,clockdomain" },
57 { } 57 { }
58}; 58};
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 3654f61912eb..96f83cedb4b3 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -69,7 +69,7 @@ struct component_clk {
69 struct list_head link; 69 struct list_head link;
70}; 70};
71 71
72static const char * __initconst component_clk_types[] = { 72static const char * const component_clk_types[] __initconst = {
73 "gate", "divider", "mux" 73 "gate", "divider", "mux"
74}; 74};
75 75
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 6211893c0980..ff5f117950a9 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -530,8 +530,8 @@ static int __init ti_clk_divider_populate(struct device_node *node,
530 u32 val; 530 u32 val;
531 531
532 *reg = ti_clk_get_reg_addr(node, 0); 532 *reg = ti_clk_get_reg_addr(node, 0);
533 if (!*reg) 533 if (IS_ERR(*reg))
534 return -EINVAL; 534 return PTR_ERR(*reg);
535 535
536 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 536 if (!of_property_read_u32(node, "ti,bit-shift", &val))
537 *shift = val; 537 *shift = val;
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 81dc4698dc41..11478a501c30 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -390,18 +390,18 @@ static void __init of_ti_dpll_setup(struct device_node *node,
390#endif 390#endif
391 } else { 391 } else {
392 dd->idlest_reg = ti_clk_get_reg_addr(node, 1); 392 dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
393 if (!dd->idlest_reg) 393 if (IS_ERR(dd->idlest_reg))
394 goto cleanup; 394 goto cleanup;
395 395
396 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2); 396 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
397 } 397 }
398 398
399 if (!dd->control_reg || !dd->mult_div1_reg) 399 if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg))
400 goto cleanup; 400 goto cleanup;
401 401
402 if (dd->autoidle_mask) { 402 if (dd->autoidle_mask) {
403 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3); 403 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
404 if (!dd->autoidle_reg) 404 if (IS_ERR(dd->autoidle_reg))
405 goto cleanup; 405 goto cleanup;
406 } 406 }
407 407
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index d21640634adf..ffcd8e09e85b 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -11,19 +11,27 @@
11 11
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/slab.h>
15#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/math64.h>
16#include <linux/of.h> 16#include <linux/of.h>
17#include <linux/of_address.h> 17#include <linux/of_address.h>
18#include <linux/clk/ti.h> 18#include <linux/clk/ti.h>
19#include <asm/div64.h>
20 19
21/* FAPLL Control Register PLL_CTRL */ 20/* FAPLL Control Register PLL_CTRL */
21#define FAPLL_MAIN_MULT_N_SHIFT 16
22#define FAPLL_MAIN_DIV_P_SHIFT 8
22#define FAPLL_MAIN_LOCK BIT(7) 23#define FAPLL_MAIN_LOCK BIT(7)
23#define FAPLL_MAIN_PLLEN BIT(3) 24#define FAPLL_MAIN_PLLEN BIT(3)
24#define FAPLL_MAIN_BP BIT(2) 25#define FAPLL_MAIN_BP BIT(2)
25#define FAPLL_MAIN_LOC_CTL BIT(0) 26#define FAPLL_MAIN_LOC_CTL BIT(0)
26 27
28#define FAPLL_MAIN_MAX_MULT_N 0xffff
29#define FAPLL_MAIN_MAX_DIV_P 0xff
30#define FAPLL_MAIN_CLEAR_MASK \
31 ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
32 (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
33 FAPLL_MAIN_LOC_CTL)
34
27/* FAPLL powerdown register PWD */ 35/* FAPLL powerdown register PWD */
28#define FAPLL_PWD_OFFSET 4 36#define FAPLL_PWD_OFFSET 4
29 37
@@ -49,6 +57,10 @@
49/* Synthesizer frequency register */ 57/* Synthesizer frequency register */
50#define SYNTH_LDFREQ BIT(31) 58#define SYNTH_LDFREQ BIT(31)
51 59
60#define SYNTH_PHASE_K 8
61#define SYNTH_MAX_INT_DIV 0xf
62#define SYNTH_MAX_DIV_M 0xff
63
52struct fapll_data { 64struct fapll_data {
53 struct clk_hw hw; 65 struct clk_hw hw;
54 void __iomem *base; 66 void __iomem *base;
@@ -79,6 +91,48 @@ static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
79 return !!(v & FAPLL_MAIN_BP); 91 return !!(v & FAPLL_MAIN_BP);
80} 92}
81 93
94static void ti_fapll_set_bypass(struct fapll_data *fd)
95{
96 u32 v = readl_relaxed(fd->base);
97
98 if (fd->bypass_bit_inverted)
99 v &= ~FAPLL_MAIN_BP;
100 else
101 v |= FAPLL_MAIN_BP;
102 writel_relaxed(v, fd->base);
103}
104
105static void ti_fapll_clear_bypass(struct fapll_data *fd)
106{
107 u32 v = readl_relaxed(fd->base);
108
109 if (fd->bypass_bit_inverted)
110 v |= FAPLL_MAIN_BP;
111 else
112 v &= ~FAPLL_MAIN_BP;
113 writel_relaxed(v, fd->base);
114}
115
116static int ti_fapll_wait_lock(struct fapll_data *fd)
117{
118 int retries = FAPLL_MAX_RETRIES;
119 u32 v;
120
121 while ((v = readl_relaxed(fd->base))) {
122 if (v & FAPLL_MAIN_LOCK)
123 return 0;
124
125 if (retries-- <= 0)
126 break;
127
128 udelay(1);
129 }
130
131 pr_err("%s failed to lock\n", fd->name);
132
133 return -ETIMEDOUT;
134}
135
82static int ti_fapll_enable(struct clk_hw *hw) 136static int ti_fapll_enable(struct clk_hw *hw)
83{ 137{
84 struct fapll_data *fd = to_fapll(hw); 138 struct fapll_data *fd = to_fapll(hw);
@@ -86,6 +140,7 @@ static int ti_fapll_enable(struct clk_hw *hw)
86 140
87 v |= FAPLL_MAIN_PLLEN; 141 v |= FAPLL_MAIN_PLLEN;
88 writel_relaxed(v, fd->base); 142 writel_relaxed(v, fd->base);
143 ti_fapll_wait_lock(fd);
89 144
90 return 0; 145 return 0;
91} 146}
@@ -141,12 +196,85 @@ static u8 ti_fapll_get_parent(struct clk_hw *hw)
141 return 0; 196 return 0;
142} 197}
143 198
199static int ti_fapll_set_div_mult(unsigned long rate,
200 unsigned long parent_rate,
201 u32 *pre_div_p, u32 *mult_n)
202{
203 /*
204 * So far no luck getting decent clock with PLL divider,
205 * PLL does not seem to lock and the signal does not look
206 * right. It seems the divider can only be used together
207 * with the multiplier?
208 */
209 if (rate < parent_rate) {
210 pr_warn("FAPLL main divider rates unsupported\n");
211 return -EINVAL;
212 }
213
214 *mult_n = rate / parent_rate;
215 if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
216 return -EINVAL;
217 *pre_div_p = 1;
218
219 return 0;
220}
221
222static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
223 unsigned long *parent_rate)
224{
225 u32 pre_div_p, mult_n;
226 int error;
227
228 if (!rate)
229 return -EINVAL;
230
231 error = ti_fapll_set_div_mult(rate, *parent_rate,
232 &pre_div_p, &mult_n);
233 if (error)
234 return error;
235
236 rate = *parent_rate / pre_div_p;
237 rate *= mult_n;
238
239 return rate;
240}
241
242static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
243 unsigned long parent_rate)
244{
245 struct fapll_data *fd = to_fapll(hw);
246 u32 pre_div_p, mult_n, v;
247 int error;
248
249 if (!rate)
250 return -EINVAL;
251
252 error = ti_fapll_set_div_mult(rate, parent_rate,
253 &pre_div_p, &mult_n);
254 if (error)
255 return error;
256
257 ti_fapll_set_bypass(fd);
258 v = readl_relaxed(fd->base);
259 v &= ~FAPLL_MAIN_CLEAR_MASK;
260 v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
261 v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
262 writel_relaxed(v, fd->base);
263 if (ti_fapll_is_enabled(hw))
264 ti_fapll_wait_lock(fd);
265 ti_fapll_clear_bypass(fd);
266
267 return 0;
268}
269
144static struct clk_ops ti_fapll_ops = { 270static struct clk_ops ti_fapll_ops = {
145 .enable = ti_fapll_enable, 271 .enable = ti_fapll_enable,
146 .disable = ti_fapll_disable, 272 .disable = ti_fapll_disable,
147 .is_enabled = ti_fapll_is_enabled, 273 .is_enabled = ti_fapll_is_enabled,
148 .recalc_rate = ti_fapll_recalc_rate, 274 .recalc_rate = ti_fapll_recalc_rate,
149 .get_parent = ti_fapll_get_parent, 275 .get_parent = ti_fapll_get_parent,
276 .round_rate = ti_fapll_round_rate,
277 .set_rate = ti_fapll_set_rate,
150}; 278};
151 279
152static int ti_fapll_synth_enable(struct clk_hw *hw) 280static int ti_fapll_synth_enable(struct clk_hw *hw)
@@ -204,7 +332,7 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
204 /* 332 /*
205 * Synth frequency integer and fractional divider. 333 * Synth frequency integer and fractional divider.
206 * Note that the phase output K is 8, so the result needs 334 * Note that the phase output K is 8, so the result needs
207 * to be multiplied by 8. 335 * to be multiplied by SYNTH_PHASE_K.
208 */ 336 */
209 if (synth->freq) { 337 if (synth->freq) {
210 u32 v, synth_int_div, synth_frac_div, synth_div_freq; 338 u32 v, synth_int_div, synth_frac_div, synth_div_freq;
@@ -215,14 +343,138 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
215 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div; 343 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
216 rate *= 10000000; 344 rate *= 10000000;
217 do_div(rate, synth_div_freq); 345 do_div(rate, synth_div_freq);
218 rate *= 8; 346 rate *= SYNTH_PHASE_K;
219 } 347 }
220 348
221 /* Synth ost-divider M */ 349 /* Synth post-divider M */
222 synth_div_m = readl_relaxed(synth->div) & 0xff; 350 synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
223 do_div(rate, synth_div_m);
224 351
225 return rate; 352 return DIV_ROUND_UP_ULL(rate, synth_div_m);
353}
354
355static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
356 unsigned long parent_rate)
357{
358 struct fapll_synth *synth = to_synth(hw);
359 unsigned long current_rate, frac_rate;
360 u32 post_div_m;
361
362 current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
363 post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
364 frac_rate = current_rate * post_div_m;
365
366 return frac_rate;
367}
368
369static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
370 unsigned long rate,
371 unsigned long parent_rate)
372{
373 u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
374
375 post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
376 post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
377 if (post_div_m > SYNTH_MAX_DIV_M)
378 return -EINVAL;
379 if (!post_div_m)
380 post_div_m = 1;
381
382 for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
383 synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
384 SYNTH_PHASE_K *
385 10000000,
386 rate * post_div_m);
387 synth_frac_div = synth_int_div % 10000000;
388 synth_int_div /= 10000000;
389
390 if (synth_int_div <= SYNTH_MAX_INT_DIV)
391 break;
392 }
393
394 if (synth_int_div > SYNTH_MAX_INT_DIV)
395 return -EINVAL;
396
397 v = readl_relaxed(synth->freq);
398 v &= ~0x1fffffff;
399 v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
400 v |= (synth_frac_div & 0xffffff);
401 v |= SYNTH_LDFREQ;
402 writel_relaxed(v, synth->freq);
403
404 return post_div_m;
405}
406
407static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
408 unsigned long *parent_rate)
409{
410 struct fapll_synth *synth = to_synth(hw);
411 struct fapll_data *fd = synth->fd;
412 unsigned long r;
413
414 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
415 return -EINVAL;
416
417 /* Only post divider m available with no fractional divider? */
418 if (!synth->freq) {
419 unsigned long frac_rate;
420 u32 synth_post_div_m;
421
422 frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
423 synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
424 r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
425 goto out;
426 }
427
428 r = *parent_rate * SYNTH_PHASE_K;
429 if (rate > r)
430 goto out;
431
432 r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
433 if (rate < r)
434 goto out;
435
436 r = rate;
437out:
438 return r;
439}
440
441static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
442 unsigned long parent_rate)
443{
444 struct fapll_synth *synth = to_synth(hw);
445 struct fapll_data *fd = synth->fd;
446 unsigned long frac_rate, post_rate = 0;
447 u32 post_div_m = 0, v;
448
449 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
450 return -EINVAL;
451
452 /* Produce the rate with just post divider M? */
453 frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
454 if (frac_rate < rate) {
455 if (!synth->freq)
456 return -EINVAL;
457 } else {
458 post_div_m = DIV_ROUND_UP(frac_rate, rate);
459 if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
460 post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
461 if (!synth->freq && !post_rate)
462 return -EINVAL;
463 }
464
465 /* Need to recalculate the fractional divider? */
466 if ((post_rate != rate) && synth->freq)
467 post_div_m = ti_fapll_synth_set_frac_rate(synth,
468 rate,
469 parent_rate);
470
471 v = readl_relaxed(synth->div);
472 v &= ~SYNTH_MAX_DIV_M;
473 v |= post_div_m;
474 v |= SYNTH_LDMDIV1;
475 writel_relaxed(v, synth->div);
476
477 return 0;
226} 478}
227 479
228static struct clk_ops ti_fapll_synt_ops = { 480static struct clk_ops ti_fapll_synt_ops = {
@@ -230,6 +482,8 @@ static struct clk_ops ti_fapll_synt_ops = {
230 .disable = ti_fapll_synth_disable, 482 .disable = ti_fapll_synth_disable,
231 .is_enabled = ti_fapll_synth_is_enabled, 483 .is_enabled = ti_fapll_synth_is_enabled,
232 .recalc_rate = ti_fapll_synth_recalc_rate, 484 .recalc_rate = ti_fapll_synth_recalc_rate,
485 .round_rate = ti_fapll_synth_round_rate,
486 .set_rate = ti_fapll_synth_set_rate,
233}; 487};
234 488
235static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd, 489static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index d493307b73f4..0c6fdfcd5f93 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -225,7 +225,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
225 225
226 if (ops != &omap_gate_clkdm_clk_ops) { 226 if (ops != &omap_gate_clkdm_clk_ops) {
227 reg = ti_clk_get_reg_addr(node, 0); 227 reg = ti_clk_get_reg_addr(node, 0);
228 if (!reg) 228 if (IS_ERR(reg))
229 return; 229 return;
230 230
231 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 231 if (!of_property_read_u32(node, "ti,bit-shift", &val))
@@ -264,7 +264,7 @@ _of_ti_composite_gate_clk_setup(struct device_node *node,
264 return; 264 return;
265 265
266 gate->enable_reg = ti_clk_get_reg_addr(node, 0); 266 gate->enable_reg = ti_clk_get_reg_addr(node, 0);
267 if (!gate->enable_reg) 267 if (IS_ERR(gate->enable_reg))
268 goto cleanup; 268 goto cleanup;
269 269
270 of_property_read_u32(node, "ti,bit-shift", &val); 270 of_property_read_u32(node, "ti,bit-shift", &val);
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index 265d91f071c5..c76230d8dd04 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -111,7 +111,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
111 u32 val; 111 u32 val;
112 112
113 reg = ti_clk_get_reg_addr(node, 0); 113 reg = ti_clk_get_reg_addr(node, 0);
114 if (!reg) 114 if (IS_ERR(reg))
115 return; 115 return;
116 116
117 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 117 if (!of_property_read_u32(node, "ti,bit-shift", &val))
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 728e253606bc..5cdeed538b08 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -210,7 +210,7 @@ static void of_mux_clk_setup(struct device_node *node)
210 210
211 reg = ti_clk_get_reg_addr(node, 0); 211 reg = ti_clk_get_reg_addr(node, 0);
212 212
213 if (!reg) 213 if (IS_ERR(reg))
214 goto cleanup; 214 goto cleanup;
215 215
216 of_property_read_u32(node, "ti,bit-shift", &shift); 216 of_property_read_u32(node, "ti,bit-shift", &shift);
@@ -283,7 +283,7 @@ static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
283 283
284 mux->reg = ti_clk_get_reg_addr(node, 0); 284 mux->reg = ti_clk_get_reg_addr(node, 0);
285 285
286 if (!mux->reg) 286 if (IS_ERR(mux->reg))
287 goto cleanup; 287 goto cleanup;
288 288
289 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 289 if (!of_property_read_u32(node, "ti,bit-shift", &val))
diff --git a/drivers/clk/versatile/clk-versatile.c b/drivers/clk/versatile/clk-versatile.c
index a76981e88cb6..7a4f8635bd1e 100644
--- a/drivers/clk/versatile/clk-versatile.c
+++ b/drivers/clk/versatile/clk-versatile.c
@@ -69,7 +69,7 @@ static void __init cm_osc_setup(struct device_node *np,
69 struct device_node *parent; 69 struct device_node *parent;
70 70
71 parent = of_get_parent(np); 71 parent = of_get_parent(np);
72 if (!np) { 72 if (!parent) {
73 pr_err("no parent on core module clock\n"); 73 pr_err("no parent on core module clock\n");
74 return; 74 return;
75 } 75 }
diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c
index 765f1e0eeeb2..89c0609e180b 100644
--- a/drivers/clk/versatile/clk-vexpress-osc.c
+++ b/drivers/clk/versatile/clk-vexpress-osc.c
@@ -110,7 +110,7 @@ static int vexpress_osc_probe(struct platform_device *pdev)
110 return 0; 110 return 0;
111} 111}
112 112
113static struct of_device_id vexpress_osc_of_match[] = { 113static const struct of_device_id vexpress_osc_of_match[] = {
114 { .compatible = "arm,vexpress-osc", }, 114 { .compatible = "arm,vexpress-osc", },
115 {} 115 {}
116}; 116};
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index f870aad57711..40cb113be6af 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -85,22 +85,22 @@ static DEFINE_SPINLOCK(canmioclk_lock);
85static DEFINE_SPINLOCK(dbgclk_lock); 85static DEFINE_SPINLOCK(dbgclk_lock);
86static DEFINE_SPINLOCK(aperclk_lock); 86static DEFINE_SPINLOCK(aperclk_lock);
87 87
88static const char *armpll_parents[] __initconst = {"armpll_int", "ps_clk"}; 88static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"};
89static const char *ddrpll_parents[] __initconst = {"ddrpll_int", "ps_clk"}; 89static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"};
90static const char *iopll_parents[] __initconst = {"iopll_int", "ps_clk"}; 90static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"};
91static const char *gem0_mux_parents[] __initconst = {"gem0_div1", "dummy_name"}; 91static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"};
92static const char *gem1_mux_parents[] __initconst = {"gem1_div1", "dummy_name"}; 92static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"};
93static const char *can0_mio_mux2_parents[] __initconst = {"can0_gate", 93static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate",
94 "can0_mio_mux"}; 94 "can0_mio_mux"};
95static const char *can1_mio_mux2_parents[] __initconst = {"can1_gate", 95static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate",
96 "can1_mio_mux"}; 96 "can1_mio_mux"};
97static const char *dbg_emio_mux_parents[] __initconst = {"dbg_div", 97static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
98 "dummy_name"}; 98 "dummy_name"};
99 99
100static const char *dbgtrc_emio_input_names[] __initconst = {"trace_emio_clk"}; 100static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"};
101static const char *gem0_emio_input_names[] __initconst = {"gem0_emio_clk"}; 101static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"};
102static const char *gem1_emio_input_names[] __initconst = {"gem1_emio_clk"}; 102static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"};
103static const char *swdt_ext_clk_input_names[] __initconst = {"swdt_ext_clk"}; 103static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
104 104
105static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 105static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
106 const char *clk_name, void __iomem *fclk_ctrl_reg, 106 const char *clk_name, void __iomem *fclk_ctrl_reg,
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index 961b9c130ea9..aab088d30199 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -282,4 +282,65 @@
282 */ 282 */
283#define NR_CLKS_DMC 21 283#define NR_CLKS_DMC 21
284 284
285/*
286 * CMU ISP
287 */
288
289/* Dividers */
290
291#define CLK_DIV_ISP1 1
292#define CLK_DIV_ISP0 2
293#define CLK_DIV_MCUISP1 3
294#define CLK_DIV_MCUISP0 4
295#define CLK_DIV_MPWM 5
296
297/* Gates */
298
299#define CLK_UART_ISP 8
300#define CLK_WDT_ISP 9
301#define CLK_PWM_ISP 10
302#define CLK_I2C1_ISP 11
303#define CLK_I2C0_ISP 12
304#define CLK_MPWM_ISP 13
305#define CLK_MCUCTL_ISP 14
306#define CLK_PPMUISPX 15
307#define CLK_PPMUISPMX 16
308#define CLK_QE_LITE1 17
309#define CLK_QE_LITE0 18
310#define CLK_QE_FD 19
311#define CLK_QE_DRC 20
312#define CLK_QE_ISP 21
313#define CLK_CSIS1 22
314#define CLK_SMMU_LITE1 23
315#define CLK_SMMU_LITE0 24
316#define CLK_SMMU_FD 25
317#define CLK_SMMU_DRC 26
318#define CLK_SMMU_ISP 27
319#define CLK_GICISP 28
320#define CLK_CSIS0 29
321#define CLK_MCUISP 30
322#define CLK_LITE1 31
323#define CLK_LITE0 32
324#define CLK_FD 33
325#define CLK_DRC 34
326#define CLK_ISP 35
327#define CLK_QE_ISPCX 36
328#define CLK_QE_SCALERP 37
329#define CLK_QE_SCALERC 38
330#define CLK_SMMU_SCALERP 39
331#define CLK_SMMU_SCALERC 40
332#define CLK_SCALERP 41
333#define CLK_SCALERC 42
334#define CLK_SPI1_ISP 43
335#define CLK_SPI0_ISP 44
336#define CLK_SMMU_ISPCX 45
337#define CLK_ASYNCAXIM 46
338#define CLK_SCLK_MPWM_ISP 47
339
340/*
341 * Total number of clocks of CMU_ISP.
342 * NOTE: Must be equal to last clock ID increased by one.
343 */
344#define NR_CLKS_ISP 48
345
285#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ 346#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
new file mode 100644
index 000000000000..5bd80d5ecd0f
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -0,0 +1,1403 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
11#define _DT_BINDINGS_CLOCK_EXYNOS5433_H
12
13/* CMU_TOP */
14#define CLK_FOUT_ISP_PLL 1
15#define CLK_FOUT_AUD_PLL 2
16
17#define CLK_MOUT_AUD_PLL 10
18#define CLK_MOUT_ISP_PLL 11
19#define CLK_MOUT_AUD_PLL_USER_T 12
20#define CLK_MOUT_MPHY_PLL_USER 13
21#define CLK_MOUT_MFC_PLL_USER 14
22#define CLK_MOUT_BUS_PLL_USER 15
23#define CLK_MOUT_ACLK_HEVC_400 16
24#define CLK_MOUT_ACLK_CAM1_333 17
25#define CLK_MOUT_ACLK_CAM1_552_B 18
26#define CLK_MOUT_ACLK_CAM1_552_A 19
27#define CLK_MOUT_ACLK_ISP_DIS_400 20
28#define CLK_MOUT_ACLK_ISP_400 21
29#define CLK_MOUT_ACLK_BUS0_400 22
30#define CLK_MOUT_ACLK_MSCL_400_B 23
31#define CLK_MOUT_ACLK_MSCL_400_A 24
32#define CLK_MOUT_ACLK_GSCL_333 25
33#define CLK_MOUT_ACLK_G2D_400_B 26
34#define CLK_MOUT_ACLK_G2D_400_A 27
35#define CLK_MOUT_SCLK_JPEG_C 28
36#define CLK_MOUT_SCLK_JPEG_B 29
37#define CLK_MOUT_SCLK_JPEG_A 30
38#define CLK_MOUT_SCLK_MMC2_B 31
39#define CLK_MOUT_SCLK_MMC2_A 32
40#define CLK_MOUT_SCLK_MMC1_B 33
41#define CLK_MOUT_SCLK_MMC1_A 34
42#define CLK_MOUT_SCLK_MMC0_D 35
43#define CLK_MOUT_SCLK_MMC0_C 36
44#define CLK_MOUT_SCLK_MMC0_B 37
45#define CLK_MOUT_SCLK_MMC0_A 38
46#define CLK_MOUT_SCLK_SPI4 39
47#define CLK_MOUT_SCLK_SPI3 40
48#define CLK_MOUT_SCLK_UART2 41
49#define CLK_MOUT_SCLK_UART1 42
50#define CLK_MOUT_SCLK_UART0 43
51#define CLK_MOUT_SCLK_SPI2 44
52#define CLK_MOUT_SCLK_SPI1 45
53#define CLK_MOUT_SCLK_SPI0 46
54#define CLK_MOUT_ACLK_MFC_400_C 47
55#define CLK_MOUT_ACLK_MFC_400_B 48
56#define CLK_MOUT_ACLK_MFC_400_A 49
57#define CLK_MOUT_SCLK_ISP_SENSOR2 50
58#define CLK_MOUT_SCLK_ISP_SENSOR1 51
59#define CLK_MOUT_SCLK_ISP_SENSOR0 52
60#define CLK_MOUT_SCLK_ISP_UART 53
61#define CLK_MOUT_SCLK_ISP_SPI1 54
62#define CLK_MOUT_SCLK_ISP_SPI0 55
63#define CLK_MOUT_SCLK_PCIE_100 56
64#define CLK_MOUT_SCLK_UFSUNIPRO 57
65#define CLK_MOUT_SCLK_USBHOST30 58
66#define CLK_MOUT_SCLK_USBDRD30 59
67#define CLK_MOUT_SCLK_SLIMBUS 60
68#define CLK_MOUT_SCLK_SPDIF 61
69#define CLK_MOUT_SCLK_AUDIO1 62
70#define CLK_MOUT_SCLK_AUDIO0 63
71#define CLK_MOUT_SCLK_HDMI_SPDIF 64
72
73#define CLK_DIV_ACLK_FSYS_200 100
74#define CLK_DIV_ACLK_IMEM_SSSX_266 101
75#define CLK_DIV_ACLK_IMEM_200 102
76#define CLK_DIV_ACLK_IMEM_266 103
77#define CLK_DIV_ACLK_PERIC_66_B 104
78#define CLK_DIV_ACLK_PERIC_66_A 105
79#define CLK_DIV_ACLK_PERIS_66_B 106
80#define CLK_DIV_ACLK_PERIS_66_A 107
81#define CLK_DIV_SCLK_MMC1_B 108
82#define CLK_DIV_SCLK_MMC1_A 109
83#define CLK_DIV_SCLK_MMC0_B 110
84#define CLK_DIV_SCLK_MMC0_A 111
85#define CLK_DIV_SCLK_MMC2_B 112
86#define CLK_DIV_SCLK_MMC2_A 113
87#define CLK_DIV_SCLK_SPI1_B 114
88#define CLK_DIV_SCLK_SPI1_A 115
89#define CLK_DIV_SCLK_SPI0_B 116
90#define CLK_DIV_SCLK_SPI0_A 117
91#define CLK_DIV_SCLK_SPI2_B 118
92#define CLK_DIV_SCLK_SPI2_A 119
93#define CLK_DIV_SCLK_UART2 120
94#define CLK_DIV_SCLK_UART1 121
95#define CLK_DIV_SCLK_UART0 122
96#define CLK_DIV_SCLK_SPI4_B 123
97#define CLK_DIV_SCLK_SPI4_A 124
98#define CLK_DIV_SCLK_SPI3_B 125
99#define CLK_DIV_SCLK_SPI3_A 126
100#define CLK_DIV_SCLK_I2S1 127
101#define CLK_DIV_SCLK_PCM1 128
102#define CLK_DIV_SCLK_AUDIO1 129
103#define CLK_DIV_SCLK_AUDIO0 130
104#define CLK_DIV_ACLK_GSCL_111 131
105#define CLK_DIV_ACLK_GSCL_333 132
106#define CLK_DIV_ACLK_HEVC_400 133
107#define CLK_DIV_ACLK_MFC_400 134
108#define CLK_DIV_ACLK_G2D_266 135
109#define CLK_DIV_ACLK_G2D_400 136
110#define CLK_DIV_ACLK_G3D_400 137
111#define CLK_DIV_ACLK_BUS0_400 138
112#define CLK_DIV_ACLK_BUS1_400 139
113#define CLK_DIV_SCLK_PCIE_100 140
114#define CLK_DIV_SCLK_USBHOST30 141
115#define CLK_DIV_SCLK_UFSUNIPRO 142
116#define CLK_DIV_SCLK_USBDRD30 143
117#define CLK_DIV_SCLK_JPEG 144
118#define CLK_DIV_ACLK_MSCL_400 145
119#define CLK_DIV_ACLK_ISP_DIS_400 146
120#define CLK_DIV_ACLK_ISP_400 147
121#define CLK_DIV_ACLK_CAM0_333 148
122#define CLK_DIV_ACLK_CAM0_400 149
123#define CLK_DIV_ACLK_CAM0_552 150
124#define CLK_DIV_ACLK_CAM1_333 151
125#define CLK_DIV_ACLK_CAM1_400 152
126#define CLK_DIV_ACLK_CAM1_552 153
127#define CLK_DIV_SCLK_ISP_UART 154
128#define CLK_DIV_SCLK_ISP_SPI1_B 155
129#define CLK_DIV_SCLK_ISP_SPI1_A 156
130#define CLK_DIV_SCLK_ISP_SPI0_B 157
131#define CLK_DIV_SCLK_ISP_SPI0_A 158
132#define CLK_DIV_SCLK_ISP_SENSOR2_B 159
133#define CLK_DIV_SCLK_ISP_SENSOR2_A 160
134#define CLK_DIV_SCLK_ISP_SENSOR1_B 161
135#define CLK_DIV_SCLK_ISP_SENSOR1_A 162
136#define CLK_DIV_SCLK_ISP_SENSOR0_B 163
137#define CLK_DIV_SCLK_ISP_SENSOR0_A 164
138
139#define CLK_ACLK_PERIC_66 200
140#define CLK_ACLK_PERIS_66 201
141#define CLK_ACLK_FSYS_200 202
142#define CLK_SCLK_MMC2_FSYS 203
143#define CLK_SCLK_MMC1_FSYS 204
144#define CLK_SCLK_MMC0_FSYS 205
145#define CLK_SCLK_SPI4_PERIC 206
146#define CLK_SCLK_SPI3_PERIC 207
147#define CLK_SCLK_UART2_PERIC 208
148#define CLK_SCLK_UART1_PERIC 209
149#define CLK_SCLK_UART0_PERIC 210
150#define CLK_SCLK_SPI2_PERIC 211
151#define CLK_SCLK_SPI1_PERIC 212
152#define CLK_SCLK_SPI0_PERIC 213
153#define CLK_SCLK_SPDIF_PERIC 214
154#define CLK_SCLK_I2S1_PERIC 215
155#define CLK_SCLK_PCM1_PERIC 216
156#define CLK_SCLK_SLIMBUS 217
157#define CLK_SCLK_AUDIO1 218
158#define CLK_SCLK_AUDIO0 219
159#define CLK_ACLK_G2D_266 220
160#define CLK_ACLK_G2D_400 221
161#define CLK_ACLK_G3D_400 222
162#define CLK_ACLK_IMEM_SSX_266 223
163#define CLK_ACLK_BUS0_400 224
164#define CLK_ACLK_BUS1_400 225
165#define CLK_ACLK_IMEM_200 226
166#define CLK_ACLK_IMEM_266 227
167#define CLK_SCLK_PCIE_100_FSYS 228
168#define CLK_SCLK_UFSUNIPRO_FSYS 229
169#define CLK_SCLK_USBHOST30_FSYS 230
170#define CLK_SCLK_USBDRD30_FSYS 231
171#define CLK_ACLK_GSCL_111 232
172#define CLK_ACLK_GSCL_333 233
173#define CLK_SCLK_JPEG_MSCL 234
174#define CLK_ACLK_MSCL_400 235
175#define CLK_ACLK_MFC_400 236
176#define CLK_ACLK_HEVC_400 237
177#define CLK_ACLK_ISP_DIS_400 238
178#define CLK_ACLK_ISP_400 239
179#define CLK_ACLK_CAM0_333 240
180#define CLK_ACLK_CAM0_400 241
181#define CLK_ACLK_CAM0_552 242
182#define CLK_ACLK_CAM1_333 243
183#define CLK_ACLK_CAM1_400 244
184#define CLK_ACLK_CAM1_552 245
185#define CLK_SCLK_ISP_SENSOR2 246
186#define CLK_SCLK_ISP_SENSOR1 247
187#define CLK_SCLK_ISP_SENSOR0 248
188#define CLK_SCLK_ISP_MCTADC_CAM1 249
189#define CLK_SCLK_ISP_UART_CAM1 250
190#define CLK_SCLK_ISP_SPI1_CAM1 251
191#define CLK_SCLK_ISP_SPI0_CAM1 252
192#define CLK_SCLK_HDMI_SPDIF_DISP 253
193
194#define TOP_NR_CLK 254
195
196/* CMU_CPIF */
197#define CLK_FOUT_MPHY_PLL 1
198
199#define CLK_MOUT_MPHY_PLL 2
200
201#define CLK_DIV_SCLK_MPHY 10
202
203#define CLK_SCLK_MPHY_PLL 11
204#define CLK_SCLK_UFS_MPHY 11
205
206#define CPIF_NR_CLK 12
207
208/* CMU_MIF */
209#define CLK_FOUT_MEM0_PLL 1
210#define CLK_FOUT_MEM1_PLL 2
211#define CLK_FOUT_BUS_PLL 3
212#define CLK_FOUT_MFC_PLL 4
213#define CLK_DOUT_MFC_PLL 5
214#define CLK_DOUT_BUS_PLL 6
215#define CLK_DOUT_MEM1_PLL 7
216#define CLK_DOUT_MEM0_PLL 8
217
218#define CLK_MOUT_MFC_PLL_DIV2 10
219#define CLK_MOUT_BUS_PLL_DIV2 11
220#define CLK_MOUT_MEM1_PLL_DIV2 12
221#define CLK_MOUT_MEM0_PLL_DIV2 13
222#define CLK_MOUT_MFC_PLL 14
223#define CLK_MOUT_BUS_PLL 15
224#define CLK_MOUT_MEM1_PLL 16
225#define CLK_MOUT_MEM0_PLL 17
226#define CLK_MOUT_CLK2X_PHY_C 18
227#define CLK_MOUT_CLK2X_PHY_B 19
228#define CLK_MOUT_CLK2X_PHY_A 20
229#define CLK_MOUT_CLKM_PHY_C 21
230#define CLK_MOUT_CLKM_PHY_B 22
231#define CLK_MOUT_CLKM_PHY_A 23
232#define CLK_MOUT_ACLK_MIFNM_200 24
233#define CLK_MOUT_ACLK_MIFNM_400 25
234#define CLK_MOUT_ACLK_DISP_333_B 26
235#define CLK_MOUT_ACLK_DISP_333_A 27
236#define CLK_MOUT_SCLK_DECON_VCLK_C 28
237#define CLK_MOUT_SCLK_DECON_VCLK_B 29
238#define CLK_MOUT_SCLK_DECON_VCLK_A 30
239#define CLK_MOUT_SCLK_DECON_ECLK_C 31
240#define CLK_MOUT_SCLK_DECON_ECLK_B 32
241#define CLK_MOUT_SCLK_DECON_ECLK_A 33
242#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34
243#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
244#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
245#define CLK_MOUT_SCLK_DSD_C 37
246#define CLK_MOUT_SCLK_DSD_B 38
247#define CLK_MOUT_SCLK_DSD_A 39
248#define CLK_MOUT_SCLK_DSIM0_C 40
249#define CLK_MOUT_SCLK_DSIM0_B 41
250#define CLK_MOUT_SCLK_DSIM0_A 42
251#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46
252#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47
253#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48
254#define CLK_MOUT_SCLK_DSIM1_C 49
255#define CLK_MOUT_SCLK_DSIM1_B 50
256#define CLK_MOUT_SCLK_DSIM1_A 51
257
258#define CLK_DIV_SCLK_HPM_MIF 55
259#define CLK_DIV_ACLK_DREX1 56
260#define CLK_DIV_ACLK_DREX0 57
261#define CLK_DIV_CLK2XPHY 58
262#define CLK_DIV_ACLK_MIF_266 59
263#define CLK_DIV_ACLK_MIFND_133 60
264#define CLK_DIV_ACLK_MIF_133 61
265#define CLK_DIV_ACLK_MIFNM_200 62
266#define CLK_DIV_ACLK_MIF_200 63
267#define CLK_DIV_ACLK_MIF_400 64
268#define CLK_DIV_ACLK_BUS2_400 65
269#define CLK_DIV_ACLK_DISP_333 66
270#define CLK_DIV_ACLK_CPIF_200 67
271#define CLK_DIV_SCLK_DSIM1 68
272#define CLK_DIV_SCLK_DECON_TV_VCLK 69
273#define CLK_DIV_SCLK_DSIM0 70
274#define CLK_DIV_SCLK_DSD 71
275#define CLK_DIV_SCLK_DECON_TV_ECLK 72
276#define CLK_DIV_SCLK_DECON_VCLK 73
277#define CLK_DIV_SCLK_DECON_ECLK 74
278#define CLK_DIV_MIF_PRE 75
279
280#define CLK_CLK2X_PHY1 80
281#define CLK_CLK2X_PHY0 81
282#define CLK_CLKM_PHY1 82
283#define CLK_CLKM_PHY0 83
284#define CLK_RCLK_DREX1 84
285#define CLK_RCLK_DREX0 85
286#define CLK_ACLK_DREX1_TZ 86
287#define CLK_ACLK_DREX0_TZ 87
288#define CLK_ACLK_DREX1_PEREV 88
289#define CLK_ACLK_DREX0_PEREV 89
290#define CLK_ACLK_DREX1_MEMIF 90
291#define CLK_ACLK_DREX0_MEMIF 91
292#define CLK_ACLK_DREX1_SCH 92
293#define CLK_ACLK_DREX0_SCH 93
294#define CLK_ACLK_DREX1_BUSIF 94
295#define CLK_ACLK_DREX0_BUSIF 95
296#define CLK_ACLK_DREX1_BUSIF_RD 96
297#define CLK_ACLK_DREX0_BUSIF_RD 97
298#define CLK_ACLK_DREX1 98
299#define CLK_ACLK_DREX0 99
300#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100
301#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101
302#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102
303#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103
304#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104
305#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105
306#define CLK_ACLK_ASYNCAXIS_CP1 106
307#define CLK_ACLK_ASYNCAXIM_CP1 107
308#define CLK_ACLK_ASYNCAXIS_CP0 108
309#define CLK_ACLK_ASYNCAXIM_CP0 109
310#define CLK_ACLK_ASYNCAXIS_DREX1_3 110
311#define CLK_ACLK_ASYNCAXIM_DREX1_3 111
312#define CLK_ACLK_ASYNCAXIS_DREX1_1 112
313#define CLK_ACLK_ASYNCAXIM_DREX1_1 113
314#define CLK_ACLK_ASYNCAXIS_DREX1_0 114
315#define CLK_ACLK_ASYNCAXIM_DREX1_0 115
316#define CLK_ACLK_ASYNCAXIS_DREX0_3 116
317#define CLK_ACLK_ASYNCAXIM_DREX0_3 117
318#define CLK_ACLK_ASYNCAXIS_DREX0_1 118
319#define CLK_ACLK_ASYNCAXIM_DREX0_1 119
320#define CLK_ACLK_ASYNCAXIS_DREX0_0 120
321#define CLK_ACLK_ASYNCAXIM_DREX0_0 121
322#define CLK_ACLK_AHB2APB_MIF2P 122
323#define CLK_ACLK_AHB2APB_MIF1P 123
324#define CLK_ACLK_AHB2APB_MIF0P 124
325#define CLK_ACLK_IXIU_CCI 125
326#define CLK_ACLK_XIU_MIFSFRX 126
327#define CLK_ACLK_MIFNP_133 127
328#define CLK_ACLK_MIFNM_200 128
329#define CLK_ACLK_MIFND_133 129
330#define CLK_ACLK_MIFND_400 130
331#define CLK_ACLK_CCI 131
332#define CLK_ACLK_MIFND_266 132
333#define CLK_ACLK_PPMU_DREX1S3 133
334#define CLK_ACLK_PPMU_DREX1S1 134
335#define CLK_ACLK_PPMU_DREX1S0 135
336#define CLK_ACLK_PPMU_DREX0S3 136
337#define CLK_ACLK_PPMU_DREX0S1 137
338#define CLK_ACLK_PPMU_DREX0S0 138
339#define CLK_ACLK_BTS_APOLLO 139
340#define CLK_ACLK_BTS_ATLAS 140
341#define CLK_ACLK_ACE_SEL_APOLL 141
342#define CLK_ACLK_ACE_SEL_ATLAS 142
343#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143
344#define CLK_ACLK_AXIUS_ATLAS_CCI 144
345#define CLK_ACLK_AXISYNCDNS_CCI 145
346#define CLK_ACLK_AXISYNCDN_CCI 146
347#define CLK_ACLK_AXISYNCDN_NOC_D 147
348#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148
349#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149
350#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150
351#define CLK_ACLK_BUS2_400 151
352#define CLK_ACLK_DISP_333 152
353#define CLK_ACLK_CPIF_200 153
354#define CLK_PCLK_PPMU_DREX1S3 154
355#define CLK_PCLK_PPMU_DREX1S1 155
356#define CLK_PCLK_PPMU_DREX1S0 156
357#define CLK_PCLK_PPMU_DREX0S3 157
358#define CLK_PCLK_PPMU_DREX0S1 158
359#define CLK_PCLK_PPMU_DREX0S0 159
360#define CLK_PCLK_BTS_APOLLO 160
361#define CLK_PCLK_BTS_ATLAS 161
362#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162
363#define CLK_PCLK_ASYNCAXI_CP1 163
364#define CLK_PCLK_ASYNCAXI_CP0 164
365#define CLK_PCLK_ASYNCAXI_DREX1_3 165
366#define CLK_PCLK_ASYNCAXI_DREX1_1 166
367#define CLK_PCLK_ASYNCAXI_DREX1_0 167
368#define CLK_PCLK_ASYNCAXI_DREX0_3 168
369#define CLK_PCLK_ASYNCAXI_DREX0_1 169
370#define CLK_PCLK_ASYNCAXI_DREX0_0 170
371#define CLK_PCLK_MIFSRVND_133 171
372#define CLK_PCLK_PMU_MIF 172
373#define CLK_PCLK_SYSREG_MIF 173
374#define CLK_PCLK_GPIO_ALIVE 174
375#define CLK_PCLK_ABB 175
376#define CLK_PCLK_PMU_APBIF 176
377#define CLK_PCLK_DDR_PHY1 177
378#define CLK_PCLK_DREX1 178
379#define CLK_PCLK_DDR_PHY0 179
380#define CLK_PCLK_DREX0 180
381#define CLK_PCLK_DREX0_TZ 181
382#define CLK_PCLK_DREX1_TZ 182
383#define CLK_PCLK_MONOTONIC_CNT 183
384#define CLK_PCLK_RTC 184
385#define CLK_SCLK_DSIM1_DISP 185
386#define CLK_SCLK_DECON_TV_VCLK_DISP 186
387#define CLK_SCLK_FREQ_DET_BUS_PLL 187
388#define CLK_SCLK_FREQ_DET_MFC_PLL 188
389#define CLK_SCLK_FREQ_DET_MEM0_PLL 189
390#define CLK_SCLK_FREQ_DET_MEM1_PLL 190
391#define CLK_SCLK_DSIM0_DISP 191
392#define CLK_SCLK_DSD_DISP 192
393#define CLK_SCLK_DECON_TV_ECLK_DISP 193
394#define CLK_SCLK_DECON_VCLK_DISP 194
395#define CLK_SCLK_DECON_ECLK_DISP 195
396#define CLK_SCLK_HPM_MIF 196
397#define CLK_SCLK_MFC_PLL 197
398#define CLK_SCLK_BUS_PLL 198
399#define CLK_SCLK_BUS_PLL_APOLLO 199
400#define CLK_SCLK_BUS_PLL_ATLAS 200
401
402#define MIF_NR_CLK 201
403
404/* CMU_PERIC */
405#define CLK_PCLK_SPI2 1
406#define CLK_PCLK_SPI1 2
407#define CLK_PCLK_SPI0 3
408#define CLK_PCLK_UART2 4
409#define CLK_PCLK_UART1 5
410#define CLK_PCLK_UART0 6
411#define CLK_PCLK_HSI2C3 7
412#define CLK_PCLK_HSI2C2 8
413#define CLK_PCLK_HSI2C1 9
414#define CLK_PCLK_HSI2C0 10
415#define CLK_PCLK_I2C7 11
416#define CLK_PCLK_I2C6 12
417#define CLK_PCLK_I2C5 13
418#define CLK_PCLK_I2C4 14
419#define CLK_PCLK_I2C3 15
420#define CLK_PCLK_I2C2 16
421#define CLK_PCLK_I2C1 17
422#define CLK_PCLK_I2C0 18
423#define CLK_PCLK_SPI4 19
424#define CLK_PCLK_SPI3 20
425#define CLK_PCLK_HSI2C11 21
426#define CLK_PCLK_HSI2C10 22
427#define CLK_PCLK_HSI2C9 23
428#define CLK_PCLK_HSI2C8 24
429#define CLK_PCLK_HSI2C7 25
430#define CLK_PCLK_HSI2C6 26
431#define CLK_PCLK_HSI2C5 27
432#define CLK_PCLK_HSI2C4 28
433#define CLK_SCLK_SPI4 29
434#define CLK_SCLK_SPI3 30
435#define CLK_SCLK_SPI2 31
436#define CLK_SCLK_SPI1 32
437#define CLK_SCLK_SPI0 33
438#define CLK_SCLK_UART2 34
439#define CLK_SCLK_UART1 35
440#define CLK_SCLK_UART0 36
441#define CLK_ACLK_AHB2APB_PERIC2P 37
442#define CLK_ACLK_AHB2APB_PERIC1P 38
443#define CLK_ACLK_AHB2APB_PERIC0P 39
444#define CLK_ACLK_PERICNP_66 40
445#define CLK_PCLK_SCI 41
446#define CLK_PCLK_GPIO_FINGER 42
447#define CLK_PCLK_GPIO_ESE 43
448#define CLK_PCLK_PWM 44
449#define CLK_PCLK_SPDIF 45
450#define CLK_PCLK_PCM1 46
451#define CLK_PCLK_I2S1 47
452#define CLK_PCLK_ADCIF 48
453#define CLK_PCLK_GPIO_TOUCH 49
454#define CLK_PCLK_GPIO_NFC 50
455#define CLK_PCLK_GPIO_PERIC 51
456#define CLK_PCLK_PMU_PERIC 52
457#define CLK_PCLK_SYSREG_PERIC 53
458#define CLK_SCLK_IOCLK_SPI4 54
459#define CLK_SCLK_IOCLK_SPI3 55
460#define CLK_SCLK_SCI 56
461#define CLK_SCLK_SC_IN 57
462#define CLK_SCLK_PWM 58
463#define CLK_SCLK_IOCLK_SPI2 59
464#define CLK_SCLK_IOCLK_SPI1 60
465#define CLK_SCLK_IOCLK_SPI0 61
466#define CLK_SCLK_IOCLK_I2S1_BCLK 62
467#define CLK_SCLK_SPDIF 63
468#define CLK_SCLK_PCM1 64
469#define CLK_SCLK_I2S1 65
470
471#define CLK_DIV_SCLK_SCI 70
472#define CLK_DIV_SCLK_SC_IN 71
473
474#define PERIC_NR_CLK 72
475
476/* CMU_PERIS */
477#define CLK_PCLK_HPM_APBIF 1
478#define CLK_PCLK_TMU1_APBIF 2
479#define CLK_PCLK_TMU0_APBIF 3
480#define CLK_PCLK_PMU_PERIS 4
481#define CLK_PCLK_SYSREG_PERIS 5
482#define CLK_PCLK_CMU_TOP_APBIF 6
483#define CLK_PCLK_WDT_APOLLO 7
484#define CLK_PCLK_WDT_ATLAS 8
485#define CLK_PCLK_MCT 9
486#define CLK_PCLK_HDMI_CEC 10
487#define CLK_ACLK_AHB2APB_PERIS1P 11
488#define CLK_ACLK_AHB2APB_PERIS0P 12
489#define CLK_ACLK_PERISNP_66 13
490#define CLK_PCLK_TZPC12 14
491#define CLK_PCLK_TZPC11 15
492#define CLK_PCLK_TZPC10 16
493#define CLK_PCLK_TZPC9 17
494#define CLK_PCLK_TZPC8 18
495#define CLK_PCLK_TZPC7 19
496#define CLK_PCLK_TZPC6 20
497#define CLK_PCLK_TZPC5 21
498#define CLK_PCLK_TZPC4 22
499#define CLK_PCLK_TZPC3 23
500#define CLK_PCLK_TZPC2 24
501#define CLK_PCLK_TZPC1 25
502#define CLK_PCLK_TZPC0 26
503#define CLK_PCLK_SECKEY_APBIF 27
504#define CLK_PCLK_CHIPID_APBIF 28
505#define CLK_PCLK_TOPRTC 29
506#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30
507#define CLK_PCLK_ANTIRBK_CNT_APBIF 31
508#define CLK_PCLK_OTP_CON_APBIF 32
509#define CLK_SCLK_ASV_TB 33
510#define CLK_SCLK_TMU1 34
511#define CLK_SCLK_TMU0 35
512#define CLK_SCLK_SECKEY 36
513#define CLK_SCLK_CHIPID 37
514#define CLK_SCLK_TOPRTC 38
515#define CLK_SCLK_CUSTOM_EFUSE 39
516#define CLK_SCLK_ANTIRBK_CNT 40
517#define CLK_SCLK_OTP_CON 41
518
519#define PERIS_NR_CLK 42
520
521/* CMU_FSYS */
522#define CLK_MOUT_ACLK_FSYS_200_USER 1
523#define CLK_MOUT_SCLK_MMC2_USER 2
524#define CLK_MOUT_SCLK_MMC1_USER 3
525#define CLK_MOUT_SCLK_MMC0_USER 4
526#define CLK_MOUT_SCLK_UFS_MPHY_USER 5
527#define CLK_MOUT_SCLK_PCIE_100_USER 6
528#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7
529#define CLK_MOUT_SCLK_USBHOST30_USER 8
530#define CLK_MOUT_SCLK_USBDRD30_USER 9
531#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10
532#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11
533#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12
534#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13
535#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14
536#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15
537#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16
538#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17
539#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
540#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19
541#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20
542#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21
543#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22
544#define CLK_MOUT_SCLK_MPHY 23
545
546#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25
547#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26
548#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27
549#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28
550#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29
551#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30
552#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31
553#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32
554#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33
555#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34
556#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35
557#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36
558#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37
559
560#define CLK_ACLK_PCIE 50
561#define CLK_ACLK_PDMA1 51
562#define CLK_ACLK_TSI 52
563#define CLK_ACLK_MMC2 53
564#define CLK_ACLK_MMC1 54
565#define CLK_ACLK_MMC0 55
566#define CLK_ACLK_UFS 56
567#define CLK_ACLK_USBHOST20 57
568#define CLK_ACLK_USBHOST30 58
569#define CLK_ACLK_USBDRD30 59
570#define CLK_ACLK_PDMA0 60
571#define CLK_SCLK_MMC2 61
572#define CLK_SCLK_MMC1 62
573#define CLK_SCLK_MMC0 63
574#define CLK_PDMA1 64
575#define CLK_PDMA0 65
576#define CLK_ACLK_XIU_FSYSPX 66
577#define CLK_ACLK_AHB_USBLINKH1 67
578#define CLK_ACLK_SMMU_PDMA1 68
579#define CLK_ACLK_BTS_PCIE 69
580#define CLK_ACLK_AXIUS_PDMA1 70
581#define CLK_ACLK_SMMU_PDMA0 71
582#define CLK_ACLK_BTS_UFS 72
583#define CLK_ACLK_BTS_USBHOST30 73
584#define CLK_ACLK_BTS_USBDRD30 74
585#define CLK_ACLK_AXIUS_PDMA0 75
586#define CLK_ACLK_AXIUS_USBHS 76
587#define CLK_ACLK_AXIUS_FSYSSX 77
588#define CLK_ACLK_AHB2APB_FSYSP 78
589#define CLK_ACLK_AHB2AXI_USBHS 79
590#define CLK_ACLK_AHB_USBLINKH0 80
591#define CLK_ACLK_AHB_USBHS 81
592#define CLK_ACLK_AHB_FSYSH 82
593#define CLK_ACLK_XIU_FSYSX 83
594#define CLK_ACLK_XIU_FSYSSX 84
595#define CLK_ACLK_FSYSNP_200 85
596#define CLK_ACLK_FSYSND_200 86
597#define CLK_PCLK_PCIE_CTRL 87
598#define CLK_PCLK_SMMU_PDMA1 88
599#define CLK_PCLK_PCIE_PHY 89
600#define CLK_PCLK_BTS_PCIE 90
601#define CLK_PCLK_SMMU_PDMA0 91
602#define CLK_PCLK_BTS_UFS 92
603#define CLK_PCLK_BTS_USBHOST30 93
604#define CLK_PCLK_BTS_USBDRD30 94
605#define CLK_PCLK_GPIO_FSYS 95
606#define CLK_PCLK_PMU_FSYS 96
607#define CLK_PCLK_SYSREG_FSYS 97
608#define CLK_SCLK_PCIE_100 98
609#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99
610#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100
611#define CLK_PHYCLK_UFS_RX1_SYMBOL 101
612#define CLK_PHYCLK_UFS_RX0_SYMBOL 102
613#define CLK_PHYCLK_UFS_TX1_SYMBOL 103
614#define CLK_PHYCLK_UFS_TX0_SYMBOL 104
615#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105
616#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106
617#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107
618#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108
619#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109
620#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110
621#define CLK_SCLK_MPHY 111
622#define CLK_SCLK_UFSUNIPRO 112
623#define CLK_SCLK_USBHOST30 113
624#define CLK_SCLK_USBDRD30 114
625
626#define FSYS_NR_CLK 115
627
628/* CMU_G2D */
629#define CLK_MUX_ACLK_G2D_266_USER 1
630#define CLK_MUX_ACLK_G2D_400_USER 2
631
632#define CLK_DIV_PCLK_G2D 3
633
634#define CLK_ACLK_SMMU_MDMA1 4
635#define CLK_ACLK_BTS_MDMA1 5
636#define CLK_ACLK_BTS_G2D 6
637#define CLK_ACLK_ALB_G2D 7
638#define CLK_ACLK_AXIUS_G2DX 8
639#define CLK_ACLK_ASYNCAXI_SYSX 9
640#define CLK_ACLK_AHB2APB_G2D1P 10
641#define CLK_ACLK_AHB2APB_G2D0P 11
642#define CLK_ACLK_XIU_G2DX 12
643#define CLK_ACLK_G2DNP_133 13
644#define CLK_ACLK_G2DND_400 14
645#define CLK_ACLK_MDMA1 15
646#define CLK_ACLK_G2D 16
647#define CLK_ACLK_SMMU_G2D 17
648#define CLK_PCLK_SMMU_MDMA1 18
649#define CLK_PCLK_BTS_MDMA1 19
650#define CLK_PCLK_BTS_G2D 20
651#define CLK_PCLK_ALB_G2D 21
652#define CLK_PCLK_ASYNCAXI_SYSX 22
653#define CLK_PCLK_PMU_G2D 23
654#define CLK_PCLK_SYSREG_G2D 24
655#define CLK_PCLK_G2D 25
656#define CLK_PCLK_SMMU_G2D 26
657
658#define G2D_NR_CLK 27
659
660/* CMU_DISP */
661#define CLK_FOUT_DISP_PLL 1
662
663#define CLK_MOUT_DISP_PLL 2
664#define CLK_MOUT_SCLK_DSIM1_USER 3
665#define CLK_MOUT_SCLK_DSIM0_USER 4
666#define CLK_MOUT_SCLK_DSD_USER 5
667#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6
668#define CLK_MOUT_SCLK_DECON_VCLK_USER 7
669#define CLK_MOUT_SCLK_DECON_ECLK_USER 8
670#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9
671#define CLK_MOUT_ACLK_DISP_333_USER 10
672#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11
673#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12
674#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13
675#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14
676#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15
677#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16
678#define CLK_MOUT_SCLK_DSIM0 17
679#define CLK_MOUT_SCLK_DECON_TV_ECLK 18
680#define CLK_MOUT_SCLK_DECON_VCLK 19
681#define CLK_MOUT_SCLK_DECON_ECLK 20
682#define CLK_MOUT_SCLK_DSIM1_B_DISP 21
683#define CLK_MOUT_SCLK_DSIM1_A_DISP 22
684#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23
685#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24
686#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25
687
688#define CLK_DIV_SCLK_DSIM1_DISP 30
689#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31
690#define CLK_DIV_SCLK_DSIM0_DISP 32
691#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33
692#define CLK_DIV_SCLK_DECON_VCLK_DISP 34
693#define CLK_DIV_SCLK_DECON_ECLK_DISP 35
694#define CLK_DIV_PCLK_DISP 36
695
696#define CLK_ACLK_DECON_TV 40
697#define CLK_ACLK_DECON 41
698#define CLK_ACLK_SMMU_TV1X 42
699#define CLK_ACLK_SMMU_TV0X 43
700#define CLK_ACLK_SMMU_DECON1X 44
701#define CLK_ACLK_SMMU_DECON0X 45
702#define CLK_ACLK_BTS_DECON_TV_M3 46
703#define CLK_ACLK_BTS_DECON_TV_M2 47
704#define CLK_ACLK_BTS_DECON_TV_M1 48
705#define CLK_ACLK_BTS_DECON_TV_M0 49
706#define CLK_ACLK_BTS_DECON_NM4 50
707#define CLK_ACLK_BTS_DECON_NM3 51
708#define CLK_ACLK_BTS_DECON_NM2 52
709#define CLK_ACLK_BTS_DECON_NM1 53
710#define CLK_ACLK_BTS_DECON_NM0 54
711#define CLK_ACLK_AHB2APB_DISPSFR2P 55
712#define CLK_ACLK_AHB2APB_DISPSFR1P 56
713#define CLK_ACLK_AHB2APB_DISPSFR0P 57
714#define CLK_ACLK_AHB_DISPH 58
715#define CLK_ACLK_XIU_TV1X 59
716#define CLK_ACLK_XIU_TV0X 60
717#define CLK_ACLK_XIU_DECON1X 61
718#define CLK_ACLK_XIU_DECON0X 62
719#define CLK_ACLK_XIU_DISP1X 63
720#define CLK_ACLK_XIU_DISPNP_100 64
721#define CLK_ACLK_DISP1ND_333 65
722#define CLK_ACLK_DISP0ND_333 66
723#define CLK_PCLK_SMMU_TV1X 67
724#define CLK_PCLK_SMMU_TV0X 68
725#define CLK_PCLK_SMMU_DECON1X 69
726#define CLK_PCLK_SMMU_DECON0X 70
727#define CLK_PCLK_BTS_DECON_TV_M3 71
728#define CLK_PCLK_BTS_DECON_TV_M2 72
729#define CLK_PCLK_BTS_DECON_TV_M1 73
730#define CLK_PCLK_BTS_DECON_TV_M0 74
731#define CLK_PCLK_BTS_DECONM4 75
732#define CLK_PCLK_BTS_DECONM3 76
733#define CLK_PCLK_BTS_DECONM2 77
734#define CLK_PCLK_BTS_DECONM1 78
735#define CLK_PCLK_BTS_DECONM0 79
736#define CLK_PCLK_MIC1 80
737#define CLK_PCLK_PMU_DISP 81
738#define CLK_PCLK_SYSREG_DISP 82
739#define CLK_PCLK_HDMIPHY 83
740#define CLK_PCLK_HDMI 84
741#define CLK_PCLK_MIC0 85
742#define CLK_PCLK_DSIM1 86
743#define CLK_PCLK_DSIM0 87
744#define CLK_PCLK_DECON_TV 88
745#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89
746#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90
747#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91
748#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92
749#define CLK_SCLK_DSIM1 93
750#define CLK_SCLK_DECON_TV_VCLK 94
751#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95
752#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96
753#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97
754#define CLK_PHYCLK_HDMI_PIXEL 98
755#define CLK_SCLK_RGB_VCLK_TO_SMIES 99
756#define CLK_SCLK_FREQ_DET_DISP_PLL 100
757#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101
758#define CLK_SCLK_RGB_VCLK_TO_MIC0 102
759#define CLK_SCLK_DSD 103
760#define CLK_SCLK_HDMI_SPDIF 104
761#define CLK_SCLK_DSIM0 105
762#define CLK_SCLK_DECON_TV_ECLK 106
763#define CLK_SCLK_DECON_VCLK 107
764#define CLK_SCLK_DECON_ECLK 108
765#define CLK_SCLK_RGB_VCLK 109
766#define CLK_SCLK_RGB_TV_VCLK 110
767
768#define DISP_NR_CLK 111
769
770/* CMU_AUD */
771#define CLK_MOUT_AUD_PLL_USER 1
772#define CLK_MOUT_SCLK_AUD_PCM 2
773#define CLK_MOUT_SCLK_AUD_I2S 3
774
775#define CLK_DIV_ATCLK_AUD 4
776#define CLK_DIV_PCLK_DBG_AUD 5
777#define CLK_DIV_ACLK_AUD 6
778#define CLK_DIV_AUD_CA5 7
779#define CLK_DIV_SCLK_AUD_SLIMBUS 8
780#define CLK_DIV_SCLK_AUD_UART 9
781#define CLK_DIV_SCLK_AUD_PCM 10
782#define CLK_DIV_SCLK_AUD_I2S 11
783
784#define CLK_ACLK_INTR_CTRL 12
785#define CLK_ACLK_AXIDS2_LPASSP 13
786#define CLK_ACLK_AXIDS1_LPASSP 14
787#define CLK_ACLK_AXI2APB1_LPASSP 15
788#define CLK_ACLK_AXI2APH_LPASSP 16
789#define CLK_ACLK_SMMU_LPASSX 17
790#define CLK_ACLK_AXIDS0_LPASSP 18
791#define CLK_ACLK_AXI2APB0_LPASSP 19
792#define CLK_ACLK_XIU_LPASSX 20
793#define CLK_ACLK_AUDNP_133 21
794#define CLK_ACLK_AUDND_133 22
795#define CLK_ACLK_SRAMC 23
796#define CLK_ACLK_DMAC 24
797#define CLK_PCLK_WDT1 25
798#define CLK_PCLK_WDT0 26
799#define CLK_PCLK_SFR1 27
800#define CLK_PCLK_SMMU_LPASSX 28
801#define CLK_PCLK_GPIO_AUD 29
802#define CLK_PCLK_PMU_AUD 30
803#define CLK_PCLK_SYSREG_AUD 31
804#define CLK_PCLK_AUD_SLIMBUS 32
805#define CLK_PCLK_AUD_UART 33
806#define CLK_PCLK_AUD_PCM 34
807#define CLK_PCLK_AUD_I2S 35
808#define CLK_PCLK_TIMER 36
809#define CLK_PCLK_SFR0_CTRL 37
810#define CLK_ATCLK_AUD 38
811#define CLK_PCLK_DBG_AUD 39
812#define CLK_SCLK_AUD_CA5 40
813#define CLK_SCLK_JTAG_TCK 41
814#define CLK_SCLK_SLIMBUS_CLKIN 42
815#define CLK_SCLK_AUD_SLIMBUS 43
816#define CLK_SCLK_AUD_UART 44
817#define CLK_SCLK_AUD_PCM 45
818#define CLK_SCLK_I2S_BCLK 46
819#define CLK_SCLK_AUD_I2S 47
820
821#define AUD_NR_CLK 48
822
823/* CMU_BUS{0|1|2} */
824#define CLK_DIV_PCLK_BUS_133 1
825
826#define CLK_ACLK_AHB2APB_BUSP 2
827#define CLK_ACLK_BUSNP_133 3
828#define CLK_ACLK_BUSND_400 4
829#define CLK_PCLK_BUSSRVND_133 5
830#define CLK_PCLK_PMU_BUS 6
831#define CLK_PCLK_SYSREG_BUS 7
832
833#define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */
834#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */
835#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */
836
837#define BUSx_NR_CLK 11
838
839/* CMU_G3D */
840#define CLK_FOUT_G3D_PLL 1
841
842#define CLK_MOUT_ACLK_G3D_400 2
843#define CLK_MOUT_G3D_PLL 3
844
845#define CLK_DIV_SCLK_HPM_G3D 4
846#define CLK_DIV_PCLK_G3D 5
847#define CLK_DIV_ACLK_G3D 6
848#define CLK_ACLK_BTS_G3D1 7
849#define CLK_ACLK_BTS_G3D0 8
850#define CLK_ACLK_ASYNCAPBS_G3D 9
851#define CLK_ACLK_ASYNCAPBM_G3D 10
852#define CLK_ACLK_AHB2APB_G3DP 11
853#define CLK_ACLK_G3DNP_150 12
854#define CLK_ACLK_G3DND_600 13
855#define CLK_ACLK_G3D 14
856#define CLK_PCLK_BTS_G3D1 15
857#define CLK_PCLK_BTS_G3D0 16
858#define CLK_PCLK_PMU_G3D 17
859#define CLK_PCLK_SYSREG_G3D 18
860#define CLK_SCLK_HPM_G3D 19
861
862#define G3D_NR_CLK 20
863
864/* CMU_GSCL */
865#define CLK_MOUT_ACLK_GSCL_111_USER 1
866#define CLK_MOUT_ACLK_GSCL_333_USER 2
867
868#define CLK_ACLK_BTS_GSCL2 3
869#define CLK_ACLK_BTS_GSCL1 4
870#define CLK_ACLK_BTS_GSCL0 5
871#define CLK_ACLK_AHB2APB_GSCLP 6
872#define CLK_ACLK_XIU_GSCLX 7
873#define CLK_ACLK_GSCLNP_111 8
874#define CLK_ACLK_GSCLRTND_333 9
875#define CLK_ACLK_GSCLBEND_333 10
876#define CLK_ACLK_GSD 11
877#define CLK_ACLK_GSCL2 12
878#define CLK_ACLK_GSCL1 13
879#define CLK_ACLK_GSCL0 14
880#define CLK_ACLK_SMMU_GSCL0 15
881#define CLK_ACLK_SMMU_GSCL1 16
882#define CLK_ACLK_SMMU_GSCL2 17
883#define CLK_PCLK_BTS_GSCL2 18
884#define CLK_PCLK_BTS_GSCL1 19
885#define CLK_PCLK_BTS_GSCL0 20
886#define CLK_PCLK_PMU_GSCL 21
887#define CLK_PCLK_SYSREG_GSCL 22
888#define CLK_PCLK_GSCL2 23
889#define CLK_PCLK_GSCL1 24
890#define CLK_PCLK_GSCL0 25
891#define CLK_PCLK_SMMU_GSCL0 26
892#define CLK_PCLK_SMMU_GSCL1 27
893#define CLK_PCLK_SMMU_GSCL2 28
894
895#define GSCL_NR_CLK 29
896
897/* CMU_APOLLO */
898#define CLK_FOUT_APOLLO_PLL 1
899
900#define CLK_MOUT_APOLLO_PLL 2
901#define CLK_MOUT_BUS_PLL_APOLLO_USER 3
902#define CLK_MOUT_APOLLO 4
903
904#define CLK_DIV_CNTCLK_APOLLO 5
905#define CLK_DIV_PCLK_DBG_APOLLO 6
906#define CLK_DIV_ATCLK_APOLLO 7
907#define CLK_DIV_PCLK_APOLLO 8
908#define CLK_DIV_ACLK_APOLLO 9
909#define CLK_DIV_APOLLO2 10
910#define CLK_DIV_APOLLO1 11
911#define CLK_DIV_SCLK_HPM_APOLLO 12
912#define CLK_DIV_APOLLO_PLL 13
913
914#define CLK_ACLK_ATBDS_APOLLO_3 14
915#define CLK_ACLK_ATBDS_APOLLO_2 15
916#define CLK_ACLK_ATBDS_APOLLO_1 16
917#define CLK_ACLK_ATBDS_APOLLO_0 17
918#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18
919#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19
920#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20
921#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21
922#define CLK_ACLK_ASYNCACES_APOLLO_CCI 22
923#define CLK_ACLK_AHB2APB_APOLLOP 23
924#define CLK_ACLK_APOLLONP_200 24
925#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25
926#define CLK_PCLK_PMU_APOLLO 26
927#define CLK_PCLK_SYSREG_APOLLO 27
928#define CLK_CNTCLK_APOLLO 28
929#define CLK_SCLK_HPM_APOLLO 29
930#define CLK_SCLK_APOLLO 30
931
932#define APOLLO_NR_CLK 31
933
934/* CMU_ATLAS */
935#define CLK_FOUT_ATLAS_PLL 1
936
937#define CLK_MOUT_ATLAS_PLL 2
938#define CLK_MOUT_BUS_PLL_ATLAS_USER 3
939#define CLK_MOUT_ATLAS 4
940
941#define CLK_DIV_CNTCLK_ATLAS 5
942#define CLK_DIV_PCLK_DBG_ATLAS 6
943#define CLK_DIV_ATCLK_ATLASO 7
944#define CLK_DIV_PCLK_ATLAS 8
945#define CLK_DIV_ACLK_ATLAS 9
946#define CLK_DIV_ATLAS2 10
947#define CLK_DIV_ATLAS1 11
948#define CLK_DIV_SCLK_HPM_ATLAS 12
949#define CLK_DIV_ATLAS_PLL 13
950
951#define CLK_ACLK_ATB_AUD_CSSYS 14
952#define CLK_ACLK_ATB_APOLLO3_CSSYS 15
953#define CLK_ACLK_ATB_APOLLO2_CSSYS 16
954#define CLK_ACLK_ATB_APOLLO1_CSSYS 17
955#define CLK_ACLK_ATB_APOLLO0_CSSYS 18
956#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19
957#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20
958#define CLK_ACLK_ASYNCACES_ATLAS_CCI 21
959#define CLK_ACLK_AHB2APB_ATLASP 22
960#define CLK_ACLK_ATLASNP_200 23
961#define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24
962#define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25
963#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26
964#define CLK_PCLK_PMU_ATLAS 27
965#define CLK_PCLK_SYSREG_ATLAS 28
966#define CLK_PCLK_SECJTAG 29
967#define CLK_CNTCLK_ATLAS 30
968#define CLK_SCLK_FREQ_DET_ATLAS_PLL 31
969#define CLK_SCLK_HPM_ATLAS 32
970#define CLK_TRACECLK 33
971#define CLK_CTMCLK 34
972#define CLK_HCLK_CSSYS 35
973#define CLK_PCLK_DBG_CSSYS 36
974#define CLK_PCLK_DBG 37
975#define CLK_ATCLK 38
976#define CLK_SCLK_ATLAS 39
977
978#define ATLAS_NR_CLK 40
979
980/* CMU_MSCL */
981#define CLK_MOUT_SCLK_JPEG_USER 1
982#define CLK_MOUT_ACLK_MSCL_400_USER 2
983#define CLK_MOUT_SCLK_JPEG 3
984
985#define CLK_DIV_PCLK_MSCL 4
986
987#define CLK_ACLK_BTS_JPEG 5
988#define CLK_ACLK_BTS_M2MSCALER1 6
989#define CLK_ACLK_BTS_M2MSCALER0 7
990#define CLK_ACLK_AHB2APB_MSCL0P 8
991#define CLK_ACLK_XIU_MSCLX 9
992#define CLK_ACLK_MSCLNP_100 10
993#define CLK_ACLK_MSCLND_400 11
994#define CLK_ACLK_JPEG 12
995#define CLK_ACLK_M2MSCALER1 13
996#define CLK_ACLK_M2MSCALER0 14
997#define CLK_ACLK_SMMU_M2MSCALER0 15
998#define CLK_ACLK_SMMU_M2MSCALER1 16
999#define CLK_ACLK_SMMU_JPEG 17
1000#define CLK_PCLK_BTS_JPEG 18
1001#define CLK_PCLK_BTS_M2MSCALER1 19
1002#define CLK_PCLK_BTS_M2MSCALER0 20
1003#define CLK_PCLK_PMU_MSCL 21
1004#define CLK_PCLK_SYSREG_MSCL 22
1005#define CLK_PCLK_JPEG 23
1006#define CLK_PCLK_M2MSCALER1 24
1007#define CLK_PCLK_M2MSCALER0 25
1008#define CLK_PCLK_SMMU_M2MSCALER0 26
1009#define CLK_PCLK_SMMU_M2MSCALER1 27
1010#define CLK_PCLK_SMMU_JPEG 28
1011#define CLK_SCLK_JPEG 29
1012
1013#define MSCL_NR_CLK 30
1014
1015/* CMU_MFC */
1016#define CLK_MOUT_ACLK_MFC_400_USER 1
1017
1018#define CLK_DIV_PCLK_MFC 2
1019
1020#define CLK_ACLK_BTS_MFC_1 3
1021#define CLK_ACLK_BTS_MFC_0 4
1022#define CLK_ACLK_AHB2APB_MFCP 5
1023#define CLK_ACLK_XIU_MFCX 6
1024#define CLK_ACLK_MFCNP_100 7
1025#define CLK_ACLK_MFCND_400 8
1026#define CLK_ACLK_MFC 9
1027#define CLK_ACLK_SMMU_MFC_1 10
1028#define CLK_ACLK_SMMU_MFC_0 11
1029#define CLK_PCLK_BTS_MFC_1 12
1030#define CLK_PCLK_BTS_MFC_0 13
1031#define CLK_PCLK_PMU_MFC 14
1032#define CLK_PCLK_SYSREG_MFC 15
1033#define CLK_PCLK_MFC 16
1034#define CLK_PCLK_SMMU_MFC_1 17
1035#define CLK_PCLK_SMMU_MFC_0 18
1036
1037#define MFC_NR_CLK 19
1038
1039/* CMU_HEVC */
1040#define CLK_MOUT_ACLK_HEVC_400_USER 1
1041
1042#define CLK_DIV_PCLK_HEVC 2
1043
1044#define CLK_ACLK_BTS_HEVC_1 3
1045#define CLK_ACLK_BTS_HEVC_0 4
1046#define CLK_ACLK_AHB2APB_HEVCP 5
1047#define CLK_ACLK_XIU_HEVCX 6
1048#define CLK_ACLK_HEVCNP_100 7
1049#define CLK_ACLK_HEVCND_400 8
1050#define CLK_ACLK_HEVC 9
1051#define CLK_ACLK_SMMU_HEVC_1 10
1052#define CLK_ACLK_SMMU_HEVC_0 11
1053#define CLK_PCLK_BTS_HEVC_1 12
1054#define CLK_PCLK_BTS_HEVC_0 13
1055#define CLK_PCLK_PMU_HEVC 14
1056#define CLK_PCLK_SYSREG_HEVC 15
1057#define CLK_PCLK_HEVC 16
1058#define CLK_PCLK_SMMU_HEVC_1 17
1059#define CLK_PCLK_SMMU_HEVC_0 18
1060
1061#define HEVC_NR_CLK 19
1062
1063/* CMU_ISP */
1064#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1
1065#define CLK_MOUT_ACLK_ISP_400_USER 2
1066
1067#define CLK_DIV_PCLK_ISP_DIS 3
1068#define CLK_DIV_PCLK_ISP 4
1069#define CLK_DIV_ACLK_ISP_D_200 5
1070#define CLK_DIV_ACLK_ISP_C_200 6
1071
1072#define CLK_ACLK_ISP_D_GLUE 7
1073#define CLK_ACLK_SCALERP 8
1074#define CLK_ACLK_3DNR 9
1075#define CLK_ACLK_DIS 10
1076#define CLK_ACLK_SCALERC 11
1077#define CLK_ACLK_DRC 12
1078#define CLK_ACLK_ISP 13
1079#define CLK_ACLK_AXIUS_SCALERP 14
1080#define CLK_ACLK_AXIUS_SCALERC 15
1081#define CLK_ACLK_AXIUS_DRC 16
1082#define CLK_ACLK_ASYNCAHBM_ISP2P 17
1083#define CLK_ACLK_ASYNCAHBM_ISP1P 18
1084#define CLK_ACLK_ASYNCAXIS_DIS1 19
1085#define CLK_ACLK_ASYNCAXIS_DIS0 20
1086#define CLK_ACLK_ASYNCAXIM_DIS1 21
1087#define CLK_ACLK_ASYNCAXIM_DIS0 22
1088#define CLK_ACLK_ASYNCAXIM_ISP2P 23
1089#define CLK_ACLK_ASYNCAXIM_ISP1P 24
1090#define CLK_ACLK_AHB2APB_ISP2P 25
1091#define CLK_ACLK_AHB2APB_ISP1P 26
1092#define CLK_ACLK_AXI2APB_ISP2P 27
1093#define CLK_ACLK_AXI2APB_ISP1P 28
1094#define CLK_ACLK_XIU_ISPEX1 29
1095#define CLK_ACLK_XIU_ISPEX0 30
1096#define CLK_ACLK_ISPND_400 31
1097#define CLK_ACLK_SMMU_SCALERP 32
1098#define CLK_ACLK_SMMU_3DNR 33
1099#define CLK_ACLK_SMMU_DIS1 34
1100#define CLK_ACLK_SMMU_DIS0 35
1101#define CLK_ACLK_SMMU_SCALERC 36
1102#define CLK_ACLK_SMMU_DRC 37
1103#define CLK_ACLK_SMMU_ISP 38
1104#define CLK_ACLK_BTS_SCALERP 39
1105#define CLK_ACLK_BTS_3DR 40
1106#define CLK_ACLK_BTS_DIS1 41
1107#define CLK_ACLK_BTS_DIS0 42
1108#define CLK_ACLK_BTS_SCALERC 43
1109#define CLK_ACLK_BTS_DRC 44
1110#define CLK_ACLK_BTS_ISP 45
1111#define CLK_PCLK_SMMU_SCALERP 46
1112#define CLK_PCLK_SMMU_3DNR 47
1113#define CLK_PCLK_SMMU_DIS1 48
1114#define CLK_PCLK_SMMU_DIS0 49
1115#define CLK_PCLK_SMMU_SCALERC 50
1116#define CLK_PCLK_SMMU_DRC 51
1117#define CLK_PCLK_SMMU_ISP 52
1118#define CLK_PCLK_BTS_SCALERP 53
1119#define CLK_PCLK_BTS_3DNR 54
1120#define CLK_PCLK_BTS_DIS1 55
1121#define CLK_PCLK_BTS_DIS0 56
1122#define CLK_PCLK_BTS_SCALERC 57
1123#define CLK_PCLK_BTS_DRC 58
1124#define CLK_PCLK_BTS_ISP 59
1125#define CLK_PCLK_ASYNCAXI_DIS1 60
1126#define CLK_PCLK_ASYNCAXI_DIS0 61
1127#define CLK_PCLK_PMU_ISP 62
1128#define CLK_PCLK_SYSREG_ISP 63
1129#define CLK_PCLK_CMU_ISP_LOCAL 64
1130#define CLK_PCLK_SCALERP 65
1131#define CLK_PCLK_3DNR 66
1132#define CLK_PCLK_DIS_CORE 67
1133#define CLK_PCLK_DIS 68
1134#define CLK_PCLK_SCALERC 69
1135#define CLK_PCLK_DRC 70
1136#define CLK_PCLK_ISP 71
1137#define CLK_SCLK_PIXELASYNCS_DIS 72
1138#define CLK_SCLK_PIXELASYNCM_DIS 73
1139#define CLK_SCLK_PIXELASYNCS_SCALERP 74
1140#define CLK_SCLK_PIXELASYNCM_ISPD 75
1141#define CLK_SCLK_PIXELASYNCS_ISPC 76
1142#define CLK_SCLK_PIXELASYNCM_ISPC 77
1143
1144#define ISP_NR_CLK 78
1145
1146/* CMU_CAM0 */
1147#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1
1148#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2
1149
1150#define CLK_MOUT_ACLK_CAM0_333_USER 3
1151#define CLK_MOUT_ACLK_CAM0_400_USER 4
1152#define CLK_MOUT_ACLK_CAM0_552_USER 5
1153#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6
1154#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7
1155#define CLK_MOUT_ACLK_LITE_D_B 8
1156#define CLK_MOUT_ACLK_LITE_D_A 9
1157#define CLK_MOUT_ACLK_LITE_B_B 10
1158#define CLK_MOUT_ACLK_LITE_B_A 11
1159#define CLK_MOUT_ACLK_LITE_A_B 12
1160#define CLK_MOUT_ACLK_LITE_A_A 13
1161#define CLK_MOUT_ACLK_CAM0_400 14
1162#define CLK_MOUT_ACLK_CSIS1_B 15
1163#define CLK_MOUT_ACLK_CSIS1_A 16
1164#define CLK_MOUT_ACLK_CSIS0_B 17
1165#define CLK_MOUT_ACLK_CSIS0_A 18
1166#define CLK_MOUT_ACLK_3AA1_B 19
1167#define CLK_MOUT_ACLK_3AA1_A 20
1168#define CLK_MOUT_ACLK_3AA0_B 21
1169#define CLK_MOUT_ACLK_3AA0_A 22
1170#define CLK_MOUT_SCLK_LITE_FREECNT_C 23
1171#define CLK_MOUT_SCLK_LITE_FREECNT_B 24
1172#define CLK_MOUT_SCLK_LITE_FREECNT_A 25
1173#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26
1174#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27
1175#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28
1176#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29
1177
1178#define CLK_DIV_PCLK_CAM0_50 30
1179#define CLK_DIV_ACLK_CAM0_200 31
1180#define CLK_DIV_ACLK_CAM0_BUS_400 32
1181#define CLK_DIV_PCLK_LITE_D 33
1182#define CLK_DIV_ACLK_LITE_D 34
1183#define CLK_DIV_PCLK_LITE_B 35
1184#define CLK_DIV_ACLK_LITE_B 36
1185#define CLK_DIV_PCLK_LITE_A 37
1186#define CLK_DIV_ACLK_LITE_A 38
1187#define CLK_DIV_ACLK_CSIS1 39
1188#define CLK_DIV_ACLK_CSIS0 40
1189#define CLK_DIV_PCLK_3AA1 41
1190#define CLK_DIV_ACLK_3AA1 42
1191#define CLK_DIV_PCLK_3AA0 43
1192#define CLK_DIV_ACLK_3AA0 44
1193#define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45
1194#define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46
1195#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47
1196
1197#define CLK_ACLK_CSIS1 50
1198#define CLK_ACLK_CSIS0 51
1199#define CLK_ACLK_3AA1 52
1200#define CLK_ACLK_3AA0 53
1201#define CLK_ACLK_LITE_D 54
1202#define CLK_ACLK_LITE_B 55
1203#define CLK_ACLK_LITE_A 56
1204#define CLK_ACLK_AHBSYNCDN 57
1205#define CLK_ACLK_AXIUS_LITE_D 58
1206#define CLK_ACLK_AXIUS_LITE_B 59
1207#define CLK_ACLK_AXIUS_LITE_A 60
1208#define CLK_ACLK_ASYNCAPBM_3AA1 61
1209#define CLK_ACLK_ASYNCAPBS_3AA1 62
1210#define CLK_ACLK_ASYNCAPBM_3AA0 63
1211#define CLK_ACLK_ASYNCAPBS_3AA0 64
1212#define CLK_ACLK_ASYNCAPBM_LITE_D 65
1213#define CLK_ACLK_ASYNCAPBS_LITE_D 66
1214#define CLK_ACLK_ASYNCAPBM_LITE_B 67
1215#define CLK_ACLK_ASYNCAPBS_LITE_B 68
1216#define CLK_ACLK_ASYNCAPBM_LITE_A 69
1217#define CLK_ACLK_ASYNCAPBS_LITE_A 70
1218#define CLK_ACLK_ASYNCAXIM_ISP0P 71
1219#define CLK_ACLK_ASYNCAXIM_3AA1 72
1220#define CLK_ACLK_ASYNCAXIS_3AA1 73
1221#define CLK_ACLK_ASYNCAXIM_3AA0 74
1222#define CLK_ACLK_ASYNCAXIS_3AA0 75
1223#define CLK_ACLK_ASYNCAXIM_LITE_D 76
1224#define CLK_ACLK_ASYNCAXIS_LITE_D 77
1225#define CLK_ACLK_ASYNCAXIM_LITE_B 78
1226#define CLK_ACLK_ASYNCAXIS_LITE_B 79
1227#define CLK_ACLK_ASYNCAXIM_LITE_A 80
1228#define CLK_ACLK_ASYNCAXIS_LITE_A 81
1229#define CLK_ACLK_AHB2APB_ISPSFRP 82
1230#define CLK_ACLK_AXI2APB_ISP0P 83
1231#define CLK_ACLK_AXI2AHB_ISP0P 84
1232#define CLK_ACLK_XIU_IS0X 85
1233#define CLK_ACLK_XIU_ISP0EX 86
1234#define CLK_ACLK_CAM0NP_276 87
1235#define CLK_ACLK_CAM0ND_400 88
1236#define CLK_ACLK_SMMU_3AA1 89
1237#define CLK_ACLK_SMMU_3AA0 90
1238#define CLK_ACLK_SMMU_LITE_D 91
1239#define CLK_ACLK_SMMU_LITE_B 92
1240#define CLK_ACLK_SMMU_LITE_A 93
1241#define CLK_ACLK_BTS_3AA1 94
1242#define CLK_ACLK_BTS_3AA0 95
1243#define CLK_ACLK_BTS_LITE_D 96
1244#define CLK_ACLK_BTS_LITE_B 97
1245#define CLK_ACLK_BTS_LITE_A 98
1246#define CLK_PCLK_SMMU_3AA1 99
1247#define CLK_PCLK_SMMU_3AA0 100
1248#define CLK_PCLK_SMMU_LITE_D 101
1249#define CLK_PCLK_SMMU_LITE_B 102
1250#define CLK_PCLK_SMMU_LITE_A 103
1251#define CLK_PCLK_BTS_3AA1 104
1252#define CLK_PCLK_BTS_3AA0 105
1253#define CLK_PCLK_BTS_LITE_D 106
1254#define CLK_PCLK_BTS_LITE_B 107
1255#define CLK_PCLK_BTS_LITE_A 108
1256#define CLK_PCLK_ASYNCAXI_CAM1 109
1257#define CLK_PCLK_ASYNCAXI_3AA1 110
1258#define CLK_PCLK_ASYNCAXI_3AA0 111
1259#define CLK_PCLK_ASYNCAXI_LITE_D 112
1260#define CLK_PCLK_ASYNCAXI_LITE_B 113
1261#define CLK_PCLK_ASYNCAXI_LITE_A 114
1262#define CLK_PCLK_PMU_CAM0 115
1263#define CLK_PCLK_SYSREG_CAM0 116
1264#define CLK_PCLK_CMU_CAM0_LOCAL 117
1265#define CLK_PCLK_CSIS1 118
1266#define CLK_PCLK_CSIS0 119
1267#define CLK_PCLK_3AA1 120
1268#define CLK_PCLK_3AA0 121
1269#define CLK_PCLK_LITE_D 122
1270#define CLK_PCLK_LITE_B 123
1271#define CLK_PCLK_LITE_A 124
1272#define CLK_PHYCLK_RXBYTECLKHS0_S4 125
1273#define CLK_PHYCLK_RXBYTECLKHS0_S2A 126
1274#define CLK_SCLK_LITE_FREECNT 127
1275#define CLK_SCLK_PIXELASYNCM_3AA1 128
1276#define CLK_SCLK_PIXELASYNCM_3AA0 129
1277#define CLK_SCLK_PIXELASYNCS_3AA0 130
1278#define CLK_SCLK_PIXELASYNCM_LITE_C 131
1279#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132
1280#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133
1281
1282#define CAM0_NR_CLK 134
1283
1284/* CMU_CAM1 */
1285#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1
1286
1287#define CLK_MOUT_SCLK_ISP_UART_USER 2
1288#define CLK_MOUT_SCLK_ISP_SPI1_USER 3
1289#define CLK_MOUT_SCLK_ISP_SPI0_USER 4
1290#define CLK_MOUT_ACLK_CAM1_333_USER 5
1291#define CLK_MOUT_ACLK_CAM1_400_USER 6
1292#define CLK_MOUT_ACLK_CAM1_552_USER 7
1293#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8
1294#define CLK_MOUT_ACLK_CSIS2_B 9
1295#define CLK_MOUT_ACLK_CSIS2_A 10
1296#define CLK_MOUT_ACLK_FD_B 11
1297#define CLK_MOUT_ACLK_FD_A 12
1298#define CLK_MOUT_ACLK_LITE_C_B 13
1299#define CLK_MOUT_ACLK_LITE_C_A 14
1300
1301#define CLK_DIV_SCLK_ISP_WPWM 15
1302#define CLK_DIV_PCLK_CAM1_83 16
1303#define CLK_DIV_PCLK_CAM1_166 17
1304#define CLK_DIV_PCLK_DBG_CAM1 18
1305#define CLK_DIV_ATCLK_CAM1 19
1306#define CLK_DIV_ACLK_CSIS2 20
1307#define CLK_DIV_PCLK_FD 21
1308#define CLK_DIV_ACLK_FD 22
1309#define CLK_DIV_PCLK_LITE_C 23
1310#define CLK_DIV_ACLK_LITE_C 24
1311
1312#define CLK_ACLK_ISP_GIC 25
1313#define CLK_ACLK_FD 26
1314#define CLK_ACLK_LITE_C 27
1315#define CLK_ACLK_CSIS2 28
1316#define CLK_ACLK_ASYNCAPBM_FD 29
1317#define CLK_ACLK_ASYNCAPBS_FD 30
1318#define CLK_ACLK_ASYNCAPBM_LITE_C 31
1319#define CLK_ACLK_ASYNCAPBS_LITE_C 32
1320#define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33
1321#define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34
1322#define CLK_ACLK_ASYNCAXIM_CA5 35
1323#define CLK_ACLK_ASYNCAXIS_CA5 36
1324#define CLK_ACLK_ASYNCAXIS_ISPX2 37
1325#define CLK_ACLK_ASYNCAXIS_ISPX1 38
1326#define CLK_ACLK_ASYNCAXIS_ISPX0 39
1327#define CLK_ACLK_ASYNCAXIM_ISPEX 40
1328#define CLK_ACLK_ASYNCAXIM_ISP3P 41
1329#define CLK_ACLK_ASYNCAXIS_ISP3P 42
1330#define CLK_ACLK_ASYNCAXIM_FD 43
1331#define CLK_ACLK_ASYNCAXIS_FD 44
1332#define CLK_ACLK_ASYNCAXIM_LITE_C 45
1333#define CLK_ACLK_ASYNCAXIS_LITE_C 46
1334#define CLK_ACLK_AHB2APB_ISP5P 47
1335#define CLK_ACLK_AHB2APB_ISP3P 48
1336#define CLK_ACLK_AXI2APB_ISP3P 49
1337#define CLK_ACLK_AHB_SFRISP2H 50
1338#define CLK_ACLK_AXI_ISP_HX_R 51
1339#define CLK_ACLK_AXI_ISP_CX_R 52
1340#define CLK_ACLK_AXI_ISP_HX 53
1341#define CLK_ACLK_AXI_ISP_CX 54
1342#define CLK_ACLK_XIU_ISPX 55
1343#define CLK_ACLK_XIU_ISPEX 56
1344#define CLK_ACLK_CAM1NP_333 57
1345#define CLK_ACLK_CAM1ND_400 58
1346#define CLK_ACLK_SMMU_ISPCPU 59
1347#define CLK_ACLK_SMMU_FD 60
1348#define CLK_ACLK_SMMU_LITE_C 61
1349#define CLK_ACLK_BTS_ISP3P 62
1350#define CLK_ACLK_BTS_FD 63
1351#define CLK_ACLK_BTS_LITE_C 64
1352#define CLK_ACLK_AHBDN_SFRISP2H 65
1353#define CLK_ACLK_AHBDN_ISP5P 66
1354#define CLK_ACLK_AXIUS_ISP3P 67
1355#define CLK_ACLK_AXIUS_FD 68
1356#define CLK_ACLK_AXIUS_LITE_C 69
1357#define CLK_PCLK_SMMU_ISPCPU 70
1358#define CLK_PCLK_SMMU_FD 71
1359#define CLK_PCLK_SMMU_LITE_C 72
1360#define CLK_PCLK_BTS_ISP3P 73
1361#define CLK_PCLK_BTS_FD 74
1362#define CLK_PCLK_BTS_LITE_C 75
1363#define CLK_PCLK_ASYNCAXIM_CA5 76
1364#define CLK_PCLK_ASYNCAXIM_ISPEX 77
1365#define CLK_PCLK_ASYNCAXIM_ISP3P 78
1366#define CLK_PCLK_ASYNCAXIM_FD 79
1367#define CLK_PCLK_ASYNCAXIM_LITE_C 80
1368#define CLK_PCLK_PMU_CAM1 81
1369#define CLK_PCLK_SYSREG_CAM1 82
1370#define CLK_PCLK_CMU_CAM1_LOCAL 83
1371#define CLK_PCLK_ISP_MCTADC 84
1372#define CLK_PCLK_ISP_WDT 85
1373#define CLK_PCLK_ISP_PWM 86
1374#define CLK_PCLK_ISP_UART 87
1375#define CLK_PCLK_ISP_MCUCTL 88
1376#define CLK_PCLK_ISP_SPI1 89
1377#define CLK_PCLK_ISP_SPI0 90
1378#define CLK_PCLK_ISP_I2C2 91
1379#define CLK_PCLK_ISP_I2C1 92
1380#define CLK_PCLK_ISP_I2C0 93
1381#define CLK_PCLK_ISP_MPWM 94
1382#define CLK_PCLK_FD 95
1383#define CLK_PCLK_LITE_C 96
1384#define CLK_PCLK_CSIS2 97
1385#define CLK_SCLK_ISP_I2C2 98
1386#define CLK_SCLK_ISP_I2C1 99
1387#define CLK_SCLK_ISP_I2C0 100
1388#define CLK_SCLK_ISP_PWM 101
1389#define CLK_PHYCLK_RXBYTECLKHS0_S2B 102
1390#define CLK_SCLK_LITE_C_FREECNT 103
1391#define CLK_SCLK_PIXELASYNCM_FD 104
1392#define CLK_SCLK_ISP_MCTADC 105
1393#define CLK_SCLK_ISP_UART 106
1394#define CLK_SCLK_ISP_SPI1 107
1395#define CLK_SCLK_ISP_SPI0 108
1396#define CLK_SCLK_ISP_MPWM 109
1397#define CLK_PCLK_DBG_ISP 110
1398#define CLK_ATCLK_ISP 111
1399#define CLK_SCLK_ISP_CA5 112
1400
1401#define CAM1_NR_CLK 113
1402
1403#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
index 04fb29ae30e6..ebd63fd05649 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -288,5 +288,6 @@
288#define UBI32_CORE2_CLK_SRC 278 288#define UBI32_CORE2_CLK_SRC 278
289#define UBI32_CORE1_CLK 279 289#define UBI32_CORE1_CLK 279
290#define UBI32_CORE2_CLK 280 290#define UBI32_CORE2_CLK 280
291#define EBI2_AON_CLK 281
291 292
292#endif 293#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
new file mode 100644
index 000000000000..e430f644dd6c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -0,0 +1,156 @@
1/*
2 * Copyright 2015 Linaro Limited
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
15#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
16
17#define GPLL0 0
18#define GPLL0_VOTE 1
19#define BIMC_PLL 2
20#define BIMC_PLL_VOTE 3
21#define GPLL1 4
22#define GPLL1_VOTE 5
23#define GPLL2 6
24#define GPLL2_VOTE 7
25#define PCNOC_BFDCD_CLK_SRC 8
26#define SYSTEM_NOC_BFDCD_CLK_SRC 9
27#define CAMSS_AHB_CLK_SRC 10
28#define APSS_AHB_CLK_SRC 11
29#define CSI0_CLK_SRC 12
30#define CSI1_CLK_SRC 13
31#define GFX3D_CLK_SRC 14
32#define VFE0_CLK_SRC 15
33#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
34#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
35#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
36#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
37#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
38#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
39#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
40#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
41#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
42#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
43#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
44#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
45#define BLSP1_UART1_APPS_CLK_SRC 28
46#define BLSP1_UART2_APPS_CLK_SRC 29
47#define CCI_CLK_SRC 30
48#define CAMSS_GP0_CLK_SRC 31
49#define CAMSS_GP1_CLK_SRC 32
50#define JPEG0_CLK_SRC 33
51#define MCLK0_CLK_SRC 34
52#define MCLK1_CLK_SRC 35
53#define CSI0PHYTIMER_CLK_SRC 36
54#define CSI1PHYTIMER_CLK_SRC 37
55#define CPP_CLK_SRC 38
56#define CRYPTO_CLK_SRC 39
57#define GP1_CLK_SRC 40
58#define GP2_CLK_SRC 41
59#define GP3_CLK_SRC 42
60#define BYTE0_CLK_SRC 43
61#define ESC0_CLK_SRC 44
62#define MDP_CLK_SRC 45
63#define PCLK0_CLK_SRC 46
64#define VSYNC_CLK_SRC 47
65#define PDM2_CLK_SRC 48
66#define SDCC1_APPS_CLK_SRC 49
67#define SDCC2_APPS_CLK_SRC 50
68#define APSS_TCU_CLK_SRC 51
69#define USB_HS_SYSTEM_CLK_SRC 52
70#define VCODEC0_CLK_SRC 53
71#define GCC_BLSP1_AHB_CLK 54
72#define GCC_BLSP1_SLEEP_CLK 55
73#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
74#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
75#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
76#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
77#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
78#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
79#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
80#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
81#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
82#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
83#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
84#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
85#define GCC_BLSP1_UART1_APPS_CLK 68
86#define GCC_BLSP1_UART2_APPS_CLK 69
87#define GCC_BOOT_ROM_AHB_CLK 70
88#define GCC_CAMSS_CCI_AHB_CLK 71
89#define GCC_CAMSS_CCI_CLK 72
90#define GCC_CAMSS_CSI0_AHB_CLK 73
91#define GCC_CAMSS_CSI0_CLK 74
92#define GCC_CAMSS_CSI0PHY_CLK 75
93#define GCC_CAMSS_CSI0PIX_CLK 76
94#define GCC_CAMSS_CSI0RDI_CLK 77
95#define GCC_CAMSS_CSI1_AHB_CLK 78
96#define GCC_CAMSS_CSI1_CLK 79
97#define GCC_CAMSS_CSI1PHY_CLK 80
98#define GCC_CAMSS_CSI1PIX_CLK 81
99#define GCC_CAMSS_CSI1RDI_CLK 82
100#define GCC_CAMSS_CSI_VFE0_CLK 83
101#define GCC_CAMSS_GP0_CLK 84
102#define GCC_CAMSS_GP1_CLK 85
103#define GCC_CAMSS_ISPIF_AHB_CLK 86
104#define GCC_CAMSS_JPEG0_CLK 87
105#define GCC_CAMSS_JPEG_AHB_CLK 88
106#define GCC_CAMSS_JPEG_AXI_CLK 89
107#define GCC_CAMSS_MCLK0_CLK 90
108#define GCC_CAMSS_MCLK1_CLK 91
109#define GCC_CAMSS_MICRO_AHB_CLK 92
110#define GCC_CAMSS_CSI0PHYTIMER_CLK 93
111#define GCC_CAMSS_CSI1PHYTIMER_CLK 94
112#define GCC_CAMSS_AHB_CLK 95
113#define GCC_CAMSS_TOP_AHB_CLK 96
114#define GCC_CAMSS_CPP_AHB_CLK 97
115#define GCC_CAMSS_CPP_CLK 98
116#define GCC_CAMSS_VFE0_CLK 99
117#define GCC_CAMSS_VFE_AHB_CLK 100
118#define GCC_CAMSS_VFE_AXI_CLK 101
119#define GCC_CRYPTO_AHB_CLK 102
120#define GCC_CRYPTO_AXI_CLK 103
121#define GCC_CRYPTO_CLK 104
122#define GCC_OXILI_GMEM_CLK 105
123#define GCC_GP1_CLK 106
124#define GCC_GP2_CLK 107
125#define GCC_GP3_CLK 108
126#define GCC_MDSS_AHB_CLK 109
127#define GCC_MDSS_AXI_CLK 110
128#define GCC_MDSS_BYTE0_CLK 111
129#define GCC_MDSS_ESC0_CLK 112
130#define GCC_MDSS_MDP_CLK 113
131#define GCC_MDSS_PCLK0_CLK 114
132#define GCC_MDSS_VSYNC_CLK 115
133#define GCC_MSS_CFG_AHB_CLK 116
134#define GCC_OXILI_AHB_CLK 117
135#define GCC_OXILI_GFX3D_CLK 118
136#define GCC_PDM2_CLK 119
137#define GCC_PDM_AHB_CLK 120
138#define GCC_PRNG_AHB_CLK 121
139#define GCC_SDCC1_AHB_CLK 122
140#define GCC_SDCC1_APPS_CLK 123
141#define GCC_SDCC2_AHB_CLK 124
142#define GCC_SDCC2_APPS_CLK 125
143#define GCC_GTCU_AHB_CLK 126
144#define GCC_JPEG_TBU_CLK 127
145#define GCC_MDP_TBU_CLK 128
146#define GCC_SMMU_CFG_CLK 129
147#define GCC_VENUS_TBU_CLK 130
148#define GCC_VFE_TBU_CLK 131
149#define GCC_USB2A_PHY_SLEEP_CLK 132
150#define GCC_USB_HS_AHB_CLK 133
151#define GCC_USB_HS_SYSTEM_CLK 134
152#define GCC_VENUS0_AHB_CLK 135
153#define GCC_VENUS0_AXI_CLK 136
154#define GCC_VENUS0_VCODEC0_CLK 137
155
156#endif
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index ae2eb17a1658..a2156090563f 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -297,7 +297,7 @@
297#define TEGRA124_CLK_PLL_C4 270 297#define TEGRA124_CLK_PLL_C4 270
298#define TEGRA124_CLK_PLL_DP 271 298#define TEGRA124_CLK_PLL_DP 271
299#define TEGRA124_CLK_PLL_E_MUX 272 299#define TEGRA124_CLK_PLL_E_MUX 272
300#define TEGRA124_CLK_PLLD_DSI 273 300#define TEGRA124_CLK_PLL_D_DSI_OUT 273
301/* 274 */ 301/* 274 */
302/* 275 */ 302/* 275 */
303/* 276 */ 303/* 276 */
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h
new file mode 100644
index 000000000000..3d90410f09c7
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-msm8916.h
@@ -0,0 +1,108 @@
1/*
2 * Copyright 2015 Linaro Limited
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H
15#define _DT_BINDINGS_RESET_MSM_GCC_8916_H
16
17#define GCC_BLSP1_BCR 0
18#define GCC_BLSP1_QUP1_BCR 1
19#define GCC_BLSP1_UART1_BCR 2
20#define GCC_BLSP1_QUP2_BCR 3
21#define GCC_BLSP1_UART2_BCR 4
22#define GCC_BLSP1_QUP3_BCR 5
23#define GCC_BLSP1_QUP4_BCR 6
24#define GCC_BLSP1_QUP5_BCR 7
25#define GCC_BLSP1_QUP6_BCR 8
26#define GCC_IMEM_BCR 9
27#define GCC_SMMU_BCR 10
28#define GCC_APSS_TCU_BCR 11
29#define GCC_SMMU_XPU_BCR 12
30#define GCC_PCNOC_TBU_BCR 13
31#define GCC_PRNG_BCR 14
32#define GCC_BOOT_ROM_BCR 15
33#define GCC_CRYPTO_BCR 16
34#define GCC_SEC_CTRL_BCR 17
35#define GCC_AUDIO_CORE_BCR 18
36#define GCC_ULT_AUDIO_BCR 19
37#define GCC_DEHR_BCR 20
38#define GCC_SYSTEM_NOC_BCR 21
39#define GCC_PCNOC_BCR 22
40#define GCC_TCSR_BCR 23
41#define GCC_QDSS_BCR 24
42#define GCC_DCD_BCR 25
43#define GCC_MSG_RAM_BCR 26
44#define GCC_MPM_BCR 27
45#define GCC_SPMI_BCR 28
46#define GCC_SPDM_BCR 29
47#define GCC_MM_SPDM_BCR 30
48#define GCC_BIMC_BCR 31
49#define GCC_RBCPR_BCR 32
50#define GCC_TLMM_BCR 33
51#define GCC_USB_HS_BCR 34
52#define GCC_USB2A_PHY_BCR 35
53#define GCC_SDCC1_BCR 36
54#define GCC_SDCC2_BCR 37
55#define GCC_PDM_BCR 38
56#define GCC_SNOC_BUS_TIMEOUT0_BCR 39
57#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40
58#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41
59#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42
60#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43
61#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44
62#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45
63#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46
64#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47
65#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48
66#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49
67#define GCC_MMSS_BCR 50
68#define GCC_VENUS0_BCR 51
69#define GCC_MDSS_BCR 52
70#define GCC_CAMSS_PHY0_BCR 53
71#define GCC_CAMSS_CSI0_BCR 54
72#define GCC_CAMSS_CSI0PHY_BCR 55
73#define GCC_CAMSS_CSI0RDI_BCR 56
74#define GCC_CAMSS_CSI0PIX_BCR 57
75#define GCC_CAMSS_PHY1_BCR 58
76#define GCC_CAMSS_CSI1_BCR 59
77#define GCC_CAMSS_CSI1PHY_BCR 60
78#define GCC_CAMSS_CSI1RDI_BCR 61
79#define GCC_CAMSS_CSI1PIX_BCR 62
80#define GCC_CAMSS_ISPIF_BCR 63
81#define GCC_CAMSS_CCI_BCR 64
82#define GCC_CAMSS_MCLK0_BCR 65
83#define GCC_CAMSS_MCLK1_BCR 66
84#define GCC_CAMSS_GP0_BCR 67
85#define GCC_CAMSS_GP1_BCR 68
86#define GCC_CAMSS_TOP_BCR 69
87#define GCC_CAMSS_MICRO_BCR 70
88#define GCC_CAMSS_JPEG_BCR 71
89#define GCC_CAMSS_VFE_BCR 72
90#define GCC_CAMSS_CSI_VFE0_BCR 73
91#define GCC_OXILI_BCR 74
92#define GCC_GMEM_BCR 75
93#define GCC_CAMSS_AHB_BCR 76
94#define GCC_MDP_TBU_BCR 77
95#define GCC_GFX_TBU_BCR 78
96#define GCC_GFX_TCU_BCR 79
97#define GCC_MSS_TBU_AXI_BCR 80
98#define GCC_MSS_TBU_GSS_AXI_BCR 81
99#define GCC_MSS_TBU_Q6_AXI_BCR 82
100#define GCC_GTCU_AHB_BCR 83
101#define GCC_SMMU_CFG_BCR 84
102#define GCC_VFE_TBU_BCR 85
103#define GCC_VENUS_TBU_BCR 86
104#define GCC_JPEG_TBU_BCR 87
105#define GCC_PRONTO_TBU_BCR 88
106#define GCC_SMMU_CATS_BCR 89
107
108#endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5591ea71a8d1..df695313f975 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -541,7 +541,7 @@ struct clk_gpio {
541 541
542extern const struct clk_ops clk_gpio_gate_ops; 542extern const struct clk_ops clk_gpio_gate_ops;
543struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 543struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
544 const char *parent_name, struct gpio_desc *gpio, 544 const char *parent_name, unsigned gpio, bool active_low,
545 unsigned long flags); 545 unsigned long flags);
546 546
547void of_gpio_clk_gate_setup(struct device_node *node); 547void of_gpio_clk_gate_setup(struct device_node *node);
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index c8e3b3d1eded..7669f7618f39 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -20,10 +20,10 @@
20extern void __iomem *at91_pmc_base; 20extern void __iomem *at91_pmc_base;
21 21
22#define at91_pmc_read(field) \ 22#define at91_pmc_read(field) \
23 __raw_readl(at91_pmc_base + field) 23 readl_relaxed(at91_pmc_base + field)
24 24
25#define at91_pmc_write(field, value) \ 25#define at91_pmc_write(field, value) \
26 __raw_writel(value, at91_pmc_base + field) 26 writel_relaxed(value, at91_pmc_base + field)
27#else 27#else
28.extern at91_pmc_base 28.extern at91_pmc_base
29#endif 29#endif
diff --git a/include/trace/events/clk.h b/include/trace/events/clk.h
new file mode 100644
index 000000000000..758607226bfd
--- /dev/null
+++ b/include/trace/events/clk.h
@@ -0,0 +1,198 @@
1/*
2 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#undef TRACE_SYSTEM
14#define TRACE_SYSTEM clk
15
16#if !defined(_TRACE_CLK_H) || defined(TRACE_HEADER_MULTI_READ)
17#define _TRACE_CLK_H
18
19#include <linux/tracepoint.h>
20
21struct clk_core;
22
23DECLARE_EVENT_CLASS(clk,
24
25 TP_PROTO(struct clk_core *core),
26
27 TP_ARGS(core),
28
29 TP_STRUCT__entry(
30 __string( name, core->name )
31 ),
32
33 TP_fast_assign(
34 __assign_str(name, core->name);
35 ),
36
37 TP_printk("%s", __get_str(name))
38);
39
40DEFINE_EVENT(clk, clk_enable,
41
42 TP_PROTO(struct clk_core *core),
43
44 TP_ARGS(core)
45);
46
47DEFINE_EVENT(clk, clk_enable_complete,
48
49 TP_PROTO(struct clk_core *core),
50
51 TP_ARGS(core)
52);
53
54DEFINE_EVENT(clk, clk_disable,
55
56 TP_PROTO(struct clk_core *core),
57
58 TP_ARGS(core)
59);
60
61DEFINE_EVENT(clk, clk_disable_complete,
62
63 TP_PROTO(struct clk_core *core),
64
65 TP_ARGS(core)
66);
67
68DEFINE_EVENT(clk, clk_prepare,
69
70 TP_PROTO(struct clk_core *core),
71
72 TP_ARGS(core)
73);
74
75DEFINE_EVENT(clk, clk_prepare_complete,
76
77 TP_PROTO(struct clk_core *core),
78
79 TP_ARGS(core)
80);
81
82DEFINE_EVENT(clk, clk_unprepare,
83
84 TP_PROTO(struct clk_core *core),
85
86 TP_ARGS(core)
87);
88
89DEFINE_EVENT(clk, clk_unprepare_complete,
90
91 TP_PROTO(struct clk_core *core),
92
93 TP_ARGS(core)
94);
95
96DECLARE_EVENT_CLASS(clk_rate,
97
98 TP_PROTO(struct clk_core *core, unsigned long rate),
99
100 TP_ARGS(core, rate),
101
102 TP_STRUCT__entry(
103 __string( name, core->name )
104 __field(unsigned long, rate )
105 ),
106
107 TP_fast_assign(
108 __assign_str(name, core->name);
109 __entry->rate = rate;
110 ),
111
112 TP_printk("%s %lu", __get_str(name), (unsigned long)__entry->rate)
113);
114
115DEFINE_EVENT(clk_rate, clk_set_rate,
116
117 TP_PROTO(struct clk_core *core, unsigned long rate),
118
119 TP_ARGS(core, rate)
120);
121
122DEFINE_EVENT(clk_rate, clk_set_rate_complete,
123
124 TP_PROTO(struct clk_core *core, unsigned long rate),
125
126 TP_ARGS(core, rate)
127);
128
129DECLARE_EVENT_CLASS(clk_parent,
130
131 TP_PROTO(struct clk_core *core, struct clk_core *parent),
132
133 TP_ARGS(core, parent),
134
135 TP_STRUCT__entry(
136 __string( name, core->name )
137 __string( pname, parent->name )
138 ),
139
140 TP_fast_assign(
141 __assign_str(name, core->name);
142 __assign_str(pname, parent->name);
143 ),
144
145 TP_printk("%s %s", __get_str(name), __get_str(pname))
146);
147
148DEFINE_EVENT(clk_parent, clk_set_parent,
149
150 TP_PROTO(struct clk_core *core, struct clk_core *parent),
151
152 TP_ARGS(core, parent)
153);
154
155DEFINE_EVENT(clk_parent, clk_set_parent_complete,
156
157 TP_PROTO(struct clk_core *core, struct clk_core *parent),
158
159 TP_ARGS(core, parent)
160);
161
162DECLARE_EVENT_CLASS(clk_phase,
163
164 TP_PROTO(struct clk_core *core, int phase),
165
166 TP_ARGS(core, phase),
167
168 TP_STRUCT__entry(
169 __string( name, core->name )
170 __field( int, phase )
171 ),
172
173 TP_fast_assign(
174 __assign_str(name, core->name);
175 __entry->phase = phase;
176 ),
177
178 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
179);
180
181DEFINE_EVENT(clk_phase, clk_set_phase,
182
183 TP_PROTO(struct clk_core *core, int phase),
184
185 TP_ARGS(core, phase)
186);
187
188DEFINE_EVENT(clk_phase, clk_set_phase_complete,
189
190 TP_PROTO(struct clk_core *core, int phase),
191
192 TP_ARGS(core, phase)
193);
194
195#endif /* _TRACE_CLK_H */
196
197/* This part must be outside protection */
198#include <trace/define_trace.h>
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