281 files changed, 13865 insertions, 4716 deletions

diff --git a/Documentation/bcache.txt b/Documentation/bcache.txt
index 77db8809bd96..b3a7e7d384f6 100644
--- a/Documentation/bcache.txt
+++ b/Documentation/bcache.txt
@@ -319,7 +319,10 @@ cache<0..n>
   Symlink to each of the cache devices comprising this cache set. 
 
 cache_available_percent
-  Percentage of cache device free.
+  Percentage of cache device which doesn't contain dirty data, and could
+  potentially be used for writeback.  This doesn't mean this space isn't used
+  for clean cached data; the unused statistic (in priority_stats) is typically
+  much lower.
 
 clear_stats
   Clears the statistics associated with this cache
@@ -423,8 +426,11 @@ nbuckets
   Total buckets in this cache
 
 priority_stats
-  Statistics about how recently data in the cache has been accessed.  This can
-  reveal your working set size.
+  Statistics about how recently data in the cache has been accessed.
+  This can reveal your working set size.  Unused is the percentage of
+  the cache that doesn't contain any data.  Metadata is bcache's
+  metadata overhead.  Average is the average priority of cache buckets.
+  Next is a list of quantiles with the priority threshold of each.
 
 written
   Sum of all data that has been written to the cache; comparison with
diff --git a/Documentation/devices.txt b/Documentation/devices.txt
index 08f01e79c41a..b9015912bca6 100644
--- a/Documentation/devices.txt
+++ b/Documentation/devices.txt
@@ -498,12 +498,8 @@ Your cooperation is appreciated.
 
                 Each device type has 5 bits (32 minors).
 
- 13 block       8-bit MFM/RLL/IDE controller
-                  0 = /dev/xda          First XT disk whole disk
-                 64 = /dev/xdb          Second XT disk whole disk
-
-                Partitions are handled in the same way as IDE disks
-                (see major number 3).
+ 13 block       Previously used for the XT disk (/dev/xdN)
+                Deleted in kernel v3.9.
 
  14 char        Open Sound System (OSS)
                   0 = /dev/mixer        Mixer control
diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
index 2a3feabd3b22..34c1505774bf 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -1,7 +1,7 @@
 Atmel AT91RM9200 Real Time Clock
 
 Required properties:
-- compatible: should be: "atmel,at91rm9200-rtc"
+- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: rtc alarm/event interrupt
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 6e3b18a8afc6..2fe6e767b3d6 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3351,9 +3351,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                         plus one apbt timer for broadcast timer.
                         x86_mrst_timer=apbt_only | lapic_and_apbt
 
-        xd=             [HW,XT] Original XT pre-IDE (RLL encoded) disks.
-        xd_geo=         See header of drivers/block/xd.c.
-
         xen_emul_unplug=                [HW,X86,XEN]
                         Unplug Xen emulated devices
                         Format: [unplug0,][unplug1]
diff --git a/Documentation/m68k/kernel-options.txt b/Documentation/m68k/kernel-options.txt
index 97d45f276fe6..eaf32a1fd0b1 100644
--- a/Documentation/m68k/kernel-options.txt
+++ b/Documentation/m68k/kernel-options.txt
@@ -80,8 +80,6 @@ Valid names are:
   /dev/sdd: -> 0x0830 (forth SCSI disk)
   /dev/sde: -> 0x0840 (fifth SCSI disk)
   /dev/fd : -> 0x0200 (floppy disk)
-  /dev/xda: -> 0x0c00 (first XT disk, unused in Linux/m68k)
-  /dev/xdb: -> 0x0c40 (second XT disk, unused in Linux/m68k)
 
   The name must be followed by a decimal number, that stands for the
 partition number. Internally, the value of the number is just
diff --git a/MAINTAINERS b/MAINTAINERS
index 250dc970c62d..5be702cc8449 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5766,7 +5766,7 @@ M:	Matthew Wilcox <willy@linux.intel.com>
 L:      linux-nvme@lists.infradead.org
 T:      git git://git.infradead.org/users/willy/linux-nvme.git
 S:      Supported
-F:      drivers/block/nvme.c
+F:      drivers/block/nvme*
 F:      include/linux/nvme.h
 
 OMAP SUPPORT
@@ -7624,7 +7624,7 @@ F:	drivers/clk/spear/
 SPI SUBSYSTEM
 M:      Mark Brown <broonie@kernel.org>
 M:      Grant Likely <grant.likely@linaro.org>
-L:      spi-devel-general@lists.sourceforge.net
+L:      linux-spi@vger.kernel.org
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
 Q:      http://patchwork.kernel.org/project/spi-devel-general/list/
 S:      Maintained
@@ -9004,7 +9004,7 @@ S:	Maintained
 F:      drivers/net/wireless/wl3501*
 
 WM97XX TOUCHSCREEN DRIVERS
-M:      Mark Brown <broonie@opensource.wolfsonmicro.com>
+M:      Mark Brown <broonie@kernel.org>
 M:      Liam Girdwood <lrg@slimlogic.co.uk>
 L:      linux-input@vger.kernel.org
 T:      git git://opensource.wolfsonmicro.com/linux-2.6-touch
@@ -9014,7 +9014,6 @@ F:	drivers/input/touchscreen/*wm97*
 F:      include/linux/wm97xx.h
 
 WOLFSON MICROELECTRONICS DRIVERS
-M:      Mark Brown <broonie@opensource.wolfsonmicro.com>
 L:      patches@opensource.wolfsonmicro.com
 T:      git git://opensource.wolfsonmicro.com/linux-2.6-asoc
 T:      git git://opensource.wolfsonmicro.com/linux-2.6-audioplus
diff --git a/Makefile b/Makefile
index 90400165125e..c6863b55f7c7 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 10
 SUBLEVEL = 0
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
 NAME = Unicycling Gorilla
 
 # *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993cee512..dfb4fee1f552 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -645,7 +645,7 @@ config ARCH_SHMOBILE
         select MULTI_IRQ_HANDLER
         select NEED_MACH_MEMORY_H
         select NO_IOPORT
-        select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
+        select PINCTRL
         select PM_GENERIC_DOMAINS if PM
         select SPARSE_IRQ
         help
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 3580d57ea218..79e9bdbfc491 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -124,7 +124,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
 ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all -DZIMAGE
+asflags-y := -DZIMAGE
 
 # Supply kernel BSS size to the decompressor via a linker symbol.
 KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S
index 6e8382d5b7a4..5392ee63338f 100644
--- a/arch/arm/boot/compressed/debug.S
+++ b/arch/arm/boot/compressed/debug.S
@@ -1,6 +1,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+#ifndef CONFIG_DEBUG_SEMIHOSTING
+
 #include CONFIG_DEBUG_LL_INCLUDE
 
 ENTRY(putc)
@@ -10,3 +12,29 @@ ENTRY(putc)
         busyuart r3, r1
         mov      pc, lr
 ENDPROC(putc)
+
+#else
+
+ENTRY(putc)
+        adr     r1, 1f
+        ldmia   r1, {r2, r3}
+        add     r2, r2, r1
+        ldr     r1, [r2, r3]
+        strb    r0, [r1]
+        mov     r0, #0x03               @ SYS_WRITEC
+   ARM( svc     #0x123456       )
+ THUMB( svc     #0xab           )
+        mov     pc, lr
+        .align  2
+1:      .word   _GLOBAL_OFFSET_TABLE_ - .
+        .word   semi_writec_buf(GOT)
+ENDPROC(putc)
+
+        .bss
+        .global semi_writec_buf
+        .type   semi_writec_buf, %object
+semi_writec_buf:
+        .space  4
+        .size   semi_writec_buf, 4
+
+#endif
diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
index 6179d94dd5c6..3115e313d9f6 100644
--- a/arch/arm/boot/compressed/head-sa1100.S
+++ b/arch/arm/boot/compressed/head-sa1100.S
@@ -11,6 +11,7 @@
 #include <asm/mach-types.h>
 
                 .section        ".start", "ax"
+                .arch   armv4
 
 __SA1100_start:
 
diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S
index 089c560e07f1..92b56897ed64 100644
--- a/arch/arm/boot/compressed/head-shark.S
+++ b/arch/arm/boot/compressed/head-shark.S
@@ -18,6 +18,7 @@
         
                 .section        ".start", "ax"
 
+                .arch armv4
                 b       __beginning
         
 __ofw_data:     .long   0                               @ the number of memory blocks
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fe4d9c3ad761..032a8d987148 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -11,6 +11,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+        .arch   armv7-a
 /*
  * Debugging stuff
  *
@@ -805,8 +806,8 @@ call_cache_fn:	adr	r12, proc_types
                 .align  2
                 .type   proc_types,#object
 proc_types:
-                .word   0x00000000              @ old ARM ID
-                .word   0x0000f000
+                .word   0x41000000              @ old ARM ID
+                .word   0xff00f000
                 mov     pc, lr
  THUMB(         nop                             )
                 mov     pc, lr
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b88adf..8e1248f01fab 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -409,8 +409,8 @@
                         ti,hwmods = "gpmc";
                         reg = <0x50000000 0x2000>;
                         interrupts = <100>;
-                        num-cs = <7>;
-                        num-waitpins = <2>;
+                        gpmc,num-cs = <7>;
+                        gpmc,num-waitpins = <2>;
                         #address-cells = <2>;
                         #size-cells = <1>;
                         status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 3ee63d128e27..76db557adbe7 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,8 +39,9 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000
-                          0xf0000000 0 0xf0000000 0x1000000>;
+                ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */
+                          0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
+                          0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;
 
                 internal-regs {
                         serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 46b785064dd8..fdea75c73411 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,8 +27,9 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000
-                          0xf0000000 0 0xf0000000 0x8000000>;
+                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
+                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
+                          0xf0000000 0 0xf0000000 0x8000000     /* Device Bus, NOR 128MiB   */>;
 
                 internal-regs {
                         serial@12000 {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60deb52b..eeb734e25709 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -56,9 +56,23 @@
         };
 };
 
+&omap4_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6030_wkup_pins
+        >;
+
+        twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+                pinctrl-single,pins = <
+                        0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+                >;
+        };
+};
+
 &omap4_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
+                        &twl6030_pins
                         &twl6040_pins
                         &mcpdm_pins
                         &mcbsp1_pins
@@ -66,6 +80,12 @@
                         &tpd12s015_pins
         >;
 
+        twl6030_pins: pinmux_twl6030_pins {
+                pinctrl-single,pins = <
+                        0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+                >;
+        };
+
         twl6040_pins: pinmux_twl6040_pins {
                 pinctrl-single,pins = <
                         0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index a35d9cd58063..98505a2ef162 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -142,9 +142,23 @@
         };
 };
 
+&omap4_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6030_wkup_pins
+        >;
+
+        twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+                pinctrl-single,pins = <
+                        0x14 0x2        /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
+                >;
+        };
+};
+
 &omap4_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
+                        &twl6030_pins
                         &twl6040_pins
                         &mcpdm_pins
                         &dmic_pins
@@ -179,6 +193,12 @@
                 >;
         };
 
+        twl6030_pins: pinmux_twl6030_pins {
+                pinctrl-single,pins = <
+                        0x15e 0x4118    /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
+                >;
+        };
+
         twl6040_pins: pinmux_twl6040_pins {
                 pinctrl-single,pins = <
                         0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff825828..635cae283011 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -538,6 +538,7 @@
                         interrupts = <0 41 0x4>;
                         ti,hwmods = "timer5";
                         ti,timer-dsp;
+                        ti,timer-pwm;
                 };
 
                 timer6: timer@4013a000 {
@@ -574,6 +575,7 @@
                         reg = <0x4803e000 0x80>;
                         interrupts = <0 45 0x4>;
                         ti,hwmods = "timer9";
+                        ti,timer-pwm;
                 };
 
                 timer10: timer@48086000 {
@@ -581,6 +583,7 @@
                         reg = <0x48086000 0x80>;
                         interrupts = <0 46 0x4>;
                         ti,hwmods = "timer10";
+                        ti,timer-pwm;
                 };
 
                 timer11: timer@48088000 {
diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h
index 968c0a14e0a3..209e6504922e 100644
--- a/arch/arm/include/asm/percpu.h
+++ b/arch/arm/include/asm/percpu.h
@@ -30,8 +30,15 @@ static inline void set_my_cpu_offset(unsigned long off)
 static inline unsigned long __my_cpu_offset(void)
 {
         unsigned long off;
-        /* Read TPIDRPRW */
-        asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : : "memory");
+        register unsigned long *sp asm ("sp");
+
+        /*
+         * Read TPIDRPRW.
+         * We want to allow caching the value, so avoid using volatile and
+         * instead use a fake stack read to hazard against barrier().
+         */
+        asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp));
+
         return off;
 }
 #define __my_cpu_offset __my_cpu_offset()
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index f10316b4ecdc..c5a59546a256 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -13,6 +13,7 @@
 
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/percpu.h>
 #include <linux/node.h>
@@ -200,6 +201,7 @@ static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}
  * cpu topology table
  */
 struct cputopo_arm cpu_topology[NR_CPUS];
+EXPORT_SYMBOL_GPL(cpu_topology);
 
 const struct cpumask *cpu_coregroup_mask(int cpu)
 {
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 827cde42414f..e96fd71abd76 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -22,9 +22,10 @@ static unsigned int __init kirkwood_variant(void)
 
         kirkwood_pcie_id(&dev, &rev);
 
-        if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
-            (dev == MV88F6282_DEV_ID))
+        if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
                 return MPP_F6281_MASK;
+        if (dev == MV88F6282_DEV_ID)
+                return MPP_F6282_MASK;
         if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
                 return MPP_F6192_MASK;
         if (dev == MV88F6180_DEV_ID)
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index 8f3bf4e50908..bbd6a3f717e6 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -20,11 +20,12 @@
 
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 
 #include "clock.h"
 #include "clock36xx.h"
-
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 /**
  * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
@@ -39,29 +40,28 @@
  */
 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 {
-        struct clk_hw_omap *parent;
+        struct clk_divider *parent;
         struct clk_hw *parent_hw;
-        u32 dummy_v, orig_v, clksel_shift;
+        u32 dummy_v, orig_v;
         int ret;
 
         /* Clear PWRDN bit of HSDIVIDER */
         ret = omap2_dflt_clk_enable(clk);
 
         parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
-        parent = to_clk_hw_omap(parent_hw);
+        parent = to_clk_divider(parent_hw);
 
         /* Restore the dividers */
         if (!ret) {
-                clksel_shift = __ffs(parent->clksel_mask);
-                orig_v = __raw_readl(parent->clksel_reg);
+                orig_v = __raw_readl(parent->reg);
                 dummy_v = orig_v;
 
                 /* Write any other value different from the Read value */
-                dummy_v ^= (1 << clksel_shift);
-                __raw_writel(dummy_v, parent->clksel_reg);
+                dummy_v ^= (1 << parent->shift);
+                __raw_writel(dummy_v, parent->reg);
 
                 /* Write the original divider */
-                __raw_writel(orig_v, parent->clksel_reg);
+                __raw_writel(orig_v, parent->reg);
         }
 
         return ret;
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 075f7cc51026..69337af748cc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -2007,6 +2007,13 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
         },
 };
 
+/* uart2 */
+static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
+        { .name = "tx", .dma_req = 28, },
+        { .name = "rx", .dma_req = 29, },
+        { .dma_req = -1 }
+};
+
 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
         { .irq = 73 + OMAP_INTC_START, },
         { .irq = -1 },
@@ -2018,7 +2025,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
         .mpu_irqs       = am33xx_uart2_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
+        .sdma_reqs      = uart2_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
                 .omap4  = {
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c01859398b54..5a2d8034c8de 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
         /* Clear any pending PRCM interrupts */
         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-        if (omap3_has_iva())
-                omap3_iva_idle();
+        /*
+         * We need to idle iva2_pwrdm even on am3703 with no iva2.
+         */
+        omap3_iva_idle();
 
         omap3_d2d_idle();
 }
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 9936c180bf01..8f595c0cc8d9 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -101,8 +101,10 @@ static int __init sirfsoc_of_pwrc_init(void)
         struct device_node *np;
 
         np = of_find_matching_node(NULL, pwrc_ids);
-        if (!np)
-                panic("unable to find compatible pwrc node in dtb\n");
+        if (!np) {
+                pr_err("unable to find compatible sirf pwrc node in dtb\n");
+                return -ENOENT;
+        }
 
         /*
          * pwrc behind rtciobrg is not located in memory space
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019ca0a48..d5e0cbc934c0 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -28,8 +28,10 @@ static int __init sirfsoc_of_rstc_init(void)
         struct device_node *np;
 
         np = of_find_matching_node(NULL, rstc_ids);
-        if (!np)
-                panic("unable to find compatible rstc node in dtb\n");
+        if (!np) {
+                pr_err("unable to find compatible sirf rstc node in dtb\n");
+                return -ENOENT;
+        }
 
         sirfsoc_rstc_base = of_iomap(np, 0);
         if (!sirfsoc_rstc_base)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2fe449..5414402938a5 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -36,7 +36,8 @@ config ARCH_R8A7740
         select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7778
-        bool "R-Car M1 (R8A77780)"
+        bool "R-Car M1A (R8A77781)"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select CPU_V7
         select SH_CLK_CPG
         select ARM_GIC
@@ -169,6 +170,8 @@ config MACH_KZM9D
 config MACH_KZM9G
         bool "KZM-A9-GT board"
         depends on ARCH_SH73A0
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 45f78cadec1d..297bf5eec5ab 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1026,10 +1026,8 @@ out:
 
 /* TouchScreen */
 #ifdef CONFIG_AP4EVB_QHD
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
 # define GPIO_TSC_PORT  123
 #else /* WVGA */
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ7_40
 # define GPIO_TSC_PORT  40
 #endif
 
@@ -1037,22 +1035,12 @@ out:
 #define IRQ7    evt2irq(0x02e0) /* IRQ7A */
 static int ts_get_pendown_state(void)
 {
-        int val;
-
-        gpio_free(GPIO_TSC_IRQ);
-
-        gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
-
-        val = gpio_get_value(GPIO_TSC_PORT);
-
-        gpio_request(GPIO_TSC_IRQ, NULL);
-
-        return !val;
+        return !gpio_get_value(GPIO_TSC_PORT);
 }
 
 static int ts_init(void)
 {
-        gpio_request(GPIO_TSC_IRQ, NULL);
+        gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
 
         return 0;
 }
@@ -1086,11 +1074,42 @@ static struct i2c_board_info i2c1_devices[] = {
 
 
 static const struct pinctrl_map ap4evb_pinctrl_map[] = {
+        /* CEU */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_clk_0", "ceu"),
+        /* FSIA (AK4643) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_out", "fsia"),
+        /* FSIB (HDMI) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+                                  "fsib_mclk_in", "fsib"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+                                  "hdmi", "hdmi"),
+        /* KEYSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
+                                  "keysc_in04_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
+                                  "keysc_out5", "keysc"),
+#ifndef CONFIG_AP4EVB_QHD
+        /* LCDC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_data18", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_sync", "lcd"),
+#endif
         /* MMCIF */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
                                   "mmc0_data8_0", "mmc0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
                                   "mmc0_ctrl_0", "mmc0"),
+        /* SCIFA0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+                                  "scifa0_data", "scifa0"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_data4", "sdhi0"),
@@ -1105,6 +1124,26 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
                                   "sdhi1_data4", "sdhi1"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
                                   "sdhi1_ctrl", "sdhi1"),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "bsc_cs5a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "intc_irq6_0", "intc"),
+        /* TSC2007 */
+#ifdef CONFIG_AP4EVB_QHD
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
+                                  "intc_irq28_0", "intc"),
+#else /* WVGA */
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
+                                  "intc_irq7_0", "intc"),
+#endif
+        /* USBHS1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+                                  "usb1_vbus", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+                                  "usb1_otg_id_0", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+                                  "usb1_otg_ctrl_0", "usb1"),
 };
 
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
@@ -1137,36 +1176,16 @@ static void __init ap4evb_init(void)
                                   ARRAY_SIZE(ap4evb_pinctrl_map));
         sh7372_pinmux_init();
 
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-
         /* enable Debug switch (S6) */
         gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
         gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
         gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
         gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
 
-        /* USB enable */
-        gpio_request(GPIO_FN_VBUS0_1,    NULL);
-        gpio_request(GPIO_FN_IDIN_1_18,  NULL);
-        gpio_request(GPIO_FN_PWEN_1_115, NULL);
-        gpio_request(GPIO_FN_OVCN_1_114, NULL);
-        gpio_request(GPIO_FN_EXTLP_1,    NULL);
-        gpio_request(GPIO_FN_OVCN2_1,    NULL);
-
         /* setup USB phy */
         __raw_writew(0x8a0a, IOMEM(0xE6058130));        /* USBCR4 */
 
-        /* enable FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        /* FSI2 port A (ak4643) */
         gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
         gpio_request(9, NULL);
@@ -1177,8 +1196,7 @@ static void __init ap4evb_init(void)
         /* card detect pin for MMC slot (CN7) */
         gpio_request_one(41, GPIOF_IN, NULL);
 
-        /* setup FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
+        /* FSI2 port B (HDMI) */
         __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
 
         /* set SPU2 clock to 119.6 MHz */
@@ -1208,18 +1226,6 @@ static void __init ap4evb_init(void)
          * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
          */
 
-        /* enable KEYSC */
-        gpio_request(GPIO_FN_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_KEYIN0_136, NULL);
-        gpio_request(GPIO_FN_KEYIN1_135, NULL);
-        gpio_request(GPIO_FN_KEYIN2_134, NULL);
-        gpio_request(GPIO_FN_KEYIN3_133, NULL);
-        gpio_request(GPIO_FN_KEYIN4,     NULL);
-
         /* enable TouchScreen */
         irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
 
@@ -1241,28 +1247,6 @@ static void __init ap4evb_init(void)
          * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
          * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
          */
-
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
-
         gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
         gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
@@ -1288,8 +1272,6 @@ static void __init ap4evb_init(void)
          */
 
         /* MIPI-CSI stuff */
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-
         clk = clk_get(NULL, "vck1_clk");
         if (!IS_ERR(clk)) {
                 clk_set_rate(clk, clk_round_rate(clk, 13000000));
@@ -1299,10 +1281,6 @@ static void __init ap4evb_init(void)
 
         sh7372_add_standard_devices();
 
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
         /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
 #define SRCR4 IOMEM(0xe61580bc)
         srcr4 = __raw_readl(SRCR4);
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b2882dbd0..44a621505eeb 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -584,7 +584,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = {
 static struct fixed_voltage_config vcc_sdhi0_info = {
         .supply_name = "SDHI0 Vcc",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT75,
+        .gpio = 75,
         .enable_high = 1,
         .init_data = &vcc_sdhi0_init_data,
 };
@@ -615,7 +615,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = {
 };
 
 static struct gpio vccq_sdhi0_gpios[] = {
-        {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
+        {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
 };
 
 static struct gpio_regulator_state vccq_sdhi0_states[] = {
@@ -626,7 +626,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = {
 static struct gpio_regulator_config vccq_sdhi0_info = {
         .supply_name = "vqmmc",
 
-        .enable_gpio = GPIO_PORT74,
+        .enable_gpio = 74,
         .enable_high = 1,
         .enabled_at_boot = 0,
 
@@ -664,7 +664,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = {
 static struct fixed_voltage_config vcc_sdhi1_info = {
         .supply_name = "SDHI1 Vcc",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT16,
+        .gpio = 16,
         .enable_high = 1,
         .init_data = &vcc_sdhi1_init_data,
 };
@@ -693,7 +693,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
                           MMC_CAP_POWER_OFF_CARD,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
-        .cd_gpio        = GPIO_PORT167,
+        .cd_gpio        = 167,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -736,7 +736,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
                           MMC_CAP_POWER_OFF_CARD,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
         /* Port72 cannot generate IRQs, will be used in polling mode. */
-        .cd_gpio        = GPIO_PORT72,
+        .cd_gpio        = 72,
 };
 
 static struct resource sdhi1_resources[] = {
@@ -1046,6 +1046,35 @@ static struct platform_device *eva_devices[] __initdata = {
 };
 
 static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* CEU0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_data_0_7", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_clk_0", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_sync", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_field", "ceu0"),
+        /* FSIA */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_mclk_out", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_in_1", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_out_0", "fsia"),
+        /* FSIB */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
+                                  "fsib_mclk_in", "fsib"),
+        /* GETHER */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_mii", "gether"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_int", "gether"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",
+                                  "hdmi", "hdmi"),
         /* LCD0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
                                   "lcd0_data24_0", "lcd0"),
@@ -1058,6 +1087,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                   "mmc0_data8_1", "mmc0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
                                   "mmc0_ctrl_1", "mmc0"),
+        /* SCIFA1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+                                  "scifa1_data", "scifa1"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                   "sdhi0_data4", "sdhi0"),
@@ -1065,6 +1097,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                   "sdhi0_wp", "sdhi0"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740",
+                                  "intc_irq10", "intc"),
+        /* USBHS */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740",
+                                  "intc_irq7_1", "intc"),
 };
 
 static void __init eva_clock_init(void)
@@ -1119,40 +1157,14 @@ static void __init eva_init(void)
         r8a7740_pinmux_init();
         r8a7740_meram_workaround();
 
-        /* SCIFA1 */
-        gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
-
         /* LCDC0 */
-        gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
-
         gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
         gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
 
         /* Touchscreen */
-        gpio_request(GPIO_FN_IRQ10,     NULL); /* TP_INT */
+        gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
 
         /* GETHER */
-        gpio_request(GPIO_FN_ET_CRS,            NULL);
-        gpio_request(GPIO_FN_ET_MDC,            NULL);
-        gpio_request(GPIO_FN_ET_MDIO,           NULL);
-        gpio_request(GPIO_FN_ET_TX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_RX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD3,          NULL);
-        gpio_request(GPIO_FN_ET_TX_CLK,         NULL);
-        gpio_request(GPIO_FN_ET_TX_EN,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD3,          NULL);
-        gpio_request(GPIO_FN_ET_PHY_INT,        NULL);
-        gpio_request(GPIO_FN_ET_COL,            NULL);
-        gpio_request(GPIO_FN_ET_RX_DV,          NULL);
-        gpio_request(GPIO_FN_ET_RX_CLK,         NULL);
-
         gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
 
         /* USB */
@@ -1163,34 +1175,17 @@ static void __init eva_init(void)
         } else {
                 /* USB Func */
                 /*
-                 * A1 chip has 2 IRQ7 pin and it was controled by MSEL register.
-                 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
-                 * USB connection/disconnection (usbhsf_get_vbus()).
-                 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
-                 * and select GPIO 209 here
+                 * The USBHS interrupt handlers needs to read the IRQ pin value
+                 * (HI/LOW) to diffentiate USB connection and disconnection
+                 * events (usbhsf_get_vbus()). We thus need to select both the
+                 * intc_irq7_1 pin group and GPIO 209 here.
                  */
-                gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
                 gpio_request_one(209, GPIOF_IN, NULL);
 
                 platform_device_register(&usbhsf_device);
                 usb = &usbhsf_device;
         }
 
-        /* CEU0 */
-        gpio_request(GPIO_FN_VIO0_D7,           NULL);
-        gpio_request(GPIO_FN_VIO0_D6,           NULL);
-        gpio_request(GPIO_FN_VIO0_D5,           NULL);
-        gpio_request(GPIO_FN_VIO0_D4,           NULL);
-        gpio_request(GPIO_FN_VIO0_D3,           NULL);
-        gpio_request(GPIO_FN_VIO0_D2,           NULL);
-        gpio_request(GPIO_FN_VIO0_D1,           NULL);
-        gpio_request(GPIO_FN_VIO0_D0,           NULL);
-        gpio_request(GPIO_FN_VIO0_CLK,          NULL);
-        gpio_request(GPIO_FN_VIO0_HD,           NULL);
-        gpio_request(GPIO_FN_VIO0_VD,           NULL);
-        gpio_request(GPIO_FN_VIO0_FIELD,        NULL);
-        gpio_request(GPIO_FN_VIO_CKO,           NULL);
-
         /* CON1/CON15 Camera */
         gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
         gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
@@ -1198,24 +1193,11 @@ static void __init eva_init(void)
         gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
 
         /* FSI-WM8978 */
-        gpio_request(GPIO_FN_FSIAIBT,           NULL);
-        gpio_request(GPIO_FN_FSIAILR,           NULL);
-        gpio_request(GPIO_FN_FSIAOMC,           NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,          NULL);
-        gpio_request(GPIO_FN_FSIAISLD_PORT5,    NULL);
-
         gpio_request(7, NULL);
         gpio_request(8, NULL);
         gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
 
-        /* FSI-HDMI */
-        gpio_request(GPIO_FN_FSIBCK,            NULL);
-
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD,          NULL);
-        gpio_request(GPIO_FN_HDMI_CEC,          NULL);
-
         /*
          * CAUTION
          *
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 38e5e50fb318..dac4365c5158 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 #include <mach/common.h>
@@ -37,6 +38,14 @@ static struct resource smsc911x_resources[] = {
         DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
 };
 
+static const struct pinctrl_map bockw_pinctrl_map[] = {
+        /* SCIF0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_data_a", "scif0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_ctrl", "scif0"),
+};
+
 #define IRQ0MR  0x30
 static void __init bockw_init(void)
 {
@@ -46,6 +55,10 @@ static void __init bockw_init(void)
         r8a7778_init_irq_extpin(1);
         r8a7778_add_standard_devices();
 
+        pinctrl_register_mappings(bockw_pinctrl_map,
+                                  ARRAY_SIZE(bockw_pinctrl_map));
+        r8a7778_pinmux_init();
+
         fpga = ioremap_nocache(0x18200000, SZ_1M);
         if (fpga) {
                 /*
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 70d992c540ae..b373e9ced573 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -331,12 +331,6 @@ static struct platform_device smsc_device = {
 };
 
 /*
- * core board devices
- */
-static struct platform_device *bonito_core_devices[] __initdata = {
-};
-
-/*
  * base board devices
  */
 static struct platform_device *bonito_base_devices[] __initdata = {
@@ -375,12 +369,37 @@ static void __init bonito_map_io(void)
 #define VCCQ1CR         IOMEM(0xE6058140)
 #define VCCQ1LCDCR      IOMEM(0xE6058186)
 
+/*
+ * HACK: The FPGA mappings should be associated with the FPGA device, but we
+ * don't have one at the moment. Associate them with the PFC device to make
+ * sure they will be applied.
+ */
+static const struct pinctrl_map fpga_pinctrl_map[] = {
+        /* FPGA */
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "bsc_cs5a_0", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "bsc_cs5b", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "bsc_cs6a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "intc_irq10", "intc"),
+};
+
+static const struct pinctrl_map scifa5_pinctrl_map[] = {
+        /* SCIFA5 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740",
+                                  "scifa5_data_2", "scifa5"),
+};
+
 static void __init bonito_init(void)
 {
         u16 val;
 
         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        pinctrl_register_mappings(fpga_pinctrl_map,
+                                  ARRAY_SIZE(fpga_pinctrl_map));
         r8a7740_pinmux_init();
         bonito_fpga_init();
 
@@ -397,9 +416,6 @@ static void __init bonito_init(void)
 
         r8a7740_add_standard_devices();
 
-        platform_add_devices(bonito_core_devices,
-                             ARRAY_SIZE(bonito_core_devices));
-
         /*
          * base board settings
          */
@@ -409,14 +425,6 @@ static void __init bonito_init(void)
                 u16 bsw3;
                 u16 bsw4;
 
-                /*
-                 * FPGA
-                 */
-                gpio_request(GPIO_FN_CS5B,              NULL);
-                gpio_request(GPIO_FN_CS6A,              NULL);
-                gpio_request(GPIO_FN_CS5A_PORT105,      NULL);
-                gpio_request(GPIO_FN_IRQ10,             NULL);
-
                 val = bonito_fpga_read(BVERR);
                 pr_info("bonito version: cpu %02x, base %02x\n",
                         ((val >> 8) & 0xFF),
@@ -432,8 +440,8 @@ static void __init bonito_init(void)
                 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
                     BIT_OFF(bsw3, 9) && /* S39.6 = ON */
                     BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
-                        gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
-                        gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
+                        pinctrl_register_mappings(scifa5_pinctrl_map,
+                                                  ARRAY_SIZE(scifa5_pinctrl_map));
                 }
 
                 /*
@@ -443,7 +451,6 @@ static void __init bonito_init(void)
                     BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
                         pinctrl_register_mappings(lcdc0_pinctrl_map,
                                                   ARRAY_SIZE(lcdc0_pinctrl_map));
-                        gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
 
                         gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
                                          NULL); /* LCDDON */
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index aefa50d385b7..44055fe8a45c 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -79,7 +79,6 @@ static void __init kzm_init(void)
         sh73a0_pinmux_init();
 
         /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
         gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
 
         gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a10aad..1fdf05cb6da1 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -663,13 +663,13 @@ static unsigned long pin_pullup_conf[] = {
 
 static const struct pinctrl_map kzm_pinctrl_map[] = {
         /* FSIA (AK4648) */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_mclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_sclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_data_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_data_out", "fsia"),
         /* I2C3 */
         PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
@@ -788,9 +788,6 @@ static void __init kzm_init(void)
         /* Touchscreen */
         gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
 
-        /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
-
 #ifdef CONFIG_CACHE_L2X0
         /* Early BRESP enable, Shared attribute override enable, 64K*8way */
         l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f587187a8603..6114edd0a977 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -21,15 +21,30 @@
 #include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 #include <mach/r8a7790.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+static const struct pinctrl_map lager_pinctrl_map[] = {
+        /* SCIF0 (CN19: DEBUG SERIAL0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
+                                  "scif0_data", "scif0"),
+        /* SCIF1 (CN20: DEBUG SERIAL1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
+                                  "scif1_data", "scif1"),
+};
+
 static void __init lager_add_standard_devices(void)
 {
         r8a7790_clock_init();
+
+        pinctrl_register_mappings(lager_pinctrl_map,
+                                  ARRAY_SIZE(lager_pinctrl_map));
+        r8a7790_pinmux_init();
+
         r8a7790_add_standard_devices();
 }
 
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fa3407da682a..85f51a849a50 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1309,6 +1309,49 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 static const struct pinctrl_map mackerel_pinctrl_map[] = {
+        /* ADXL34X */
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
+                                  "intc_irq21", "intc"),
+        /* CEU */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_data_0_7", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_clk_0", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_sync", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_field", "ceu"),
+        /* FLCTL */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_data", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ce0", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ctrl", "flctl"),
+        /* FSIA (AK4643) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_out", "fsia"),
+        /* FSIB (HDMI) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+                                  "fsib_mclk_in", "fsib"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+                                  "hdmi", "hdmi"),
+        /* LCDC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_data24", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_sync", "lcd"),
+        /* SCIFA0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+                                  "scifa0_data", "scifa0"),
+        /* SCIFA2 (GT-720F GPS module) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372",
+                                  "scifa2_data", "scifa2"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_data4", "sdhi0"),
@@ -1316,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_wp", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "intc_irq26_1", "intc"),
         /* SDHI1 */
 #if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
@@ -1334,6 +1379,25 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                   "sdhi2_data4", "sdhi2"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
                                   "sdhi2_ctrl", "sdhi2"),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "bsc_cs5a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "intc_irq6_0", "intc"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
+                                  "intc_irq7_0", "intc"),
+        /* TCA6416 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
+                                  "intc_irq9_0", "intc"),
+        /* USBHS0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
+                                  "usb0_vbus", "usb0"),
+        /* USBHS1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_vbus", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_otg_id_0", "usb1"),
 };
 
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
@@ -1377,61 +1441,18 @@ static void __init mackerel_init(void)
                                   ARRAY_SIZE(mackerel_pinctrl_map));
         sh7372_pinmux_init();
 
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-
-        /* LCDC */
-        gpio_request(GPIO_FN_LCDD23,   NULL);
-        gpio_request(GPIO_FN_LCDD22,   NULL);
-        gpio_request(GPIO_FN_LCDD21,   NULL);
-        gpio_request(GPIO_FN_LCDD20,   NULL);
-        gpio_request(GPIO_FN_LCDD19,   NULL);
-        gpio_request(GPIO_FN_LCDD18,   NULL);
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
-
         /* backlight, off by default */
         gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
 
         gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
         /* USBHS0 */
-        gpio_request(GPIO_FN_VBUS0_0, NULL);
         gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */
 
         /* USBHS1 */
-        gpio_request(GPIO_FN_VBUS0_1, NULL);
         gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
-        gpio_request(GPIO_FN_IDIN_1_113, NULL);
 
-        /* enable FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        /* FSI2 port A (ak4643) */
         gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
         gpio_request(9,  NULL);
@@ -1441,8 +1462,7 @@ static void __init mackerel_init(void)
 
         intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
 
-        /* setup FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
+        /* FSI2 port B (HDMI) */
         __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
 
         /* set SPU2 clock to 119.6 MHz */
@@ -1452,68 +1472,15 @@ static void __init mackerel_init(void)
                 clk_put(clk);
         }
 
-        /* enable Keypad */
-        gpio_request(GPIO_FN_IRQ9_42,   NULL);
+        /* Keypad */
         irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
 
-        /* enable Touchscreen */
-        gpio_request(GPIO_FN_IRQ7_40,   NULL);
+        /* Touchscreen */
         irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
 
-        /* enable Accelerometer */
-        gpio_request(GPIO_FN_IRQ21,     NULL);
+        /* Accelerometer */
         irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
 
-        /* SDHI0 PORT172 card-detect IRQ26 */
-        gpio_request(GPIO_FN_IRQ26_172, NULL);
-
-        /* FLCTL */
-        gpio_request(GPIO_FN_D0_NAF0, NULL);
-        gpio_request(GPIO_FN_D1_NAF1, NULL);
-        gpio_request(GPIO_FN_D2_NAF2, NULL);
-        gpio_request(GPIO_FN_D3_NAF3, NULL);
-        gpio_request(GPIO_FN_D4_NAF4, NULL);
-        gpio_request(GPIO_FN_D5_NAF5, NULL);
-        gpio_request(GPIO_FN_D6_NAF6, NULL);
-        gpio_request(GPIO_FN_D7_NAF7, NULL);
-        gpio_request(GPIO_FN_D8_NAF8, NULL);
-        gpio_request(GPIO_FN_D9_NAF9, NULL);
-        gpio_request(GPIO_FN_D10_NAF10, NULL);
-        gpio_request(GPIO_FN_D11_NAF11, NULL);
-        gpio_request(GPIO_FN_D12_NAF12, NULL);
-        gpio_request(GPIO_FN_D13_NAF13, NULL);
-        gpio_request(GPIO_FN_D14_NAF14, NULL);
-        gpio_request(GPIO_FN_D15_NAF15, NULL);
-        gpio_request(GPIO_FN_FCE0, NULL);
-        gpio_request(GPIO_FN_WE0_FWE, NULL);
-        gpio_request(GPIO_FN_FRB, NULL);
-        gpio_request(GPIO_FN_A4_FOE, NULL);
-        gpio_request(GPIO_FN_A5_FCDE, NULL);
-        gpio_request(GPIO_FN_RD_FSC, NULL);
-
-        /* enable GPS module (GT-720F) */
-        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-
-        /* CEU */
-        gpio_request(GPIO_FN_VIO_CLK, NULL);
-        gpio_request(GPIO_FN_VIO_VD, NULL);
-        gpio_request(GPIO_FN_VIO_HD, NULL);
-        gpio_request(GPIO_FN_VIO_FIELD, NULL);
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-        gpio_request(GPIO_FN_VIO_D7, NULL);
-        gpio_request(GPIO_FN_VIO_D6, NULL);
-        gpio_request(GPIO_FN_VIO_D5, NULL);
-        gpio_request(GPIO_FN_VIO_D4, NULL);
-        gpio_request(GPIO_FN_VIO_D3, NULL);
-        gpio_request(GPIO_FN_VIO_D2, NULL);
-        gpio_request(GPIO_FN_VIO_D1, NULL);
-        gpio_request(GPIO_FN_VIO_D0, NULL);
-
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
         /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
         srcr4 = __raw_readl(SRCR4);
         __raw_writel(srcr4 | (1 << 13), SRCR4);
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index b9594e911ce7..9112faef923b 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -28,6 +28,7 @@
 #include <linux/leds.h>
 #include <linux/dma-mapping.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -173,15 +174,15 @@ static struct platform_device usb_phy_device = {
 static struct gpio_led marzen_leds[] = {
         {
                 .name           = "led2",
-                .gpio           = 157,
+                .gpio           = RCAR_GP_PIN(4, 29),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }, {
                 .name           = "led3",
-                .gpio           = 158,
+                .gpio           = RCAR_GP_PIN(4, 30),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }, {
                 .name           = "led4",
-                .gpio           = 159,
+                .gpio           = RCAR_GP_PIN(4, 31),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
 };
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index e710c00c3822..f6227bb10aca 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,15 +22,43 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x270
 
-#define MPCKCR 0xe6150080
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR5 0xe6150144
 
+#define FRQCRA          0xE6150000
+#define FRQCRB          0xE6150004
+#define VCLKCR1         0xE6150008
+#define VCLKCR2         0xE615000C
+#define VCLKCR3         0xE615001C
+#define VCLKCR4         0xE6150014
+#define VCLKCR5         0xE6150034
+#define ZBCKCR          0xE6150010
+#define SD0CKCR         0xE6150074
+#define SD1CKCR         0xE6150078
+#define SD2CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define FSIACKCR        0xE6150018
+#define FSIBCKCR        0xE6150090
+#define MPCKCR          0xe6150080
+#define SPUVCKCR        0xE6150094
+#define HSICKCR         0xE615026C
+#define M4CKCR          0xE6150098
+#define PLLECR          0xE61500D0
+#define PLL1CR          0xE6150028
+#define PLL2CR          0xE615002C
+#define PLL2SCR         0xE61501F4
+#define PLL2HCR         0xE61501E4
+#define CKSCR           0xE61500C0
+
+#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
@@ -51,29 +79,326 @@ static struct clk extal2_clk = {
         .mapping        = &cpg_mapping,
 };
 
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
+};
+
+SH_CLK_RATIO(div2,      1, 2);
+SH_CLK_RATIO(div4,      1, 4);
+
+SH_FIXED_RATIO_CLK(main_div2_clk,       main_clk,               div2);
+SH_FIXED_RATIO_CLK(extal1_div2_clk,     extal1_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div2_clk,     extal2_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div4_clk,     extal2_clk,             div4);
+
+/* External FSIACK/FSIBCK clock */
+static struct clk fsiack_clk = {
+};
+
+static struct clk fsibck_clk = {
+};
+
+/*
+ *              PLL clocks
+ */
+static struct clk *pll_parent_main[] = {
+        [0] = &main_clk,
+        [1] = &main_div2_clk
+};
+
+static struct clk *pll_parent_main_extal[8] = {
+        [0] = &main_div2_clk,
+        [1] = &extal2_div2_clk,
+        [3] = &extal2_div4_clk,
+        [4] = &main_clk,
+        [5] = &extal2_clk,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
+                mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
+
+        return clk->parent->rate * mult;
+}
+
+static int pll_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 val;
+        int i, ret;
+
+        if (!clk->parent_table || !clk->parent_num)
+                return -EINVAL;
+
+        /* Search the parent */
+        for (i = 0; i < clk->parent_num; i++)
+                if (clk->parent_table[i] == parent)
+                        break;
+
+        if (i == clk->parent_num)
+                return -ENODEV;
+
+        ret = clk_reparent(clk, parent);
+        if (ret < 0)
+                return ret;
+
+        val = ioread32(clk->mapped_reg) &
+                ~(((1 << clk->src_width) - 1) << clk->src_shift);
+
+        iowrite32(val | i << clk->src_shift, clk->mapped_reg);
+
+        return 0;
+}
+
+static struct sh_clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+        .set_parent     = pll_set_parent,
+};
+
+#define PLL_CLOCK(name, p, pt, w, s, reg, e)            \
+        static struct clk name = {                      \
+                .ops            = &pll_clk_ops,         \
+                .flags          = CLK_ENABLE_ON_INIT,   \
+                .parent         = p,                    \
+                .parent_table   = pt,                   \
+                .parent_num     = ARRAY_SIZE(pt),       \
+                .src_width      = w,                    \
+                .src_shift      = s,                    \
+                .enable_reg     = (void __iomem *)reg,  \
+                .enable_bit     = e,                    \
+                .mapping        = &cpg_mapping,         \
+        }
+
+PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
+PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
+PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
+PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
+
+SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
+
 static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
+        &extal1_div2_clk,
         &extal2_clk,
+        &extal2_div2_clk,
+        &extal2_div4_clk,
+        &main_clk,
+        &main_div2_clk,
+        &fsiack_clk,
+        &fsibck_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll2_clk,
+        &pll2s_clk,
+        &pll2h_clk,
+};
+
+/* DIV4 */
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRB to update hardware setting */
+        value = ioread32(CPG_MAP(FRQCRB));
+        value |= (1 << 31);
+        iowrite32(value, CPG_MAP(FRQCRB));
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors       = divisors,
+        .nr_divisors    = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick           = div4_kick,
+};
+
+enum {
+        DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
+        DIV4_ZX, DIV4_ZS, DIV4_HP,
+        DIV4_NR };
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I]        = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M3]       = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
+        [DIV4_B]        = SH_CLK_DIV4(&pll1_clk, FRQCRA,  8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  4, 0x1dff, 0),
+        [DIV4_M2]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  0, 0x1dff, 0),
+        [DIV4_ZX]       = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
+        [DIV4_ZS]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  8, 0x0dff, 0),
+        [DIV4_HP]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
 };
 
 enum {
+        DIV6_ZB,
+        DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
+        DIV6_FSIA, DIV6_FSIB,
+        DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
+        DIV6_NR };
+
+static struct clk *div6_parents[8] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [3] = &extal2_clk,
+        [4] = &main_div2_clk,
+        [6] = &extalr_clk,
+};
+
+static struct clk *fsia_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsiack_clk,
+};
+
+static struct clk *fsib_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsibck_clk,
+};
+
+static struct clk *mp_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &extal2_clk,
+        [3] = &extal2_clk,
+};
+
+static struct clk *m4_parents[2] = {
+        [0] = &pll2s_clk,
+};
+
+static struct clk *hsi_parents[4] = {
+        [0] = &pll2h_clk,
+        [1] = &pll1_div2_clk,
+        [3] = &pll2s_clk,
+};
+
+/*** FIXME ***
+ * SH_CLK_DIV6_EXT() macro doesn't care .mapping
+ * but, it is necessary on R-Car (= ioremap() base CPG)
+ * The difference between
+ * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
+ * is only .mapping
+ */
+#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents,                     \
+                            _num_parents, _src_shift, _src_width)       \
+{                                                                       \
+        .enable_reg     = (void __iomem *)_reg,                         \
+        .enable_bit     = 0, /* unused */                               \
+        .flags          = _flags | CLK_MASK_DIV_ON_DISABLE,             \
+        .div_mask       = SH_CLK_DIV6_MSK,                              \
+        .parent_table   = _parents,                                     \
+        .parent_num     = _num_parents,                                 \
+        .src_shift      = _src_shift,                                   \
+        .src_width      = _src_width,                                   \
+        .mapping        = &cpg_mapping,                                 \
+}
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
+                                div6_parents, 2, 7, 1),
+        [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
+                                fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
+        [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
+                                fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
+        [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+        /* pll2s will be selected always for M4 */
+        [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
+                                m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
+        [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
+                                hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
+        [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+};
+
+/* MSTP */
+enum {
         MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
         MSTP522,
         MSTP_NR
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
-        [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
-        [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
-        [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
-        [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
-        [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 6, 0), /* SCIFB0 */
+        [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
+        [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
+        [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
         [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
 };
 
 static struct clk_lookup lookups[] = {
+        /* main clock */
+        CLKDEV_CON_ID("extal1",                 &extal1_clk),
+        CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
+        CLKDEV_CON_ID("extal2",                 &extal2_clk),
+        CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
+        CLKDEV_CON_ID("extal2_div4",            &extal2_div4_clk),
+        CLKDEV_CON_ID("fsiack",                 &fsiack_clk),
+        CLKDEV_CON_ID("fsibck",                 &fsibck_clk),
+
+        /* pll clock */
+        CLKDEV_CON_ID("pll1",                   &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",              &pll1_div2_clk),
+        CLKDEV_CON_ID("pll2",                   &pll2_clk),
+        CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
+        CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
+
+        /* DIV6 */
+        CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
+        CLKDEV_CON_ID("sdhi0",                  &div6_clks[DIV6_SDHI0]),
+        CLKDEV_CON_ID("sdhi1",                  &div6_clks[DIV6_SDHI1]),
+        CLKDEV_CON_ID("sdhi2",                  &div6_clks[DIV6_SDHI2]),
+        CLKDEV_CON_ID("mmc0",                   &div6_clks[DIV6_MMC0]),
+        CLKDEV_CON_ID("mmc1",                   &div6_clks[DIV6_MMC1]),
+        CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2",                   &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3",                   &div6_clks[DIV6_VCK3]),
+        CLKDEV_CON_ID("vck4",                   &div6_clks[DIV6_VCK4]),
+        CLKDEV_CON_ID("vck5",                   &div6_clks[DIV6_VCK5]),
+        CLKDEV_CON_ID("fsia",                   &div6_clks[DIV6_FSIA]),
+        CLKDEV_CON_ID("fsib",                   &div6_clks[DIV6_FSIB]),
+        CLKDEV_CON_ID("mp",                     &div6_clks[DIV6_MP]),
+        CLKDEV_CON_ID("m4",                     &div6_clks[DIV6_M4]),
+        CLKDEV_CON_ID("hsi",                    &div6_clks[DIV6_HSI]),
+        CLKDEV_CON_ID("spuv",                   &div6_clks[DIV6_SPUV]),
+
+        /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -88,22 +413,40 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a73a4_clock_init(void)
 {
-        void __iomem *cpg_base, *reg;
+        void __iomem *reg;
         int k, ret = 0;
+        u32 ckscr;
+
+        reg = ioremap_nocache(CKSCR, PAGE_SIZE);
+        BUG_ON(!reg);
+        ckscr = ioread32(reg);
+        iounmap(reg);
 
-        /* fix MPCLK to EXTAL2 for now.
-         * this is needed until more detailed clock topology is supported
-         */
-        cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
-        BUG_ON(!cpg_base);
-        reg = cpg_base + (MPCKCR - CPG_BASE);
-        iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
-        iounmap(cpg_base);
+        switch ((ckscr >> 28) & 0x3) {
+        case 0:
+                main_clk.parent = &extal1_clk;
+                break;
+        case 1:
+                main_clk.parent = &extal1_div2_clk;
+                break;
+        case 2:
+                main_clk.parent = &extal2_clk;
+                break;
+        case 3:
+                main_clk.parent = &extal2_div2_clk;
+                break;
+        }
 
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
         if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
+
+        if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c0d39aa6de50..7fd32d604e34 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -266,7 +266,7 @@ static struct clk fsiack_clk = {
 static struct clk fsibck_clk = {
 };
 
-struct clk *main_clks[] = {
+static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
         &extal2_clk,
@@ -317,7 +317,7 @@ enum {
         DIV4_NR
 };
 
-struct clk div4_clks[DIV4_NR] = {
+static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
         [DIV4_ZG]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
         [DIV4_B]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  8, 0x6fff, CLK_ENABLE_ON_INIT),
@@ -461,7 +461,7 @@ enum {
 
         MSTP329, MSTP328, MSTP323, MSTP320,
         MSTP314, MSTP313, MSTP312,
-        MSTP309,
+        MSTP309, MSTP304,
 
         MSTP416, MSTP415, MSTP407, MSTP406,
 
@@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 12, 0), /* MMC */
         [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3,  9, 0), /* GEther */
+        [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP],  SMSTPCR3,  4, 0), /* TPU0 */
 
         [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 16, 0), /* USBHOST */
         [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 15, 0), /* SDHI2 */
@@ -551,6 +552,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_tmu.4",               &mstp_clks[MSTP111]),
         CLKDEV_DEV_ID("sh_tmu.5",               &mstp_clks[MSTP111]),
         CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
+        CLKDEV_DEV_ID("fff20000.i2c",           &mstp_clks[MSTP116]),
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
         CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
         CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP125]),
@@ -584,6 +586,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
+        CLKDEV_DEV_ID("e6c20000.i2c",           &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
@@ -592,6 +595,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("renesas_tpu_pwm",        &mstp_clks[MSTP304]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
         CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index cd6855290b1f..b251e4d0924d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -23,9 +23,23 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ *     MD      MD      MD      MD       PLLA   PLLB    EXTAL   clki    clkz
+ *     19      18      12      11                      (HMz)   (MHz)   (MHz)
+ *----------------------------------------------------------------------------
+ *     1       0       0       0       x21     x21     38.00   800     800
+ *     1       0       0       1       x24     x24     33.33   800     800
+ *     1       0       1       0       x28     x28     28.50   800     800
+ *     1       0       1       1       x32     x32     25.00   800     800
+ *     1       1       0       1       x24     x21     33.33   800     700
+ *     1       1       1       0       x28     x21     28.50   800     600
+ *     1       1       1       1       x32     x24     25.00   800     600
+ */
+
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define MSTPCR0         IOMEM(0xffc80030)
@@ -37,6 +51,9 @@
 #define MSTPCR4         IOMEM(0xffc80050)
 #define MSTPCR5         IOMEM(0xffc80054)
 #define MSTPCR6         IOMEM(0xffc80058)
+#define MODEMR          0xFFCC0020
+
+#define MD(nr)  BIT(nr)
 
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
@@ -47,36 +64,71 @@ static struct clk_mapping cpg_mapping = {
         .len    = 0x80,
 };
 
-static struct clk clkp = {
-        .rate   = 62500000, /* FIXME: shortcut */
-        .flags  = CLK_ENABLE_ON_INIT,
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7778_clock_init() */
         .mapping = &cpg_mapping,
 };
 
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7778_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(plla_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(pllb_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(i_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s1_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s3_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s4_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(b_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(out_clk,         plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(p_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(g_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(z_clk,           pllb_clk,  1, 1);
+
 static struct clk *main_clks[] = {
-        &clkp,
+        &extal_clk,
+        &plla_clk,
+        &pllb_clk,
+        &i_clk,
+        &s_clk,
+        &s1_clk,
+        &s3_clk,
+        &s4_clk,
+        &b_clk,
+        &out_clk,
+        &p_clk,
+        &g_clk,
+        &z_clk,
 };
 
 enum {
+        MSTP323, MSTP322, MSTP321,
         MSTP114,
         MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015,
         MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
-        [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
-        [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
-        [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
-        [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
-        [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
-        [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
-        [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
-        [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
+        [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
+        [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
+        [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
+        [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
+        [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
+        [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
+        [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
+        [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
+        [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
+        [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
+        [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
 };
 
 static struct clk_lookup lookups[] = {
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
@@ -90,8 +142,86 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7778_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
         int k, ret = 0;
 
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
+        case MD(19):
+                extal_clk.rate = 38000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       21, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        case MD(19) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       28, 1);
+                break;
+        case MD(19) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       32, 1);
+                break;
+        case MD(19) | MD(18) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        default:
+                BUG();
+        }
+
+        if (mode & MD(1)) {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 3);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 12);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 18);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 18);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        } else {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 4);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 16);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 16);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 16);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        }
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 31d5cd4d9787..9daeb8c37483 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -112,7 +112,7 @@ static struct clk *main_clks[] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP115, MSTP114,
+        MSTP116, MSTP115, MSTP114,
         MSTP103, MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
         [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
         [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
         [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */
@@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
         CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
         CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
         CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bad9bf2e34d6..b393592edc83 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -22,39 +22,174 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
+/*
+ *   MD         EXTAL           PLL0    PLL1    PLL3
+ * 14 13 19     (MHz)           *1      *1
+ *---------------------------------------------------
+ * 0  0  0      15 x 1          x172/2  x208/2  x106
+ * 0  0  1      15 x 1          x172/2  x208/2  x88
+ * 0  1  0      20 x 1          x130/2  x156/2  x80
+ * 0  1  1      20 x 1          x130/2  x156/2  x66
+ * 1  0  0      26 / 2          x200/2  x240/2  x122
+ * 1  0  1      26 / 2          x200/2  x240/2  x102
+ * 1  1  0      30 / 2          x172/2  x208/2  x106
+ * 1  1  1      30 / 2          x172/2  x208/2  x88
+ *
+ * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
+ *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
+ */
+
+#define MD(nr)  (1 << nr)
+
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
 #define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
 
+#define MODEMR          0xE6160060
+#define SDCKCR          0xE6150074
+#define SD2CKCR         0xE6150078
+#define SD3CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define SSPCKCR         0xE6150248
+#define SSPRSCKCR       0xE615024C
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
 };
 
-static struct clk p_clk = {
-        .rate   = 65000000, /* shortcut for now */
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7790_clock_init() */
         .mapping        = &cpg_mapping,
 };
 
-static struct clk mp_clk = {
-        .rate   = 52000000,  /* shortcut for now */
-        .mapping        = &cpg_mapping,
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
 };
 
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7790_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(lb_clk,                  pll1_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
+
+/* fixed ratio clock */
+SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
+SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
+
+SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
+SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(i_clk,                   pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(b_clk,                   pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
+SH_FIXED_RATIO_CLK_SET(cl_clk,                  pll1_clk,       1, 48);
+SH_FIXED_RATIO_CLK_SET(m2_clk,                  pll1_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(imp_clk,                 pll1_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
+SH_FIXED_RATIO_CLK_SET(oscclk_clk,              pll1_clk,       1, (12 * 1024));
+
+SH_FIXED_RATIO_CLK_SET(zb3_clk,                 pll3_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(zb3d2_clk,               pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(ddr_clk,                 pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
+
 static struct clk *main_clks[] = {
+        &extal_clk,
+        &extal_div2_clk,
+        &main_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll3_clk,
+        &lb_clk,
+        &qspi_clk,
+        &zg_clk,
+        &zx_clk,
+        &zs_clk,
+        &hp_clk,
+        &i_clk,
+        &b_clk,
         &p_clk,
+        &cl_clk,
+        &m2_clk,
+        &imp_clk,
+        &rclk_clk,
+        &oscclk_clk,
+        &zb3_clk,
+        &zb3d2_clk,
+        &ddr_clk,
         &mp_clk,
+        &cp_clk,
+};
+
+/* SDHI (DIV4) clock */
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum {
+        DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
+};
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+        [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
+};
+
+/* DIV6 clocks */
+enum {
+        DIV6_SD2, DIV6_SD3,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_SSP, DIV6_SSPRS,
+        DIV6_NR
+};
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+        [DIV6_SD3]      = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
+        [DIV6_MMC0]     = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
+        [DIV6_MMC1]     = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
+        [DIV6_SSP]      = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
+        [DIV6_SSPRS]    = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
+};
+
+/* MSTP */
+enum {
+        MSTP721, MSTP720,
+        MSTP304,
+        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
+        MSTP_NR
 };
 
-enum { MSTP721, MSTP720,
-        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
         [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
         [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
         [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
         [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@@ -64,6 +199,48 @@ static struct clk mstp_clks[MSTP_NR] = {
 };
 
 static struct clk_lookup lookups[] = {
+
+        /* main clocks */
+        CLKDEV_CON_ID("extal",          &extal_clk),
+        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
+        CLKDEV_CON_ID("main",           &main_clk),
+        CLKDEV_CON_ID("pll1",           &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
+        CLKDEV_CON_ID("pll3",           &pll3_clk),
+        CLKDEV_CON_ID("zg",             &zg_clk),
+        CLKDEV_CON_ID("zx",             &zx_clk),
+        CLKDEV_CON_ID("zs",             &zs_clk),
+        CLKDEV_CON_ID("hp",             &hp_clk),
+        CLKDEV_CON_ID("i",              &i_clk),
+        CLKDEV_CON_ID("b",              &b_clk),
+        CLKDEV_CON_ID("lb",             &lb_clk),
+        CLKDEV_CON_ID("p",              &p_clk),
+        CLKDEV_CON_ID("cl",             &cl_clk),
+        CLKDEV_CON_ID("m2",             &m2_clk),
+        CLKDEV_CON_ID("imp",            &imp_clk),
+        CLKDEV_CON_ID("rclk",           &rclk_clk),
+        CLKDEV_CON_ID("oscclk",         &oscclk_clk),
+        CLKDEV_CON_ID("zb3",            &zb3_clk),
+        CLKDEV_CON_ID("zb3d2",          &zb3d2_clk),
+        CLKDEV_CON_ID("ddr",            &ddr_clk),
+        CLKDEV_CON_ID("mp",             &mp_clk),
+        CLKDEV_CON_ID("qspi",           &qspi_clk),
+        CLKDEV_CON_ID("cp",             &cp_clk),
+
+        /* DIV4 */
+        CLKDEV_CON_ID("sdh",            &div4_clks[DIV4_SDH]),
+        CLKDEV_CON_ID("sd0",            &div4_clks[DIV4_SD0]),
+        CLKDEV_CON_ID("sd1",            &div4_clks[DIV4_SD1]),
+
+        /* DIV6 */
+        CLKDEV_CON_ID("sd2",            &div6_clks[DIV6_SD2]),
+        CLKDEV_CON_ID("sd3",            &div6_clks[DIV6_SD3]),
+        CLKDEV_CON_ID("mmc0",           &div6_clks[DIV6_MMC0]),
+        CLKDEV_CON_ID("mmc1",           &div6_clks[DIV6_MMC1]),
+        CLKDEV_CON_ID("ssp",            &div6_clks[DIV6_SSP]),
+        CLKDEV_CON_ID("ssprs",          &div6_clks[DIV6_SSPRS]),
+
+        /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -74,14 +251,61 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
 };
 
+#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
+        extal_clk.rate  = e * 1000 * 1000;                      \
+        main_clk.parent = m;                                    \
+        SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
+        if (mode & MD(19))                                      \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
+        else                                                    \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
+
+
 void __init r8a7790_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
         int k, ret = 0;
 
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
+                break;
+        case MD(13):
+                R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
+                break;
+        case MD(14):
+                R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
+                break;
+        case MD(13) | MD(14):
+                R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
+                break;
+        }
+
+        if (mode & (MD(18)))
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
+        else
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
+
+        if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+        else
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
         if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 784fbaa4cc55..d9fd0336b910 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
+        /*
+         * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to
+         * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and
+         * 239.2MHz for VDD_DVFS=1.315V.
+         */
         [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
         [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
@@ -252,6 +257,101 @@ static struct clk twd_clk = {
         .ops = &twd_clk_ops,
 };
 
+static struct sh_clk_ops zclk_ops, kicker_ops;
+static const struct sh_clk_ops *div4_clk_ops;
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret;
+
+        if (!clk->parent || !__clk_get(clk->parent))
+                return -ENODEV;
+
+        if (readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+
+        if (rate == clk_get_rate(clk->parent)) {
+                /* 1:1 - switch off divider */
+                __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
+                /* nullify the divider to prepare for the next time */
+                ret = div4_clk_ops->set_rate(clk, rate / 2);
+                if (!ret)
+                        ret = frqcr_kick();
+                if (ret > 0)
+                        ret = 0;
+        } else {
+                /* Enable the divider */
+                __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB);
+
+                ret = frqcr_kick();
+                if (ret >= 0)
+                        /*
+                         * set the divider - call the DIV4 method, it will kick
+                         * FRQCRB too
+                         */
+                        ret = div4_clk_ops->set_rate(clk, rate);
+                if (ret < 0)
+                        goto esetrate;
+        }
+
+esetrate:
+        __clk_put(clk->parent);
+        return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),
+                parent_freq = clk_get_rate(clk->parent);
+
+        if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
+                return parent_freq;
+
+        return div_freq;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+        /*
+         * Must recalculate frequencies in case PLL0 has been changed, even if
+         * the divisor is unused ATM!
+         */
+        unsigned long div_freq = div4_clk_ops->recalc(clk);
+
+        if (__raw_readl(FRQCRB) & (1 << 28))
+                return div_freq;
+
+        return clk_get_rate(clk->parent);
+}
+
+static int kicker_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (__raw_readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+
+        return div4_clk_ops->set_rate(clk, rate);
+}
+
+static void div4_clk_extend(void)
+{
+        int i;
+
+        div4_clk_ops = div4_clks[0].ops;
+
+        /* Add a kicker-busy check before changing the rate */
+        kicker_ops = *div4_clk_ops;
+        /* We extend the DIV4 clock with a 1:1 pass-through case */
+        zclk_ops = *div4_clk_ops;
+
+        kicker_ops.set_rate = kicker_set_rate;
+        zclk_ops.set_rate = zclk_set_rate;
+        zclk_ops.round_rate = zclk_round_rate;
+        zclk_ops.recalc = zclk_recalc;
+
+        for (i = 0; i < DIV4_NR; i++)
+                div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops;
+}
+
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
         DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
         DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -450,7 +550,7 @@ static struct clk *late_main_clks[] = {
 };
 
 enum { MSTP001,
-        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
+        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100,
         MSTP219, MSTP218, MSTP217,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
         MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
@@ -471,6 +571,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
         [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */
         [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
         [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
         [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
@@ -513,6 +614,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("r_clk", &r_clk),
         CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
 
+        /* DIV4 clocks */
+        CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),
+
         /* DIV6 clocks */
         CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
         CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
@@ -604,8 +708,11 @@ void __init sh73a0_clock_init(void)
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
-        if (!ret)
+        if (!ret) {
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+                if (!ret)
+                        div4_clk_extend();
+        }
 
         if (!ret)
                 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 76ac61292e48..03e56074928c 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -24,16 +24,16 @@ struct clk name = {			\
 }
 
 #define SH_FIXED_RATIO_CLK(name, p, r)          \
-static SH_FIXED_RATIO_CLKg(name, p, r);
+static SH_FIXED_RATIO_CLKg(name, p, r)
 
 #define SH_FIXED_RATIO_CLK_SET(name, p, m, d)   \
         SH_CLK_RATIO(name, m, d);               \
-        SH_FIXED_RATIO_CLK(name, p, name);
+        SH_FIXED_RATIO_CLK(name, p, name)
 
 #define SH_CLK_SET_RATIO(p, m, d)       \
-{                       \
+do {                    \
         (p)->mul = m;   \
         (p)->div = d;   \
-}
+} while (0)
 
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index b2074e2acb15..d241bfd6926d 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -16,4 +16,9 @@
 #define IRQPIN_BASE             2000
 #define irq_pin(nr)             ((nr) + IRQPIN_BASE)
 
+/* GPIO IRQ */
+#define _GPIO_IRQ_BASE          2500
+#define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
+#define GPIO_IRQ(x, y)          (_GPIO_IRQ_BASE + (32 * x) + y)
+
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index abdc4d4efa28..9c9a66ccaf6f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -28,494 +28,6 @@
 #define MD_CK1  (1 << 1)
 #define MD_CK0  (1 << 0)
 
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-        GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-        GPIO_PORT210, GPIO_PORT211,
-
-        /* IRQ */
-        GPIO_FN_IRQ0_PORT2,     GPIO_FN_IRQ0_PORT13,
-        GPIO_FN_IRQ1,
-        GPIO_FN_IRQ2_PORT11,    GPIO_FN_IRQ2_PORT12,
-        GPIO_FN_IRQ3_PORT10,    GPIO_FN_IRQ3_PORT14,
-        GPIO_FN_IRQ4_PORT15,    GPIO_FN_IRQ4_PORT172,
-        GPIO_FN_IRQ5_PORT0,     GPIO_FN_IRQ5_PORT1,
-        GPIO_FN_IRQ6_PORT121,   GPIO_FN_IRQ6_PORT173,
-        GPIO_FN_IRQ7_PORT120,   GPIO_FN_IRQ7_PORT209,
-        GPIO_FN_IRQ8,
-        GPIO_FN_IRQ9_PORT118,   GPIO_FN_IRQ9_PORT210,
-        GPIO_FN_IRQ10,
-        GPIO_FN_IRQ11,
-        GPIO_FN_IRQ12_PORT42,   GPIO_FN_IRQ12_PORT97,
-        GPIO_FN_IRQ13_PORT64,   GPIO_FN_IRQ13_PORT98,
-        GPIO_FN_IRQ14_PORT63,   GPIO_FN_IRQ14_PORT99,
-        GPIO_FN_IRQ15_PORT62,   GPIO_FN_IRQ15_PORT100,
-        GPIO_FN_IRQ16_PORT68,   GPIO_FN_IRQ16_PORT211,
-        GPIO_FN_IRQ17,
-        GPIO_FN_IRQ18,
-        GPIO_FN_IRQ19,
-        GPIO_FN_IRQ20,
-        GPIO_FN_IRQ21,
-        GPIO_FN_IRQ22,
-        GPIO_FN_IRQ23,
-        GPIO_FN_IRQ24,
-        GPIO_FN_IRQ25,
-        GPIO_FN_IRQ26_PORT58,   GPIO_FN_IRQ26_PORT81,
-        GPIO_FN_IRQ27_PORT57,   GPIO_FN_IRQ27_PORT168,
-        GPIO_FN_IRQ28_PORT56,   GPIO_FN_IRQ28_PORT169,
-        GPIO_FN_IRQ29_PORT50,   GPIO_FN_IRQ29_PORT170,
-        GPIO_FN_IRQ30_PORT49,   GPIO_FN_IRQ30_PORT171,
-        GPIO_FN_IRQ31_PORT41,   GPIO_FN_IRQ31_PORT167,
-
-        /* Function */
-
-        /* DBGT */
-        GPIO_FN_DBGMDT2,        GPIO_FN_DBGMDT1,        GPIO_FN_DBGMDT0,
-        GPIO_FN_DBGMD10,        GPIO_FN_DBGMD11,        GPIO_FN_DBGMD20,
-        GPIO_FN_DBGMD21,
-
-        /* FSI-A */
-        GPIO_FN_FSIAISLD_PORT0,         /* FSIAISLD Port 0/5 */
-        GPIO_FN_FSIAISLD_PORT5,
-        GPIO_FN_FSIASPDIF_PORT9,        /* FSIASPDIF Port 9/18 */
-        GPIO_FN_FSIASPDIF_PORT18,
-        GPIO_FN_FSIAOSLD1,      GPIO_FN_FSIAOSLD2,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIACK,         GPIO_FN_FSIAILR,
-        GPIO_FN_FSIAIBT,
-
-        /* FSI-B */
-        GPIO_FN_FSIBCK,
-
-        /* FMSI */
-        GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
-        GPIO_FN_FMSISLD_PORT6,
-        GPIO_FN_FMSIILR,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSIOBT,
-        GPIO_FN_FMSICK,         GPIO_FN_FMSOILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSOOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOCK,
-
-        /* SCIFA0 */
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_CTS,
-        GPIO_FN_SCIFA0_RTS,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_TXD,
-
-        /* SCIFA1 */
-        GPIO_FN_SCIFA1_CTS,     GPIO_FN_SCIFA1_SCK,
-        GPIO_FN_SCIFA1_RXD,     GPIO_FN_SCIFA1_TXD,
-        GPIO_FN_SCIFA1_RTS,
-
-        /* SCIFA2 */
-        GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN_SCIFA2_SCK_PORT199,
-        GPIO_FN_SCIFA2_RXD,     GPIO_FN_SCIFA2_TXD,
-        GPIO_FN_SCIFA2_CTS,     GPIO_FN_SCIFA2_RTS,
-
-        /* SCIFA3 */
-        GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
-        GPIO_FN_SCIFA3_SCK_PORT116,
-        GPIO_FN_SCIFA3_CTS_PORT117,
-        GPIO_FN_SCIFA3_RXD_PORT174,
-        GPIO_FN_SCIFA3_TXD_PORT175,
-
-        GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
-        GPIO_FN_SCIFA3_SCK_PORT158,
-        GPIO_FN_SCIFA3_CTS_PORT162,
-        GPIO_FN_SCIFA3_RXD_PORT159,
-        GPIO_FN_SCIFA3_TXD_PORT160,
-
-        /* SCIFA4 */
-        GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
-        GPIO_FN_SCIFA4_TXD_PORT13,
-
-        GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
-        GPIO_FN_SCIFA4_TXD_PORT203,
-
-        GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
-        GPIO_FN_SCIFA4_TXD_PORT93,
-
-        GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN_SCIFA4_SCK_PORT205,
-
-        /* SCIFA5 */
-        GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
-        GPIO_FN_SCIFA5_RXD_PORT10,
-
-        GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
-        GPIO_FN_SCIFA5_TXD_PORT208,
-
-        GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
-        GPIO_FN_SCIFA5_RXD_PORT92,
-
-        GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN_SCIFA5_SCK_PORT206,
-
-        /* SCIFA6 */
-        GPIO_FN_SCIFA6_SCK,     GPIO_FN_SCIFA6_RXD,     GPIO_FN_SCIFA6_TXD,
-
-        /* SCIFA7 */
-        GPIO_FN_SCIFA7_TXD,     GPIO_FN_SCIFA7_RXD,
-
-        /* SCIFAB */
-        GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
-        GPIO_FN_SCIFB_RXD_PORT191,
-        GPIO_FN_SCIFB_TXD_PORT192,
-        GPIO_FN_SCIFB_RTS_PORT186,
-        GPIO_FN_SCIFB_CTS_PORT187,
-
-        GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
-        GPIO_FN_SCIFB_RXD_PORT3,
-        GPIO_FN_SCIFB_TXD_PORT4,
-        GPIO_FN_SCIFB_RTS_PORT172,
-        GPIO_FN_SCIFB_CTS_PORT173,
-
-        /* LCD0 */
-        GPIO_FN_LCDC0_SELECT,
-
-        /* LCD1 */
-        GPIO_FN_LCDC1_SELECT,
-
-        /* RSPI */
-        GPIO_FN_RSPI_SSL0_A,    GPIO_FN_RSPI_SSL1_A,
-        GPIO_FN_RSPI_SSL2_A,    GPIO_FN_RSPI_SSL3_A,
-        GPIO_FN_RSPI_MOSI_A,    GPIO_FN_RSPI_MISO_A,
-        GPIO_FN_RSPI_CK_A,
-
-        /* VIO CKO */
-        GPIO_FN_VIO_CKO1,
-        GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_CKO_1,
-        GPIO_FN_VIO_CKO,
-
-        /* VIO0 */
-        GPIO_FN_VIO0_D0,        GPIO_FN_VIO0_D1,        GPIO_FN_VIO0_D2,
-        GPIO_FN_VIO0_D3,        GPIO_FN_VIO0_D4,        GPIO_FN_VIO0_D5,
-        GPIO_FN_VIO0_D6,        GPIO_FN_VIO0_D7,        GPIO_FN_VIO0_D8,
-        GPIO_FN_VIO0_D9,        GPIO_FN_VIO0_D10,       GPIO_FN_VIO0_D11,
-        GPIO_FN_VIO0_D12,       GPIO_FN_VIO0_VD,        GPIO_FN_VIO0_HD,
-        GPIO_FN_VIO0_CLK,       GPIO_FN_VIO0_FIELD,
-
-        GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
-        GPIO_FN_VIO0_D14_PORT25,
-        GPIO_FN_VIO0_D15_PORT24,
-
-        GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
-        GPIO_FN_VIO0_D14_PORT95,
-        GPIO_FN_VIO0_D15_PORT96,
-
-        /* VIO1 */
-        GPIO_FN_VIO1_D0,        GPIO_FN_VIO1_D1,        GPIO_FN_VIO1_D2,
-        GPIO_FN_VIO1_D3,        GPIO_FN_VIO1_D4,        GPIO_FN_VIO1_D5,
-        GPIO_FN_VIO1_D6,        GPIO_FN_VIO1_D7,        GPIO_FN_VIO1_VD,
-        GPIO_FN_VIO1_HD,        GPIO_FN_VIO1_CLK,       GPIO_FN_VIO1_FIELD,
-
-        /* TPU0 */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO3,
-        GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
-        GPIO_FN_TPU0TO2_PORT202,
-
-        /* SSP1 0 */
-        GPIO_FN_STP0_IPD0,      GPIO_FN_STP0_IPD1,      GPIO_FN_STP0_IPD2,
-        GPIO_FN_STP0_IPD3,      GPIO_FN_STP0_IPD4,      GPIO_FN_STP0_IPD5,
-        GPIO_FN_STP0_IPD6,      GPIO_FN_STP0_IPD7,      GPIO_FN_STP0_IPEN,
-        GPIO_FN_STP0_IPCLK,     GPIO_FN_STP0_IPSYNC,
-
-        /* SSP1 1 */
-        GPIO_FN_STP1_IPD1,      GPIO_FN_STP1_IPD2,      GPIO_FN_STP1_IPD3,
-        GPIO_FN_STP1_IPD4,      GPIO_FN_STP1_IPD5,      GPIO_FN_STP1_IPD6,
-        GPIO_FN_STP1_IPD7,      GPIO_FN_STP1_IPCLK,     GPIO_FN_STP1_IPSYNC,
-
-        GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
-        GPIO_FN_STP1_IPEN_PORT187,
-
-        GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
-        GPIO_FN_STP1_IPEN_PORT193,
-
-        /* SIM */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,
-        GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
-        GPIO_FN_SIM_D_PORT199,
-
-        /* MSIOF2 */
-        GPIO_FN_MSIOF2_TXD,     GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_SS2,     GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_SS1,
-        GPIO_FN_MSIOF2_MCK1,    GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_RSCK,
-
-        /* KEYSC */
-        GPIO_FN_KEYIN4,         GPIO_FN_KEYIN5,
-        GPIO_FN_KEYIN6,         GPIO_FN_KEYIN7,
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYOUT1,        GPIO_FN_KEYOUT2,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYOUT4,        GPIO_FN_KEYOUT5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYOUT7,
-
-        GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
-        GPIO_FN_KEYIN1_PORT44,
-        GPIO_FN_KEYIN2_PORT45,
-        GPIO_FN_KEYIN3_PORT46,
-
-        GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
-        GPIO_FN_KEYIN1_PORT57,
-        GPIO_FN_KEYIN2_PORT56,
-        GPIO_FN_KEYIN3_PORT55,
-
-        /* VOU */
-        GPIO_FN_DV_D0,  GPIO_FN_DV_D1,  GPIO_FN_DV_D2,  GPIO_FN_DV_D3,
-        GPIO_FN_DV_D4,  GPIO_FN_DV_D5,  GPIO_FN_DV_D6,  GPIO_FN_DV_D7,
-        GPIO_FN_DV_D8,  GPIO_FN_DV_D9,  GPIO_FN_DV_D10, GPIO_FN_DV_D11,
-        GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
-        GPIO_FN_DV_CLK,
-        GPIO_FN_DV_VSYNC,
-        GPIO_FN_DV_HSYNC,
-
-        /* MEMC */
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,      GPIO_FN_MEMC_CS0,       GPIO_FN_MEMC_INT,
-        GPIO_FN_MEMC_NWE,       GPIO_FN_MEMC_NOE,
-
-        GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
-        GPIO_FN_MEMC_ADV,
-        GPIO_FN_MEMC_WAIT,
-        GPIO_FN_MEMC_BUSCLK,
-
-        GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
-        GPIO_FN_MEMC_DREQ0,
-        GPIO_FN_MEMC_DREQ1,
-        GPIO_FN_MEMC_A0,
-
-        /* MSIOF0 */
-        GPIO_FN_MSIOF0_SS1,     GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_MSIOF0_MCK0,    GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_TSCK,    GPIO_FN_MSIOF0_TSYNC,
-
-        /* MSIOF1 */
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-
-        GPIO_FN_MSIOF1_SS2_PORT116,     GPIO_FN_MSIOF1_SS1_PORT117,
-        GPIO_FN_MSIOF1_RXD_PORT118,     GPIO_FN_MSIOF1_TXD_PORT119,
-        GPIO_FN_MSIOF1_TSYNC_PORT120,
-        GPIO_FN_MSIOF1_TSCK_PORT121,    /* MSEL4CR_10_0 */
-
-        GPIO_FN_MSIOF1_SS1_PORT67,      GPIO_FN_MSIOF1_TSCK_PORT72,
-        GPIO_FN_MSIOF1_TSYNC_PORT73,    GPIO_FN_MSIOF1_TXD_PORT74,
-        GPIO_FN_MSIOF1_RXD_PORT75,
-        GPIO_FN_MSIOF1_SS2_PORT202,     /* MSEL4CR_10_1 */
-
-        /* GPIO */
-        GPIO_FN_GPO0,   GPIO_FN_GPI0,
-        GPIO_FN_GPO1,   GPIO_FN_GPI1,
-
-        /* USB0 */
-        GPIO_FN_USB0_OCI,       GPIO_FN_USB0_PPON,      GPIO_FN_VBUS,
-
-        /* USB1 */
-        GPIO_FN_USB1_OCI,       GPIO_FN_USB1_PPON,
-
-        /* BBIF1 */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BBIF1_RX_FLOW_N,
-
-        /* BBIF2 */
-        GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
-        GPIO_FN_BBIF2_RXD2_PORT60,
-        GPIO_FN_BBIF2_TSYNC2_PORT6,
-        GPIO_FN_BBIF2_TSCK2_PORT59,
-
-        GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
-        GPIO_FN_BBIF2_TXD2_PORT183,
-        GPIO_FN_BBIF2_TSCK2_PORT89,
-        GPIO_FN_BBIF2_TSYNC2_PORT184,
-
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5B,   GPIO_FN_CS6A,
-        GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
-        GPIO_FN_CS5A_PORT19,
-        GPIO_FN_IOIS16, /* ? */
-
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A4_FOE,         /* share with FLCTL */
-        GPIO_FN_A5_FCDE,        /* share with FLCTL */
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        /* share with FLCTL */
-        GPIO_FN_D2_NAF2,        GPIO_FN_D3_NAF3,        /* share with FLCTL */
-        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,        /* share with FLCTL */
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        /* share with FLCTL */
-        GPIO_FN_D8_NAF8,        GPIO_FN_D9_NAF9,        /* share with FLCTL */
-        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,      /* share with FLCTL */
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      /* share with FLCTL */
-        GPIO_FN_D14_NAF14,      GPIO_FN_D15_NAF15,      /* share with FLCTL */
-
-        GPIO_FN_D16,    GPIO_FN_D17,    GPIO_FN_D18,    GPIO_FN_D19,
-        GPIO_FN_D20,    GPIO_FN_D21,    GPIO_FN_D22,    GPIO_FN_D23,
-        GPIO_FN_D24,    GPIO_FN_D25,    GPIO_FN_D26,    GPIO_FN_D27,
-        GPIO_FN_D28,    GPIO_FN_D29,    GPIO_FN_D30,    GPIO_FN_D31,
-
-        GPIO_FN_WE0_FWE,        /* share with FLCTL */
-        GPIO_FN_WE1,
-        GPIO_FN_WE2_ICIORD,     /* share with PCMCIA */
-        GPIO_FN_WE3_ICIOWR,     /* share with PCMCIA */
-        GPIO_FN_CKO,    GPIO_FN_BS,     GPIO_FN_RDWR,
-        GPIO_FN_RD_FSC,         /* share with FLCTL */
-        GPIO_FN_WAIT_PORT177,   /* WAIT Port 90/177 */
-        GPIO_FN_WAIT_PORT90,
-
-        GPIO_FN_FCE0,   GPIO_FN_FCE1,   GPIO_FN_FRB, /* FLCTL */
-
-        /* IRDA */
-        GPIO_FN_IRDA_FIRSEL,    GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_OUT,
-
-        /* ATAPI */
-        GPIO_FN_IDE_D0,         GPIO_FN_IDE_D1,         GPIO_FN_IDE_D2,
-        GPIO_FN_IDE_D3,         GPIO_FN_IDE_D4,         GPIO_FN_IDE_D5,
-        GPIO_FN_IDE_D6,         GPIO_FN_IDE_D7,         GPIO_FN_IDE_D8,
-        GPIO_FN_IDE_D9,         GPIO_FN_IDE_D10,        GPIO_FN_IDE_D11,
-        GPIO_FN_IDE_D12,        GPIO_FN_IDE_D13,        GPIO_FN_IDE_D14,
-        GPIO_FN_IDE_D15,        GPIO_FN_IDE_A0,         GPIO_FN_IDE_A1,
-        GPIO_FN_IDE_A2,         GPIO_FN_IDE_CS0,        GPIO_FN_IDE_CS1,
-        GPIO_FN_IDE_IOWR,       GPIO_FN_IDE_IORD,       GPIO_FN_IDE_IORDY,
-        GPIO_FN_IDE_INT,        GPIO_FN_IDE_RST,        GPIO_FN_IDE_DIRECTION,
-        GPIO_FN_IDE_EXBUF_ENB,  GPIO_FN_IDE_IODACK,     GPIO_FN_IDE_IODREQ,
-
-        /* RMII */
-        GPIO_FN_RMII_CRS_DV,    GPIO_FN_RMII_RX_ER,     GPIO_FN_RMII_RXD0,
-        GPIO_FN_RMII_RXD1,      GPIO_FN_RMII_TX_EN,     GPIO_FN_RMII_TXD0,
-        GPIO_FN_RMII_MDC,       GPIO_FN_RMII_TXD1,      GPIO_FN_RMII_MDIO,
-        GPIO_FN_RMII_REF50CK,   /* for RMII */
-        GPIO_FN_RMII_REF125CK,  /* for GMII */
-
-        /* GEther */
-        GPIO_FN_ET_TX_CLK,      GPIO_FN_ET_TX_EN,       GPIO_FN_ET_ETXD0,
-        GPIO_FN_ET_ETXD1,       GPIO_FN_ET_ETXD2,       GPIO_FN_ET_ETXD3,
-        GPIO_FN_ET_ETXD4,       GPIO_FN_ET_ETXD5, /* for GEther */
-        GPIO_FN_ET_ETXD6,       GPIO_FN_ET_ETXD7, /* for GEther */
-        GPIO_FN_ET_COL,         GPIO_FN_ET_TX_ER,
-        GPIO_FN_ET_RX_CLK,      GPIO_FN_ET_RX_DV,
-        GPIO_FN_ET_ERXD0,       GPIO_FN_ET_ERXD1,
-        GPIO_FN_ET_ERXD2,       GPIO_FN_ET_ERXD3,
-        GPIO_FN_ET_ERXD4,       GPIO_FN_ET_ERXD5, /* for GEther */
-        GPIO_FN_ET_ERXD6,       GPIO_FN_ET_ERXD7, /* for GEther */
-        GPIO_FN_ET_RX_ER,       GPIO_FN_ET_CRS,
-        GPIO_FN_ET_MDC,         GPIO_FN_ET_MDIO,
-        GPIO_FN_ET_LINK,        GPIO_FN_ET_PHY_INT,
-        GPIO_FN_ET_WOL,         GPIO_FN_ET_GTX_CLK,
-
-        /* DMA0 */
-        GPIO_FN_DREQ0,          GPIO_FN_DACK0,
-
-        /* DMA1 */
-        GPIO_FN_DREQ1,          GPIO_FN_DACK1,
-
-        /* SYSC */
-        GPIO_FN_RESETOUTS,
-        GPIO_FN_RESETP_PULLUP,
-        GPIO_FN_RESETP_PLAIN,
-
-        /* HDMI */
-        GPIO_FN_HDMI_HPD,
-        GPIO_FN_HDMI_CEC,
-
-        /* SDENC */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-
-        /* IRREM */
-        GPIO_FN_IROUT,
-
-        /* DEBUG */
-        GPIO_FN_EDEBGREQ_PULLDOWN,
-        GPIO_FN_EDEBGREQ_PULLUP,
-
-        GPIO_FN_TRACEAUD_FROM_VIO,
-        GPIO_FN_TRACEAUD_FROM_LCDC0,
-        GPIO_FN_TRACEAUD_FROM_MEMC,
-};
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 951149e6bcca..ae65b459483f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -18,6 +18,7 @@
 #ifndef __ASM_R8A7778_H__
 #define __ASM_R8A7778_H__
 
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/sh_eth.h>
 
 extern void r8a7778_add_standard_devices(void);
@@ -28,5 +29,7 @@ extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
+extern void r8a7778_pinmux_init(void);
+extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info);
 
 #endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index fd7cba024c39..e882717ca97f 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -15,397 +15,6 @@
 #include <linux/pm_domain.h>
 #include <mach/pm-rmobile.h>
 
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-        GPIO_PORT190,
-
-        /* IRQ */
-        GPIO_FN_IRQ0_6,         /* PORT   6 */
-        GPIO_FN_IRQ0_162,       /* PORT 162 */
-        GPIO_FN_IRQ1,           /* PORT  12 */
-        GPIO_FN_IRQ2_4,         /* PORT   4 */
-        GPIO_FN_IRQ2_5,         /* PORT   5 */
-        GPIO_FN_IRQ3_8,         /* PORT   8 */
-        GPIO_FN_IRQ3_16,        /* PORT  16 */
-        GPIO_FN_IRQ4_17,        /* PORT  17 */
-        GPIO_FN_IRQ4_163,       /* PORT 163 */
-        GPIO_FN_IRQ5,           /* PORT  18 */
-        GPIO_FN_IRQ6_39,        /* PORT  39 */
-        GPIO_FN_IRQ6_164,       /* PORT 164 */
-        GPIO_FN_IRQ7_40,        /* PORT  40 */
-        GPIO_FN_IRQ7_167,       /* PORT 167 */
-        GPIO_FN_IRQ8_41,        /* PORT  41 */
-        GPIO_FN_IRQ8_168,       /* PORT 168 */
-        GPIO_FN_IRQ9_42,        /* PORT  42 */
-        GPIO_FN_IRQ9_169,       /* PORT 169 */
-        GPIO_FN_IRQ10,          /* PORT  65 */
-        GPIO_FN_IRQ11,          /* PORT  67 */
-        GPIO_FN_IRQ12_80,       /* PORT  80 */
-        GPIO_FN_IRQ12_137,      /* PORT 137 */
-        GPIO_FN_IRQ13_81,       /* PORT  81 */
-        GPIO_FN_IRQ13_145,      /* PORT 145 */
-        GPIO_FN_IRQ14_82,       /* PORT  82 */
-        GPIO_FN_IRQ14_146,      /* PORT 146 */
-        GPIO_FN_IRQ15_83,       /* PORT  83 */
-        GPIO_FN_IRQ15_147,      /* PORT 147 */
-        GPIO_FN_IRQ16_84,       /* PORT  84 */
-        GPIO_FN_IRQ16_170,      /* PORT 170 */
-        GPIO_FN_IRQ17,          /* PORT  85 */
-        GPIO_FN_IRQ18,          /* PORT  86 */
-        GPIO_FN_IRQ19,          /* PORT  87 */
-        GPIO_FN_IRQ20,          /* PORT  92 */
-        GPIO_FN_IRQ21,          /* PORT  93 */
-        GPIO_FN_IRQ22,          /* PORT  94 */
-        GPIO_FN_IRQ23,          /* PORT  95 */
-        GPIO_FN_IRQ24,          /* PORT 112 */
-        GPIO_FN_IRQ25,          /* PORT 119 */
-        GPIO_FN_IRQ26_121,      /* PORT 121 */
-        GPIO_FN_IRQ26_172,      /* PORT 172 */
-        GPIO_FN_IRQ27_122,      /* PORT 122 */
-        GPIO_FN_IRQ27_180,      /* PORT 180 */
-        GPIO_FN_IRQ28_123,      /* PORT 123 */
-        GPIO_FN_IRQ28_181,      /* PORT 181 */
-        GPIO_FN_IRQ29_129,      /* PORT 129 */
-        GPIO_FN_IRQ29_182,      /* PORT 182 */
-        GPIO_FN_IRQ30_130,      /* PORT 130 */
-        GPIO_FN_IRQ30_183,      /* PORT 183 */
-        GPIO_FN_IRQ31_138,      /* PORT 138 */
-        GPIO_FN_IRQ31_184,      /* PORT 184 */
-
-        /*
-         * MSIOF0       (PORT 36, 37, 38, 39
-         *                    40, 41, 42, 43, 44, 45)
-         */
-        GPIO_FN_MSIOF0_TSYNC,   GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_MSIOF0_MCK1,    GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_MSIOF0_SS2,     GPIO_FN_MSIOF0_TXD,
-
-        /*
-         * MSIOF1       (PORT 39, 40, 41, 42, 43, 44
-         *                    84, 85, 86, 87, 88, 89, 90, 91, 92, 93)
-         */
-        GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40,
-        GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89,
-        GPIO_FN_MSIOF1_TXD_41,  GPIO_FN_MSIOF1_RXD_42,
-        GPIO_FN_MSIOF1_TXD_90,  GPIO_FN_MSIOF1_RXD_91,
-        GPIO_FN_MSIOF1_SS1_43,  GPIO_FN_MSIOF1_SS2_44,
-        GPIO_FN_MSIOF1_SS1_92,  GPIO_FN_MSIOF1_SS2_93,
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-
-        /*
-         * MSIOF2       (PORT 134, 135, 136, 137, 138, 139
-         *                    148, 149, 150, 151)
-         */
-        GPIO_FN_MSIOF2_RSCK,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_MSIOF2_SS1,     GPIO_FN_MSIOF2_SS2,
-        GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TXD,
-
-        /* MSIOF3       (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_TXD,
-        GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BB_RX_FLOW_N,
-
-        /* MSIOF4       (PORT 0, 1, 2, 3) */
-        GPIO_FN_BBIF2_TSCK1,    GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_BBIF2_TXD1,     GPIO_FN_BBIF2_RXD,
-
-        /* FSI          (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */
-        GPIO_FN_FSIACK,         GPIO_FN_FSIBCK,
-        GPIO_FN_FSIAILR,        GPIO_FN_FSIAIBT,
-        GPIO_FN_FSIAISLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIASPDIF_11,
-        GPIO_FN_FSIASPDIF_15,
-
-        /* FMSI         (PORT 12, 13, 14, 15, 16, 17, 18, 65) */
-        GPIO_FN_FMSOCK,         GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSOOBT,
-        GPIO_FN_FMSIOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOILR,        GPIO_FN_FMSIILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSISLD,        GPIO_FN_FMSICK,
-
-        /* SCIFA0       (PORT 152, 153, 156, 157, 158) */
-        GPIO_FN_SCIFA0_TXD,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_RTS,
-        GPIO_FN_SCIFA0_CTS,
-
-        /* SCIFA1       (PORT 154, 155, 159, 160, 161) */
-        GPIO_FN_SCIFA1_TXD,     GPIO_FN_SCIFA1_RXD,
-        GPIO_FN_SCIFA1_SCK,     GPIO_FN_SCIFA1_RTS,
-        GPIO_FN_SCIFA1_CTS,
-
-        /* SCIFA2       (PORT 94, 95, 96, 97, 98) */
-        GPIO_FN_SCIFA2_CTS1,    GPIO_FN_SCIFA2_RTS1,
-        GPIO_FN_SCIFA2_TXD1,    GPIO_FN_SCIFA2_RXD1,
-        GPIO_FN_SCIFA2_SCK1,
-
-        /* SCIFA3       (PORT 43, 44,
-                             140, 141, 142, 143, 144) */
-        GPIO_FN_SCIFA3_CTS_43,  GPIO_FN_SCIFA3_CTS_140,
-        GPIO_FN_SCIFA3_RTS_44,  GPIO_FN_SCIFA3_RTS_141,
-        GPIO_FN_SCIFA3_SCK,     GPIO_FN_SCIFA3_TXD,
-        GPIO_FN_SCIFA3_RXD,
-
-        /* SCIFA4       (PORT 5, 6) */
-        GPIO_FN_SCIFA4_RXD,     GPIO_FN_SCIFA4_TXD,
-
-        /* SCIFA5       (PORT 8, 12) */
-        GPIO_FN_SCIFA5_RXD,     GPIO_FN_SCIFA5_TXD,
-
-        /* SCIFB        (PORT 162, 163, 164, 165, 166) */
-        GPIO_FN_SCIFB_SCK,      GPIO_FN_SCIFB_RTS,
-        GPIO_FN_SCIFB_CTS,      GPIO_FN_SCIFB_TXD,
-        GPIO_FN_SCIFB_RXD,
-
-        /*
-         * CEU          (PORT 16, 17,
-         *                    100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
-         *                    110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
-         *                    120)
-         */
-        GPIO_FN_VIO_HD,         GPIO_FN_VIO_CKO1,       GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_VD,         GPIO_FN_VIO_CLK,        GPIO_FN_VIO_FIELD,
-        GPIO_FN_VIO_CKO,
-        GPIO_FN_VIO_D0,         GPIO_FN_VIO_D1,         GPIO_FN_VIO_D2,
-        GPIO_FN_VIO_D3,         GPIO_FN_VIO_D4,         GPIO_FN_VIO_D5,
-        GPIO_FN_VIO_D6,         GPIO_FN_VIO_D7,         GPIO_FN_VIO_D8,
-        GPIO_FN_VIO_D9,         GPIO_FN_VIO_D10,        GPIO_FN_VIO_D11,
-        GPIO_FN_VIO_D12,        GPIO_FN_VIO_D13,        GPIO_FN_VIO_D14,
-        GPIO_FN_VIO_D15,
-
-        /* USB0         (PORT 113, 114, 115, 116, 117, 167) */
-        GPIO_FN_IDIN_0,         GPIO_FN_EXTLP_0,
-        GPIO_FN_OVCN2_0,        GPIO_FN_PWEN_0,
-        GPIO_FN_OVCN_0,         GPIO_FN_VBUS0_0,
-
-        /* USB1         (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */
-        GPIO_FN_IDIN_1_18,      GPIO_FN_IDIN_1_113,
-        GPIO_FN_PWEN_1_115,     GPIO_FN_PWEN_1_138,
-        GPIO_FN_OVCN_1_114,     GPIO_FN_OVCN_1_162,
-        GPIO_FN_EXTLP_1,        GPIO_FN_OVCN2_1,
-        GPIO_FN_VBUS0_1,
-
-        /* GPIO         (PORT 41, 42, 43, 44) */
-        GPIO_FN_GPI0,   GPIO_FN_GPI1,   GPIO_FN_GPO0,   GPIO_FN_GPO1,
-
-        /*
-         * BSC          (PORT 19,
-         *                    20, 21, 22, 25, 26, 27, 28, 29,
-         *                    30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
-         *                    40, 41, 42, 43, 44, 45,
-         *                    62, 63, 64, 65, 66, 67,
-         *                    71, 72, 74, 75)
-         */
-        GPIO_FN_BS,     GPIO_FN_WE1,
-        GPIO_FN_CKO,    GPIO_FN_WAIT,   GPIO_FN_RDWR,
-
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5A,   GPIO_FN_CS5B,   GPIO_FN_CS6A,
-
-        /*
-         * BSC/FLCTL            (PORT 23, 24,
-         *                            46, 47, 48, 49,
-         *                            50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
-         *                            60, 61, 69, 70)
-         */
-        GPIO_FN_RD_FSC,         GPIO_FN_WE0_FWE,
-        GPIO_FN_A4_FOE,         GPIO_FN_A5_FCDE,
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        GPIO_FN_D2_NAF2,
-        GPIO_FN_D3_NAF3,        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        GPIO_FN_D8_NAF8,
-        GPIO_FN_D9_NAF9,        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      GPIO_FN_D14_NAF14,
-        GPIO_FN_D15_NAF15,
-
-        /* SPU2         (PORT 65) */
-        GPIO_FN_VINT_I,
-
-        /* FLCTL        (PORT 66, 68, 73) */
-        GPIO_FN_FCE1,   GPIO_FN_FCE0,   GPIO_FN_FRB,
-
-        /* HSI          (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_GP_RX_FLAG,     GPIO_FN_GP_RX_DATA,     GPIO_FN_GP_TX_READY,
-        GPIO_FN_GP_RX_WAKE,     GPIO_FN_MP_TX_FLAG,     GPIO_FN_MP_TX_DATA,
-        GPIO_FN_MP_RX_READY,    GPIO_FN_MP_TX_WAKE,
-
-        /*
-         * MFI          (PORT 76, 77, 78, 79,
-         *                    80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
-         *                    90, 91, 92, 93, 94, 95, 96, 97, 98, 99)
-         */
-        GPIO_FN_MFIv6,  /* see MSEL4CR 6 */
-        GPIO_FN_MFIv4,  /* see MSEL4CR 6 */
-
-        GPIO_FN_MEMC_CS0,               GPIO_FN_MEMC_BUSCLK_MEMC_A0,
-        GPIO_FN_MEMC_CS1_MEMC_A1,       GPIO_FN_MEMC_ADV_MEMC_DREQ0,
-        GPIO_FN_MEMC_WAIT_MEMC_DREQ1,   GPIO_FN_MEMC_NOE,
-        GPIO_FN_MEMC_NWE,               GPIO_FN_MEMC_INT,
-
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,
-
-        /* SIM          (PORT 94, 95, 98) */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,        GPIO_FN_SIM_D,
-
-        /* TPU          (PORT 93, 99, 112, 160, 161) */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO2_93,     GPIO_FN_TPU0TO2_99,
-        GPIO_FN_TPU0TO3,
-
-        /* I2C2         (PORT 110, 111) */
-        GPIO_FN_I2C_SCL2,       GPIO_FN_I2C_SDA2,
-
-        /* I2C3(1)      (PORT 114, 115) */
-        GPIO_FN_I2C_SCL3,       GPIO_FN_I2C_SDA3,
-
-        /* I2C3(2)      (PORT 137, 145) */
-        GPIO_FN_I2C_SCL3S,      GPIO_FN_I2C_SDA3S,
-
-        /* I2C4(2)      (PORT 116, 117) */
-        GPIO_FN_I2C_SCL4,       GPIO_FN_I2C_SDA4,
-
-        /* I2C4(2)      (PORT 146, 147) */
-        GPIO_FN_I2C_SCL4S,      GPIO_FN_I2C_SDA4S,
-
-        /*
-         * KEYSC        (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136)
-         */
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYIN0_121,     GPIO_FN_KEYIN0_136,
-        GPIO_FN_KEYOUT1,        GPIO_FN_KEYIN1_122,     GPIO_FN_KEYIN1_135,
-        GPIO_FN_KEYOUT2,        GPIO_FN_KEYIN2_123,     GPIO_FN_KEYIN2_134,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYIN3_124,     GPIO_FN_KEYIN3_133,
-        GPIO_FN_KEYOUT4,        GPIO_FN_KEYIN4,
-        GPIO_FN_KEYOUT5,        GPIO_FN_KEYIN5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYIN6,
-        GPIO_FN_KEYOUT7,        GPIO_FN_KEYIN7,
-
-        /*
-         * LCDC         (PORT      121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136, 137, 138, 139,
-         *                    140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
-         *                    150, 151)
-         */
-        GPIO_FN_LCDC0_SELECT, /* LCDC 0 */
-        GPIO_FN_LCDC1_SELECT, /* LCDC 1 */
-        GPIO_FN_LCDHSYN,        GPIO_FN_LCDCS,  GPIO_FN_LCDVSYN,
-        GPIO_FN_LCDDCK,         GPIO_FN_LCDWR,  GPIO_FN_LCDRD,
-        GPIO_FN_LCDDISP,        GPIO_FN_LCDRS,  GPIO_FN_LCDLCLK,
-        GPIO_FN_LCDDON,
-
-        GPIO_FN_LCDD0,  GPIO_FN_LCDD1,  GPIO_FN_LCDD2,  GPIO_FN_LCDD3,
-        GPIO_FN_LCDD4,  GPIO_FN_LCDD5,  GPIO_FN_LCDD6,  GPIO_FN_LCDD7,
-        GPIO_FN_LCDD8,  GPIO_FN_LCDD9,  GPIO_FN_LCDD10, GPIO_FN_LCDD11,
-        GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15,
-        GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19,
-        GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23,
-
-        /* IRDA         (PORT 139, 140, 141, 142) */
-        GPIO_FN_IRDA_OUT,       GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_FIRSEL,
-        GPIO_FN_IROUT_139,      GPIO_FN_IROUT_140,
-
-        /* TSIF1        (PORT 156, 157, 158, 159) */
-        GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */
-        GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */
-        GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */
-        GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */
-
-        GPIO_FN_TS_SPSYNC1,     GPIO_FN_TS_SDAT1,
-        GPIO_FN_TS_SDEN1,       GPIO_FN_TS_SCK1,
-
-        /* TSIF2        (PORT 137, 145, 146, 147) */
-        GPIO_FN_TS_SPSYNC2,     GPIO_FN_TS_SDAT2,
-        GPIO_FN_TS_SDEN2,       GPIO_FN_TS_SCK2,
-
-        /* HDMI         (PORT 169, 170) */
-        GPIO_FN_HDMI_HPD,       GPIO_FN_HDMI_CEC,
-
-        /* SDENC        see MSEL4CR 19 */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-};
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 326a4ab0bd5f..3a6b6fe7b6c0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -70,29 +70,15 @@ void __init r8a7740_map_io(void)
 }
 
 /* PFC */
-static struct resource r8a7740_pfc_resources[] = {
-        [0] = {
-                .start  = 0xe6050000,
-                .end    = 0xe6057fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xe605800c,
-                .end    = 0xe605802b,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device r8a7740_pfc_device = {
-        .name           = "pfc-r8a7740",
-        .id             = -1,
-        .resource       = r8a7740_pfc_resources,
-        .num_resources  = ARRAY_SIZE(r8a7740_pfc_resources),
+static const struct resource pfc_resources[] = {
+        DEFINE_RES_MEM(0xe6050000, 0x8000),
+        DEFINE_RES_MEM(0xe605800c, 0x0020),
 };
 
 void __init r8a7740_pinmux_init(void)
 {
-        platform_device_register(&r8a7740_pfc_device);
+        platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
+                                        ARRAY_SIZE(pfc_resources));
 }
 
 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 30b4a336308f..1b9b7f2a5016 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -24,6 +24,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/platform_device.h>
 #include <linux/irqchip.h>
@@ -80,12 +81,6 @@ static struct sh_timer_config sh_tmu1_platform_data = {
         .clocksource_rating     = 200,
 };
 
-/* Ether */
-static struct resource ether_resources[] = {
-        DEFINE_RES_MEM(0xfde00000, 0x400),
-        DEFINE_RES_IRQ(gic_iid(0x89)),
-};
-
 #define r8a7778_register_tmu(idx)                       \
         platform_device_register_resndata(              \
                 &platform_bus, "sh_tmu", idx,           \
@@ -94,6 +89,90 @@ static struct resource ether_resources[] = {
                 &sh_tmu##idx##_platform_data,           \
                 sizeof(sh_tmu##idx##_platform_data))
 
+/* Ether */
+static struct resource ether_resources[] = {
+        DEFINE_RES_MEM(0xfde00000, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x89)),
+};
+
+void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
+                                          ether_resources,
+                                          ARRAY_SIZE(ether_resources),
+                                          pdata, sizeof(*pdata));
+}
+
+/* PFC/GPIO */
+static struct resource pfc_resources[] = {
+        DEFINE_RES_MEM(0xfffc0000, 0x118),
+};
+
+#define R8A7778_GPIO(idx)                                               \
+static struct resource r8a7778_gpio##idx##_resources[] = {              \
+        DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
+        DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = {    \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = GPIO_IRQ_BASE(idx),                           \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7778",                                \
+}
+
+R8A7778_GPIO(0);
+R8A7778_GPIO(1);
+R8A7778_GPIO(2);
+R8A7778_GPIO(3);
+R8A7778_GPIO(4);
+
+#define r8a7778_register_gpio(idx)                              \
+        platform_device_register_resndata(                      \
+                &platform_bus, "gpio_rcar", idx,                \
+                r8a7778_gpio##idx##_resources,                  \
+                ARRAY_SIZE(r8a7778_gpio##idx##_resources),      \
+                &r8a7778_gpio##idx##_platform_data,             \
+                sizeof(r8a7778_gpio##idx##_platform_data))
+
+void __init r8a7778_pinmux_init(void)
+{
+        platform_device_register_simple(
+                "pfc-r8a7778", -1,
+                pfc_resources,
+                ARRAY_SIZE(pfc_resources));
+
+        r8a7778_register_gpio(0);
+        r8a7778_register_gpio(1);
+        r8a7778_register_gpio(2);
+        r8a7778_register_gpio(3);
+        r8a7778_register_gpio(4);
+};
+
+/* SDHI */
+static struct resource sdhi_resources[] = {
+        /* SDHI0 */
+        DEFINE_RES_MEM(0xFFE4C000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x77)),
+        /* SDHI1 */
+        DEFINE_RES_MEM(0xFFE4D000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x78)),
+        /* SDHI2 */
+        DEFINE_RES_MEM(0xFFE4F000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x76)),
+};
+
+void __init r8a7778_sdhi_init(int id,
+                              struct sh_mobile_sdhi_info *info)
+{
+        BUG_ON(id < 0 || id > 2);
+
+        platform_device_register_resndata(
+                &platform_bus, "sh_mobile_sdhi", id,
+                sdhi_resources + (2 * id), 2,
+                info, sizeof(*info));
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
         int i;
@@ -118,14 +197,6 @@ void __init r8a7778_add_standard_devices(void)
         r8a7778_register_tmu(1);
 }
 
-void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
-{
-        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
-                                          ether_resources,
-                                          ARRAY_SIZE(ether_resources),
-                                          pdata, sizeof(*pdata));
-}
-
 static struct renesas_intc_irqpin_config irqpin_platform_data = {
         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
         .sense_bitfield_width = 2,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index b0b394842ea5..dbb13f289e79 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -65,11 +65,7 @@ void __init r8a7779_map_io(void)
 }
 
 static struct resource r8a7779_pfc_resources[] = {
-        [0] = {
-                .start  = 0xfffc0000,
-                .end    = 0xfffc023b,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM(0xfffc0000, 0x023c),
 };
 
 static struct platform_device r8a7779_pfc_device = {
@@ -81,15 +77,8 @@ static struct platform_device r8a7779_pfc_device = {
 
 #define R8A7779_GPIO(idx, npins) \
 static struct resource r8a7779_gpio##idx##_resources[] = {              \
-        [0] = {                                                         \
-                .start  = 0xffc40000 + 0x1000 * (idx),                  \
-                .end    = 0xffc4002b + 0x1000 * (idx),                  \
-                .flags  = IORESOURCE_MEM,                               \
-        },                                                              \
-        [1] = {                                                         \
-                .start  = gic_iid(0xad + (idx)),                        \
-                .flags  = IORESOURCE_IRQ,                               \
-        }                                                               \
+        DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
+        DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 };                                                                      \
                                                                         \
 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 49de2d56f86d..196bd7325df0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -23,21 +23,55 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7790.h>
 #include <asm/mach/arch.h>
 
-static const struct resource pfc_resources[] = {
+static struct resource pfc_resources[] __initdata = {
         DEFINE_RES_MEM(0xe6060000, 0x250),
-        DEFINE_RES_MEM(0xe6050000, 0x5050),
 };
 
+#define R8A7790_GPIO(idx)                                               \
+static struct resource r8a7790_gpio##idx##_resources[] __initdata = {   \
+        DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),              \
+        DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = 0,                                            \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7790",                                \
+        .has_both_edge_trigger = 1,                                     \
+};                                                                      \
+
+R8A7790_GPIO(0);
+R8A7790_GPIO(1);
+R8A7790_GPIO(2);
+R8A7790_GPIO(3);
+R8A7790_GPIO(4);
+R8A7790_GPIO(5);
+
+#define r8a7790_register_gpio(idx)                                      \
+        platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
+                r8a7790_gpio##idx##_resources,                          \
+                ARRAY_SIZE(r8a7790_gpio##idx##_resources),              \
+                &r8a7790_gpio##idx##_platform_data,                     \
+                sizeof(r8a7790_gpio##idx##_platform_data))
+
 void __init r8a7790_pinmux_init(void)
 {
         platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
                                         ARRAY_SIZE(pfc_resources));
+        r8a7790_register_gpio(0);
+        r8a7790_register_gpio(1);
+        r8a7790_register_gpio(2);
+        r8a7790_register_gpio(3);
+        r8a7790_register_gpio(4);
+        r8a7790_register_gpio(5);
 }
 
 #define SCIF_COMMON(scif_type, baseaddr, irq)                   \
@@ -69,7 +103,7 @@ void __init r8a7790_pinmux_init(void)
 
 enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
 
-static const struct plat_sci_port scif[] = {
+static struct plat_sci_port scif[] __initdata = {
         SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
         SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
         SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
@@ -86,11 +120,11 @@ static inline void r8a7790_register_scif(int idx)
                                       sizeof(struct plat_sci_port));
 }
 
-static struct renesas_irqc_config irqc0_data = {
+static struct renesas_irqc_config irqc0_data __initdata = {
         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 };
 
-static struct resource irqc0_resources[] = {
+static struct resource irqc0_resources[] __initdata = {
         DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
         DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 9696f3646864..96e7ca1e4e11 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = {
 };
 
 static struct resource tmu00_resources[] = {
-        [0] = {
-                .name   = "TMU00",
-                .start  = 0xfff60008,
-                .end    = 0xfff60013,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
         [1] = {
                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
                 .flags  = IORESOURCE_IRQ,
@@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = {
 };
 
 static struct resource tmu01_resources[] = {
-        [0] = {
-                .name   = "TMU01",
-                .start  = 0xfff60014,
-                .end    = 0xfff6001f,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
         [1] = {
                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
                 .flags  = IORESOURCE_IRQ,
@@ -341,12 +331,7 @@ static struct platform_device tmu01_device = {
 };
 
 static struct resource i2c0_resources[] = {
-        [0] = {
-                .name   = "IIC0",
-                .start  = 0xe6820000,
-                .end    = 0xe6820425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
         [1] = {
                 .start  = gic_spi(167),
                 .end    = gic_spi(170),
@@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = {
 };
 
 static struct resource i2c1_resources[] = {
-        [0] = {
-                .name   = "IIC1",
-                .start  = 0xe6822000,
-                .end    = 0xe6822425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
         [1] = {
                 .start  = gic_spi(51),
                 .end    = gic_spi(54),
@@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = {
 };
 
 static struct resource i2c2_resources[] = {
-        [0] = {
-                .name   = "IIC2",
-                .start  = 0xe6824000,
-                .end    = 0xe6824425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
         [1] = {
                 .start  = gic_spi(171),
                 .end    = gic_spi(174),
@@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = {
 };
 
 static struct resource i2c3_resources[] = {
-        [0] = {
-                .name   = "IIC3",
-                .start  = 0xe6826000,
-                .end    = 0xe6826425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
         [1] = {
                 .start  = gic_spi(183),
                 .end    = gic_spi(186),
@@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = {
 };
 
 static struct resource i2c4_resources[] = {
-        [0] = {
-                .name   = "IIC4",
-                .start  = 0xe6828000,
-                .end    = 0xe6828425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
         [1] = {
                 .start  = gic_spi(187),
                 .end    = gic_spi(190),
@@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 };
 
 static struct resource sh73a0_dmae_resources[] = {
-        {
-                /* Registers including DMAOR and channels including DMARSx */
-                .start  = 0xfe000020,
-                .end    = 0xfe008a00 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM(0xfe000020, 0x89e0),
         {
                 .name   = "error_irq",
                 .start  = gic_spi(129),
@@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 
 /* Resource order important! */
 static struct resource sh73a0_mpdma_resources[] = {
-        {
-                /* Channel registers and DMAOR */
-                .start  = 0xec618020,
-                .end    = 0xec61828f,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* DMARSx */
-                .start  = 0xec619000,
-                .end    = 0xec61900b,
-                .flags  = IORESOURCE_MEM,
-        },
+        /* Channel registers and DMAOR */
+        DEFINE_RES_MEM(0xec618020, 0x270),
+        /* DMARSx */
+        DEFINE_RES_MEM(0xec619000, 0xc),
         {
                 .name   = "error_irq",
                 .start  = gic_spi(181),
@@ -785,12 +737,7 @@ static struct platform_device pmu_device = {
 
 /* an IPMMU module for ICB */
 static struct resource ipmmu_resources[] = {
-        [0] = {
-                .name   = "IPMMU",
-                .start  = 0xfe951000,
-                .end    = 0xfe9510ff,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
 };
 
 static const char * const ipmmu_dev_names[] = {
@@ -982,11 +929,17 @@ void __init sh73a0_add_standard_devices(void)
                             ARRAY_SIZE(sh73a0_late_devices));
 }
 
+void __init sh73a0_init_delay(void)
+{
+        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
+}
+
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak sh73a0_register_twd(void) { }
 
 void __init sh73a0_earlytimer_init(void)
 {
+        sh73a0_init_delay();
         sh73a0_clock_init();
         shmobile_earlytimer_init();
         sh73a0_register_twd();
@@ -1005,17 +958,14 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init sh73a0_init_delay(void)
-{
-        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-}
-
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
         {},
 };
 
 void __init sh73a0_add_standard_devices_dt(void)
 {
+        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
+
         /* clocks are setup late during boot in the case of DT */
         sh73a0_clock_init();
 
@@ -1023,6 +973,9 @@ void __init sh73a0_add_standard_devices_dt(void)
                              ARRAY_SIZE(sh73a0_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              sh73a0_auxdata_lookup, NULL);
+
+        /* Instantiate cpufreq-cpu0 */
+        platform_device_register_full(&devinfo);
 }
 
 static const char *sh73a0_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 53210ec4e8ec..bd7124c87fea 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -16,6 +16,7 @@
 #include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/of.h>
 #include <linux/serial_core.h>
 #include <linux/io.h>
 
@@ -261,7 +262,8 @@ static int s3c_pm_enter(suspend_state_t state)
          * require a full power-cycle)
         */
 
-        if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
+        if (!of_have_populated_dt() &&
+            !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
             !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
                 printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
                 printk(KERN_ERR "%s: Aborting sleep\n", __func__);
@@ -270,8 +272,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
         /* save all necessary core registers not covered by the drivers */
 
-        samsung_pm_save_gpios();
-        samsung_pm_saved_gpios();
+        if (!of_have_populated_dt()) {
+                samsung_pm_save_gpios();
+                samsung_pm_saved_gpios();
+        }
+
         s3c_pm_save_uarts();
         s3c_pm_save_core();
 
@@ -310,8 +315,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
         s3c_pm_restore_core();
         s3c_pm_restore_uarts();
-        samsung_pm_restore_gpios();
-        s3c_pm_restored_gpios();
+
+        if (!of_have_populated_dt()) {
+                samsung_pm_restore_gpios();
+                s3c_pm_restored_gpios();
+        }
 
         s3c_pm_debug_init();
 
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 820116067c10..516e6e9a5594 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -117,7 +117,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
         if (! ((asid += ASID_INC) & ASID_MASK) ) {
                 if (cpu_has_vtag_icache)
                         flush_icache_all();
-#ifdef CONFIG_VIRTUALIZATION
+#ifdef CONFIG_KVM
                 kvm_local_flush_tlb_all();      /* start new asid cycle */
 #else
                 local_flush_tlb_all();  /* start new asid cycle */
diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h
index 3f424f5217da..f09ff5ae2059 100644
--- a/arch/mips/include/uapi/asm/kvm.h
+++ b/arch/mips/include/uapi/asm/kvm.h
@@ -58,56 +58,53 @@ struct kvm_fpu {
  *  bits[2..0]   - Register 'sel' index.
  *  bits[7..3]   - Register 'rd'  index.
  *  bits[15..8]  - Must be zero.
- *  bits[63..16] - 1 -> CP0 registers.
+ *  bits[31..16] - 1 -> CP0 registers.
+ *  bits[51..32] - Must be zero.
+ *  bits[63..52] - As per linux/kvm.h
  *
  * Other sets registers may be added in the future.  Each set would
- * have its own identifier in bits[63..16].
- *
- * The addr field of struct kvm_one_reg must point to an aligned
- * 64-bit wide location.  For registers that are narrower than
- * 64-bits, the value is stored in the low order bits of the location,
- * and sign extended to 64-bits.
+ * have its own identifier in bits[31..16].
  *
  * The registers defined in struct kvm_regs are also accessible, the
  * id values for these are below.
  */
 
-#define KVM_REG_MIPS_R0 0
-#define KVM_REG_MIPS_R1 1
-#define KVM_REG_MIPS_R2 2
-#define KVM_REG_MIPS_R3 3
-#define KVM_REG_MIPS_R4 4
-#define KVM_REG_MIPS_R5 5
-#define KVM_REG_MIPS_R6 6
-#define KVM_REG_MIPS_R7 7
-#define KVM_REG_MIPS_R8 8
-#define KVM_REG_MIPS_R9 9
-#define KVM_REG_MIPS_R10 10
-#define KVM_REG_MIPS_R11 11
-#define KVM_REG_MIPS_R12 12
-#define KVM_REG_MIPS_R13 13
-#define KVM_REG_MIPS_R14 14
-#define KVM_REG_MIPS_R15 15
-#define KVM_REG_MIPS_R16 16
-#define KVM_REG_MIPS_R17 17
-#define KVM_REG_MIPS_R18 18
-#define KVM_REG_MIPS_R19 19
-#define KVM_REG_MIPS_R20 20
-#define KVM_REG_MIPS_R21 21
-#define KVM_REG_MIPS_R22 22
-#define KVM_REG_MIPS_R23 23
-#define KVM_REG_MIPS_R24 24
-#define KVM_REG_MIPS_R25 25
-#define KVM_REG_MIPS_R26 26
-#define KVM_REG_MIPS_R27 27
-#define KVM_REG_MIPS_R28 28
-#define KVM_REG_MIPS_R29 29
-#define KVM_REG_MIPS_R30 30
-#define KVM_REG_MIPS_R31 31
+#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
+#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
+#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
+#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
+#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
+#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
+#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
+#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
+#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
+#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
+#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
+#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
+#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
+#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
+#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
+#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
+#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
+#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
+#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
+#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
+#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
+#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
+#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
+#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
+#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
+#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
+#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
+#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
+#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
+#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
+#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
+#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
 
-#define KVM_REG_MIPS_HI 32
-#define KVM_REG_MIPS_LO 33
-#define KVM_REG_MIPS_PC 34
+#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
+#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
+#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
 
 /*
  * KVM MIPS specific structures and definitions
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index cf5509f13dd5..dba90ec0dc38 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -25,12 +25,16 @@
 #define MCOUNT_OFFSET_INSNS 4
 #endif
 
+#ifdef CONFIG_DYNAMIC_FTRACE
+
 /* Arch override because MIPS doesn't need to run this from stop_machine() */
 void arch_ftrace_update_code(int command)
 {
         ftrace_modify_all_code(command);
 }
 
+#endif
+
 /*
  * Check if the address is in kernel space
  *
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 3b09b888afa9..0c655deeea4a 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
 }
 
 /*
- * The Au1xxx wait is available only if using 32khz counter or
- * external timer source, but specifically not CP0 Counter.
- * alchemy/common/time.c may override cpu_wait!
+ * Au1 'wait' is only useful when the 32kHz counter is used as timer,
+ * since coreclock (and the cp0 counter) stops upon executing it. Only an
+ * interrupt can wake it, so they must be enabled before entering idle modes.
  */
 static void au1k_wait(void)
 {
+        unsigned long c0status = read_c0_status() | 1;  /* irqs on */
+
         __asm__(
         "       .set    mips3                   \n"
         "       cache   0x14, 0(%0)             \n"
         "       cache   0x14, 32(%0)            \n"
         "       sync                            \n"
-        "       nop                             \n"
+        "       mtc0    %1, $12                 \n" /* wr c0status */
         "       wait                            \n"
         "       nop                             \n"
         "       nop                             \n"
         "       nop                             \n"
         "       nop                             \n"
         "       .set    mips0                   \n"
-        : : "r" (au1k_wait));
-        local_irq_enable();
+        : : "r" (au1k_wait), "r" (c0status));
 }
 
 static int __initdata nowait;
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index d934b017f479..dd203e59e6fd 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -485,29 +485,35 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
         return -ENOIOCTLCMD;
 }
 
-#define KVM_REG_MIPS_CP0_INDEX (0x10000 + 8 * 0 + 0)
-#define KVM_REG_MIPS_CP0_ENTRYLO0 (0x10000 + 8 * 2 + 0)
-#define KVM_REG_MIPS_CP0_ENTRYLO1 (0x10000 + 8 * 3 + 0)
-#define KVM_REG_MIPS_CP0_CONTEXT (0x10000 + 8 * 4 + 0)
-#define KVM_REG_MIPS_CP0_USERLOCAL (0x10000 + 8 * 4 + 2)
-#define KVM_REG_MIPS_CP0_PAGEMASK (0x10000 + 8 * 5 + 0)
-#define KVM_REG_MIPS_CP0_PAGEGRAIN (0x10000 + 8 * 5 + 1)
-#define KVM_REG_MIPS_CP0_WIRED (0x10000 + 8 * 6 + 0)
-#define KVM_REG_MIPS_CP0_HWRENA (0x10000 + 8 * 7 + 0)
-#define KVM_REG_MIPS_CP0_BADVADDR (0x10000 + 8 * 8 + 0)
-#define KVM_REG_MIPS_CP0_COUNT (0x10000 + 8 * 9 + 0)
-#define KVM_REG_MIPS_CP0_ENTRYHI (0x10000 + 8 * 10 + 0)
-#define KVM_REG_MIPS_CP0_COMPARE (0x10000 + 8 * 11 + 0)
-#define KVM_REG_MIPS_CP0_STATUS (0x10000 + 8 * 12 + 0)
-#define KVM_REG_MIPS_CP0_CAUSE (0x10000 + 8 * 13 + 0)
-#define KVM_REG_MIPS_CP0_EBASE (0x10000 + 8 * 15 + 1)
-#define KVM_REG_MIPS_CP0_CONFIG (0x10000 + 8 * 16 + 0)
-#define KVM_REG_MIPS_CP0_CONFIG1 (0x10000 + 8 * 16 + 1)
-#define KVM_REG_MIPS_CP0_CONFIG2 (0x10000 + 8 * 16 + 2)
-#define KVM_REG_MIPS_CP0_CONFIG3 (0x10000 + 8 * 16 + 3)
-#define KVM_REG_MIPS_CP0_CONFIG7 (0x10000 + 8 * 16 + 7)
-#define KVM_REG_MIPS_CP0_XCONTEXT (0x10000 + 8 * 20 + 0)
-#define KVM_REG_MIPS_CP0_ERROREPC (0x10000 + 8 * 30 + 0)
+#define MIPS_CP0_32(_R, _S)                                     \
+        (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
+
+#define MIPS_CP0_64(_R, _S)                                     \
+        (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
+
+#define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
+#define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
+#define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
+#define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
+#define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
+#define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
+#define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
+#define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
+#define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
+#define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
+#define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
+#define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
+#define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
+#define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
+#define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
+#define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
+#define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
+#define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
+#define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
+#define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
+#define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
+#define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
+#define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
 
 static u64 kvm_mips_get_one_regs[] = {
         KVM_REG_MIPS_R0,
@@ -567,8 +573,6 @@ static u64 kvm_mips_get_one_regs[] = {
 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
                             const struct kvm_one_reg *reg)
 {
-        u64 __user *uaddr = (u64 __user *)(long)reg->addr;
-
         struct mips_coproc *cop0 = vcpu->arch.cop0;
         s64 v;
 
@@ -631,18 +635,39 @@ static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
         default:
                 return -EINVAL;
         }
-        return put_user(v, uaddr);
+        if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
+                u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
+                return put_user(v, uaddr64);
+        } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
+                u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
+                u32 v32 = (u32)v;
+                return put_user(v32, uaddr32);
+        } else {
+                return -EINVAL;
+        }
 }
 
 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
                             const struct kvm_one_reg *reg)
 {
-        u64 __user *uaddr = (u64 __user *)(long)reg->addr;
         struct mips_coproc *cop0 = vcpu->arch.cop0;
         u64 v;
 
-        if (get_user(v, uaddr) != 0)
-                return -EFAULT;
+        if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
+                u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
+
+                if (get_user(v, uaddr64) != 0)
+                        return -EFAULT;
+        } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
+                u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
+                s32 v32;
+
+                if (get_user(v32, uaddr32) != 0)
+                        return -EFAULT;
+                v = (s64)v32;
+        } else {
+                return -EINVAL;
+        }
 
         switch (reg->id) {
         case KVM_REG_MIPS_R0:
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 26807e5aff51..6f3887d884d2 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -176,6 +176,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0100000000000000)
 #define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 #define CPU_FTR_DAWR                    LONG_ASM_CONST(0x0400000000000000)
+#define CPU_FTR_DABRX                   LONG_ASM_CONST(0x0800000000000000)
 
 #ifndef __ASSEMBLY__
 
@@ -394,19 +395,20 @@ extern const char *powerpc_base_platform;
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
             CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
-            CPU_FTR_HVMODE)
+            CPU_FTR_HVMODE | CPU_FTR_DABRX)
 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
-            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | \
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
             CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
-            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
+            CPU_FTR_DABRX)
 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -415,7 +417,7 @@ extern const char *powerpc_base_platform;
             CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
             CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
-            CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
+            CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -430,14 +432,15 @@ extern const char *powerpc_base_platform;
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
-            CPU_FTR_UNALIGNED_LD_STD)
+            CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
-            CPU_FTR_PURR | CPU_FTR_REAL_LE)
+            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 
 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
+                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
+                     CPU_FTR_ICSWX | CPU_FTR_DABRX )
 
 #ifdef __powerpc64__
 #ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 8e5fae8beaf6..46793b58a761 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -513,7 +513,7 @@ label##_common:							\
  */
 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr)             \
         EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
-                         FINISH_NAP;RUNLATCH_ON;DISABLE_INTS)
+                         FINISH_NAP;DISABLE_INTS;RUNLATCH_ON)
 
 /*
  * When the idle code in power4_idle puts the CPU into NAP mode,
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index b9dd382cb349..851bac7afa4b 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -54,8 +54,16 @@
 #define BOOKE_INTERRUPT_DEBUG 15
 
 /* E500 */
-#define BOOKE_INTERRUPT_SPE_UNAVAIL 32
-#define BOOKE_INTERRUPT_SPE_FP_DATA 33
+#define BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL 32
+#define BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST 33
+/*
+ * TODO: Unify 32-bit and 64-bit kernel exception handlers to use same defines
+ */
+#define BOOKE_INTERRUPT_SPE_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
+#define BOOKE_INTERRUPT_SPE_FP_DATA BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
+#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
+#define BOOKE_INTERRUPT_ALTIVEC_ASSIST \
+                                BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
 #define BOOKE_INTERRUPT_SPE_FP_ROUND 34
 #define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
 #define BOOKE_INTERRUPT_DOORBELL 36
@@ -67,10 +75,6 @@
 #define BOOKE_INTERRUPT_HV_SYSCALL 40
 #define BOOKE_INTERRUPT_HV_PRIV 41
 
-/* altivec */
-#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42
-#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43
-
 /* book3s */
 
 #define BOOK3S_INTERRUPT_SYSTEM_RESET   0x100
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 1f0937d7d4b5..2a45d0f04385 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -452,8 +452,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .mmu_features           = MMU_FTRS_POWER8,
                 .icache_bsize           = 128,
                 .dcache_bsize           = 128,
-                .oprofile_type          = PPC_OPROFILE_POWER4,
-                .oprofile_cpu_type      = 0,
+                .oprofile_type          = PPC_OPROFILE_INVALID,
+                .oprofile_cpu_type      = "ppc64/ibm-compat-v1",
                 .cpu_setup              = __setup_cpu_power8,
                 .cpu_restore            = __restore_cpu_power8,
                 .platform               = "power8",
@@ -506,8 +506,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .dcache_bsize           = 128,
                 .num_pmcs               = 6,
                 .pmc_type               = PPC_PMC_IBM,
-                .oprofile_cpu_type      = 0,
-                .oprofile_type          = PPC_OPROFILE_POWER4,
+                .oprofile_cpu_type      = "ppc64/power8",
+                .oprofile_type          = PPC_OPROFILE_INVALID,
                 .cpu_setup              = __setup_cpu_power8,
                 .cpu_restore            = __restore_cpu_power8,
                 .platform               = "power8",
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 246b11c4fe7e..8741c854e03d 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -465,20 +465,6 @@ BEGIN_FTR_SECTION
         std     r0, THREAD_EBBHR(r3)
         mfspr   r0, SPRN_EBBRR
         std     r0, THREAD_EBBRR(r3)
-
-        /* PMU registers made user read/(write) by EBB */
-        mfspr   r0, SPRN_SIAR
-        std     r0, THREAD_SIAR(r3)
-        mfspr   r0, SPRN_SDAR
-        std     r0, THREAD_SDAR(r3)
-        mfspr   r0, SPRN_SIER
-        std     r0, THREAD_SIER(r3)
-        mfspr   r0, SPRN_MMCR0
-        std     r0, THREAD_MMCR0(r3)
-        mfspr   r0, SPRN_MMCR2
-        std     r0, THREAD_MMCR2(r3)
-        mfspr   r0, SPRN_MMCRA
-        std     r0, THREAD_MMCRA(r3)
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 #endif
 
@@ -581,20 +567,6 @@ BEGIN_FTR_SECTION
         ld      r0, THREAD_EBBRR(r4)
         mtspr   SPRN_EBBRR, r0
 
-        /* PMU registers made user read/(write) by EBB */
-        ld      r0, THREAD_SIAR(r4)
-        mtspr   SPRN_SIAR, r0
-        ld      r0, THREAD_SDAR(r4)
-        mtspr   SPRN_SDAR, r0
-        ld      r0, THREAD_SIER(r4)
-        mtspr   SPRN_SIER, r0
-        ld      r0, THREAD_MMCR0(r4)
-        mtspr   SPRN_MMCR0, r0
-        ld      r0, THREAD_MMCR2(r4)
-        mtspr   SPRN_MMCR2, r0
-        ld      r0, THREAD_MMCRA(r4)
-        mtspr   SPRN_MMCRA, r0
-
         ld      r0,THREAD_TAR(r4)
         mtspr   SPRN_TAR,r0
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index e6eba1bf61ad..40e4a17c8ba0 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -454,38 +454,14 @@ BEGIN_FTR_SECTION
         xori    r10,r10,(MSR_FE0|MSR_FE1)
         mtmsrd  r10
         sync
-        fmr     0,0
-        fmr     1,1
-        fmr     2,2
-        fmr     3,3
-        fmr     4,4
-        fmr     5,5
-        fmr     6,6
-        fmr     7,7
-        fmr     8,8
-        fmr     9,9
-        fmr     10,10
-        fmr     11,11
-        fmr     12,12
-        fmr     13,13
-        fmr     14,14
-        fmr     15,15
-        fmr     16,16
-        fmr     17,17
-        fmr     18,18
-        fmr     19,19
-        fmr     20,20
-        fmr     21,21
-        fmr     22,22
-        fmr     23,23
-        fmr     24,24
-        fmr     25,25
-        fmr     26,26
-        fmr     27,27
-        fmr     28,28
-        fmr     29,29
-        fmr     30,30
-        fmr     31,31
+
+#define FMR2(n)  fmr (n), (n) ; fmr n+1, n+1
+#define FMR4(n)  FMR2(n) ; FMR2(n+2)
+#define FMR8(n)  FMR4(n) ; FMR4(n+4)
+#define FMR16(n) FMR8(n) ; FMR8(n+8)
+#define FMR32(n) FMR16(n) ; FMR16(n+16)
+        FMR32(0)
+
 FTR_SECTION_ELSE
 /*
  * To denormalise we need to move a copy of the register to itself.
@@ -495,39 +471,25 @@ FTR_SECTION_ELSE
         oris    r10,r10,MSR_VSX@h
         mtmsrd  r10
         sync
-        XVCPSGNDP(0,0,0)
-        XVCPSGNDP(1,1,1)
-        XVCPSGNDP(2,2,2)
-        XVCPSGNDP(3,3,3)
-        XVCPSGNDP(4,4,4)
-        XVCPSGNDP(5,5,5)
-        XVCPSGNDP(6,6,6)
-        XVCPSGNDP(7,7,7)
-        XVCPSGNDP(8,8,8)
-        XVCPSGNDP(9,9,9)
-        XVCPSGNDP(10,10,10)
-        XVCPSGNDP(11,11,11)
-        XVCPSGNDP(12,12,12)
-        XVCPSGNDP(13,13,13)
-        XVCPSGNDP(14,14,14)
-        XVCPSGNDP(15,15,15)
-        XVCPSGNDP(16,16,16)
-        XVCPSGNDP(17,17,17)
-        XVCPSGNDP(18,18,18)
-        XVCPSGNDP(19,19,19)
-        XVCPSGNDP(20,20,20)
-        XVCPSGNDP(21,21,21)
-        XVCPSGNDP(22,22,22)
-        XVCPSGNDP(23,23,23)
-        XVCPSGNDP(24,24,24)
-        XVCPSGNDP(25,25,25)
-        XVCPSGNDP(26,26,26)
-        XVCPSGNDP(27,27,27)
-        XVCPSGNDP(28,28,28)
-        XVCPSGNDP(29,29,29)
-        XVCPSGNDP(30,30,30)
-        XVCPSGNDP(31,31,31)
+
+#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
+#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
+#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
+#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
+#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
+        XVCPSGNDP32(0)
+
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
+
+BEGIN_FTR_SECTION
+        b       denorm_done
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+/*
+ * To denormalise we need to move a copy of the register to itself.
+ * For POWER8 we need to do that for all 64 VSX registers
+ */
+        XVCPSGNDP32(32)
+denorm_done:
         mtspr   SPRN_HSRR0,r11
         mtcrf   0x80,r9
         ld      r9,PACA_EXGEN+EX_R9(r13)
@@ -721,7 +683,7 @@ machine_check_common:
         STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
         STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
         STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
-        STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception)
+        STD_EXCEPTION_COMMON(0xe40, emulation_assist, .emulation_assist_interrupt)
         STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
 #ifdef CONFIG_PPC_DOORBELL
         STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5cbcf4d5a808..ea185e0b3cae 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -162,7 +162,7 @@ notrace unsigned int __check_irq_replay(void)
          * in case we also had a rollover while hard disabled
          */
         local_paca->irq_happened &= ~PACA_IRQ_DEC;
-        if (decrementer_check_overflow())
+        if ((happened & PACA_IRQ_DEC) || decrementer_check_overflow())
                 return 0x900;
 
         /* Finally check if an external interrupt happened */
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 7f2273cc3c7d..eabeec991016 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -827,6 +827,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
         }
         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
                 struct resource *res = dev->resource + i;
+                struct pci_bus_region reg;
                 if (!res->flags)
                         continue;
 
@@ -835,8 +836,9 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
                  * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
                  * since in that case, we don't want to re-assign anything
                  */
+                pcibios_resource_to_bus(dev, &reg, res);
                 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
-                    (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
+                    (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
                         /* Only print message if not re-assigning */
                         if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
                                 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index a902723fdc69..076d1242507a 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -399,7 +399,8 @@ static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 {
         mtspr(SPRN_DABR, dabr);
-        mtspr(SPRN_DABRX, dabrx);
+        if (cpu_has_feature(CPU_FTR_DABRX))
+                mtspr(SPRN_DABRX, dabrx);
         return 0;
 }
 #else
@@ -1368,7 +1369,7 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
 
 #ifdef CONFIG_PPC64
 /* Called with hard IRQs off */
-void __ppc64_runlatch_on(void)
+void notrace __ppc64_runlatch_on(void)
 {
         struct thread_info *ti = current_thread_info();
         unsigned long ctrl;
@@ -1381,7 +1382,7 @@ void __ppc64_runlatch_on(void)
 }
 
 /* Called with hard IRQs off */
-void __ppc64_runlatch_off(void)
+void notrace __ppc64_runlatch_off(void)
 {
         struct thread_info *ti = current_thread_info();
         unsigned long ctrl;
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f18c79c324ef..c0e5caf8ccc7 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1165,6 +1165,16 @@ bail:
         exception_exit(prev_state);
 }
 
+/*
+ * This occurs when running in hypervisor mode on POWER6 or later
+ * and an illegal instruction is encountered.
+ */
+void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
+{
+        regs->msr |= REASON_ILLEGAL;
+        program_check_exception(regs);
+}
+
 void alignment_exception(struct pt_regs *regs)
 {
         enum ctx_state prev_state = exception_enter();
diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c
index 5dd3ab469976..ed0385448148 100644
--- a/arch/powerpc/kvm/44x_tlb.c
+++ b/arch/powerpc/kvm/44x_tlb.c
@@ -441,6 +441,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
         struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
         struct kvmppc_44x_tlbe *tlbe;
         unsigned int gtlb_index;
+        int idx;
 
         gtlb_index = kvmppc_get_gpr(vcpu, ra);
         if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {
@@ -473,6 +474,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
                 return EMULATE_FAIL;
         }
 
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+
         if (tlbe_is_host_safe(vcpu, tlbe)) {
                 gva_t eaddr;
                 gpa_t gpaddr;
@@ -489,6 +492,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
                 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
         }
 
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+
         trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,
                              tlbe->word2);
 
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 1020119226db..5cd7ad0c1176 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -832,6 +832,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
 {
         int r = RESUME_HOST;
         int s;
+        int idx;
+
+#ifdef CONFIG_PPC64
+        WARN_ON(local_paca->irq_happened != 0);
+#endif
+
+        /*
+         * We enter with interrupts disabled in hardware, but
+         * we need to call hard_irq_disable anyway to ensure that
+         * the software state is kept in sync.
+         */
+        hard_irq_disable();
 
         /* update before a new last_exit_type is rewritten */
         kvmppc_update_timing_stats(vcpu);
@@ -1053,6 +1065,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         break;
                 }
 
+                idx = srcu_read_lock(&vcpu->kvm->srcu);
+
                 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
                 gfn = gpaddr >> PAGE_SHIFT;
 
@@ -1075,6 +1089,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         kvmppc_account_exit(vcpu, MMIO_EXITS);
                 }
 
+                srcu_read_unlock(&vcpu->kvm->srcu, idx);
                 break;
         }
 
@@ -1098,6 +1113,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
 
                 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
 
+                idx = srcu_read_lock(&vcpu->kvm->srcu);
+
                 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
                 gfn = gpaddr >> PAGE_SHIFT;
 
@@ -1114,6 +1131,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
                 }
 
+                srcu_read_unlock(&vcpu->kvm->srcu, idx);
                 break;
         }
 
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index c41a5a96b558..6d6f153b6c1d 100644
--- a/arch/powerpc/kvm/e500_mmu.c
+++ b/arch/powerpc/kvm/e500_mmu.c
@@ -396,6 +396,7 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
         struct kvm_book3e_206_tlb_entry *gtlbe;
         int tlbsel, esel;
         int recal = 0;
+        int idx;
 
         tlbsel = get_tlb_tlbsel(vcpu);
         esel = get_tlb_esel(vcpu, tlbsel);
@@ -430,6 +431,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
                         kvmppc_set_tlb1map_range(vcpu, gtlbe);
         }
 
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+
         /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
         if (tlbe_is_host_safe(vcpu, gtlbe)) {
                 u64 eaddr = get_tlb_eaddr(gtlbe);
@@ -444,6 +447,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
                 kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel));
         }
 
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+
         kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
         return EMULATE_DONE;
 }
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 753cc99eff2b..19c8379575f7 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -177,8 +177,6 @@ int kvmppc_core_check_processor_compat(void)
                 r = 0;
         else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0)
                 r = 0;
-        else if (strcmp(cur_cpu_spec->cpu_name, "e6500") == 0)
-                r = 0;
         else
                 r = -ENOTSUPP;
 
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 845c867444e6..29c6482890c8 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1758,7 +1758,7 @@ static void perf_event_interrupt(struct pt_regs *regs)
                         }
                 }
         }
-        if ((!found) && printk_ratelimit())
+        if (!found && !nmi && printk_ratelimit())
                 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
 
         /*
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 19506f935737..b456b157d33d 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -83,7 +83,11 @@ static int pseries_eeh_init(void)
         ibm_configure_pe                = rtas_token("ibm,configure-pe");
         ibm_configure_bridge            = rtas_token("ibm,configure-bridge");
 
-        /* necessary sanity check */
+        /*
+         * Necessary sanity check. We needn't check "get-config-addr-info"
+         * and its variant since the old firmware probably support address
+         * of domain/bus/slot/function for EEH RTAS operations.
+         */
         if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) {
                 pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n",
                         __func__);
@@ -102,12 +106,6 @@ static int pseries_eeh_init(void)
                 pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n",
                         __func__);
                 return -EINVAL;
-        } else if (ibm_get_config_addr_info2 == RTAS_UNKNOWN_SERVICE &&
-                   ibm_get_config_addr_info == RTAS_UNKNOWN_SERVICE) {
-                pr_warning("%s: RTAS service <ibm,get-config-addr-info2> and "
-                        "<ibm,get-config-addr-info> invalid\n",
-                        __func__);
-                return -EINVAL;
         } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE &&
                    ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) {
                 pr_warning("%s: RTAS service <ibm,configure-pe> and "
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index ac01463038f1..e8b6e5b8932c 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -623,7 +623,7 @@ static inline pgste_t pgste_get_lock(pte_t *ptep)
                 "       csg     %0,%1,%2\n"
                 "       jl      0b\n"
                 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
-                : "Q" (ptep[PTRS_PER_PTE]) : "cc");
+                : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
 #endif
         return __pgste(new);
 }
@@ -635,11 +635,19 @@ static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
                 "       nihh    %1,0xff7f\n"    /* clear RCP_PCL_BIT */
                 "       stg     %1,%0\n"
                 : "=Q" (ptep[PTRS_PER_PTE])
-                : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
+                : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
+                : "cc", "memory");
         preempt_enable();
 #endif
 }
 
+static inline void pgste_set(pte_t *ptep, pgste_t pgste)
+{
+#ifdef CONFIG_PGSTE
+        *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
+#endif
+}
+
 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
 {
 #ifdef CONFIG_PGSTE
@@ -704,17 +712,19 @@ static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
 {
 #ifdef CONFIG_PGSTE
         unsigned long address;
-        unsigned long okey, nkey;
+        unsigned long nkey;
 
         if (pte_val(entry) & _PAGE_INVALID)
                 return;
+        VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
         address = pte_val(entry) & PAGE_MASK;
-        okey = nkey = page_get_storage_key(address);
-        nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
-        /* Set page access key and fetch protection bit from pgste */
-        nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
-        if (okey != nkey)
-                page_set_storage_key(address, nkey, 0);
+        /*
+         * Set page access key and fetch protection bit from pgste.
+         * The guest C/R information is still in the PGSTE, set real
+         * key C/R to 0.
+         */
+        nkey = (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
+        page_set_storage_key(address, nkey, 0);
 #endif
 }
 
@@ -1099,8 +1109,10 @@ static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
         if (!mm_exclusive(mm))
                 __ptep_ipte(address, ptep);
 
-        if (mm_has_pgste(mm))
+        if (mm_has_pgste(mm)) {
                 pgste = pgste_update_all(&pte, pgste);
+                pgste_set(ptep, pgste);
+        }
         return pte;
 }
 
diff --git a/arch/s390/kernel/dumpstack.c b/arch/s390/kernel/dumpstack.c
index 298297477257..87acc38f73c6 100644
--- a/arch/s390/kernel/dumpstack.c
+++ b/arch/s390/kernel/dumpstack.c
@@ -74,6 +74,8 @@ __show_trace(unsigned long sp, unsigned long low, unsigned long high)
 
 static void show_trace(struct task_struct *task, unsigned long *stack)
 {
+        const unsigned long frame_size =
+                STACK_FRAME_OVERHEAD + sizeof(struct pt_regs);
         register unsigned long __r15 asm ("15");
         unsigned long sp;
 
@@ -82,11 +84,13 @@ static void show_trace(struct task_struct *task, unsigned long *stack)
                 sp = task ? task->thread.ksp : __r15;
         printk("Call Trace:\n");
 #ifdef CONFIG_CHECK_STACK
-        sp = __show_trace(sp, S390_lowcore.panic_stack - 4096,
-                          S390_lowcore.panic_stack);
+        sp = __show_trace(sp,
+                          S390_lowcore.panic_stack + frame_size - 4096,
+                          S390_lowcore.panic_stack + frame_size);
 #endif
-        sp = __show_trace(sp, S390_lowcore.async_stack - ASYNC_SIZE,
-                          S390_lowcore.async_stack);
+        sp = __show_trace(sp,
+                          S390_lowcore.async_stack + frame_size - ASYNC_SIZE,
+                          S390_lowcore.async_stack + frame_size);
         if (task)
                 __show_trace(sp, (unsigned long) task_stack_page(task),
                              (unsigned long) task_stack_page(task) + THREAD_SIZE);
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index f7fb58903f6a..408e866ae548 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -311,3 +311,67 @@ void measurement_alert_subclass_unregister(void)
         spin_unlock(&ma_subclass_lock);
 }
 EXPORT_SYMBOL(measurement_alert_subclass_unregister);
+
+void synchronize_irq(unsigned int irq)
+{
+        /*
+         * Not needed, the handler is protected by a lock and IRQs that occur
+         * after the handler is deleted are just NOPs.
+         */
+}
+EXPORT_SYMBOL_GPL(synchronize_irq);
+
+#ifndef CONFIG_PCI
+
+/* Only PCI devices have dynamically-defined IRQ handlers */
+
+int request_irq(unsigned int irq, irq_handler_t handler,
+                unsigned long irqflags, const char *devname, void *dev_id)
+{
+        return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(request_irq);
+
+void free_irq(unsigned int irq, void *dev_id)
+{
+        WARN_ON(1);
+}
+EXPORT_SYMBOL_GPL(free_irq);
+
+void enable_irq(unsigned int irq)
+{
+        WARN_ON(1);
+}
+EXPORT_SYMBOL_GPL(enable_irq);
+
+void disable_irq(unsigned int irq)
+{
+        WARN_ON(1);
+}
+EXPORT_SYMBOL_GPL(disable_irq);
+
+#endif /* !CONFIG_PCI */
+
+void disable_irq_nosync(unsigned int irq)
+{
+        disable_irq(irq);
+}
+EXPORT_SYMBOL_GPL(disable_irq_nosync);
+
+unsigned long probe_irq_on(void)
+{
+        return 0;
+}
+EXPORT_SYMBOL_GPL(probe_irq_on);
+
+int probe_irq_off(unsigned long val)
+{
+        return 0;
+}
+EXPORT_SYMBOL_GPL(probe_irq_off);
+
+unsigned int probe_irq_mask(unsigned long val)
+{
+        return val;
+}
+EXPORT_SYMBOL_GPL(probe_irq_mask);
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index b6506ee32a36..29bd7bec4176 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -225,7 +225,7 @@ _sclp_print:
         ahi     %r2,1
         ltr     %r0,%r0                         # end of string?
         jz      .LfinalizemtoS4
-        chi     %r0,0x15                        # end of line (NL)?
+        chi     %r0,0x0a                        # end of line (NL)?
         jz      .LfinalizemtoS4
         stc     %r0,0(%r6,%r7)                  # copy to mto
         la      %r11,0(%r6,%r7)
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
index e6f15b5d8b7d..f1e5be85d592 100644
--- a/arch/s390/pci/pci.c
+++ b/arch/s390/pci/pci.c
@@ -302,15 +302,6 @@ static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len)
         return rc;
 }
 
-void synchronize_irq(unsigned int irq)
-{
-        /*
-         * Not needed, the handler is protected by a lock and IRQs that occur
-         * after the handler is deleted are just NOPs.
-         */
-}
-EXPORT_SYMBOL_GPL(synchronize_irq);
-
 void enable_irq(unsigned int irq)
 {
         struct msi_desc *msi = irq_get_msi_desc(irq);
@@ -327,30 +318,6 @@ void disable_irq(unsigned int irq)
 }
 EXPORT_SYMBOL_GPL(disable_irq);
 
-void disable_irq_nosync(unsigned int irq)
-{
-        disable_irq(irq);
-}
-EXPORT_SYMBOL_GPL(disable_irq_nosync);
-
-unsigned long probe_irq_on(void)
-{
-        return 0;
-}
-EXPORT_SYMBOL_GPL(probe_irq_on);
-
-int probe_irq_off(unsigned long val)
-{
-        return 0;
-}
-EXPORT_SYMBOL_GPL(probe_irq_off);
-
-unsigned int probe_irq_mask(unsigned long val)
-{
-        return val;
-}
-EXPORT_SYMBOL_GPL(probe_irq_mask);
-
 void pcibios_fixup_bus(struct pci_bus *bus)
 {
 }
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index 9f20566b0773..79cc0d1a477d 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -54,6 +54,7 @@ EXPORT_SYMBOL(of_set_property_mutex);
 int of_set_property(struct device_node *dp, const char *name, void *val, int len)
 {
         struct property **prevp;
+        unsigned long flags;
         void *new_val;
         int err;
 
@@ -64,7 +65,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
         err = -ENODEV;
 
         mutex_lock(&of_set_property_mutex);
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         prevp = &dp->properties;
         while (*prevp) {
                 struct property *prop = *prevp;
@@ -91,7 +92,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
                 }
                 prevp = &(*prevp)->next;
         }
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         mutex_unlock(&of_set_property_mutex);
 
         /* XXX Upate procfs if necessary... */
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 35ee62fccf98..c205035a6b96 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -251,51 +251,6 @@ static void find_bits(unsigned long mask, u8 *pos, u8 *size)
         *size = len;
 }
 
-static efi_status_t setup_efi_vars(struct boot_params *params)
-{
-        struct setup_data *data;
-        struct efi_var_bootdata *efidata;
-        u64 store_size, remaining_size, var_size;
-        efi_status_t status;
-
-        if (sys_table->runtime->hdr.revision < EFI_2_00_SYSTEM_TABLE_REVISION)
-                return EFI_UNSUPPORTED;
-
-        data = (struct setup_data *)(unsigned long)params->hdr.setup_data;
-
-        while (data && data->next)
-                data = (struct setup_data *)(unsigned long)data->next;
-
-        status = efi_call_phys4((void *)sys_table->runtime->query_variable_info,
-                                EFI_VARIABLE_NON_VOLATILE |
-                                EFI_VARIABLE_BOOTSERVICE_ACCESS |
-                                EFI_VARIABLE_RUNTIME_ACCESS, &store_size,
-                                &remaining_size, &var_size);
-
-        if (status != EFI_SUCCESS)
-                return status;
-
-        status = efi_call_phys3(sys_table->boottime->allocate_pool,
-                                EFI_LOADER_DATA, sizeof(*efidata), &efidata);
-
-        if (status != EFI_SUCCESS)
-                return status;
-
-        efidata->data.type = SETUP_EFI_VARS;
-        efidata->data.len = sizeof(struct efi_var_bootdata) -
-                sizeof(struct setup_data);
-        efidata->data.next = 0;
-        efidata->store_size = store_size;
-        efidata->remaining_size = remaining_size;
-        efidata->max_var_size = var_size;
-
-        if (data)
-                data->next = (unsigned long)efidata;
-        else
-                params->hdr.setup_data = (unsigned long)efidata;
-
-}
-
 static efi_status_t setup_efi_pci(struct boot_params *params)
 {
         efi_pci_io_protocol *pci;
@@ -1202,8 +1157,6 @@ struct boot_params *efi_main(void *handle, efi_system_table_t *_table,
 
         setup_graphics(boot_params);
 
-        setup_efi_vars(boot_params);
-
         setup_efi_pci(boot_params);
 
         status = efi_call_phys3(sys_table->boottime->allocate_pool,
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 2fb5d5884e23..60c89f30c727 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -102,13 +102,6 @@ extern void efi_call_phys_epilog(void);
 extern void efi_unmap_memmap(void);
 extern void efi_memory_uc(u64 addr, unsigned long size);
 
-struct efi_var_bootdata {
-        struct setup_data data;
-        u64 store_size;
-        u64 remaining_size;
-        u64 max_var_size;
-};
-
 #ifdef CONFIG_EFI
 
 static inline bool efi_is_native(void)
diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
index 08744242b8d2..c15ddaf90710 100644
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -6,7 +6,6 @@
 #define SETUP_E820_EXT                  1
 #define SETUP_DTB                       2
 #define SETUP_PCI                       3
-#define SETUP_EFI_VARS                  4
 
 /* ram_size flags */
 #define RAMDISK_IMAGE_START_MASK        0x07FF
diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S
index 7a6f3b3be3cf..f2bb9c96720a 100644
--- a/arch/x86/kernel/relocate_kernel_64.S
+++ b/arch/x86/kernel/relocate_kernel_64.S
@@ -160,7 +160,7 @@ identity_mapped:
         xorq    %rbp, %rbp
         xorq    %r8,  %r8
         xorq    %r9,  %r9
-        xorq    %r10, %r9
+        xorq    %r10, %r10
         xorq    %r11, %r11
         xorq    %r12, %r12
         xorq    %r13, %r13
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index eaac1743def7..1f34e9219775 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -277,6 +277,9 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range,
         end_pfn = limit_pfn;
         nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
 
+        if (!after_bootmem)
+                adjust_range_page_size_mask(mr, nr_range);
+
         /* try to merge same page size and continuous */
         for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
                 unsigned long old_start;
@@ -291,9 +294,6 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range,
                 nr_range--;
         }
 
-        if (!after_bootmem)
-                adjust_range_page_size_mask(mr, nr_range);
-
         for (i = 0; i < nr_range; i++)
                 printk(KERN_DEBUG " [mem %#010lx-%#010lx] page %s\n",
                                 mr[i].start, mr[i].end - 1,
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index 82089d8b1954..5ae2eb09419e 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -42,7 +42,6 @@
 #include <linux/io.h>
 #include <linux/reboot.h>
 #include <linux/bcd.h>
-#include <linux/ucs2_string.h>
 
 #include <asm/setup.h>
 #include <asm/efi.h>
@@ -54,12 +53,12 @@
 
 #define EFI_DEBUG       1
 
-/*
- * There's some additional metadata associated with each
- * variable. Intel's reference implementation is 60 bytes - bump that
- * to account for potential alignment constraints
- */
-#define VAR_METADATA_SIZE 64
+#define EFI_MIN_RESERVE 5120
+
+#define EFI_DUMMY_GUID \
+        EFI_GUID(0x4424ac57, 0xbe4b, 0x47dd, 0x9e, 0x97, 0xed, 0x50, 0xf0, 0x9f, 0x92, 0xa9)
+
+static efi_char16_t efi_dummy_name[6] = { 'D', 'U', 'M', 'M', 'Y', 0 };
 
 struct efi __read_mostly efi = {
         .mps        = EFI_INVALID_TABLE_ADDR,
@@ -79,13 +78,6 @@ struct efi_memory_map memmap;
 static struct efi efi_phys __initdata;
 static efi_system_table_t efi_systab __initdata;
 
-static u64 efi_var_store_size;
-static u64 efi_var_remaining_size;
-static u64 efi_var_max_var_size;
-static u64 boot_used_size;
-static u64 boot_var_size;
-static u64 active_size;
-
 unsigned long x86_efi_facility;
 
 /*
@@ -188,53 +180,8 @@ static efi_status_t virt_efi_get_next_variable(unsigned long *name_size,
                                                efi_char16_t *name,
                                                efi_guid_t *vendor)
 {
-        efi_status_t status;
-        static bool finished = false;
-        static u64 var_size;
-
-        status = efi_call_virt3(get_next_variable,
-                                name_size, name, vendor);
-
-        if (status == EFI_NOT_FOUND) {
-                finished = true;
-                if (var_size < boot_used_size) {
-                        boot_var_size = boot_used_size - var_size;
-                        active_size += boot_var_size;
-                } else {
-                        printk(KERN_WARNING FW_BUG  "efi: Inconsistent initial sizes\n");
-                }
-        }
-
-        if (boot_used_size && !finished) {
-                unsigned long size = 0;
-                u32 attr;
-                efi_status_t s;
-                void *tmp;
-
-                s = virt_efi_get_variable(name, vendor, &attr, &size, NULL);
-
-                if (s != EFI_BUFFER_TOO_SMALL || !size)
-                        return status;
-
-                tmp = kmalloc(size, GFP_ATOMIC);
-
-                if (!tmp)
-                        return status;
-
-                s = virt_efi_get_variable(name, vendor, &attr, &size, tmp);
-
-                if (s == EFI_SUCCESS && (attr & EFI_VARIABLE_NON_VOLATILE)) {
-                        var_size += size;
-                        var_size += ucs2_strsize(name, 1024);
-                        active_size += size;
-                        active_size += VAR_METADATA_SIZE;
-                        active_size += ucs2_strsize(name, 1024);
-                }
-
-                kfree(tmp);
-        }
-
-        return status;
+        return efi_call_virt3(get_next_variable,
+                              name_size, name, vendor);
 }
 
 static efi_status_t virt_efi_set_variable(efi_char16_t *name,
@@ -243,34 +190,9 @@ static efi_status_t virt_efi_set_variable(efi_char16_t *name,
                                           unsigned long data_size,
                                           void *data)
 {
-        efi_status_t status;
-        u32 orig_attr = 0;
-        unsigned long orig_size = 0;
-
-        status = virt_efi_get_variable(name, vendor, &orig_attr, &orig_size,
-                                       NULL);
-
-        if (status != EFI_BUFFER_TOO_SMALL)
-                orig_size = 0;
-
-        status = efi_call_virt5(set_variable,
-                                name, vendor, attr,
-                                data_size, data);
-
-        if (status == EFI_SUCCESS) {
-                if (orig_size) {
-                        active_size -= orig_size;
-                        active_size -= ucs2_strsize(name, 1024);
-                        active_size -= VAR_METADATA_SIZE;
-                }
-                if (data_size) {
-                        active_size += data_size;
-                        active_size += ucs2_strsize(name, 1024);
-                        active_size += VAR_METADATA_SIZE;
-                }
-        }
-
-        return status;
+        return efi_call_virt5(set_variable,
+                              name, vendor, attr,
+                              data_size, data);
 }
 
 static efi_status_t virt_efi_query_variable_info(u32 attr,
@@ -786,9 +708,6 @@ void __init efi_init(void)
         char vendor[100] = "unknown";
         int i = 0;
         void *tmp;
-        struct setup_data *data;
-        struct efi_var_bootdata *efi_var_data;
-        u64 pa_data;
 
 #ifdef CONFIG_X86_32
         if (boot_params.efi_info.efi_systab_hi ||
@@ -806,22 +725,6 @@ void __init efi_init(void)
         if (efi_systab_init(efi_phys.systab))
                 return;
 
-        pa_data = boot_params.hdr.setup_data;
-        while (pa_data) {
-                data = early_ioremap(pa_data, sizeof(*efi_var_data));
-                if (data->type == SETUP_EFI_VARS) {
-                        efi_var_data = (struct efi_var_bootdata *)data;
-
-                        efi_var_store_size = efi_var_data->store_size;
-                        efi_var_remaining_size = efi_var_data->remaining_size;
-                        efi_var_max_var_size = efi_var_data->max_var_size;
-                }
-                pa_data = data->next;
-                early_iounmap(data, sizeof(*efi_var_data));
-        }
-
-        boot_used_size = efi_var_store_size - efi_var_remaining_size;
-
         set_bit(EFI_SYSTEM_TABLES, &x86_efi_facility);
 
         /*
@@ -1085,6 +988,13 @@ void __init efi_enter_virtual_mode(void)
                 runtime_code_page_mkexec();
 
         kfree(new_memmap);
+
+        /* clean DUMMY object */
+        efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+                         EFI_VARIABLE_NON_VOLATILE |
+                         EFI_VARIABLE_BOOTSERVICE_ACCESS |
+                         EFI_VARIABLE_RUNTIME_ACCESS,
+                         0, NULL);
 }
 
 /*
@@ -1136,33 +1046,65 @@ efi_status_t efi_query_variable_store(u32 attributes, unsigned long size)
         efi_status_t status;
         u64 storage_size, remaining_size, max_size;
 
+        if (!(attributes & EFI_VARIABLE_NON_VOLATILE))
+                return 0;
+
         status = efi.query_variable_info(attributes, &storage_size,
                                          &remaining_size, &max_size);
         if (status != EFI_SUCCESS)
                 return status;
 
-        if (!max_size && remaining_size > size)
-                printk_once(KERN_ERR FW_BUG "Broken EFI implementation"
-                            " is returning MaxVariableSize=0\n");
         /*
          * Some firmware implementations refuse to boot if there's insufficient
          * space in the variable store. We account for that by refusing the
          * write if permitting it would reduce the available space to under
-         * 50%. However, some firmware won't reclaim variable space until
-         * after the used (not merely the actively used) space drops below
-         * a threshold. We can approximate that case with the value calculated
-         * above. If both the firmware and our calculations indicate that the
-         * available space would drop below 50%, refuse the write.
+         * 5KB. This figure was provided by Samsung, so should be safe.
          */
+        if ((remaining_size - size < EFI_MIN_RESERVE) &&
+                !efi_no_storage_paranoia) {
+
+                /*
+                 * Triggering garbage collection may require that the firmware
+                 * generate a real EFI_OUT_OF_RESOURCES error. We can force
+                 * that by attempting to use more space than is available.
+                 */
+                unsigned long dummy_size = remaining_size + 1024;
+                void *dummy = kmalloc(dummy_size, GFP_ATOMIC);
+
+                status = efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+                                          EFI_VARIABLE_NON_VOLATILE |
+                                          EFI_VARIABLE_BOOTSERVICE_ACCESS |
+                                          EFI_VARIABLE_RUNTIME_ACCESS,
+                                          dummy_size, dummy);
+
+                if (status == EFI_SUCCESS) {
+                        /*
+                         * This should have failed, so if it didn't make sure
+                         * that we delete it...
+                         */
+                        efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+                                         EFI_VARIABLE_NON_VOLATILE |
+                                         EFI_VARIABLE_BOOTSERVICE_ACCESS |
+                                         EFI_VARIABLE_RUNTIME_ACCESS,
+                                         0, dummy);
+                }
 
-        if (!storage_size || size > remaining_size ||
-            (max_size && size > max_size))
-                return EFI_OUT_OF_RESOURCES;
+                /*
+                 * The runtime code may now have triggered a garbage collection
+                 * run, so check the variable info again
+                 */
+                status = efi.query_variable_info(attributes, &storage_size,
+                                                 &remaining_size, &max_size);
 
-        if (!efi_no_storage_paranoia &&
-            ((active_size + size + VAR_METADATA_SIZE > storage_size / 2) &&
-             (remaining_size - size < storage_size / 2)))
-                return EFI_OUT_OF_RESOURCES;
+                if (status != EFI_SUCCESS)
+                        return status;
+
+                /*
+                 * There still isn't enough room, so return an error
+                 */
+                if (remaining_size - size < EFI_MIN_RESERVE)
+                        return EFI_OUT_OF_RESOURCES;
+        }
 
         return EFI_SUCCESS;
 }
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index 590be1090892..f7bab68a4b83 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -42,9 +42,6 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
         "^(xen_irq_disable_direct_reloc$|"
         "xen_save_fl_direct_reloc$|"
         "VDSO|"
-#if ELF_BITS == 64
-        "__vvar_page|"
-#endif
         "__crc_)",
 
 /*
@@ -72,6 +69,7 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
         "__per_cpu_load|"
         "init_per_cpu__.*|"
         "__end_rodata_hpage_align|"
+        "__vvar_page|"
 #endif
         "_end)$"
 };
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index fb44426fe931..d99cae8147d1 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -17,6 +17,7 @@
 #include <linux/slab.h>
 #include <linux/smp.h>
 #include <linux/irq_work.h>
+#include <linux/tick.h>
 
 #include <asm/paravirt.h>
 #include <asm/desc.h>
@@ -447,6 +448,13 @@ static void __cpuinit xen_play_dead(void) /* used only with HOTPLUG_CPU */
         play_dead_common();
         HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL);
         cpu_bringup();
+        /*
+         * commit 4b0c0f294 (tick: Cleanup NOHZ per cpu data on cpu down)
+         * clears certain data that the cpu_idle loop (which called us
+         * and that we return from) expects. The only way to get that
+         * data back is to call:
+         */
+        tick_nohz_idle_enter();
 }
 
 #else /* !CONFIG_HOTPLUG_CPU */
diff --git a/block/blk-core.c b/block/blk-core.c
index 33c33bc99ddd..d5745b5833c9 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -3164,7 +3164,7 @@ void blk_post_runtime_resume(struct request_queue *q, int err)
                 q->rpm_status = RPM_ACTIVE;
                 __blk_run_queue(q);
                 pm_runtime_mark_last_busy(q->dev);
-                pm_runtime_autosuspend(q->dev);
+                pm_request_autosuspend(q->dev);
         } else {
                 q->rpm_status = RPM_SUSPENDED;
         }
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 622d8a48cbe9..bf8148e74e73 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -823,6 +823,7 @@ config CRYPTO_BLOWFISH_X86_64
 config CRYPTO_BLOWFISH_AVX2_X86_64
         tristate "Blowfish cipher algorithm (x86_64/AVX2)"
         depends on X86 && 64BIT
+        depends on BROKEN
         select CRYPTO_ALGAPI
         select CRYPTO_CRYPTD
         select CRYPTO_ABLK_HELPER_X86
@@ -1299,6 +1300,7 @@ config CRYPTO_TWOFISH_AVX_X86_64
 config CRYPTO_TWOFISH_AVX2_X86_64
         tristate "Twofish cipher algorithm (x86_64/AVX2)"
         depends on X86 && 64BIT
+        depends on BROKEN
         select CRYPTO_ALGAPI
         select CRYPTO_CRYPTD
         select CRYPTO_ABLK_HELPER_X86
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 44225cb15f3a..b14ac46948c9 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -1017,11 +1017,8 @@ acpi_bus_driver_init(struct acpi_device *device, struct acpi_driver *driver)
                 return -ENOSYS;
 
         result = driver->ops.add(device);
-        if (result) {
-                device->driver = NULL;
-                device->driver_data = NULL;
+        if (result)
                 return result;
-        }
 
         device->driver = driver;
 
diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c
index 5d7075d25700..440eadf2d32c 100644
--- a/drivers/acpi/video.c
+++ b/drivers/acpi/video.c
@@ -1722,6 +1722,9 @@ static int acpi_video_bus_add(struct acpi_device *device)
         int error;
         acpi_status status;
 
+        if (device->handler)
+                return -EINVAL;
+
         status = acpi_walk_namespace(ACPI_TYPE_DEVICE,
                                 device->parent->handle, 1,
                                 acpi_video_bus_match, NULL,
diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index aa0875f6f1b7..02f490bad30f 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -143,7 +143,7 @@ static int rbtree_show(struct seq_file *s, void *ignored)
         int registers = 0;
         int this_registers, average;
 
-        map->lock(map);
+        map->lock(map->lock_arg);
 
         mem_size = sizeof(*rbtree_ctx);
         mem_size += BITS_TO_LONGS(map->cache_present_nbits) * sizeof(long);
@@ -170,7 +170,7 @@ static int rbtree_show(struct seq_file *s, void *ignored)
         seq_printf(s, "%d nodes, %d registers, average %d registers, used %zu bytes\n",
                    nodes, registers, average, mem_size);
 
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 
         return 0;
 }
@@ -391,8 +391,6 @@ static int regcache_rbtree_sync(struct regmap *map, unsigned int min,
         for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) {
                 rbnode = rb_entry(node, struct regcache_rbtree_node, node);
 
-                if (rbnode->base_reg < min)
-                        continue;
                 if (rbnode->base_reg > max)
                         break;
                 if (rbnode->base_reg + rbnode->blklen < min)
diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c
index 75923f2396bd..507ee2da0f6e 100644
--- a/drivers/base/regmap/regcache.c
+++ b/drivers/base/regmap/regcache.c
@@ -270,7 +270,7 @@ int regcache_sync(struct regmap *map)
 
         BUG_ON(!map->cache_ops || !map->cache_ops->sync);
 
-        map->lock(map);
+        map->lock(map->lock_arg);
         /* Remember the initial bypass state */
         bypass = map->cache_bypass;
         dev_dbg(map->dev, "Syncing %s cache\n",
@@ -306,7 +306,7 @@ out:
         trace_regcache_sync(map->dev, name, "stop");
         /* Restore the bypass state */
         map->cache_bypass = bypass;
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 
         return ret;
 }
@@ -333,7 +333,7 @@ int regcache_sync_region(struct regmap *map, unsigned int min,
 
         BUG_ON(!map->cache_ops || !map->cache_ops->sync);
 
-        map->lock(map);
+        map->lock(map->lock_arg);
 
         /* Remember the initial bypass state */
         bypass = map->cache_bypass;
@@ -352,7 +352,7 @@ out:
         trace_regcache_sync(map->dev, name, "stop region");
         /* Restore the bypass state */
         map->cache_bypass = bypass;
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 
         return ret;
 }
@@ -372,11 +372,11 @@ EXPORT_SYMBOL_GPL(regcache_sync_region);
  */
 void regcache_cache_only(struct regmap *map, bool enable)
 {
-        map->lock(map);
+        map->lock(map->lock_arg);
         WARN_ON(map->cache_bypass && enable);
         map->cache_only = enable;
         trace_regmap_cache_only(map->dev, enable);
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 }
 EXPORT_SYMBOL_GPL(regcache_cache_only);
 
@@ -391,9 +391,9 @@ EXPORT_SYMBOL_GPL(regcache_cache_only);
  */
 void regcache_mark_dirty(struct regmap *map)
 {
-        map->lock(map);
+        map->lock(map->lock_arg);
         map->cache_dirty = true;
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 }
 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
 
@@ -410,11 +410,11 @@ EXPORT_SYMBOL_GPL(regcache_mark_dirty);
  */
 void regcache_cache_bypass(struct regmap *map, bool enable)
 {
-        map->lock(map);
+        map->lock(map->lock_arg);
         WARN_ON(map->cache_only && enable);
         map->cache_bypass = enable;
         trace_regmap_cache_bypass(map->dev, enable);
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 }
 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
 
diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c
index 23b701f5fd2f..975719bc3450 100644
--- a/drivers/base/regmap/regmap-debugfs.c
+++ b/drivers/base/regmap/regmap-debugfs.c
@@ -265,6 +265,7 @@ static ssize_t regmap_map_write_file(struct file *file,
         char *start = buf;
         unsigned long reg, value;
         struct regmap *map = file->private_data;
+        int ret;
 
         buf_size = min(count, (sizeof(buf)-1));
         if (copy_from_user(buf, user_buf, buf_size))
@@ -282,7 +283,9 @@ static ssize_t regmap_map_write_file(struct file *file,
         /* Userspace has been fiddling around behind the kernel's back */
         add_taint(TAINT_USER, LOCKDEP_NOW_UNRELIABLE);
 
-        regmap_write(map, reg, value);
+        ret = regmap_write(map, reg, value);
+        if (ret < 0)
+                return ret;
         return buf_size;
 }
 #else
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
index 6374dc103521..62b6c2cc80b5 100644
--- a/drivers/block/cciss.c
+++ b/drivers/block/cciss.c
@@ -168,8 +168,6 @@ static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id);
 static int cciss_open(struct block_device *bdev, fmode_t mode);
 static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode);
 static void cciss_release(struct gendisk *disk, fmode_t mode);
-static int do_ioctl(struct block_device *bdev, fmode_t mode,
-                    unsigned int cmd, unsigned long arg);
 static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
                        unsigned int cmd, unsigned long arg);
 static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo);
@@ -235,7 +233,7 @@ static const struct block_device_operations cciss_fops = {
         .owner = THIS_MODULE,
         .open = cciss_unlocked_open,
         .release = cciss_release,
-        .ioctl = do_ioctl,
+        .ioctl = cciss_ioctl,
         .getgeo = cciss_getgeo,
 #ifdef CONFIG_COMPAT
         .compat_ioctl = cciss_compat_ioctl,
@@ -1143,16 +1141,6 @@ static void cciss_release(struct gendisk *disk, fmode_t mode)
         mutex_unlock(&cciss_mutex);
 }
 
-static int do_ioctl(struct block_device *bdev, fmode_t mode,
-                    unsigned cmd, unsigned long arg)
-{
-        int ret;
-        mutex_lock(&cciss_mutex);
-        ret = cciss_ioctl(bdev, mode, cmd, arg);
-        mutex_unlock(&cciss_mutex);
-        return ret;
-}
-
 #ifdef CONFIG_COMPAT
 
 static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
@@ -1179,7 +1167,7 @@ static int cciss_compat_ioctl(struct block_device *bdev, fmode_t mode,
         case CCISS_REGNEWD:
         case CCISS_RESCANDISK:
         case CCISS_GETLUNINFO:
-                return do_ioctl(bdev, mode, cmd, arg);
+                return cciss_ioctl(bdev, mode, cmd, arg);
 
         case CCISS_PASSTHRU32:
                 return cciss_ioctl32_passthru(bdev, mode, cmd, arg);
@@ -1219,7 +1207,7 @@ static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
         if (err)
                 return -EFAULT;
 
-        err = do_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
+        err = cciss_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
         if (err)
                 return err;
         err |=
@@ -1261,7 +1249,7 @@ static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
         if (err)
                 return -EFAULT;
 
-        err = do_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
+        err = cciss_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
         if (err)
                 return err;
         err |=
@@ -1311,11 +1299,14 @@ static int cciss_getpciinfo(ctlr_info_t *h, void __user *argp)
 static int cciss_getintinfo(ctlr_info_t *h, void __user *argp)
 {
         cciss_coalint_struct intinfo;
+        unsigned long flags;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         intinfo.delay = readl(&h->cfgtable->HostWrite.CoalIntDelay);
         intinfo.count = readl(&h->cfgtable->HostWrite.CoalIntCount);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user
             (argp, &intinfo, sizeof(cciss_coalint_struct)))
                 return -EFAULT;
@@ -1356,12 +1347,15 @@ static int cciss_setintinfo(ctlr_info_t *h, void __user *argp)
 static int cciss_getnodename(ctlr_info_t *h, void __user *argp)
 {
         NodeName_type NodeName;
+        unsigned long flags;
         int i;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         for (i = 0; i < 16; i++)
                 NodeName[i] = readb(&h->cfgtable->ServerName[i]);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user(argp, NodeName, sizeof(NodeName_type)))
                 return -EFAULT;
         return 0;
@@ -1398,10 +1392,13 @@ static int cciss_setnodename(ctlr_info_t *h, void __user *argp)
 static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
 {
         Heartbeat_type heartbeat;
+        unsigned long flags;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         heartbeat = readl(&h->cfgtable->HeartBeat);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user(argp, &heartbeat, sizeof(Heartbeat_type)))
                 return -EFAULT;
         return 0;
@@ -1410,10 +1407,13 @@ static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
 static int cciss_getbustypes(ctlr_info_t *h, void __user *argp)
 {
         BusTypes_type BusTypes;
+        unsigned long flags;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         BusTypes = readl(&h->cfgtable->BusTypes);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user(argp, &BusTypes, sizeof(BusTypes_type)))
                 return -EFAULT;
         return 0;
diff --git a/drivers/block/mtip32xx/mtip32xx.c b/drivers/block/mtip32xx/mtip32xx.c
index 847107ef0cce..20dd52a2f92f 100644
--- a/drivers/block/mtip32xx/mtip32xx.c
+++ b/drivers/block/mtip32xx/mtip32xx.c
@@ -3002,7 +3002,8 @@ static int mtip_hw_debugfs_init(struct driver_data *dd)
 
 static void mtip_hw_debugfs_exit(struct driver_data *dd)
 {
-        debugfs_remove_recursive(dd->dfs_node);
+        if (dd->dfs_node)
+                debugfs_remove_recursive(dd->dfs_node);
 }
 
 
@@ -3863,7 +3864,7 @@ static void mtip_make_request(struct request_queue *queue, struct bio *bio)
         struct driver_data *dd = queue->queuedata;
         struct scatterlist *sg;
         struct bio_vec *bvec;
-        int nents = 0;
+        int i, nents = 0;
         int tag = 0, unaligned = 0;
 
         if (unlikely(dd->dd_flag & MTIP_DDF_STOP_IO)) {
@@ -3921,11 +3922,12 @@ static void mtip_make_request(struct request_queue *queue, struct bio *bio)
                 }
 
                 /* Create the scatter list for this bio. */
-                bio_for_each_segment(bvec, bio, nents) {
+                bio_for_each_segment(bvec, bio, i) {
                         sg_set_page(&sg[nents],
                                         bvec->bv_page,
                                         bvec->bv_len,
                                         bvec->bv_offset);
+                        nents++;
                 }
 
                 /* Issue the read/write. */
diff --git a/drivers/block/nvme-core.c b/drivers/block/nvme-core.c
index 8efdfaa44a59..ce79a590b45b 100644
--- a/drivers/block/nvme-core.c
+++ b/drivers/block/nvme-core.c
@@ -629,7 +629,7 @@ static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
         struct nvme_command *cmnd;
         struct nvme_iod *iod;
         enum dma_data_direction dma_dir;
-        int cmdid, length, result = -ENOMEM;
+        int cmdid, length, result;
         u16 control;
         u32 dsmgmt;
         int psegs = bio_phys_segments(ns->queue, bio);
@@ -640,6 +640,7 @@ static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
                         return result;
         }
 
+        result = -ENOMEM;
         iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
         if (!iod)
                 goto nomem;
@@ -977,6 +978,8 @@ static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
 
                 if (timeout && !time_after(now, info[cmdid].timeout))
                         continue;
+                if (info[cmdid].ctx == CMD_CTX_CANCELLED)
+                        continue;
                 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
                 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
                 fn(nvmeq->dev, ctx, &cqe);
@@ -1206,7 +1209,7 @@ struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
 
         if (addr & 3)
                 return ERR_PTR(-EINVAL);
-        if (!length)
+        if (!length || length > INT_MAX - PAGE_SIZE)
                 return ERR_PTR(-EINVAL);
 
         offset = offset_in_page(addr);
@@ -1227,7 +1230,8 @@ struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
         sg_init_table(sg, count);
         for (i = 0; i < count; i++) {
                 sg_set_page(&sg[i], pages[i],
-                                min_t(int, length, PAGE_SIZE - offset), offset);
+                            min_t(unsigned, length, PAGE_SIZE - offset),
+                            offset);
                 length -= (PAGE_SIZE - offset);
                 offset = 0;
         }
@@ -1435,7 +1439,7 @@ static int nvme_user_admin_cmd(struct nvme_dev *dev,
                 nvme_free_iod(dev, iod);
         }
 
-        if (!status && copy_to_user(&ucmd->result, &cmd.result,
+        if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
                                                         sizeof(cmd.result)))
                 status = -EFAULT;
 
@@ -1633,7 +1637,8 @@ static int set_queue_count(struct nvme_dev *dev, int count)
 
 static int nvme_setup_io_queues(struct nvme_dev *dev)
 {
-        int result, cpu, i, nr_io_queues, db_bar_size, q_depth;
+        struct pci_dev *pdev = dev->pci_dev;
+        int result, cpu, i, nr_io_queues, db_bar_size, q_depth, q_count;
 
         nr_io_queues = num_online_cpus();
         result = set_queue_count(dev, nr_io_queues);
@@ -1642,14 +1647,14 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
         if (result < nr_io_queues)
                 nr_io_queues = result;
 
+        q_count = nr_io_queues;
         /* Deregister the admin queue's interrupt */
         free_irq(dev->entry[0].vector, dev->queues[0]);
 
         db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
         if (db_bar_size > 8192) {
                 iounmap(dev->bar);
-                dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
-                                                                db_bar_size);
+                dev->bar = ioremap(pci_resource_start(pdev, 0), db_bar_size);
                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
                 dev->queues[0]->q_db = dev->dbs;
         }
@@ -1657,19 +1662,36 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
         for (i = 0; i < nr_io_queues; i++)
                 dev->entry[i].entry = i;
         for (;;) {
-                result = pci_enable_msix(dev->pci_dev, dev->entry,
-                                                                nr_io_queues);
+                result = pci_enable_msix(pdev, dev->entry, nr_io_queues);
                 if (result == 0) {
                         break;
                 } else if (result > 0) {
                         nr_io_queues = result;
                         continue;
                 } else {
-                        nr_io_queues = 1;
+                        nr_io_queues = 0;
                         break;
                 }
         }
 
+        if (nr_io_queues == 0) {
+                nr_io_queues = q_count;
+                for (;;) {
+                        result = pci_enable_msi_block(pdev, nr_io_queues);
+                        if (result == 0) {
+                                for (i = 0; i < nr_io_queues; i++)
+                                        dev->entry[i].vector = i + pdev->irq;
+                                break;
+                        } else if (result > 0) {
+                                nr_io_queues = result;
+                                continue;
+                        } else {
+                                nr_io_queues = 1;
+                                break;
+                        }
+                }
+        }
+
         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
         /* XXX: handle failure here */
 
@@ -1850,7 +1872,10 @@ static void nvme_free_dev(struct kref *kref)
 {
         struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
         nvme_dev_remove(dev);
-        pci_disable_msix(dev->pci_dev);
+        if (dev->pci_dev->msi_enabled)
+                pci_disable_msi(dev->pci_dev);
+        else if (dev->pci_dev->msix_enabled)
+                pci_disable_msix(dev->pci_dev);
         iounmap(dev->bar);
         nvme_release_instance(dev);
         nvme_release_prp_pools(dev);
@@ -1923,8 +1948,14 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
         INIT_LIST_HEAD(&dev->namespaces);
         dev->pci_dev = pdev;
         pci_set_drvdata(pdev, dev);
-        dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
-        dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
+
+        if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))
+                dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
+        else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))
+                dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+        else
+                goto disable;
+
         result = nvme_set_instance(dev);
         if (result)
                 goto disable;
@@ -1977,7 +2008,10 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  unmap:
         iounmap(dev->bar);
  disable_msix:
-        pci_disable_msix(pdev);
+        if (dev->pci_dev->msi_enabled)
+                pci_disable_msi(dev->pci_dev);
+        else if (dev->pci_dev->msix_enabled)
+                pci_disable_msix(dev->pci_dev);
         nvme_release_instance(dev);
         nvme_release_prp_pools(dev);
  disable:
diff --git a/drivers/block/nvme-scsi.c b/drivers/block/nvme-scsi.c
index fed54b039893..102de2f52b5c 100644
--- a/drivers/block/nvme-scsi.c
+++ b/drivers/block/nvme-scsi.c
@@ -44,7 +44,6 @@
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/types.h>
-#include <linux/version.h>
 #include <scsi/sg.h>
 #include <scsi/scsi.h>
 
@@ -1654,7 +1653,7 @@ static void nvme_trans_modesel_save_bd(struct nvme_ns *ns, u8 *parm_list,
         }
 }
 
-static u16 nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
+static int nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
                                         u8 *mode_page, u8 page_code)
 {
         int res = SNTI_TRANSLATION_SUCCESS;
diff --git a/drivers/block/pktcdvd.c b/drivers/block/pktcdvd.c
index 3c08983e600a..f5d0ea11d9fd 100644
--- a/drivers/block/pktcdvd.c
+++ b/drivers/block/pktcdvd.c
@@ -83,7 +83,8 @@
 
 #define MAX_SPEED 0xffff
 
-#define ZONE(sector, pd) (((sector) + (pd)->offset) & ~((pd)->settings.size - 1))
+#define ZONE(sector, pd) (((sector) + (pd)->offset) & \
+                        ~(sector_t)((pd)->settings.size - 1))
 
 static DEFINE_MUTEX(pktcdvd_mutex);
 static struct pktcdvd_device *pkt_devs[MAX_WRITERS];
diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c
index d6d314027b5d..3063452e55da 100644
--- a/drivers/block/rbd.c
+++ b/drivers/block/rbd.c
@@ -519,8 +519,8 @@ static const struct block_device_operations rbd_bd_ops = {
 };
 
 /*
- * Initialize an rbd client instance.
- * We own *ceph_opts.
+ * Initialize an rbd client instance.  Success or not, this function
+ * consumes ceph_opts.
  */
 static struct rbd_client *rbd_client_create(struct ceph_options *ceph_opts)
 {
@@ -675,7 +675,8 @@ static int parse_rbd_opts_token(char *c, void *private)
 
 /*
  * Get a ceph client with specific addr and configuration, if one does
- * not exist create it.
+ * not exist create it.  Either way, ceph_opts is consumed by this
+ * function.
  */
 static struct rbd_client *rbd_get_client(struct ceph_options *ceph_opts)
 {
@@ -4697,8 +4698,10 @@ out:
         return ret;
 }
 
-/* Undo whatever state changes are made by v1 or v2 image probe */
-
+/*
+ * Undo whatever state changes are made by v1 or v2 header info
+ * call.
+ */
 static void rbd_dev_unprobe(struct rbd_device *rbd_dev)
 {
         struct rbd_image_header *header;
@@ -4902,9 +4905,10 @@ static int rbd_dev_image_probe(struct rbd_device *rbd_dev, bool mapping)
         int tmp;
 
         /*
-         * Get the id from the image id object.  If it's not a
-         * format 2 image, we'll get ENOENT back, and we'll assume
-         * it's a format 1 image.
+         * Get the id from the image id object.  Unless there's an
+         * error, rbd_dev->spec->image_id will be filled in with
+         * a dynamically-allocated string, and rbd_dev->image_format
+         * will be set to either 1 or 2.
          */
         ret = rbd_dev_image_id(rbd_dev);
         if (ret)
@@ -4992,7 +4996,6 @@ static ssize_t rbd_add(struct bus_type *bus,
                 rc = PTR_ERR(rbdc);
                 goto err_out_args;
         }
-        ceph_opts = NULL;       /* rbd_dev client now owns this */
 
         /* pick the pool */
         osdc = &rbdc->client->osdc;
@@ -5027,18 +5030,18 @@ static ssize_t rbd_add(struct bus_type *bus,
         rbd_dev->mapping.read_only = read_only;
 
         rc = rbd_dev_device_setup(rbd_dev);
-        if (!rc)
-                return count;
+        if (rc) {
+                rbd_dev_image_release(rbd_dev);
+                goto err_out_module;
+        }
+
+        return count;
 
-        rbd_dev_image_release(rbd_dev);
 err_out_rbd_dev:
         rbd_dev_destroy(rbd_dev);
 err_out_client:
         rbd_put_client(rbdc);
 err_out_args:
-        if (ceph_opts)
-                ceph_destroy_options(ceph_opts);
-        kfree(rbd_opts);
         rbd_spec_put(spec);
 err_out_module:
         module_put(THIS_MODULE);
diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig
index fdfd61a2d523..11a6104a1e4f 100644
--- a/drivers/bluetooth/Kconfig
+++ b/drivers/bluetooth/Kconfig
@@ -201,7 +201,7 @@ config BT_MRVL
           The core driver to support Marvell Bluetooth devices.
 
           This driver is required if you want to support
-          Marvell Bluetooth devices, such as 8688/8787/8797.
+          Marvell Bluetooth devices, such as 8688/8787/8797/8897.
 
           Say Y here to compile Marvell Bluetooth driver
           into the kernel or say M to compile it as module.
@@ -214,7 +214,7 @@ config BT_MRVL_SDIO
           The driver for Marvell Bluetooth chipsets with SDIO interface.
 
           This driver is required if you want to use Marvell Bluetooth
-          devices with SDIO interface. Currently SD8688/SD8787/SD8797
+          devices with SDIO interface. Currently SD8688/SD8787/SD8797/SD8897
           chipsets are supported.
 
           Say Y here to compile support for Marvell BT-over-SDIO driver
diff --git a/drivers/bluetooth/btmrvl_sdio.c b/drivers/bluetooth/btmrvl_sdio.c
index c63488c54f4a..13693b7a0d5c 100644
--- a/drivers/bluetooth/btmrvl_sdio.c
+++ b/drivers/bluetooth/btmrvl_sdio.c
@@ -82,6 +82,23 @@ static const struct btmrvl_sdio_card_reg btmrvl_reg_87xx = {
         .io_port_2 = 0x7a,
 };
 
+static const struct btmrvl_sdio_card_reg btmrvl_reg_88xx = {
+        .cfg = 0x00,
+        .host_int_mask = 0x02,
+        .host_intstatus = 0x03,
+        .card_status = 0x50,
+        .sq_read_base_addr_a0 = 0x60,
+        .sq_read_base_addr_a1 = 0x61,
+        .card_revision = 0xbc,
+        .card_fw_status0 = 0xc0,
+        .card_fw_status1 = 0xc1,
+        .card_rx_len = 0xc2,
+        .card_rx_unit = 0xc3,
+        .io_port_0 = 0xd8,
+        .io_port_1 = 0xd9,
+        .io_port_2 = 0xda,
+};
+
 static const struct btmrvl_sdio_device btmrvl_sdio_sd8688 = {
         .helper         = "mrvl/sd8688_helper.bin",
         .firmware       = "mrvl/sd8688.bin",
@@ -103,6 +120,13 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8797 = {
         .sd_blksz_fw_dl = 256,
 };
 
+static const struct btmrvl_sdio_device btmrvl_sdio_sd8897 = {
+        .helper         = NULL,
+        .firmware       = "mrvl/sd8897_uapsta.bin",
+        .reg            = &btmrvl_reg_88xx,
+        .sd_blksz_fw_dl = 256,
+};
+
 static const struct sdio_device_id btmrvl_sdio_ids[] = {
         /* Marvell SD8688 Bluetooth device */
         { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x9105),
@@ -116,6 +140,9 @@ static const struct sdio_device_id btmrvl_sdio_ids[] = {
         /* Marvell SD8797 Bluetooth device */
         { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x912A),
                         .driver_data = (unsigned long) &btmrvl_sdio_sd8797 },
+        /* Marvell SD8897 Bluetooth device */
+        { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x912E),
+                        .driver_data = (unsigned long) &btmrvl_sdio_sd8897 },
 
         { }     /* Terminating entry */
 };
@@ -1194,3 +1221,4 @@ MODULE_FIRMWARE("mrvl/sd8688_helper.bin");
 MODULE_FIRMWARE("mrvl/sd8688.bin");
 MODULE_FIRMWARE("mrvl/sd8787_uapsta.bin");
 MODULE_FIRMWARE("mrvl/sd8797_uapsta.bin");
+MODULE_FIRMWARE("mrvl/sd8897_uapsta.bin");
diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c
index a97bb6c1596c..c3dc1c04a5df 100644
--- a/drivers/crypto/sahara.c
+++ b/drivers/crypto/sahara.c
@@ -863,7 +863,7 @@ static struct of_device_id sahara_dt_ids[] = {
         { .compatible = "fsl,imx27-sahara" },
         { /* sentinel */ }
 };
-MODULE_DEVICE_TABLE(platform, sahara_dt_ids);
+MODULE_DEVICE_TABLE(of, sahara_dt_ids);
 
 static int sahara_probe(struct platform_device *pdev)
 {
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index b4ca450947b8..d173d56dbb8c 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -49,6 +49,7 @@ struct gpio_rcar_priv {
 #define POSNEG 0x20
 #define EDGLEVEL 0x24
 #define FILONOFF 0x28
+#define BOTHEDGE 0x4c
 
 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
 {
@@ -91,7 +92,8 @@ static void gpio_rcar_irq_enable(struct irq_data *d)
 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
                                                   unsigned int hwirq,
                                                   bool active_high_rising_edge,
-                                                  bool level_trigger)
+                                                  bool level_trigger,
+                                                  bool both)
 {
         unsigned long flags;
 
@@ -108,6 +110,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
         /* Configure edge or level trigger in EDGLEVEL */
         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 
+        /* Select one edge or both edges in BOTHEDGE */
+        if (p->config.has_both_edge_trigger)
+                gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
+
         /* Select "Interrupt Input Mode" in IOINTSEL */
         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 
@@ -127,16 +133,26 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 
         switch (type & IRQ_TYPE_SENSE_MASK) {
         case IRQ_TYPE_LEVEL_HIGH:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
+                                                      false);
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
+                                                      false);
                 break;
         case IRQ_TYPE_EDGE_RISING:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+                                                      false);
                 break;
         case IRQ_TYPE_EDGE_FALLING:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
+                                                      false);
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                if (!p->config.has_both_edge_trigger)
+                        return -EINVAL;
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+                                                      true);
                 break;
         default:
                 return -EINVAL;
@@ -333,7 +349,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
         }
 
         if (devm_request_irq(&pdev->dev, irq->start,
-                             gpio_rcar_irq_handler, 0, name, p)) {
+                             gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
                 dev_err(&pdev->dev, "failed to request IRQ\n");
                 ret = -ENOENT;
                 goto err1;
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 3cfd0931fbfb..82430ad8ba62 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -1462,7 +1462,7 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
         size_t addr = 0;
         struct gtt_range *gt;
         struct drm_gem_object *obj;
-        int ret;
+        int ret = 0;
 
         /* if we want to turn of the cursor ignore width and height */
         if (!handle) {
@@ -1499,7 +1499,8 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
 
         if (obj->size < width * height * 4) {
                 dev_dbg(dev->dev, "buffer is to small\n");
-                return -ENOMEM;
+                ret = -ENOMEM;
+                goto unref_cursor;
         }
 
         gt = container_of(obj, struct gtt_range, gem);
@@ -1508,7 +1509,7 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
         ret = psb_gtt_pin(gt);
         if (ret) {
                 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
-                return ret;
+                goto unref_cursor;
         }
 
         addr = gt->offset;      /* Or resource.start ??? */
@@ -1532,9 +1533,14 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
                                                         struct gtt_range, gem);
                 psb_gtt_unpin(gt);
                 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
-                psb_intel_crtc->cursor_obj = obj;
         }
-        return 0;
+
+        psb_intel_crtc->cursor_obj = obj;
+        return ret;
+
+unref_cursor:
+        drm_gem_object_unreference(obj);
+        return ret;
 }
 
 static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
@@ -1750,6 +1756,19 @@ static void cdv_intel_crtc_destroy(struct drm_crtc *crtc)
         kfree(psb_intel_crtc);
 }
 
+static void cdv_intel_crtc_disable(struct drm_crtc *crtc)
+{
+        struct gtt_range *gt;
+        struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+        crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+
+        if (crtc->fb) {
+                gt = to_psb_fb(crtc->fb)->gtt;
+                psb_gtt_unpin(gt);
+        }
+}
+
 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
         .dpms = cdv_intel_crtc_dpms,
         .mode_fixup = cdv_intel_crtc_mode_fixup,
@@ -1757,6 +1776,7 @@ const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
         .mode_set_base = cdv_intel_pipe_set_base,
         .prepare = cdv_intel_crtc_prepare,
         .commit = cdv_intel_crtc_commit,
+        .disable = cdv_intel_crtc_disable,
 };
 
 const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c
index 1534e220097a..8b1b6d923abe 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -121,8 +121,8 @@ static int psbfb_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
         unsigned long address;
         int ret;
         unsigned long pfn;
-        /* FIXME: assumes fb at stolen base which may not be true */
-        unsigned long phys_addr = (unsigned long)dev_priv->stolen_base;
+        unsigned long phys_addr = (unsigned long)dev_priv->stolen_base +
+                                  psbfb->gtt->offset;
 
         page_num = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
         address = (unsigned long)vmf->virtual_address - (vmf->pgoff << PAGE_SHIFT);
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c
index 6e8f42b61ff6..6666493789d1 100644
--- a/drivers/gpu/drm/gma500/psb_intel_display.c
+++ b/drivers/gpu/drm/gma500/psb_intel_display.c
@@ -843,7 +843,7 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
         struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt;
         struct drm_gem_object *obj;
         void *tmp_dst, *tmp_src;
-        int ret, i, cursor_pages;
+        int ret = 0, i, cursor_pages;
 
         /* if we want to turn of the cursor ignore width and height */
         if (!handle) {
@@ -880,7 +880,8 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
 
         if (obj->size < width * height * 4) {
                 dev_dbg(dev->dev, "buffer is to small\n");
-                return -ENOMEM;
+                ret = -ENOMEM;
+                goto unref_cursor;
         }
 
         gt = container_of(obj, struct gtt_range, gem);
@@ -889,13 +890,14 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
         ret = psb_gtt_pin(gt);
         if (ret) {
                 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
-                return ret;
+                goto unref_cursor;
         }
 
         if (dev_priv->ops->cursor_needs_phys) {
                 if (cursor_gt == NULL) {
                         dev_err(dev->dev, "No hardware cursor mem available");
-                        return -ENOMEM;
+                        ret = -ENOMEM;
+                        goto unref_cursor;
                 }
 
                 /* Prevent overflow */
@@ -936,9 +938,14 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
                                                         struct gtt_range, gem);
                 psb_gtt_unpin(gt);
                 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
-                psb_intel_crtc->cursor_obj = obj;
         }
-        return 0;
+
+        psb_intel_crtc->cursor_obj = obj;
+        return ret;
+
+unref_cursor:
+        drm_gem_object_unreference(obj);
+        return ret;
 }
 
 static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
@@ -1150,6 +1157,19 @@ static void psb_intel_crtc_destroy(struct drm_crtc *crtc)
         kfree(psb_intel_crtc);
 }
 
+static void psb_intel_crtc_disable(struct drm_crtc *crtc)
+{
+        struct gtt_range *gt;
+        struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+        crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+
+        if (crtc->fb) {
+                gt = to_psb_fb(crtc->fb)->gtt;
+                psb_gtt_unpin(gt);
+        }
+}
+
 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
         .dpms = psb_intel_crtc_dpms,
         .mode_fixup = psb_intel_crtc_mode_fixup,
@@ -1157,6 +1177,7 @@ const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
         .mode_set_base = psb_intel_pipe_set_base,
         .prepare = psb_intel_crtc_prepare,
         .commit = psb_intel_crtc_commit,
+        .disable = psb_intel_crtc_disable,
 };
 
 const struct drm_crtc_funcs psb_intel_crtc_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4c47b449b775..d4ea6c265ce1 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1777,10 +1777,13 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
          * arranged in priority order.
          */
         intel_ddc_get_modes(connector, &intel_sdvo->ddc);
-        if (list_empty(&connector->probed_modes) == false)
-                goto end;
 
-        /* Fetch modes from VBT */
+        /*
+         * Fetch modes from VBT. For SDVO prefer the VBT mode since some
+         * SDVO->LVDS transcoders can't cope with the EDID mode. Since
+         * drm_mode_probed_add adds the mode at the head of the list we add it
+         * last.
+         */
         if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
                 newmode = drm_mode_duplicate(connector->dev,
                                              dev_priv->sdvo_lvds_vbt_mode);
@@ -1792,7 +1795,6 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
                 }
         }
 
-end:
         list_for_each_entry(newmode, &connector->probed_modes, head) {
                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
                         intel_sdvo->sdvo_lvds_fixed_mode =
@@ -2790,12 +2792,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
                         SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
         }
 
-        /* Only enable the hotplug irq if we need it, to work around noisy
-         * hotplug lines.
-         */
-        if (intel_sdvo->hotplug_active)
-                intel_encoder->hpd_pin = HPD_SDVO_B ? HPD_SDVO_B : HPD_SDVO_C;
-
         intel_encoder->compute_config = intel_sdvo_compute_config;
         intel_encoder->disable = intel_disable_sdvo;
         intel_encoder->mode_set = intel_sdvo_mode_set;
@@ -2814,6 +2810,14 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
                 goto err_output;
         }
 
+        /* Only enable the hotplug irq if we need it, to work around noisy
+         * hotplug lines.
+         */
+        if (intel_sdvo->hotplug_active) {
+                intel_encoder->hpd_pin =
+                        intel_sdvo->is_sdvob ?  HPD_SDVO_B : HPD_SDVO_C;
+        }
+
         /*
          * Cloning SDVO with anything is often impossible, since the SDVO
          * encoder can request a special input timing mode. And even if that's
diff --git a/drivers/hid/hid-multitouch.c b/drivers/hid/hid-multitouch.c
index dc3ae5c56f56..d39a5cede0b0 100644
--- a/drivers/hid/hid-multitouch.c
+++ b/drivers/hid/hid-multitouch.c
@@ -264,9 +264,12 @@ static struct mt_class mt_classes[] = {
 static void mt_free_input_name(struct hid_input *hi)
 {
         struct hid_device *hdev = hi->report->device;
+        const char *name = hi->input->name;
 
-        if (hi->input->name != hdev->name)
-                kfree(hi->input->name);
+        if (name != hdev->name) {
+                hi->input->name = hdev->name;
+                kfree(name);
+        }
 }
 
 static ssize_t mt_show_quirks(struct device *dev,
@@ -1040,11 +1043,11 @@ static void mt_remove(struct hid_device *hdev)
         struct hid_input *hi;
 
         sysfs_remove_group(&hdev->dev.kobj, &mt_attribute_group);
-        hid_hw_stop(hdev);
-
         list_for_each_entry(hi, &hdev->inputs, list)
                 mt_free_input_name(hi);
 
+        hid_hw_stop(hdev);
+
         kfree(td);
         hid_set_drvdata(hdev, NULL);
 }
diff --git a/drivers/hwmon/adm1021.c b/drivers/hwmon/adm1021.c
index 7e76922a4ba9..f920619cd6da 100644
--- a/drivers/hwmon/adm1021.c
+++ b/drivers/hwmon/adm1021.c
@@ -331,26 +331,68 @@ static int adm1021_detect(struct i2c_client *client,
         man_id = i2c_smbus_read_byte_data(client, ADM1021_REG_MAN_ID);
         dev_id = i2c_smbus_read_byte_data(client, ADM1021_REG_DEV_ID);
 
+        if (man_id < 0 || dev_id < 0)
+                return -ENODEV;
+
         if (man_id == 0x4d && dev_id == 0x01)
                 type_name = "max1617a";
         else if (man_id == 0x41) {
                 if ((dev_id & 0xF0) == 0x30)
                         type_name = "adm1023";
-                else
+                else if ((dev_id & 0xF0) == 0x00)
                         type_name = "adm1021";
+                else
+                        return -ENODEV;
         } else if (man_id == 0x49)
                 type_name = "thmc10";
         else if (man_id == 0x23)
                 type_name = "gl523sm";
         else if (man_id == 0x54)
                 type_name = "mc1066";
-        /* LM84 Mfr ID in a different place, and it has more unused bits */
-        else if (conv_rate == 0x00
-                 && (config & 0x7F) == 0x00
-                 && (status & 0xAB) == 0x00)
-                type_name = "lm84";
-        else
-                type_name = "max1617";
+        else {
+                int lte, rte, lhi, rhi, llo, rlo;
+
+                /* extra checks for LM84 and MAX1617 to avoid misdetections */
+
+                llo = i2c_smbus_read_byte_data(client, ADM1021_REG_THYST_R(0));
+                rlo = i2c_smbus_read_byte_data(client, ADM1021_REG_THYST_R(1));
+
+                /* fail if any of the additional register reads failed */
+                if (llo < 0 || rlo < 0)
+                        return -ENODEV;
+
+                lte = i2c_smbus_read_byte_data(client, ADM1021_REG_TEMP(0));
+                rte = i2c_smbus_read_byte_data(client, ADM1021_REG_TEMP(1));
+                lhi = i2c_smbus_read_byte_data(client, ADM1021_REG_TOS_R(0));
+                rhi = i2c_smbus_read_byte_data(client, ADM1021_REG_TOS_R(1));
+
+                /*
+                 * Fail for negative temperatures and negative high limits.
+                 * This check also catches read errors on the tested registers.
+                 */
+                if ((s8)lte < 0 || (s8)rte < 0 || (s8)lhi < 0 || (s8)rhi < 0)
+                        return -ENODEV;
+
+                /* fail if all registers hold the same value */
+                if (lte == rte && lte == lhi && lte == rhi && lte == llo
+                    && lte == rlo)
+                        return -ENODEV;
+
+                /*
+                 * LM84 Mfr ID is in a different place,
+                 * and it has more unused bits.
+                 */
+                if (conv_rate == 0x00
+                    && (config & 0x7F) == 0x00
+                    && (status & 0xAB) == 0x00) {
+                        type_name = "lm84";
+                } else {
+                        /* fail if low limits are larger than high limits */
+                        if ((s8)llo > lhi || (s8)rlo > rhi)
+                                return -ENODEV;
+                        type_name = "max1617";
+                }
+        }
 
         pr_debug("Detected chip %s at adapter %d, address 0x%02x.\n",
                  type_name, i2c_adapter_id(adapter), client->addr);
diff --git a/drivers/md/bcache/Kconfig b/drivers/md/bcache/Kconfig
index 05c220d05e23..f950c9d29f3e 100644
--- a/drivers/md/bcache/Kconfig
+++ b/drivers/md/bcache/Kconfig
@@ -1,7 +1,6 @@
 
 config BCACHE
         tristate "Block device as cache"
-        select CLOSURES
         ---help---
         Allows a block device to be used as cache for other devices; uses
         a btree for indexing and the layout is optimized for SSDs.
diff --git a/drivers/md/bcache/bcache.h b/drivers/md/bcache/bcache.h
index 340146d7c17f..d3e15b42a4ab 100644
--- a/drivers/md/bcache/bcache.h
+++ b/drivers/md/bcache/bcache.h
@@ -1241,7 +1241,7 @@ void bch_cache_set_stop(struct cache_set *);
 struct cache_set *bch_cache_set_alloc(struct cache_sb *);
 void bch_btree_cache_free(struct cache_set *);
 int bch_btree_cache_alloc(struct cache_set *);
-void bch_writeback_init_cached_dev(struct cached_dev *);
+void bch_cached_dev_writeback_init(struct cached_dev *);
 void bch_moving_init_cache_set(struct cache_set *);
 
 void bch_cache_allocator_exit(struct cache *ca);
diff --git a/drivers/md/bcache/stats.c b/drivers/md/bcache/stats.c
index 64e679449c2a..b8730e714d69 100644
--- a/drivers/md/bcache/stats.c
+++ b/drivers/md/bcache/stats.c
@@ -93,24 +93,6 @@ static struct attribute *bch_stats_files[] = {
 };
 static KTYPE(bch_stats);
 
-static void scale_accounting(unsigned long data);
-
-void bch_cache_accounting_init(struct cache_accounting *acc,
-                               struct closure *parent)
-{
-        kobject_init(&acc->total.kobj,          &bch_stats_ktype);
-        kobject_init(&acc->five_minute.kobj,    &bch_stats_ktype);
-        kobject_init(&acc->hour.kobj,           &bch_stats_ktype);
-        kobject_init(&acc->day.kobj,            &bch_stats_ktype);
-
-        closure_init(&acc->cl, parent);
-        init_timer(&acc->timer);
-        acc->timer.expires      = jiffies + accounting_delay;
-        acc->timer.data         = (unsigned long) acc;
-        acc->timer.function     = scale_accounting;
-        add_timer(&acc->timer);
-}
-
 int bch_cache_accounting_add_kobjs(struct cache_accounting *acc,
                                    struct kobject *parent)
 {
@@ -244,3 +226,19 @@ void bch_mark_sectors_bypassed(struct search *s, int sectors)
         atomic_add(sectors, &dc->accounting.collector.sectors_bypassed);
         atomic_add(sectors, &s->op.c->accounting.collector.sectors_bypassed);
 }
+
+void bch_cache_accounting_init(struct cache_accounting *acc,
+                               struct closure *parent)
+{
+        kobject_init(&acc->total.kobj,          &bch_stats_ktype);
+        kobject_init(&acc->five_minute.kobj,    &bch_stats_ktype);
+        kobject_init(&acc->hour.kobj,           &bch_stats_ktype);
+        kobject_init(&acc->day.kobj,            &bch_stats_ktype);
+
+        closure_init(&acc->cl, parent);
+        init_timer(&acc->timer);
+        acc->timer.expires      = jiffies + accounting_delay;
+        acc->timer.data         = (unsigned long) acc;
+        acc->timer.function     = scale_accounting;
+        add_timer(&acc->timer);
+}
diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c
index c8046bc4aa57..f88e2b653a3f 100644
--- a/drivers/md/bcache/super.c
+++ b/drivers/md/bcache/super.c
@@ -634,11 +634,10 @@ static int open_dev(struct block_device *b, fmode_t mode)
         return 0;
 }
 
-static int release_dev(struct gendisk *b, fmode_t mode)
+static void release_dev(struct gendisk *b, fmode_t mode)
 {
         struct bcache_device *d = b->private_data;
         closure_put(&d->cl);
-        return 0;
 }
 
 static int ioctl_dev(struct block_device *b, fmode_t mode,
@@ -732,8 +731,7 @@ static void bcache_device_free(struct bcache_device *d)
 
         if (d->c)
                 bcache_device_detach(d);
-
-        if (d->disk)
+        if (d->disk && d->disk->flags & GENHD_FL_UP)
                 del_gendisk(d->disk);
         if (d->disk && d->disk->queue)
                 blk_cleanup_queue(d->disk->queue);
@@ -756,12 +754,9 @@ static int bcache_device_init(struct bcache_device *d, unsigned block_size)
         if (!(d->bio_split = bioset_create(4, offsetof(struct bbio, bio))) ||
             !(d->unaligned_bvec = mempool_create_kmalloc_pool(1,
                                 sizeof(struct bio_vec) * BIO_MAX_PAGES)) ||
-            bio_split_pool_init(&d->bio_split_hook))
-
-                return -ENOMEM;
-
-        d->disk = alloc_disk(1);
-        if (!d->disk)
+            bio_split_pool_init(&d->bio_split_hook) ||
+            !(d->disk = alloc_disk(1)) ||
+            !(q = blk_alloc_queue(GFP_KERNEL)))
                 return -ENOMEM;
 
         snprintf(d->disk->disk_name, DISK_NAME_LEN, "bcache%i", bcache_minor);
@@ -771,10 +766,6 @@ static int bcache_device_init(struct bcache_device *d, unsigned block_size)
         d->disk->fops           = &bcache_ops;
         d->disk->private_data   = d;
 
-        q = blk_alloc_queue(GFP_KERNEL);
-        if (!q)
-                return -ENOMEM;
-
         blk_queue_make_request(q, NULL);
         d->disk->queue                  = q;
         q->queuedata                    = d;
@@ -999,14 +990,17 @@ static void cached_dev_free(struct closure *cl)
 
         mutex_lock(&bch_register_lock);
 
-        bd_unlink_disk_holder(dc->bdev, dc->disk.disk);
+        if (atomic_read(&dc->running))
+                bd_unlink_disk_holder(dc->bdev, dc->disk.disk);
         bcache_device_free(&dc->disk);
         list_del(&dc->list);
 
         mutex_unlock(&bch_register_lock);
 
         if (!IS_ERR_OR_NULL(dc->bdev)) {
-                blk_sync_queue(bdev_get_queue(dc->bdev));
+                if (dc->bdev->bd_disk)
+                        blk_sync_queue(bdev_get_queue(dc->bdev));
+
                 blkdev_put(dc->bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
         }
 
@@ -1028,73 +1022,67 @@ static void cached_dev_flush(struct closure *cl)
 
 static int cached_dev_init(struct cached_dev *dc, unsigned block_size)
 {
-        int err;
+        int ret;
         struct io *io;
-
-        closure_init(&dc->disk.cl, NULL);
-        set_closure_fn(&dc->disk.cl, cached_dev_flush, system_wq);
+        struct request_queue *q = bdev_get_queue(dc->bdev);
 
         __module_get(THIS_MODULE);
         INIT_LIST_HEAD(&dc->list);
+        closure_init(&dc->disk.cl, NULL);
+        set_closure_fn(&dc->disk.cl, cached_dev_flush, system_wq);
         kobject_init(&dc->disk.kobj, &bch_cached_dev_ktype);
-
-        bch_cache_accounting_init(&dc->accounting, &dc->disk.cl);
-
-        err = bcache_device_init(&dc->disk, block_size);
-        if (err)
-                goto err;
-
-        spin_lock_init(&dc->io_lock);
-        closure_init_unlocked(&dc->sb_write);
         INIT_WORK(&dc->detach, cached_dev_detach_finish);
+        closure_init_unlocked(&dc->sb_write);
+        INIT_LIST_HEAD(&dc->io_lru);
+        spin_lock_init(&dc->io_lock);
+        bch_cache_accounting_init(&dc->accounting, &dc->disk.cl);
 
         dc->sequential_merge            = true;
         dc->sequential_cutoff           = 4 << 20;
 
-        INIT_LIST_HEAD(&dc->io_lru);
-        dc->sb_bio.bi_max_vecs  = 1;
-        dc->sb_bio.bi_io_vec    = dc->sb_bio.bi_inline_vecs;
-
         for (io = dc->io; io < dc->io + RECENT_IO; io++) {
                 list_add(&io->lru, &dc->io_lru);
                 hlist_add_head(&io->hash, dc->io_hash + RECENT_IO);
         }
 
-        bch_writeback_init_cached_dev(dc);
+        ret = bcache_device_init(&dc->disk, block_size);
+        if (ret)
+                return ret;
+
+        set_capacity(dc->disk.disk,
+                     dc->bdev->bd_part->nr_sects - dc->sb.data_offset);
+
+        dc->disk.disk->queue->backing_dev_info.ra_pages =
+                max(dc->disk.disk->queue->backing_dev_info.ra_pages,
+                    q->backing_dev_info.ra_pages);
+
+        bch_cached_dev_request_init(dc);
+        bch_cached_dev_writeback_init(dc);
         return 0;
-err:
-        bcache_device_stop(&dc->disk);
-        return err;
 }
 
 /* Cached device - bcache superblock */
 
-static const char *register_bdev(struct cache_sb *sb, struct page *sb_page,
+static void register_bdev(struct cache_sb *sb, struct page *sb_page,
                                  struct block_device *bdev,
                                  struct cached_dev *dc)
 {
         char name[BDEVNAME_SIZE];
         const char *err = "cannot allocate memory";
-        struct gendisk *g;
         struct cache_set *c;
 
-        if (!dc || cached_dev_init(dc, sb->block_size << 9) != 0)
-                return err;
-
         memcpy(&dc->sb, sb, sizeof(struct cache_sb));
-        dc->sb_bio.bi_io_vec[0].bv_page = sb_page;
         dc->bdev = bdev;
         dc->bdev->bd_holder = dc;
 
-        g = dc->disk.disk;
-
-        set_capacity(g, dc->bdev->bd_part->nr_sects - dc->sb.data_offset);
-
-        g->queue->backing_dev_info.ra_pages =
-                max(g->queue->backing_dev_info.ra_pages,
-                    bdev->bd_queue->backing_dev_info.ra_pages);
+        bio_init(&dc->sb_bio);
+        dc->sb_bio.bi_max_vecs  = 1;
+        dc->sb_bio.bi_io_vec    = dc->sb_bio.bi_inline_vecs;
+        dc->sb_bio.bi_io_vec[0].bv_page = sb_page;
+        get_page(sb_page);
 
-        bch_cached_dev_request_init(dc);
+        if (cached_dev_init(dc, sb->block_size << 9))
+                goto err;
 
         err = "error creating kobject";
         if (kobject_add(&dc->disk.kobj, &part_to_dev(bdev->bd_part)->kobj,
@@ -1103,6 +1091,8 @@ static const char *register_bdev(struct cache_sb *sb, struct page *sb_page,
         if (bch_cache_accounting_add_kobjs(&dc->accounting, &dc->disk.kobj))
                 goto err;
 
+        pr_info("registered backing device %s", bdevname(bdev, name));
+
         list_add(&dc->list, &uncached_devices);
         list_for_each_entry(c, &bch_cache_sets, list)
                 bch_cached_dev_attach(dc, c);
@@ -1111,15 +1101,10 @@ static const char *register_bdev(struct cache_sb *sb, struct page *sb_page,
             BDEV_STATE(&dc->sb) == BDEV_STATE_STALE)
                 bch_cached_dev_run(dc);
 
-        return NULL;
+        return;
 err:
-        kobject_put(&dc->disk.kobj);
         pr_notice("error opening %s: %s", bdevname(bdev, name), err);
-        /*
-         * Return NULL instead of an error because kobject_put() cleans
-         * everything up
-         */
-        return NULL;
+        bcache_device_stop(&dc->disk);
 }
 
 /* Flash only volumes */
@@ -1717,20 +1702,11 @@ static int cache_alloc(struct cache_sb *sb, struct cache *ca)
         size_t free;
         struct bucket *b;
 
-        if (!ca)
-                return -ENOMEM;
-
         __module_get(THIS_MODULE);
         kobject_init(&ca->kobj, &bch_cache_ktype);
 
-        memcpy(&ca->sb, sb, sizeof(struct cache_sb));
-
         INIT_LIST_HEAD(&ca->discards);
 
-        bio_init(&ca->sb_bio);
-        ca->sb_bio.bi_max_vecs  = 1;
-        ca->sb_bio.bi_io_vec    = ca->sb_bio.bi_inline_vecs;
-
         bio_init(&ca->journal.bio);
         ca->journal.bio.bi_max_vecs = 8;
         ca->journal.bio.bi_io_vec = ca->journal.bio.bi_inline_vecs;
@@ -1742,18 +1718,17 @@ static int cache_alloc(struct cache_sb *sb, struct cache *ca)
             !init_fifo(&ca->free_inc,   free << 2, GFP_KERNEL) ||
             !init_fifo(&ca->unused,     free << 2, GFP_KERNEL) ||
             !init_heap(&ca->heap,       free << 3, GFP_KERNEL) ||
-            !(ca->buckets       = vmalloc(sizeof(struct bucket) *
+            !(ca->buckets       = vzalloc(sizeof(struct bucket) *
                                           ca->sb.nbuckets)) ||
             !(ca->prio_buckets  = kzalloc(sizeof(uint64_t) * prio_buckets(ca) *
                                           2, GFP_KERNEL)) ||
             !(ca->disk_buckets  = alloc_bucket_pages(GFP_KERNEL, ca)) ||
             !(ca->alloc_workqueue = alloc_workqueue("bch_allocator", 0, 1)) ||
             bio_split_pool_init(&ca->bio_split_hook))
-                goto err;
+                return -ENOMEM;
 
         ca->prio_last_buckets = ca->prio_buckets + prio_buckets(ca);
 
-        memset(ca->buckets, 0, ca->sb.nbuckets * sizeof(struct bucket));
         for_each_bucket(b, ca)
                 atomic_set(&b->pin, 0);
 
@@ -1766,22 +1741,28 @@ err:
         return -ENOMEM;
 }
 
-static const char *register_cache(struct cache_sb *sb, struct page *sb_page,
+static void register_cache(struct cache_sb *sb, struct page *sb_page,
                                   struct block_device *bdev, struct cache *ca)
 {
         char name[BDEVNAME_SIZE];
         const char *err = "cannot allocate memory";
 
-        if (cache_alloc(sb, ca) != 0)
-                return err;
-
-        ca->sb_bio.bi_io_vec[0].bv_page = sb_page;
+        memcpy(&ca->sb, sb, sizeof(struct cache_sb));
         ca->bdev = bdev;
         ca->bdev->bd_holder = ca;
 
+        bio_init(&ca->sb_bio);
+        ca->sb_bio.bi_max_vecs  = 1;
+        ca->sb_bio.bi_io_vec    = ca->sb_bio.bi_inline_vecs;
+        ca->sb_bio.bi_io_vec[0].bv_page = sb_page;
+        get_page(sb_page);
+
         if (blk_queue_discard(bdev_get_queue(ca->bdev)))
                 ca->discard = CACHE_DISCARD(&ca->sb);
 
+        if (cache_alloc(sb, ca) != 0)
+                goto err;
+
         err = "error creating kobject";
         if (kobject_add(&ca->kobj, &part_to_dev(bdev->bd_part)->kobj, "bcache"))
                 goto err;
@@ -1791,15 +1772,10 @@ static const char *register_cache(struct cache_sb *sb, struct page *sb_page,
                 goto err;
 
         pr_info("registered cache device %s", bdevname(bdev, name));
-
-        return NULL;
+        return;
 err:
+        pr_notice("error opening %s: %s", bdevname(bdev, name), err);
         kobject_put(&ca->kobj);
-        pr_info("error opening %s: %s", bdevname(bdev, name), err);
-        /* Return NULL instead of an error because kobject_put() cleans
-         * everything up
-         */
-        return NULL;
 }
 
 /* Global interfaces/init */
@@ -1833,12 +1809,15 @@ static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr,
         bdev = blkdev_get_by_path(strim(path),
                                   FMODE_READ|FMODE_WRITE|FMODE_EXCL,
                                   sb);
-        if (bdev == ERR_PTR(-EBUSY))
-                err = "device busy";
-
-        if (IS_ERR(bdev) ||
-            set_blocksize(bdev, 4096))
+        if (IS_ERR(bdev)) {
+                if (bdev == ERR_PTR(-EBUSY))
+                        err = "device busy";
                 goto err;
+        }
+
+        err = "failed to set blocksize";
+        if (set_blocksize(bdev, 4096))
+                goto err_close;
 
         err = read_super(sb, bdev, &sb_page);
         if (err)
@@ -1846,33 +1825,33 @@ static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr,
 
         if (SB_IS_BDEV(sb)) {
                 struct cached_dev *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
+                if (!dc)
+                        goto err_close;
 
-                err = register_bdev(sb, sb_page, bdev, dc);
+                register_bdev(sb, sb_page, bdev, dc);
         } else {
                 struct cache *ca = kzalloc(sizeof(*ca), GFP_KERNEL);
+                if (!ca)
+                        goto err_close;
 
-                err = register_cache(sb, sb_page, bdev, ca);
+                register_cache(sb, sb_page, bdev, ca);
         }
-
-        if (err) {
-                /* register_(bdev|cache) will only return an error if they
-                 * didn't get far enough to create the kobject - if they did,
-                 * the kobject destructor will do this cleanup.
-                 */
+out:
+        if (sb_page)
                 put_page(sb_page);
-err_close:
-                blkdev_put(bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
-err:
-                if (attr != &ksysfs_register_quiet)
-                        pr_info("error opening %s: %s", path, err);
-                ret = -EINVAL;
-        }
-
         kfree(sb);
         kfree(path);
         mutex_unlock(&bch_register_lock);
         module_put(THIS_MODULE);
         return ret;
+
+err_close:
+        blkdev_put(bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
+err:
+        if (attr != &ksysfs_register_quiet)
+                pr_info("error opening %s: %s", path, err);
+        ret = -EINVAL;
+        goto out;
 }
 
 static int bcache_reboot(struct notifier_block *n, unsigned long code, void *x)
diff --git a/drivers/md/bcache/writeback.c b/drivers/md/bcache/writeback.c
index 93e7e31a4bd3..2714ed3991d1 100644
--- a/drivers/md/bcache/writeback.c
+++ b/drivers/md/bcache/writeback.c
@@ -375,7 +375,7 @@ err:
         refill_dirty(cl);
 }
 
-void bch_writeback_init_cached_dev(struct cached_dev *dc)
+void bch_cached_dev_writeback_init(struct cached_dev *dc)
 {
         closure_init_unlocked(&dc->writeback);
         init_rwsem(&dc->writeback_lock);
diff --git a/drivers/md/md.c b/drivers/md/md.c
index 681d1099a2d5..9b82377a833b 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -5268,8 +5268,8 @@ static void md_clean(struct mddev *mddev)
 
 static void __md_stop_writes(struct mddev *mddev)
 {
+        set_bit(MD_RECOVERY_FROZEN, &mddev->recovery);
         if (mddev->sync_thread) {
-                set_bit(MD_RECOVERY_FROZEN, &mddev->recovery);
                 set_bit(MD_RECOVERY_INTR, &mddev->recovery);
                 md_reap_sync_thread(mddev);
         }
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index 55951182af73..6e17f8181c4b 100644
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
@@ -417,7 +417,17 @@ static void raid1_end_write_request(struct bio *bio, int error)
 
                 r1_bio->bios[mirror] = NULL;
                 to_put = bio;
-                set_bit(R1BIO_Uptodate, &r1_bio->state);
+                /*
+                 * Do not set R1BIO_Uptodate if the current device is
+                 * rebuilding or Faulty. This is because we cannot use
+                 * such device for properly reading the data back (we could
+                 * potentially use it, if the current write would have felt
+                 * before rdev->recovery_offset, but for simplicity we don't
+                 * check this here.
+                 */
+                if (test_bit(In_sync, &conf->mirrors[mirror].rdev->flags) &&
+                    !test_bit(Faulty, &conf->mirrors[mirror].rdev->flags))
+                        set_bit(R1BIO_Uptodate, &r1_bio->state);
 
                 /* Maybe we can clear some bad blocks. */
                 if (is_badblock(conf->mirrors[mirror].rdev,
@@ -870,17 +880,17 @@ static void allow_barrier(struct r1conf *conf)
         wake_up(&conf->wait_barrier);
 }
 
-static void freeze_array(struct r1conf *conf)
+static void freeze_array(struct r1conf *conf, int extra)
 {
         /* stop syncio and normal IO and wait for everything to
          * go quite.
          * We increment barrier and nr_waiting, and then
-         * wait until nr_pending match nr_queued+1
+         * wait until nr_pending match nr_queued+extra
          * This is called in the context of one normal IO request
          * that has failed. Thus any sync request that might be pending
          * will be blocked by nr_pending, and we need to wait for
          * pending IO requests to complete or be queued for re-try.
-         * Thus the number queued (nr_queued) plus this request (1)
+         * Thus the number queued (nr_queued) plus this request (extra)
          * must match the number of pending IOs (nr_pending) before
          * we continue.
          */
@@ -888,7 +898,7 @@ static void freeze_array(struct r1conf *conf)
         conf->barrier++;
         conf->nr_waiting++;
         wait_event_lock_irq_cmd(conf->wait_barrier,
-                                conf->nr_pending == conf->nr_queued+1,
+                                conf->nr_pending == conf->nr_queued+extra,
                                 conf->resync_lock,
                                 flush_pending_writes(conf));
         spin_unlock_irq(&conf->resync_lock);
@@ -1544,8 +1554,8 @@ static int raid1_add_disk(struct mddev *mddev, struct md_rdev *rdev)
                  * we wait for all outstanding requests to complete.
                  */
                 synchronize_sched();
-                raise_barrier(conf);
-                lower_barrier(conf);
+                freeze_array(conf, 0);
+                unfreeze_array(conf);
                 clear_bit(Unmerged, &rdev->flags);
         }
         md_integrity_add_rdev(rdev, mddev);
@@ -1595,11 +1605,11 @@ static int raid1_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
                          */
                         struct md_rdev *repl =
                                 conf->mirrors[conf->raid_disks + number].rdev;
-                        raise_barrier(conf);
+                        freeze_array(conf, 0);
                         clear_bit(Replacement, &repl->flags);
                         p->rdev = repl;
                         conf->mirrors[conf->raid_disks + number].rdev = NULL;
-                        lower_barrier(conf);
+                        unfreeze_array(conf);
                         clear_bit(WantReplacement, &rdev->flags);
                 } else
                         clear_bit(WantReplacement, &rdev->flags);
@@ -2195,7 +2205,7 @@ static void handle_read_error(struct r1conf *conf, struct r1bio *r1_bio)
          * frozen
          */
         if (mddev->ro == 0) {
-                freeze_array(conf);
+                freeze_array(conf, 1);
                 fix_read_error(conf, r1_bio->read_disk,
                                r1_bio->sector, r1_bio->sectors);
                 unfreeze_array(conf);
@@ -2780,8 +2790,8 @@ static int run(struct mddev *mddev)
                 return PTR_ERR(conf);
 
         if (mddev->queue)
-                blk_queue_max_write_same_sectors(mddev->queue,
-                                                 mddev->chunk_sectors);
+                blk_queue_max_write_same_sectors(mddev->queue, 0);
+
         rdev_for_each(rdev, mddev) {
                 if (!mddev->gendisk)
                         continue;
@@ -2963,7 +2973,7 @@ static int raid1_reshape(struct mddev *mddev)
                 return -ENOMEM;
         }
 
-        raise_barrier(conf);
+        freeze_array(conf, 0);
 
         /* ok, everything is stopped */
         oldpool = conf->r1bio_pool;
@@ -2994,7 +3004,7 @@ static int raid1_reshape(struct mddev *mddev)
         conf->raid_disks = mddev->raid_disks = raid_disks;
         mddev->delta_disks = 0;
 
-        lower_barrier(conf);
+        unfreeze_array(conf);
 
         set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
         md_wakeup_thread(mddev->thread);
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 59d4daa5f4c7..6ddae2501b9a 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -490,7 +490,17 @@ static void raid10_end_write_request(struct bio *bio, int error)
                 sector_t first_bad;
                 int bad_sectors;
 
-                set_bit(R10BIO_Uptodate, &r10_bio->state);
+                /*
+                 * Do not set R10BIO_Uptodate if the current device is
+                 * rebuilding or Faulty. This is because we cannot use
+                 * such device for properly reading the data back (we could
+                 * potentially use it, if the current write would have felt
+                 * before rdev->recovery_offset, but for simplicity we don't
+                 * check this here.
+                 */
+                if (test_bit(In_sync, &rdev->flags) &&
+                    !test_bit(Faulty, &rdev->flags))
+                        set_bit(R10BIO_Uptodate, &r10_bio->state);
 
                 /* Maybe we can clear some bad blocks. */
                 if (is_badblock(rdev,
@@ -1055,17 +1065,17 @@ static void allow_barrier(struct r10conf *conf)
         wake_up(&conf->wait_barrier);
 }
 
-static void freeze_array(struct r10conf *conf)
+static void freeze_array(struct r10conf *conf, int extra)
 {
         /* stop syncio and normal IO and wait for everything to
          * go quiet.
          * We increment barrier and nr_waiting, and then
-         * wait until nr_pending match nr_queued+1
+         * wait until nr_pending match nr_queued+extra
          * This is called in the context of one normal IO request
          * that has failed. Thus any sync request that might be pending
          * will be blocked by nr_pending, and we need to wait for
          * pending IO requests to complete or be queued for re-try.
-         * Thus the number queued (nr_queued) plus this request (1)
+         * Thus the number queued (nr_queued) plus this request (extra)
          * must match the number of pending IOs (nr_pending) before
          * we continue.
          */
@@ -1073,7 +1083,7 @@ static void freeze_array(struct r10conf *conf)
         conf->barrier++;
         conf->nr_waiting++;
         wait_event_lock_irq_cmd(conf->wait_barrier,
-                                conf->nr_pending == conf->nr_queued+1,
+                                conf->nr_pending == conf->nr_queued+extra,
                                 conf->resync_lock,
                                 flush_pending_writes(conf));
 
@@ -1837,8 +1847,8 @@ static int raid10_add_disk(struct mddev *mddev, struct md_rdev *rdev)
                  * we wait for all outstanding requests to complete.
                  */
                 synchronize_sched();
-                raise_barrier(conf, 0);
-                lower_barrier(conf);
+                freeze_array(conf, 0);
+                unfreeze_array(conf);
                 clear_bit(Unmerged, &rdev->flags);
         }
         md_integrity_add_rdev(rdev, mddev);
@@ -2612,7 +2622,7 @@ static void handle_read_error(struct mddev *mddev, struct r10bio *r10_bio)
         r10_bio->devs[slot].bio = NULL;
 
         if (mddev->ro == 0) {
-                freeze_array(conf);
+                freeze_array(conf, 1);
                 fix_read_error(conf, mddev, r10_bio);
                 unfreeze_array(conf);
         } else
@@ -3609,8 +3619,7 @@ static int run(struct mddev *mddev)
         if (mddev->queue) {
                 blk_queue_max_discard_sectors(mddev->queue,
                                               mddev->chunk_sectors);
-                blk_queue_max_write_same_sectors(mddev->queue,
-                                                 mddev->chunk_sectors);
+                blk_queue_max_write_same_sectors(mddev->queue, 0);
                 blk_queue_io_min(mddev->queue, chunk_size);
                 if (conf->geo.raid_disks % conf->geo.near_copies)
                         blk_queue_io_opt(mddev->queue, chunk_size * conf->geo.raid_disks);
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index 9359828ffe26..05e4a105b9c7 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -664,6 +664,7 @@ static void ops_run_io(struct stripe_head *sh, struct stripe_head_state *s)
                         if (test_bit(R5_ReadNoMerge, &sh->dev[i].flags))
                                 bi->bi_rw |= REQ_FLUSH;
 
+                        bi->bi_vcnt = 1;
                         bi->bi_io_vec[0].bv_len = STRIPE_SIZE;
                         bi->bi_io_vec[0].bv_offset = 0;
                         bi->bi_size = STRIPE_SIZE;
@@ -701,6 +702,7 @@ static void ops_run_io(struct stripe_head *sh, struct stripe_head_state *s)
                         else
                                 rbi->bi_sector = (sh->sector
                                                   + rrdev->data_offset);
+                        rbi->bi_vcnt = 1;
                         rbi->bi_io_vec[0].bv_len = STRIPE_SIZE;
                         rbi->bi_io_vec[0].bv_offset = 0;
                         rbi->bi_size = STRIPE_SIZE;
@@ -5464,7 +5466,7 @@ static int run(struct mddev *mddev)
                 if (mddev->major_version == 0 &&
                     mddev->minor_version > 90)
                         rdev->recovery_offset = reshape_offset;
-                        
+
                 if (rdev->recovery_offset < reshape_offset) {
                         /* We need to check old and new layout */
                         if (!only_parity(rdev->raid_disk,
@@ -5587,6 +5589,8 @@ static int run(struct mddev *mddev)
                  */
                 mddev->queue->limits.discard_zeroes_data = 0;
 
+                blk_queue_max_write_same_sectors(mddev->queue, 0);
+
                 rdev_for_each(rdev, mddev) {
                         disk_stack_limits(mddev->gendisk, rdev->bdev,
                                           rdev->data_offset << 9);
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index 713d89fedc46..f580d30bb784 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -197,6 +197,8 @@ void mei_stop(struct mei_device *dev)
 {
         dev_dbg(&dev->pdev->dev, "stopping the device.\n");
 
+        flush_scheduled_work();
+
         mutex_lock(&dev->device_lock);
 
         cancel_delayed_work(&dev->timer_work);
@@ -210,8 +212,6 @@ void mei_stop(struct mei_device *dev)
 
         mutex_unlock(&dev->device_lock);
 
-        flush_scheduled_work();
-
         mei_watchdog_unregister(dev);
 }
 EXPORT_SYMBOL_GPL(mei_stop);
diff --git a/drivers/misc/mei/nfc.c b/drivers/misc/mei/nfc.c
index 3adf8a70f26e..d0c6907dfd92 100644
--- a/drivers/misc/mei/nfc.c
+++ b/drivers/misc/mei/nfc.c
@@ -142,6 +142,8 @@ static void mei_nfc_free(struct mei_nfc_dev *ndev)
                 mei_cl_unlink(ndev->cl_info);
                 kfree(ndev->cl_info);
         }
+
+        memset(ndev, 0, sizeof(struct mei_nfc_dev));
 }
 
 static int mei_nfc_build_bus_name(struct mei_nfc_dev *ndev)
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index a727464e9c3f..0f268329bd3a 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -325,6 +325,7 @@ static int mei_me_pci_resume(struct device *device)
 
         mutex_lock(&dev->device_lock);
         dev->dev_state = MEI_DEV_POWER_UP;
+        mei_clear_interrupts(dev);
         mei_reset(dev, 1);
         mutex_unlock(&dev->device_lock);
 
diff --git a/drivers/misc/sgi-gru/grufile.c b/drivers/misc/sgi-gru/grufile.c
index 44d273c5e19d..0535d1e0bc78 100644
--- a/drivers/misc/sgi-gru/grufile.c
+++ b/drivers/misc/sgi-gru/grufile.c
@@ -172,6 +172,7 @@ static long gru_get_config_info(unsigned long arg)
                 nodesperblade = 2;
         else
                 nodesperblade = 1;
+        memset(&info, 0, sizeof(info));
         info.cpus = num_online_cpus();
         info.nodes = num_online_nodes();
         info.blades = info.nodes / nodesperblade;
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 29b846cbfb48..02d9ae7d527e 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -764,8 +764,8 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
         struct net_device *bond_dev, *vlan_dev, *upper_dev;
         struct vlan_entry *vlan;
 
-        rcu_read_lock();
         read_lock(&bond->lock);
+        rcu_read_lock();
 
         bond_dev = bond->dev;
 
@@ -787,12 +787,19 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
                 if (vlan_dev)
                         __bond_resend_igmp_join_requests(vlan_dev);
         }
+        rcu_read_unlock();
 
-        if (--bond->igmp_retrans > 0)
+        /* We use curr_slave_lock to protect against concurrent access to
+         * igmp_retrans from multiple running instances of this function and
+         * bond_change_active_slave
+         */
+        write_lock_bh(&bond->curr_slave_lock);
+        if (bond->igmp_retrans > 1) {
+                bond->igmp_retrans--;
                 queue_delayed_work(bond->wq, &bond->mcast_work, HZ/5);
-
+        }
+        write_unlock_bh(&bond->curr_slave_lock);
         read_unlock(&bond->lock);
-        rcu_read_unlock();
 }
 
 static void bond_resend_igmp_join_requests_delayed(struct work_struct *work)
@@ -1957,6 +1964,10 @@ err_free:
 
 err_undo_flags:
         bond_compute_features(bond);
+        /* Enslave of first slave has failed and we need to fix master's mac */
+        if (bond->slave_cnt == 0 &&
+            ether_addr_equal(bond_dev->dev_addr, slave_dev->dev_addr))
+                eth_hw_addr_random(bond_dev);
 
         return res;
 }
diff --git a/drivers/net/bonding/bonding.h b/drivers/net/bonding/bonding.h
index 2baec24388b1..f989e1529a29 100644
--- a/drivers/net/bonding/bonding.h
+++ b/drivers/net/bonding/bonding.h
@@ -225,7 +225,7 @@ struct bonding {
         rwlock_t curr_slave_lock;
         u8       send_peer_notif;
         s8       setup_by_slave;
-        s8       igmp_retrans;
+        u8       igmp_retrans;
 #ifdef CONFIG_PROC_FS
         struct   proc_dir_entry *proc_entry;
         char     proc_file_name[IFNAMSIZ];
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 0f493c8dc28b..c777b9013164 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -1800,6 +1800,9 @@ static int tg3_poll_fw(struct tg3 *tp)
         int i;
         u32 val;
 
+        if (tg3_flag(tp, NO_FWARE_REPORTED))
+                return 0;
+
         if (tg3_flag(tp, IS_SSB_CORE)) {
                 /* We don't use firmware. */
                 return 0;
@@ -10404,6 +10407,13 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
  */
 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
 {
+        /* Chip may have been just powered on. If so, the boot code may still
+         * be running initialization. Wait for it to finish to avoid races in
+         * accessing the hardware.
+         */
+        tg3_enable_register_access(tp);
+        tg3_poll_fw(tp);
+
         tg3_switch_clocks(tp);
 
         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
diff --git a/drivers/net/ethernet/dec/tulip/interrupt.c b/drivers/net/ethernet/dec/tulip/interrupt.c
index 28a5e425fecf..92306b320840 100644
--- a/drivers/net/ethernet/dec/tulip/interrupt.c
+++ b/drivers/net/ethernet/dec/tulip/interrupt.c
@@ -76,6 +76,12 @@ int tulip_refill_rx(struct net_device *dev)
 
                         mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ,
                                                  PCI_DMA_FROMDEVICE);
+                        if (dma_mapping_error(&tp->pdev->dev, mapping)) {
+                                dev_kfree_skb(skb);
+                                tp->rx_buffers[entry].skb = NULL;
+                                break;
+                        }
+
                         tp->rx_buffers[entry].mapping = mapping;
 
                         tp->rx_ring[entry].buffer1 = cpu_to_le32(mapping);
diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c
index 8bc1b21b1c79..a0b4be51f0d1 100644
--- a/drivers/net/ethernet/emulex/benet/be_main.c
+++ b/drivers/net/ethernet/emulex/benet/be_main.c
@@ -4262,6 +4262,9 @@ static int be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id)
                 netdev->features |= NETIF_F_HIGHDMA;
         } else {
                 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+                if (!status)
+                        status = dma_set_coherent_mask(&pdev->dev,
+                                                       DMA_BIT_MASK(32));
                 if (status) {
                         dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
                         goto free_netdev;
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 42e9dd05c936..5e3982fc5398 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -897,8 +897,8 @@ static int sh_eth_check_reset(struct net_device *ndev)
                 mdelay(1);
                 cnt--;
         }
-        if (cnt < 0) {
-                pr_err("Device reset fail\n");
+        if (cnt <= 0) {
+                pr_err("Device reset failed\n");
                 ret = -ETIMEDOUT;
         }
         return ret;
@@ -1401,16 +1401,23 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
                 pkt_len = rxdesc->frame_length;
 
-#if defined(CONFIG_ARCH_R8A7740)
-                desc_status >>= 16;
-#endif
-
                 if (--boguscnt < 0)
                         break;
 
                 if (!(desc_status & RDFEND))
                         ndev->stats.rx_length_errors++;
 
+#if defined(CONFIG_ARCH_R8A7740)
+                /*
+                 * In case of almost all GETHER/ETHERs, the Receive Frame State
+                 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
+                 * bit 0. However, in case of the R8A7740's GETHER, the RFS
+                 * bits are from bit 25 to bit 16. So, the driver needs right
+                 * shifting by 16.
+                 */
+                desc_status >>= 16;
+#endif
+
                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
                         ndev->stats.rx_errors++;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 618446ae1ec1..ee919ca8b8a0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1899,7 +1899,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
 
 #ifdef STMMAC_XMIT_DEBUG
         if (netif_msg_pktdata(priv)) {
-                pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d"
+                pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
                         __func__, (priv->cur_tx % txsize),
                         (priv->dirty_tx % txsize), entry, first, nfrags);
                 if (priv->extend_desc)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec173564c..c47f0dbcebb5 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -449,10 +449,9 @@ static int davinci_mdio_suspend(struct device *dev)
         __raw_writel(ctrl, &data->regs->control);
         wait_for_idle(data);
 
-        pm_runtime_put_sync(data->dev);
-
         data->suspended = true;
         spin_unlock(&data->lock);
+        pm_runtime_put_sync(data->dev);
 
         return 0;
 }
@@ -460,15 +459,12 @@ static int davinci_mdio_suspend(struct device *dev)
 static int davinci_mdio_resume(struct device *dev)
 {
         struct davinci_mdio_data *data = dev_get_drvdata(dev);
-        u32 ctrl;
 
-        spin_lock(&data->lock);
         pm_runtime_get_sync(data->dev);
 
+        spin_lock(&data->lock);
         /* restart the scan state machine */
-        ctrl = __raw_readl(&data->regs->control);
-        ctrl |= CONTROL_ENABLE;
-        __raw_writel(ctrl, &data->regs->control);
+        __davinci_mdio_reset(data);
 
         data->suspended = false;
         spin_unlock(&data->lock);
@@ -477,8 +473,8 @@ static int davinci_mdio_resume(struct device *dev)
 }
 
 static const struct dev_pm_ops davinci_mdio_pm_ops = {
-        .suspend        = davinci_mdio_suspend,
-        .resume         = davinci_mdio_resume,
+        .suspend_late   = davinci_mdio_suspend,
+        .resume_early   = davinci_mdio_resume,
 };
 
 static const struct of_device_id davinci_mdio_of_mtable[] = {
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index 1c502bb0c916..6e91931a1c2c 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -853,18 +853,24 @@ static int macvlan_changelink(struct net_device *dev,
                 struct nlattr *tb[], struct nlattr *data[])
 {
         struct macvlan_dev *vlan = netdev_priv(dev);
-        if (data && data[IFLA_MACVLAN_MODE])
-                vlan->mode = nla_get_u32(data[IFLA_MACVLAN_MODE]);
+
         if (data && data[IFLA_MACVLAN_FLAGS]) {
                 __u16 flags = nla_get_u16(data[IFLA_MACVLAN_FLAGS]);
                 bool promisc = (flags ^ vlan->flags) & MACVLAN_FLAG_NOPROMISC;
-
-                if (promisc && (flags & MACVLAN_FLAG_NOPROMISC))
-                        dev_set_promiscuity(vlan->lowerdev, -1);
-                else if (promisc && !(flags & MACVLAN_FLAG_NOPROMISC))
-                        dev_set_promiscuity(vlan->lowerdev, 1);
+                if (vlan->port->passthru && promisc) {
+                        int err;
+
+                        if (flags & MACVLAN_FLAG_NOPROMISC)
+                                err = dev_set_promiscuity(vlan->lowerdev, -1);
+                        else
+                                err = dev_set_promiscuity(vlan->lowerdev, 1);
+                        if (err < 0)
+                                return err;
+                }
                 vlan->flags = flags;
         }
+        if (data && data[IFLA_MACVLAN_MODE])
+                vlan->mode = nla_get_u32(data[IFLA_MACVLAN_MODE]);
         return 0;
 }
 
diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c
index d016a76ad44b..b3051052f3ad 100644
--- a/drivers/net/team/team.c
+++ b/drivers/net/team/team.c
@@ -1092,8 +1092,8 @@ static int team_port_add(struct team *team, struct net_device *port_dev)
         }
 
         port->index = -1;
-        team_port_enable(team, port);
         list_add_tail_rcu(&port->list, &team->port_list);
+        team_port_enable(team, port);
         __team_compute_features(team);
         __team_port_change_port_added(port, !!netif_carrier_ok(port_dev));
         __team_options_change_check(team);
diff --git a/drivers/net/team/team_mode_random.c b/drivers/net/team/team_mode_random.c
index 5ca14d463ba7..7f032e211343 100644
--- a/drivers/net/team/team_mode_random.c
+++ b/drivers/net/team/team_mode_random.c
@@ -28,6 +28,8 @@ static bool rnd_transmit(struct team *team, struct sk_buff *skb)
 
         port_index = random_N(team->en_port_count);
         port = team_get_port_by_index_rcu(team, port_index);
+        if (unlikely(!port))
+                goto drop;
         port = team_get_first_port_txable_rcu(team, port);
         if (unlikely(!port))
                 goto drop;
diff --git a/drivers/net/team/team_mode_roundrobin.c b/drivers/net/team/team_mode_roundrobin.c
index d268e4de781b..472623f8ce3d 100644
--- a/drivers/net/team/team_mode_roundrobin.c
+++ b/drivers/net/team/team_mode_roundrobin.c
@@ -32,6 +32,8 @@ static bool rr_transmit(struct team *team, struct sk_buff *skb)
 
         port_index = rr_priv(team)->sent_packets++ % team->en_port_count;
         port = team_get_port_by_index_rcu(team, port_index);
+        if (unlikely(!port))
+                goto drop;
         port = team_get_first_port_txable_rcu(team, port);
         if (unlikely(!port))
                 goto drop;
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 89776c592151..bfa9bb48e42d 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -352,7 +352,7 @@ static u16 tun_select_queue(struct net_device *dev, struct sk_buff *skb)
         u32 numqueues = 0;
 
         rcu_read_lock();
-        numqueues = tun->numqueues;
+        numqueues = ACCESS_ONCE(tun->numqueues);
 
         txq = skb_get_rxhash(skb);
         if (txq) {
@@ -2159,6 +2159,8 @@ static int tun_chr_open(struct inode *inode, struct file * file)
         set_bit(SOCK_EXTERNALLY_ALLOCATED, &tfile->socket.flags);
         INIT_LIST_HEAD(&tfile->next);
 
+        sock_set_flag(&tfile->sk, SOCK_ZEROCOPY);
+
         return 0;
 }
 
diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c
index 078795fe6e31..04ee044dde51 100644
--- a/drivers/net/usb/cdc_ether.c
+++ b/drivers/net/usb/cdc_ether.c
@@ -627,6 +627,12 @@ static const struct usb_device_id	products [] = {
         .driver_info = 0,
 },
 
+/* Huawei E1820 - handled by qmi_wwan */
+{
+        USB_DEVICE_INTERFACE_NUMBER(HUAWEI_VENDOR_ID, 0x14ac, 1),
+        .driver_info = 0,
+},
+
 /* Realtek RTL8152 Based USB 2.0 Ethernet Adapters */
 #if defined(CONFIG_USB_RTL8152) || defined(CONFIG_USB_RTL8152_MODULE)
 {
diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index 86adfa0a912e..d095d0d3056b 100644
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -519,6 +519,7 @@ static const struct usb_device_id products[] = {
         /* 3. Combined interface devices matching on interface number */
         {QMI_FIXED_INTF(0x0408, 0xea42, 4)},    /* Yota / Megafon M100-1 */
         {QMI_FIXED_INTF(0x12d1, 0x140c, 1)},    /* Huawei E173 */
+        {QMI_FIXED_INTF(0x12d1, 0x14ac, 1)},    /* Huawei E1820 */
         {QMI_FIXED_INTF(0x19d2, 0x0002, 1)},
         {QMI_FIXED_INTF(0x19d2, 0x0012, 1)},
         {QMI_FIXED_INTF(0x19d2, 0x0017, 3)},
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index f3dc124c60c7..3c2cbc9d6295 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -92,13 +92,17 @@ config ATH9K_MAC_DEBUG
           This option enables collection of statistics for Rx/Tx status
           data and some other MAC related statistics
 
-config ATH9K_RATE_CONTROL
+config ATH9K_LEGACY_RATE_CONTROL
         bool "Atheros ath9k rate control"
         depends on ATH9K
-        default y
+        default n
         ---help---
           Say Y, if you want to use the ath9k specific rate control
-          module instead of minstrel_ht.
+          module instead of minstrel_ht. Be warned that there are various
+          issues with the ath9k RC and minstrel is a more robust algorithm.
+          Note that even if this option is selected, "ath9k_rate_control"
+          has to be passed to mac80211 using the module parameter,
+          ieee80211_default_rc_algo.
 
 config ATH9K_HTC
        tristate "Atheros HTC based wireless cards support"
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 2ad8f9474ba1..75ee9e7704ce 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -8,7 +8,7 @@ ath9k-y +=	beacon.o \
                 antenna.o
 
 ath9k-$(CONFIG_ATH9K_BTCOEX_SUPPORT) += mci.o
-ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o
+ath9k-$(CONFIG_ATH9K_LEGACY_RATE_CONTROL) += rc.o
 ath9k-$(CONFIG_ATH9K_PCI) += pci.o
 ath9k-$(CONFIG_ATH9K_AHB) += ahb.o
 ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index db5ffada2217..7546b9a7dcbf 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -958,11 +958,11 @@ static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
         {0x0000a074, 0x00000000},
         {0x0000a078, 0x00000000},
         {0x0000a07c, 0x00000000},
-        {0x0000a080, 0x1a1a1a1a},
-        {0x0000a084, 0x1a1a1a1a},
-        {0x0000a088, 0x1a1a1a1a},
-        {0x0000a08c, 0x1a1a1a1a},
-        {0x0000a090, 0x171a1a1a},
+        {0x0000a080, 0x22222229},
+        {0x0000a084, 0x1d1d1d1d},
+        {0x0000a088, 0x1d1d1d1d},
+        {0x0000a08c, 0x1d1d1d1d},
+        {0x0000a090, 0x171d1d1d},
         {0x0000a094, 0x11111717},
         {0x0000a098, 0x00030311},
         {0x0000a09c, 0x00000000},
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index aba415103f94..2ba494567777 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -787,8 +787,7 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         hw->wiphy->iface_combinations = if_comb;
         hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
 
-        if (AR_SREV_5416(sc->sc_ah))
-                hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+        hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 
         hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
@@ -830,10 +829,6 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         sc->ant_rx = hw->wiphy->available_antennas_rx;
         sc->ant_tx = hw->wiphy->available_antennas_tx;
 
-#ifdef CONFIG_ATH9K_RATE_CONTROL
-        hw->rate_control_algorithm = "ath9k_rate_control";
-#endif
-
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
                         &sc->sbands[IEEE80211_BAND_2GHZ];
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index 267dbfcfaa96..b9a87383cb43 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -231,7 +231,7 @@ static inline void ath_debug_stat_retries(struct ath_rate_priv *rc, int rix,
 }
 #endif
 
-#ifdef CONFIG_ATH9K_RATE_CONTROL
+#ifdef CONFIG_ATH9K_LEGACY_RATE_CONTROL
 int ath_rate_control_register(void);
 void ath_rate_control_unregister(void);
 #else
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 6dd07e2ec595..a95b77ab360e 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -2458,7 +2458,7 @@ static void b43_request_firmware(struct work_struct *work)
         for (i = 0; i < B43_NR_FWTYPES; i++) {
                 errmsg = ctx->errors[i];
                 if (strlen(errmsg))
-                        b43err(dev->wl, errmsg);
+                        b43err(dev->wl, "%s", errmsg);
         }
         b43_print_fw_helptext(dev->wl, 1);
         goto out;
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index f8246f2d88f9..4caaf52986a4 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1832,16 +1832,16 @@ u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
                           u32 beacon_interval);
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 extern const struct dev_pm_ops il_pm_ops;
 
 #define IL_LEGACY_PM_OPS        (&il_pm_ops)
 
-#else /* !CONFIG_PM */
+#else /* !CONFIG_PM_SLEEP */
 
 #define IL_LEGACY_PM_OPS        NULL
 
-#endif /* !CONFIG_PM */
+#endif /* !CONFIG_PM_SLEEP */
 
 /*****************************************************
 *  Error Handling Debugging
diff --git a/drivers/net/wireless/mwifiex/debugfs.c b/drivers/net/wireless/mwifiex/debugfs.c
index 753b5682d53f..a5f9875cfd6e 100644
--- a/drivers/net/wireless/mwifiex/debugfs.c
+++ b/drivers/net/wireless/mwifiex/debugfs.c
@@ -26,10 +26,17 @@
 static struct dentry *mwifiex_dfs_dir;
 
 static char *bss_modes[] = {
-        "Unknown",
-        "Ad-hoc",
-        "Managed",
-        "Auto"
+        "UNSPECIFIED",
+        "ADHOC",
+        "STATION",
+        "AP",
+        "AP_VLAN",
+        "WDS",
+        "MONITOR",
+        "MESH_POINT",
+        "P2P_CLIENT",
+        "P2P_GO",
+        "P2P_DEVICE",
 };
 
 /* size/addr for mwifiex_debug_info */
@@ -200,7 +207,12 @@ mwifiex_info_read(struct file *file, char __user *ubuf,
         p += sprintf(p, "driver_version = %s", fmt);
         p += sprintf(p, "\nverext = %s", priv->version_str);
         p += sprintf(p, "\ninterface_name=\"%s\"\n", netdev->name);
-        p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]);
+
+        if (info.bss_mode >= ARRAY_SIZE(bss_modes))
+                p += sprintf(p, "bss_mode=\"%d\"\n", info.bss_mode);
+        else
+                p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]);
+
         p += sprintf(p, "media_state=\"%s\"\n",
                      (!priv->media_connected ? "Disconnected" : "Connected"));
         p += sprintf(p, "mac_address=\"%pM\"\n", netdev->dev_addr);
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 999ffc12578b..c97e9d327331 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -764,6 +764,7 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
                                  "can't alloc skb for rx\n");
                         goto done;
                 }
+                kmemleak_not_leak(new_skb);
 
                 pci_unmap_single(rtlpci->pdev,
                                  *((dma_addr_t *) skb->cb),
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
index 3d0498e69c8c..189ba124a8c6 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
@@ -1973,26 +1973,35 @@ void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
         }
 }
 
-void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
-                                   struct ieee80211_sta *sta,
-                                   u8 rssi_level)
+static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
+                                          struct ieee80211_sta *sta)
 {
         struct rtl_priv *rtlpriv = rtl_priv(hw);
         struct rtl_phy *rtlphy = &(rtlpriv->phy);
         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-        u32 ratr_value = (u32) mac->basic_rates;
-        u8 *mcsrate = mac->mcs;
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u32 ratr_value;
         u8 ratr_index = 0;
         u8 nmode = mac->ht_enable;
-        u8 mimo_ps = 1;
-        u16 shortgi_rate = 0;
-        u32 tmp_ratr_value = 0;
+        u8 mimo_ps = IEEE80211_SMPS_OFF;
+        u16 shortgi_rate;
+        u32 tmp_ratr_value;
         u8 curtxbw_40mhz = mac->bw_40;
-        u8 curshortgi_40mhz = mac->sgi_40;
-        u8 curshortgi_20mhz = mac->sgi_20;
+        u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
+                               1 : 0;
+        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
+                               1 : 0;
         enum wireless_mode wirelessmode = mac->mode;
 
-        ratr_value |= ((*(u16 *) (mcsrate))) << 12;
+        if (rtlhal->current_bandtype == BAND_ON_5G)
+                ratr_value = sta->supp_rates[1] << 4;
+        else
+                ratr_value = sta->supp_rates[0];
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                ratr_value = 0xfff;
+
+        ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
+                        sta->ht_cap.mcs.rx_mask[0] << 12);
         switch (wirelessmode) {
         case WIRELESS_MODE_B:
                 if (ratr_value & 0x0000000c)
@@ -2006,7 +2015,7 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
         case WIRELESS_MODE_N_24G:
         case WIRELESS_MODE_N_5G:
                 nmode = 1;
-                if (mimo_ps == 0) {
+                if (mimo_ps == IEEE80211_SMPS_STATIC) {
                         ratr_value &= 0x0007F005;
                 } else {
                         u32 ratr_mask;
@@ -2016,8 +2025,7 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
                                 ratr_mask = 0x000ff005;
                         else
                                 ratr_mask = 0x0f0ff005;
-                        if (curtxbw_40mhz)
-                                ratr_mask |= 0x00000010;
+
                         ratr_value &= ratr_mask;
                 }
                 break;
@@ -2026,41 +2034,74 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
                         ratr_value &= 0x000ff0ff;
                 else
                         ratr_value &= 0x0f0ff0ff;
+
                 break;
         }
+
         ratr_value &= 0x0FFFFFFF;
-        if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
-            (!curtxbw_40mhz && curshortgi_20mhz))) {
+
+        if (nmode && ((curtxbw_40mhz &&
+                         curshortgi_40mhz) || (!curtxbw_40mhz &&
+                                               curshortgi_20mhz))) {
+
                 ratr_value |= 0x10000000;
                 tmp_ratr_value = (ratr_value >> 12);
+
                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
                         if ((1 << shortgi_rate) & tmp_ratr_value)
                                 break;
                 }
+
                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
-                               (shortgi_rate << 4) | (shortgi_rate);
+                    (shortgi_rate << 4) | (shortgi_rate);
         }
+
         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
+
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
+                 rtl_read_dword(rtlpriv, REG_ARFR0));
 }
 
-void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
+static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
+                                         struct ieee80211_sta *sta,
+                                         u8 rssi_level)
 {
         struct rtl_priv *rtlpriv = rtl_priv(hw);
         struct rtl_phy *rtlphy = &(rtlpriv->phy);
         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-        u32 ratr_bitmap = (u32) mac->basic_rates;
-        u8 *p_mcsrate = mac->mcs;
-        u8 ratr_index = 0;
-        u8 curtxbw_40mhz = mac->bw_40;
-        u8 curshortgi_40mhz = mac->sgi_40;
-        u8 curshortgi_20mhz = mac->sgi_20;
-        enum wireless_mode wirelessmode = mac->mode;
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_sta_info *sta_entry = NULL;
+        u32 ratr_bitmap;
+        u8 ratr_index;
+        u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
+        u8 curshortgi_40mhz = curtxbw_40mhz &&
+                              (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
+                                1 : 0;
+        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
+                                1 : 0;
+        enum wireless_mode wirelessmode = 0;
         bool shortgi = false;
         u8 rate_mask[5];
         u8 macid = 0;
-        u8 mimops = 1;
-
-        ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
+        u8 mimo_ps = IEEE80211_SMPS_OFF;
+
+        sta_entry = (struct rtl_sta_info *) sta->drv_priv;
+        wirelessmode = sta_entry->wireless_mode;
+        if (mac->opmode == NL80211_IFTYPE_STATION ||
+            mac->opmode == NL80211_IFTYPE_MESH_POINT)
+                curtxbw_40mhz = mac->bw_40;
+        else if (mac->opmode == NL80211_IFTYPE_AP ||
+                mac->opmode == NL80211_IFTYPE_ADHOC)
+                macid = sta->aid + 1;
+
+        if (rtlhal->current_bandtype == BAND_ON_5G)
+                ratr_bitmap = sta->supp_rates[1] << 4;
+        else
+                ratr_bitmap = sta->supp_rates[0];
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                ratr_bitmap = 0xfff;
+        ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
+                        sta->ht_cap.mcs.rx_mask[0] << 12);
         switch (wirelessmode) {
         case WIRELESS_MODE_B:
                 ratr_index = RATR_INX_WIRELESS_B;
@@ -2071,6 +2112,7 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                 break;
         case WIRELESS_MODE_G:
                 ratr_index = RATR_INX_WIRELESS_GB;
+
                 if (rssi_level == 1)
                         ratr_bitmap &= 0x00000f00;
                 else if (rssi_level == 2)
@@ -2085,7 +2127,8 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
         case WIRELESS_MODE_N_24G:
         case WIRELESS_MODE_N_5G:
                 ratr_index = RATR_INX_WIRELESS_NGB;
-                if (mimops == 0) {
+
+                if (mimo_ps == IEEE80211_SMPS_STATIC) {
                         if (rssi_level == 1)
                                 ratr_bitmap &= 0x00070000;
                         else if (rssi_level == 2)
@@ -2128,8 +2171,10 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                                 }
                         }
                 }
+
                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
                     (!curtxbw_40mhz && curshortgi_20mhz)) {
+
                         if (macid == 0)
                                 shortgi = true;
                         else if (macid == 1)
@@ -2138,21 +2183,42 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                 break;
         default:
                 ratr_index = RATR_INX_WIRELESS_NGB;
+
                 if (rtlphy->rf_type == RF_1T2R)
                         ratr_bitmap &= 0x000ff0ff;
                 else
                         ratr_bitmap &= 0x0f0ff0ff;
                 break;
         }
-        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "ratr_bitmap :%x\n",
-                 ratr_bitmap);
-        *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
-                                      ratr_index << 28);
+        sta_entry->ratr_index = ratr_index;
+
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
+                 "ratr_bitmap :%x\n", ratr_bitmap);
+        *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
+                                     (ratr_index << 28);
         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
                  "Rate_index:%x, ratr_val:%x, %5phC\n",
                  ratr_index, ratr_bitmap, rate_mask);
-        rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
+        memcpy(rtlpriv->rate_mask, rate_mask, 5);
+        /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
+         * "scheduled while atomic" if called directly */
+        schedule_work(&rtlpriv->works.fill_h2c_cmd);
+
+        if (macid != 0)
+                sta_entry->ratr_index = ratr_index;
+}
+
+void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
+                                 struct ieee80211_sta *sta,
+                                 u8 rssi_level)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        if (rtlpriv->dm.useramask)
+                rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
+        else
+                rtl92cu_update_hal_rate_table(hw, sta);
 }
 
 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
index f41a3aa4a26f..8e3ec1e25644 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
@@ -98,10 +98,6 @@ void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
                                    u32 add_msr, u32 rm_msr);
 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
-void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
-                                   struct ieee80211_sta *sta,
-                                   u8 rssi_level);
-void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level);
 
 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw);
 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
index 85b6bdb163c0..da4f587199ee 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
@@ -289,14 +289,30 @@ void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
                                 macaddr = cam_const_broad;
                                 entry_id = key_index;
                         } else {
+                                if (mac->opmode == NL80211_IFTYPE_AP ||
+                                    mac->opmode == NL80211_IFTYPE_MESH_POINT) {
+                                        entry_id = rtl_cam_get_free_entry(hw,
+                                                                 p_macaddr);
+                                        if (entry_id >=  TOTAL_CAM_ENTRY) {
+                                                RT_TRACE(rtlpriv, COMP_SEC,
+                                                         DBG_EMERG,
+                                                         "Can not find free hw security cam entry\n");
+                                                return;
+                                        }
+                                } else {
+                                        entry_id = CAM_PAIRWISE_KEY_POSITION;
+                                }
+
                                 key_index = PAIRWISE_KEYIDX;
-                                entry_id = CAM_PAIRWISE_KEY_POSITION;
                                 is_pairwise = true;
                         }
                 }
                 if (rtlpriv->sec.key_len[key_index] == 0) {
                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
                                  "delete one entry\n");
+                        if (mac->opmode == NL80211_IFTYPE_AP ||
+                            mac->opmode == NL80211_IFTYPE_MESH_POINT)
+                                rtl_cam_del_entry(hw, p_macaddr);
                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
                 } else {
                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
index 938b1e670b93..826f085c29dd 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
@@ -106,8 +106,7 @@ static struct rtl_hal_ops rtl8192cu_hal_ops = {
         .update_interrupt_mask = rtl92cu_update_interrupt_mask,
         .get_hw_reg = rtl92cu_get_hw_reg,
         .set_hw_reg = rtl92cu_set_hw_reg,
-        .update_rate_tbl = rtl92cu_update_hal_rate_table,
-        .update_rate_mask = rtl92cu_update_hal_rate_mask,
+        .update_rate_tbl = rtl92cu_update_hal_rate_tbl,
         .fill_tx_desc = rtl92cu_tx_fill_desc,
         .fill_fake_txdesc = rtl92cu_fill_fake_txdesc,
         .fill_tx_cmddesc = rtl92cu_tx_fill_cmddesc,
@@ -137,6 +136,7 @@ static struct rtl_hal_ops rtl8192cu_hal_ops = {
         .phy_lc_calibrate = _rtl92cu_phy_lc_calibrate,
         .phy_set_bw_mode_callback = rtl92cu_phy_set_bw_mode_callback,
         .dm_dynamic_txpower = rtl92cu_dm_dynamic_txpower,
+        .fill_h2c_cmd = rtl92c_fill_h2c_cmd,
 };
 
 static struct rtl_mod_params rtl92cu_mod_params = {
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
index a1310abd0d54..262e1e4c6e5b 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
@@ -49,5 +49,8 @@ bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
 u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
                             enum radio_path rfpath, u32 regaddr, u32 bitmask);
 void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
+void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
+                                 struct ieee80211_sta *sta,
+                                 u8 rssi_level);
 
 #endif
diff --git a/drivers/net/wireless/rtlwifi/usb.c b/drivers/net/wireless/rtlwifi/usb.c
index 76732b0cd221..a3532e077871 100644
--- a/drivers/net/wireless/rtlwifi/usb.c
+++ b/drivers/net/wireless/rtlwifi/usb.c
@@ -824,6 +824,7 @@ static void rtl_usb_stop(struct ieee80211_hw *hw)
 
         /* should after adapter start and interrupt enable. */
         set_hal_stop(rtlhal);
+        cancel_work_sync(&rtlpriv->works.fill_h2c_cmd);
         /* Enable software */
         SET_USB_STOP(rtlusb);
         rtl_usb_deinit(hw);
@@ -1026,6 +1027,16 @@ static bool rtl_usb_tx_chk_waitq_insert(struct ieee80211_hw *hw,
         return false;
 }
 
+static void rtl_fill_h2c_cmd_work_callback(struct work_struct *work)
+{
+        struct rtl_works *rtlworks =
+            container_of(work, struct rtl_works, fill_h2c_cmd);
+        struct ieee80211_hw *hw = rtlworks->hw;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpriv->cfg->ops->fill_h2c_cmd(hw, H2C_RA_MASK, 5, rtlpriv->rate_mask);
+}
+
 static struct rtl_intf_ops rtl_usb_ops = {
         .adapter_start = rtl_usb_start,
         .adapter_stop = rtl_usb_stop,
@@ -1057,6 +1068,8 @@ int rtl_usb_probe(struct usb_interface *intf,
 
         /* this spin lock must be initialized early */
         spin_lock_init(&rtlpriv->locks.usb_lock);
+        INIT_WORK(&rtlpriv->works.fill_h2c_cmd,
+                  rtl_fill_h2c_cmd_work_callback);
 
         rtlpriv->usb_data_index = 0;
         init_completion(&rtlpriv->firmware_loading_complete);
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index 44328baa6389..cc03e7c87cbe 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -1736,6 +1736,8 @@ struct rtl_hal_ops {
         void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
                                              bool mstate);
         void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
+        void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
+                              u32 cmd_len, u8 *p_cmdbuffer);
 };
 
 struct rtl_intf_ops {
@@ -1869,6 +1871,7 @@ struct rtl_works {
         struct delayed_work fwevt_wq;
 
         struct work_struct lps_change_work;
+        struct work_struct fill_h2c_cmd;
 };
 
 struct rtl_debug {
@@ -2048,6 +2051,7 @@ struct rtl_priv {
                 };
         };
         bool enter_ps;  /* true when entering PS */
+        u8 rate_mask[5];
 
         /*This must be the last item so
            that it points to the data allocated
diff --git a/drivers/net/wireless/ti/wl12xx/scan.c b/drivers/net/wireless/ti/wl12xx/scan.c
index affdb3ec6225..4a0bbb13806b 100644
--- a/drivers/net/wireless/ti/wl12xx/scan.c
+++ b/drivers/net/wireless/ti/wl12xx/scan.c
@@ -310,7 +310,7 @@ static void wl12xx_adjust_channels(struct wl1271_cmd_sched_scan_config *cmd,
         memcpy(cmd->channels_2, cmd_channels->channels_2,
                sizeof(cmd->channels_2));
         memcpy(cmd->channels_5, cmd_channels->channels_5,
-               sizeof(cmd->channels_2));
+               sizeof(cmd->channels_5));
         /* channels_4 are not supported, so no need to copy them */
 }
 
diff --git a/drivers/net/wireless/ti/wl12xx/wl12xx.h b/drivers/net/wireless/ti/wl12xx/wl12xx.h
index 222d03540200..9e5484a73667 100644
--- a/drivers/net/wireless/ti/wl12xx/wl12xx.h
+++ b/drivers/net/wireless/ti/wl12xx/wl12xx.h
@@ -36,12 +36,12 @@
 #define WL127X_IFTYPE_SR_VER    3
 #define WL127X_MAJOR_SR_VER     10
 #define WL127X_SUBTYPE_SR_VER   WLCORE_FW_VER_IGNORE
-#define WL127X_MINOR_SR_VER     115
+#define WL127X_MINOR_SR_VER     133
 /* minimum multi-role FW version for wl127x */
 #define WL127X_IFTYPE_MR_VER    5
 #define WL127X_MAJOR_MR_VER     7
 #define WL127X_SUBTYPE_MR_VER   WLCORE_FW_VER_IGNORE
-#define WL127X_MINOR_MR_VER     115
+#define WL127X_MINOR_MR_VER     42
 
 /* FW chip version for wl128x */
 #define WL128X_CHIP_VER         7
@@ -49,7 +49,7 @@
 #define WL128X_IFTYPE_SR_VER    3
 #define WL128X_MAJOR_SR_VER     10
 #define WL128X_SUBTYPE_SR_VER   WLCORE_FW_VER_IGNORE
-#define WL128X_MINOR_SR_VER     115
+#define WL128X_MINOR_SR_VER     133
 /* minimum multi-role FW version for wl128x */
 #define WL128X_IFTYPE_MR_VER    5
 #define WL128X_MAJOR_MR_VER     7
diff --git a/drivers/net/wireless/ti/wl18xx/scan.c b/drivers/net/wireless/ti/wl18xx/scan.c
index 09d944505ac0..2b642f8c9266 100644
--- a/drivers/net/wireless/ti/wl18xx/scan.c
+++ b/drivers/net/wireless/ti/wl18xx/scan.c
@@ -34,7 +34,7 @@ static void wl18xx_adjust_channels(struct wl18xx_cmd_scan_params *cmd,
         memcpy(cmd->channels_2, cmd_channels->channels_2,
                sizeof(cmd->channels_2));
         memcpy(cmd->channels_5, cmd_channels->channels_5,
-               sizeof(cmd->channels_2));
+               sizeof(cmd->channels_5));
         /* channels_4 are not supported, so no need to copy them */
 }
 
diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c
index 37984e6d4e99..8c20935d72c9 100644
--- a/drivers/net/xen-netback/netback.c
+++ b/drivers/net/xen-netback/netback.c
@@ -662,7 +662,7 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
 {
         struct xenvif *vif = NULL, *tmp;
         s8 status;
-        u16 irq, flags;
+        u16 flags;
         struct xen_netif_rx_response *resp;
         struct sk_buff_head rxq;
         struct sk_buff *skb;
@@ -771,13 +771,13 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
                                          sco->meta_slots_used);
 
                 RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(&vif->rx, ret);
-                irq = vif->irq;
-                if (ret && list_empty(&vif->notify_list))
-                        list_add_tail(&vif->notify_list, &notify);
 
                 xenvif_notify_tx_completion(vif);
 
-                xenvif_put(vif);
+                if (ret && list_empty(&vif->notify_list))
+                        list_add_tail(&vif->notify_list, &notify);
+                else
+                        xenvif_put(vif);
                 npo.meta_cons += sco->meta_slots_used;
                 dev_kfree_skb(skb);
         }
@@ -785,6 +785,7 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
         list_for_each_entry_safe(vif, tmp, &notify, notify_list) {
                 notify_remote_via_irq(vif->irq);
                 list_del_init(&vif->notify_list);
+                xenvif_put(vif);
         }
 
         /* More work to do? */
diff --git a/drivers/of/base.c b/drivers/of/base.c
index f53b992f060a..a6f584a7f4a1 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -192,14 +192,15 @@ EXPORT_SYMBOL(of_find_property);
 struct device_node *of_find_all_nodes(struct device_node *prev)
 {
         struct device_node *np;
+        unsigned long flags;
 
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         np = prev ? prev->allnext : of_allnodes;
         for (; np != NULL; np = np->allnext)
                 if (of_node_get(np))
                         break;
         of_node_put(prev);
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         return np;
 }
 EXPORT_SYMBOL(of_find_all_nodes);
@@ -421,8 +422,9 @@ struct device_node *of_get_next_available_child(const struct device_node *node,
         struct device_node *prev)
 {
         struct device_node *next;
+        unsigned long flags;
 
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         next = prev ? prev->sibling : node->child;
         for (; next; next = next->sibling) {
                 if (!__of_device_is_available(next))
@@ -431,7 +433,7 @@ struct device_node *of_get_next_available_child(const struct device_node *node,
                         break;
         }
         of_node_put(prev);
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         return next;
 }
 EXPORT_SYMBOL(of_get_next_available_child);
@@ -735,13 +737,14 @@ EXPORT_SYMBOL_GPL(of_modalias_node);
 struct device_node *of_find_node_by_phandle(phandle handle)
 {
         struct device_node *np;
+        unsigned long flags;
 
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         for (np = of_allnodes; np; np = np->allnext)
                 if (np->phandle == handle)
                         break;
         of_node_get(np);
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         return np;
 }
 EXPORT_SYMBOL(of_find_node_by_phandle);
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index f8a2ae413c7f..636a882b406e 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -5,8 +5,6 @@
 if ARCH_SHMOBILE || SUPERH
 
 config PINCTRL_SH_PFC
-        # XXX move off the gpio dependency
-        depends on GPIOLIB
         select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
         select PINMUX
         select PINCONF
@@ -32,11 +30,21 @@ config PINCTRL_PFC_R8A7740
         depends on ARCH_R8A7740
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7778
+        def_bool y
+        depends on ARCH_R8A7778
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A7779
         def_bool y
         depends on ARCH_R8A7779
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7790
+        def_bool y
+        depends on ARCH_R8A7790
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_SH7203
         def_bool y
         depends on CPU_SUBTYPE_SH7203
@@ -64,6 +72,7 @@ config PINCTRL_PFC_SH73A0
         def_bool y
         depends on ARCH_SH73A0
         select PINCTRL_SH_PFC
+        select REGULATOR
 
 config PINCTRL_PFC_SH7720
         def_bool y
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 211cd8e98a8a..5e0c222c12d7 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -5,7 +5,9 @@ endif
 obj-$(CONFIG_PINCTRL_SH_PFC)    += sh-pfc.o
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)       += pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)       += pfc-r8a7740.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7778)       += pfc-r8a7778.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7779)       += pfc-r8a7779.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7790)       += pfc-r8a7790.o
 obj-$(CONFIG_PINCTRL_PFC_SH7203)        += pfc-sh7203.o
 obj-$(CONFIG_PINCTRL_PFC_SH7264)        += pfc-sh7264.o
 obj-$(CONFIG_PINCTRL_PFC_SH7269)        += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index b551336924a5..3b2fd43ff294 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -372,6 +372,12 @@ static int sh_pfc_probe(struct platform_device *pdev)
 
         spin_lock_init(&pfc->lock);
 
+        if (info->ops && info->ops->init) {
+                ret = info->ops->init(pfc);
+                if (ret < 0)
+                        return ret;
+        }
+
         pinctrl_provide_dummies();
 
         /*
@@ -379,7 +385,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
          */
         ret = sh_pfc_register_pinctrl(pfc);
         if (unlikely(ret != 0))
-                return ret;
+                goto error;
 
 #ifdef CONFIG_GPIO_SH_PFC
         /*
@@ -401,6 +407,11 @@ static int sh_pfc_probe(struct platform_device *pdev)
         dev_info(pfc->dev, "%s support registered\n", info->name);
 
         return 0;
+
+error:
+        if (info->ops && info->ops->exit)
+                info->ops->exit(pfc);
+        return ret;
 }
 
 static int sh_pfc_remove(struct platform_device *pdev)
@@ -412,6 +423,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
 #endif
         sh_pfc_unregister_pinctrl(pfc);
 
+        if (pfc->info->ops && pfc->info->ops->exit)
+                pfc->info->ops->exit(pfc);
+
         platform_set_drvdata(pdev, NULL);
 
         return 0;
@@ -424,9 +438,15 @@ static const struct platform_device_id sh_pfc_id_table[] = {
 #ifdef CONFIG_PINCTRL_PFC_R8A7740
         { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7778
+        { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A7779
         { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
+        { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_SH7203
         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 #endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 89cb4289d761..f02ba1dde3a0 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -11,6 +11,7 @@
 #define __SH_PFC_CORE_H__
 
 #include <linux/compiler.h>
+#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include "sh_pfc.h"
@@ -27,6 +28,7 @@ struct sh_pfc_pinctrl;
 struct sh_pfc {
         struct device *dev;
         const struct sh_pfc_soc_info *info;
+        void *soc_data;
         spinlock_t lock;
 
         unsigned int num_windows;
@@ -56,7 +58,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
 
 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index bbd87d29bfd0..f6ea47c433b3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -18,10 +18,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/r8a7740.h>
 #include <mach/irqs.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
@@ -30,6 +34,29 @@
         PORT_10(fn, pfx##20, sfx),                                      \
         PORT_1(fn, pfx##210, sfx),      PORT_1(fn, pfx##211, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)                                           \
+        [gpio] = {                                                      \
+                .name = __stringify(PORT##gpio),                        \
+                .enum_id = PORT##gpio##_DATA,                           \
+        }
+
+#define IRQC_PIN_MUX(irq, pin)                                          \
+static const unsigned int intc_irq##irq##_pins[] = {                    \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_mux[] = {                     \
+        IRQ##irq##_MARK,                                                \
+}
+
+#define IRQC_PINS_MUX(irq, idx, pin)                                    \
+static const unsigned int intc_irq##irq##_##idx##_pins[] = {            \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_##idx##_mux[] = {             \
+        IRQ##irq##_PORT##pin##_MARK,                                    \
+}
+
 enum {
         PINMUX_RESERVED = 0,
 
@@ -43,16 +70,6 @@ enum {
         PORT_ALL(IN),
         PINMUX_INPUT_END,
 
-        /* PORT0_IN_PU -> PORT211_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-
-        /* PORT0_IN_PD -> PORT211_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-
         /* PORT0_OUT -> PORT211_OUT */
         PINMUX_OUTPUT_BEGIN,
         PORT_ALL(OUT),
@@ -261,8 +278,6 @@ enum {
         SCIFB_CTS_PORT173_MARK,
 
         /* LCD0 */
-        LCDC0_SELECT_MARK,
-
         LCD0_D0_MARK,   LCD0_D1_MARK,   LCD0_D2_MARK,   LCD0_D3_MARK,
         LCD0_D4_MARK,   LCD0_D5_MARK,   LCD0_D6_MARK,   LCD0_D7_MARK,
         LCD0_D8_MARK,   LCD0_D9_MARK,   LCD0_D10_MARK,  LCD0_D11_MARK,
@@ -285,8 +300,6 @@ enum {
         LCD0_LCLK_PORT102_MARK,
 
         /* LCD1 */
-        LCDC1_SELECT_MARK,
-
         LCD1_D0_MARK,   LCD1_D1_MARK,   LCD1_D2_MARK,   LCD1_D3_MARK,
         LCD1_D4_MARK,   LCD1_D5_MARK,   LCD1_D6_MARK,   LCD1_D7_MARK,
         LCD1_D8_MARK,   LCD1_D9_MARK,   LCD1_D10_MARK,  LCD1_D11_MARK,
@@ -577,137 +590,11 @@ enum {
         PINMUX_MARK_END,
 };
 
+#define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
+
 static const pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-
-        /* I/O and Pull U/D */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_IO_PD(2),             PORT_DATA_IO_PD(3),
-        PORT_DATA_IO_PD(4),             PORT_DATA_IO_PD(5),
-        PORT_DATA_IO_PD(6),             PORT_DATA_IO(7),
-        PORT_DATA_IO(8),                PORT_DATA_IO(9),
-
-        PORT_DATA_IO_PD(10),            PORT_DATA_IO_PD(11),
-        PORT_DATA_IO_PD(12),            PORT_DATA_IO_PU_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_IO_PD(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_IO(18),               PORT_DATA_IO_PU(19),
-
-        PORT_DATA_IO_PU_PD(20),         PORT_DATA_IO_PD(21),
-        PORT_DATA_IO_PU_PD(22),         PORT_DATA_IO(23),
-        PORT_DATA_IO_PU(24),            PORT_DATA_IO_PU(25),
-        PORT_DATA_IO_PU(26),            PORT_DATA_IO_PU(27),
-        PORT_DATA_IO_PU(28),            PORT_DATA_IO_PU(29),
-
-        PORT_DATA_IO_PU(30),            PORT_DATA_IO_PD(31),
-        PORT_DATA_IO_PD(32),            PORT_DATA_IO_PD(33),
-        PORT_DATA_IO_PD(34),            PORT_DATA_IO_PU(35),
-        PORT_DATA_IO_PU(36),            PORT_DATA_IO_PD(37),
-        PORT_DATA_IO_PU(38),            PORT_DATA_IO_PD(39),
-
-        PORT_DATA_IO_PU_PD(40),         PORT_DATA_IO_PD(41),
-        PORT_DATA_IO_PD(42),            PORT_DATA_IO_PU_PD(43),
-        PORT_DATA_IO_PU_PD(44),         PORT_DATA_IO_PU_PD(45),
-        PORT_DATA_IO_PU_PD(46),         PORT_DATA_IO_PU_PD(47),
-        PORT_DATA_IO_PU_PD(48),         PORT_DATA_IO_PU_PD(49),
-
-        PORT_DATA_IO_PU_PD(50),         PORT_DATA_IO_PD(51),
-        PORT_DATA_IO_PD(52),            PORT_DATA_IO_PD(53),
-        PORT_DATA_IO_PD(54),            PORT_DATA_IO_PU_PD(55),
-        PORT_DATA_IO_PU_PD(56),         PORT_DATA_IO_PU_PD(57),
-        PORT_DATA_IO_PU_PD(58),         PORT_DATA_IO_PU_PD(59),
-
-        PORT_DATA_IO_PU_PD(60),         PORT_DATA_IO_PD(61),
-        PORT_DATA_IO_PD(62),            PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PD(64),            PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66),         PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68),         PORT_DATA_IO_PU_PD(69),
-
-        PORT_DATA_IO_PU_PD(70),         PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72),         PORT_DATA_IO_PU_PD(73),
-        PORT_DATA_IO_PU_PD(74),         PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO(82),               PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO(84),               PORT_DATA_IO_PD(85),
-        PORT_DATA_IO_PD(86),            PORT_DATA_IO_PD(87),
-        PORT_DATA_IO_PD(88),            PORT_DATA_IO_PD(89),
-
-        PORT_DATA_IO_PD(90),            PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU_PD(96),         PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_IO_PU_PD(99),
-
-        PORT_DATA_IO_PU_PD(100),        PORT_DATA_IO(101),
-        PORT_DATA_IO_PU(102),           PORT_DATA_IO_PU_PD(103),
-        PORT_DATA_IO_PU(104),           PORT_DATA_IO_PU(105),
-        PORT_DATA_IO_PU_PD(106),        PORT_DATA_IO(107),
-        PORT_DATA_IO(108),              PORT_DATA_IO(109),
-
-        PORT_DATA_IO(110),              PORT_DATA_IO(111),
-        PORT_DATA_IO(112),              PORT_DATA_IO(113),
-        PORT_DATA_IO_PU_PD(114),        PORT_DATA_IO(115),
-        PORT_DATA_IO_PD(116),           PORT_DATA_IO_PD(117),
-        PORT_DATA_IO_PD(118),           PORT_DATA_IO_PD(119),
-
-        PORT_DATA_IO_PD(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO(125),
-        PORT_DATA_IO(126),              PORT_DATA_IO(127),
-        PORT_DATA_IO(128),              PORT_DATA_IO(129),
-
-        PORT_DATA_IO(130),              PORT_DATA_IO(131),
-        PORT_DATA_IO(132),              PORT_DATA_IO(133),
-        PORT_DATA_IO(134),              PORT_DATA_IO(135),
-        PORT_DATA_IO(136),              PORT_DATA_IO(137),
-        PORT_DATA_IO(138),              PORT_DATA_IO(139),
-
-        PORT_DATA_IO(140),              PORT_DATA_IO(141),
-        PORT_DATA_IO_PU(142),           PORT_DATA_IO_PU(143),
-        PORT_DATA_IO_PU(144),           PORT_DATA_IO_PU(145),
-        PORT_DATA_IO_PU(146),           PORT_DATA_IO_PU(147),
-        PORT_DATA_IO_PU(148),           PORT_DATA_IO_PU(149),
-
-        PORT_DATA_IO_PU(150),           PORT_DATA_IO_PU(151),
-        PORT_DATA_IO_PU(152),           PORT_DATA_IO_PU(153),
-        PORT_DATA_IO_PU(154),           PORT_DATA_IO_PU(155),
-        PORT_DATA_IO_PU(156),           PORT_DATA_IO_PU(157),
-        PORT_DATA_IO_PD(158),           PORT_DATA_IO_PD(159),
-
-        PORT_DATA_IO_PU_PD(160),        PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_IO_PD(164),           PORT_DATA_IO_PD(165),
-        PORT_DATA_IO_PU(166),           PORT_DATA_IO_PU(167),
-        PORT_DATA_IO_PU(168),           PORT_DATA_IO_PU(169),
-
-        PORT_DATA_IO_PU(170),           PORT_DATA_IO_PU(171),
-        PORT_DATA_IO_PD(172),           PORT_DATA_IO_PD(173),
-        PORT_DATA_IO_PD(174),           PORT_DATA_IO_PD(175),
-        PORT_DATA_IO_PU(176),           PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU(178),           PORT_DATA_IO_PD(179),
-
-        PORT_DATA_IO_PD(180),           PORT_DATA_IO_PU(181),
-        PORT_DATA_IO_PU(182),           PORT_DATA_IO(183),
-        PORT_DATA_IO_PD(184),           PORT_DATA_IO_PD(185),
-        PORT_DATA_IO_PD(186),           PORT_DATA_IO_PD(187),
-        PORT_DATA_IO_PD(188),           PORT_DATA_IO_PD(189),
-
-        PORT_DATA_IO_PD(190),           PORT_DATA_IO_PD(191),
-        PORT_DATA_IO_PD(192),           PORT_DATA_IO_PU_PD(193),
-        PORT_DATA_IO_PU_PD(194),        PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PU_PD(196),        PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PU_PD(198),        PORT_DATA_IO_PU_PD(199),
-
-        PORT_DATA_IO_PU_PD(200),        PORT_DATA_IO_PU(201),
-        PORT_DATA_IO_PU_PD(202),        PORT_DATA_IO(203),
-        PORT_DATA_IO_PU_PD(204),        PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206),        PORT_DATA_IO_PU_PD(207),
-        PORT_DATA_IO_PU_PD(208),        PORT_DATA_IO_PD(209),
-
-        PORT_DATA_IO_PD(210),           PORT_DATA_IO_PD(211),
+        PINMUX_DATA_GP_ALL(),
 
         /* Port0 */
         PINMUX_DATA(DBGMDT2_MARK,               PORT0_FN1),
@@ -986,7 +873,7 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(IRQ27_PORT57_MARK,          PORT57_FN0,     MSEL1CR_27_1),
 
         /* Port58 */
-        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1),
+        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1,     MSEL3CR_6_0),
         PINMUX_DATA(KEYOUT7_MARK,               PORT58_FN3),
         PINMUX_DATA(KEYIN0_PORT58_MARK,         PORT58_FN4,     MSEL4CR_18_1),
         PINMUX_DATA(DV_D0_MARK,                 PORT58_FN6),
@@ -1633,10 +1520,6 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(IRQ16_PORT211_MARK,         PORT211_FN0,    MSEL1CR_16_1),
         PINMUX_DATA(HDMI_CEC_MARK,              PORT211_FN1),
 
-        /* LCDC select */
-        PINMUX_DATA(LCDC0_SELECT_MARK,                          MSEL3CR_6_0),
-        PINMUX_DATA(LCDC1_SELECT_MARK,                          MSEL3CR_6_1),
-
         /* SDENC */
         PINMUX_DATA(SDENC_CPG_MARK,                             MSEL4CR_19_0),
         PINMUX_DATA(SDENC_DV_CLKI_MARK,                         MSEL4CR_19_1),
@@ -1654,9 +1537,565 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,                    MSEL5CR_30_1,   MSEL5CR_29_0),
 };
 
+#define R8A7740_PIN(pin, cfgs)                                          \
+        {                                                               \
+                .name = __stringify(PORT##pin),                         \
+                .enum_id = PORT##pin##_DATA,                            \
+                .configs = cfgs,                                        \
+        }
+
+#define __I             (SH_PFC_PIN_CFG_INPUT)
+#define __O             (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU            (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define R8A7740_PIN_I_PD(pin)           R8A7740_PIN(pin, __I | __PD)
+#define R8A7740_PIN_I_PU(pin)           R8A7740_PIN(pin, __I | __PU)
+#define R8A7740_PIN_I_PU_PD(pin)                R8A7740_PIN(pin, __I | __PUD)
+#define R8A7740_PIN_IO(pin)             R8A7740_PIN(pin, __IO)
+#define R8A7740_PIN_IO_PD(pin)          R8A7740_PIN(pin, __IO | __PD)
+#define R8A7740_PIN_IO_PU(pin)          R8A7740_PIN(pin, __IO | __PU)
+#define R8A7740_PIN_IO_PU_PD(pin)       R8A7740_PIN(pin, __IO | __PUD)
+#define R8A7740_PIN_O(pin)              R8A7740_PIN(pin, __O)
+#define R8A7740_PIN_O_PU_PD(pin)                R8A7740_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-        GPIO_PORT_ALL(),
+        /* Table 56-1 (I/O and Pull U/D) */
+        R8A7740_PIN_IO_PD(0),           R8A7740_PIN_IO_PD(1),
+        R8A7740_PIN_IO_PD(2),           R8A7740_PIN_IO_PD(3),
+        R8A7740_PIN_IO_PD(4),           R8A7740_PIN_IO_PD(5),
+        R8A7740_PIN_IO_PD(6),           R8A7740_PIN_IO(7),
+        R8A7740_PIN_IO(8),              R8A7740_PIN_IO(9),
+        R8A7740_PIN_IO_PD(10),          R8A7740_PIN_IO_PD(11),
+        R8A7740_PIN_IO_PD(12),          R8A7740_PIN_IO_PU_PD(13),
+        R8A7740_PIN_IO_PD(14),          R8A7740_PIN_IO_PD(15),
+        R8A7740_PIN_IO_PD(16),          R8A7740_PIN_IO_PD(17),
+        R8A7740_PIN_IO(18),             R8A7740_PIN_IO_PU(19),
+        R8A7740_PIN_IO_PU_PD(20),       R8A7740_PIN_IO_PD(21),
+        R8A7740_PIN_IO_PU_PD(22),       R8A7740_PIN_IO(23),
+        R8A7740_PIN_IO_PU(24),          R8A7740_PIN_IO_PU(25),
+        R8A7740_PIN_IO_PU(26),          R8A7740_PIN_IO_PU(27),
+        R8A7740_PIN_IO_PU(28),          R8A7740_PIN_IO_PU(29),
+        R8A7740_PIN_IO_PU(30),          R8A7740_PIN_IO_PD(31),
+        R8A7740_PIN_IO_PD(32),          R8A7740_PIN_IO_PD(33),
+        R8A7740_PIN_IO_PD(34),          R8A7740_PIN_IO_PU(35),
+        R8A7740_PIN_IO_PU(36),          R8A7740_PIN_IO_PD(37),
+        R8A7740_PIN_IO_PU(38),          R8A7740_PIN_IO_PD(39),
+        R8A7740_PIN_IO_PU_PD(40),       R8A7740_PIN_IO_PD(41),
+        R8A7740_PIN_IO_PD(42),          R8A7740_PIN_IO_PU_PD(43),
+        R8A7740_PIN_IO_PU_PD(44),       R8A7740_PIN_IO_PU_PD(45),
+        R8A7740_PIN_IO_PU_PD(46),       R8A7740_PIN_IO_PU_PD(47),
+        R8A7740_PIN_IO_PU_PD(48),       R8A7740_PIN_IO_PU_PD(49),
+        R8A7740_PIN_IO_PU_PD(50),       R8A7740_PIN_IO_PD(51),
+        R8A7740_PIN_IO_PD(52),          R8A7740_PIN_IO_PD(53),
+        R8A7740_PIN_IO_PD(54),          R8A7740_PIN_IO_PU_PD(55),
+        R8A7740_PIN_IO_PU_PD(56),       R8A7740_PIN_IO_PU_PD(57),
+        R8A7740_PIN_IO_PU_PD(58),       R8A7740_PIN_IO_PU_PD(59),
+        R8A7740_PIN_IO_PU_PD(60),       R8A7740_PIN_IO_PD(61),
+        R8A7740_PIN_IO_PD(62),          R8A7740_PIN_IO_PD(63),
+        R8A7740_PIN_IO_PD(64),          R8A7740_PIN_IO_PD(65),
+        R8A7740_PIN_IO_PU_PD(66),       R8A7740_PIN_IO_PU_PD(67),
+        R8A7740_PIN_IO_PU_PD(68),       R8A7740_PIN_IO_PU_PD(69),
+        R8A7740_PIN_IO_PU_PD(70),       R8A7740_PIN_IO_PU_PD(71),
+        R8A7740_PIN_IO_PU_PD(72),       R8A7740_PIN_IO_PU_PD(73),
+        R8A7740_PIN_IO_PU_PD(74),       R8A7740_PIN_IO_PU_PD(75),
+        R8A7740_PIN_IO_PU_PD(76),       R8A7740_PIN_IO_PU_PD(77),
+        R8A7740_PIN_IO_PU_PD(78),       R8A7740_PIN_IO_PU_PD(79),
+        R8A7740_PIN_IO_PU_PD(80),       R8A7740_PIN_IO_PU_PD(81),
+        R8A7740_PIN_IO(82),             R8A7740_PIN_IO_PU_PD(83),
+        R8A7740_PIN_IO(84),             R8A7740_PIN_IO_PD(85),
+        R8A7740_PIN_IO_PD(86),          R8A7740_PIN_IO_PD(87),
+        R8A7740_PIN_IO_PD(88),          R8A7740_PIN_IO_PD(89),
+        R8A7740_PIN_IO_PD(90),          R8A7740_PIN_IO_PU_PD(91),
+        R8A7740_PIN_IO_PU_PD(92),       R8A7740_PIN_IO_PU_PD(93),
+        R8A7740_PIN_IO_PU_PD(94),       R8A7740_PIN_IO_PU_PD(95),
+        R8A7740_PIN_IO_PU_PD(96),       R8A7740_PIN_IO_PU_PD(97),
+        R8A7740_PIN_IO_PU_PD(98),       R8A7740_PIN_IO_PU_PD(99),
+        R8A7740_PIN_IO_PU_PD(100),      R8A7740_PIN_IO(101),
+        R8A7740_PIN_IO_PU(102),         R8A7740_PIN_IO_PU_PD(103),
+        R8A7740_PIN_IO_PU(104),         R8A7740_PIN_IO_PU(105),
+        R8A7740_PIN_IO_PU_PD(106),      R8A7740_PIN_IO(107),
+        R8A7740_PIN_IO(108),            R8A7740_PIN_IO(109),
+        R8A7740_PIN_IO(110),            R8A7740_PIN_IO(111),
+        R8A7740_PIN_IO(112),            R8A7740_PIN_IO(113),
+        R8A7740_PIN_IO_PU_PD(114),      R8A7740_PIN_IO(115),
+        R8A7740_PIN_IO_PD(116),         R8A7740_PIN_IO_PD(117),
+        R8A7740_PIN_IO_PD(118),         R8A7740_PIN_IO_PD(119),
+        R8A7740_PIN_IO_PD(120),         R8A7740_PIN_IO_PD(121),
+        R8A7740_PIN_IO_PD(122),         R8A7740_PIN_IO_PD(123),
+        R8A7740_PIN_IO_PD(124),         R8A7740_PIN_IO(125),
+        R8A7740_PIN_IO(126),            R8A7740_PIN_IO(127),
+        R8A7740_PIN_IO(128),            R8A7740_PIN_IO(129),
+        R8A7740_PIN_IO(130),            R8A7740_PIN_IO(131),
+        R8A7740_PIN_IO(132),            R8A7740_PIN_IO(133),
+        R8A7740_PIN_IO(134),            R8A7740_PIN_IO(135),
+        R8A7740_PIN_IO(136),            R8A7740_PIN_IO(137),
+        R8A7740_PIN_IO(138),            R8A7740_PIN_IO(139),
+        R8A7740_PIN_IO(140),            R8A7740_PIN_IO(141),
+        R8A7740_PIN_IO_PU(142),         R8A7740_PIN_IO_PU(143),
+        R8A7740_PIN_IO_PU(144),         R8A7740_PIN_IO_PU(145),
+        R8A7740_PIN_IO_PU(146),         R8A7740_PIN_IO_PU(147),
+        R8A7740_PIN_IO_PU(148),         R8A7740_PIN_IO_PU(149),
+        R8A7740_PIN_IO_PU(150),         R8A7740_PIN_IO_PU(151),
+        R8A7740_PIN_IO_PU(152),         R8A7740_PIN_IO_PU(153),
+        R8A7740_PIN_IO_PU(154),         R8A7740_PIN_IO_PU(155),
+        R8A7740_PIN_IO_PU(156),         R8A7740_PIN_IO_PU(157),
+        R8A7740_PIN_IO_PD(158),         R8A7740_PIN_IO_PD(159),
+        R8A7740_PIN_IO_PU_PD(160),      R8A7740_PIN_IO_PD(161),
+        R8A7740_PIN_IO_PD(162),         R8A7740_PIN_IO_PD(163),
+        R8A7740_PIN_IO_PD(164),         R8A7740_PIN_IO_PD(165),
+        R8A7740_PIN_IO_PU(166),         R8A7740_PIN_IO_PU(167),
+        R8A7740_PIN_IO_PU(168),         R8A7740_PIN_IO_PU(169),
+        R8A7740_PIN_IO_PU(170),         R8A7740_PIN_IO_PU(171),
+        R8A7740_PIN_IO_PD(172),         R8A7740_PIN_IO_PD(173),
+        R8A7740_PIN_IO_PD(174),         R8A7740_PIN_IO_PD(175),
+        R8A7740_PIN_IO_PU(176),         R8A7740_PIN_IO_PU_PD(177),
+        R8A7740_PIN_IO_PU(178),         R8A7740_PIN_IO_PD(179),
+        R8A7740_PIN_IO_PD(180),         R8A7740_PIN_IO_PU(181),
+        R8A7740_PIN_IO_PU(182),         R8A7740_PIN_IO(183),
+        R8A7740_PIN_IO_PD(184),         R8A7740_PIN_IO_PD(185),
+        R8A7740_PIN_IO_PD(186),         R8A7740_PIN_IO_PD(187),
+        R8A7740_PIN_IO_PD(188),         R8A7740_PIN_IO_PD(189),
+        R8A7740_PIN_IO_PD(190),         R8A7740_PIN_IO_PD(191),
+        R8A7740_PIN_IO_PD(192),         R8A7740_PIN_IO_PU_PD(193),
+        R8A7740_PIN_IO_PU_PD(194),      R8A7740_PIN_IO_PD(195),
+        R8A7740_PIN_IO_PU_PD(196),      R8A7740_PIN_IO_PD(197),
+        R8A7740_PIN_IO_PU_PD(198),      R8A7740_PIN_IO_PU_PD(199),
+        R8A7740_PIN_IO_PU_PD(200),      R8A7740_PIN_IO_PU(201),
+        R8A7740_PIN_IO_PU_PD(202),      R8A7740_PIN_IO(203),
+        R8A7740_PIN_IO_PU_PD(204),      R8A7740_PIN_IO_PU_PD(205),
+        R8A7740_PIN_IO_PU_PD(206),      R8A7740_PIN_IO_PU_PD(207),
+        R8A7740_PIN_IO_PU_PD(208),      R8A7740_PIN_IO_PD(209),
+        R8A7740_PIN_IO_PD(210),         R8A7740_PIN_IO_PD(211),
+};
+
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+        /* D[0:7] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+};
+static const unsigned int bsc_data8_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+        /* D[0:15] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+        149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int bsc_data16_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_data32_pins[] = {
+        /* D[0:31] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+        149, 148, 147, 146, 145, 144, 143, 142,
+        171, 170, 169, 168, 167, 166, 173, 172,
+        165, 164, 163, 162, 161, 160, 159, 158,
+};
+static const unsigned int bsc_data32_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+        D16_MARK, D17_MARK, D18_MARK, D19_MARK,
+        D20_MARK, D21_MARK, D22_MARK, D23_MARK,
+        D24_MARK, D25_MARK, D26_MARK, D27_MARK,
+        D28_MARK, D29_MARK, D30_MARK, D31_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+        /* CS */
+        109,
+};
+static const unsigned int bsc_cs0_mux[] = {
+        CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+        /* CS */
+        110,
+};
+static const unsigned int bsc_cs2_mux[] = {
+        CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+        /* CS */
+        111,
+};
+static const unsigned int bsc_cs4_mux[] = {
+        CS4_MARK,
+};
+static const unsigned int bsc_cs5a_0_pins[] = {
+        /* CS */
+        105,
+};
+static const unsigned int bsc_cs5a_0_mux[] = {
+        CS5A_PORT105_MARK,
+};
+static const unsigned int bsc_cs5a_1_pins[] = {
+        /* CS */
+        19,
+};
+static const unsigned int bsc_cs5a_1_mux[] = {
+        CS5A_PORT19_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+        /* CS */
+        103,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+        CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+        /* CS */
+        104,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+        CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+        /* RD, WE[0] */
+        115, 113,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+        /* RD, WE[0:1] */
+        115, 113, 112,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_rd_we32_pins[] = {
+        /* RD, WE[0:3] */
+        115, 113, 112, 108, 107,
+};
+static const unsigned int bsc_rd_we32_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+        /* BS */
+        175,
+};
+static const unsigned int bsc_bs_mux[] = {
+        BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+        /* RDWR */
+        114,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+        RDWR_MARK,
+};
+/* - CEU0 ------------------------------------------------------------------- */
+static const unsigned int ceu0_data_0_7_pins[] = {
+        /* D[0:7] */
+        34, 33, 32, 31, 30, 29, 28, 27,
+};
+static const unsigned int ceu0_data_0_7_mux[] = {
+        VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
+        VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
+};
+static const unsigned int ceu0_data_8_15_0_pins[] = {
+        /* D[8:15] */
+        182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu0_data_8_15_0_mux[] = {
+        VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+        VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
+        VIO0_D15_PORT24_MARK,
+};
+static const unsigned int ceu0_data_8_15_1_pins[] = {
+        /* D[8:15] */
+        182, 181, 180, 179, 178, 22, 95, 96,
+};
+static const unsigned int ceu0_data_8_15_1_mux[] = {
+        VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+        VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
+        VIO0_D15_PORT96_MARK,
+};
+static const unsigned int ceu0_clk_0_pins[] = {
+        /* CKO */
+        36,
+};
+static const unsigned int ceu0_clk_0_mux[] = {
+        VIO_CKO_MARK,
+};
+static const unsigned int ceu0_clk_1_pins[] = {
+        /* CKO */
+        14,
+};
+static const unsigned int ceu0_clk_1_mux[] = {
+        VIO_CKO1_MARK,
+};
+static const unsigned int ceu0_clk_2_pins[] = {
+        /* CKO */
+        15,
+};
+static const unsigned int ceu0_clk_2_mux[] = {
+        VIO_CKO2_MARK,
+};
+static const unsigned int ceu0_sync_pins[] = {
+        /* CLK, VD, HD */
+        35, 39, 37,
+};
+static const unsigned int ceu0_sync_mux[] = {
+        VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
+};
+static const unsigned int ceu0_field_pins[] = {
+        /* FIELD */
+        38,
+};
+static const unsigned int ceu0_field_mux[] = {
+        VIO0_FIELD_MARK,
+};
+/* - CEU1 ------------------------------------------------------------------- */
+static const unsigned int ceu1_data_pins[] = {
+        /* D[0:7] */
+        182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu1_data_mux[] = {
+        VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
+        VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
+};
+static const unsigned int ceu1_clk_pins[] = {
+        /* CKO */
+        23,
+};
+static const unsigned int ceu1_clk_mux[] = {
+        VIO_CKO_1_MARK,
+};
+static const unsigned int ceu1_sync_pins[] = {
+        /* CLK, VD, HD */
+        197, 198, 160,
+};
+static const unsigned int ceu1_sync_mux[] = {
+        VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
+};
+static const unsigned int ceu1_field_pins[] = {
+        /* FIELD */
+        21,
+};
+static const unsigned int ceu1_field_mux[] = {
+        VIO1_FIELD_MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+        /* CK */
+        11,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+        FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+        /* OMC */
+        10,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+        FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+        /* ILR, IBT */
+        12, 13,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+        FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+        /* OLR, OBT */
+        7, 8,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+        FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_0_pins[] = {
+        /* ISLD */
+        0,
 };
+static const unsigned int fsia_data_in_0_mux[] = {
+        FSIAISLD_PORT0_MARK,
+};
+static const unsigned int fsia_data_in_1_pins[] = {
+        /* ISLD */
+        5,
+};
+static const unsigned int fsia_data_in_1_mux[] = {
+        FSIAISLD_PORT5_MARK,
+};
+static const unsigned int fsia_data_out_0_pins[] = {
+        /* OSLD */
+        9,
+};
+static const unsigned int fsia_data_out_0_mux[] = {
+        FSIAOSLD_MARK,
+};
+static const unsigned int fsia_data_out_1_pins[] = {
+        /* OSLD */
+        0,
+};
+static const unsigned int fsia_data_out_1_mux[] = {
+        FSIAOSLD1_MARK,
+};
+static const unsigned int fsia_data_out_2_pins[] = {
+        /* OSLD */
+        1,
+};
+static const unsigned int fsia_data_out_2_mux[] = {
+        FSIAOSLD2_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+        /* SPDIF */
+        9,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+        FSIASPDIF_PORT9_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+        /* SPDIF */
+        18,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+        FSIASPDIF_PORT18_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+        /* CK */
+        11,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+        FSIBCK_MARK,
+};
+/* - GETHER ----------------------------------------------------------------- */
+static const unsigned int gether_rmii_pins[] = {
+        /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
+        195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
+};
+static const unsigned int gether_rmii_mux[] = {
+        RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
+        RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
+        RMII_MDC_MARK, RMII_MDIO_MARK,
+};
+static const unsigned int gether_mii_pins[] = {
+        /* RXD[0:3], RX_CLK, RX_DV, RX_ER
+         * TXD[0:3], TX_CLK, TX_EN, TX_ER
+         * CRS, COL, MDC, MDIO,
+         */
+        185, 186, 187, 188, 174, 161, 204,
+        171, 170, 169, 168, 184, 183, 203,
+        205, 163, 206, 207,
+};
+static const unsigned int gether_mii_mux[] = {
+        ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+        ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+        ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+        ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+        ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+};
+static const unsigned int gether_gmii_pins[] = {
+        /* RXD[0:7], RX_CLK, RX_DV, RX_ER
+         * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
+         * CRS, COL, MDC, MDIO, REF125CK_MARK,
+         */
+        185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
+        171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
+        205, 163, 206, 207,
+};
+static const unsigned int gether_gmii_mux[] = {
+        ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+        ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
+        ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+        ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+        ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
+        ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+        ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+        RMII_REF125CK_MARK,
+};
+static const unsigned int gether_int_pins[] = {
+        /* PHY_INT */
+        164,
+};
+static const unsigned int gether_int_mux[] = {
+        ET_PHY_INT_MARK,
+};
+static const unsigned int gether_link_pins[] = {
+        /* LINK */
+        177,
+};
+static const unsigned int gether_link_mux[] = {
+        ET_LINK_MARK,
+};
+static const unsigned int gether_wol_pins[] = {
+        /* WOL */
+        175,
+};
+static const unsigned int gether_wol_mux[] = {
+        ET_WOL_MARK,
+};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+        /* HPD, CEC */
+        210, 211,
+};
+static const unsigned int hdmi_mux[] = {
+        HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 0, 2);
+IRQC_PINS_MUX(0, 1, 13);
+IRQC_PIN_MUX(1, 20);
+IRQC_PINS_MUX(2, 0, 11);
+IRQC_PINS_MUX(2, 1, 12);
+IRQC_PINS_MUX(3, 0, 10);
+IRQC_PINS_MUX(3, 1, 14);
+IRQC_PINS_MUX(4, 0, 15);
+IRQC_PINS_MUX(4, 1, 172);
+IRQC_PINS_MUX(5, 0, 0);
+IRQC_PINS_MUX(5, 1, 1);
+IRQC_PINS_MUX(6, 0, 121);
+IRQC_PINS_MUX(6, 1, 173);
+IRQC_PINS_MUX(7, 0, 120);
+IRQC_PINS_MUX(7, 1, 209);
+IRQC_PIN_MUX(8, 119);
+IRQC_PINS_MUX(9, 0, 118);
+IRQC_PINS_MUX(9, 1, 210);
+IRQC_PIN_MUX(10, 19);
+IRQC_PIN_MUX(11, 104);
+IRQC_PINS_MUX(12, 0, 42);
+IRQC_PINS_MUX(12, 1, 97);
+IRQC_PINS_MUX(13, 0, 64);
+IRQC_PINS_MUX(13, 1, 98);
+IRQC_PINS_MUX(14, 0, 63);
+IRQC_PINS_MUX(14, 1, 99);
+IRQC_PINS_MUX(15, 0, 62);
+IRQC_PINS_MUX(15, 1, 100);
+IRQC_PINS_MUX(16, 0, 68);
+IRQC_PINS_MUX(16, 1, 211);
+IRQC_PIN_MUX(17, 69);
+IRQC_PIN_MUX(18, 70);
+IRQC_PIN_MUX(19, 71);
+IRQC_PIN_MUX(20, 67);
+IRQC_PIN_MUX(21, 202);
+IRQC_PIN_MUX(22, 95);
+IRQC_PIN_MUX(23, 96);
+IRQC_PIN_MUX(24, 180);
+IRQC_PIN_MUX(25, 38);
+IRQC_PINS_MUX(26, 0, 58);
+IRQC_PINS_MUX(26, 1, 81);
+IRQC_PINS_MUX(27, 0, 57);
+IRQC_PINS_MUX(27, 1, 168);
+IRQC_PINS_MUX(28, 0, 56);
+IRQC_PINS_MUX(28, 1, 169);
+IRQC_PINS_MUX(29, 0, 50);
+IRQC_PINS_MUX(29, 1, 170);
+IRQC_PINS_MUX(30, 0, 49);
+IRQC_PINS_MUX(30, 1, 171);
+IRQC_PINS_MUX(31, 0, 41);
+IRQC_PINS_MUX(31, 1, 167);
 
 /* - LCD0 ------------------------------------------------------------------- */
 static const unsigned int lcd0_data8_pins[] = {
@@ -1930,6 +2369,260 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
         MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        197, 198,
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        188,
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        194, 193,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        195, 196,
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        185,
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        23, 21,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        200, 201,
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_0_pins[] = {
+        /* SCK */
+        22,
+};
+static const unsigned int scifa2_clk_0_mux[] = {
+        SCIFA2_SCK_PORT22_MARK,
+};
+static const unsigned int scifa2_clk_1_pins[] = {
+        /* SCK */
+        199,
+};
+static const unsigned int scifa2_clk_1_mux[] = {
+        SCIFA2_SCK_PORT199_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        96, 95,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_0_pins[] = {
+        /* RXD, TXD */
+        174, 175,
+};
+static const unsigned int scifa3_data_0_mux[] = {
+        SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
+};
+static const unsigned int scifa3_clk_0_pins[] = {
+        /* SCK */
+        116,
+};
+static const unsigned int scifa3_clk_0_mux[] = {
+        SCIFA3_SCK_PORT116_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        105, 117,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+        SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
+};
+static const unsigned int scifa3_data_1_pins[] = {
+        /* RXD, TXD */
+        159, 160,
+};
+static const unsigned int scifa3_data_1_mux[] = {
+        SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
+};
+static const unsigned int scifa3_clk_1_pins[] = {
+        /* SCK */
+        158,
+};
+static const unsigned int scifa3_clk_1_mux[] = {
+        SCIFA3_SCK_PORT158_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        161, 162,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+        SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_0_pins[] = {
+        /* RXD, TXD */
+        12, 13,
+};
+static const unsigned int scifa4_data_0_mux[] = {
+        SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
+};
+static const unsigned int scifa4_data_1_pins[] = {
+        /* RXD, TXD */
+        204, 203,
+};
+static const unsigned int scifa4_data_1_mux[] = {
+        SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
+};
+static const unsigned int scifa4_data_2_pins[] = {
+        /* RXD, TXD */
+        94, 93,
+};
+static const unsigned int scifa4_data_2_mux[] = {
+        SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
+};
+static const unsigned int scifa4_clk_0_pins[] = {
+        /* SCK */
+        21,
+};
+static const unsigned int scifa4_clk_0_mux[] = {
+        SCIFA4_SCK_PORT21_MARK,
+};
+static const unsigned int scifa4_clk_1_pins[] = {
+        /* SCK */
+        205,
+};
+static const unsigned int scifa4_clk_1_mux[] = {
+        SCIFA4_SCK_PORT205_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_0_pins[] = {
+        /* RXD, TXD */
+        10, 20,
+};
+static const unsigned int scifa5_data_0_mux[] = {
+        SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
+};
+static const unsigned int scifa5_data_1_pins[] = {
+        /* RXD, TXD */
+        207, 208,
+};
+static const unsigned int scifa5_data_1_mux[] = {
+        SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
+};
+static const unsigned int scifa5_data_2_pins[] = {
+        /* RXD, TXD */
+        92, 91,
+};
+static const unsigned int scifa5_data_2_mux[] = {
+        SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
+};
+static const unsigned int scifa5_clk_0_pins[] = {
+        /* SCK */
+        23,
+};
+static const unsigned int scifa5_clk_0_mux[] = {
+        SCIFA5_SCK_PORT23_MARK,
+};
+static const unsigned int scifa5_clk_1_pins[] = {
+        /* SCK */
+        206,
+};
+static const unsigned int scifa5_clk_1_mux[] = {
+        SCIFA5_SCK_PORT206_MARK,
+};
+/* - SCIFA6 ----------------------------------------------------------------- */
+static const unsigned int scifa6_data_pins[] = {
+        /* RXD, TXD */
+        25, 26,
+};
+static const unsigned int scifa6_data_mux[] = {
+        SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
+};
+static const unsigned int scifa6_clk_pins[] = {
+        /* SCK */
+        24,
+};
+static const unsigned int scifa6_clk_mux[] = {
+        SCIFA6_SCK_MARK,
+};
+/* - SCIFA7 ----------------------------------------------------------------- */
+static const unsigned int scifa7_data_pins[] = {
+        /* RXD, TXD */
+        0, 1,
+};
+static const unsigned int scifa7_data_mux[] = {
+        SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_0_pins[] = {
+        /* RXD, TXD */
+        191, 192,
+};
+static const unsigned int scifb_data_0_mux[] = {
+        SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
+};
+static const unsigned int scifb_clk_0_pins[] = {
+        /* SCK */
+        190,
+};
+static const unsigned int scifb_clk_0_mux[] = {
+        SCIFB_SCK_PORT190_MARK,
+};
+static const unsigned int scifb_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        186, 187,
+};
+static const unsigned int scifb_ctrl_0_mux[] = {
+        SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
+};
+static const unsigned int scifb_data_1_pins[] = {
+        /* RXD, TXD */
+        3, 4,
+};
+static const unsigned int scifb_data_1_mux[] = {
+        SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
+};
+static const unsigned int scifb_clk_1_pins[] = {
+        /* SCK */
+        2,
+};
+static const unsigned int scifb_clk_1_mux[] = {
+        SCIFB_SCK_PORT2_MARK,
+};
+static const unsigned int scifb_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        172, 173,
+};
+static const unsigned int scifb_ctrl_1_mux[] = {
+        SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
@@ -2052,8 +2745,141 @@ static const unsigned int sdhi2_wp_1_pins[] = {
 static const unsigned int sdhi2_wp_1_mux[] = {
         SDHI2_WP_PORT25_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        23,
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        21,
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_0_pins[] = {
+        /* TO */
+        66,
+};
+static const unsigned int tpu0_to2_0_mux[] = {
+        TPU0TO2_PORT66_MARK,
+};
+static const unsigned int tpu0_to2_1_pins[] = {
+        /* TO */
+        202,
+};
+static const unsigned int tpu0_to2_1_mux[] = {
+        TPU0TO2_PORT202_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        180,
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(bsc_data8),
+        SH_PFC_PIN_GROUP(bsc_data16),
+        SH_PFC_PIN_GROUP(bsc_data32),
+        SH_PFC_PIN_GROUP(bsc_cs0),
+        SH_PFC_PIN_GROUP(bsc_cs2),
+        SH_PFC_PIN_GROUP(bsc_cs4),
+        SH_PFC_PIN_GROUP(bsc_cs5a_0),
+        SH_PFC_PIN_GROUP(bsc_cs5a_1),
+        SH_PFC_PIN_GROUP(bsc_cs5b),
+        SH_PFC_PIN_GROUP(bsc_cs6a),
+        SH_PFC_PIN_GROUP(bsc_rd_we8),
+        SH_PFC_PIN_GROUP(bsc_rd_we16),
+        SH_PFC_PIN_GROUP(bsc_rd_we32),
+        SH_PFC_PIN_GROUP(bsc_bs),
+        SH_PFC_PIN_GROUP(bsc_rdwr),
+        SH_PFC_PIN_GROUP(ceu0_data_0_7),
+        SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
+        SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
+        SH_PFC_PIN_GROUP(ceu0_clk_0),
+        SH_PFC_PIN_GROUP(ceu0_clk_1),
+        SH_PFC_PIN_GROUP(ceu0_clk_2),
+        SH_PFC_PIN_GROUP(ceu0_sync),
+        SH_PFC_PIN_GROUP(ceu0_field),
+        SH_PFC_PIN_GROUP(ceu1_data),
+        SH_PFC_PIN_GROUP(ceu1_clk),
+        SH_PFC_PIN_GROUP(ceu1_sync),
+        SH_PFC_PIN_GROUP(ceu1_field),
+        SH_PFC_PIN_GROUP(fsia_mclk_in),
+        SH_PFC_PIN_GROUP(fsia_mclk_out),
+        SH_PFC_PIN_GROUP(fsia_sclk_in),
+        SH_PFC_PIN_GROUP(fsia_sclk_out),
+        SH_PFC_PIN_GROUP(fsia_data_in_0),
+        SH_PFC_PIN_GROUP(fsia_data_in_1),
+        SH_PFC_PIN_GROUP(fsia_data_out_0),
+        SH_PFC_PIN_GROUP(fsia_data_out_1),
+        SH_PFC_PIN_GROUP(fsia_data_out_2),
+        SH_PFC_PIN_GROUP(fsia_spdif_0),
+        SH_PFC_PIN_GROUP(fsia_spdif_1),
+        SH_PFC_PIN_GROUP(fsib_mclk_in),
+        SH_PFC_PIN_GROUP(gether_rmii),
+        SH_PFC_PIN_GROUP(gether_mii),
+        SH_PFC_PIN_GROUP(gether_gmii),
+        SH_PFC_PIN_GROUP(gether_int),
+        SH_PFC_PIN_GROUP(gether_link),
+        SH_PFC_PIN_GROUP(gether_wol),
+        SH_PFC_PIN_GROUP(hdmi),
+        SH_PFC_PIN_GROUP(intc_irq0_0),
+        SH_PFC_PIN_GROUP(intc_irq0_1),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2_0),
+        SH_PFC_PIN_GROUP(intc_irq2_1),
+        SH_PFC_PIN_GROUP(intc_irq3_0),
+        SH_PFC_PIN_GROUP(intc_irq3_1),
+        SH_PFC_PIN_GROUP(intc_irq4_0),
+        SH_PFC_PIN_GROUP(intc_irq4_1),
+        SH_PFC_PIN_GROUP(intc_irq5_0),
+        SH_PFC_PIN_GROUP(intc_irq5_1),
+        SH_PFC_PIN_GROUP(intc_irq6_0),
+        SH_PFC_PIN_GROUP(intc_irq6_1),
+        SH_PFC_PIN_GROUP(intc_irq7_0),
+        SH_PFC_PIN_GROUP(intc_irq7_1),
+        SH_PFC_PIN_GROUP(intc_irq8),
+        SH_PFC_PIN_GROUP(intc_irq9_0),
+        SH_PFC_PIN_GROUP(intc_irq9_1),
+        SH_PFC_PIN_GROUP(intc_irq10),
+        SH_PFC_PIN_GROUP(intc_irq11),
+        SH_PFC_PIN_GROUP(intc_irq12_0),
+        SH_PFC_PIN_GROUP(intc_irq12_1),
+        SH_PFC_PIN_GROUP(intc_irq13_0),
+        SH_PFC_PIN_GROUP(intc_irq13_1),
+        SH_PFC_PIN_GROUP(intc_irq14_0),
+        SH_PFC_PIN_GROUP(intc_irq14_1),
+        SH_PFC_PIN_GROUP(intc_irq15_0),
+        SH_PFC_PIN_GROUP(intc_irq15_1),
+        SH_PFC_PIN_GROUP(intc_irq16_0),
+        SH_PFC_PIN_GROUP(intc_irq16_1),
+        SH_PFC_PIN_GROUP(intc_irq17),
+        SH_PFC_PIN_GROUP(intc_irq18),
+        SH_PFC_PIN_GROUP(intc_irq19),
+        SH_PFC_PIN_GROUP(intc_irq20),
+        SH_PFC_PIN_GROUP(intc_irq21),
+        SH_PFC_PIN_GROUP(intc_irq22),
+        SH_PFC_PIN_GROUP(intc_irq23),
+        SH_PFC_PIN_GROUP(intc_irq24),
+        SH_PFC_PIN_GROUP(intc_irq25),
+        SH_PFC_PIN_GROUP(intc_irq26_0),
+        SH_PFC_PIN_GROUP(intc_irq26_1),
+        SH_PFC_PIN_GROUP(intc_irq27_0),
+        SH_PFC_PIN_GROUP(intc_irq27_1),
+        SH_PFC_PIN_GROUP(intc_irq28_0),
+        SH_PFC_PIN_GROUP(intc_irq28_1),
+        SH_PFC_PIN_GROUP(intc_irq29_0),
+        SH_PFC_PIN_GROUP(intc_irq29_1),
+        SH_PFC_PIN_GROUP(intc_irq30_0),
+        SH_PFC_PIN_GROUP(intc_irq30_1),
+        SH_PFC_PIN_GROUP(intc_irq31_0),
+        SH_PFC_PIN_GROUP(intc_irq31_1),
         SH_PFC_PIN_GROUP(lcd0_data8),
         SH_PFC_PIN_GROUP(lcd0_data9),
         SH_PFC_PIN_GROUP(lcd0_data12),
@@ -2084,6 +2910,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(mmc0_data4_1),
         SH_PFC_PIN_GROUP(mmc0_data8_1),
         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk_0),
+        SH_PFC_PIN_GROUP(scifa2_clk_1),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa3_data_0),
+        SH_PFC_PIN_GROUP(scifa3_clk_0),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa3_data_1),
+        SH_PFC_PIN_GROUP(scifa3_clk_1),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa4_data_0),
+        SH_PFC_PIN_GROUP(scifa4_data_1),
+        SH_PFC_PIN_GROUP(scifa4_data_2),
+        SH_PFC_PIN_GROUP(scifa4_clk_0),
+        SH_PFC_PIN_GROUP(scifa4_clk_1),
+        SH_PFC_PIN_GROUP(scifa5_data_0),
+        SH_PFC_PIN_GROUP(scifa5_data_1),
+        SH_PFC_PIN_GROUP(scifa5_data_2),
+        SH_PFC_PIN_GROUP(scifa5_clk_0),
+        SH_PFC_PIN_GROUP(scifa5_clk_1),
+        SH_PFC_PIN_GROUP(scifa6_data),
+        SH_PFC_PIN_GROUP(scifa6_clk),
+        SH_PFC_PIN_GROUP(scifa7_data),
+        SH_PFC_PIN_GROUP(scifb_data_0),
+        SH_PFC_PIN_GROUP(scifb_clk_0),
+        SH_PFC_PIN_GROUP(scifb_ctrl_0),
+        SH_PFC_PIN_GROUP(scifb_data_1),
+        SH_PFC_PIN_GROUP(scifb_clk_1),
+        SH_PFC_PIN_GROUP(scifb_ctrl_1),
         SH_PFC_PIN_GROUP(sdhi0_data1),
         SH_PFC_PIN_GROUP(sdhi0_data4),
         SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -2101,6 +2962,132 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_wp_0),
         SH_PFC_PIN_GROUP(sdhi2_cd_1),
         SH_PFC_PIN_GROUP(sdhi2_wp_1),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2_0),
+        SH_PFC_PIN_GROUP(tpu0_to2_1),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+};
+
+static const char * const bsc_groups[] = {
+        "bsc_data8",
+        "bsc_data16",
+        "bsc_data32",
+        "bsc_cs0",
+        "bsc_cs2",
+        "bsc_cs4",
+        "bsc_cs5a_0",
+        "bsc_cs5a_1",
+        "bsc_cs5b",
+        "bsc_cs6a",
+        "bsc_rd_we8",
+        "bsc_rd_we16",
+        "bsc_rd_we32",
+        "bsc_bs",
+        "bsc_rdwr",
+};
+
+static const char * const ceu0_groups[] = {
+        "ceu0_data_0_7",
+        "ceu0_data_8_15_0",
+        "ceu0_data_8_15_1",
+        "ceu0_clk_0",
+        "ceu0_clk_1",
+        "ceu0_clk_2",
+        "ceu0_sync",
+        "ceu0_field",
+};
+
+static const char * const ceu1_groups[] = {
+        "ceu1_data",
+        "ceu1_clk",
+        "ceu1_sync",
+        "ceu1_field",
+};
+
+static const char * const fsia_groups[] = {
+        "fsia_mclk_in",
+        "fsia_mclk_out",
+        "fsia_sclk_in",
+        "fsia_sclk_out",
+        "fsia_data_in_0",
+        "fsia_data_in_1",
+        "fsia_data_out_0",
+        "fsia_data_out_1",
+        "fsia_data_out_2",
+        "fsia_spdif_0",
+        "fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+        "fsib_mclk_in",
+};
+
+static const char * const gether_groups[] = {
+        "gether_rmii",
+        "gether_mii",
+        "gether_gmii",
+        "gether_int",
+        "gether_link",
+        "gether_wol",
+};
+
+static const char * const hdmi_groups[] = {
+        "hdmi",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0_0",
+        "intc_irq0_1",
+        "intc_irq1",
+        "intc_irq2_0",
+        "intc_irq2_1",
+        "intc_irq3_0",
+        "intc_irq3_1",
+        "intc_irq4_0",
+        "intc_irq4_1",
+        "intc_irq5_0",
+        "intc_irq5_1",
+        "intc_irq6_0",
+        "intc_irq6_1",
+        "intc_irq7_0",
+        "intc_irq7_1",
+        "intc_irq8",
+        "intc_irq9_0",
+        "intc_irq9_1",
+        "intc_irq10",
+        "intc_irq11",
+        "intc_irq12_0",
+        "intc_irq12_1",
+        "intc_irq13_0",
+        "intc_irq13_1",
+        "intc_irq14_0",
+        "intc_irq14_1",
+        "intc_irq15_0",
+        "intc_irq15_1",
+        "intc_irq16_0",
+        "intc_irq16_1",
+        "intc_irq17",
+        "intc_irq18",
+        "intc_irq19",
+        "intc_irq20",
+        "intc_irq21",
+        "intc_irq22",
+        "intc_irq23",
+        "intc_irq24",
+        "intc_irq25",
+        "intc_irq26_0",
+        "intc_irq26_1",
+        "intc_irq27_0",
+        "intc_irq27_1",
+        "intc_irq28_0",
+        "intc_irq28_1",
+        "intc_irq29_0",
+        "intc_irq29_1",
+        "intc_irq30_0",
+        "intc_irq30_1",
+        "intc_irq31_0",
+        "intc_irq31_1",
 };
 
 static const char * const lcd0_groups[] = {
@@ -2142,6 +3129,68 @@ static const char * const mmc0_groups[] = {
         "mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk_0",
+        "scifa2_clk_1",
+        "scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+        "scifa3_data_0",
+        "scifa3_clk_0",
+        "scifa3_ctrl_0",
+        "scifa3_data_1",
+        "scifa3_clk_1",
+        "scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+        "scifa4_data_0",
+        "scifa4_data_1",
+        "scifa4_data_2",
+        "scifa4_clk_0",
+        "scifa4_clk_1",
+};
+
+static const char * const scifa5_groups[] = {
+        "scifa5_data_0",
+        "scifa5_data_1",
+        "scifa5_data_2",
+        "scifa5_clk_0",
+        "scifa5_clk_1",
+};
+
+static const char * const scifa6_groups[] = {
+        "scifa6_data",
+        "scifa6_clk",
+};
+
+static const char * const scifa7_groups[] = {
+        "scifa7_data",
+};
+
+static const char * const scifb_groups[] = {
+        "scifb_data_0",
+        "scifb_clk_0",
+        "scifb_ctrl_0",
+        "scifb_data_1",
+        "scifb_clk_1",
+        "scifb_ctrl_1",
+};
+
 static const char * const sdhi0_groups[] = {
         "sdhi0_data1",
         "sdhi0_data4",
@@ -2168,412 +3217,51 @@ static const char * const sdhi2_groups[] = {
         "sdhi2_wp_1",
 };
 
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2_0",
+        "tpu0_to2_1",
+        "tpu0_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(bsc),
+        SH_PFC_FUNCTION(ceu0),
+        SH_PFC_FUNCTION(ceu1),
+        SH_PFC_FUNCTION(fsia),
+        SH_PFC_FUNCTION(fsib),
+        SH_PFC_FUNCTION(gether),
+        SH_PFC_FUNCTION(hdmi),
+        SH_PFC_FUNCTION(intc),
         SH_PFC_FUNCTION(lcd0),
         SH_PFC_FUNCTION(lcd1),
         SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifa3),
+        SH_PFC_FUNCTION(scifa4),
+        SH_PFC_FUNCTION(scifa5),
+        SH_PFC_FUNCTION(scifa6),
+        SH_PFC_FUNCTION(scifa7),
+        SH_PFC_FUNCTION(scifb),
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(tpu0),
 };
 
-#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* IRQ */
-        GPIO_FN(IRQ0_PORT2),    GPIO_FN(IRQ0_PORT13),
-        GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_PORT11),   GPIO_FN(IRQ2_PORT12),
-        GPIO_FN(IRQ3_PORT10),   GPIO_FN(IRQ3_PORT14),
-        GPIO_FN(IRQ4_PORT15),   GPIO_FN(IRQ4_PORT172),
-        GPIO_FN(IRQ5_PORT0),    GPIO_FN(IRQ5_PORT1),
-        GPIO_FN(IRQ6_PORT121),  GPIO_FN(IRQ6_PORT173),
-        GPIO_FN(IRQ7_PORT120),  GPIO_FN(IRQ7_PORT209),
-        GPIO_FN(IRQ8),
-        GPIO_FN(IRQ9_PORT118),  GPIO_FN(IRQ9_PORT210),
-        GPIO_FN(IRQ10),
-        GPIO_FN(IRQ11),
-        GPIO_FN(IRQ12_PORT42),  GPIO_FN(IRQ12_PORT97),
-        GPIO_FN(IRQ13_PORT64),  GPIO_FN(IRQ13_PORT98),
-        GPIO_FN(IRQ14_PORT63),  GPIO_FN(IRQ14_PORT99),
-        GPIO_FN(IRQ15_PORT62),  GPIO_FN(IRQ15_PORT100),
-        GPIO_FN(IRQ16_PORT68),  GPIO_FN(IRQ16_PORT211),
-        GPIO_FN(IRQ17),
-        GPIO_FN(IRQ18),
-        GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),
-        GPIO_FN(IRQ21),
-        GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),
-        GPIO_FN(IRQ24),
-        GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_PORT58),  GPIO_FN(IRQ26_PORT81),
-        GPIO_FN(IRQ27_PORT57),  GPIO_FN(IRQ27_PORT168),
-        GPIO_FN(IRQ28_PORT56),  GPIO_FN(IRQ28_PORT169),
-        GPIO_FN(IRQ29_PORT50),  GPIO_FN(IRQ29_PORT170),
-        GPIO_FN(IRQ30_PORT49),  GPIO_FN(IRQ30_PORT171),
-        GPIO_FN(IRQ31_PORT41),  GPIO_FN(IRQ31_PORT167),
-
-        /* Function */
-
-        /* DBGT */
-        GPIO_FN(DBGMDT2),       GPIO_FN(DBGMDT1),       GPIO_FN(DBGMDT0),
-        GPIO_FN(DBGMD10),       GPIO_FN(DBGMD11),       GPIO_FN(DBGMD20),
-        GPIO_FN(DBGMD21),
-
-        /* FSI-A */
-        GPIO_FN(FSIAISLD_PORT0),        /* FSIAISLD Port 0/5 */
-        GPIO_FN(FSIAISLD_PORT5),
-        GPIO_FN(FSIASPDIF_PORT9),       /* FSIASPDIF Port 9/18 */
-        GPIO_FN(FSIASPDIF_PORT18),
-        GPIO_FN(FSIAOSLD1),     GPIO_FN(FSIAOSLD2),     GPIO_FN(FSIAOLR),
-        GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIACK),        GPIO_FN(FSIAILR),       GPIO_FN(FSIAIBT),
-
-        /* FSI-B */
-        GPIO_FN(FSIBCK),
-
-        /* FMSI */
-        GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
-        GPIO_FN(FMSISLD_PORT6),
-        GPIO_FN(FMSIILR),       GPIO_FN(FMSIIBT),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSIOBT),       GPIO_FN(FMSICK),        GPIO_FN(FMSOILR),
-        GPIO_FN(FMSOIBT),       GPIO_FN(FMSOOLR),       GPIO_FN(FMSOOBT),
-        GPIO_FN(FMSOSLD),       GPIO_FN(FMSOCK),
-
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_SCK),    GPIO_FN(SCIFA0_CTS),    GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_TXD),
-
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_CTS),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RTS),
-
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN(SCIFA2_SCK_PORT199),
-        GPIO_FN(SCIFA2_RXD),    GPIO_FN(SCIFA2_TXD),
-        GPIO_FN(SCIFA2_CTS),    GPIO_FN(SCIFA2_RTS),
-
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
-        GPIO_FN(SCIFA3_SCK_PORT116),
-        GPIO_FN(SCIFA3_CTS_PORT117),
-        GPIO_FN(SCIFA3_RXD_PORT174),
-        GPIO_FN(SCIFA3_TXD_PORT175),
-
-        GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
-        GPIO_FN(SCIFA3_SCK_PORT158),
-        GPIO_FN(SCIFA3_CTS_PORT162),
-        GPIO_FN(SCIFA3_RXD_PORT159),
-        GPIO_FN(SCIFA3_TXD_PORT160),
-
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
-        GPIO_FN(SCIFA4_TXD_PORT13),
-
-        GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
-        GPIO_FN(SCIFA4_TXD_PORT203),
-
-        GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
-        GPIO_FN(SCIFA4_TXD_PORT93),
-
-        GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN(SCIFA4_SCK_PORT205),
-
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
-        GPIO_FN(SCIFA5_RXD_PORT10),
-
-        GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
-        GPIO_FN(SCIFA5_TXD_PORT208),
-
-        GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
-        GPIO_FN(SCIFA5_RXD_PORT92),
-
-        GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN(SCIFA5_SCK_PORT206),
-
-        /* SCIFA6 */
-        GPIO_FN(SCIFA6_SCK),    GPIO_FN(SCIFA6_RXD),    GPIO_FN(SCIFA6_TXD),
-
-        /* SCIFA7 */
-        GPIO_FN(SCIFA7_TXD),    GPIO_FN(SCIFA7_RXD),
-
-        /* SCIFAB */
-        GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
-        GPIO_FN(SCIFB_RXD_PORT191),
-        GPIO_FN(SCIFB_TXD_PORT192),
-        GPIO_FN(SCIFB_RTS_PORT186),
-        GPIO_FN(SCIFB_CTS_PORT187),
-
-        GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
-        GPIO_FN(SCIFB_RXD_PORT3),
-        GPIO_FN(SCIFB_TXD_PORT4),
-        GPIO_FN(SCIFB_RTS_PORT172),
-        GPIO_FN(SCIFB_CTS_PORT173),
-
-        /* RSPI */
-        GPIO_FN(RSPI_SSL0_A),   GPIO_FN(RSPI_SSL1_A),   GPIO_FN(RSPI_SSL2_A),
-        GPIO_FN(RSPI_SSL3_A),   GPIO_FN(RSPI_CK_A),     GPIO_FN(RSPI_MOSI_A),
-        GPIO_FN(RSPI_MISO_A),
-
-        /* VIO CKO */
-        GPIO_FN(VIO_CKO1),
-        GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_CKO_1),
-        GPIO_FN(VIO_CKO),
-
-        /* VIO0 */
-        GPIO_FN(VIO0_D0),       GPIO_FN(VIO0_D1),       GPIO_FN(VIO0_D2),
-        GPIO_FN(VIO0_D3),       GPIO_FN(VIO0_D4),       GPIO_FN(VIO0_D5),
-        GPIO_FN(VIO0_D6),       GPIO_FN(VIO0_D7),       GPIO_FN(VIO0_D8),
-        GPIO_FN(VIO0_D9),       GPIO_FN(VIO0_D10),      GPIO_FN(VIO0_D11),
-        GPIO_FN(VIO0_D12),      GPIO_FN(VIO0_VD),       GPIO_FN(VIO0_HD),
-        GPIO_FN(VIO0_CLK),      GPIO_FN(VIO0_FIELD),
-
-        GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
-        GPIO_FN(VIO0_D14_PORT25),
-        GPIO_FN(VIO0_D15_PORT24),
-
-        GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
-        GPIO_FN(VIO0_D14_PORT95),
-        GPIO_FN(VIO0_D15_PORT96),
-
-        /* VIO1 */
-        GPIO_FN(VIO1_D0),       GPIO_FN(VIO1_D1),       GPIO_FN(VIO1_D2),
-        GPIO_FN(VIO1_D3),       GPIO_FN(VIO1_D4),       GPIO_FN(VIO1_D5),
-        GPIO_FN(VIO1_D6),       GPIO_FN(VIO1_D7),       GPIO_FN(VIO1_VD),
-        GPIO_FN(VIO1_HD),       GPIO_FN(VIO1_CLK),      GPIO_FN(VIO1_FIELD),
-
-        /* TPU0 */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO3),
-        GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
-        GPIO_FN(TPU0TO2_PORT202),
-
-        /* SSP1 0 */
-        GPIO_FN(STP0_IPD0),     GPIO_FN(STP0_IPD1),     GPIO_FN(STP0_IPD2),
-        GPIO_FN(STP0_IPD3),     GPIO_FN(STP0_IPD4),     GPIO_FN(STP0_IPD5),
-        GPIO_FN(STP0_IPD6),     GPIO_FN(STP0_IPD7),     GPIO_FN(STP0_IPEN),
-        GPIO_FN(STP0_IPCLK),    GPIO_FN(STP0_IPSYNC),
-
-        /* SSP1 1 */
-        GPIO_FN(STP1_IPD1),     GPIO_FN(STP1_IPD2),     GPIO_FN(STP1_IPD3),
-        GPIO_FN(STP1_IPD4),     GPIO_FN(STP1_IPD5),     GPIO_FN(STP1_IPD6),
-        GPIO_FN(STP1_IPD7),     GPIO_FN(STP1_IPCLK),    GPIO_FN(STP1_IPSYNC),
-
-        GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
-        GPIO_FN(STP1_IPEN_PORT187),
-
-        GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
-        GPIO_FN(STP1_IPEN_PORT193),
-
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),
-        GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
-        GPIO_FN(SIM_D_PORT199),
-
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_TXD),    GPIO_FN(MSIOF2_RXD),    GPIO_FN(MSIOF2_TSCK),
-        GPIO_FN(MSIOF2_SS2),    GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_MCK0),   GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(MSIOF2_RSCK),
-
-        /* KEYSC */
-        GPIO_FN(KEYIN4),        GPIO_FN(KEYIN5),
-        GPIO_FN(KEYIN6),        GPIO_FN(KEYIN7),
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYOUT1),       GPIO_FN(KEYOUT2),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYOUT4),       GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYOUT6),       GPIO_FN(KEYOUT7),
-
-        GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
-        GPIO_FN(KEYIN1_PORT44),
-        GPIO_FN(KEYIN2_PORT45),
-        GPIO_FN(KEYIN3_PORT46),
-
-        GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
-        GPIO_FN(KEYIN1_PORT57),
-        GPIO_FN(KEYIN2_PORT56),
-        GPIO_FN(KEYIN3_PORT55),
-
-        /* VOU */
-        GPIO_FN(DV_D0),         GPIO_FN(DV_D1),         GPIO_FN(DV_D2),
-        GPIO_FN(DV_D3),         GPIO_FN(DV_D4),         GPIO_FN(DV_D5),
-        GPIO_FN(DV_D6),         GPIO_FN(DV_D7),         GPIO_FN(DV_D8),
-        GPIO_FN(DV_D9),         GPIO_FN(DV_D10),        GPIO_FN(DV_D11),
-        GPIO_FN(DV_D12),        GPIO_FN(DV_D13),        GPIO_FN(DV_D14),
-        GPIO_FN(DV_D15),        GPIO_FN(DV_CLK),
-        GPIO_FN(DV_VSYNC),      GPIO_FN(DV_HSYNC),
-
-        /* MEMC */
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),     GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_INT),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_NOE),      GPIO_FN(MEMC_CS1),
-        GPIO_FN(MEMC_A1),       GPIO_FN(MEMC_ADV),      GPIO_FN(MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT),     GPIO_FN(MEMC_DREQ1),    GPIO_FN(MEMC_BUSCLK),
-        GPIO_FN(MEMC_A0),
-
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),    GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_TXD),    GPIO_FN(MSIOF0_MCK0),   GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(MSIOF0_TSYNC),
-
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_RSCK),   GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),   GPIO_FN(MSIOF1_MCK1),
-
-        GPIO_FN(MSIOF1_SS2_PORT116),    GPIO_FN(MSIOF1_SS1_PORT117),
-        GPIO_FN(MSIOF1_RXD_PORT118),    GPIO_FN(MSIOF1_TXD_PORT119),
-        GPIO_FN(MSIOF1_TSYNC_PORT120),
-        GPIO_FN(MSIOF1_TSCK_PORT121),   /* MSEL4CR_10_0 */
-
-        GPIO_FN(MSIOF1_SS1_PORT67),     GPIO_FN(MSIOF1_TSCK_PORT72),
-        GPIO_FN(MSIOF1_TSYNC_PORT73),   GPIO_FN(MSIOF1_TXD_PORT74),
-        GPIO_FN(MSIOF1_RXD_PORT75),
-        GPIO_FN(MSIOF1_SS2_PORT202),    /* MSEL4CR_10_1 */
-
-        /* GPIO */
-        GPIO_FN(GPO0),  GPIO_FN(GPI0),
-        GPIO_FN(GPO1),  GPIO_FN(GPI1),
-
-        /* USB0 */
-        GPIO_FN(USB0_OCI),      GPIO_FN(USB0_PPON),     GPIO_FN(VBUS),
-
-        /* USB1 */
-        GPIO_FN(USB1_OCI),      GPIO_FN(USB1_PPON),
-
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(BBIF1_TSCK),    GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BBIF1_RX_FLOW_N),
-
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
-        GPIO_FN(BBIF2_RXD2_PORT60),
-        GPIO_FN(BBIF2_TSYNC2_PORT6),
-        GPIO_FN(BBIF2_TSCK2_PORT59),
-
-        GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
-        GPIO_FN(BBIF2_TXD2_PORT183),
-        GPIO_FN(BBIF2_TSCK2_PORT89),
-        GPIO_FN(BBIF2_TSYNC2_PORT184),
-
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5B),  GPIO_FN(CS6A),
-        GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
-        GPIO_FN(CS5A_PORT19),
-        GPIO_FN(IOIS16), /* ? */
-
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),    GPIO_FN(A3),
-        GPIO_FN(A4_FOE),        GPIO_FN(A5_FCDE),       /* share with FLCTL */
-        GPIO_FN(A6),    GPIO_FN(A7),    GPIO_FN(A8),    GPIO_FN(A9),
-        GPIO_FN(A10),   GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),   GPIO_FN(A17),
-        GPIO_FN(A18),   GPIO_FN(A19),   GPIO_FN(A20),   GPIO_FN(A21),
-        GPIO_FN(A22),   GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-
-        GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),       /* share with FLCTL */
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       /* share with FLCTL */
-        GPIO_FN(D4_NAF4),       GPIO_FN(D5_NAF5),       /* share with FLCTL */
-        GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),       /* share with FLCTL */
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       /* share with FLCTL */
-        GPIO_FN(D10_NAF10),     GPIO_FN(D11_NAF11),     /* share with FLCTL */
-        GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),     /* share with FLCTL */
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),     /* share with FLCTL */
-        GPIO_FN(D16),   GPIO_FN(D17),   GPIO_FN(D18),   GPIO_FN(D19),
-        GPIO_FN(D20),   GPIO_FN(D21),   GPIO_FN(D22),   GPIO_FN(D23),
-        GPIO_FN(D24),   GPIO_FN(D25),   GPIO_FN(D26),   GPIO_FN(D27),
-        GPIO_FN(D28),   GPIO_FN(D29),   GPIO_FN(D30),   GPIO_FN(D31),
-
-        GPIO_FN(WE0_FWE),       /* share with FLCTL */
-        GPIO_FN(WE1),
-        GPIO_FN(WE2_ICIORD),    /* share with PCMCIA */
-        GPIO_FN(WE3_ICIOWR),    /* share with PCMCIA */
-        GPIO_FN(CKO),   GPIO_FN(BS),    GPIO_FN(RDWR),
-        GPIO_FN(RD_FSC),        /* share with FLCTL */
-        GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
-        GPIO_FN(WAIT_PORT90),
-
-        GPIO_FN(FCE0),  GPIO_FN(FCE1),  GPIO_FN(FRB), /* FLCTL */
-
-        /* IRDA */
-        GPIO_FN(IRDA_FIRSEL),   GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_OUT),
-
-        /* ATAPI */
-        GPIO_FN(IDE_D0),        GPIO_FN(IDE_D1),        GPIO_FN(IDE_D2),
-        GPIO_FN(IDE_D3),        GPIO_FN(IDE_D4),        GPIO_FN(IDE_D5),
-        GPIO_FN(IDE_D6),        GPIO_FN(IDE_D7),        GPIO_FN(IDE_D8),
-        GPIO_FN(IDE_D9),        GPIO_FN(IDE_D10),       GPIO_FN(IDE_D11),
-        GPIO_FN(IDE_D12),       GPIO_FN(IDE_D13),       GPIO_FN(IDE_D14),
-        GPIO_FN(IDE_D15),       GPIO_FN(IDE_A0),        GPIO_FN(IDE_A1),
-        GPIO_FN(IDE_A2),        GPIO_FN(IDE_CS0),       GPIO_FN(IDE_CS1),
-        GPIO_FN(IDE_IOWR),      GPIO_FN(IDE_IORD),      GPIO_FN(IDE_IORDY),
-        GPIO_FN(IDE_INT),       GPIO_FN(IDE_RST),       GPIO_FN(IDE_DIRECTION),
-        GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK),    GPIO_FN(IDE_IODREQ),
-
-        /* RMII */
-        GPIO_FN(RMII_CRS_DV),   GPIO_FN(RMII_RX_ER),    GPIO_FN(RMII_RXD0),
-        GPIO_FN(RMII_RXD1),     GPIO_FN(RMII_TX_EN),    GPIO_FN(RMII_TXD0),
-        GPIO_FN(RMII_MDC),      GPIO_FN(RMII_TXD1),     GPIO_FN(RMII_MDIO),
-        GPIO_FN(RMII_REF50CK),  GPIO_FN(RMII_REF125CK), /* for GMII */
-
-        /* GEther */
-        GPIO_FN(ET_TX_CLK),     GPIO_FN(ET_TX_EN),      GPIO_FN(ET_ETXD0),
-        GPIO_FN(ET_ETXD1),      GPIO_FN(ET_ETXD2),      GPIO_FN(ET_ETXD3),
-        GPIO_FN(ET_ETXD4),      GPIO_FN(ET_ETXD5), /* for GEther */
-        GPIO_FN(ET_ETXD6),      GPIO_FN(ET_ETXD7), /* for GEther */
-        GPIO_FN(ET_COL),        GPIO_FN(ET_TX_ER),      GPIO_FN(ET_RX_CLK),
-        GPIO_FN(ET_RX_DV),      GPIO_FN(ET_ERXD0),      GPIO_FN(ET_ERXD1),
-        GPIO_FN(ET_ERXD2),      GPIO_FN(ET_ERXD3),
-        GPIO_FN(ET_ERXD4),      GPIO_FN(ET_ERXD5), /* for GEther */
-        GPIO_FN(ET_ERXD6),      GPIO_FN(ET_ERXD7), /* for GEther */
-        GPIO_FN(ET_RX_ER),      GPIO_FN(ET_CRS),        GPIO_FN(ET_MDC),
-        GPIO_FN(ET_MDIO),       GPIO_FN(ET_LINK),       GPIO_FN(ET_PHY_INT),
-        GPIO_FN(ET_WOL),        GPIO_FN(ET_GTX_CLK),
-
-        /* DMA0 */
-        GPIO_FN(DREQ0), GPIO_FN(DACK0),
-
-        /* DMA1 */
-        GPIO_FN(DREQ1), GPIO_FN(DACK1),
-
-        /* SYSC */
-        GPIO_FN(RESETOUTS),
-
-        /* IRREM */
-        GPIO_FN(IROUT),
-
-        /* LCDC */
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),
-        GPIO_FN(HDMI_CEC),
-
-        /* SYSC */
-        GPIO_FN(RESETP_PULLUP),
-        GPIO_FN(RESETP_PLAIN),
-
-        /* DEBUG */
-        GPIO_FN(EDEBGREQ_PULLDOWN),
-        GPIO_FN(EDEBGREQ_PULLUP),
-
-        GPIO_FN(TRACEAUD_FROM_VIO),
-        GPIO_FN(TRACEAUD_FROM_LCDC0),
-        GPIO_FN(TRACEAUD_FROM_MEMC),
-};
+#undef PORTCR
+#define PORTCR(nr, reg)                                                 \
+        {                                                               \
+                PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
+                        _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1,         \
+                                PORT##nr##_FN2, PORT##nr##_FN3,         \
+                                PORT##nr##_FN4, PORT##nr##_FN5,         \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xe6050000), /* PORT0CR */
@@ -2994,48 +3682,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 };
 
 static const struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(irq_pin(0), GPIO_PORT2,   GPIO_PORT13),      /* IRQ0A */
-        PINMUX_IRQ(irq_pin(1), GPIO_PORT20),            /* IRQ1A */
-        PINMUX_IRQ(irq_pin(2), GPIO_PORT11,  GPIO_PORT12),      /* IRQ2A */
-        PINMUX_IRQ(irq_pin(3), GPIO_PORT10,  GPIO_PORT14),      /* IRQ3A */
-        PINMUX_IRQ(irq_pin(4), GPIO_PORT15,  GPIO_PORT172),/* IRQ4A */
-        PINMUX_IRQ(irq_pin(5), GPIO_PORT0,   GPIO_PORT1),       /* IRQ5A */
-        PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
-        PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
-        PINMUX_IRQ(irq_pin(8), GPIO_PORT119),           /* IRQ8A */
-        PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
-        PINMUX_IRQ(irq_pin(10), GPIO_PORT19),           /* IRQ10A */
-        PINMUX_IRQ(irq_pin(11), GPIO_PORT104),          /* IRQ11A */
-        PINMUX_IRQ(irq_pin(12), GPIO_PORT42,  GPIO_PORT97),     /* IRQ12A */
-        PINMUX_IRQ(irq_pin(13), GPIO_PORT64,  GPIO_PORT98),     /* IRQ13A */
-        PINMUX_IRQ(irq_pin(14), GPIO_PORT63,  GPIO_PORT99),     /* IRQ14A */
-        PINMUX_IRQ(irq_pin(15), GPIO_PORT62,  GPIO_PORT100),/* IRQ15A */
-        PINMUX_IRQ(irq_pin(16), GPIO_PORT68,  GPIO_PORT211),/* IRQ16A */
-        PINMUX_IRQ(irq_pin(17), GPIO_PORT69),           /* IRQ17A */
-        PINMUX_IRQ(irq_pin(18), GPIO_PORT70),           /* IRQ18A */
-        PINMUX_IRQ(irq_pin(19), GPIO_PORT71),           /* IRQ19A */
-        PINMUX_IRQ(irq_pin(20), GPIO_PORT67),           /* IRQ20A */
-        PINMUX_IRQ(irq_pin(21), GPIO_PORT202),          /* IRQ21A */
-        PINMUX_IRQ(irq_pin(22), GPIO_PORT95),           /* IRQ22A */
-        PINMUX_IRQ(irq_pin(23), GPIO_PORT96),           /* IRQ23A */
-        PINMUX_IRQ(irq_pin(24), GPIO_PORT180),          /* IRQ24A */
-        PINMUX_IRQ(irq_pin(25), GPIO_PORT38),           /* IRQ25A */
-        PINMUX_IRQ(irq_pin(26), GPIO_PORT58,  GPIO_PORT81),     /* IRQ26A */
-        PINMUX_IRQ(irq_pin(27), GPIO_PORT57,  GPIO_PORT168),/* IRQ27A */
-        PINMUX_IRQ(irq_pin(28), GPIO_PORT56,  GPIO_PORT169),/* IRQ28A */
-        PINMUX_IRQ(irq_pin(29), GPIO_PORT50,  GPIO_PORT170),/* IRQ29A */
-        PINMUX_IRQ(irq_pin(30), GPIO_PORT49,  GPIO_PORT171),/* IRQ30A */
-        PINMUX_IRQ(irq_pin(31), GPIO_PORT41,  GPIO_PORT167),/* IRQ31A */
+        PINMUX_IRQ(irq_pin(0), 2,   13),        /* IRQ0A */
+        PINMUX_IRQ(irq_pin(1), 20),             /* IRQ1A */
+        PINMUX_IRQ(irq_pin(2), 11,  12),        /* IRQ2A */
+        PINMUX_IRQ(irq_pin(3), 10,  14),        /* IRQ3A */
+        PINMUX_IRQ(irq_pin(4), 15,  172),       /* IRQ4A */
+        PINMUX_IRQ(irq_pin(5), 0,   1),         /* IRQ5A */
+        PINMUX_IRQ(irq_pin(6), 121, 173),       /* IRQ6A */
+        PINMUX_IRQ(irq_pin(7), 120, 209),       /* IRQ7A */
+        PINMUX_IRQ(irq_pin(8), 119),            /* IRQ8A */
+        PINMUX_IRQ(irq_pin(9), 118, 210),       /* IRQ9A */
+        PINMUX_IRQ(irq_pin(10), 19),            /* IRQ10A */
+        PINMUX_IRQ(irq_pin(11), 104),           /* IRQ11A */
+        PINMUX_IRQ(irq_pin(12), 42,  97),       /* IRQ12A */
+        PINMUX_IRQ(irq_pin(13), 64,  98),       /* IRQ13A */
+        PINMUX_IRQ(irq_pin(14), 63,  99),       /* IRQ14A */
+        PINMUX_IRQ(irq_pin(15), 62,  100),      /* IRQ15A */
+        PINMUX_IRQ(irq_pin(16), 68,  211),      /* IRQ16A */
+        PINMUX_IRQ(irq_pin(17), 69),            /* IRQ17A */
+        PINMUX_IRQ(irq_pin(18), 70),            /* IRQ18A */
+        PINMUX_IRQ(irq_pin(19), 71),            /* IRQ19A */
+        PINMUX_IRQ(irq_pin(20), 67),            /* IRQ20A */
+        PINMUX_IRQ(irq_pin(21), 202),           /* IRQ21A */
+        PINMUX_IRQ(irq_pin(22), 95),            /* IRQ22A */
+        PINMUX_IRQ(irq_pin(23), 96),            /* IRQ23A */
+        PINMUX_IRQ(irq_pin(24), 180),           /* IRQ24A */
+        PINMUX_IRQ(irq_pin(25), 38),            /* IRQ25A */
+        PINMUX_IRQ(irq_pin(26), 58,  81),       /* IRQ26A */
+        PINMUX_IRQ(irq_pin(27), 57,  168),      /* IRQ27A */
+        PINMUX_IRQ(irq_pin(28), 56,  169),      /* IRQ28A */
+        PINMUX_IRQ(irq_pin(29), 50,  170),      /* IRQ29A */
+        PINMUX_IRQ(irq_pin(30), 49,  171),      /* IRQ30A */
+        PINMUX_IRQ(irq_pin(31), 41,  167),      /* IRQ31A */
+};
+
+#define PORTnCR_PULMD_OFF       (0 << 6)
+#define PORTnCR_PULMD_DOWN      (2 << 6)
+#define PORTnCR_PULMD_UP        (3 << 6)
+#define PORTnCR_PULMD_MASK      (3 << 6)
+
+struct r8a7740_portcr_group {
+        unsigned int end_pin;
+        unsigned int offset;
+};
+
+static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
+        { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
+};
+
+static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
+                const struct r8a7740_portcr_group *group =
+                        &r8a7740_portcr_offsets[i];
+
+                if (i <= group->end_pin)
+                        return pfc->window->virt + group->offset + pin;
+        }
+
+        return NULL;
+}
+
+static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+        void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+        switch (value) {
+        case PORTnCR_PULMD_UP:
+                return PIN_CONFIG_BIAS_PULL_UP;
+        case PORTnCR_PULMD_DOWN:
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+        case PORTnCR_PULMD_OFF:
+        default:
+                return PIN_CONFIG_BIAS_DISABLE;
+        }
+}
+
+static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                   unsigned int bias)
+{
+        void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+        switch (bias) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                value |= PORTnCR_PULMD_UP;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                value |= PORTnCR_PULMD_DOWN;
+                break;
+        }
+
+        iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
+        .get_bias = r8a7740_pinmux_get_bias,
+        .set_bias = r8a7740_pinmux_set_bias,
 };
 
 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
         .name           = "r8a7740_pfc",
+        .ops            = &r8a7740_pinmux_ops,
+
         .input          = { PINMUX_INPUT_BEGIN,
                             PINMUX_INPUT_END },
-        .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
-                            PINMUX_INPUT_PULLUP_END },
-        .input_pd       = { PINMUX_INPUT_PULLDOWN_BEGIN,
-                            PINMUX_INPUT_PULLDOWN_END },
         .output         = { PINMUX_OUTPUT_BEGIN,
                             PINMUX_OUTPUT_END },
         .function       = { PINMUX_FUNCTION_BEGIN,
@@ -3048,9 +3802,6 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = {
         .functions      = pinmux_functions,
         .nr_functions   = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios     = pinmux_func_gpios,
-        .nr_func_gpios  = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs       = pinmux_config_regs,
         .data_regs      = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
new file mode 100644
index 000000000000..1dcbabcd7b3c
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -0,0 +1,2783 @@
+/*
+ * r8a7778 processor support - PFC hardware block
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Copyright (C) 2013  Cogent Embedded, Inc.
+ *
+ * based on
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_data/gpio-rcar.h>
+#include <linux/kernel.h>
+#include "sh_pfc.h"
+
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
+        PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
+        PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_27(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)           \
+        PORT_GP_32(0, fn, sfx),         \
+        PORT_GP_32(1, fn, sfx),         \
+        PORT_GP_32(2, fn, sfx),         \
+        PORT_GP_32(3, fn, sfx),         \
+        PORT_GP_27(4, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)         \
+        [RCAR_GP_PIN(bank, pin)] = {            \
+                .name = __stringify(_name),     \
+                .enum_id = _name##_DATA,        \
+        }
+
+#define _GP_DATA(bank, pin, name, sfx)          \
+        PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
+
+#define PINMUX_IPSR_NOGP(ispr, fn)      PINMUX_DATA(fn##_MARK, FN_##fn)
+#define PINMUX_IPSR_DATA(ipsr, fn)      PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
+#define PINMUX_IPSR_MSEL(ipsr, fn, ms)  PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
+#define PINMUX_IPSR_NOGM(ispr, fn, ms)  PINMUX_DATA(fn##_MARK, FN_##fn,            FN_##ms)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
+        PINMUX_DATA_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
+
+        /* GPSR0 */
+        FN_IP0_1_0,     FN_PENC0,       FN_PENC1,       FN_IP0_4_2,
+        FN_IP0_7_5,     FN_IP0_11_8,    FN_IP0_14_12,   FN_A1,
+        FN_A2,          FN_A3,          FN_IP0_15,      FN_IP0_16,
+        FN_IP0_17,      FN_IP0_18,      FN_IP0_19,      FN_IP0_20,
+        FN_IP0_21,      FN_IP0_22,      FN_IP0_23,      FN_IP0_24,
+        FN_IP0_25,      FN_IP0_26,      FN_IP0_27,      FN_IP0_28,
+        FN_IP0_29,      FN_IP0_30,      FN_IP1_0,       FN_IP1_1,
+        FN_IP1_4_2,     FN_IP1_7_5,     FN_IP1_10_8,    FN_IP1_14_11,
+
+        /* GPSR1 */
+        FN_IP1_23_21,   FN_WE0,         FN_IP1_24,      FN_IP1_27_25,
+        FN_IP1_29_28,   FN_IP2_2_0,     FN_IP2_5_3,     FN_IP2_8_6,
+        FN_IP2_11_9,    FN_IP2_13_12,   FN_IP2_16_14,   FN_IP2_17,
+        FN_IP2_30,      FN_IP2_31,      FN_IP3_1_0,     FN_IP3_4_2,
+        FN_IP3_7_5,     FN_IP3_9_8,     FN_IP3_12_10,   FN_IP3_15_13,
+        FN_IP3_18_16,   FN_IP3_20_19,   FN_IP3_23_21,   FN_IP3_26_24,
+        FN_IP3_27,      FN_IP3_28,      FN_IP3_29,      FN_IP3_30,
+        FN_IP3_31,      FN_IP4_0,       FN_IP4_3_1,     FN_IP4_6_4,
+
+        /* GPSR2 */
+        FN_IP4_7,       FN_IP4_8,       FN_IP4_10_9,    FN_IP4_12_11,
+        FN_IP4_14_13,   FN_IP4_16_15,   FN_IP4_20_17,   FN_IP4_24_21,
+        FN_IP4_26_25,   FN_IP4_28_27,   FN_IP4_30_29,   FN_IP5_1_0,
+        FN_IP5_3_2,     FN_IP5_5_4,     FN_IP5_6,       FN_IP5_7,
+        FN_IP5_9_8,     FN_IP5_11_10,   FN_IP5_12,      FN_IP5_14_13,
+        FN_IP5_17_15,   FN_IP5_20_18,   FN_AUDIO_CLKA,  FN_AUDIO_CLKB,
+        FN_IP5_22_21,   FN_IP5_25_23,   FN_IP5_28_26,   FN_IP5_30_29,
+        FN_IP6_1_0,     FN_IP6_4_2,     FN_IP6_6_5,     FN_IP6_7,
+
+        /* GPSR3 */
+        FN_IP6_8,       FN_IP6_9,       FN_SSI_SCK34,   FN_IP6_10,
+        FN_IP6_12_11,   FN_IP6_13,      FN_IP6_15_14,   FN_IP6_16,
+        FN_IP6_18_17,   FN_IP6_20_19,   FN_IP6_21,      FN_IP6_23_22,
+        FN_IP6_25_24,   FN_IP6_27_26,   FN_IP6_29_28,   FN_IP6_31_30,
+        FN_IP7_1_0,     FN_IP7_3_2,     FN_IP7_5_4,     FN_IP7_8_6,
+        FN_IP7_11_9,    FN_IP7_14_12,   FN_IP7_17_15,   FN_IP7_20_18,
+        FN_IP7_21,      FN_IP7_24_22,   FN_IP7_28_25,   FN_IP7_31_29,
+        FN_IP8_2_0,     FN_IP8_5_3,     FN_IP8_8_6,     FN_IP8_10_9,
+
+        /* GPSR4 */
+        FN_IP8_13_11,   FN_IP8_15_14,   FN_IP8_18_16,   FN_IP8_21_19,
+        FN_IP8_23_22,   FN_IP8_26_24,   FN_IP8_29_27,   FN_IP9_2_0,
+        FN_IP9_5_3,     FN_IP9_8_6,     FN_IP9_11_9,    FN_IP9_14_12,
+        FN_IP9_17_15,   FN_IP9_20_18,   FN_IP9_23_21,   FN_IP9_26_24,
+        FN_IP9_29_27,   FN_IP10_2_0,    FN_IP10_5_3,    FN_IP10_8_6,
+        FN_IP10_12_9,   FN_IP10_15_13,  FN_IP10_18_16,  FN_IP10_21_19,
+        FN_IP10_24_22,  FN_AVS1,        FN_AVS2,
+
+        /* IPSR0 */
+        FN_PRESETOUT,   FN_PWM1,        FN_AUDATA0,     FN_ARM_TRACEDATA_0,
+        FN_GPSCLK_C,    FN_USB_OVC0,    FN_TX2_E,       FN_SDA2_B,
+        FN_AUDATA1,     FN_ARM_TRACEDATA_1,             FN_GPSIN_C,
+        FN_USB_OVC1,    FN_RX2_E,       FN_SCL2_B,      FN_SD1_DAT2_A,
+        FN_MMC_D2,      FN_BS,          FN_ATADIR0_A,   FN_SDSELF_A,
+        FN_PWM4_B,      FN_SD1_DAT3_A,  FN_MMC_D3,      FN_A0,
+        FN_ATAG0_A,     FN_REMOCON_B,   FN_A4,          FN_A5,
+        FN_A6,          FN_A7,          FN_A8,          FN_A9,
+        FN_A10,         FN_A11,         FN_A12,         FN_A13,
+        FN_A14,         FN_A15,         FN_A16,         FN_A17,
+        FN_A18,         FN_A19,
+
+        /* IPSR1 */
+        FN_A20,         FN_HSPI_CS1_B,  FN_A21,         FN_HSPI_CLK1_B,
+        FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
+        FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
+        FN_TS_SDEN0_A,  FN_SD1_CD_A,    FN_MMC_D6,      FN_A24,
+        FN_DREQ1_A,     FN_HRX0_B,      FN_TS_SPSYNC0_A,
+        FN_SD1_WP_A,    FN_MMC_D7,      FN_A25, FN_DACK1_A,
+        FN_HCTS0_B,     FN_RX3_C,       FN_TS_SDAT0_A,  FN_CLKOUT,
+        FN_HSPI_TX1_B,  FN_PWM0_B,      FN_CS0,         FN_HSPI_RX1_B,
+        FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
+        FN_SCK2_B,      FN_MMC_D5,      FN_ATADIR0_B,   FN_RD_WR,
+        FN_WE1,         FN_ATAWR0_B,    FN_SSI_WS1_B,   FN_EX_CS0,
+        FN_SCL2_A,      FN_TX3_C,       FN_TS_SCK0_A,   FN_EX_CS1,
+        FN_MMC_D4,
+
+        /* IPSR2 */
+        FN_SD1_CLK_A,   FN_MMC_CLK,     FN_ATACS00,     FN_EX_CS2,
+        FN_SD1_CMD_A,   FN_MMC_CMD,     FN_ATACS10,     FN_EX_CS3,
+        FN_SD1_DAT0_A,  FN_MMC_D0,      FN_ATARD0,      FN_EX_CS4,
+        FN_EX_WAIT1_A,  FN_SD1_DAT1_A,  FN_MMC_D1,      FN_ATAWR0_A,
+        FN_EX_CS5,      FN_EX_WAIT2_A,  FN_DREQ0_A,     FN_RX3_A,
+        FN_DACK0,       FN_TX3_A,       FN_DRACK0,      FN_EX_WAIT0,
+        FN_PWM0_C,      FN_D0,          FN_D1,          FN_D2,
+        FN_D3,          FN_D4,          FN_D5,          FN_D6,
+        FN_D7,          FN_D8,          FN_D9,          FN_D10,
+        FN_D11,         FN_RD_WR_B,     FN_IRQ0,        FN_MLB_CLK,
+        FN_IRQ1_A,
+
+        /* IPSR3 */
+        FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
+        FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
+        FN_SDSELF_B,    FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,
+        FN_CAN_CLK_B,   FN_SDA3_B,      FN_SD1_CLK_B,   FN_HTX0_A,
+        FN_TX0_A,       FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,
+        FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
+        FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        FN_SD1_DAT3_B,
+        FN_HRTS0_A,     FN_RTS0,        FN_SSI_SCK4,    FN_DU0_DR0,
+        FN_LCDOUT0,     FN_AUDATA2,     FN_ARM_TRACEDATA_2,
+        FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,  FN_SSI_WS4,
+        FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,     FN_ARM_TRACEDATA_3,
+        FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
+        FN_DU0_DR2,     FN_LCDOUT2,     FN_DU0_DR3,     FN_LCDOUT3,
+        FN_DU0_DR4,     FN_LCDOUT4,     FN_DU0_DR5,     FN_LCDOUT5,
+        FN_DU0_DR6,     FN_LCDOUT6,
+
+        /* IPSR4 */
+        FN_DU0_DR7,     FN_LCDOUT7,     FN_DU0_DG0,     FN_LCDOUT8,
+        FN_AUDATA4,     FN_ARM_TRACEDATA_4,             FN_TX1_D,
+        FN_CAN0_TX_A,   FN_ADICHS0,     FN_DU0_DG1,     FN_LCDOUT9,
+        FN_AUDATA5,     FN_ARM_TRACEDATA_5,             FN_RX1_D,
+        FN_CAN0_RX_A,   FN_ADIDATA,     FN_DU0_DG2,     FN_LCDOUT10,
+        FN_DU0_DG3,     FN_LCDOUT11,    FN_DU0_DG4,     FN_LCDOUT12,
+        FN_RX0_B,       FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,
+        FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       FN_DU0_DG7,
+        FN_LCDOUT15,    FN_TX4_A,       FN_SSI_SCK2_B,  FN_VI0_R0_B,
+        FN_DU0_DB0,     FN_LCDOUT16,    FN_AUDATA6,     FN_ARM_TRACEDATA_6,
+        FN_GPSCLK_A,    FN_PWM0_A,      FN_ADICLK,      FN_TS_SDAT0_B,
+        FN_AUDIO_CLKC,  FN_VI0_R1_B,    FN_DU0_DB1,     FN_LCDOUT17,
+        FN_AUDATA7,     FN_ARM_TRACEDATA_7,             FN_GPSIN_A,
+        FN_ADICS_SAMP,  FN_TS_SCK0_B,   FN_VI0_R2_B,    FN_DU0_DB2,
+        FN_LCDOUT18,    FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,
+        FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,
+
+        /* IPSR5 */
+        FN_VI0_R5_B,    FN_DU0_DB5,     FN_LCDOUT21,    FN_VI1_DATA10_B,
+        FN_DU0_DB6,     FN_LCDOUT22,    FN_VI1_DATA11_B,
+        FN_DU0_DB7,     FN_LCDOUT23,    FN_DU0_DOTCLKIN,
+        FN_QSTVA_QVS,   FN_DU0_DOTCLKO_UT0,             FN_QCLK,
+        FN_DU0_DOTCLKO_UT1,             FN_QSTVB_QVE,   FN_AUDIO_CLKOUT_A,
+        FN_REMOCON_C,   FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
+        FN_QSTH_QHS,    FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
+        FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
+        FN_QCPV_QDE,    FN_FMCLK_D,     FN_SSI_SCK1_A,  FN_DU0_DISP,
+        FN_QPOLA,       FN_AUDCK,       FN_ARM_TRACECLK,
+        FN_BPFCLK_D,    FN_SSI_WS1_A,   FN_DU0_CDE,     FN_QPOLB,
+        FN_AUDSYNC,     FN_ARM_TRACECTL,                FN_FMIN_D,
+        FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
+        FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
+        FN_CAN_CLK_D,   FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,
+        FN_TX2_A,       FN_CAN0_TX_B,   FN_SSI_SDATA7,  FN_HSPI_TX0_B,
+        FN_RX2_A,       FN_CAN0_RX_B,
+
+        /* IPSR6 */
+        FN_SSI_SCK6,    FN_HSPI_RX2_A,  FN_FMCLK_B,     FN_CAN1_TX_B,
+        FN_SSI_WS6,     FN_HSPI_CLK2_A, FN_BPFCLK_B,    FN_CAN1_RX_B,
+        FN_SSI_SDATA6,  FN_HSPI_TX2_A,  FN_FMIN_B,      FN_SSI_SCK5,
+        FN_RX4_C,       FN_SSI_WS5,     FN_TX4_C,       FN_SSI_SDATA5,
+        FN_RX0_D,       FN_SSI_WS34,    FN_ARM_TRACEDATA_8,
+        FN_SSI_SDATA4,  FN_SSI_WS2_A,   FN_ARM_TRACEDATA_9,
+        FN_SSI_SDATA3,  FN_ARM_TRACEDATA_10,
+        FN_SSI_SCK012,  FN_ARM_TRACEDATA_11,
+        FN_TX0_D,       FN_SSI_WS012,   FN_ARM_TRACEDATA_12,
+        FN_SSI_SDATA2,  FN_HSPI_CS2_A,  FN_ARM_TRACEDATA_13,
+        FN_SDA1_A,      FN_SSI_SDATA1,  FN_ARM_TRACEDATA_14,
+        FN_SCL1_A,      FN_SCK2_A,      FN_SSI_SDATA0,
+        FN_ARM_TRACEDATA_15,
+        FN_SD0_CLK,     FN_SUB_TDO,     FN_SD0_CMD,     FN_SUB_TRST,
+        FN_SD0_DAT0,    FN_SUB_TMS,     FN_SD0_DAT1,    FN_SUB_TCK,
+        FN_SD0_DAT2,    FN_SUB_TDI,
+
+        /* IPSR7 */
+        FN_SD0_DAT3,    FN_IRQ1_B,      FN_SD0_CD,      FN_TX5_A,
+        FN_SD0_WP,      FN_RX5_A,       FN_VI1_CLKENB,  FN_HSPI_CLK0_A,
+        FN_HTX1_A,      FN_RTS1_C,      FN_VI1_FIELD,   FN_HSPI_CS0_A,
+        FN_HRX1_A,      FN_SCK1_C,      FN_VI1_HSYNC,   FN_HSPI_RX0_A,
+        FN_HRTS1_A,     FN_FMCLK_A,     FN_RX1_C,       FN_VI1_VSYNC,
+        FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,    FN_TX1_C,
+        FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      FN_IRQ2_C,
+        FN_CTS1_C,      FN_SPEEDIN,     FN_VI0_CLK,     FN_CAN_CLK_A,
+        FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
+        FN_HSPI_RX1_A,  FN_RX4_B,       FN_VI0_FIELD,   FN_SD2_DAT3_B,
+        FN_VI0_R3_C,    FN_VI1_DATA1,   FN_DU1_DG7,     FN_HSPI_CLK1_A,
+        FN_TX4_B,       FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,
+        FN_DU1_DR2,     FN_HSPI_CS1_A,  FN_RX3_B,
+
+        /* IPSR8 */
+        FN_VI0_VSYNC,   FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
+        FN_HSPI_TX1_A,  FN_TX3_B,       FN_VI0_DATA0_VI0_B0,
+        FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,       FN_VI0_DATA1_VI0_B1,
+        FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,       FN_VI0_DATA2_VI0_B2,
+        FN_DU1_DG4,     FN_RX0_C,       FN_VI0_DATA3_VI0_B3,
+        FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,       FN_VI0_DATA4_VI0_B4,
+        FN_DU1_DB2,     FN_RX1_A,       FN_VI0_DATA5_VI0_B5,
+        FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,        FN_HSCK1_B,
+        FN_VI0_DATA6_VI0_G0,            FN_DU1_DB4,     FN_CTS1_A,
+        FN_PWM5,        FN_VI0_DATA7_VI0_G1,            FN_DU1_DB5,
+        FN_RTS1_A,      FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,
+        FN_DU1_DR4,     FN_HTX1_B,      FN_VI0_G3,      FN_SD2_CMD_B,
+        FN_VI1_DATA5,   FN_DU1_DR5,     FN_HRX1_B,
+
+        /* IPSR9 */
+        FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
+        FN_HRTS1_B,     FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,
+        FN_DU1_DR7,     FN_HCTS1_B,     FN_VI0_R0_A,    FN_VI1_CLK,
+        FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,                FN_VI0_R1_A,
+        FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,    FN_PWM2,
+        FN_TCLK1,       FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,
+        FN_ETH_TXD1,    FN_PWM3,        FN_VI0_R3_A,    FN_ETH_CRS_DV,
+        FN_IECLK,       FN_SCK2_C,      FN_VI0_R4_A,    FN_ETH_TX_EN,
+        FN_IETX,        FN_TX2_C,       FN_VI0_R5_A,    FN_ETH_RX_ER,
+        FN_FMCLK_C,     FN_IERX,        FN_RX2_C,       FN_VI1_DATA10_A,
+        FN_DU1_DOTCLKOUT,               FN_ETH_RXD0,    FN_BPFCLK_C,
+        FN_TX2_D,       FN_SDA2_C,      FN_VI1_DATA11_A,
+        FN_DU1_EXHSYNC_DU1_HSYNC,       FN_ETH_RXD1,    FN_FMIN_C,
+        FN_RX2_D,       FN_SCL2_C,
+
+        /* IPSR10 */
+        FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,       FN_ATARD1,
+        FN_ETH_MDC,     FN_SDA1_B,      FN_SD2_CMD_A,
+        FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,                FN_ATAWR1,
+        FN_ETH_MDIO,    FN_SCL1_B,      FN_SD2_DAT0_A,  FN_DU1_DISP,
+        FN_ATACS01,     FN_DREQ1_B,     FN_ETH_LINK,    FN_CAN1_RX_A,
+        FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
+        FN_ETH_MAGIC,   FN_CAN1_TX_A,   FN_PWM6,        FN_SD2_DAT2_A,
+        FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,     FN_HSPI_CLK2_B,
+        FN_GPSCLK_B,    FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,
+        FN_ATAG1,       FN_HSPI_CS2_B,  FN_GPSIN_B,     FN_SD2_CD_A,
+        FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,     FN_HSPI_RX2_B,
+        FN_REMOCON_A,   FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,
+        FN_DACK0_B,     FN_HSPI_TX2_B,  FN_CAN_CLK_C,
+
+        /* SEL */
+        FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
+        FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
+        FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
+        FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
+        FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
+        FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
+        FN_SEL_SSI2_A,  FN_SEL_SSI2_B,
+        FN_SEL_SSI1_A,  FN_SEL_SSI1_B,
+        FN_SEL_VI1_A,   FN_SEL_VI1_B,
+        FN_SEL_VI0_A,   FN_SEL_VI0_B,   FN_SEL_VI0_C,   FN_SEL_VI0_D,
+        FN_SEL_SD2_A,   FN_SEL_SD2_B,
+        FN_SEL_SD1_A,   FN_SEL_SD1_B,
+        FN_SEL_IRQ3_A,  FN_SEL_IRQ3_B,
+        FN_SEL_IRQ2_A,  FN_SEL_IRQ2_B,  FN_SEL_IRQ2_C,
+        FN_SEL_IRQ1_A,  FN_SEL_IRQ1_B,
+        FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
+        FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
+        FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
+        FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
+        FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
+        FN_SEL_CAN1_A,  FN_SEL_CAN1_B,
+        FN_SEL_CAN0_A,  FN_SEL_CAN0_B,
+        FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
+        FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
+        FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
+        FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
+        FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,       FN_SEL_REMOCON_C,
+        FN_SEL_FM_A,    FN_SEL_FM_B,    FN_SEL_FM_C,    FN_SEL_FM_D,
+        FN_SEL_GPS_A,   FN_SEL_GPS_B,   FN_SEL_GPS_C,
+        FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
+        FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
+        FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
+        FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
+        FN_SEL_I2C3_A,  FN_SEL_I2C3_B,  FN_SEL_I2C3_C,
+        FN_SEL_I2C2_A,  FN_SEL_I2C2_B,  FN_SEL_I2C2_C,
+        FN_SEL_I2C1_A,  FN_SEL_I2C1_B,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        /* GPSR0 */
+        PENC0_MARK,     PENC1_MARK,     A1_MARK,        A2_MARK,        A3_MARK,
+
+        /* GPSR1 */
+        WE0_MARK,
+
+        /* GPSR2 */
+        AUDIO_CLKA_MARK,
+        AUDIO_CLKB_MARK,
+
+        /* GPSR3 */
+        SSI_SCK34_MARK,
+
+        /* GPSR4 */
+        AVS1_MARK,
+        AVS2_MARK,
+
+        VI0_R0_C_MARK,          /* see sel_vi0 */
+        VI0_R1_C_MARK,          /* see sel_vi0 */
+        VI0_R2_C_MARK,          /* see sel_vi0 */
+        /* VI0_R3_C_MARK, */
+        VI0_R4_C_MARK,          /* see sel_vi0 */
+        VI0_R5_C_MARK,          /* see sel_vi0 */
+
+        VI0_R0_D_MARK,          /* see sel_vi0 */
+        VI0_R1_D_MARK,          /* see sel_vi0 */
+        VI0_R2_D_MARK,          /* see sel_vi0 */
+        VI0_R3_D_MARK,          /* see sel_vi0 */
+        VI0_R4_D_MARK,          /* see sel_vi0 */
+        VI0_R5_D_MARK,          /* see sel_vi0 */
+
+        /* IPSR0 */
+        PRESETOUT_MARK, PWM1_MARK,      AUDATA0_MARK,
+        ARM_TRACEDATA_0_MARK,           GPSCLK_C_MARK,  USB_OVC0_MARK,
+        TX2_E_MARK,     SDA2_B_MARK,    AUDATA1_MARK,   ARM_TRACEDATA_1_MARK,
+        GPSIN_C_MARK,   USB_OVC1_MARK,  RX2_E_MARK,     SCL2_B_MARK,
+        SD1_DAT2_A_MARK,                MMC_D2_MARK,    BS_MARK,
+        ATADIR0_A_MARK, SDSELF_A_MARK,  PWM4_B_MARK,    SD1_DAT3_A_MARK,
+        MMC_D3_MARK,    A0_MARK,        ATAG0_A_MARK,   REMOCON_B_MARK,
+        A4_MARK,        A5_MARK,        A6_MARK,        A7_MARK,
+        A8_MARK,        A9_MARK,        A10_MARK,       A11_MARK,
+        A12_MARK,       A13_MARK,       A14_MARK,       A15_MARK,
+        A16_MARK,       A17_MARK,       A18_MARK,       A19_MARK,
+
+        /* IPSR1 */
+        A20_MARK,       HSPI_CS1_B_MARK,                A21_MARK,
+        HSPI_CLK1_B_MARK,               A22_MARK,       HRTS0_B_MARK,
+        RX2_B_MARK,     DREQ2_A_MARK,   A23_MARK,       HTX0_B_MARK,
+        TX2_B_MARK,     DACK2_A_MARK,   TS_SDEN0_A_MARK,
+        SD1_CD_A_MARK,  MMC_D6_MARK,    A24_MARK,       DREQ1_A_MARK,
+        HRX0_B_MARK,    TS_SPSYNC0_A_MARK,              SD1_WP_A_MARK,
+        MMC_D7_MARK,    A25_MARK,       DACK1_A_MARK,   HCTS0_B_MARK,
+        RX3_C_MARK,     TS_SDAT0_A_MARK,                CLKOUT_MARK,
+        HSPI_TX1_B_MARK,                PWM0_B_MARK,    CS0_MARK,
+        HSPI_RX1_B_MARK,                SSI_SCK1_B_MARK,
+        ATAG0_B_MARK,   CS1_A26_MARK,   SDA2_A_MARK,    SCK2_B_MARK,
+        MMC_D5_MARK,    ATADIR0_B_MARK, RD_WR_MARK,     WE1_MARK,
+        ATAWR0_B_MARK,  SSI_WS1_B_MARK, EX_CS0_MARK,    SCL2_A_MARK,
+        TX3_C_MARK,     TS_SCK0_A_MARK, EX_CS1_MARK,    MMC_D4_MARK,
+
+        /* IPSR2 */
+        SD1_CLK_A_MARK, MMC_CLK_MARK,   ATACS00_MARK,   EX_CS2_MARK,
+        SD1_CMD_A_MARK, MMC_CMD_MARK,   ATACS10_MARK,   EX_CS3_MARK,
+        SD1_DAT0_A_MARK,                MMC_D0_MARK,    ATARD0_MARK,
+        EX_CS4_MARK,    EX_WAIT1_A_MARK,                SD1_DAT1_A_MARK,
+        MMC_D1_MARK,    ATAWR0_A_MARK,  EX_CS5_MARK,    EX_WAIT2_A_MARK,
+        DREQ0_A_MARK,   RX3_A_MARK,     DACK0_MARK,     TX3_A_MARK,
+        DRACK0_MARK,    EX_WAIT0_MARK,  PWM0_C_MARK,    D0_MARK,
+        D1_MARK,        D2_MARK,        D3_MARK,        D4_MARK,
+        D5_MARK,        D6_MARK,        D7_MARK,        D8_MARK,
+        D9_MARK,        D10_MARK,       D11_MARK,       RD_WR_B_MARK,
+        IRQ0_MARK,      MLB_CLK_MARK,   IRQ1_A_MARK,
+
+        /* IPSR3 */
+        MLB_SIG_MARK,   RX5_B_MARK,     SDA3_A_MARK,    IRQ2_A_MARK,
+        MLB_DAT_MARK,   TX5_B_MARK,     SCL3_A_MARK,    IRQ3_A_MARK,
+        SDSELF_B_MARK,  SD1_CMD_B_MARK, SCIF_CLK_MARK,  AUDIO_CLKOUT_B_MARK,
+        CAN_CLK_B_MARK, SDA3_B_MARK,    SD1_CLK_B_MARK, HTX0_A_MARK,
+        TX0_A_MARK,     SD1_DAT0_B_MARK,                HRX0_A_MARK,
+        RX0_A_MARK,     SD1_DAT1_B_MARK,                HSCK0_MARK,
+        SCK0_MARK,      SCL3_B_MARK,    SD1_DAT2_B_MARK,
+        HCTS0_A_MARK,   CTS0_MARK,      SD1_DAT3_B_MARK,
+        HRTS0_A_MARK,   RTS0_MARK,      SSI_SCK4_MARK,
+        DU0_DR0_MARK,   LCDOUT0_MARK,   AUDATA2_MARK,   ARM_TRACEDATA_2_MARK,
+        SDA3_C_MARK,    ADICHS1_MARK,   TS_SDEN0_B_MARK,
+        SSI_WS4_MARK,   DU0_DR1_MARK,   LCDOUT1_MARK,   AUDATA3_MARK,
+        ARM_TRACEDATA_3_MARK,           SCL3_C_MARK,    ADICHS2_MARK,
+        TS_SPSYNC0_B_MARK,              DU0_DR2_MARK,   LCDOUT2_MARK,
+        DU0_DR3_MARK,   LCDOUT3_MARK,   DU0_DR4_MARK,   LCDOUT4_MARK,
+        DU0_DR5_MARK,   LCDOUT5_MARK,   DU0_DR6_MARK,   LCDOUT6_MARK,
+
+        /* IPSR4 */
+        DU0_DR7_MARK,   LCDOUT7_MARK,   DU0_DG0_MARK,   LCDOUT8_MARK,
+        AUDATA4_MARK,   ARM_TRACEDATA_4_MARK,
+        TX1_D_MARK,     CAN0_TX_A_MARK, ADICHS0_MARK,   DU0_DG1_MARK,
+        LCDOUT9_MARK,   AUDATA5_MARK,   ARM_TRACEDATA_5_MARK,
+        RX1_D_MARK,     CAN0_RX_A_MARK, ADIDATA_MARK,   DU0_DG2_MARK,
+        LCDOUT10_MARK,  DU0_DG3_MARK,   LCDOUT11_MARK,  DU0_DG4_MARK,
+        LCDOUT12_MARK,  RX0_B_MARK,     DU0_DG5_MARK,   LCDOUT13_MARK,
+        TX0_B_MARK,     DU0_DG6_MARK,   LCDOUT14_MARK,  RX4_A_MARK,
+        DU0_DG7_MARK,   LCDOUT15_MARK,  TX4_A_MARK,     SSI_SCK2_B_MARK,
+        VI0_R0_B_MARK,  DU0_DB0_MARK,   LCDOUT16_MARK,  AUDATA6_MARK,
+        ARM_TRACEDATA_6_MARK,           GPSCLK_A_MARK,  PWM0_A_MARK,
+        ADICLK_MARK,    TS_SDAT0_B_MARK,                AUDIO_CLKC_MARK,
+        VI0_R1_B_MARK,  DU0_DB1_MARK,   LCDOUT17_MARK,  AUDATA7_MARK,
+        ARM_TRACEDATA_7_MARK,           GPSIN_A_MARK,   ADICS_SAMP_MARK,
+        TS_SCK0_B_MARK, VI0_R2_B_MARK,  DU0_DB2_MARK,   LCDOUT18_MARK,
+        VI0_R3_B_MARK,  DU0_DB3_MARK,   LCDOUT19_MARK,  VI0_R4_B_MARK,
+        DU0_DB4_MARK,   LCDOUT20_MARK,
+
+        /* IPSR5 */
+        VI0_R5_B_MARK,  DU0_DB5_MARK,   LCDOUT21_MARK,  VI1_DATA10_B_MARK,
+        DU0_DB6_MARK,   LCDOUT22_MARK,  VI1_DATA11_B_MARK,
+        DU0_DB7_MARK,   LCDOUT23_MARK,  DU0_DOTCLKIN_MARK,
+        QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
+        QCLK_MARK,      DU0_DOTCLKO_UT1_MARK,           QSTVB_QVE_MARK,
+        AUDIO_CLKOUT_A_MARK,            REMOCON_C_MARK, SSI_WS2_B_MARK,
+        DU0_EXHSYNC_DU0_HSYNC_MARK,     QSTH_QHS_MARK,
+        DU0_EXVSYNC_DU0_VSYNC_MARK,     QSTB_QHE_MARK,
+        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
+        QCPV_QDE_MARK,  FMCLK_D_MARK,   SSI_SCK1_A_MARK,
+        DU0_DISP_MARK,  QPOLA_MARK,     AUDCK_MARK,     ARM_TRACECLK_MARK,
+        BPFCLK_D_MARK,  SSI_WS1_A_MARK, DU0_CDE_MARK,   QPOLB_MARK,
+        AUDSYNC_MARK,   ARM_TRACECTL_MARK,              FMIN_D_MARK,
+        SD1_CD_B_MARK,  SSI_SCK78_MARK, HSPI_RX0_B_MARK,
+        TX1_B_MARK,     SD1_WP_B_MARK,  SSI_WS78_MARK,  HSPI_CLK0_B_MARK,
+        RX1_B_MARK,     CAN_CLK_D_MARK, SSI_SDATA8_MARK,
+        SSI_SCK2_A_MARK,                HSPI_CS0_B_MARK,
+        TX2_A_MARK,     CAN0_TX_B_MARK, SSI_SDATA7_MARK,
+        HSPI_TX0_B_MARK,                RX2_A_MARK,     CAN0_RX_B_MARK,
+
+        /* IPSR6 */
+        SSI_SCK6_MARK,  HSPI_RX2_A_MARK,                FMCLK_B_MARK,
+        CAN1_TX_B_MARK, SSI_WS6_MARK,   HSPI_CLK2_A_MARK,
+        BPFCLK_B_MARK,  CAN1_RX_B_MARK, SSI_SDATA6_MARK,
+        HSPI_TX2_A_MARK,                FMIN_B_MARK,    SSI_SCK5_MARK,
+        RX4_C_MARK,     SSI_WS5_MARK,   TX4_C_MARK,     SSI_SDATA5_MARK,
+        RX0_D_MARK,     SSI_WS34_MARK,  ARM_TRACEDATA_8_MARK,
+        SSI_SDATA4_MARK,                SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
+        SSI_SDATA3_MARK,                ARM_TRACEDATA_10_MARK,
+        SSI_SCK012_MARK,                ARM_TRACEDATA_11_MARK,
+        TX0_D_MARK,     SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
+        SSI_SDATA2_MARK,                HSPI_CS2_A_MARK,
+        ARM_TRACEDATA_13_MARK,          SDA1_A_MARK,    SSI_SDATA1_MARK,
+        ARM_TRACEDATA_14_MARK,          SCL1_A_MARK,    SCK2_A_MARK,
+        SSI_SDATA0_MARK,                ARM_TRACEDATA_15_MARK,
+        SD0_CLK_MARK,   SUB_TDO_MARK,   SD0_CMD_MARK,   SUB_TRST_MARK,
+        SD0_DAT0_MARK,  SUB_TMS_MARK,   SD0_DAT1_MARK,  SUB_TCK_MARK,
+        SD0_DAT2_MARK,  SUB_TDI_MARK,
+
+        /* IPSR7 */
+        SD0_DAT3_MARK,  IRQ1_B_MARK,    SD0_CD_MARK,    TX5_A_MARK,
+        SD0_WP_MARK,    RX5_A_MARK,     VI1_CLKENB_MARK,
+        HSPI_CLK0_A_MARK,       HTX1_A_MARK,    RTS1_C_MARK,    VI1_FIELD_MARK,
+        HSPI_CS0_A_MARK,        HRX1_A_MARK,    SCK1_C_MARK,    VI1_HSYNC_MARK,
+        HSPI_RX0_A_MARK,        HRTS1_A_MARK,   FMCLK_A_MARK,   RX1_C_MARK,
+        VI1_VSYNC_MARK, HSPI_TX0_MARK,  HCTS1_A_MARK,   BPFCLK_A_MARK,
+        TX1_C_MARK,     TCLK0_MARK,     HSCK1_A_MARK,   FMIN_A_MARK,
+        IRQ2_C_MARK,    CTS1_C_MARK,    SPEEDIN_MARK,   VI0_CLK_MARK,
+        CAN_CLK_A_MARK, VI0_CLKENB_MARK,                SD2_DAT2_B_MARK,
+        VI1_DATA0_MARK, DU1_DG6_MARK,   HSPI_RX1_A_MARK,
+        RX4_B_MARK,     VI0_FIELD_MARK, SD2_DAT3_B_MARK,
+        VI0_R3_C_MARK,  VI1_DATA1_MARK, DU1_DG7_MARK,   HSPI_CLK1_A_MARK,
+        TX4_B_MARK,     VI0_HSYNC_MARK, SD2_CD_B_MARK,  VI1_DATA2_MARK,
+        DU1_DR2_MARK,   HSPI_CS1_A_MARK,                RX3_B_MARK,
+
+        /* IPSR8 */
+        VI0_VSYNC_MARK, SD2_WP_B_MARK,  VI1_DATA3_MARK, DU1_DR3_MARK,
+        HSPI_TX1_A_MARK,                TX3_B_MARK,     VI0_DATA0_VI0_B0_MARK,
+        DU1_DG2_MARK,   IRQ2_B_MARK,    RX3_D_MARK,     VI0_DATA1_VI0_B1_MARK,
+        DU1_DG3_MARK,   IRQ3_B_MARK,    TX3_D_MARK,     VI0_DATA2_VI0_B2_MARK,
+        DU1_DG4_MARK,   RX0_C_MARK,     VI0_DATA3_VI0_B3_MARK,
+        DU1_DG5_MARK,   TX1_A_MARK,     TX0_C_MARK,     VI0_DATA4_VI0_B4_MARK,
+        DU1_DB2_MARK,   RX1_A_MARK,     VI0_DATA5_VI0_B5_MARK,
+        DU1_DB3_MARK,   SCK1_A_MARK,    PWM4_MARK,      HSCK1_B_MARK,
+        VI0_DATA6_VI0_G0_MARK,          DU1_DB4_MARK,   CTS1_A_MARK,
+        PWM5_MARK,      VI0_DATA7_VI0_G1_MARK,          DU1_DB5_MARK,
+        RTS1_A_MARK,    VI0_G2_MARK,    SD2_CLK_B_MARK, VI1_DATA4_MARK,
+        DU1_DR4_MARK,   HTX1_B_MARK,    VI0_G3_MARK,    SD2_CMD_B_MARK,
+        VI1_DATA5_MARK, DU1_DR5_MARK,   HRX1_B_MARK,
+
+        /* IPSR9 */
+        VI0_G4_MARK,    SD2_DAT0_B_MARK,                VI1_DATA6_MARK,
+        DU1_DR6_MARK,   HRTS1_B_MARK,   VI0_G5_MARK,    SD2_DAT1_B_MARK,
+        VI1_DATA7_MARK, DU1_DR7_MARK,   HCTS1_B_MARK,   VI0_R0_A_MARK,
+        VI1_CLK_MARK,   ETH_REF_CLK_MARK,               DU1_DOTCLKIN_MARK,
+        VI0_R1_A_MARK,  VI1_DATA8_MARK, DU1_DB6_MARK,   ETH_TXD0_MARK,
+        PWM2_MARK,      TCLK1_MARK,     VI0_R2_A_MARK,  VI1_DATA9_MARK,
+        DU1_DB7_MARK,   ETH_TXD1_MARK,  PWM3_MARK,      VI0_R3_A_MARK,
+        ETH_CRS_DV_MARK,                IECLK_MARK,     SCK2_C_MARK,
+        VI0_R4_A_MARK,                  ETH_TX_EN_MARK, IETX_MARK,
+        TX2_C_MARK,     VI0_R5_A_MARK,  ETH_RX_ER_MARK, FMCLK_C_MARK,
+        IERX_MARK,      RX2_C_MARK,     VI1_DATA10_A_MARK,
+        DU1_DOTCLKOUT_MARK,             ETH_RXD0_MARK,
+        BPFCLK_C_MARK,  TX2_D_MARK,     SDA2_C_MARK,    VI1_DATA11_A_MARK,
+        DU1_EXHSYNC_DU1_HSYNC_MARK,     ETH_RXD1_MARK,  FMIN_C_MARK,
+        RX2_D_MARK,     SCL2_C_MARK,
+
+        /* IPSR10 */
+        SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,     ATARD1_MARK,
+        ETH_MDC_MARK,   SDA1_B_MARK,    SD2_CMD_A_MARK,
+        DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,              ATAWR1_MARK,
+        ETH_MDIO_MARK,  SCL1_B_MARK,    SD2_DAT0_A_MARK,
+        DU1_DISP_MARK,  ATACS01_MARK,   DREQ1_B_MARK,   ETH_LINK_MARK,
+        CAN1_RX_A_MARK, SD2_DAT1_A_MARK,                DU1_CDE_MARK,
+        ATACS11_MARK,   DACK1_B_MARK,   ETH_MAGIC_MARK, CAN1_TX_A_MARK,
+        PWM6_MARK,      SD2_DAT2_A_MARK,                VI1_DATA12_MARK,
+        DREQ2_B_MARK,   ATADIR1_MARK,   HSPI_CLK2_B_MARK,
+        GPSCLK_B_MARK,  SD2_DAT3_A_MARK,                VI1_DATA13_MARK,
+        DACK2_B_MARK,   ATAG1_MARK,     HSPI_CS2_B_MARK,
+        GPSIN_B_MARK,   SD2_CD_A_MARK,  VI1_DATA14_MARK,
+        EX_WAIT1_B_MARK,                DREQ0_B_MARK,   HSPI_RX2_B_MARK,
+        REMOCON_A_MARK, SD2_WP_A_MARK,  VI1_DATA15_MARK,
+        EX_WAIT2_B_MARK,                DACK0_B_MARK,
+        HSPI_TX2_B_MARK,                CAN_CLK_C_MARK,
+
+        PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+        PINMUX_DATA(PENC0_MARK,         FN_PENC0),
+        PINMUX_DATA(PENC1_MARK,         FN_PENC1),
+        PINMUX_DATA(A1_MARK,            FN_A1),
+        PINMUX_DATA(A2_MARK,            FN_A2),
+        PINMUX_DATA(A3_MARK,            FN_A3),
+        PINMUX_DATA(WE0_MARK,           FN_WE0),
+        PINMUX_DATA(AUDIO_CLKA_MARK,    FN_AUDIO_CLKA),
+        PINMUX_DATA(AUDIO_CLKB_MARK,    FN_AUDIO_CLKB),
+        PINMUX_DATA(SSI_SCK34_MARK,     FN_SSI_SCK34),
+        PINMUX_DATA(AVS1_MARK,          FN_AVS1),
+        PINMUX_DATA(AVS2_MARK,          FN_AVS2),
+
+        /* IPSR0 */
+        PINMUX_IPSR_DATA(IP0_1_0,       PRESETOUT),
+        PINMUX_IPSR_DATA(IP0_1_0,       PWM1),
+
+        PINMUX_IPSR_DATA(IP0_4_2,       AUDATA0),
+        PINMUX_IPSR_DATA(IP0_4_2,       ARM_TRACEDATA_0),
+        PINMUX_IPSR_MSEL(IP0_4_2,       GPSCLK_C,       SEL_GPS_C),
+        PINMUX_IPSR_DATA(IP0_4_2,       USB_OVC0),
+        PINMUX_IPSR_DATA(IP0_4_2,       TX2_E),
+        PINMUX_IPSR_MSEL(IP0_4_2,       SDA2_B,         SEL_I2C2_B),
+
+        PINMUX_IPSR_DATA(IP0_7_5,       AUDATA1),
+        PINMUX_IPSR_DATA(IP0_7_5,       ARM_TRACEDATA_1),
+        PINMUX_IPSR_MSEL(IP0_7_5,       GPSIN_C,        SEL_GPS_C),
+        PINMUX_IPSR_DATA(IP0_7_5,       USB_OVC1),
+        PINMUX_IPSR_MSEL(IP0_7_5,       RX2_E,          SEL_SCIF2_E),
+        PINMUX_IPSR_MSEL(IP0_7_5,       SCL2_B,         SEL_I2C2_B),
+
+        PINMUX_IPSR_MSEL(IP0_11_8,      SD1_DAT2_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      MMC_D2),
+        PINMUX_IPSR_DATA(IP0_11_8,      BS),
+        PINMUX_IPSR_DATA(IP0_11_8,      ATADIR0_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      SDSELF_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      PWM4_B),
+
+        PINMUX_IPSR_MSEL(IP0_14_12,     SD1_DAT3_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP0_14_12,     MMC_D3),
+        PINMUX_IPSR_DATA(IP0_14_12,     A0),
+        PINMUX_IPSR_DATA(IP0_14_12,     ATAG0_A),
+        PINMUX_IPSR_MSEL(IP0_14_12,     REMOCON_B,      SEL_REMOCON_B),
+
+        PINMUX_IPSR_DATA(IP0_15,        A4),
+        PINMUX_IPSR_DATA(IP0_16,        A5),
+        PINMUX_IPSR_DATA(IP0_17,        A6),
+        PINMUX_IPSR_DATA(IP0_18,        A7),
+        PINMUX_IPSR_DATA(IP0_19,        A8),
+        PINMUX_IPSR_DATA(IP0_20,        A9),
+        PINMUX_IPSR_DATA(IP0_21,        A10),
+        PINMUX_IPSR_DATA(IP0_22,        A11),
+        PINMUX_IPSR_DATA(IP0_23,        A12),
+        PINMUX_IPSR_DATA(IP0_24,        A13),
+        PINMUX_IPSR_DATA(IP0_25,        A14),
+        PINMUX_IPSR_DATA(IP0_26,        A15),
+        PINMUX_IPSR_DATA(IP0_27,        A16),
+        PINMUX_IPSR_DATA(IP0_28,        A17),
+        PINMUX_IPSR_DATA(IP0_29,        A18),
+        PINMUX_IPSR_DATA(IP0_30,        A19),
+
+        /* IPSR1 */
+        PINMUX_IPSR_DATA(IP1_0,         A20),
+        PINMUX_IPSR_MSEL(IP1_0,         HSPI_CS1_B,     SEL_HSPI1_B),
+
+        PINMUX_IPSR_DATA(IP1_1,         A21),
+        PINMUX_IPSR_MSEL(IP1_1,         HSPI_CLK1_B,    SEL_HSPI1_B),
+
+        PINMUX_IPSR_DATA(IP1_4_2,       A22),
+        PINMUX_IPSR_MSEL(IP1_4_2,       HRTS0_B,        SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_4_2,       RX2_B,          SEL_SCIF2_B),
+        PINMUX_IPSR_MSEL(IP1_4_2,       DREQ2_A,        SEL_DREQ2_A),
+
+        PINMUX_IPSR_DATA(IP1_7_5,       A23),
+        PINMUX_IPSR_DATA(IP1_7_5,       HTX0_B),
+        PINMUX_IPSR_DATA(IP1_7_5,       TX2_B),
+        PINMUX_IPSR_DATA(IP1_7_5,       DACK2_A),
+        PINMUX_IPSR_MSEL(IP1_7_5,       TS_SDEN0_A,     SEL_TSIF0_A),
+
+        PINMUX_IPSR_MSEL(IP1_10_8,      SD1_CD_A,       SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP1_10_8,      MMC_D6),
+        PINMUX_IPSR_DATA(IP1_10_8,      A24),
+        PINMUX_IPSR_MSEL(IP1_10_8,      DREQ1_A,        SEL_DREQ1_A),
+        PINMUX_IPSR_MSEL(IP1_10_8,      HRX0_B,         SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_10_8,      TS_SPSYNC0_A,   SEL_TSIF0_A),
+
+        PINMUX_IPSR_MSEL(IP1_14_11,     SD1_WP_A,       SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP1_14_11,     MMC_D7),
+        PINMUX_IPSR_DATA(IP1_14_11,     A25),
+        PINMUX_IPSR_DATA(IP1_14_11,     DACK1_A),
+        PINMUX_IPSR_MSEL(IP1_14_11,     HCTS0_B,        SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_14_11,     RX3_C,          SEL_SCIF3_C),
+        PINMUX_IPSR_MSEL(IP1_14_11,     TS_SDAT0_A,     SEL_TSIF0_A),
+
+        PINMUX_IPSR_NOGP(IP1_16_15,     CLKOUT),
+        PINMUX_IPSR_NOGP(IP1_16_15,     HSPI_TX1_B),
+        PINMUX_IPSR_NOGP(IP1_16_15,     PWM0_B),
+
+        PINMUX_IPSR_NOGP(IP1_17,        CS0),
+        PINMUX_IPSR_NOGM(IP1_17,        HSPI_RX1_B,     SEL_HSPI1_B),
+
+        PINMUX_IPSR_NOGM(IP1_20_18,     SSI_SCK1_B,     SEL_SSI1_B),
+        PINMUX_IPSR_NOGP(IP1_20_18,     ATAG0_B),
+        PINMUX_IPSR_NOGP(IP1_20_18,     CS1_A26),
+        PINMUX_IPSR_NOGM(IP1_20_18,     SDA2_A,         SEL_I2C2_A),
+        PINMUX_IPSR_NOGM(IP1_20_18,     SCK2_B,         SEL_SCIF2_B),
+
+        PINMUX_IPSR_DATA(IP1_23_21,     MMC_D5),
+        PINMUX_IPSR_DATA(IP1_23_21,     ATADIR0_B),
+        PINMUX_IPSR_DATA(IP1_23_21,     RD_WR),
+
+        PINMUX_IPSR_DATA(IP1_24,        WE1),
+        PINMUX_IPSR_DATA(IP1_24,        ATAWR0_B),
+
+        PINMUX_IPSR_MSEL(IP1_27_25,     SSI_WS1_B,      SEL_SSI1_B),
+        PINMUX_IPSR_DATA(IP1_27_25,     EX_CS0),
+        PINMUX_IPSR_MSEL(IP1_27_25,     SCL2_A,         SEL_I2C2_A),
+        PINMUX_IPSR_DATA(IP1_27_25,     TX3_C),
+        PINMUX_IPSR_MSEL(IP1_27_25,     TS_SCK0_A,      SEL_TSIF0_A),
+
+        PINMUX_IPSR_DATA(IP1_29_28,     EX_CS1),
+        PINMUX_IPSR_DATA(IP1_29_28,     MMC_D4),
+
+        /* IPSR2 */
+        PINMUX_IPSR_DATA(IP2_2_0,       SD1_CLK_A),
+        PINMUX_IPSR_DATA(IP2_2_0,       MMC_CLK),
+        PINMUX_IPSR_DATA(IP2_2_0,       ATACS00),
+        PINMUX_IPSR_DATA(IP2_2_0,       EX_CS2),
+
+        PINMUX_IPSR_MSEL(IP2_5_3,       SD1_CMD_A,      SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_5_3,       MMC_CMD),
+        PINMUX_IPSR_DATA(IP2_5_3,       ATACS10),
+        PINMUX_IPSR_DATA(IP2_5_3,       EX_CS3),
+
+        PINMUX_IPSR_MSEL(IP2_8_6,       SD1_DAT0_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_8_6,       MMC_D0),
+        PINMUX_IPSR_DATA(IP2_8_6,       ATARD0),
+        PINMUX_IPSR_DATA(IP2_8_6,       EX_CS4),
+        PINMUX_IPSR_MSEL(IP2_8_6,       EX_WAIT1_A,     SEL_WAIT1_A),
+
+        PINMUX_IPSR_MSEL(IP2_11_9,      SD1_DAT1_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_11_9,      MMC_D1),
+        PINMUX_IPSR_DATA(IP2_11_9,      ATAWR0_A),
+        PINMUX_IPSR_DATA(IP2_11_9,      EX_CS5),
+        PINMUX_IPSR_MSEL(IP2_11_9,      EX_WAIT2_A,     SEL_WAIT2_A),
+
+        PINMUX_IPSR_MSEL(IP2_13_12,     DREQ0_A,        SEL_DREQ0_A),
+        PINMUX_IPSR_MSEL(IP2_13_12,     RX3_A,          SEL_SCIF3_A),
+
+        PINMUX_IPSR_DATA(IP2_16_14,     DACK0),
+        PINMUX_IPSR_DATA(IP2_16_14,     TX3_A),
+        PINMUX_IPSR_DATA(IP2_16_14,     DRACK0),
+
+        PINMUX_IPSR_DATA(IP2_17,        EX_WAIT0),
+        PINMUX_IPSR_DATA(IP2_17,        PWM0_C),
+
+        PINMUX_IPSR_NOGP(IP2_18,        D0),
+        PINMUX_IPSR_NOGP(IP2_19,        D1),
+        PINMUX_IPSR_NOGP(IP2_20,        D2),
+        PINMUX_IPSR_NOGP(IP2_21,        D3),
+        PINMUX_IPSR_NOGP(IP2_22,        D4),
+        PINMUX_IPSR_NOGP(IP2_23,        D5),
+        PINMUX_IPSR_NOGP(IP2_24,        D6),
+        PINMUX_IPSR_NOGP(IP2_25,        D7),
+        PINMUX_IPSR_NOGP(IP2_26,        D8),
+        PINMUX_IPSR_NOGP(IP2_27,        D9),
+        PINMUX_IPSR_NOGP(IP2_28,        D10),
+        PINMUX_IPSR_NOGP(IP2_29,        D11),
+
+        PINMUX_IPSR_DATA(IP2_30,        RD_WR_B),
+        PINMUX_IPSR_DATA(IP2_30,        IRQ0),
+
+        PINMUX_IPSR_DATA(IP2_31,        MLB_CLK),
+        PINMUX_IPSR_MSEL(IP2_31,        IRQ1_A,         SEL_IRQ1_A),
+
+        /* IPSR3 */
+        PINMUX_IPSR_DATA(IP3_1_0,       MLB_SIG),
+        PINMUX_IPSR_MSEL(IP3_1_0,       RX5_B,          SEL_SCIF5_B),
+        PINMUX_IPSR_MSEL(IP3_1_0,       SDA3_A,         SEL_I2C3_A),
+        PINMUX_IPSR_MSEL(IP3_1_0,       IRQ2_A,         SEL_IRQ2_A),
+
+        PINMUX_IPSR_DATA(IP3_4_2,       MLB_DAT),
+        PINMUX_IPSR_DATA(IP3_4_2,       TX5_B),
+        PINMUX_IPSR_MSEL(IP3_4_2,       SCL3_A,         SEL_I2C3_A),
+        PINMUX_IPSR_MSEL(IP3_4_2,       IRQ3_A,         SEL_IRQ3_A),
+        PINMUX_IPSR_DATA(IP3_4_2,       SDSELF_B),
+
+        PINMUX_IPSR_MSEL(IP3_7_5,       SD1_CMD_B,      SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP3_7_5,       SCIF_CLK),
+        PINMUX_IPSR_DATA(IP3_7_5,       AUDIO_CLKOUT_B),
+        PINMUX_IPSR_MSEL(IP3_7_5,       CAN_CLK_B,      SEL_CANCLK_B),
+        PINMUX_IPSR_MSEL(IP3_7_5,       SDA3_B,         SEL_I2C3_B),
+
+        PINMUX_IPSR_DATA(IP3_9_8,       SD1_CLK_B),
+        PINMUX_IPSR_DATA(IP3_9_8,       HTX0_A),
+        PINMUX_IPSR_DATA(IP3_9_8,       TX0_A),
+
+        PINMUX_IPSR_MSEL(IP3_12_10,     SD1_DAT0_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_12_10,     HRX0_A,         SEL_HSCIF0_A),
+        PINMUX_IPSR_MSEL(IP3_12_10,     RX0_A,          SEL_SCIF0_A),
+
+        PINMUX_IPSR_MSEL(IP3_15_13,     SD1_DAT1_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_15_13,     HSCK0,          SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_15_13,     SCK0),
+        PINMUX_IPSR_MSEL(IP3_15_13,     SCL3_B,         SEL_I2C3_B),
+
+        PINMUX_IPSR_MSEL(IP3_18_16,     SD1_DAT2_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_18_16,     HCTS0_A,        SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_18_16,     CTS0),
+
+        PINMUX_IPSR_MSEL(IP3_20_19,     SD1_DAT3_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_20_19,     HRTS0_A,        SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_20_19,     RTS0),
+
+        PINMUX_IPSR_DATA(IP3_23_21,     SSI_SCK4),
+        PINMUX_IPSR_DATA(IP3_23_21,     DU0_DR0),
+        PINMUX_IPSR_DATA(IP3_23_21,     LCDOUT0),
+        PINMUX_IPSR_DATA(IP3_23_21,     AUDATA2),
+        PINMUX_IPSR_DATA(IP3_23_21,     ARM_TRACEDATA_2),
+        PINMUX_IPSR_MSEL(IP3_23_21,     SDA3_C,         SEL_I2C3_C),
+        PINMUX_IPSR_DATA(IP3_23_21,     ADICHS1),
+        PINMUX_IPSR_MSEL(IP3_23_21,     TS_SDEN0_B,     SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP3_26_24,     SSI_WS4),
+        PINMUX_IPSR_DATA(IP3_26_24,     DU0_DR1),
+        PINMUX_IPSR_DATA(IP3_26_24,     LCDOUT1),
+        PINMUX_IPSR_DATA(IP3_26_24,     AUDATA3),
+        PINMUX_IPSR_DATA(IP3_26_24,     ARM_TRACEDATA_3),
+        PINMUX_IPSR_MSEL(IP3_26_24,     SCL3_C,         SEL_I2C3_C),
+        PINMUX_IPSR_DATA(IP3_26_24,     ADICHS2),
+        PINMUX_IPSR_MSEL(IP3_26_24,     TS_SPSYNC0_B,   SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP3_27,        DU0_DR2),
+        PINMUX_IPSR_DATA(IP3_27,        LCDOUT2),
+
+        PINMUX_IPSR_DATA(IP3_28,        DU0_DR3),
+        PINMUX_IPSR_DATA(IP3_28,        LCDOUT3),
+
+        PINMUX_IPSR_DATA(IP3_29,        DU0_DR4),
+        PINMUX_IPSR_DATA(IP3_29,        LCDOUT4),
+
+        PINMUX_IPSR_DATA(IP3_30,        DU0_DR5),
+        PINMUX_IPSR_DATA(IP3_30,        LCDOUT5),
+
+        PINMUX_IPSR_DATA(IP3_31,        DU0_DR6),
+        PINMUX_IPSR_DATA(IP3_31,        LCDOUT6),
+
+        /* IPSR4 */
+        PINMUX_IPSR_DATA(IP4_0,         DU0_DR7),
+        PINMUX_IPSR_DATA(IP4_0,         LCDOUT7),
+
+        PINMUX_IPSR_DATA(IP4_3_1,       DU0_DG0),
+        PINMUX_IPSR_DATA(IP4_3_1,       LCDOUT8),
+        PINMUX_IPSR_DATA(IP4_3_1,       AUDATA4),
+        PINMUX_IPSR_DATA(IP4_3_1,       ARM_TRACEDATA_4),
+        PINMUX_IPSR_DATA(IP4_3_1,       TX1_D),
+        PINMUX_IPSR_DATA(IP4_3_1,       CAN0_TX_A),
+        PINMUX_IPSR_DATA(IP4_3_1,       ADICHS0),
+
+        PINMUX_IPSR_DATA(IP4_6_4,       DU0_DG1),
+        PINMUX_IPSR_DATA(IP4_6_4,       LCDOUT9),
+        PINMUX_IPSR_DATA(IP4_6_4,       AUDATA5),
+        PINMUX_IPSR_DATA(IP4_6_4,       ARM_TRACEDATA_5),
+        PINMUX_IPSR_MSEL(IP4_6_4,       RX1_D,          SEL_SCIF1_D),
+        PINMUX_IPSR_MSEL(IP4_6_4,       CAN0_RX_A,      SEL_CAN0_A),
+        PINMUX_IPSR_DATA(IP4_6_4,       ADIDATA),
+
+        PINMUX_IPSR_DATA(IP4_7,         DU0_DG2),
+        PINMUX_IPSR_DATA(IP4_7,         LCDOUT10),
+
+        PINMUX_IPSR_DATA(IP4_8,         DU0_DG3),
+        PINMUX_IPSR_DATA(IP4_8,         LCDOUT11),
+
+        PINMUX_IPSR_DATA(IP4_10_9,      DU0_DG4),
+        PINMUX_IPSR_DATA(IP4_10_9,      LCDOUT12),
+        PINMUX_IPSR_MSEL(IP4_10_9,      RX0_B,          SEL_SCIF0_B),
+
+        PINMUX_IPSR_DATA(IP4_12_11,     DU0_DG5),
+        PINMUX_IPSR_DATA(IP4_12_11,     LCDOUT13),
+        PINMUX_IPSR_DATA(IP4_12_11,     TX0_B),
+
+        PINMUX_IPSR_DATA(IP4_14_13,     DU0_DG6),
+        PINMUX_IPSR_DATA(IP4_14_13,     LCDOUT14),
+        PINMUX_IPSR_MSEL(IP4_14_13,     RX4_A,          SEL_SCIF4_A),
+
+        PINMUX_IPSR_DATA(IP4_16_15,     DU0_DG7),
+        PINMUX_IPSR_DATA(IP4_16_15,     LCDOUT15),
+        PINMUX_IPSR_DATA(IP4_16_15,     TX4_A),
+
+        PINMUX_IPSR_MSEL(IP4_20_17,     SSI_SCK2_B,     SEL_SSI2_B),
+        PINMUX_DATA(VI0_R0_B_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R0_D_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_20_17,     DU0_DB0),
+        PINMUX_IPSR_DATA(IP4_20_17,     LCDOUT16),
+        PINMUX_IPSR_DATA(IP4_20_17,     AUDATA6),
+        PINMUX_IPSR_DATA(IP4_20_17,     ARM_TRACEDATA_6),
+        PINMUX_IPSR_MSEL(IP4_20_17,     GPSCLK_A,       SEL_GPS_A),
+        PINMUX_IPSR_DATA(IP4_20_17,     PWM0_A),
+        PINMUX_IPSR_DATA(IP4_20_17,     ADICLK),
+        PINMUX_IPSR_MSEL(IP4_20_17,     TS_SDAT0_B,     SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP4_24_21,     AUDIO_CLKC),
+        PINMUX_DATA(VI0_R1_B_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R1_D_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_24_21,     DU0_DB1),
+        PINMUX_IPSR_DATA(IP4_24_21,     LCDOUT17),
+        PINMUX_IPSR_DATA(IP4_24_21,     AUDATA7),
+        PINMUX_IPSR_DATA(IP4_24_21,     ARM_TRACEDATA_7),
+        PINMUX_IPSR_MSEL(IP4_24_21,     GPSIN_A,        SEL_GPS_A),
+        PINMUX_IPSR_DATA(IP4_24_21,     ADICS_SAMP),
+        PINMUX_IPSR_MSEL(IP4_24_21,     TS_SCK0_B,      SEL_TSIF0_B),
+
+        PINMUX_DATA(VI0_R2_B_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R2_D_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_26_25,     DU0_DB2),
+        PINMUX_IPSR_DATA(IP4_26_25,     LCDOUT18),
+
+        PINMUX_IPSR_MSEL(IP4_28_27,     VI0_R3_B,       SEL_VI0_B),
+        PINMUX_IPSR_DATA(IP4_28_27,     DU0_DB3),
+        PINMUX_IPSR_DATA(IP4_28_27,     LCDOUT19),
+
+        PINMUX_DATA(VI0_R4_B_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R4_D_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_30_29,     DU0_DB4),
+        PINMUX_IPSR_DATA(IP4_30_29,     LCDOUT20),
+
+        /* IPSR5 */
+        PINMUX_DATA(VI0_R5_B_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R5_D_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP5_1_0,       DU0_DB5),
+        PINMUX_IPSR_DATA(IP5_1_0,       LCDOUT21),
+
+        PINMUX_IPSR_MSEL(IP5_3_2,       VI1_DATA10_B,   SEL_VI1_B),
+        PINMUX_IPSR_DATA(IP5_3_2,       DU0_DB6),
+        PINMUX_IPSR_DATA(IP5_3_2,       LCDOUT22),
+
+        PINMUX_IPSR_MSEL(IP5_5_4,       VI1_DATA11_B,   SEL_VI1_B),
+        PINMUX_IPSR_DATA(IP5_5_4,       DU0_DB7),
+        PINMUX_IPSR_DATA(IP5_5_4,       LCDOUT23),
+
+        PINMUX_IPSR_DATA(IP5_6,         DU0_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP5_6,         QSTVA_QVS),
+
+        PINMUX_IPSR_DATA(IP5_7,         DU0_DOTCLKO_UT0),
+        PINMUX_IPSR_DATA(IP5_7,         QCLK),
+
+        PINMUX_IPSR_DATA(IP5_9_8,       DU0_DOTCLKO_UT1),
+        PINMUX_IPSR_DATA(IP5_9_8,       QSTVB_QVE),
+        PINMUX_IPSR_DATA(IP5_9_8,       AUDIO_CLKOUT_A),
+        PINMUX_IPSR_MSEL(IP5_9_8,       REMOCON_C,      SEL_REMOCON_C),
+
+        PINMUX_IPSR_MSEL(IP5_11_10,     SSI_WS2_B,      SEL_SSI2_B),
+        PINMUX_IPSR_DATA(IP5_11_10,     DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_DATA(IP5_11_10,     QSTH_QHS),
+
+        PINMUX_IPSR_DATA(IP5_12,        DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_DATA(IP5_12,        QSTB_QHE),
+
+        PINMUX_IPSR_DATA(IP5_14_13,     DU0_EXODDF_DU0_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP5_14_13,     QCPV_QDE),
+        PINMUX_IPSR_MSEL(IP5_14_13,     FMCLK_D,        SEL_FM_D),
+
+        PINMUX_IPSR_MSEL(IP5_17_15,     SSI_SCK1_A,     SEL_SSI1_A),
+        PINMUX_IPSR_DATA(IP5_17_15,     DU0_DISP),
+        PINMUX_IPSR_DATA(IP5_17_15,     QPOLA),
+        PINMUX_IPSR_DATA(IP5_17_15,     AUDCK),
+        PINMUX_IPSR_DATA(IP5_17_15,     ARM_TRACECLK),
+        PINMUX_IPSR_DATA(IP5_17_15,     BPFCLK_D),
+
+        PINMUX_IPSR_MSEL(IP5_20_18,     SSI_WS1_A,      SEL_SSI1_A),
+        PINMUX_IPSR_DATA(IP5_20_18,     DU0_CDE),
+        PINMUX_IPSR_DATA(IP5_20_18,     QPOLB),
+        PINMUX_IPSR_DATA(IP5_20_18,     AUDSYNC),
+        PINMUX_IPSR_DATA(IP5_20_18,     ARM_TRACECTL),
+        PINMUX_IPSR_MSEL(IP5_20_18,     FMIN_D,         SEL_FM_D),
+
+        PINMUX_IPSR_MSEL(IP5_22_21,     SD1_CD_B,       SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP5_22_21,     SSI_SCK78),
+        PINMUX_IPSR_MSEL(IP5_22_21,     HSPI_RX0_B,     SEL_HSPI0_B),
+        PINMUX_IPSR_DATA(IP5_22_21,     TX1_B),
+
+        PINMUX_IPSR_MSEL(IP5_25_23,     SD1_WP_B,       SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP5_25_23,     SSI_WS78),
+        PINMUX_IPSR_MSEL(IP5_25_23,     HSPI_CLK0_B,    SEL_HSPI0_B),
+        PINMUX_IPSR_MSEL(IP5_25_23,     RX1_B,          SEL_SCIF1_B),
+        PINMUX_IPSR_MSEL(IP5_25_23,     CAN_CLK_D,      SEL_CANCLK_D),
+
+        PINMUX_IPSR_DATA(IP5_28_26,     SSI_SDATA8),
+        PINMUX_IPSR_MSEL(IP5_28_26,     SSI_SCK2_A,     SEL_SSI2_A),
+        PINMUX_IPSR_MSEL(IP5_28_26,     HSPI_CS0_B,     SEL_HSPI0_B),
+        PINMUX_IPSR_DATA(IP5_28_26,     TX2_A),
+        PINMUX_IPSR_DATA(IP5_28_26,     CAN0_TX_B),
+
+        PINMUX_IPSR_DATA(IP5_30_29,     SSI_SDATA7),
+        PINMUX_IPSR_DATA(IP5_30_29,     HSPI_TX0_B),
+        PINMUX_IPSR_MSEL(IP5_30_29,     RX2_A,          SEL_SCIF2_A),
+        PINMUX_IPSR_MSEL(IP5_30_29,     CAN0_RX_B,      SEL_CAN0_B),
+
+        /* IPSR6 */
+        PINMUX_IPSR_DATA(IP6_1_0,       SSI_SCK6),
+        PINMUX_IPSR_MSEL(IP6_1_0,       HSPI_RX2_A,     SEL_HSPI2_A),
+        PINMUX_IPSR_MSEL(IP6_1_0,       FMCLK_B,        SEL_FM_B),
+        PINMUX_IPSR_DATA(IP6_1_0,       CAN1_TX_B),
+
+        PINMUX_IPSR_DATA(IP6_4_2,       SSI_WS6),
+        PINMUX_IPSR_MSEL(IP6_4_2,       HSPI_CLK2_A,    SEL_HSPI2_A),
+        PINMUX_IPSR_DATA(IP6_4_2,       BPFCLK_B),
+        PINMUX_IPSR_MSEL(IP6_4_2,       CAN1_RX_B,      SEL_CAN1_B),
+
+        PINMUX_IPSR_DATA(IP6_6_5,       SSI_SDATA6),
+        PINMUX_IPSR_DATA(IP6_6_5,       HSPI_TX2_A),
+        PINMUX_IPSR_MSEL(IP6_6_5,       FMIN_B,         SEL_FM_B),
+
+        PINMUX_IPSR_DATA(IP6_7,         SSI_SCK5),
+        PINMUX_IPSR_MSEL(IP6_7,         RX4_C,          SEL_SCIF4_C),
+
+        PINMUX_IPSR_DATA(IP6_8,         SSI_WS5),
+        PINMUX_IPSR_DATA(IP6_8,         TX4_C),
+
+        PINMUX_IPSR_DATA(IP6_9,         SSI_SDATA5),
+        PINMUX_IPSR_MSEL(IP6_9,         RX0_D,          SEL_SCIF0_D),
+
+        PINMUX_IPSR_DATA(IP6_10,        SSI_WS34),
+        PINMUX_IPSR_DATA(IP6_10,        ARM_TRACEDATA_8),
+
+        PINMUX_IPSR_DATA(IP6_12_11,     SSI_SDATA4),
+        PINMUX_IPSR_MSEL(IP6_12_11,     SSI_WS2_A,      SEL_SSI2_A),
+        PINMUX_IPSR_DATA(IP6_12_11,     ARM_TRACEDATA_9),
+
+        PINMUX_IPSR_DATA(IP6_13,        SSI_SDATA3),
+        PINMUX_IPSR_DATA(IP6_13,        ARM_TRACEDATA_10),
+
+        PINMUX_IPSR_DATA(IP6_15_14,     SSI_SCK012),
+        PINMUX_IPSR_DATA(IP6_15_14,     ARM_TRACEDATA_11),
+        PINMUX_IPSR_DATA(IP6_15_14,     TX0_D),
+
+        PINMUX_IPSR_DATA(IP6_16,        SSI_WS012),
+        PINMUX_IPSR_DATA(IP6_16,        ARM_TRACEDATA_12),
+
+        PINMUX_IPSR_DATA(IP6_18_17,     SSI_SDATA2),
+        PINMUX_IPSR_MSEL(IP6_18_17,     HSPI_CS2_A,     SEL_HSPI2_A),
+        PINMUX_IPSR_DATA(IP6_18_17,     ARM_TRACEDATA_13),
+        PINMUX_IPSR_MSEL(IP6_18_17,     SDA1_A,         SEL_I2C1_A),
+
+        PINMUX_IPSR_DATA(IP6_20_19,     SSI_SDATA1),
+        PINMUX_IPSR_DATA(IP6_20_19,     ARM_TRACEDATA_14),
+        PINMUX_IPSR_MSEL(IP6_20_19,     SCL1_A,         SEL_I2C1_A),
+        PINMUX_IPSR_MSEL(IP6_20_19,     SCK2_A,         SEL_SCIF2_A),
+
+        PINMUX_IPSR_DATA(IP6_21,        SSI_SDATA0),
+        PINMUX_IPSR_DATA(IP6_21,        ARM_TRACEDATA_15),
+
+        PINMUX_IPSR_DATA(IP6_23_22,     SD0_CLK),
+        PINMUX_IPSR_DATA(IP6_23_22,     SUB_TDO),
+
+        PINMUX_IPSR_DATA(IP6_25_24,     SD0_CMD),
+        PINMUX_IPSR_DATA(IP6_25_24,     SUB_TRST),
+
+        PINMUX_IPSR_DATA(IP6_27_26,     SD0_DAT0),
+        PINMUX_IPSR_DATA(IP6_27_26,     SUB_TMS),
+
+        PINMUX_IPSR_DATA(IP6_29_28,     SD0_DAT1),
+        PINMUX_IPSR_DATA(IP6_29_28,     SUB_TCK),
+
+        PINMUX_IPSR_DATA(IP6_31_30,     SD0_DAT2),
+        PINMUX_IPSR_DATA(IP6_31_30,     SUB_TDI),
+
+        /* IPSR7 */
+        PINMUX_IPSR_DATA(IP7_1_0,       SD0_DAT3),
+        PINMUX_IPSR_MSEL(IP7_1_0,       IRQ1_B,         SEL_IRQ1_B),
+
+        PINMUX_IPSR_DATA(IP7_3_2,       SD0_CD),
+        PINMUX_IPSR_DATA(IP7_3_2,       TX5_A),
+
+        PINMUX_IPSR_DATA(IP7_5_4,       SD0_WP),
+        PINMUX_IPSR_MSEL(IP7_5_4,       RX5_A,          SEL_SCIF5_A),
+
+        PINMUX_IPSR_DATA(IP7_8_6,       VI1_CLKENB),
+        PINMUX_IPSR_MSEL(IP7_8_6,       HSPI_CLK0_A,    SEL_HSPI0_A),
+        PINMUX_IPSR_DATA(IP7_8_6,       HTX1_A),
+        PINMUX_IPSR_MSEL(IP7_8_6,       RTS1_C,         SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_11_9,      VI1_FIELD),
+        PINMUX_IPSR_MSEL(IP7_11_9,      HSPI_CS0_A,     SEL_HSPI0_A),
+        PINMUX_IPSR_MSEL(IP7_11_9,      HRX1_A,         SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_11_9,      SCK1_C,         SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_14_12,     VI1_HSYNC),
+        PINMUX_IPSR_MSEL(IP7_14_12,     HSPI_RX0_A,     SEL_HSPI0_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     HRTS1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     FMCLK_A,        SEL_FM_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     RX1_C,          SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_17_15,     VI1_VSYNC),
+        PINMUX_IPSR_DATA(IP7_17_15,     HSPI_TX0),
+        PINMUX_IPSR_MSEL(IP7_17_15,     HCTS1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_DATA(IP7_17_15,     BPFCLK_A),
+        PINMUX_IPSR_DATA(IP7_17_15,     TX1_C),
+
+        PINMUX_IPSR_DATA(IP7_20_18,     TCLK0),
+        PINMUX_IPSR_MSEL(IP7_20_18,     HSCK1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_20_18,     FMIN_A,         SEL_FM_A),
+        PINMUX_IPSR_MSEL(IP7_20_18,     IRQ2_C,         SEL_IRQ2_C),
+        PINMUX_IPSR_MSEL(IP7_20_18,     CTS1_C,         SEL_SCIF1_C),
+        PINMUX_IPSR_DATA(IP7_20_18,     SPEEDIN),
+
+        PINMUX_IPSR_DATA(IP7_21,        VI0_CLK),
+        PINMUX_IPSR_MSEL(IP7_21,        CAN_CLK_A,      SEL_CANCLK_A),
+
+        PINMUX_IPSR_DATA(IP7_24_22,     VI0_CLKENB),
+        PINMUX_IPSR_MSEL(IP7_24_22,     SD2_DAT2_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP7_24_22,     VI1_DATA0),
+        PINMUX_IPSR_DATA(IP7_24_22,     DU1_DG6),
+        PINMUX_IPSR_MSEL(IP7_24_22,     HSPI_RX1_A,     SEL_HSPI1_A),
+        PINMUX_IPSR_MSEL(IP7_24_22,     RX4_B,          SEL_SCIF4_B),
+
+        PINMUX_IPSR_DATA(IP7_28_25,     VI0_FIELD),
+        PINMUX_IPSR_MSEL(IP7_28_25,     SD2_DAT3_B,     SEL_SD2_B),
+        PINMUX_DATA(VI0_R3_C_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R3_D_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP7_28_25,     VI1_DATA1),
+        PINMUX_IPSR_DATA(IP7_28_25,     DU1_DG7),
+        PINMUX_IPSR_MSEL(IP7_28_25,     HSPI_CLK1_A,    SEL_HSPI1_A),
+        PINMUX_IPSR_DATA(IP7_28_25,     TX4_B),
+
+        PINMUX_IPSR_DATA(IP7_31_29,     VI0_HSYNC),
+        PINMUX_IPSR_MSEL(IP7_31_29,     SD2_CD_B,       SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP7_31_29,     VI1_DATA2),
+        PINMUX_IPSR_DATA(IP7_31_29,     DU1_DR2),
+        PINMUX_IPSR_MSEL(IP7_31_29,     HSPI_CS1_A,     SEL_HSPI1_A),
+        PINMUX_IPSR_MSEL(IP7_31_29,     RX3_B,          SEL_SCIF3_B),
+
+        /* IPSR8 */
+        PINMUX_IPSR_DATA(IP8_2_0,       VI0_VSYNC),
+        PINMUX_IPSR_MSEL(IP8_2_0,       SD2_WP_B,       SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP8_2_0,       VI1_DATA3),
+        PINMUX_IPSR_DATA(IP8_2_0,       DU1_DR3),
+        PINMUX_IPSR_DATA(IP8_2_0,       HSPI_TX1_A),
+        PINMUX_IPSR_DATA(IP8_2_0,       TX3_B),
+
+        PINMUX_IPSR_DATA(IP8_5_3,       VI0_DATA0_VI0_B0),
+        PINMUX_IPSR_DATA(IP8_5_3,       DU1_DG2),
+        PINMUX_IPSR_MSEL(IP8_5_3,       IRQ2_B,         SEL_IRQ2_B),
+        PINMUX_IPSR_MSEL(IP8_5_3,       RX3_D,          SEL_SCIF3_D),
+
+        PINMUX_IPSR_DATA(IP8_8_6,       VI0_DATA1_VI0_B1),
+        PINMUX_IPSR_DATA(IP8_8_6,       DU1_DG3),
+        PINMUX_IPSR_MSEL(IP8_8_6,       IRQ3_B,         SEL_IRQ3_B),
+        PINMUX_IPSR_DATA(IP8_8_6,       TX3_D),
+
+        PINMUX_IPSR_DATA(IP8_10_9,      VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_DATA(IP8_10_9,      DU1_DG4),
+        PINMUX_IPSR_MSEL(IP8_10_9,      RX0_C,          SEL_SCIF0_C),
+
+        PINMUX_IPSR_DATA(IP8_13_11,     VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_DATA(IP8_13_11,     DU1_DG5),
+        PINMUX_IPSR_DATA(IP8_13_11,     TX1_A),
+        PINMUX_IPSR_DATA(IP8_13_11,     TX0_C),
+
+        PINMUX_IPSR_DATA(IP8_15_14,     VI0_DATA4_VI0_B4),
+        PINMUX_IPSR_DATA(IP8_15_14,     DU1_DB2),
+        PINMUX_IPSR_MSEL(IP8_15_14,     RX1_A,          SEL_SCIF1_A),
+
+        PINMUX_IPSR_DATA(IP8_18_16,     VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_DATA(IP8_18_16,     DU1_DB3),
+        PINMUX_IPSR_MSEL(IP8_18_16,     SCK1_A,         SEL_SCIF1_A),
+        PINMUX_IPSR_DATA(IP8_18_16,     PWM4),
+        PINMUX_IPSR_MSEL(IP8_18_16,     HSCK1_B,        SEL_HSCIF1_B),
+
+        PINMUX_IPSR_DATA(IP8_21_19,     VI0_DATA6_VI0_G0),
+        PINMUX_IPSR_DATA(IP8_21_19,     DU1_DB4),
+        PINMUX_IPSR_MSEL(IP8_21_19,     CTS1_A,         SEL_SCIF1_A),
+        PINMUX_IPSR_DATA(IP8_21_19,     PWM5),
+
+        PINMUX_IPSR_DATA(IP8_23_22,     VI0_DATA7_VI0_G1),
+        PINMUX_IPSR_DATA(IP8_23_22,     DU1_DB5),
+        PINMUX_IPSR_MSEL(IP8_23_22,     RTS1_A,         SEL_SCIF1_A),
+
+        PINMUX_IPSR_DATA(IP8_26_24,     VI0_G2),
+        PINMUX_IPSR_DATA(IP8_26_24,     SD2_CLK_B),
+        PINMUX_IPSR_DATA(IP8_26_24,     VI1_DATA4),
+        PINMUX_IPSR_DATA(IP8_26_24,     DU1_DR4),
+        PINMUX_IPSR_DATA(IP8_26_24,     HTX1_B),
+
+        PINMUX_IPSR_DATA(IP8_29_27,     VI0_G3),
+        PINMUX_IPSR_MSEL(IP8_29_27,     SD2_CMD_B,      SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP8_29_27,     VI1_DATA5),
+        PINMUX_IPSR_DATA(IP8_29_27,     DU1_DR5),
+        PINMUX_IPSR_MSEL(IP8_29_27,     HRX1_B,         SEL_HSCIF1_B),
+
+        /* IPSR9 */
+        PINMUX_IPSR_DATA(IP9_2_0,       VI0_G4),
+        PINMUX_IPSR_MSEL(IP9_2_0,       SD2_DAT0_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP9_2_0,       VI1_DATA6),
+        PINMUX_IPSR_DATA(IP9_2_0,       DU1_DR6),
+        PINMUX_IPSR_MSEL(IP9_2_0,       HRTS1_B,        SEL_HSCIF1_B),
+
+        PINMUX_IPSR_DATA(IP9_5_3,       VI0_G5),
+        PINMUX_IPSR_MSEL(IP9_5_3,       SD2_DAT1_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP9_5_3,       VI1_DATA7),
+        PINMUX_IPSR_DATA(IP9_5_3,       DU1_DR7),
+        PINMUX_IPSR_MSEL(IP9_5_3,       HCTS1_B,        SEL_HSCIF1_B),
+
+        PINMUX_DATA(VI0_R0_A_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R0_C_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_8_6,       VI1_CLK),
+        PINMUX_IPSR_DATA(IP9_8_6,       ETH_REF_CLK),
+        PINMUX_IPSR_DATA(IP9_8_6,       DU1_DOTCLKIN),
+
+        PINMUX_DATA(VI0_R1_A_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R1_C_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_11_9,      VI1_DATA8),
+        PINMUX_IPSR_DATA(IP9_11_9,      DU1_DB6),
+        PINMUX_IPSR_DATA(IP9_11_9,      ETH_TXD0),
+        PINMUX_IPSR_DATA(IP9_11_9,      PWM2),
+        PINMUX_IPSR_DATA(IP9_11_9,      TCLK1),
+
+        PINMUX_DATA(VI0_R2_A_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R2_C_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_14_12,     VI1_DATA9),
+        PINMUX_IPSR_DATA(IP9_14_12,     DU1_DB7),
+        PINMUX_IPSR_DATA(IP9_14_12,     ETH_TXD1),
+        PINMUX_IPSR_DATA(IP9_14_12,     PWM3),
+
+        PINMUX_IPSR_MSEL(IP9_17_15,     VI0_R3_A,       SEL_VI0_A),
+        PINMUX_IPSR_DATA(IP9_17_15,     ETH_CRS_DV),
+        PINMUX_IPSR_DATA(IP9_17_15,     IECLK),
+        PINMUX_IPSR_MSEL(IP9_17_15,     SCK2_C,         SEL_SCIF2_C),
+
+        PINMUX_DATA(VI0_R4_A_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R3_C_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_20_18,     ETH_TX_EN),
+        PINMUX_IPSR_DATA(IP9_20_18,     IETX),
+        PINMUX_IPSR_DATA(IP9_20_18,     TX2_C),
+
+        PINMUX_DATA(VI0_R5_A_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R5_C_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_23_21,     ETH_RX_ER),
+        PINMUX_IPSR_MSEL(IP9_23_21,     FMCLK_C,        SEL_FM_C),
+        PINMUX_IPSR_DATA(IP9_23_21,     IERX),
+        PINMUX_IPSR_MSEL(IP9_23_21,     RX2_C,          SEL_SCIF2_C),
+
+        PINMUX_IPSR_MSEL(IP9_26_24,     VI1_DATA10_A,   SEL_VI1_A),
+        PINMUX_IPSR_DATA(IP9_26_24,     DU1_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP9_26_24,     ETH_RXD0),
+        PINMUX_IPSR_DATA(IP9_26_24,     BPFCLK_C),
+        PINMUX_IPSR_DATA(IP9_26_24,     TX2_D),
+        PINMUX_IPSR_MSEL(IP9_26_24,     SDA2_C,         SEL_I2C2_C),
+
+        PINMUX_IPSR_MSEL(IP9_29_27,     VI1_DATA11_A,   SEL_VI1_A),
+        PINMUX_IPSR_DATA(IP9_29_27,     DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_DATA(IP9_29_27,     ETH_RXD1),
+        PINMUX_IPSR_MSEL(IP9_29_27,     FMIN_C,         SEL_FM_C),
+        PINMUX_IPSR_MSEL(IP9_29_27,     RX2_D,          SEL_SCIF2_D),
+        PINMUX_IPSR_MSEL(IP9_29_27,     SCL2_C,         SEL_I2C2_C),
+
+        /* IPSR10 */
+        PINMUX_IPSR_DATA(IP10_2_0,      SD2_CLK_A),
+        PINMUX_IPSR_DATA(IP10_2_0,      DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_DATA(IP10_2_0,      ATARD1),
+        PINMUX_IPSR_DATA(IP10_2_0,      ETH_MDC),
+        PINMUX_IPSR_MSEL(IP10_2_0,      SDA1_B,         SEL_I2C1_B),
+
+        PINMUX_IPSR_MSEL(IP10_5_3,      SD2_CMD_A,      SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_5_3,      DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP10_5_3,      ATAWR1),
+        PINMUX_IPSR_DATA(IP10_5_3,      ETH_MDIO),
+        PINMUX_IPSR_MSEL(IP10_5_3,      SCL1_B,         SEL_I2C1_B),
+
+        PINMUX_IPSR_MSEL(IP10_8_6,      SD2_DAT0_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_8_6,      DU1_DISP),
+        PINMUX_IPSR_DATA(IP10_8_6,      ATACS01),
+        PINMUX_IPSR_MSEL(IP10_8_6,      DREQ1_B,        SEL_DREQ1_B),
+        PINMUX_IPSR_DATA(IP10_8_6,      ETH_LINK),
+        PINMUX_IPSR_MSEL(IP10_8_6,      CAN1_RX_A,      SEL_CAN1_A),
+
+        PINMUX_IPSR_MSEL(IP10_12_9,     SD2_DAT1_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_12_9,     DU1_CDE),
+        PINMUX_IPSR_DATA(IP10_12_9,     ATACS11),
+        PINMUX_IPSR_DATA(IP10_12_9,     DACK1_B),
+        PINMUX_IPSR_DATA(IP10_12_9,     ETH_MAGIC),
+        PINMUX_IPSR_DATA(IP10_12_9,     CAN1_TX_A),
+        PINMUX_IPSR_DATA(IP10_12_9,     PWM6),
+
+        PINMUX_IPSR_MSEL(IP10_15_13,    SD2_DAT2_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_15_13,    VI1_DATA12),
+        PINMUX_IPSR_MSEL(IP10_15_13,    DREQ2_B,        SEL_DREQ2_B),
+        PINMUX_IPSR_DATA(IP10_15_13,    ATADIR1),
+        PINMUX_IPSR_MSEL(IP10_15_13,    HSPI_CLK2_B,    SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_15_13,    GPSCLK_B,       SEL_GPS_B),
+
+        PINMUX_IPSR_MSEL(IP10_18_16,    SD2_DAT3_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_18_16,    VI1_DATA13),
+        PINMUX_IPSR_DATA(IP10_18_16,    DACK2_B),
+        PINMUX_IPSR_DATA(IP10_18_16,    ATAG1),
+        PINMUX_IPSR_MSEL(IP10_18_16,    HSPI_CS2_B,     SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_18_16,    GPSIN_B,        SEL_GPS_B),
+
+        PINMUX_IPSR_MSEL(IP10_21_19,    SD2_CD_A,       SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_21_19,    VI1_DATA14),
+        PINMUX_IPSR_MSEL(IP10_21_19,    EX_WAIT1_B,     SEL_WAIT1_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    DREQ0_B,        SEL_DREQ0_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    HSPI_RX2_B,     SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    REMOCON_A,      SEL_REMOCON_A),
+
+        PINMUX_IPSR_MSEL(IP10_24_22,    SD2_WP_A,       SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_24_22,    VI1_DATA15),
+        PINMUX_IPSR_MSEL(IP10_24_22,    EX_WAIT2_B,     SEL_WAIT2_B),
+        PINMUX_IPSR_DATA(IP10_24_22,    DACK0_B),
+        PINMUX_IPSR_DATA(IP10_24_22,    HSPI_TX2_B),
+        PINMUX_IPSR_MSEL(IP10_24_22,    CAN_CLK_C,      SEL_CANCLK_C),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+};
+
+/* Pin numbers for pins without a corresponding GPIO port number are computed
+ * from the row and column numbers with a 1000 offset to avoid collisions with
+ * GPIO port numbers.
+ */
+#define PIN_NUMBER(row, col)            (1000+((row)-1)*25+(col)-1)
+
+/* - macro */
+#define SH_PFC_PINS(name, args...) \
+        static const unsigned int name ##_pins[] = { args }
+#define SH_PFC_MUX1(name, arg1)                                 \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK }
+#define SH_PFC_MUX2(name, arg1, arg2)                                   \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
+#define SH_PFC_MUX3(name, arg1, arg2, arg3)                                     \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,  \
+                                                     arg3##_MARK }
+#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)                       \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+                                                     arg3##_MARK, arg4##_MARK }
+#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+                                                     arg3##_MARK, arg4##_MARK, \
+                                                     arg5##_MARK, arg6##_MARK, \
+                                                     arg7##_MARK, arg8##_MARK, }
+
+/* - Ether ------------------------------------------------------------------ */
+SH_PFC_PINS(ether_rmii,         RCAR_GP_PIN(4, 10),     RCAR_GP_PIN(4, 11),
+                                RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 9),
+                                RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16),
+                                RCAR_GP_PIN(4, 12),     RCAR_GP_PIN(4, 14),
+                                RCAR_GP_PIN(4, 18),     RCAR_GP_PIN(4, 17));
+static const unsigned int ether_rmii_mux[] = {
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+        ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+SH_PFC_PINS(ether_link,         RCAR_GP_PIN(4, 19));
+SH_PFC_MUX1(ether_link,         ETH_LINK);
+SH_PFC_PINS(ether_magic,        RCAR_GP_PIN(4, 20));
+SH_PFC_MUX1(ether_magic,        ETH_MAGIC);
+
+/* - SCIF macro ------------------------------------------------------------- */
+#define SCIF_PFC_PIN(name, args...)     SH_PFC_PINS(name, args)
+#define SCIF_PFC_DAT(name, tx, rx)      SH_PFC_MUX2(name, tx, rx)
+#define SCIF_PFC_CTR(name, cts, rts)    SH_PFC_MUX2(name, cts, rts)
+#define SCIF_PFC_CLK(name, sck)         SH_PFC_MUX1(name, sck)
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif0_data_a,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(hscif0_data_a,     HTX0_A,                 HRX0_A);
+SCIF_PFC_PIN(hscif0_data_b,     RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 30));
+SCIF_PFC_DAT(hscif0_data_b,     HTX0_B,                 HRX0_B);
+SCIF_PFC_PIN(hscif0_ctrl_a,     RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(hscif0_ctrl_a,     HCTS0_A,                HRTS0_A);
+SCIF_PFC_PIN(hscif0_ctrl_b,     RCAR_GP_PIN(0, 31),     RCAR_GP_PIN(0, 28));
+SCIF_PFC_CTR(hscif0_ctrl_b,     HCTS0_B,                HRTS0_B);
+SCIF_PFC_PIN(hscif0_clk,        RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(hscif0_clk,        HSCK0);
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif1_data_a,     RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20));
+SCIF_PFC_DAT(hscif1_data_a,     HTX1_A,                 HRX1_A);
+SCIF_PFC_PIN(hscif1_data_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
+SCIF_PFC_DAT(hscif1_data_b,     HTX1_B,                 HRX1_B);
+SCIF_PFC_PIN(hscif1_ctrl_a,     RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
+SCIF_PFC_CTR(hscif1_ctrl_a,     HCTS1_A,                HRTS1_A);
+SCIF_PFC_PIN(hscif1_ctrl_b,     RCAR_GP_PIN(4, 8),      RCAR_GP_PIN(4, 7));
+SCIF_PFC_CTR(hscif1_ctrl_b,     HCTS1_B,                HRTS1_B);
+SCIF_PFC_PIN(hscif1_clk_a,      RCAR_GP_PIN(3, 23));
+SCIF_PFC_CLK(hscif1_clk_a,      HSCK1_A);
+SCIF_PFC_PIN(hscif1_clk_b,      RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(hscif1_clk_b,      HSCK1_B);
+
+/* - HSPI macro --------------------------------------------------------------*/
+#define HSPI_PFC_PIN(name, args...)             SH_PFC_PINS(name, args)
+#define HSPI_PFC_DAT(name, clk, cs, rx, tx)     SH_PFC_MUX4(name, clk, cs, rx, tx)
+
+/* - HSPI0 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi0_a,   RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20),
+                        RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
+HSPI_PFC_DAT(hspi0_a,   HSPI_CLK0_A,            HSPI_CS0_A,
+                        HSPI_RX0_A,             HSPI_TX0);
+
+HSPI_PFC_PIN(hspi0_b,   RCAR_GP_PIN(2, 25),     RCAR_GP_PIN(2, 26),
+                        RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 27));
+HSPI_PFC_DAT(hspi0_b,   HSPI_CLK0_B,            HSPI_CS0_B,
+                        HSPI_RX0_B,             HSPI_TX0_B);
+
+/* - HSPI1 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi1_a,   RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 27),
+                        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 28));
+HSPI_PFC_DAT(hspi1_a,   HSPI_CLK1_A,            HSPI_CS1_A,
+                        HSPI_RX1_A,             HSPI_TX1_A);
+
+HSPI_PFC_PIN(hspi1_b,   RCAR_GP_PIN(0, 27),     RCAR_GP_PIN(0, 26),
+                        PIN_NUMBER(20, 1),      PIN_NUMBER(25, 2));
+HSPI_PFC_DAT(hspi1_b,   HSPI_CLK1_B,            HSPI_CS1_B,
+                        HSPI_RX1_B,             HSPI_TX1_B);
+
+/* - HSPI2 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi2_a,   RCAR_GP_PIN(2, 29),     RCAR_GP_PIN(3, 8),
+                        RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 30));
+HSPI_PFC_DAT(hspi2_a,   HSPI_CLK2_A,            HSPI_CS2_A,
+                        HSPI_RX2_A,             HSPI_TX2_A);
+
+HSPI_PFC_PIN(hspi2_b,   RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22),
+                        RCAR_GP_PIN(4, 23),     RCAR_GP_PIN(4, 24));
+HSPI_PFC_DAT(hspi2_b,   HSPI_CLK2_B,            HSPI_CS2_B,
+                        HSPI_RX2_B,             HSPI_TX2_B);
+
+/* - I2C macro ------------------------------------------------------------- */
+#define I2C_PFC_PIN(name, args...)      SH_PFC_PINS(name, args)
+#define I2C_PFC_MUX(name, sda, scl)     SH_PFC_MUX2(name, sda, scl)
+
+/* - I2C1 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c1_a,     RCAR_GP_PIN(3, 8),      RCAR_GP_PIN(3, 9));
+I2C_PFC_MUX(i2c1_a,     SDA1_A,                 SCL1_A);
+I2C_PFC_PIN(i2c1_b,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
+I2C_PFC_MUX(i2c1_b,     SDA1_B,                 SCL1_B);
+
+/* - I2C2 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c2_a,     PIN_NUMBER(3, 20),      RCAR_GP_PIN(1, 3));
+I2C_PFC_MUX(i2c2_a,     SDA2_A,                 SCL2_A);
+I2C_PFC_PIN(i2c2_b,     RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
+I2C_PFC_MUX(i2c2_b,     SDA2_B,                 SCL2_B);
+I2C_PFC_PIN(i2c2_c,     RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
+I2C_PFC_MUX(i2c2_c,     SDA2_C,                 SCL2_C);
+
+/* - I2C3 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c3_a,     RCAR_GP_PIN(1, 14),     RCAR_GP_PIN(1, 15));
+I2C_PFC_MUX(i2c3_a,     SDA3_A,                 SCL3_A);
+I2C_PFC_PIN(i2c3_b,     RCAR_GP_PIN(1, 16),     RCAR_GP_PIN(1, 19));
+I2C_PFC_MUX(i2c3_b,     SDA3_B,                 SCL3_B);
+I2C_PFC_PIN(i2c3_c,     RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
+I2C_PFC_MUX(i2c3_c,     SDA3_C,                 SCL3_C);
+
+/* - MMC macro -------------------------------------------------------------- */
+#define MMC_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
+#define MMC_PFC_CTRL(name, clk, cmd)            SH_PFC_MUX2(name, clk, cmd)
+#define MMC_PFC_DAT1(name, d0)                  SH_PFC_MUX1(name, d0)
+#define MMC_PFC_DAT4(name, d0, d1, d2, d3)      SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
+                        SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+
+/* - MMC -------------------------------------------------------------------- */
+MMC_PFC_PINS(mmc_ctrl,          RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
+MMC_PFC_CTRL(mmc_ctrl,          MMC_CLK,                MMC_CMD);
+MMC_PFC_PINS(mmc_data1,         RCAR_GP_PIN(1, 7));
+MMC_PFC_DAT1(mmc_data1,         MMC_D0);
+MMC_PFC_PINS(mmc_data4,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(2, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
+MMC_PFC_DAT4(mmc_data4,         MMC_D0,                 MMC_D1,
+                                MMC_D2,                 MMC_D3);
+MMC_PFC_PINS(mmc_data8,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(2, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6),
+                                RCAR_GP_PIN(1, 4),      RCAR_GP_PIN(1, 0),
+                                RCAR_GP_PIN(0, 30),     RCAR_GP_PIN(0, 31));
+MMC_PFC_DAT8(mmc_data8,         MMC_D0,                 MMC_D1,
+                                MMC_D2,                 MMC_D3,
+                                MMC_D4,                 MMC_D5,
+                                MMC_D6,                 MMC_D7);
+
+/* - SCIF CLOCK ------------------------------------------------------------- */
+SCIF_PFC_PIN(scif_clk,          RCAR_GP_PIN(1, 16));
+SCIF_PFC_CLK(scif_clk,          SCIF_CLK);
+
+/* - SCIF0 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif0_data_a,      RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(scif0_data_a,      TX0_A,                  RX0_A);
+SCIF_PFC_PIN(scif0_data_b,      RCAR_GP_PIN(2, 3),      RCAR_GP_PIN(2, 2));
+SCIF_PFC_DAT(scif0_data_b,      TX0_B,                  RX0_B);
+SCIF_PFC_PIN(scif0_data_c,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(3, 31));
+SCIF_PFC_DAT(scif0_data_c,      TX0_C,                  RX0_C);
+SCIF_PFC_PIN(scif0_data_d,      RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 1));
+SCIF_PFC_DAT(scif0_data_d,      TX0_D,                  RX0_D);
+SCIF_PFC_PIN(scif0_ctrl,        RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(scif0_ctrl,        CTS0,                   RTS0);
+SCIF_PFC_PIN(scif0_clk,         RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(scif0_clk,         SCK0);
+
+/* - SCIF1 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif1_data_a,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(4, 1));
+SCIF_PFC_DAT(scif1_data_a,      TX1_A,                  RX1_A);
+SCIF_PFC_PIN(scif1_data_b,      RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
+SCIF_PFC_DAT(scif1_data_b,      TX1_B,                  RX1_B);
+SCIF_PFC_PIN(scif1_data_c,      RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
+SCIF_PFC_DAT(scif1_data_c,      TX1_C,                  RX1_C);
+SCIF_PFC_PIN(scif1_data_d,      RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
+SCIF_PFC_DAT(scif1_data_d,      TX1_D,                  RX1_D);
+SCIF_PFC_PIN(scif1_ctrl_a,      RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
+SCIF_PFC_CTR(scif1_ctrl_a,      CTS1_A,                 RTS1_A);
+SCIF_PFC_PIN(scif1_ctrl_c,      RCAR_GP_PIN(3, 23),     RCAR_GP_PIN(3, 19));
+SCIF_PFC_CTR(scif1_ctrl_c,      CTS1_C,                 RTS1_C);
+SCIF_PFC_PIN(scif1_clk_a,       RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(scif1_clk_a,       SCK1_A);
+SCIF_PFC_PIN(scif1_clk_c,       RCAR_GP_PIN(3, 20));
+SCIF_PFC_CLK(scif1_clk_c,       SCK1_C);
+
+/* - SCIF2 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif2_data_a,      RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
+SCIF_PFC_DAT(scif2_data_a,      TX2_A,                  RX2_A);
+SCIF_PFC_PIN(scif2_data_b,      RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 28));
+SCIF_PFC_DAT(scif2_data_b,      TX2_B,                  RX2_B);
+SCIF_PFC_PIN(scif2_data_c,      RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 14));
+SCIF_PFC_DAT(scif2_data_c,      TX2_C,                  RX2_C);
+SCIF_PFC_PIN(scif2_data_d,      RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
+SCIF_PFC_DAT(scif2_data_d,      TX2_D,                  RX2_D);
+SCIF_PFC_PIN(scif2_data_e,      RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
+SCIF_PFC_DAT(scif2_data_e,      TX2_E,                  RX2_E);
+SCIF_PFC_PIN(scif2_clk_a,       RCAR_GP_PIN(3, 9));
+SCIF_PFC_CLK(scif2_clk_a,       SCK2_A);
+SCIF_PFC_PIN(scif2_clk_b,       PIN_NUMBER(3, 20));
+SCIF_PFC_CLK(scif2_clk_b,       SCK2_B);
+SCIF_PFC_PIN(scif2_clk_c,       RCAR_GP_PIN(4, 12));
+SCIF_PFC_CLK(scif2_clk_c,       SCK2_C);
+
+/* - SCIF3 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif3_data_a,      RCAR_GP_PIN(1, 10),     RCAR_GP_PIN(1, 9));
+SCIF_PFC_DAT(scif3_data_a,      TX3_A,                  RX3_A);
+SCIF_PFC_PIN(scif3_data_b,      RCAR_GP_PIN(3, 28),     RCAR_GP_PIN(3, 27));
+SCIF_PFC_DAT(scif3_data_b,      TX3_B,                  RX3_B);
+SCIF_PFC_PIN(scif3_data_c,      RCAR_GP_PIN(1, 3),      RCAR_GP_PIN(0, 31));
+SCIF_PFC_DAT(scif3_data_c,      TX3_C,                  RX3_C);
+SCIF_PFC_PIN(scif3_data_d,      RCAR_GP_PIN(3, 30),     RCAR_GP_PIN(3, 29));
+SCIF_PFC_DAT(scif3_data_d,      TX3_D,                  RX3_D);
+
+/* - SCIF4 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif4_data_a,      RCAR_GP_PIN(2, 5),      RCAR_GP_PIN(2, 4));
+SCIF_PFC_DAT(scif4_data_a,      TX4_A,                  RX4_A);
+SCIF_PFC_PIN(scif4_data_b,      RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 25));
+SCIF_PFC_DAT(scif4_data_b,      TX4_B,                  RX4_B);
+SCIF_PFC_PIN(scif4_data_c,      RCAR_GP_PIN(3, 0),      RCAR_GP_PIN(2, 31));
+SCIF_PFC_DAT(scif4_data_c,      TX4_C,                  RX4_C);
+
+/* - SCIF5 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif5_data_a,      RCAR_GP_PIN(3, 17),     RCAR_GP_PIN(3, 18));
+SCIF_PFC_DAT(scif5_data_a,      TX5_A,                  RX5_A);
+SCIF_PFC_PIN(scif5_data_b,      RCAR_GP_PIN(1, 15),     RCAR_GP_PIN(1, 14));
+SCIF_PFC_DAT(scif5_data_b,      TX5_B,                  RX5_B);
+
+/* - SDHI macro ------------------------------------------------------------- */
+#define SDHI_PFC_PINS(name, args...)            SH_PFC_PINS(name, args)
+#define SDHI_PFC_DAT1(name, d0)                 SH_PFC_MUX1(name, d0)
+#define SDHI_PFC_DAT4(name, d0, d1, d2, d3)     SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define SDHI_PFC_CTRL(name, clk, cmd)           SH_PFC_MUX2(name, clk, cmd)
+#define SDHI_PFC_CDPN(name, cd)                 SH_PFC_MUX1(name, cd)
+#define SDHI_PFC_WPPN(name, wp)                 SH_PFC_MUX1(name, wp)
+
+/* - SDHI0 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi0_cd,         RCAR_GP_PIN(3, 17));
+SDHI_PFC_CDPN(sdhi0_cd,         SD0_CD);
+SDHI_PFC_PINS(sdhi0_ctrl,       RCAR_GP_PIN(3, 11),     RCAR_GP_PIN(3, 12));
+SDHI_PFC_CTRL(sdhi0_ctrl,       SD0_CLK,                SD0_CMD);
+SDHI_PFC_PINS(sdhi0_data1,      RCAR_GP_PIN(3, 13));
+SDHI_PFC_DAT1(sdhi0_data1,      SD0_DAT0);
+SDHI_PFC_PINS(sdhi0_data4,      RCAR_GP_PIN(3, 13),     RCAR_GP_PIN(3, 14),
+                                RCAR_GP_PIN(3, 15),     RCAR_GP_PIN(3, 16));
+SDHI_PFC_DAT4(sdhi0_data4,      SD0_DAT0,               SD0_DAT1,
+                                SD0_DAT2,               SD0_DAT3);
+SDHI_PFC_PINS(sdhi0_wp,         RCAR_GP_PIN(3, 18));
+SDHI_PFC_WPPN(sdhi0_wp,         SD0_WP);
+
+/* - SDHI1 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi1_cd_a,       RCAR_GP_PIN(0, 30));
+SDHI_PFC_CDPN(sdhi1_cd_a,       SD1_CD_A);
+SDHI_PFC_PINS(sdhi1_cd_b,       RCAR_GP_PIN(2, 24));
+SDHI_PFC_CDPN(sdhi1_cd_b,       SD1_CD_B);
+SDHI_PFC_PINS(sdhi1_ctrl_a,     RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
+SDHI_PFC_CTRL(sdhi1_ctrl_a,     SD1_CLK_A,              SD1_CMD_A);
+SDHI_PFC_PINS(sdhi1_ctrl_b,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 16));
+SDHI_PFC_CTRL(sdhi1_ctrl_b,     SD1_CLK_B,              SD1_CMD_B);
+SDHI_PFC_PINS(sdhi1_data1_a,    RCAR_GP_PIN(1, 7));
+SDHI_PFC_DAT1(sdhi1_data1_a,    SD1_DAT0_A);
+SDHI_PFC_PINS(sdhi1_data1_b,    RCAR_GP_PIN(1, 18));
+SDHI_PFC_DAT1(sdhi1_data1_b,    SD1_DAT0_B);
+SDHI_PFC_PINS(sdhi1_data4_a,    RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
+SDHI_PFC_DAT4(sdhi1_data4_a,    SD1_DAT0_A,             SD1_DAT1_A,
+                                SD1_DAT2_A,             SD1_DAT3_A);
+SDHI_PFC_PINS(sdhi1_data4_b,    RCAR_GP_PIN(1, 18),     RCAR_GP_PIN(1, 19),
+                                RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SDHI_PFC_DAT4(sdhi1_data4_b,    SD1_DAT0_B,             SD1_DAT1_B,
+                                SD1_DAT2_B,             SD1_DAT3_B);
+SDHI_PFC_PINS(sdhi1_wp_a,       RCAR_GP_PIN(0, 31));
+SDHI_PFC_WPPN(sdhi1_wp_a,       SD1_WP_A);
+SDHI_PFC_PINS(sdhi1_wp_b,       RCAR_GP_PIN(2, 25));
+SDHI_PFC_WPPN(sdhi1_wp_b,       SD1_WP_B);
+
+/* - SDH2 ------------------------------------------------------------------- */
+SDHI_PFC_PINS(sdhi2_cd_a,       RCAR_GP_PIN(4, 23));
+SDHI_PFC_CDPN(sdhi2_cd_a,       SD2_CD_A);
+SDHI_PFC_PINS(sdhi2_cd_b,       RCAR_GP_PIN(3, 27));
+SDHI_PFC_CDPN(sdhi2_cd_b,       SD2_CD_B);
+SDHI_PFC_PINS(sdhi2_ctrl_a,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
+SDHI_PFC_CTRL(sdhi2_ctrl_a,     SD2_CLK_A,              SD2_CMD_A);
+SDHI_PFC_PINS(sdhi2_ctrl_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
+SDHI_PFC_CTRL(sdhi2_ctrl_b,     SD2_CLK_B,              SD2_CMD_B);
+SDHI_PFC_PINS(sdhi2_data1_a,    RCAR_GP_PIN(4, 19));
+SDHI_PFC_DAT1(sdhi2_data1_a,    SD2_DAT0_A);
+SDHI_PFC_PINS(sdhi2_data1_b,    RCAR_GP_PIN(4, 7));
+SDHI_PFC_DAT1(sdhi2_data1_b,    SD2_DAT0_B);
+SDHI_PFC_PINS(sdhi2_data4_a,    RCAR_GP_PIN(4, 19),     RCAR_GP_PIN(4, 20),
+                                RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22));
+SDHI_PFC_DAT4(sdhi2_data4_a,    SD2_DAT0_A,             SD2_DAT1_A,
+                                SD2_DAT2_A,             SD2_DAT3_A);
+SDHI_PFC_PINS(sdhi2_data4_b,    RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8),
+                                RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26));
+SDHI_PFC_DAT4(sdhi2_data4_b,    SD2_DAT0_B,             SD2_DAT1_B,
+                                SD2_DAT2_B,             SD2_DAT3_B);
+SDHI_PFC_PINS(sdhi2_wp_a,       RCAR_GP_PIN(4, 24));
+SDHI_PFC_WPPN(sdhi2_wp_a,       SD2_WP_A);
+SDHI_PFC_PINS(sdhi2_wp_b,       RCAR_GP_PIN(3, 28));
+SDHI_PFC_WPPN(sdhi2_wp_b,       SD2_WP_B);
+
+/* - USB0 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb0,               RCAR_GP_PIN(0, 1));
+SH_PFC_MUX1(usb0,               PENC0);
+SH_PFC_PINS(usb0_ovc,           RCAR_GP_PIN(0, 3));
+SH_PFC_MUX1(usb0_ovc,           USB_OVC0);
+
+/* - USB1 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb1,               RCAR_GP_PIN(0, 2));
+SH_PFC_MUX1(usb1,               PENC1);
+SH_PFC_PINS(usb1_ovc,           RCAR_GP_PIN(0, 4));
+SH_PFC_MUX1(usb1_ovc,           USB_OVC1);
+
+/* - VIN macros ------------------------------------------------------------- */
+#define VIN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
+#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
+        SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+#define VIN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
+#define VIN_PFC_SYNC(name, hsync, vsync)        SH_PFC_MUX2(name, hsync, vsync)
+
+/* - VIN0 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin0_data8,        RCAR_GP_PIN(3, 29),     RCAR_GP_PIN(3, 30),
+                                RCAR_GP_PIN(3, 31),     RCAR_GP_PIN(4, 0),
+                                RCAR_GP_PIN(4, 1),      RCAR_GP_PIN(4, 2),
+                                RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
+VIN_PFC_DAT8(vin0_data8,        VI0_DATA0_VI0_B0,       VI0_DATA1_VI0_B1,
+                                VI0_DATA2_VI0_B2,       VI0_DATA3_VI0_B3,
+                                VI0_DATA4_VI0_B4,       VI0_DATA5_VI0_B5,
+                                VI0_DATA6_VI0_G0,       VI0_DATA7_VI0_G1);
+VIN_PFC_PINS(vin0_clk,          RCAR_GP_PIN(3, 24));
+VIN_PFC_CLK(vin0_clk,           VI0_CLK);
+VIN_PFC_PINS(vin0_sync,         RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28));
+VIN_PFC_SYNC(vin0_sync,         VI0_HSYNC,              VI0_VSYNC);
+/* - VIN1 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin1_data8,        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26),
+                                RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28),
+                                RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6),
+                                RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8));
+VIN_PFC_DAT8(vin1_data8,        VI1_DATA0,              VI1_DATA1,
+                                VI1_DATA2,              VI1_DATA3,
+                                VI1_DATA4,              VI1_DATA5,
+                                VI1_DATA6,              VI1_DATA7);
+VIN_PFC_PINS(vin1_clk,          RCAR_GP_PIN(4, 9));
+VIN_PFC_CLK(vin1_clk,           VI1_CLK);
+VIN_PFC_PINS(vin1_sync,         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
+VIN_PFC_SYNC(vin1_sync,         VI1_HSYNC,              VI1_VSYNC);
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(ether_rmii),
+        SH_PFC_PIN_GROUP(ether_link),
+        SH_PFC_PIN_GROUP(ether_magic),
+        SH_PFC_PIN_GROUP(hscif0_data_a),
+        SH_PFC_PIN_GROUP(hscif0_data_b),
+        SH_PFC_PIN_GROUP(hscif0_ctrl_a),
+        SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+        SH_PFC_PIN_GROUP(hscif0_clk),
+        SH_PFC_PIN_GROUP(hscif1_data_a),
+        SH_PFC_PIN_GROUP(hscif1_data_b),
+        SH_PFC_PIN_GROUP(hscif1_ctrl_a),
+        SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+        SH_PFC_PIN_GROUP(hscif1_clk_a),
+        SH_PFC_PIN_GROUP(hscif1_clk_b),
+        SH_PFC_PIN_GROUP(hspi0_a),
+        SH_PFC_PIN_GROUP(hspi0_b),
+        SH_PFC_PIN_GROUP(hspi1_a),
+        SH_PFC_PIN_GROUP(hspi1_b),
+        SH_PFC_PIN_GROUP(hspi2_a),
+        SH_PFC_PIN_GROUP(hspi2_b),
+        SH_PFC_PIN_GROUP(i2c1_a),
+        SH_PFC_PIN_GROUP(i2c1_b),
+        SH_PFC_PIN_GROUP(i2c2_a),
+        SH_PFC_PIN_GROUP(i2c2_b),
+        SH_PFC_PIN_GROUP(i2c2_c),
+        SH_PFC_PIN_GROUP(i2c3_a),
+        SH_PFC_PIN_GROUP(i2c3_b),
+        SH_PFC_PIN_GROUP(i2c3_c),
+        SH_PFC_PIN_GROUP(mmc_ctrl),
+        SH_PFC_PIN_GROUP(mmc_data1),
+        SH_PFC_PIN_GROUP(mmc_data4),
+        SH_PFC_PIN_GROUP(mmc_data8),
+        SH_PFC_PIN_GROUP(scif_clk),
+        SH_PFC_PIN_GROUP(scif0_data_a),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif0_data_c),
+        SH_PFC_PIN_GROUP(scif0_data_d),
+        SH_PFC_PIN_GROUP(scif0_ctrl),
+        SH_PFC_PIN_GROUP(scif0_clk),
+        SH_PFC_PIN_GROUP(scif1_data_a),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_data_d),
+        SH_PFC_PIN_GROUP(scif1_ctrl_a),
+        SH_PFC_PIN_GROUP(scif1_ctrl_c),
+        SH_PFC_PIN_GROUP(scif1_clk_a),
+        SH_PFC_PIN_GROUP(scif1_clk_c),
+        SH_PFC_PIN_GROUP(scif2_data_a),
+        SH_PFC_PIN_GROUP(scif2_data_b),
+        SH_PFC_PIN_GROUP(scif2_data_c),
+        SH_PFC_PIN_GROUP(scif2_data_d),
+        SH_PFC_PIN_GROUP(scif2_data_e),
+        SH_PFC_PIN_GROUP(scif2_clk_a),
+        SH_PFC_PIN_GROUP(scif2_clk_b),
+        SH_PFC_PIN_GROUP(scif2_clk_c),
+        SH_PFC_PIN_GROUP(scif3_data_a),
+        SH_PFC_PIN_GROUP(scif3_data_b),
+        SH_PFC_PIN_GROUP(scif3_data_c),
+        SH_PFC_PIN_GROUP(scif3_data_d),
+        SH_PFC_PIN_GROUP(scif4_data_a),
+        SH_PFC_PIN_GROUP(scif4_data_b),
+        SH_PFC_PIN_GROUP(scif4_data_c),
+        SH_PFC_PIN_GROUP(scif5_data_a),
+        SH_PFC_PIN_GROUP(scif5_data_b),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_cd_a),
+        SH_PFC_PIN_GROUP(sdhi1_cd_b),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
+        SH_PFC_PIN_GROUP(sdhi1_data1_a),
+        SH_PFC_PIN_GROUP(sdhi1_data1_b),
+        SH_PFC_PIN_GROUP(sdhi1_data4_a),
+        SH_PFC_PIN_GROUP(sdhi1_data4_b),
+        SH_PFC_PIN_GROUP(sdhi1_wp_a),
+        SH_PFC_PIN_GROUP(sdhi1_wp_b),
+        SH_PFC_PIN_GROUP(sdhi2_cd_a),
+        SH_PFC_PIN_GROUP(sdhi2_cd_b),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
+        SH_PFC_PIN_GROUP(sdhi2_data1_a),
+        SH_PFC_PIN_GROUP(sdhi2_data1_b),
+        SH_PFC_PIN_GROUP(sdhi2_data4_a),
+        SH_PFC_PIN_GROUP(sdhi2_data4_b),
+        SH_PFC_PIN_GROUP(sdhi2_wp_a),
+        SH_PFC_PIN_GROUP(sdhi2_wp_b),
+        SH_PFC_PIN_GROUP(usb0),
+        SH_PFC_PIN_GROUP(usb0_ovc),
+        SH_PFC_PIN_GROUP(usb1),
+        SH_PFC_PIN_GROUP(usb1_ovc),
+        SH_PFC_PIN_GROUP(vin0_data8),
+        SH_PFC_PIN_GROUP(vin0_clk),
+        SH_PFC_PIN_GROUP(vin0_sync),
+        SH_PFC_PIN_GROUP(vin1_data8),
+        SH_PFC_PIN_GROUP(vin1_clk),
+        SH_PFC_PIN_GROUP(vin1_sync),
+};
+
+static const char * const ether_groups[] = {
+        "ether_rmii",
+        "ether_link",
+        "ether_magic",
+};
+
+static const char * const hscif0_groups[] = {
+        "hscif0_data_a",
+        "hscif0_data_b",
+        "hscif0_ctrl_a",
+        "hscif0_ctrl_b",
+        "hscif0_clk",
+};
+
+static const char * const hscif1_groups[] = {
+        "hscif1_data_a",
+        "hscif1_data_b",
+        "hscif1_ctrl_a",
+        "hscif1_ctrl_b",
+        "hscif1_clk_a",
+        "hscif1_clk_b",
+};
+
+static const char * const hspi0_groups[] = {
+        "hspi0_a",
+        "hspi0_b",
+};
+
+static const char * const hspi1_groups[] = {
+        "hspi1_a",
+        "hspi1_b",
+};
+
+static const char * const hspi2_groups[] = {
+        "hspi2_a",
+        "hspi2_b",
+};
+
+static const char * const i2c1_groups[] = {
+        "i2c1_a",
+        "i2c1_b",
+};
+
+static const char * const i2c2_groups[] = {
+        "i2c2_a",
+        "i2c2_b",
+        "i2c2_c",
+};
+
+static const char * const i2c3_groups[] = {
+        "i2c3_a",
+        "i2c3_b",
+        "i2c3_c",
+};
+
+static const char * const mmc_groups[] = {
+        "mmc_ctrl",
+        "mmc_data1",
+        "mmc_data4",
+        "mmc_data8",
+};
+
+static const char * const scif_clk_groups[] = {
+        "scif_clk",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data_a",
+        "scif0_data_b",
+        "scif0_data_c",
+        "scif0_data_d",
+        "scif0_ctrl",
+        "scif0_clk",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data_a",
+        "scif1_data_b",
+        "scif1_data_c",
+        "scif1_data_d",
+        "scif1_ctrl_a",
+        "scif1_ctrl_c",
+        "scif1_clk_a",
+        "scif1_clk_c",
+};
+
+static const char * const scif2_groups[] = {
+        "scif2_data_a",
+        "scif2_data_b",
+        "scif2_data_c",
+        "scif2_data_d",
+        "scif2_data_e",
+        "scif2_clk_a",
+        "scif2_clk_b",
+        "scif2_clk_c",
+};
+
+static const char * const scif3_groups[] = {
+        "scif3_data_a",
+        "scif3_data_b",
+        "scif3_data_c",
+        "scif3_data_d",
+};
+
+static const char * const scif4_groups[] = {
+        "scif4_data_a",
+        "scif4_data_b",
+        "scif4_data_c",
+};
+
+static const char * const scif5_groups[] = {
+        "scif5_data_a",
+        "scif5_data_b",
+};
+
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_cd",
+        "sdhi0_ctrl",
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_cd_a",
+        "sdhi1_cd_b",
+        "sdhi1_ctrl_a",
+        "sdhi1_ctrl_b",
+        "sdhi1_data1_a",
+        "sdhi1_data1_b",
+        "sdhi1_data4_a",
+        "sdhi1_data4_b",
+        "sdhi1_wp_a",
+        "sdhi1_wp_b",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_cd_a",
+        "sdhi2_cd_b",
+        "sdhi2_ctrl_a",
+        "sdhi2_ctrl_b",
+        "sdhi2_data1_a",
+        "sdhi2_data1_b",
+        "sdhi2_data4_a",
+        "sdhi2_data4_b",
+        "sdhi2_wp_a",
+        "sdhi2_wp_b",
+};
+
+static const char * const usb0_groups[] = {
+        "usb0",
+        "usb0_ovc",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1",
+        "usb1_ovc",
+};
+
+static const char * const vin0_groups[] = {
+        "vin0_data8",
+        "vin0_clk",
+        "vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+        "vin1_data8",
+        "vin1_clk",
+        "vin1_sync",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(ether),
+        SH_PFC_FUNCTION(hscif0),
+        SH_PFC_FUNCTION(hscif1),
+        SH_PFC_FUNCTION(hspi0),
+        SH_PFC_FUNCTION(hspi1),
+        SH_PFC_FUNCTION(hspi2),
+        SH_PFC_FUNCTION(i2c1),
+        SH_PFC_FUNCTION(i2c2),
+        SH_PFC_FUNCTION(i2c3),
+        SH_PFC_FUNCTION(mmc),
+        SH_PFC_FUNCTION(scif_clk),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scif2),
+        SH_PFC_FUNCTION(scif3),
+        SH_PFC_FUNCTION(scif4),
+        SH_PFC_FUNCTION(scif5),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
+        SH_PFC_FUNCTION(vin0),
+        SH_PFC_FUNCTION(vin1),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
+                GP_0_31_FN,     FN_IP1_14_11,
+                GP_0_30_FN,     FN_IP1_10_8,
+                GP_0_29_FN,     FN_IP1_7_5,
+                GP_0_28_FN,     FN_IP1_4_2,
+                GP_0_27_FN,     FN_IP1_1,
+                GP_0_26_FN,     FN_IP1_0,
+                GP_0_25_FN,     FN_IP0_30,
+                GP_0_24_FN,     FN_IP0_29,
+                GP_0_23_FN,     FN_IP0_28,
+                GP_0_22_FN,     FN_IP0_27,
+                GP_0_21_FN,     FN_IP0_26,
+                GP_0_20_FN,     FN_IP0_25,
+                GP_0_19_FN,     FN_IP0_24,
+                GP_0_18_FN,     FN_IP0_23,
+                GP_0_17_FN,     FN_IP0_22,
+                GP_0_16_FN,     FN_IP0_21,
+                GP_0_15_FN,     FN_IP0_20,
+                GP_0_14_FN,     FN_IP0_19,
+                GP_0_13_FN,     FN_IP0_18,
+                GP_0_12_FN,     FN_IP0_17,
+                GP_0_11_FN,     FN_IP0_16,
+                GP_0_10_FN,     FN_IP0_15,
+                GP_0_9_FN,      FN_A3,
+                GP_0_8_FN,      FN_A2,
+                GP_0_7_FN,      FN_A1,
+                GP_0_6_FN,      FN_IP0_14_12,
+                GP_0_5_FN,      FN_IP0_11_8,
+                GP_0_4_FN,      FN_IP0_7_5,
+                GP_0_3_FN,      FN_IP0_4_2,
+                GP_0_2_FN,      FN_PENC1,
+                GP_0_1_FN,      FN_PENC0,
+                GP_0_0_FN,      FN_IP0_1_0 }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
+                GP_1_31_FN,     FN_IP4_6_4,
+                GP_1_30_FN,     FN_IP4_3_1,
+                GP_1_29_FN,     FN_IP4_0,
+                GP_1_28_FN,     FN_IP3_31,
+                GP_1_27_FN,     FN_IP3_30,
+                GP_1_26_FN,     FN_IP3_29,
+                GP_1_25_FN,     FN_IP3_28,
+                GP_1_24_FN,     FN_IP3_27,
+                GP_1_23_FN,     FN_IP3_26_24,
+                GP_1_22_FN,     FN_IP3_23_21,
+                GP_1_21_FN,     FN_IP3_20_19,
+                GP_1_20_FN,     FN_IP3_18_16,
+                GP_1_19_FN,     FN_IP3_15_13,
+                GP_1_18_FN,     FN_IP3_12_10,
+                GP_1_17_FN,     FN_IP3_9_8,
+                GP_1_16_FN,     FN_IP3_7_5,
+                GP_1_15_FN,     FN_IP3_4_2,
+                GP_1_14_FN,     FN_IP3_1_0,
+                GP_1_13_FN,     FN_IP2_31,
+                GP_1_12_FN,     FN_IP2_30,
+                GP_1_11_FN,     FN_IP2_17,
+                GP_1_10_FN,     FN_IP2_16_14,
+                GP_1_9_FN,      FN_IP2_13_12,
+                GP_1_8_FN,      FN_IP2_11_9,
+                GP_1_7_FN,      FN_IP2_8_6,
+                GP_1_6_FN,      FN_IP2_5_3,
+                GP_1_5_FN,      FN_IP2_2_0,
+                GP_1_4_FN,      FN_IP1_29_28,
+                GP_1_3_FN,      FN_IP1_27_25,
+                GP_1_2_FN,      FN_IP1_24,
+                GP_1_1_FN,      FN_WE0,
+                GP_1_0_FN,      FN_IP1_23_21 }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
+                GP_2_31_FN,     FN_IP6_7,
+                GP_2_30_FN,     FN_IP6_6_5,
+                GP_2_29_FN,     FN_IP6_4_2,
+                GP_2_28_FN,     FN_IP6_1_0,
+                GP_2_27_FN,     FN_IP5_30_29,
+                GP_2_26_FN,     FN_IP5_28_26,
+                GP_2_25_FN,     FN_IP5_25_23,
+                GP_2_24_FN,     FN_IP5_22_21,
+                GP_2_23_FN,     FN_AUDIO_CLKB,
+                GP_2_22_FN,     FN_AUDIO_CLKA,
+                GP_2_21_FN,     FN_IP5_20_18,
+                GP_2_20_FN,     FN_IP5_17_15,
+                GP_2_19_FN,     FN_IP5_14_13,
+                GP_2_18_FN,     FN_IP5_12,
+                GP_2_17_FN,     FN_IP5_11_10,
+                GP_2_16_FN,     FN_IP5_9_8,
+                GP_2_15_FN,     FN_IP5_7,
+                GP_2_14_FN,     FN_IP5_6,
+                GP_2_13_FN,     FN_IP5_5_4,
+                GP_2_12_FN,     FN_IP5_3_2,
+                GP_2_11_FN,     FN_IP5_1_0,
+                GP_2_10_FN,     FN_IP4_30_29,
+                GP_2_9_FN,      FN_IP4_28_27,
+                GP_2_8_FN,      FN_IP4_26_25,
+                GP_2_7_FN,      FN_IP4_24_21,
+                GP_2_6_FN,      FN_IP4_20_17,
+                GP_2_5_FN,      FN_IP4_16_15,
+                GP_2_4_FN,      FN_IP4_14_13,
+                GP_2_3_FN,      FN_IP4_12_11,
+                GP_2_2_FN,      FN_IP4_10_9,
+                GP_2_1_FN,      FN_IP4_8,
+                GP_2_0_FN,      FN_IP4_7 }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
+                GP_3_31_FN,     FN_IP8_10_9,
+                GP_3_30_FN,     FN_IP8_8_6,
+                GP_3_29_FN,     FN_IP8_5_3,
+                GP_3_28_FN,     FN_IP8_2_0,
+                GP_3_27_FN,     FN_IP7_31_29,
+                GP_3_26_FN,     FN_IP7_28_25,
+                GP_3_25_FN,     FN_IP7_24_22,
+                GP_3_24_FN,     FN_IP7_21,
+                GP_3_23_FN,     FN_IP7_20_18,
+                GP_3_22_FN,     FN_IP7_17_15,
+                GP_3_21_FN,     FN_IP7_14_12,
+                GP_3_20_FN,     FN_IP7_11_9,
+                GP_3_19_FN,     FN_IP7_8_6,
+                GP_3_18_FN,     FN_IP7_5_4,
+                GP_3_17_FN,     FN_IP7_3_2,
+                GP_3_16_FN,     FN_IP7_1_0,
+                GP_3_15_FN,     FN_IP6_31_30,
+                GP_3_14_FN,     FN_IP6_29_28,
+                GP_3_13_FN,     FN_IP6_27_26,
+                GP_3_12_FN,     FN_IP6_25_24,
+                GP_3_11_FN,     FN_IP6_23_22,
+                GP_3_10_FN,     FN_IP6_21,
+                GP_3_9_FN,      FN_IP6_20_19,
+                GP_3_8_FN,      FN_IP6_18_17,
+                GP_3_7_FN,      FN_IP6_16,
+                GP_3_6_FN,      FN_IP6_15_14,
+                GP_3_5_FN,      FN_IP6_13,
+                GP_3_4_FN,      FN_IP6_12_11,
+                GP_3_3_FN,      FN_IP6_10,
+                GP_3_2_FN,      FN_SSI_SCK34,
+                GP_3_1_FN,      FN_IP6_9,
+                GP_3_0_FN,      FN_IP6_8 }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_4_26_FN,     FN_AVS2,
+                GP_4_25_FN,     FN_AVS1,
+                GP_4_24_FN,     FN_IP10_24_22,
+                GP_4_23_FN,     FN_IP10_21_19,
+                GP_4_22_FN,     FN_IP10_18_16,
+                GP_4_21_FN,     FN_IP10_15_13,
+                GP_4_20_FN,     FN_IP10_12_9,
+                GP_4_19_FN,     FN_IP10_8_6,
+                GP_4_18_FN,     FN_IP10_5_3,
+                GP_4_17_FN,     FN_IP10_2_0,
+                GP_4_16_FN,     FN_IP9_29_27,
+                GP_4_15_FN,     FN_IP9_26_24,
+                GP_4_14_FN,     FN_IP9_23_21,
+                GP_4_13_FN,     FN_IP9_20_18,
+                GP_4_12_FN,     FN_IP9_17_15,
+                GP_4_11_FN,     FN_IP9_14_12,
+                GP_4_10_FN,     FN_IP9_11_9,
+                GP_4_9_FN,      FN_IP9_8_6,
+                GP_4_8_FN,      FN_IP9_5_3,
+                GP_4_7_FN,      FN_IP9_2_0,
+                GP_4_6_FN,      FN_IP8_29_27,
+                GP_4_5_FN,      FN_IP8_26_24,
+                GP_4_4_FN,      FN_IP8_23_22,
+                GP_4_3_FN,      FN_IP8_21_19,
+                GP_4_2_FN,      FN_IP8_18_16,
+                GP_4_1_FN,      FN_IP8_15_14,
+                GP_4_0_FN,      FN_IP8_13_11 }
+        },
+
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
+                             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
+                /* IP0_31 [1] */
+                0,      0,
+                /* IP0_30 [1] */
+                FN_A19, 0,
+                /* IP0_29 [1] */
+                FN_A18, 0,
+                /* IP0_28 [1] */
+                FN_A17, 0,
+                /* IP0_27 [1] */
+                FN_A16, 0,
+                /* IP0_26 [1] */
+                FN_A15, 0,
+                /* IP0_25 [1] */
+                FN_A14, 0,
+                /* IP0_24 [1] */
+                FN_A13, 0,
+                /* IP0_23 [1] */
+                FN_A12, 0,
+                /* IP0_22 [1] */
+                FN_A11, 0,
+                /* IP0_21 [1] */
+                FN_A10, 0,
+                /* IP0_20 [1] */
+                FN_A9,  0,
+                /* IP0_19 [1] */
+                FN_A8,  0,
+                /* IP0_18 [1] */
+                FN_A7,  0,
+                /* IP0_17 [1] */
+                FN_A6,  0,
+                /* IP0_16 [1] */
+                FN_A5,  0,
+                /* IP0_15 [1] */
+                FN_A4,  0,
+                /* IP0_14_12 [3] */
+                FN_SD1_DAT3_A,  FN_MMC_D3,      0,              FN_A0,
+                FN_ATAG0_A,     0,              FN_REMOCON_B,   0,
+                /* IP0_11_8 [4] */
+                FN_SD1_DAT2_A,  FN_MMC_D2,      0,              FN_BS,
+                FN_ATADIR0_A,   0,              FN_SDSELF_B,    0,
+                FN_PWM4_B,      0,              0,              0,
+                0,              0,              0,              0,
+                /* IP0_7_5 [3] */
+                FN_AUDATA1,     FN_ARM_TRACEDATA_1,     FN_GPSIN_C,     FN_USB_OVC1,
+                FN_RX2_E,       FN_SCL2_B,              0,              0,
+                /* IP0_4_2 [3] */
+                FN_AUDATA0,     FN_ARM_TRACEDATA_0,     FN_GPSCLK_C,    FN_USB_OVC0,
+                FN_TX2_E,       FN_SDA2_B,              0,              0,
+                /* IP0_1_0 [2] */
+                FN_PRESETOUT,   0,      FN_PWM1,        0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
+                             1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
+                /* IP1_31 [1] */
+                0,      0,
+                /* IP1_30 [1] */
+                0,      0,
+                /* IP1_29_28 [2] */
+                FN_EX_CS1,      FN_MMC_D4,      0,      0,
+                /* IP1_27_25 [3] */
+                FN_SSI_WS1_B,   FN_EX_CS0,      FN_SCL2_A,      FN_TX3_C,
+                FN_TS_SCK0_A,   0,              0,              0,
+                /* IP1_24 [1] */
+                FN_WE1,         FN_ATAWR0_B,
+                /* IP1_23_21 [3] */
+                FN_MMC_D5,      FN_ATADIR0_B,   0,              FN_RD_WR,
+                0,              0,              0,              0,
+                /* IP1_20_18 [3] */
+                FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
+                FN_SCK2_B,      0,              0,              0,
+                /* IP1_17 [1] */
+                FN_CS0,         FN_HSPI_RX1_B,
+                /* IP1_16_15 [2] */
+                FN_CLKOUT,      FN_HSPI_TX1_B,  FN_PWM0_B,      0,
+                /* IP1_14_11 [4] */
+                FN_SD1_WP_A,    FN_MMC_D7,      0,              FN_A25,
+                FN_DACK1_A,     0,              FN_HCTS0_B,     FN_RX3_C,
+                FN_TS_SDAT0_A,  0,              0,              0,
+                0,              0,              0,              0,
+                /* IP1_10_8 [3] */
+                FN_SD1_CLK_B,   FN_MMC_D6,      0,              FN_A24,
+                FN_DREQ1_A,     0,              FN_HRX0_B,      FN_TS_SPSYNC0_A,
+                /* IP1_7_5 [3] */
+                FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
+                FN_TS_SDEN0_A,  0,              0,              0,
+                /* IP1_4_2 [3] */
+                FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
+                0,              0,              0,              0,
+                /* IP1_1 [1] */
+                FN_A21,         FN_HSPI_CLK1_B,
+                /* IP1_0 [1] */
+                FN_A20,         FN_HSPI_CS1_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
+                             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
+                /* IP2_31 [1] */
+                FN_MLB_CLK,     FN_IRQ1_A,
+                /* IP2_30 [1] */
+                FN_RD_WR_B,     FN_IRQ0,
+                /* IP2_29 [1] */
+                FN_D11,         0,
+                /* IP2_28 [1] */
+                FN_D10,         0,
+                /* IP2_27 [1] */
+                FN_D9,          0,
+                /* IP2_26 [1] */
+                FN_D8,          0,
+                /* IP2_25 [1] */
+                FN_D7,          0,
+                /* IP2_24 [1] */
+                FN_D6,          0,
+                /* IP2_23 [1] */
+                FN_D5,          0,
+                /* IP2_22 [1] */
+                FN_D4,          0,
+                /* IP2_21 [1] */
+                FN_D3,          0,
+                /* IP2_20 [1] */
+                FN_D2,          0,
+                /* IP2_19 [1] */
+                FN_D1,          0,
+                /* IP2_18 [1] */
+                FN_D0,          0,
+                /* IP2_17 [1] */
+                FN_EX_WAIT0,    FN_PWM0_C,
+                /* IP2_16_14 [3] */
+                FN_DACK0,       0,      0,      FN_TX3_A,
+                FN_DRACK0,      0,      0,      0,
+                /* IP2_13_12 [2] */
+                FN_DREQ0_A,     0,      0,      FN_RX3_A,
+                /* IP2_11_9 [3] */
+                FN_SD1_DAT1_A,  FN_MMC_D1,      0,      FN_ATAWR0_A,
+                FN_EX_CS5,      FN_EX_WAIT2_A,  0,      0,
+                /* IP2_8_6 [3] */
+                FN_SD1_DAT0_A,  FN_MMC_D0,      0,      FN_ATARD0,
+                FN_EX_CS4,      FN_EX_WAIT1_A,  0,      0,
+                /* IP2_5_3 [3] */
+                FN_SD1_CMD_A,   FN_MMC_CMD,     0,      FN_ATACS10,
+                FN_EX_CS3,      0,              0,      0,
+                /* IP2_2_0 [3] */
+                FN_SD1_CLK_A,   FN_MMC_CLK,     0,      FN_ATACS00,
+                FN_EX_CS2,      0,              0,      0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
+                             1, 1, 1, 1, 1, 3, 3, 2,
+                             3, 3, 3, 2, 3, 3, 2) {
+                /* IP3_31 [1] */
+                FN_DU0_DR6,     FN_LCDOUT6,
+                /* IP3_30 [1] */
+                FN_DU0_DR5,     FN_LCDOUT5,
+                /* IP3_29 [1] */
+                FN_DU0_DR4,     FN_LCDOUT4,
+                /* IP3_28 [1] */
+                FN_DU0_DR3,     FN_LCDOUT3,
+                /* IP3_27 [1] */
+                FN_DU0_DR2,     FN_LCDOUT2,
+                /* IP3_26_24 [3] */
+                FN_SSI_WS4,             FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,
+                FN_ARM_TRACEDATA_3,     FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
+                /* IP3_23_21 [3] */
+                FN_SSI_SCK4,            FN_DU0_DR0,     FN_LCDOUT0,     FN_AUDATA2,
+                FN_ARM_TRACEDATA_2,     FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,
+                /* IP3_20_19 [2] */
+                FN_SD1_DAT3_B,  FN_HRTS0_A,     FN_RTS0,        0,
+                /* IP3_18_16 [3] */
+                FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        0,
+                0,              0,              0,              0,
+                /* IP3_15_13 [3] */
+                FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
+                0,              0,              0,              0,
+                /* IP3_12_10 [3] */
+                FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,       0,
+                0,              0,              0,              0,
+                /* IP3_9_8 [2] */
+                FN_SD1_CLK_B,   FN_HTX0_A,      FN_TX0_A,       0,
+                /* IP3_7_5 [3] */
+                FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,      FN_CAN_CLK_B,
+                FN_SDA3_B,      0,              0,                      0,
+                /* IP3_4_2 [3] */
+                FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
+                FN_SDSELF_B,    0,              0,              0,
+                /* IP3_1_0 [2] */
+                FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
+                             1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
+                /* IP4_31 [1] */
+                0,      0,
+                /* IP4_30_29 [2] */
+                FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,    0,
+                /* IP4_28_27 [2] */
+                FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,    0,
+                /* IP4_26_25 [2] */
+                FN_VI0_R2_B,    FN_DU0_DB2,     FN_LCDOUT18,    0,
+                /* IP4_24_21 [4] */
+                FN_AUDIO_CLKC,  FN_VI0_R1_B,            FN_DU0_DB1,     FN_LCDOUT17,
+                FN_AUDATA7,     FN_ARM_TRACEDATA_7,     FN_GPSIN_A,     0,
+                FN_ADICS_SAMP,  FN_TS_SCK0_B,           0,              0,
+                0,              0,                      0,              0,
+                /* IP4_20_17 [4] */
+                FN_SSI_SCK2_B,  FN_VI0_R0_B,            FN_DU0_DB0,     FN_LCDOUT16,
+                FN_AUDATA6,     FN_ARM_TRACEDATA_6,     FN_GPSCLK_A,    FN_PWM0_A,
+                FN_ADICLK,      FN_TS_SDAT0_B,          0,              0,
+                0,              0,                      0,              0,
+                /* IP4_16_15 [2] */
+                FN_DU0_DG7,     FN_LCDOUT15,    FN_TX4_A,       0,
+                /* IP4_14_13 [2] */
+                FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       0,
+                /* IP4_12_11 [2] */
+                FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,       0,
+                /* IP4_10_9 [2] */
+                FN_DU0_DG4,     FN_LCDOUT12,    FN_RX0_B,       0,
+                /* IP4_8 [1] */
+                FN_DU0_DG3,     FN_LCDOUT11,
+                /* IP4_7 [1] */
+                FN_DU0_DG2,     FN_LCDOUT10,
+                /* IP4_6_4 [3] */
+                FN_DU0_DG1,     FN_LCDOUT9,     FN_AUDATA5,     FN_ARM_TRACEDATA_5,
+                FN_RX1_D,       FN_CAN0_RX_A,   FN_ADIDATA,     0,
+                /* IP4_3_1 [3] */
+                FN_DU0_DG0,     FN_LCDOUT8,     FN_AUDATA4,     FN_ARM_TRACEDATA_4,
+                FN_TX1_D,       FN_CAN0_TX_A,   FN_ADICHS0,     0,
+                /* IP4_0 [1] */
+                FN_DU0_DR7,     FN_LCDOUT7,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
+                             1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
+
+                /* IP5_31 [1] */
+                0, 0,
+                /* IP5_30_29 [2] */
+                FN_SSI_SDATA7,  FN_HSPI_TX0_B,  FN_RX2_A,       FN_CAN0_RX_B,
+                /* IP5_28_26 [3] */
+                FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,  FN_TX2_A,
+                FN_CAN0_TX_B,   0,              0,              0,
+                /* IP5_25_23 [3] */
+                FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
+                FN_CAN_CLK_D,   0,              0,              0,
+                /* IP5_22_21 [2] */
+                FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
+                /* IP5_20_18 [3] */
+                FN_SSI_WS1_A,           FN_DU0_CDE,     FN_QPOLB,       FN_AUDSYNC,
+                FN_ARM_TRACECTL,        FN_FMIN_D,      0,              0,
+                /* IP5_17_15 [3] */
+                FN_SSI_SCK1_A,          FN_DU0_DISP,    FN_QPOLA,       FN_AUDCK,
+                FN_ARM_TRACECLK,        FN_BPFCLK_D,    0,              0,
+                /* IP5_14_13 [2] */
+                FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,        FN_QCPV_QDE,
+                FN_FMCLK_D,                             0,
+                /* IP5_12 [1] */
+                FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
+                /* IP5_11_10 [2] */
+                FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
+                FN_QSTH_QHS,    0,
+                /* IP5_9_8 [2] */
+                FN_DU0_DOTCLKO_UT1,     FN_QSTVB_QVE,
+                FN_AUDIO_CLKOUT_A,      FN_REMOCON_C,
+                /* IP5_7 [1] */
+                FN_DU0_DOTCLKO_UT0,     FN_QCLK,
+                /* IP5_6 [1] */
+                FN_DU0_DOTCLKIN,        FN_QSTVA_QVS,
+                /* IP5_5_4 [2] */
+                FN_VI1_DATA11_B,        FN_DU0_DB7,     FN_LCDOUT23,    0,
+                /* IP5_3_2 [2] */
+                FN_VI1_DATA10_B,        FN_DU0_DB6,     FN_LCDOUT22,    0,
+                /* IP5_1_0 [2] */
+                FN_VI0_R5_B,            FN_DU0_DB5,     FN_LCDOUT21,    0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
+                             2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
+                             1, 2, 1, 1, 1, 1, 2, 3, 2) {
+                /* IP6_31_30 [2] */
+                FN_SD0_DAT2,    0,      FN_SUB_TDI,     0,
+                /* IP6_29_28 [2] */
+                FN_SD0_DAT1,    0,      FN_SUB_TCK,     0,
+                /* IP6_27_26 [2] */
+                FN_SD0_DAT0,    0,      FN_SUB_TMS,     0,
+                /* IP6_25_24 [2] */
+                FN_SD0_CMD,     0,      FN_SUB_TRST,    0,
+                /* IP6_23_22 [2] */
+                FN_SD0_CLK,     0,      FN_SUB_TDO,     0,
+                /* IP6_21 [1] */
+                FN_SSI_SDATA0,          FN_ARM_TRACEDATA_15,
+                /* IP6_20_19 [2] */
+                FN_SSI_SDATA1,          FN_ARM_TRACEDATA_14,
+                FN_SCL1_A,              FN_SCK2_A,
+                /* IP6_18_17 [2] */
+                FN_SSI_SDATA2,          FN_HSPI_CS2_A,
+                FN_ARM_TRACEDATA_13,    FN_SDA1_A,
+                /* IP6_16 [1] */
+                FN_SSI_WS012,           FN_ARM_TRACEDATA_12,
+                /* IP6_15_14 [2] */
+                FN_SSI_SCK012,          FN_ARM_TRACEDATA_11,
+                FN_TX0_D,               0,
+                /* IP6_13 [1] */
+                FN_SSI_SDATA3,          FN_ARM_TRACEDATA_10,
+                /* IP6_12_11 [2] */
+                FN_SSI_SDATA4,          FN_SSI_WS2_A,
+                FN_ARM_TRACEDATA_9,     0,
+                /* IP6_10 [1] */
+                FN_SSI_WS34,            FN_ARM_TRACEDATA_8,
+                /* IP6_9 [1] */
+                FN_SSI_SDATA5,          FN_RX0_D,
+                /* IP6_8 [1] */
+                FN_SSI_WS5,             FN_TX4_C,
+                /* IP6_7 [1] */
+                FN_SSI_SCK5,            FN_RX4_C,
+                /* IP6_6_5 [2] */
+                FN_SSI_SDATA6,          FN_HSPI_TX2_A,
+                FN_FMIN_B,              0,
+                /* IP6_4_2 [3] */
+                FN_SSI_WS6,             FN_HSPI_CLK2_A,
+                FN_BPFCLK_B,            FN_CAN1_RX_B,
+                0,      0,      0,      0,
+                /* IP6_1_0 [2] */
+                FN_SSI_SCK6,            FN_HSPI_RX2_A,
+                FN_FMCLK_B,             FN_CAN1_TX_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
+                             3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
+
+                /* IP7_31_29 [3] */
+                FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,   FN_DU1_DR2,
+                0,              FN_HSPI_CS1_A,  FN_RX3_B,       0,
+                /* IP7_28_25 [4] */
+                FN_VI0_FIELD,   FN_SD2_DAT3_B,  FN_VI0_R3_C,    FN_VI1_DATA1,
+                FN_DU1_DG7,     0,              FN_HSPI_CLK1_A, FN_TX4_B,
+                0,      0,      0,      0,
+                0,      0,      0,      0,
+                /* IP7_24_22 [3] */
+                FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
+                0,              FN_HSPI_RX1_A,  FN_RX4_B,       0,
+                /* IP7_21 [1] */
+                FN_VI0_CLK,     FN_CAN_CLK_A,
+                /* IP7_20_18 [3] */
+                FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      0,
+                FN_IRQ2_C,      FN_CTS1_C,      FN_SPEEDIN,     0,
+                /* IP7_17_15 [3] */
+                FN_VI1_VSYNC,   FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,
+                0,              FN_TX1_C,       0,              0,
+                /* IP7_14_12 [3] */
+                FN_VI1_HSYNC,   FN_HSPI_RX0_A,  FN_HRTS1_A,     FN_FMCLK_A,
+                0,              FN_RX1_C,       0,              0,
+                /* IP7_11_9 [3] */
+                FN_VI1_FIELD,   FN_HSPI_CS0_A,  FN_HRX1_A,      0,
+                FN_SCK1_C,      0,              0,              0,
+                /* IP7_8_6 [3] */
+                FN_VI1_CLKENB,  FN_HSPI_CLK0_A, FN_HTX1_A,      0,
+                FN_RTS1_C,      0,              0,              0,
+                /* IP7_5_4 [2] */
+                FN_SD0_WP,      0,              FN_RX5_A,       0,
+                /* IP7_3_2 [2] */
+                FN_SD0_CD,      0,              FN_TX5_A,       0,
+                /* IP7_1_0 [2] */
+                FN_SD0_DAT3,    0,              FN_IRQ1_B,      0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
+                             1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
+                /* IP8_31 [1] */
+                0, 0,
+                /* IP8_30 [1] */
+                0, 0,
+                /* IP8_29_27 [3] */
+                FN_VI0_G3,      FN_SD2_CMD_B,   FN_VI1_DATA5,   FN_DU1_DR5,
+                0,              FN_HRX1_B,      0,              0,
+                /* IP8_26_24 [3] */
+                FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,   FN_DU1_DR4,
+                0,              FN_HTX1_B,      0,              0,
+                /* IP8_23_22 [2] */
+                FN_VI0_DATA7_VI0_G1,    FN_DU1_DB5,
+                FN_RTS1_A,              0,
+                /* IP8_21_19 [3] */
+                FN_VI0_DATA6_VI0_G0,    FN_DU1_DB4,
+                FN_CTS1_A,              FN_PWM5,
+                0,      0,      0,      0,
+                /* IP8_18_16 [3] */
+                FN_VI0_DATA5_VI0_B5,    FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,
+                0,                      FN_HSCK1_B,     0,              0,
+                /* IP8_15_14 [2] */
+                FN_VI0_DATA4_VI0_B4,    FN_DU1_DB2,     FN_RX1_A,       0,
+                /* IP8_13_11 [3] */
+                FN_VI0_DATA3_VI0_B3,    FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,
+                0,                       0,             0,              0,
+                /* IP8_10_9 [2] */
+                FN_VI0_DATA2_VI0_B2,    FN_DU1_DG4,     FN_RX0_C,       0,
+                /* IP8_8_6 [3] */
+                FN_VI0_DATA1_VI0_B1,    FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,
+                0,                       0,             0,              0,
+                /* IP8_5_3 [3] */
+                FN_VI0_DATA0_VI0_B0,    FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,
+                0,                       0,             0,              0,
+                /* IP8_2_0 [3] */
+                FN_VI0_VSYNC,           FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
+                0,                      FN_HSPI_TX1_A,  FN_TX3_B,       0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
+                             1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+                /* IP9_31 [1] */
+                0, 0,
+                /* IP9_30 [1] */
+                0, 0,
+                /* IP9_29_27 [3] */
+                FN_VI1_DATA11_A,        FN_DU1_EXHSYNC_DU1_HSYNC,
+                FN_ETH_RXD1,            FN_FMIN_C,
+                0,                      FN_RX2_D,
+                FN_SCL2_C,              0,
+                /* IP9_26_24 [3] */
+                FN_VI1_DATA10_A,        FN_DU1_DOTCLKOUT,
+                FN_ETH_RXD0,            FN_BPFCLK_C,
+                0,                      FN_TX2_D,
+                FN_SDA2_C,              0,
+                /* IP9_23_21 [3] */
+                FN_VI0_R5_A,    0,              FN_ETH_RX_ER,   FN_FMCLK_C,
+                FN_IERX,        FN_RX2_C,       0,              0,
+                /* IP9_20_18 [3] */
+                FN_VI0_R4_A,    FN_ETH_TX_EN,   0,              0,
+                FN_IETX,        FN_TX2_C,       0,              0,
+                /* IP9_17_15 [3] */
+                FN_VI0_R3_A,    FN_ETH_CRS_DV,  0,              FN_IECLK,
+                FN_SCK2_C,      0,              0,              0,
+                /* IP9_14_12 [3] */
+                FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,     FN_ETH_TXD1,
+                0,              FN_PWM3,        0,              0,
+                /* IP9_11_9 [3] */
+                FN_VI0_R1_A,    FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,
+                0,              FN_PWM2,        FN_TCLK1,       0,
+                /* IP9_8_6 [3] */
+                FN_VI0_R0_A,    FN_VI1_CLK,     FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
+                0,              0,              0,              0,
+                /* IP9_5_3 [3] */
+                FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,   FN_DU1_DR7,
+                0,              FN_HCTS1_B,     0,              0,
+                /* IP9_2_0 [3] */
+                FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
+                0,              FN_HRTS1_B,     0,              0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
+                             1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
+
+                /* IP10_31 [1] */
+                0, 0,
+                /* IP10_30 [1] */
+                0, 0,
+                /* IP10_29 [1] */
+                0, 0,
+                /* IP10_28 [1] */
+                0, 0,
+                /* IP10_27 [1] */
+                0, 0,
+                /* IP10_26 [1] */
+                0, 0,
+                /* IP10_25 [1] */
+                0, 0,
+                /* IP10_24_22 [3] */
+                FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,  FN_DACK0_B,
+                FN_HSPI_TX2_B,  FN_CAN_CLK_C,   0,              0,
+                /* IP10_21_19 [3] */
+                FN_SD2_CD_A,    FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,
+                FN_HSPI_RX2_B,  FN_REMOCON_A,   0,              0,
+                /* IP10_18_16 [3] */
+                FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,     FN_ATAG1,
+                FN_HSPI_CS2_B,  FN_GPSIN_B,     0,              0,
+                /* IP10_15_13 [3] */
+                FN_SD2_DAT2_A,  FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,
+                FN_HSPI_CLK2_B, FN_GPSCLK_B,    0,              0,
+                /* IP10_12_9 [4] */
+                FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
+                FN_ETH_MAGIC,   FN_CAN1_TX_A,   0,              FN_PWM6,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                /* IP10_8_6 [3] */
+                FN_SD2_DAT0_A,  FN_DU1_DISP,    FN_ATACS01,     FN_DREQ1_B,
+                FN_ETH_LINK,    FN_CAN1_RX_A,   0,              0,
+                /* IP10_5_3 [3] */
+                FN_SD2_CMD_A,   FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+                FN_ATAWR1,      FN_ETH_MDIO,
+                FN_SCL1_B,      0,
+                0,              0,
+                /* IP10_2_0 [3] */
+                FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,
+                FN_ATARD1,      FN_ETH_MDC,
+                FN_SDA1_B,      0,
+                0,              0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
+                             1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
+                             1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+
+                /* SEL 31  [1] */
+                0, 0,
+                /* SEL_30 (SCIF5) [1] */
+                FN_SEL_SCIF5_A,         FN_SEL_SCIF5_B,
+                /* SEL_29_28 (SCIF4) [2] */
+                FN_SEL_SCIF4_A,         FN_SEL_SCIF4_B,
+                FN_SEL_SCIF4_C,         0,
+                /* SEL_27_26 (SCIF3) [2] */
+                FN_SEL_SCIF3_A,         FN_SEL_SCIF3_B,
+                FN_SEL_SCIF3_C,         FN_SEL_SCIF3_D,
+                /* SEL_25_23 (SCIF2) [3] */
+                FN_SEL_SCIF2_A,         FN_SEL_SCIF2_B,
+                FN_SEL_SCIF2_C,         FN_SEL_SCIF2_D,
+                FN_SEL_SCIF2_E,         0,
+                0,                      0,
+                /* SEL_22_21 (SCIF1) [2] */
+                FN_SEL_SCIF1_A,         FN_SEL_SCIF1_B,
+                FN_SEL_SCIF1_C,         FN_SEL_SCIF1_D,
+                /* SEL_20_19 (SCIF0) [2] */
+                FN_SEL_SCIF0_A,         FN_SEL_SCIF0_B,
+                FN_SEL_SCIF0_C,         FN_SEL_SCIF0_D,
+                /* SEL_18 [1] */
+                0, 0,
+                /* SEL_17 (SSI2) [1] */
+                FN_SEL_SSI2_A,          FN_SEL_SSI2_B,
+                /* SEL_16 (SSI1) [1] */
+                FN_SEL_SSI1_A,          FN_SEL_SSI1_B,
+                /* SEL_15 (VI1) [1] */
+                FN_SEL_VI1_A,           FN_SEL_VI1_B,
+                /* SEL_14_13 (VI0) [2] */
+                FN_SEL_VI0_A,           FN_SEL_VI0_B,
+                FN_SEL_VI0_C,           FN_SEL_VI0_D,
+                /* SEL_12 [1] */
+                0, 0,
+                /* SEL_11 (SD2) [1] */
+                FN_SEL_SD2_A,           FN_SEL_SD2_B,
+                /* SEL_10 (SD1) [1] */
+                FN_SEL_SD1_A,           FN_SEL_SD1_B,
+                /* SEL_9 (IRQ3) [1] */
+                FN_SEL_IRQ3_A,          FN_SEL_IRQ3_B,
+                /* SEL_8_7 (IRQ2) [2] */
+                FN_SEL_IRQ2_A,          FN_SEL_IRQ2_B,
+                FN_SEL_IRQ2_C,          0,
+                /* SEL_6 (IRQ1) [1] */
+                FN_SEL_IRQ1_A,          FN_SEL_IRQ1_B,
+                /* SEL_5 [1] */
+                0, 0,
+                /* SEL_4 (DREQ2) [1] */
+                FN_SEL_DREQ2_A,         FN_SEL_DREQ2_B,
+                /* SEL_3 (DREQ1) [1] */
+                FN_SEL_DREQ1_A,         FN_SEL_DREQ1_B,
+                /* SEL_2 (DREQ0) [1] */
+                FN_SEL_DREQ0_A,         FN_SEL_DREQ0_B,
+                /* SEL_1 (WAIT2) [1] */
+                FN_SEL_WAIT2_A,         FN_SEL_WAIT2_B,
+                /* SEL_0 (WAIT1) [1] */
+                FN_SEL_WAIT1_A,         FN_SEL_WAIT1_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
+                             1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
+
+                /* SEL_31 [1] */
+                0, 0,
+                /* SEL_30 [1] */
+                0, 0,
+                /* SEL_29 [1] */
+                0, 0,
+                /* SEL_28 [1] */
+                0, 0,
+                /* SEL_27 (CAN1) [1] */
+                FN_SEL_CAN1_A,          FN_SEL_CAN1_B,
+                /* SEL_26 (CAN0) [1] */
+                FN_SEL_CAN0_A,          FN_SEL_CAN0_B,
+                /* SEL_25_24 (CANCLK) [2] */
+                FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
+                FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
+                /* SEL_23 (HSCIF1) [1] */
+                FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
+                /* SEL_22 (HSCIF0) [1] */
+                FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
+                /* SEL_21 [1] */
+                0, 0,
+                /* SEL_20 [1] */
+                0, 0,
+                /* SEL_19 [1] */
+                0, 0,
+                /* SEL_18 [1] */
+                0, 0,
+                /* SEL_17 [1] */
+                0, 0,
+                /* SEL_16 [1] */
+                0, 0,
+                /* SEL_15 [1] */
+                0, 0,
+                /* SEL_14_13 (REMOCON) [2] */
+                FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,
+                FN_SEL_REMOCON_C,       0,
+                /* SEL_12_11 (FM) [2] */
+                FN_SEL_FM_A,            FN_SEL_FM_B,
+                FN_SEL_FM_C,            FN_SEL_FM_D,
+                /* SEL_10_9 (GPS) [2] */
+                FN_SEL_GPS_A,           FN_SEL_GPS_B,
+                FN_SEL_GPS_C,           0,
+                /* SEL_8 (TSIF0) [1] */
+                FN_SEL_TSIF0_A,         FN_SEL_TSIF0_B,
+                /* SEL_7 (HSPI2) [1] */
+                FN_SEL_HSPI2_A,         FN_SEL_HSPI2_B,
+                /* SEL_6 (HSPI1) [1] */
+                FN_SEL_HSPI1_A,         FN_SEL_HSPI1_B,
+                /* SEL_5 (HSPI0) [1] */
+                FN_SEL_HSPI0_A,         FN_SEL_HSPI0_B,
+                /* SEL_4_3 (I2C3) [2] */
+                FN_SEL_I2C3_A,          FN_SEL_I2C3_B,
+                FN_SEL_I2C3_C,          0,
+                /* SEL_2_1 (I2C2) [2] */
+                FN_SEL_I2C2_A,          FN_SEL_I2C2_B,
+                FN_SEL_I2C2_C,          0,
+                /* SEL_0 (I2C1) [1] */
+                FN_SEL_I2C1_A,          FN_SEL_I2C1_B,
+                }
+        },
+        { },
+};
+
+const struct sh_pfc_soc_info r8a7778_pinmux_info = {
+        .name = "r8a7778_pfc",
+
+        .unlock_reg = 0xfffc0000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 8cd90e7e945a..8e22ca6c1044 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1,8 +1,9 @@
 /*
  * r8a7779 processor support - PFC hardware block
  *
- * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011, 2013  Renesas Solutions Corp.
  * Copyright (C) 2011  Magnus Damm
+ * Copyright (C) 2013  Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,6 +20,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
 
 #include "sh_pfc.h"
 
@@ -79,7 +81,7 @@
 #define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
 
 #define _GP_GPIO(bank, pin, _name, sfx)                                 \
-        [(bank * 32) + pin] = {                                         \
+        [RCAR_GP_PIN(bank, pin)] = {                                    \
                 .name = __stringify(_name),                             \
                 .enum_id = _name##_DATA,                                \
         }
@@ -1472,9 +1474,12 @@ static struct sh_pfc_pin pinmux_pins[] = {
 /* - DU0 -------------------------------------------------------------------- */
 static const unsigned int du0_rgb666_pins[] = {
         /* R[7:2], G[7:2], B[7:2] */
-        188, 187, 186, 185, 184, 183,
-        194, 193, 192, 191, 190, 189,
-        200, 199, 198, 197, 196, 195,
+        RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+        RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+        RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
+        RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
+        RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
+        RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
 };
 static const unsigned int du0_rgb666_mux[] = {
         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1486,9 +1491,14 @@ static const unsigned int du0_rgb666_mux[] = {
 };
 static const unsigned int du0_rgb888_pins[] = {
         /* R[7:0], G[7:0], B[7:0] */
-        188, 187, 186, 185, 184, 183, 24, 23,
-        194, 193, 192, 191, 190, 189, 26, 25,
-        200, 199, 198, 197, 196, 195, 28, 27,
+        RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+        RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
+        RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
+        RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
+        RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
+        RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
+        RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
 };
 static const unsigned int du0_rgb888_mux[] = {
         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1500,28 +1510,28 @@ static const unsigned int du0_rgb888_mux[] = {
 };
 static const unsigned int du0_clk_in_pins[] = {
         /* CLKIN */
-        29,
+        RCAR_GP_PIN(0, 29),
 };
 static const unsigned int du0_clk_in_mux[] = {
         DU0_DOTCLKIN_MARK,
 };
 static const unsigned int du0_clk_out_0_pins[] = {
         /* CLKOUT */
-        180,
+        RCAR_GP_PIN(5, 20),
 };
 static const unsigned int du0_clk_out_0_mux[] = {
         DU0_DOTCLKOUT0_MARK,
 };
 static const unsigned int du0_clk_out_1_pins[] = {
         /* CLKOUT */
-        30,
+        RCAR_GP_PIN(0, 30),
 };
 static const unsigned int du0_clk_out_1_mux[] = {
         DU0_DOTCLKOUT1_MARK,
 };
 static const unsigned int du0_sync_0_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        182, 181, 31,
+        RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_sync_0_mux[] = {
         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1529,7 +1539,7 @@ static const unsigned int du0_sync_0_mux[] = {
 };
 static const unsigned int du0_sync_1_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        182, 181, 32,
+        RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
 };
 static const unsigned int du0_sync_1_mux[] = {
         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1537,14 +1547,14 @@ static const unsigned int du0_sync_1_mux[] = {
 };
 static const unsigned int du0_oddf_pins[] = {
         /* ODDF */
-        31,
+        RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_oddf_mux[] = {
         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du0_cde_pins[] = {
         /* CDE */
-        33,
+        RCAR_GP_PIN(1, 1),
 };
 static const unsigned int du0_cde_mux[] = {
         DU0_CDE_MARK
@@ -1552,9 +1562,12 @@ static const unsigned int du0_cde_mux[] = {
 /* - DU1 -------------------------------------------------------------------- */
 static const unsigned int du1_rgb666_pins[] = {
         /* R[7:2], G[7:2], B[7:2] */
-        41, 40, 39, 38, 37, 36,
-        49, 48, 47, 46, 45, 44,
-        57, 56, 55, 54, 53, 52,
+        RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+        RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+        RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
+        RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
+        RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+        RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
 };
 static const unsigned int du1_rgb666_mux[] = {
         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1566,9 +1579,14 @@ static const unsigned int du1_rgb666_mux[] = {
 };
 static const unsigned int du1_rgb888_pins[] = {
         /* R[7:0], G[7:0], B[7:0] */
-        41, 40, 39, 38, 37, 36, 35, 34,
-        49, 48, 47, 46, 45, 44, 43, 32,
-        57, 56, 55, 54, 53, 52, 51, 50,
+        RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+        RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+        RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
+        RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+        RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
+        RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
+        RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+        RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int du1_rgb888_mux[] = {
         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1580,21 +1598,21 @@ static const unsigned int du1_rgb888_mux[] = {
 };
 static const unsigned int du1_clk_in_pins[] = {
         /* CLKIN */
-        58,
+        RCAR_GP_PIN(1, 26),
 };
 static const unsigned int du1_clk_in_mux[] = {
         DU1_DOTCLKIN_MARK,
 };
 static const unsigned int du1_clk_out_pins[] = {
         /* CLKOUT */
-        59,
+        RCAR_GP_PIN(1, 27),
 };
 static const unsigned int du1_clk_out_mux[] = {
         DU1_DOTCLKOUT_MARK,
 };
 static const unsigned int du1_sync_0_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        61, 60, 62,
+        RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_sync_0_mux[] = {
         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1602,7 +1620,7 @@ static const unsigned int du1_sync_0_mux[] = {
 };
 static const unsigned int du1_sync_1_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        61, 60, 63,
+        RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
 };
 static const unsigned int du1_sync_1_mux[] = {
         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1610,22 +1628,55 @@ static const unsigned int du1_sync_1_mux[] = {
 };
 static const unsigned int du1_oddf_pins[] = {
         /* ODDF */
-        62,
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_oddf_mux[] = {
         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du1_cde_pins[] = {
         /* CDE */
-        64,
+        RCAR_GP_PIN(2, 0),
 };
 static const unsigned int du1_cde_mux[] = {
         DU1_CDE_MARK
 };
+/* - Ether ------------------------------------------------------------------ */
+static const unsigned int ether_rmii_pins[] = {
+        /*
+         * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
+         * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
+         * ETH_MDIO, ETH_MDC
+         */
+        RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
+        RCAR_GP_PIN(2, 26),
+        RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
+        RCAR_GP_PIN(2, 19),
+        RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int ether_rmii_mux[] = {
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+        ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+static const unsigned int ether_link_pins[] = {
+        /* ETH_LINK */
+        RCAR_GP_PIN(2, 24),
+};
+static const unsigned int ether_link_mux[] = {
+        ETH_LINK_MARK,
+};
+static const unsigned int ether_magic_pins[] = {
+        /* ETH_MAGIC */
+        RCAR_GP_PIN(2, 25),
+};
+static const unsigned int ether_magic_mux[] = {
+        ETH_MAGIC_MARK,
+};
 /* - HSPI0 ------------------------------------------------------------------ */
 static const unsigned int hspi0_pins[] = {
         /* CLK, CS, RX, TX */
-        150, 151, 153, 152,
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
+        RCAR_GP_PIN(4, 24),
 };
 static const unsigned int hspi0_mux[] = {
         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
@@ -1633,28 +1684,32 @@ static const unsigned int hspi0_mux[] = {
 /* - HSPI1 ------------------------------------------------------------------ */
 static const unsigned int hspi1_pins[] = {
         /* CLK, CS, RX, TX */
-        63, 58, 64, 62,
+        RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int hspi1_mux[] = {
         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
 };
 static const unsigned int hspi1_b_pins[] = {
         /* CLK, CS, RX, TX */
-        90, 91, 93, 92,
+        RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
+        RCAR_GP_PIN(2, 28),
 };
 static const unsigned int hspi1_b_mux[] = {
         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
 };
 static const unsigned int hspi1_c_pins[] = {
         /* CLK, CS, RX, TX */
-        141, 142, 144, 143,
+        RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
+        RCAR_GP_PIN(4, 15),
 };
 static const unsigned int hspi1_c_mux[] = {
         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
 };
 static const unsigned int hspi1_d_pins[] = {
         /* CLK, CS, RX, TX */
-        101, 102, 104, 103,
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
+        RCAR_GP_PIN(3, 7),
 };
 static const unsigned int hspi1_d_mux[] = {
         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
@@ -1662,14 +1717,16 @@ static const unsigned int hspi1_d_mux[] = {
 /* - HSPI2 ------------------------------------------------------------------ */
 static const unsigned int hspi2_pins[] = {
         /* CLK, CS, RX, TX */
-        9, 10, 11, 14,
+        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+        RCAR_GP_PIN(0, 14),
 };
 static const unsigned int hspi2_mux[] = {
         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
 };
 static const unsigned int hspi2_b_pins[] = {
         /* CLK, CS, RX, TX */
-        7, 13, 8, 6,
+        RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
+        RCAR_GP_PIN(0, 6),
 };
 static const unsigned int hspi2_b_mux[] = {
         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
@@ -1677,56 +1734,56 @@ static const unsigned int hspi2_b_mux[] = {
 /* - INTC ------------------------------------------------------------------- */
 static const unsigned int intc_irq0_pins[] = {
         /* IRQ */
-        78,
+        RCAR_GP_PIN(2, 14),
 };
 static const unsigned int intc_irq0_mux[] = {
         IRQ0_MARK,
 };
 static const unsigned int intc_irq0_b_pins[] = {
         /* IRQ */
-        141,
+        RCAR_GP_PIN(4, 13),
 };
 static const unsigned int intc_irq0_b_mux[] = {
         IRQ0_B_MARK,
 };
 static const unsigned int intc_irq1_pins[] = {
         /* IRQ */
-        79,
+        RCAR_GP_PIN(2, 15),
 };
 static const unsigned int intc_irq1_mux[] = {
         IRQ1_MARK,
 };
 static const unsigned int intc_irq1_b_pins[] = {
         /* IRQ */
-        142,
+        RCAR_GP_PIN(4, 14),
 };
 static const unsigned int intc_irq1_b_mux[] = {
         IRQ1_B_MARK,
 };
 static const unsigned int intc_irq2_pins[] = {
         /* IRQ */
-        88,
+        RCAR_GP_PIN(2, 24),
 };
 static const unsigned int intc_irq2_mux[] = {
         IRQ2_MARK,
 };
 static const unsigned int intc_irq2_b_pins[] = {
         /* IRQ */
-        143,
+        RCAR_GP_PIN(4, 15),
 };
 static const unsigned int intc_irq2_b_mux[] = {
         IRQ2_B_MARK,
 };
 static const unsigned int intc_irq3_pins[] = {
         /* IRQ */
-        89,
+        RCAR_GP_PIN(2, 25),
 };
 static const unsigned int intc_irq3_mux[] = {
         IRQ3_MARK,
 };
 static const unsigned int intc_irq3_b_pins[] = {
         /* IRQ */
-        144,
+        RCAR_GP_PIN(4, 16),
 };
 static const unsigned int intc_irq3_b_mux[] = {
         IRQ3_B_MARK,
@@ -1734,56 +1791,56 @@ static const unsigned int intc_irq3_b_mux[] = {
 /* - LSBC ------------------------------------------------------------------- */
 static const unsigned int lbsc_cs0_pins[] = {
         /* CS */
-        13,
+        RCAR_GP_PIN(0, 13),
 };
 static const unsigned int lbsc_cs0_mux[] = {
         CS0_MARK,
 };
 static const unsigned int lbsc_cs1_pins[] = {
         /* CS */
-        14,
+        RCAR_GP_PIN(0, 14),
 };
 static const unsigned int lbsc_cs1_mux[] = {
         CS1_A26_MARK,
 };
 static const unsigned int lbsc_ex_cs0_pins[] = {
         /* CS */
-        15,
+        RCAR_GP_PIN(0, 15),
 };
 static const unsigned int lbsc_ex_cs0_mux[] = {
         EX_CS0_MARK,
 };
 static const unsigned int lbsc_ex_cs1_pins[] = {
         /* CS */
-        16,
+        RCAR_GP_PIN(0, 16),
 };
 static const unsigned int lbsc_ex_cs1_mux[] = {
         EX_CS1_MARK,
 };
 static const unsigned int lbsc_ex_cs2_pins[] = {
         /* CS */
-        17,
+        RCAR_GP_PIN(0, 17),
 };
 static const unsigned int lbsc_ex_cs2_mux[] = {
         EX_CS2_MARK,
 };
 static const unsigned int lbsc_ex_cs3_pins[] = {
         /* CS */
-        18,
+        RCAR_GP_PIN(0, 18),
 };
 static const unsigned int lbsc_ex_cs3_mux[] = {
         EX_CS3_MARK,
 };
 static const unsigned int lbsc_ex_cs4_pins[] = {
         /* CS */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int lbsc_ex_cs4_mux[] = {
         EX_CS4_MARK,
 };
 static const unsigned int lbsc_ex_cs5_pins[] = {
         /* CS */
-        20,
+        RCAR_GP_PIN(0, 20),
 };
 static const unsigned int lbsc_ex_cs5_mux[] = {
         EX_CS5_MARK,
@@ -1791,21 +1848,24 @@ static const unsigned int lbsc_ex_cs5_mux[] = {
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_pins[] = {
         /* D[0] */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int mmc0_data1_mux[] = {
         MMC0_D0_MARK,
 };
 static const unsigned int mmc0_data4_pins[] = {
         /* D[0:3] */
-        19, 20, 21, 2,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),
 };
 static const unsigned int mmc0_data4_mux[] = {
         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
 };
 static const unsigned int mmc0_data8_pins[] = {
         /* D[0:7] */
-        19, 20, 21, 2, 10, 11, 15, 16,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
 };
 static const unsigned int mmc0_data8_mux[] = {
         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
@@ -1813,28 +1873,31 @@ static const unsigned int mmc0_data8_mux[] = {
 };
 static const unsigned int mmc0_ctrl_pins[] = {
         /* CMD, CLK */
-        18, 17,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int mmc0_ctrl_mux[] = {
         MMC0_CMD_MARK, MMC0_CLK_MARK,
 };
 static const unsigned int mmc1_data1_pins[] = {
         /* D[0] */
-        72,
+        RCAR_GP_PIN(2, 8),
 };
 static const unsigned int mmc1_data1_mux[] = {
         MMC1_D0_MARK,
 };
 static const unsigned int mmc1_data4_pins[] = {
         /* D[0:3] */
-        72, 73, 74, 75,
+        RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+        RCAR_GP_PIN(2, 11),
 };
 static const unsigned int mmc1_data4_mux[] = {
         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
 };
 static const unsigned int mmc1_data8_pins[] = {
         /* D[0:7] */
-        72, 73, 74, 75, 76, 77, 80, 81,
+        RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
+        RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+        RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
 };
 static const unsigned int mmc1_data8_mux[] = {
         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
@@ -1842,7 +1905,7 @@ static const unsigned int mmc1_data8_mux[] = {
 };
 static const unsigned int mmc1_ctrl_pins[] = {
         /* CMD, CLK */
-        68, 65,
+        RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
 };
 static const unsigned int mmc1_ctrl_mux[] = {
         MMC1_CMD_MARK, MMC1_CLK_MARK,
@@ -1850,84 +1913,84 @@ static const unsigned int mmc1_ctrl_mux[] = {
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
         /* RXD, TXD */
-        153, 152,
+        RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
 };
 static const unsigned int scif0_data_mux[] = {
         RX0_MARK, TX0_MARK,
 };
 static const unsigned int scif0_clk_pins[] = {
         /* SCK */
-        156,
+        RCAR_GP_PIN(4, 28),
 };
 static const unsigned int scif0_clk_mux[] = {
         SCK0_MARK,
 };
 static const unsigned int scif0_ctrl_pins[] = {
         /* RTS, CTS */
-        151, 150,
+        RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
 };
 static const unsigned int scif0_ctrl_mux[] = {
         RTS0_TANS_MARK, CTS0_MARK,
 };
 static const unsigned int scif0_data_b_pins[] = {
         /* RXD, TXD */
-        20, 19,
+        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif0_data_b_mux[] = {
         RX0_B_MARK, TX0_B_MARK,
 };
 static const unsigned int scif0_clk_b_pins[] = {
         /* SCK */
-        33,
+        RCAR_GP_PIN(1, 1),
 };
 static const unsigned int scif0_clk_b_mux[] = {
         SCK0_B_MARK,
 };
 static const unsigned int scif0_ctrl_b_pins[] = {
         /* RTS, CTS */
-        18, 11,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif0_ctrl_b_mux[] = {
         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
 };
 static const unsigned int scif0_data_c_pins[] = {
         /* RXD, TXD */
-        146, 147,
+        RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
 };
 static const unsigned int scif0_data_c_mux[] = {
         RX0_C_MARK, TX0_C_MARK,
 };
 static const unsigned int scif0_clk_c_pins[] = {
         /* SCK */
-        145,
+        RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif0_clk_c_mux[] = {
         SCK0_C_MARK,
 };
 static const unsigned int scif0_ctrl_c_pins[] = {
         /* RTS, CTS */
-        149, 148,
+        RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif0_ctrl_c_mux[] = {
         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
 };
 static const unsigned int scif0_data_d_pins[] = {
         /* RXD, TXD */
-        43, 42,
+        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif0_data_d_mux[] = {
         RX0_D_MARK, TX0_D_MARK,
 };
 static const unsigned int scif0_clk_d_pins[] = {
         /* SCK */
-        50,
+        RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif0_clk_d_mux[] = {
         SCK0_D_MARK,
 };
 static const unsigned int scif0_ctrl_d_pins[] = {
         /* RTS, CTS */
-        51, 35,
+        RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
 };
 static const unsigned int scif0_ctrl_d_mux[] = {
         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
@@ -1935,63 +1998,63 @@ static const unsigned int scif0_ctrl_d_mux[] = {
 /* - SCIF1 ------------------------------------------------------------------ */
 static const unsigned int scif1_data_pins[] = {
         /* RXD, TXD */
-        149, 148,
+        RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif1_data_mux[] = {
         RX1_MARK, TX1_MARK,
 };
 static const unsigned int scif1_clk_pins[] = {
         /* SCK */
-        145,
+        RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif1_clk_mux[] = {
         SCK1_MARK,
 };
 static const unsigned int scif1_ctrl_pins[] = {
         /* RTS, CTS */
-        147, 146,
+        RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
 };
 static const unsigned int scif1_ctrl_mux[] = {
         RTS1_TANS_MARK, CTS1_MARK,
 };
 static const unsigned int scif1_data_b_pins[] = {
         /* RXD, TXD */
-        117, 114,
+        RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
 };
 static const unsigned int scif1_data_b_mux[] = {
         RX1_B_MARK, TX1_B_MARK,
 };
 static const unsigned int scif1_clk_b_pins[] = {
         /* SCK */
-        113,
+        RCAR_GP_PIN(3, 17),
 };
 static const unsigned int scif1_clk_b_mux[] = {
         SCK1_B_MARK,
 };
 static const unsigned int scif1_ctrl_b_pins[] = {
         /* RTS, CTS */
-        115, 116,
+        RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
 };
 static const unsigned int scif1_ctrl_b_mux[] = {
         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
 };
 static const unsigned int scif1_data_c_pins[] = {
         /* RXD, TXD */
-        67, 66,
+        RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
 };
 static const unsigned int scif1_data_c_mux[] = {
         RX1_C_MARK, TX1_C_MARK,
 };
 static const unsigned int scif1_clk_c_pins[] = {
         /* SCK */
-        86,
+        RCAR_GP_PIN(2, 22),
 };
 static const unsigned int scif1_clk_c_mux[] = {
         SCK1_C_MARK,
 };
 static const unsigned int scif1_ctrl_c_pins[] = {
         /* RTS, CTS */
-        69, 68,
+        RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif1_ctrl_c_mux[] = {
         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
@@ -1999,63 +2062,63 @@ static const unsigned int scif1_ctrl_c_mux[] = {
 /* - SCIF2 ------------------------------------------------------------------ */
 static const unsigned int scif2_data_pins[] = {
         /* RXD, TXD */
-        106, 105,
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
 };
 static const unsigned int scif2_data_mux[] = {
         RX2_MARK, TX2_MARK,
 };
 static const unsigned int scif2_clk_pins[] = {
         /* SCK */
-        107,
+        RCAR_GP_PIN(3, 11),
 };
 static const unsigned int scif2_clk_mux[] = {
         SCK2_MARK,
 };
 static const unsigned int scif2_data_b_pins[] = {
         /* RXD, TXD */
-        120, 119,
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
 };
 static const unsigned int scif2_data_b_mux[] = {
         RX2_B_MARK, TX2_B_MARK,
 };
 static const unsigned int scif2_clk_b_pins[] = {
         /* SCK */
-        118,
+        RCAR_GP_PIN(3, 22),
 };
 static const unsigned int scif2_clk_b_mux[] = {
         SCK2_B_MARK,
 };
 static const unsigned int scif2_data_c_pins[] = {
         /* RXD, TXD */
-        33, 31,
+        RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int scif2_data_c_mux[] = {
         RX2_C_MARK, TX2_C_MARK,
 };
 static const unsigned int scif2_clk_c_pins[] = {
         /* SCK */
-        32,
+        RCAR_GP_PIN(1, 0),
 };
 static const unsigned int scif2_clk_c_mux[] = {
         SCK2_C_MARK,
 };
 static const unsigned int scif2_data_d_pins[] = {
         /* RXD, TXD */
-        64, 62,
+        RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif2_data_d_mux[] = {
         RX2_D_MARK, TX2_D_MARK,
 };
 static const unsigned int scif2_clk_d_pins[] = {
         /* SCK */
-        63,
+        RCAR_GP_PIN(1, 31),
 };
 static const unsigned int scif2_clk_d_mux[] = {
         SCK2_D_MARK,
 };
 static const unsigned int scif2_data_e_pins[] = {
         /* RXD, TXD */
-        20, 19,
+        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif2_data_e_mux[] = {
         RX2_E_MARK, TX2_E_MARK,
@@ -2063,14 +2126,14 @@ static const unsigned int scif2_data_e_mux[] = {
 /* - SCIF3 ------------------------------------------------------------------ */
 static const unsigned int scif3_data_pins[] = {
         /* RXD, TXD */
-        137, 136,
+        RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
 };
 static const unsigned int scif3_data_mux[] = {
         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
 };
 static const unsigned int scif3_clk_pins[] = {
         /* SCK */
-        135,
+        RCAR_GP_PIN(4, 7),
 };
 static const unsigned int scif3_clk_mux[] = {
         SCK3_MARK,
@@ -2078,35 +2141,35 @@ static const unsigned int scif3_clk_mux[] = {
 
 static const unsigned int scif3_data_b_pins[] = {
         /* RXD, TXD */
-        64, 62,
+        RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif3_data_b_mux[] = {
         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
 };
 static const unsigned int scif3_data_c_pins[] = {
         /* RXD, TXD */
-        15, 12,
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
 };
 static const unsigned int scif3_data_c_mux[] = {
         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
 };
 static const unsigned int scif3_data_d_pins[] = {
         /* RXD, TXD */
-        30, 29,
+        RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
 };
 static const unsigned int scif3_data_d_mux[] = {
         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
 };
 static const unsigned int scif3_data_e_pins[] = {
         /* RXD, TXD */
-        35, 34,
+        RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int scif3_data_e_mux[] = {
         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
 };
 static const unsigned int scif3_clk_e_pins[] = {
         /* SCK */
-        42,
+        RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif3_clk_e_mux[] = {
         SCK3_E_MARK,
@@ -2114,42 +2177,42 @@ static const unsigned int scif3_clk_e_mux[] = {
 /* - SCIF4 ------------------------------------------------------------------ */
 static const unsigned int scif4_data_pins[] = {
         /* RXD, TXD */
-        123, 122,
+        RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
 };
 static const unsigned int scif4_data_mux[] = {
         RX4_MARK, TX4_MARK,
 };
 static const unsigned int scif4_clk_pins[] = {
         /* SCK */
-        121,
+        RCAR_GP_PIN(3, 25),
 };
 static const unsigned int scif4_clk_mux[] = {
         SCK4_MARK,
 };
 static const unsigned int scif4_data_b_pins[] = {
         /* RXD, TXD */
-        111, 110,
+        RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
 };
 static const unsigned int scif4_data_b_mux[] = {
         RX4_B_MARK, TX4_B_MARK,
 };
 static const unsigned int scif4_clk_b_pins[] = {
         /* SCK */
-        112,
+        RCAR_GP_PIN(3, 16),
 };
 static const unsigned int scif4_clk_b_mux[] = {
         SCK4_B_MARK,
 };
 static const unsigned int scif4_data_c_pins[] = {
         /* RXD, TXD */
-        22, 21,
+        RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 };
 static const unsigned int scif4_data_c_mux[] = {
         RX4_C_MARK, TX4_C_MARK,
 };
 static const unsigned int scif4_data_d_pins[] = {
         /* RXD, TXD */
-        69, 68,
+        RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif4_data_d_mux[] = {
         RX4_D_MARK, TX4_D_MARK,
@@ -2157,56 +2220,56 @@ static const unsigned int scif4_data_d_mux[] = {
 /* - SCIF5 ------------------------------------------------------------------ */
 static const unsigned int scif5_data_pins[] = {
         /* RXD, TXD */
-        51, 50,
+        RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif5_data_mux[] = {
         RX5_MARK, TX5_MARK,
 };
 static const unsigned int scif5_clk_pins[] = {
         /* SCK */
-        43,
+        RCAR_GP_PIN(1, 11),
 };
 static const unsigned int scif5_clk_mux[] = {
         SCK5_MARK,
 };
 static const unsigned int scif5_data_b_pins[] = {
         /* RXD, TXD */
-        18, 11,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif5_data_b_mux[] = {
         RX5_B_MARK, TX5_B_MARK,
 };
 static const unsigned int scif5_clk_b_pins[] = {
         /* SCK */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif5_clk_b_mux[] = {
         SCK5_B_MARK,
 };
 static const unsigned int scif5_data_c_pins[] = {
         /* RXD, TXD */
-        24, 23,
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
 };
 static const unsigned int scif5_data_c_mux[] = {
         RX5_C_MARK, TX5_C_MARK,
 };
 static const unsigned int scif5_clk_c_pins[] = {
         /* SCK */
-        28,
+        RCAR_GP_PIN(0, 28),
 };
 static const unsigned int scif5_clk_c_mux[] = {
         SCK5_C_MARK,
 };
 static const unsigned int scif5_data_d_pins[] = {
         /* RXD, TXD */
-        8, 6,
+        RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
 };
 static const unsigned int scif5_data_d_mux[] = {
         RX5_D_MARK, TX5_D_MARK,
 };
 static const unsigned int scif5_clk_d_pins[] = {
         /* SCK */
-        7,
+        RCAR_GP_PIN(0, 7),
 };
 static const unsigned int scif5_clk_d_mux[] = {
         SCK5_D_MARK,
@@ -2214,35 +2277,36 @@ static const unsigned int scif5_clk_d_mux[] = {
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
-        117,
+        RCAR_GP_PIN(3, 21),
 };
 static const unsigned int sdhi0_data1_mux[] = {
         SD0_DAT0_MARK,
 };
 static const unsigned int sdhi0_data4_pins[] = {
         /* D[0:3] */
-        117, 118, 119, 120,
+        RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+        RCAR_GP_PIN(3, 24),
 };
 static const unsigned int sdhi0_data4_mux[] = {
         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
         /* CMD, CLK */
-        114, 113,
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
 };
 static const unsigned int sdhi0_ctrl_mux[] = {
         SD0_CMD_MARK, SD0_CLK_MARK,
 };
 static const unsigned int sdhi0_cd_pins[] = {
         /* CD */
-        115,
+        RCAR_GP_PIN(3, 19),
 };
 static const unsigned int sdhi0_cd_mux[] = {
         SD0_CD_MARK,
 };
 static const unsigned int sdhi0_wp_pins[] = {
         /* WP */
-        116,
+        RCAR_GP_PIN(3, 20),
 };
 static const unsigned int sdhi0_wp_mux[] = {
         SD0_WP_MARK,
@@ -2250,35 +2314,36 @@ static const unsigned int sdhi0_wp_mux[] = {
 /* - SDHI1 ------------------------------------------------------------------ */
 static const unsigned int sdhi1_data1_pins[] = {
         /* D0 */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int sdhi1_data1_mux[] = {
         SD1_DAT0_MARK,
 };
 static const unsigned int sdhi1_data4_pins[] = {
         /* D[0:3] */
-        19, 20, 21, 2,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),
 };
 static const unsigned int sdhi1_data4_mux[] = {
         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
         /* CMD, CLK */
-        18, 17,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int sdhi1_ctrl_mux[] = {
         SD1_CMD_MARK, SD1_CLK_MARK,
 };
 static const unsigned int sdhi1_cd_pins[] = {
         /* CD */
-        10,
+        RCAR_GP_PIN(0, 10),
 };
 static const unsigned int sdhi1_cd_mux[] = {
         SD1_CD_MARK,
 };
 static const unsigned int sdhi1_wp_pins[] = {
         /* WP */
-        11,
+        RCAR_GP_PIN(0, 11),
 };
 static const unsigned int sdhi1_wp_mux[] = {
         SD1_WP_MARK,
@@ -2286,35 +2351,36 @@ static const unsigned int sdhi1_wp_mux[] = {
 /* - SDHI2 ------------------------------------------------------------------ */
 static const unsigned int sdhi2_data1_pins[] = {
         /* D0 */
-        97,
+        RCAR_GP_PIN(3, 1),
 };
 static const unsigned int sdhi2_data1_mux[] = {
         SD2_DAT0_MARK,
 };
 static const unsigned int sdhi2_data4_pins[] = {
         /* D[0:3] */
-        97, 98, 99, 100,
+        RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+        RCAR_GP_PIN(3, 4),
 };
 static const unsigned int sdhi2_data4_mux[] = {
         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
         /* CMD, CLK */
-        102, 101,
+        RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
 };
 static const unsigned int sdhi2_ctrl_mux[] = {
         SD2_CMD_MARK, SD2_CLK_MARK,
 };
 static const unsigned int sdhi2_cd_pins[] = {
         /* CD */
-        103,
+        RCAR_GP_PIN(3, 7),
 };
 static const unsigned int sdhi2_cd_mux[] = {
         SD2_CD_MARK,
 };
 static const unsigned int sdhi2_wp_pins[] = {
         /* WP */
-        104,
+        RCAR_GP_PIN(3, 8),
 };
 static const unsigned int sdhi2_wp_mux[] = {
         SD2_WP_MARK,
@@ -2322,35 +2388,36 @@ static const unsigned int sdhi2_wp_mux[] = {
 /* - SDHI3 ------------------------------------------------------------------ */
 static const unsigned int sdhi3_data1_pins[] = {
         /* D0 */
-        50,
+        RCAR_GP_PIN(1, 18),
 };
 static const unsigned int sdhi3_data1_mux[] = {
         SD3_DAT0_MARK,
 };
 static const unsigned int sdhi3_data4_pins[] = {
         /* D[0:3] */
-        50, 51, 52, 53,
+        RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
+        RCAR_GP_PIN(1, 21),
 };
 static const unsigned int sdhi3_data4_mux[] = {
         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
 };
 static const unsigned int sdhi3_ctrl_pins[] = {
         /* CMD, CLK */
-        35, 34,
+        RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int sdhi3_ctrl_mux[] = {
         SD3_CMD_MARK, SD3_CLK_MARK,
 };
 static const unsigned int sdhi3_cd_pins[] = {
         /* CD */
-        62,
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int sdhi3_cd_mux[] = {
         SD3_CD_MARK,
 };
 static const unsigned int sdhi3_wp_pins[] = {
         /* WP */
-        64,
+        RCAR_GP_PIN(2, 0),
 };
 static const unsigned int sdhi3_wp_mux[] = {
         SD3_WP_MARK,
@@ -2358,14 +2425,14 @@ static const unsigned int sdhi3_wp_mux[] = {
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
         /* PENC */
-        154,
+        RCAR_GP_PIN(4, 26),
 };
 static const unsigned int usb0_mux[] = {
         USB_PENC0_MARK,
 };
 static const unsigned int usb0_ovc_pins[] = {
         /* USB_OVC */
-        150
+        RCAR_GP_PIN(4, 22),
 };
 static const unsigned int usb0_ovc_mux[] = {
         USB_OVC0_MARK,
@@ -2373,14 +2440,14 @@ static const unsigned int usb0_ovc_mux[] = {
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
         /* PENC */
-        155,
+        RCAR_GP_PIN(4, 27),
 };
 static const unsigned int usb1_mux[] = {
         USB_PENC1_MARK,
 };
 static const unsigned int usb1_ovc_pins[] = {
         /* USB_OVC */
-        152,
+        RCAR_GP_PIN(4, 24),
 };
 static const unsigned int usb1_ovc_mux[] = {
         USB_OVC1_MARK,
@@ -2388,18 +2455,122 @@ static const unsigned int usb1_ovc_mux[] = {
 /* - USB2 ------------------------------------------------------------------- */
 static const unsigned int usb2_pins[] = {
         /* PENC */
-        156,
+        RCAR_GP_PIN(4, 28),
 };
 static const unsigned int usb2_mux[] = {
         USB_PENC2_MARK,
 };
 static const unsigned int usb2_ovc_pins[] = {
         /* USB_OVC */
-        125,
+        RCAR_GP_PIN(3, 29),
 };
 static const unsigned int usb2_ovc_mux[] = {
         USB_OVC2_MARK,
 };
+/* - VIN0 ------------------------------------------------------------------- */
+static const unsigned int vin0_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
+        RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+        RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int vin0_data8_mux[] = {
+        VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
+        VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+        VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 1),
+};
+static const unsigned int vin0_clk_mux[] = {
+        VI0_CLK_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int vin0_sync_mux[] = {
+        VI0_HSYNC_MARK, VI0_VSYNC_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const unsigned int vin1_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+        RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+        RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int vin1_data8_mux[] = {
+        VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
+        VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
+        VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 30),
+};
+static const unsigned int vin1_clk_mux[] = {
+        VI1_CLK_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin1_sync_mux[] = {
+        VI1_HSYNC_MARK, VI1_VSYNC_MARK,
+};
+/* - VIN2 ------------------------------------------------------------------- */
+static const unsigned int vin2_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
+        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
+        RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin2_data8_mux[] = {
+        VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
+        VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
+        VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
+};
+static const unsigned int vin2_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(1, 30),
+};
+static const unsigned int vin2_clk_mux[] = {
+        VI2_CLK_MARK,
+};
+static const unsigned int vin2_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin2_sync_mux[] = {
+        VI2_HSYNC_MARK, VI2_VSYNC_MARK,
+};
+/* - VIN3 ------------------------------------------------------------------- */
+static const unsigned int vin3_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+        RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+        RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin3_data8_mux[] = {
+        VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
+        VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
+        VI3_DATA6_MARK, VI3_DATA7_MARK,
+};
+static const unsigned int vin3_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 31),
+};
+static const unsigned int vin3_clk_mux[] = {
+        VI3_CLK_MARK,
+};
+static const unsigned int vin3_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin3_sync_mux[] = {
+        VI3_HSYNC_MARK, VI3_VSYNC_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(du0_rgb666),
@@ -2419,6 +2590,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(du1_sync_1),
         SH_PFC_PIN_GROUP(du1_oddf),
         SH_PFC_PIN_GROUP(du1_cde),
+        SH_PFC_PIN_GROUP(ether_rmii),
+        SH_PFC_PIN_GROUP(ether_link),
+        SH_PFC_PIN_GROUP(ether_magic),
         SH_PFC_PIN_GROUP(hspi0),
         SH_PFC_PIN_GROUP(hspi1),
         SH_PFC_PIN_GROUP(hspi1_b),
@@ -2527,6 +2701,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(usb1_ovc),
         SH_PFC_PIN_GROUP(usb2),
         SH_PFC_PIN_GROUP(usb2_ovc),
+        SH_PFC_PIN_GROUP(vin0_data8),
+        SH_PFC_PIN_GROUP(vin0_clk),
+        SH_PFC_PIN_GROUP(vin0_sync),
+        SH_PFC_PIN_GROUP(vin1_data8),
+        SH_PFC_PIN_GROUP(vin1_clk),
+        SH_PFC_PIN_GROUP(vin1_sync),
+        SH_PFC_PIN_GROUP(vin2_data8),
+        SH_PFC_PIN_GROUP(vin2_clk),
+        SH_PFC_PIN_GROUP(vin2_sync),
+        SH_PFC_PIN_GROUP(vin3_data8),
+        SH_PFC_PIN_GROUP(vin3_clk),
+        SH_PFC_PIN_GROUP(vin3_sync),
 };
 
 static const char * const du0_groups[] = {
@@ -2552,6 +2738,12 @@ static const char * const du1_groups[] = {
         "du1_cde",
 };
 
+static const char * const ether_groups[] = {
+        "ether_rmii",
+        "ether_link",
+        "ether_magic",
+};
+
 static const char * const hspi0_groups[] = {
         "hspi0",
 };
@@ -2720,9 +2912,34 @@ static const char * const usb2_groups[] = {
         "usb2_ovc",
 };
 
+static const char * const vin0_groups[] = {
+        "vin0_data8",
+        "vin0_clk",
+        "vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+        "vin1_data8",
+        "vin1_clk",
+        "vin1_sync",
+};
+
+static const char * const vin2_groups[] = {
+        "vin2_data8",
+        "vin2_clk",
+        "vin2_sync",
+};
+
+static const char * const vin3_groups[] = {
+        "vin3_data8",
+        "vin3_clk",
+        "vin3_sync",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(du0),
         SH_PFC_FUNCTION(du1),
+        SH_PFC_FUNCTION(ether),
         SH_PFC_FUNCTION(hspi0),
         SH_PFC_FUNCTION(hspi1),
         SH_PFC_FUNCTION(hspi2),
@@ -2743,6 +2960,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(usb0),
         SH_PFC_FUNCTION(usb1),
         SH_PFC_FUNCTION(usb2),
+        SH_PFC_FUNCTION(vin0),
+        SH_PFC_FUNCTION(vin1),
+        SH_PFC_FUNCTION(vin2),
+        SH_PFC_FUNCTION(vin3),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -3547,7 +3768,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
             /* SEL_SCIF [2] */
             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
             /* SEL_CANCLK [2] */
-            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
+            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
             /* SEL_CAN0 [1] */
             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
             /* SEL_HSCIF1 [1] */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
new file mode 100644
index 000000000000..85d77a417c0e
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -0,0 +1,3835 @@
+/*
+ * R8A7790 processor support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
+        PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
+        PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_32_REV(bank, fn, sfx)                                   \
+        PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
+        PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
+        PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
+        PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
+        PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
+        PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
+        PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
+        PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
+        PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
+        PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
+        PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
+        PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
+        PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
+        PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
+        PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
+        PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)                                           \
+        PORT_GP_32(0, fn, sfx),                                         \
+        PORT_GP_32(1, fn, sfx),                                         \
+        PORT_GP_32(2, fn, sfx),                                         \
+        PORT_GP_32(3, fn, sfx),                                         \
+        PORT_GP_32(4, fn, sfx),                                         \
+        PORT_GP_32(5, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)                                 \
+        [(bank * 32) + pin] = {                                         \
+                .name = __stringify(_name),                             \
+                .enum_id = _name##_DATA,                                \
+        }
+
+#define _GP_DATA(bank, pin, name, sfx)                                  \
+        PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+                                                          FN_##ipsr, FN_##fn)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA),
+        PINMUX_DATA_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN),
+
+        /* GPSR0 */
+        FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
+        FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
+        FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
+        FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
+        FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
+        FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
+        FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+        FN_IP3_14_12, FN_IP3_17_15,
+
+        /* GPSR1 */
+        FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
+        FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
+        FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
+        FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
+        FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
+        FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
+        FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
+
+        /* GPSR2 */
+        FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
+        FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
+        FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
+        FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
+        FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
+        FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
+        FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
+
+        /* GPSR3 */
+        FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
+        FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
+        FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
+        FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
+        FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
+        FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
+        FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
+
+        /* GPSR4 */
+        FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
+        FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
+        FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
+        FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
+        FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
+        FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
+        FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
+        FN_IP14_15_12, FN_IP14_18_16,
+
+        /* GPSR5 */
+        FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
+        FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
+        FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
+        FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
+        FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
+        FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
+        FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
+
+        /* IPSR0 */
+        FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+        FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
+        FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
+        FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
+        FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
+        FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+        FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
+        FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+        FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
+        FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+        FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C,
+        FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
+        FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
+        FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+
+        /* IPSR1 */
+        FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
+        FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
+        FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
+        FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
+        FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
+        FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+        FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+        FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+        FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+        FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
+        FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+        FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+        FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+        FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+        FN_A0, FN_PWM3, FN_A1, FN_PWM4,
+
+        /* IPSR2 */
+        FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
+        FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
+        FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
+        FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
+        FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+        FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+        FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B,
+        FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+        FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B,
+        FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+        FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
+
+        /* IPSR3 */
+        FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+        FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
+        FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+        FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+        FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+        FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+        FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
+        FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
+        FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
+        FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
+        FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
+        FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
+        FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+
+        /* IPSR4 */
+        FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
+        FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
+        FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
+        FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
+        FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+        FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
+        FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
+        FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+        FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+        FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
+        FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
+        FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
+        FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
+        FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+        FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
+
+        /* IPSR5 */
+        FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+        FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+        FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
+        FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX,
+        FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
+        FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
+        FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B,
+        FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
+        FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
+        FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+        FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+        FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
+        FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+        FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
+        FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+        FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+        FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
+        FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
+        FN_SSI_WS78_B,
+
+        /* IPSR6 */
+        FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+        FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
+        FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+        FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
+        FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+        FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
+        FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+        FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
+        FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+        FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+        FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
+        FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
+        FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
+        FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
+        FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
+        FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+        FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
+        FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+        FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
+        FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+        FN_STP_IVCXO27_1_B, FN_HRX0_F,
+
+        /* IPSR7 */
+        FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+        FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
+        FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+        FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
+        FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
+        FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
+        FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
+        FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+        FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
+        FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+        FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
+        FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
+        FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
+        FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
+        FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
+        FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+        FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+        FN_MII_RXD2,
+
+        /* IPSR8 */
+        FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
+        FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
+        FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
+        FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
+        FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
+        FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
+        FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
+        FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
+        FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
+        FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
+        FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+        FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+        FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
+        FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+        FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
+        FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+        FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
+        FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
+
+        /* IPSR9 */
+        FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
+        FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
+        FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
+        FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
+        FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+        FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+        FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
+        FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+        FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+        FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
+        FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
+        FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+        FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
+        FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
+        FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
+        FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+        FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
+        FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
+        FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
+        FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
+        FN_VI3_CLK_B,
+
+        /* IPSR10 */
+        FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+        FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+        FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+        FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+        FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+        FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+        FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+        FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+        FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+        FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+        FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+        FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+        FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+        FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+        FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+        FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
+        FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+        FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
+        FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
+        FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+        FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+        FN_GLO_I0_B, FN_VI3_DATA6_B,
+
+        /* IPSR11 */
+        FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+        FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+        FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
+        FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
+        FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
+        FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
+        FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
+        FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+        FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
+        FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+        FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+        FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
+        FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
+        FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
+        FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+        FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
+        FN_MOUT0,
+
+        /* IPSR12 */
+        FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
+        FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
+        FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
+        FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+        FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+        FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
+        FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+        FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
+        FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
+        FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+        FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
+        FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+        FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
+        FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+        FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
+        FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+        FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
+        FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+        FN_CAN_DEBUGOUT4,
+
+        /* IPSR13 */
+        FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+        FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
+        FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
+        FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+        FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6,
+        FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+        FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
+        FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
+        FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
+        FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
+        FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
+        FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
+        FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
+        FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+        FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
+        FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B,
+        FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8,
+        FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+        FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
+        FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+        FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
+        FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
+
+        /* IPSR14 */
+        FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+        FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+        FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
+        FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C,
+        FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
+        FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
+        FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
+        FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
+        FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
+        FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
+        FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
+        FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+        FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
+        FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+        FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
+        FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
+        FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
+        FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+        FN_HRTS0_N_C,
+
+        /* IPSR15 */
+        FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7,
+        FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
+        FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS,
+        FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17,
+        FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0,
+        FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
+        FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
+        FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
+        FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
+        FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+        FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
+        FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
+        FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0,
+        FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
+        FN_DU2_DG6, FN_LCDOUT14,
+
+        /* IPSR16 */
+        FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+        FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
+        FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+        FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C,
+        FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
+        FN_TCLK1_B,
+
+        FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+        FN_SEL_SCIF1_4,
+        FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
+        FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
+        FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+        FN_SEL_SCIFB1_4,
+        FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
+        FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
+        FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+        FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+        FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+        FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+        FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+        FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
+        FN_SEL_VI3_0, FN_SEL_VI3_1,
+        FN_SEL_VI2_0, FN_SEL_VI2_1,
+        FN_SEL_VI1_0, FN_SEL_VI1_1,
+        FN_SEL_VI0_0, FN_SEL_VI0_1,
+        FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
+        FN_SEL_LBS_0, FN_SEL_LBS_1,
+        FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+        FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+        FN_SEL_SOF0_0, FN_SEL_SOF0_1,
+
+        FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+        FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+        FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+        FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+        FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+        FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
+        FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+        FN_SEL_ADI_0, FN_SEL_ADI_1,
+        FN_SEL_SSP_0, FN_SEL_SSP_1,
+        FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+        FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
+        FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
+        FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
+        FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
+        FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+        FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
+        FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
+        FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+
+        FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+        FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+        FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+        FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+        FN_SEL_IIC2_4,
+        FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
+        FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+        FN_SEL_I2C2_4,
+        FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        VI1_DATA7_VI1_B7_MARK,
+
+        USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
+        USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
+        DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
+
+        D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
+        D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
+        VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
+        VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
+        VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
+        SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
+        VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
+        SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
+        VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
+        SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
+        SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
+        VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
+        D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
+        VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
+
+        D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
+        VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
+        SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
+        VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
+        SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
+        VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
+        D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
+        VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
+        D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
+        VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
+        SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
+        VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
+        D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
+        VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
+        A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
+
+        A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
+        PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
+        TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
+        A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
+        SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
+        A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
+        VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
+        A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
+        VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
+        A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
+        VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
+
+        A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
+        VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
+        A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
+        VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
+        A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
+        MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
+        VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
+        ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
+        ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
+        A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
+        AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
+        ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
+        VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
+
+        A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
+        A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
+        VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
+        VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
+        VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
+        VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
+        VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
+        VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
+        CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
+        VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
+        VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
+        MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
+        HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
+        VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
+        VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
+
+        EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
+        VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
+        EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
+        VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
+        INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
+        MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
+        VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
+        SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
+        CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
+        CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
+        VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
+        INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+        VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
+        WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
+        VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
+        IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+        VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
+        MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
+        VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
+        SSI_WS78_B_MARK,
+
+        DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+        VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
+        DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
+        SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
+        INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+        DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
+        MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+        SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
+        ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
+        TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
+        SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
+        STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
+        SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
+        STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
+        SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
+        RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
+        TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
+        RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
+        STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
+        ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
+        STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
+
+        ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
+        SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
+        RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
+        ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
+        HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
+        SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
+        STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
+        ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
+        TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
+        SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
+        GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
+        STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
+        PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
+        PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
+        AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
+        ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
+        VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
+        MII_RXD2_MARK,
+
+        VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
+        MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
+        AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
+        AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
+        AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
+        AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
+        MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
+        MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
+        MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
+        AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
+        SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
+        VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
+        MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
+        AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
+        AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
+        AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
+        SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
+        SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+
+        SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
+        SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+        SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
+        SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+        SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
+        GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
+        SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
+        MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
+        GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
+        SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
+        AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
+        AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
+        SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
+        SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
+        MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
+        AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
+        SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
+        SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
+        TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
+        SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
+        VI3_CLK_B_MARK,
+
+        SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
+        GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
+        SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
+        VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
+        VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
+        VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
+        TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
+        SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
+        VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
+        TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
+        SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
+        VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
+        TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
+        SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
+        VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
+        GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
+        MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
+        HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
+        VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
+        TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
+        VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
+        GLO_I0_B_MARK, VI3_DATA6_B_MARK,
+
+        SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
+        GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
+        TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
+        SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
+        MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
+        SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
+        MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
+        SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
+        VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
+        MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
+        RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
+        RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
+        MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
+        SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
+        SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
+        RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
+        MOUT0_MARK,
+
+        SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
+        SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
+        SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
+        SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
+        SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
+        MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
+        STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
+        CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
+        SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
+        SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
+        MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
+        SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
+        MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
+        SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
+        CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
+        IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
+        CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
+        IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
+        CAN_DEBUGOUT4_MARK,
+
+        SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
+        LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
+        SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
+        DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
+        BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
+        SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
+        LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
+        FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
+        CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
+        SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
+        CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
+        SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
+        LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
+        STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
+        TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
+        BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
+        FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
+        STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
+        CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
+        STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
+        SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
+        SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
+
+        AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
+        DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
+        REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
+        MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
+        SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
+        DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
+        TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
+        HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
+        LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
+        SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
+        MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
+        SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
+        DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+        SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
+        LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
+        CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
+        SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
+        MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
+        HRTS0_N_C_MARK,
+
+        SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
+        LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
+        DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
+        SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
+        SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
+        DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
+        DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
+        LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
+        LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
+        LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
+        DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
+        SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
+        SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
+        DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
+        DU2_DG6_MARK, LCDOUT14_MARK,
+
+        MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
+        DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
+        MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
+        ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
+        USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
+        TCLK1_B_MARK,
+        PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+        PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
+        PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+        PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
+        PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
+        PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
+        PINMUX_DATA(AVS1_MARK, FN_AVS1),
+        PINMUX_DATA(AVS2_MARK, FN_AVS2),
+        PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
+        PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
+
+        PINMUX_IPSR_DATA(IP0_2_0, D0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_5_3, D1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_8_6, D2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_11_9, D3),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_15_12, D4),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP0_19_16, D5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP0_22_20, D6),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP0_26_23, D7),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP0_30_27, D8),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
+        PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
+
+        PINMUX_IPSR_DATA(IP1_3_0, D9),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
+        PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_7_4, D10),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
+        PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_11_8, D11),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
+        PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_14_12, D12),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_17_15, D13),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_21_18, D14),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
+        PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_25_22, D15),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
+        PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_27_26, A0),
+        PINMUX_IPSR_DATA(IP1_27_26, PWM3),
+        PINMUX_IPSR_DATA(IP1_29_28, A1),
+        PINMUX_IPSR_DATA(IP1_29_28, PWM4),
+
+        PINMUX_IPSR_DATA(IP2_2_0, A2),
+        PINMUX_IPSR_DATA(IP2_2_0, PWM5),
+        PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_5_3, A3),
+        PINMUX_IPSR_DATA(IP2_5_3, PWM6),
+        PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_8_6, A4),
+        PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
+        PINMUX_IPSR_DATA(IP2_11_9, A5),
+        PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
+        PINMUX_IPSR_DATA(IP2_14_12, A6),
+        PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
+        PINMUX_IPSR_DATA(IP2_17_15, A7),
+        PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
+        PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
+        PINMUX_IPSR_DATA(IP2_21_18, A8),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP2_25_22, A9),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP2_28_26, A10),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
+        PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
+
+        PINMUX_IPSR_DATA(IP3_3_0, A11),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
+        PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B),
+        PINMUX_IPSR_DATA(IP3_7_4, A12),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
+        PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B),
+        PINMUX_IPSR_DATA(IP3_11_8, A13),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
+        PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP3_14_12, A14),
+        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
+        PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
+        PINMUX_IPSR_DATA(IP3_17_15, A15),
+        PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
+        PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
+        PINMUX_IPSR_DATA(IP3_19_18, A16),
+        PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
+        PINMUX_IPSR_DATA(IP3_22_20, A17),
+        PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
+        PINMUX_IPSR_DATA(IP3_25_23, A18),
+        PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
+        PINMUX_IPSR_DATA(IP3_28_26, A19),
+        PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
+        PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
+        PINMUX_IPSR_DATA(IP3_31_29, A20),
+        PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
+        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
+
+        PINMUX_IPSR_DATA(IP4_2_0, A21),
+        PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
+        PINMUX_IPSR_DATA(IP4_5_3, A22),
+        PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
+        PINMUX_IPSR_DATA(IP4_8_6, A23),
+        PINMUX_IPSR_DATA(IP4_8_6, IO2),
+        PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
+        PINMUX_IPSR_DATA(IP4_11_9, A24),
+        PINMUX_IPSR_DATA(IP4_11_9, IO3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_14_12, A25),
+        PINMUX_IPSR_DATA(IP4_14_12, SSL),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
+        PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
+        PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
+        PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
+        PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
+
+        PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
+        PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
+        PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0),
+        PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0),
+        PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0),
+        PINMUX_IPSR_DATA(IP5_12_10, BS_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
+        PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP5_14_13, RD_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
+        PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
+        PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
+        PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0),
+        PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
+        PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
+
+        PINMUX_IPSR_DATA(IP6_2_0, DACK0),
+        PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
+        PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
+        PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
+        PINMUX_IPSR_DATA(IP6_8_6, DACK1),
+        PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
+        PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
+        PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP6_13_11, DACK2),
+        PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
+        PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
+        PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
+        PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
+        PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
+        PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
+        PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
+        PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
+        PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
+        PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
+
+        PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
+        PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
+        PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
+        PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
+        PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
+        PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
+        PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
+        PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
+        PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
+        PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_18_16, PWM0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_21_19, PWM1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
+        PINMUX_IPSR_DATA(IP7_24_22, PWM2),
+        PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
+        PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
+        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
+        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
+        PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
+        PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
+        PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
+        PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
+
+        PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
+        PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
+        PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
+        PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
+        PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
+        PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
+        PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
+        PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
+        PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
+        PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
+        PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
+        PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
+        PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
+        PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
+        PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
+        PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
+        PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
+        PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
+        PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
+        PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
+        PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
+        PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
+        PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
+        PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
+        PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
+
+        PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
+        PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
+        PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
+        PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
+        PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
+        PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
+        PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
+        PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
+        PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
+        PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
+        PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
+        PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
+        PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
+        PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
+        PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
+        PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
+        PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
+        PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
+        PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
+        PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
+
+        PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
+        PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
+        PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
+        PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
+        PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
+        PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
+        PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
+        PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
+        PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
+        PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
+
+        PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
+        PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
+        PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
+        PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
+        PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
+        PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
+        PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
+        PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
+        PINMUX_IPSR_DATA(IP11_8_7, STM_N),
+        PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
+        PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
+        PINMUX_IPSR_DATA(IP11_10_9, MDATA),
+        PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
+        PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
+        PINMUX_IPSR_DATA(IP11_12_11, SDATA),
+        PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
+        PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
+        PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
+        PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
+        PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP11_17_15, VSP),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
+        PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
+        PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
+        PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
+        PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
+        PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
+        PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
+        PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
+
+        PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
+        PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
+        PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
+        PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
+        PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
+        PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
+        PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
+        PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
+        PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1),
+        PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
+        PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
+        PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
+        PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
+        PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
+        PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
+        PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
+        PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
+        PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
+        PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
+        PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
+        PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
+        PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
+        PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
+        PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
+
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
+        PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
+        PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2),
+        PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
+        PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
+        PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
+        PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
+        PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
+        PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2),
+        PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
+        PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
+        PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
+        PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
+        PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
+        PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
+        PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
+        PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
+        PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
+        PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
+        PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
+        PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
+        PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
+        PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
+        PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
+        PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
+
+        PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
+        PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
+        PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
+        PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
+        PINMUX_IPSR_DATA(IP14_5_3, SCK0),
+        PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
+        PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
+        PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
+        PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
+        PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
+        PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS),
+        PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
+        PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
+        PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
+        PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
+        PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP14_27_25, QCLK),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
+
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
+        PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
+        PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
+        PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
+        PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
+        PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
+        PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
+        PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
+        PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
+        PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
+        PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
+        PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
+        PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
+        PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
+        PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
+        PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
+        PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
+        PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
+        PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
+        PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
+        PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
+        PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
+        PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
+        PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
+        PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
+        PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
+        PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
+        PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
+        PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
+
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
+        PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
+        PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
+        PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
+        PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
+        PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
+        PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2),
+        PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
+        PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
+        PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
+        PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+};
+
+/* - ETH -------------------------------------------------------------------- */
+static const unsigned int eth_link_pins[] = {
+        /* LINK */
+        RCAR_GP_PIN(2, 22),
+};
+static const unsigned int eth_link_mux[] = {
+        ETH_LINK_MARK,
+};
+static const unsigned int eth_magic_pins[] = {
+        /* MAGIC */
+        RCAR_GP_PIN(2, 27),
+};
+static const unsigned int eth_magic_mux[] = {
+        ETH_MAGIC_MARK,
+};
+static const unsigned int eth_mdio_pins[] = {
+        /* MDC, MDIO */
+        RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int eth_mdio_mux[] = {
+        ETH_MDC_MARK, ETH_MDIO_MARK,
+};
+static const unsigned int eth_rmii_pins[] = {
+        /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+        RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
+        RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
+        RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int eth_rmii_mux[] = {
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_irq0_mux[] = {
+        IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_irq1_mux[] = {
+        IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 29),
+};
+static const unsigned int intc_irq2_mux[] = {
+        IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 23),
+};
+static const unsigned int intc_irq3_mux[] = {
+        IRQ3_MARK,
+};
+/* - SCIF0 ----------------------------------------------------------------- */
+static const unsigned int scif0_data_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scif0_data_mux[] = {
+        RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif0_clk_mux[] = {
+        SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+        RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scif0_data_b_mux[] = {
+        RX0_B_MARK, TX0_B_MARK,
+};
+/* - SCIF1 ----------------------------------------------------------------- */
+static const unsigned int scif1_data_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scif1_data_mux[] = {
+        RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scif1_clk_mux[] = {
+        SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+        RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scif1_data_b_mux[] = {
+        RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif1_data_c_mux[] = {
+        RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_data_d_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scif1_data_d_mux[] = {
+        RX1_D_MARK, TX1_D_MARK,
+};
+static const unsigned int scif1_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scif1_clk_d_mux[] = {
+        SCK1_D_MARK,
+};
+static const unsigned int scif1_data_e_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scif1_data_e_mux[] = {
+        RX1_E_MARK, TX1_E_MARK,
+};
+static const unsigned int scif1_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scif1_clk_e_mux[] = {
+        SCK1_E_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
+};
+static const unsigned int scifa0_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int scifa0_data_b_mux[] = {
+        SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
+};
+static const unsigned int scifa0_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 19),
+};
+static const unsigned int scifa0_clk_b_mux[] = {
+        SCIFA0_SCK_B_MARK,
+};
+static const unsigned int scifa0_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scifa0_ctrl_b_mux[] = {
+        SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
+};
+static const unsigned int scifa1_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
+};
+static const unsigned int scifa1_data_b_mux[] = {
+        SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
+};
+static const unsigned int scifa1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 23),
+};
+static const unsigned int scifa1_clk_b_mux[] = {
+        SCIFA1_SCK_B_MARK,
+};
+static const unsigned int scifa1_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifa1_ctrl_b_mux[] = {
+        SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
+};
+static const unsigned int scifa1_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scifa1_data_c_mux[] = {
+        SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
+};
+static const unsigned int scifa1_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scifa1_clk_c_mux[] = {
+        SCIFA1_SCK_C_MARK,
+};
+static const unsigned int scifa1_ctrl_c_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int scifa1_ctrl_c_mux[] = {
+        SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
+};
+static const unsigned int scifa1_data_d_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scifa1_data_d_mux[] = {
+        SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
+};
+static const unsigned int scifa1_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scifa1_clk_d_mux[] = {
+        SCIFA1_SCK_D_MARK,
+};
+static const unsigned int scifa1_ctrl_d_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int scifa1_ctrl_d_mux[] = {
+        SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scifa2_clk_mux[] = {
+        SCIFA2_SCK_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
+};
+static const unsigned int scifa2_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int scifa2_data_b_mux[] = {
+        SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
+};
+static const unsigned int scifa2_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
+};
+static const unsigned int scifa2_data_c_mux[] = {
+        SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
+};
+static const unsigned int scifa2_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 29),
+};
+static const unsigned int scifa2_clk_c_mux[] = {
+        SCIFA2_SCK_C_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+};
+static const unsigned int scifb0_data_mux[] = {
+        SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scifb0_clk_mux[] = {
+        SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+        SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
+};
+static const unsigned int scifb0_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int scifb0_data_b_mux[] = {
+        SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
+};
+static const unsigned int scifb0_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 9),
+};
+static const unsigned int scifb0_clk_b_mux[] = {
+        SCIFB0_SCK_B_MARK,
+};
+static const unsigned int scifb0_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scifb0_ctrl_b_mux[] = {
+        SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+};
+static const unsigned int scifb0_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb0_data_c_mux[] = {
+        SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int scifb1_data_mux[] = {
+        SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 14),
+};
+static const unsigned int scifb1_clk_mux[] = {
+        SCIFB1_SCK_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+        SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+};
+static const unsigned int scifb1_data_b_mux[] = {
+        SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 1),
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+        SCIFB1_SCK_B_MARK,
+};
+static const unsigned int scifb1_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
+};
+static const unsigned int scifb1_ctrl_b_mux[] = {
+        SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
+};
+static const unsigned int scifb1_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scifb1_data_c_mux[] = {
+        SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
+};
+static const unsigned int scifb1_data_d_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scifb1_data_d_mux[] = {
+        SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
+};
+static const unsigned int scifb1_data_e_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scifb1_data_e_mux[] = {
+        SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
+};
+static const unsigned int scifb1_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scifb1_clk_e_mux[] = {
+        SCIFB1_SCK_E_MARK,
+};
+static const unsigned int scifb1_data_f_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb1_data_f_mux[] = {
+        SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
+};
+static const unsigned int scifb1_data_g_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scifb1_data_g_mux[] = {
+        SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
+};
+static const unsigned int scifb1_clk_g_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scifb1_clk_g_mux[] = {
+        SCIFB1_SCK_G_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scifb2_data_mux[] = {
+        SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifb2_clk_mux[] = {
+        SCIFB2_SCK_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+        SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
+};
+static const unsigned int scifb2_data_b_mux[] = {
+        SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 31),
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+        SCIFB2_SCK_B_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+        SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
+};
+static const unsigned int scifb2_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifb2_data_c_mux[] = {
+        SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
+};
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 20),
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 21),
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 22),
+};
+static const unsigned int tpu0_to2_mux[] = {
+        TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 23),
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
+
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_pins[] = {
+        /* D[0] */
+        RCAR_GP_PIN(3, 18),
+};
+static const unsigned int mmc0_data1_mux[] = {
+        MMC0_D0_MARK,
+};
+static const unsigned int mmc0_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+        RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int mmc0_data4_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+};
+static const unsigned int mmc0_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+        RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+        RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+        RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int mmc0_data8_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+        MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc0_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int mmc0_ctrl_mux[] = {
+        MMC0_CLK_MARK, MMC0_CMD_MARK,
+};
+
+static const unsigned int mmc1_data1_pins[] = {
+        /* D[0] */
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int mmc1_data1_mux[] = {
+        MMC1_D0_MARK,
+};
+static const unsigned int mmc1_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+        RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int mmc1_data4_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+};
+static const unsigned int mmc1_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+        RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+        RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int mmc1_data8_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+        MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
+};
+static const unsigned int mmc1_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int mmc1_ctrl_mux[] = {
+        MMC1_CLK_MARK, MMC1_CMD_MARK,
+};
+
+/* - SDHI ------------------------------------------------------------------- */
+static const unsigned int sdhi0_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+        SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+        SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+        SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 6),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+        SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 7),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+        SD0_WP_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 10),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+        SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+        SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+        SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+        SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+        SD1_WP_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 18),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+        SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+        SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+        SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 22),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+        SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 23),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+        SD2_WP_MARK,
+};
+
+static const unsigned int sdhi3_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int sdhi3_data1_mux[] = {
+        SD3_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int sdhi3_data4_mux[] = {
+        SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+        SD3_CLK_MARK, SD3_CMD_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 30),
+};
+static const unsigned int sdhi3_cd_mux[] = {
+        SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 31),
+};
+static const unsigned int sdhi3_wp_mux[] = {
+        SD3_WP_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(eth_link),
+        SH_PFC_PIN_GROUP(eth_magic),
+        SH_PFC_PIN_GROUP(eth_mdio),
+        SH_PFC_PIN_GROUP(eth_rmii),
+        SH_PFC_PIN_GROUP(intc_irq0),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2),
+        SH_PFC_PIN_GROUP(intc_irq3),
+        SH_PFC_PIN_GROUP(scif0_data),
+        SH_PFC_PIN_GROUP(scif0_clk),
+        SH_PFC_PIN_GROUP(scif0_ctrl),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif1_data),
+        SH_PFC_PIN_GROUP(scif1_clk),
+        SH_PFC_PIN_GROUP(scif1_ctrl),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_data_d),
+        SH_PFC_PIN_GROUP(scif1_clk_d),
+        SH_PFC_PIN_GROUP(scif1_data_e),
+        SH_PFC_PIN_GROUP(scif1_clk_e),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa0_data_b),
+        SH_PFC_PIN_GROUP(scifa0_clk_b),
+        SH_PFC_PIN_GROUP(scifa0_ctrl_b),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data_b),
+        SH_PFC_PIN_GROUP(scifa1_clk_b),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_b),
+        SH_PFC_PIN_GROUP(scifa1_data_c),
+        SH_PFC_PIN_GROUP(scifa1_clk_c),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_c),
+        SH_PFC_PIN_GROUP(scifa1_data_d),
+        SH_PFC_PIN_GROUP(scifa1_clk_d),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_d),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data_b),
+        SH_PFC_PIN_GROUP(scifa2_data_c),
+        SH_PFC_PIN_GROUP(scifa2_clk_c),
+        SH_PFC_PIN_GROUP(scifb0_data),
+        SH_PFC_PIN_GROUP(scifb0_clk),
+        SH_PFC_PIN_GROUP(scifb0_ctrl),
+        SH_PFC_PIN_GROUP(scifb0_data_b),
+        SH_PFC_PIN_GROUP(scifb0_clk_b),
+        SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb0_data_c),
+        SH_PFC_PIN_GROUP(scifb1_data),
+        SH_PFC_PIN_GROUP(scifb1_clk),
+        SH_PFC_PIN_GROUP(scifb1_ctrl),
+        SH_PFC_PIN_GROUP(scifb1_data_b),
+        SH_PFC_PIN_GROUP(scifb1_clk_b),
+        SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb1_data_c),
+        SH_PFC_PIN_GROUP(scifb1_data_d),
+        SH_PFC_PIN_GROUP(scifb1_data_e),
+        SH_PFC_PIN_GROUP(scifb1_clk_e),
+        SH_PFC_PIN_GROUP(scifb1_data_f),
+        SH_PFC_PIN_GROUP(scifb1_data_g),
+        SH_PFC_PIN_GROUP(scifb1_clk_g),
+        SH_PFC_PIN_GROUP(scifb2_data),
+        SH_PFC_PIN_GROUP(scifb2_clk),
+        SH_PFC_PIN_GROUP(scifb2_ctrl),
+        SH_PFC_PIN_GROUP(scifb2_data_b),
+        SH_PFC_PIN_GROUP(scifb2_clk_b),
+        SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb2_data_c),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+        SH_PFC_PIN_GROUP(mmc0_data1),
+        SH_PFC_PIN_GROUP(mmc0_data4),
+        SH_PFC_PIN_GROUP(mmc0_data8),
+        SH_PFC_PIN_GROUP(mmc0_ctrl),
+        SH_PFC_PIN_GROUP(mmc1_data1),
+        SH_PFC_PIN_GROUP(mmc1_data4),
+        SH_PFC_PIN_GROUP(mmc1_data8),
+        SH_PFC_PIN_GROUP(mmc1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_data1),
+        SH_PFC_PIN_GROUP(sdhi1_data4),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi1_cd),
+        SH_PFC_PIN_GROUP(sdhi1_wp),
+        SH_PFC_PIN_GROUP(sdhi2_data1),
+        SH_PFC_PIN_GROUP(sdhi2_data4),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(sdhi2_cd),
+        SH_PFC_PIN_GROUP(sdhi2_wp),
+        SH_PFC_PIN_GROUP(sdhi3_data1),
+        SH_PFC_PIN_GROUP(sdhi3_data4),
+        SH_PFC_PIN_GROUP(sdhi3_ctrl),
+        SH_PFC_PIN_GROUP(sdhi3_cd),
+        SH_PFC_PIN_GROUP(sdhi3_wp),
+};
+
+static const char * const eth_groups[] = {
+        "eth_link",
+        "eth_magic",
+        "eth_mdio",
+        "eth_rmii",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0",
+        "intc_irq1",
+        "intc_irq2",
+        "intc_irq3",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data",
+        "scif0_clk",
+        "scif0_ctrl",
+        "scif0_data_b",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data",
+        "scif1_clk",
+        "scif1_ctrl",
+        "scif1_data_b",
+        "scif1_data_c",
+        "scif1_data_d",
+        "scif1_clk_d",
+        "scif1_data_e",
+        "scif1_clk_e",
+};
+
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+        "scifa0_data_b",
+        "scifa0_clk_b",
+        "scifa0_ctrl_b",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+        "scifa1_data_b",
+        "scifa1_clk_b",
+        "scifa1_ctrl_b",
+        "scifa1_data_c",
+        "scifa1_clk_c",
+        "scifa1_ctrl_c",
+        "scifa1_data_d",
+        "scifa1_clk_d",
+        "scifa1_ctrl_d",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk",
+        "scifa2_ctrl",
+        "scifa2_data_b",
+        "scifa2_data_c",
+        "scifa2_clk_c",
+};
+
+static const char * const scifb0_groups[] = {
+        "scifb0_data",
+        "scifb0_clk",
+        "scifb0_ctrl",
+        "scifb0_data_b",
+        "scifb0_clk_b",
+        "scifb0_ctrl_b",
+        "scifb0_data_c",
+};
+
+static const char * const scifb1_groups[] = {
+        "scifb1_data",
+        "scifb1_clk",
+        "scifb1_ctrl",
+        "scifb1_data_b",
+        "scifb1_clk_b",
+        "scifb1_ctrl_b",
+        "scifb1_data_c",
+        "scifb1_data_d",
+        "scifb1_data_e",
+        "scifb1_clk_e",
+        "scifb1_data_f",
+        "scifb1_data_g",
+        "scifb1_clk_g",
+};
+
+static const char * const scifb2_groups[] = {
+        "scifb2_data",
+        "scifb2_clk",
+        "scifb2_ctrl",
+        "scifb2_data_b",
+        "scifb2_clk_b",
+        "scifb2_ctrl_b",
+        "scifb2_data_c",
+};
+
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2",
+        "tpu0_to3",
+};
+
+static const char * const mmc0_groups[] = {
+        "mmc0_data1",
+        "mmc0_data4",
+        "mmc0_data8",
+        "mmc0_ctrl",
+};
+
+static const char * const mmc1_groups[] = {
+        "mmc1_data1",
+        "mmc1_data4",
+        "mmc1_data8",
+        "mmc1_ctrl",
+};
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_ctrl",
+        "sdhi0_cd",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_data1",
+        "sdhi1_data4",
+        "sdhi1_ctrl",
+        "sdhi1_cd",
+        "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_data1",
+        "sdhi2_data4",
+        "sdhi2_ctrl",
+        "sdhi2_cd",
+        "sdhi2_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+        "sdhi3_data1",
+        "sdhi3_data4",
+        "sdhi3_ctrl",
+        "sdhi3_cd",
+        "sdhi3_wp",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(eth),
+        SH_PFC_FUNCTION(intc),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifb0),
+        SH_PFC_FUNCTION(scifb1),
+        SH_PFC_FUNCTION(scifb2),
+        SH_PFC_FUNCTION(tpu0),
+        SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(mmc1),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(sdhi3),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+                GP_0_31_FN, FN_IP3_17_15,
+                GP_0_30_FN, FN_IP3_14_12,
+                GP_0_29_FN, FN_IP3_11_8,
+                GP_0_28_FN, FN_IP3_7_4,
+                GP_0_27_FN, FN_IP3_3_0,
+                GP_0_26_FN, FN_IP2_28_26,
+                GP_0_25_FN, FN_IP2_25_22,
+                GP_0_24_FN, FN_IP2_21_18,
+                GP_0_23_FN, FN_IP2_17_15,
+                GP_0_22_FN, FN_IP2_14_12,
+                GP_0_21_FN, FN_IP2_11_9,
+                GP_0_20_FN, FN_IP2_8_6,
+                GP_0_19_FN, FN_IP2_5_3,
+                GP_0_18_FN, FN_IP2_2_0,
+                GP_0_17_FN, FN_IP1_29_28,
+                GP_0_16_FN, FN_IP1_27_26,
+                GP_0_15_FN, FN_IP1_25_22,
+                GP_0_14_FN, FN_IP1_21_18,
+                GP_0_13_FN, FN_IP1_17_15,
+                GP_0_12_FN, FN_IP1_14_12,
+                GP_0_11_FN, FN_IP1_11_8,
+                GP_0_10_FN, FN_IP1_7_4,
+                GP_0_9_FN, FN_IP1_3_0,
+                GP_0_8_FN, FN_IP0_30_27,
+                GP_0_7_FN, FN_IP0_26_23,
+                GP_0_6_FN, FN_IP0_22_20,
+                GP_0_5_FN, FN_IP0_19_16,
+                GP_0_4_FN, FN_IP0_15_12,
+                GP_0_3_FN, FN_IP0_11_9,
+                GP_0_2_FN, FN_IP0_8_6,
+                GP_0_1_FN, FN_IP0_5_3,
+                GP_0_0_FN, FN_IP0_2_0 }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+                0, 0,
+                0, 0,
+                GP_1_29_FN, FN_IP6_13_11,
+                GP_1_28_FN, FN_IP6_10_9,
+                GP_1_27_FN, FN_IP6_8_6,
+                GP_1_26_FN, FN_IP6_5_3,
+                GP_1_25_FN, FN_IP6_2_0,
+                GP_1_24_FN, FN_IP5_29_27,
+                GP_1_23_FN, FN_IP5_26_24,
+                GP_1_22_FN, FN_IP5_23_21,
+                GP_1_21_FN, FN_IP5_20_18,
+                GP_1_20_FN, FN_IP5_17_15,
+                GP_1_19_FN, FN_IP5_14_13,
+                GP_1_18_FN, FN_IP5_12_10,
+                GP_1_17_FN, FN_IP5_9_6,
+                GP_1_16_FN, FN_IP5_5_3,
+                GP_1_15_FN, FN_IP5_2_0,
+                GP_1_14_FN, FN_IP4_29_27,
+                GP_1_13_FN, FN_IP4_26_24,
+                GP_1_12_FN, FN_IP4_23_21,
+                GP_1_11_FN, FN_IP4_20_18,
+                GP_1_10_FN, FN_IP4_17_15,
+                GP_1_9_FN, FN_IP4_14_12,
+                GP_1_8_FN, FN_IP4_11_9,
+                GP_1_7_FN, FN_IP4_8_6,
+                GP_1_6_FN, FN_IP4_5_3,
+                GP_1_5_FN, FN_IP4_2_0,
+                GP_1_4_FN, FN_IP3_31_29,
+                GP_1_3_FN, FN_IP3_28_26,
+                GP_1_2_FN, FN_IP3_25_23,
+                GP_1_1_FN, FN_IP3_22_20,
+                GP_1_0_FN, FN_IP3_19_18, }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+                0, 0,
+                0, 0,
+                GP_2_29_FN, FN_IP7_15_13,
+                GP_2_28_FN, FN_IP7_12_10,
+                GP_2_27_FN, FN_IP7_9_8,
+                GP_2_26_FN, FN_IP7_7_6,
+                GP_2_25_FN, FN_IP7_5_3,
+                GP_2_24_FN, FN_IP7_2_0,
+                GP_2_23_FN, FN_IP6_31_29,
+                GP_2_22_FN, FN_IP6_28_26,
+                GP_2_21_FN, FN_IP6_25_23,
+                GP_2_20_FN, FN_IP6_22_20,
+                GP_2_19_FN, FN_IP6_19_17,
+                GP_2_18_FN, FN_IP6_16_14,
+                GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
+                GP_2_16_FN, FN_IP8_27,
+                GP_2_15_FN, FN_IP8_26,
+                GP_2_14_FN, FN_IP8_25_24,
+                GP_2_13_FN, FN_IP8_23_22,
+                GP_2_12_FN, FN_IP8_21_20,
+                GP_2_11_FN, FN_IP8_19_18,
+                GP_2_10_FN, FN_IP8_17_16,
+                GP_2_9_FN, FN_IP8_15_14,
+                GP_2_8_FN, FN_IP8_13_12,
+                GP_2_7_FN, FN_IP8_11_10,
+                GP_2_6_FN, FN_IP8_9_8,
+                GP_2_5_FN, FN_IP8_7_6,
+                GP_2_4_FN, FN_IP8_5_4,
+                GP_2_3_FN, FN_IP8_3_2,
+                GP_2_2_FN, FN_IP8_1_0,
+                GP_2_1_FN, FN_IP7_30_29,
+                GP_2_0_FN, FN_IP7_28_27 }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+                GP_3_31_FN, FN_IP11_21_18,
+                GP_3_30_FN, FN_IP11_17_15,
+                GP_3_29_FN, FN_IP11_14_13,
+                GP_3_28_FN, FN_IP11_12_11,
+                GP_3_27_FN, FN_IP11_10_9,
+                GP_3_26_FN, FN_IP11_8_7,
+                GP_3_25_FN, FN_IP11_6_5,
+                GP_3_24_FN, FN_IP11_4,
+                GP_3_23_FN, FN_IP11_3_0,
+                GP_3_22_FN, FN_IP10_29_26,
+                GP_3_21_FN, FN_IP10_25_23,
+                GP_3_20_FN, FN_IP10_22_19,
+                GP_3_19_FN, FN_IP10_18_15,
+                GP_3_18_FN, FN_IP10_14_11,
+                GP_3_17_FN, FN_IP10_10_7,
+                GP_3_16_FN, FN_IP10_6_4,
+                GP_3_15_FN, FN_IP10_3_0,
+                GP_3_14_FN, FN_IP9_31_28,
+                GP_3_13_FN, FN_IP9_27_26,
+                GP_3_12_FN, FN_IP9_25_24,
+                GP_3_11_FN, FN_IP9_23_22,
+                GP_3_10_FN, FN_IP9_21_20,
+                GP_3_9_FN, FN_IP9_19_18,
+                GP_3_8_FN, FN_IP9_17_16,
+                GP_3_7_FN, FN_IP9_15_12,
+                GP_3_6_FN, FN_IP9_11_8,
+                GP_3_5_FN, FN_IP9_7_6,
+                GP_3_4_FN, FN_IP9_5_4,
+                GP_3_3_FN, FN_IP9_3_2,
+                GP_3_2_FN, FN_IP9_1_0,
+                GP_3_1_FN, FN_IP8_30_29,
+                GP_3_0_FN, FN_IP8_28 }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+                GP_4_31_FN, FN_IP14_18_16,
+                GP_4_30_FN, FN_IP14_15_12,
+                GP_4_29_FN, FN_IP14_11_9,
+                GP_4_28_FN, FN_IP14_8_6,
+                GP_4_27_FN, FN_IP14_5_3,
+                GP_4_26_FN, FN_IP14_2_0,
+                GP_4_25_FN, FN_IP13_30_29,
+                GP_4_24_FN, FN_IP13_28_26,
+                GP_4_23_FN, FN_IP13_25_23,
+                GP_4_22_FN, FN_IP13_22_19,
+                GP_4_21_FN, FN_IP13_18_16,
+                GP_4_20_FN, FN_IP13_15_13,
+                GP_4_19_FN, FN_IP13_12_10,
+                GP_4_18_FN, FN_IP13_9_7,
+                GP_4_17_FN, FN_IP13_6_3,
+                GP_4_16_FN, FN_IP13_2_0,
+                GP_4_15_FN, FN_IP12_30_28,
+                GP_4_14_FN, FN_IP12_27_25,
+                GP_4_13_FN, FN_IP12_24_23,
+                GP_4_12_FN, FN_IP12_22_20,
+                GP_4_11_FN, FN_IP12_19_17,
+                GP_4_10_FN, FN_IP12_16_14,
+                GP_4_9_FN, FN_IP12_13_11,
+                GP_4_8_FN, FN_IP12_10_8,
+                GP_4_7_FN, FN_IP12_7_6,
+                GP_4_6_FN, FN_IP12_5_4,
+                GP_4_5_FN, FN_IP12_3_2,
+                GP_4_4_FN, FN_IP12_1_0,
+                GP_4_3_FN, FN_IP11_31_30,
+                GP_4_2_FN, FN_IP11_29_27,
+                GP_4_1_FN, FN_IP11_26_24,
+                GP_4_0_FN, FN_IP11_23_22 }
+        },
+        { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+                GP_5_31_FN, FN_IP7_24_22,
+                GP_5_30_FN, FN_IP7_21_19,
+                GP_5_29_FN, FN_IP7_18_16,
+                GP_5_28_FN, FN_DU_DOTCLKIN2,
+                GP_5_27_FN, FN_IP7_26_25,
+                GP_5_26_FN, FN_DU_DOTCLKIN0,
+                GP_5_25_FN, FN_AVS2,
+                GP_5_24_FN, FN_AVS1,
+                GP_5_23_FN, FN_USB2_OVC,
+                GP_5_22_FN, FN_USB2_PWEN,
+                GP_5_21_FN, FN_IP16_7,
+                GP_5_20_FN, FN_IP16_6,
+                GP_5_19_FN, FN_USB0_OVC_VBUS,
+                GP_5_18_FN, FN_USB0_PWEN,
+                GP_5_17_FN, FN_IP16_5_3,
+                GP_5_16_FN, FN_IP16_2_0,
+                GP_5_15_FN, FN_IP15_29_28,
+                GP_5_14_FN, FN_IP15_27_26,
+                GP_5_13_FN, FN_IP15_25_23,
+                GP_5_12_FN, FN_IP15_22_20,
+                GP_5_11_FN, FN_IP15_19_18,
+                GP_5_10_FN, FN_IP15_17_16,
+                GP_5_9_FN, FN_IP15_15_14,
+                GP_5_8_FN, FN_IP15_13_12,
+                GP_5_7_FN, FN_IP15_11_9,
+                GP_5_6_FN, FN_IP15_8_6,
+                GP_5_5_FN, FN_IP15_5_3,
+                GP_5_4_FN, FN_IP15_2_0,
+                GP_5_3_FN, FN_IP14_30_28,
+                GP_5_2_FN, FN_IP14_27_25,
+                GP_5_1_FN, FN_IP14_24_22,
+                GP_5_0_FN, FN_IP14_21_19 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+                             1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
+                /* IP0_31 [1] */
+                0, 0,
+                /* IP0_30_27 [4] */
+                FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
+                FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_26_23 [4] */
+                FN_D7, FN_AD_DI_B, FN_SDA2_C,
+                FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_22_20 [3] */
+                FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+                FN_SCL2_CIS_C, 0, 0,
+                /* IP0_19_16 [4] */
+                FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+                FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_15_12 [4] */
+                FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+                FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_11_9 [3] */
+                FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
+                0, 0, 0,
+                /* IP0_8_6 [3] */
+                FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
+                0, 0, 0,
+                /* IP0_5_3 [3] */
+                FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
+                0, 0, 0,
+                /* IP0_2_0 [3] */
+                FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+                0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
+                             2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
+                /* IP1_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP1_29_28 [2] */
+                FN_A1, FN_PWM4, 0, 0,
+                /* IP1_27_26 [2] */
+                FN_A0, FN_PWM3, 0, 0,
+                /* IP1_25_22 [4] */
+                FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+                FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_21_18 [4] */
+                FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+                FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_17_15 [3] */
+                FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+                FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
+                0, 0, 0,
+                /* IP1_14_12 [3] */
+                FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+                FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+                0, 0,
+                /* IP1_11_8 [4] */
+                FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
+                FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_7_4 [4] */
+                FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
+                FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_3_0 [4] */
+                FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
+                FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
+                             3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
+                /* IP2_31_29 [3] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_28_26 [3] */
+                FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+                FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
+                /* IP2_25_22 [4] */
+                FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+                FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_21_18 [4] */
+                FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+                FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_17_15 [3] */
+                FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+                0, 0, 0, 0,
+                /* IP2_14_12 [3] */
+                FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
+                /* IP2_11_9 [3] */
+                FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
+                /* IP2_8_6 [3] */
+                FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
+                /* IP2_5_3 [3] */
+                FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
+                /* IP2_2_0 [3] */
+                FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
+                             3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
+                /* IP3_31_29 [3] */
+                FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+                0, 0, 0,
+                /* IP3_28_26 [3] */
+                FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
+                0, 0, 0, 0,
+                /* IP3_25_23 [3] */
+                FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
+                /* IP3_22_20 [3] */
+                FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
+                /* IP3_19_18 [2] */
+                FN_A16, FN_ATAWR1_N, 0, 0,
+                /* IP3_17_15 [3] */
+                FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
+                0, 0, 0, 0,
+                /* IP3_14_12 [3] */
+                FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
+                0, 0, 0, 0,
+                /* IP3_11_8 [4] */
+                FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+                FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+                FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP3_7_4 [4] */
+                FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+                FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP3_3_0 [4] */
+                FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+                FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
+                             2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+                /* IP4_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP4_29_27 [3] */
+                FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+                FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
+                /* IP4_26_24 [3] */
+                FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
+                FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
+                /* IP4_23_21 [3] */
+                FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
+                FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
+                /* IP4_20_18 [3] */
+                FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+                FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
+                /* IP4_17_15 [3] */
+                FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+                0, 0, 0,
+                /* IP4_14_12 [3] */
+                FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
+                FN_VI2_FIELD_B, 0, 0,
+                /* IP4_11_9 [3] */
+                FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+                FN_VI2_CLKENB_B, 0, 0,
+                /* IP4_8_6 [3] */
+                FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
+                /* IP4_5_3 [3] */
+                FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
+                /* IP4_2_0 [3] */
+                FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
+                             2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
+                /* IP5_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP5_29_27 [3] */
+                FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
+                FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
+                /* IP5_26_24 [3] */
+                FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+                FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+                FN_MSIOF0_SCK_B, 0,
+                /* IP5_23_21 [3] */
+                FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+                FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
+                FN_IERX_C, 0,
+                /* IP5_20_18 [3] */
+                FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+                FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
+                /* IP5_17_15 [3] */
+                FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+                FN_INTC_IRQ4_N, 0, 0,
+                /* IP5_14_13 [2] */
+                FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
+                /* IP5_12_10 [3] */
+                FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
+                0, 0,
+                /* IP5_9_6 [4] */
+                FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
+                FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
+                FN_SDA1_CIS, 0, 0, 0, 0, 0, 0,
+                /* IP5_5_3 [3] */
+                FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+                FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
+                FN_INTC_EN0_N, FN_SCL1_CIS,
+                /* IP5_2_0 [3] */
+                FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+                FN_VI2_R3, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+                             3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+                /* IP6_31_29 [3] */
+                FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+                FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
+                /* IP6_28_26 [3] */
+                FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+                FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
+                /* IP6_25_23 [3] */
+                FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+                FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
+                /* IP6_22_20 [3] */
+                FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
+                FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
+                /* IP6_19_17 [3] */
+                FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
+                FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
+                /* IP6_16_14 [3] */
+                FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+                FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+                FN_SCL2_CIS_E, 0,
+                /* IP6_13_11 [3] */
+                FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+                FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+                /* IP6_10_9 [2] */
+                FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
+                /* IP6_8_6 [3] */
+                FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
+                FN_SSI_SDATA8_C, 0, 0, 0,
+                /* IP6_5_3 [3] */
+                FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+                FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
+                /* IP6_2_0 [3] */
+                FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+                FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+                             1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+                /* IP7_31 [1] */
+                0, 0,
+                /* IP7_30_29 [2] */
+                FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+                FN_MII_RXD2,
+                /* IP7_28_27 [2] */
+                FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+                /* IP7_26_25 [2] */
+                FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
+                /* IP7_24_22 [3] */
+                FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
+                0, 0, 0,
+                /* IP7_21_19 [3] */
+                FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
+                FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
+                /* IP7_18_16 [3] */
+                FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+                FN_GLO_SS_C, 0, 0, 0,
+                /* IP7_15_13 [3] */
+                FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+                FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
+                /* IP7_12_10 [3] */
+                FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
+                FN_GLO_SCLK_C, 0, 0, 0,
+                /* IP7_9_8 [2] */
+                FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
+                /* IP7_7_6 [2] */
+                FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
+                /* IP7_5_3 [3] */
+                FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+                0, 0, 0,
+                /* IP7_2_0 [3] */
+                FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+                FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+                             1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
+                             2, 2, 2, 2, 2, 2, 2) {
+                /* IP8_31 [1] */
+                0, 0,
+                /* IP8_30_29 [2] */
+                FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
+                /* IP8_28 [1] */
+                FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
+                /* IP8_27 [1] */
+                FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+                /* IP8_26 [1] */
+                FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
+                /* IP8_25_24 [2] */
+                FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+                FN_AVB_MAGIC, FN_MII_MAGIC,
+                /* IP8_23_22 [2] */
+                FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
+                /* IP8_21_20 [2] */
+                FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+                FN_MII_MDIO,
+                /* IP8_19_18 [2] */
+                FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+                /* IP8_17_16 [2] */
+                FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
+                /* IP8_15_14 [2] */
+                FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
+                /* IP8_13_12 [2] */
+                FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
+                /* IP8_11_10 [2] */
+                FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
+                /* IP8_9_8 [2] */
+                FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
+                /* IP8_7_6 [2] */
+                FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
+                /* IP8_5_4 [2] */
+                FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
+                /* IP8_3_2 [2] */
+                FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
+                /* IP8_1_0 [2] */
+                FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+                             4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
+                /* IP9_31_28 [4] */
+                FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
+                FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
+                FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
+                /* IP9_27_26 [2] */
+                FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
+                /* IP9_25_24 [2] */
+                FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+                /* IP9_23_22 [2] */
+                FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
+                /* IP9_21_20 [2] */
+                FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
+                /* IP9_19_18 [2] */
+                FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+                /* IP9_17_16 [2] */
+                FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
+                /* IP9_15_12 [4] */
+                FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+                FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+                FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_11_8 [4] */
+                FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+                FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+                FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_7_6 [2] */
+                FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
+                /* IP9_5_4 [2] */
+                FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
+                /* IP9_3_2 [2] */
+                FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
+                /* IP9_1_0 [2] */
+                FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+                             2, 4, 3, 4, 4, 4, 4, 3, 4) {
+                /* IP10_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP10_29_26 [4] */
+                FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+                FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+                FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
+                /* IP10_25_23 [3] */
+                FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+                FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
+                /* IP10_22_19 [4] */
+                FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+                FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+                FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP10_18_15 [4] */
+                FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+                FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+                FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+                0, 0, 0, 0, 0, 0,
+                /* IP10_14_11 [4] */
+                FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+                FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+                FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP10_10_7 [4] */
+                FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+                FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+                FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP10_6_4 [3] */
+                FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+                FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+                FN_VI3_DATA0_B, 0,
+                /* IP10_3_0 [4] */
+                FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+                FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+                FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+                             2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
+                /* IP11_31_30 [2] */
+                FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
+                /* IP11_29_27 [3] */
+                FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+                FN_RDS_CLK_B, 0, 0,
+                /* IP11_26_24 [3] */
+                FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
+                0, 0, 0,
+                /* IP11_23_22 [2] */
+                FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
+                /* IP11_21_18 [4] */
+                FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+                FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+                FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
+                /* IP11_17_15 [3] */
+                FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+                FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
+                /* IP11_14_13 [2] */
+                FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
+                /* IP11_12_11 [2] */
+                FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
+                /* IP11_10_9 [2] */
+                FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
+                /* IP11_8_7 [2] */
+                FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
+                /* IP11_6_5 [2] */
+                FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
+                /* IP11_4 [1] */
+                FN_SD3_CLK, FN_MMC1_CLK,
+                /* IP11_3_0 [4] */
+                FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+                FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+                FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+                             1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+                /* IP12_31 [1] */
+                0, 0,
+                /* IP12_30_28 [3] */
+                FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
+                FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+                FN_CAN_DEBUGOUT4, 0, 0,
+                /* IP12_27_25 [3] */
+                FN_SSI_SCK5, FN_SCIFB1_SCK,
+                FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+                FN_CAN_DEBUGOUT3, 0, 0,
+                /* IP12_24_23 [2] */
+                FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+                FN_CAN_DEBUGOUT2,
+                /* IP12_22_20 [3] */
+                FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+                FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
+                /* IP12_19_17 [3] */
+                FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+                FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
+                /* IP12_16_14 [3] */
+                FN_SSI_SDATA3, FN_STP_ISCLK_0,
+                FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
+                /* IP12_13_11 [3] */
+                FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+                FN_CAN_STEP0, 0, 0, 0,
+                /* IP12_10_8 [3] */
+                FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+                FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
+                /* IP12_7_6 [2] */
+                FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+                /* IP12_5_4 [2] */
+                FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
+                /* IP12_3_2 [2] */
+                FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
+                /* IP12_1_0 [2] */
+                FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
+                             1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
+                /* IP13_31 [1] */
+                0, 0,
+                /* IP13_30_29 [2] */
+                FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
+                /* IP13_28_26 [3] */
+                FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+                FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
+                /* IP13_25_23 [3] */
+                FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+                FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
+                /* IP13_22_19 [4] */
+                FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+                FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
+                FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F,
+                0, 0, 0, 0,
+                /* IP13_18_16 [3] */
+                FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
+                FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
+                /* IP13_15_13 [3] */
+                FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
+                FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
+                /* IP13_12_10 [3] */
+                FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
+                FN_CAN_DEBUGOUT8, 0, 0,
+                /* IP13_9_7 [3] */
+                FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+                FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
+                /* IP13_6_3 [4] */
+                FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
+                FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+                FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0,
+                /* IP13_2_0 [3] */
+                FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+                FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
+                             1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
+                /* IP14_30 [1] */
+                0, 0,
+                /* IP14_30_28 [3] */
+                FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
+                FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+                FN_HRTS0_N_C, 0,
+                /* IP14_27_25 [3] */
+                FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
+                FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
+                /* IP14_24_22 [3] */
+                FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+                FN_LCDOUT9, 0, 0, 0,
+                /* IP14_21_19 [3] */
+                FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+                FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
+                /* IP14_18_16 [3] */
+                FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
+                FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
+                /* IP14_15_12 [4] */
+                FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
+                FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP14_11_9 [3] */
+                FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
+                0, 0, 0,
+                /* IP14_8_6 [3] */
+                FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
+                0, 0, 0,
+                /* IP14_5_3 [3] */
+                FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
+                FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C,
+                /* IP14_2_0 [3] */
+                FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+                FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+                FN_REMOCON, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
+                             2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
+                /* IP15_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP15_29_28 [2] */
+                FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
+                /* IP15_27_26 [2] */
+                FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
+                /* IP15_25_23 [3] */
+                FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
+                FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0,
+                /* IP15_22_20 [3] */
+                FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+                FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
+                /* IP15_19_18 [2] */
+                FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
+                /* IP15_17_16 [2] */
+                FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
+                /* IP15_15_14 [2] */
+                FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
+                /* IP15_13_12 [2] */
+                FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
+                /* IP15_11_9 [3] */
+                FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
+                0, 0, 0,
+                /* IP15_8_6 [3] */
+                FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17,
+                FN_SDA2, FN_SDA2_CIS, 0,
+                /* IP15_5_3 [3] */
+                FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16,
+                FN_SCL2, FN_SCL2_CIS, 0,
+                /* IP15_2_0 [3] */
+                FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7,
+                FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
+                             4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
+                /* IP16_31_28 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_27_24 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_23_20 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_19_16 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_15_12 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_11_8 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_7 [1] */
+                FN_USB1_OVC, FN_TCLK1_B,
+                /* IP16_6 [1] */
+                FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
+                /* IP16_5_3 [3] */
+                FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+                FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0,
+                /* IP16_2_0 [3] */
+                FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+                FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+                             3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
+                             2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
+                /* SEL_SCIF1 [3] */
+                FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+                FN_SEL_SCIF1_4, 0, 0, 0,
+                /* SEL_SCIFB [2] */
+                FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
+                /* SEL_SCIFB2 [2] */
+                FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
+                /* SEL_SCIFB1 [3] */
+                FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
+                FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
+                FN_SEL_SCIFB1_6, 0,
+                /* SEL_SCIFA1 [2] */
+                FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+                FN_SEL_SCIFA1_3,
+                /* SEL_SCIF0 [1] */
+                FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+                /* SEL_SCIFA [1] */
+                FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+                /* SEL_SOF1 [1] */
+                FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+                /* SEL_SSI7 [2] */
+                FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
+                /* SEL_SSI6 [1] */
+                FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+                /* SEL_SSI5 [2] */
+                FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
+                /* SEL_VI3 [1] */
+                FN_SEL_VI3_0, FN_SEL_VI3_1,
+                /* SEL_VI2 [1] */
+                FN_SEL_VI2_0, FN_SEL_VI2_1,
+                /* SEL_VI1 [1] */
+                FN_SEL_VI1_0, FN_SEL_VI1_1,
+                /* SEL_VI0 [1] */
+                FN_SEL_VI0_0, FN_SEL_VI0_1,
+                /* SEL_TSIF1 [2] */
+                FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_LBS [1] */
+                FN_SEL_LBS_0, FN_SEL_LBS_1,
+                /* SEL_TSIF0 [2] */
+                FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+                /* SEL_SOF3 [1] */
+                FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+                /* SEL_SOF0 [1] */
+                FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+                             3, 1, 1, 1, 2, 1, 2, 1, 2,
+                             1, 1, 1, 3, 3, 2, 3, 2, 2) {
+                /* RESERVED [3] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* SEL_TMU1 [1] */
+                FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+                /* SEL_HSCIF1 [1] */
+                FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+                /* SEL_SCIFCLK [1] */
+                FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+                /* SEL_CAN0 [2] */
+                FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+                /* SEL_CANCLK [1] */
+                FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+                /* SEL_SCIFA2 [2] */
+                FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
+                /* SEL_CAN1 [1] */
+                FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
+                0, 0,
+                /* SEL_ADI [1] */
+                FN_SEL_ADI_0, FN_SEL_ADI_1,
+                /* SEL_SSP [1] */
+                FN_SEL_SSP_0, FN_SEL_SSP_1,
+                /* SEL_FM [3] */
+                FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+                FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
+                /* SEL_HSCIF0 [3] */
+                FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+                FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
+                /* SEL_GPS [2] */
+                FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
+                /* SEL_RDS [3] */
+                FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+                FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
+                /* SEL_SIM [2] */
+                FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
+                /* SEL_SSI8 [2] */
+                FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+                             1, 1, 2, 4, 4, 2, 2,
+                             4, 2, 3, 2, 3, 2) {
+                /* SEL_IICDVFS [1] */
+                FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+                /* SEL_IIC0 [1] */
+                FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_IEB [2] */
+                FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_IIC2 [3] */
+                FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+                FN_SEL_IIC2_4, 0, 0, 0,
+                /* SEL_IIC1 [2] */
+                FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
+                /* SEL_I2C2 [3] */
+                FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+                FN_SEL_I2C2_4, 0, 0, 0,
+                /* SEL_I2C1 [2] */
+                FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
+        },
+        { },
+};
+
+const struct sh_pfc_soc_info r8a7790_pinmux_info = {
+        .name = "r8a77900_pfc",
+        .unlock_reg = 0xe6060000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index df0ae21a5ac8..6dfb18772574 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -20,10 +20,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -34,6 +38,35 @@
         PORT_10(fn, pfx##16, sfx),      PORT_10(fn, pfx##17, sfx), \
         PORT_10(fn, pfx##18, sfx),      PORT_1(fn, pfx##190, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)                                           \
+        [gpio] = {                                                      \
+                .name = __stringify(PORT##gpio),                        \
+                .enum_id = PORT##gpio##_DATA,                           \
+        }
+
+#define IRQC_PIN_MUX(irq, pin)                                          \
+static const unsigned int intc_irq##irq##_pins[] = {                    \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_mux[] = {                     \
+        IRQ##irq##_MARK,                                                \
+}
+
+#define IRQC_PINS_MUX(irq, pin0, pin1)                                  \
+static const unsigned int intc_irq##irq##_0_pins[] = {                  \
+        pin0,                                                           \
+};                                                                      \
+static const unsigned int intc_irq##irq##_0_mux[] = {                   \
+        IRQ##irq##_##pin0##_MARK,                                       \
+};                                                                      \
+static const unsigned int intc_irq##irq##_1_pins[] = {                  \
+        pin1,                                                           \
+};                                                                      \
+static const unsigned int intc_irq##irq##_1_mux[] = {                   \
+        IRQ##irq##_##pin1##_MARK,                                       \
+}
+
 enum {
         PINMUX_RESERVED = 0,
 
@@ -47,16 +80,6 @@ enum {
         PORT_ALL(IN),
         PINMUX_INPUT_END,
 
-        /* PORT0_IN_PU -> PORT190_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-
-        /* PORT0_IN_PD -> PORT190_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-
         /* PORT0_OUT -> PORT190_OUT */
         PINMUX_OUTPUT_BEGIN,
         PORT_ALL(OUT),
@@ -368,124 +391,11 @@ enum {
         PINMUX_MARK_END,
 };
 
-static const pinmux_enum_t pinmux_data[] = {
+#define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
 
-        /* specify valid pin states for each pin in GPIO mode */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_O(2),                 PORT_DATA_I_PD(3),
-        PORT_DATA_I_PD(4),              PORT_DATA_I_PD(5),
-        PORT_DATA_IO_PU_PD(6),          PORT_DATA_I_PD(7),
-        PORT_DATA_IO_PD(8),             PORT_DATA_O(9),
-
-        PORT_DATA_O(10),                PORT_DATA_O(11),
-        PORT_DATA_IO_PU_PD(12),         PORT_DATA_IO_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_O(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_I_PD(18),             PORT_DATA_IO(19),
-
-        PORT_DATA_IO(20),               PORT_DATA_IO(21),
-        PORT_DATA_IO(22),               PORT_DATA_IO(23),
-        PORT_DATA_IO(24),               PORT_DATA_IO(25),
-        PORT_DATA_IO(26),               PORT_DATA_IO(27),
-        PORT_DATA_IO(28),               PORT_DATA_IO(29),
-
-        PORT_DATA_IO(30),               PORT_DATA_IO(31),
-        PORT_DATA_IO(32),               PORT_DATA_IO(33),
-        PORT_DATA_IO(34),               PORT_DATA_IO(35),
-        PORT_DATA_IO(36),               PORT_DATA_IO(37),
-        PORT_DATA_IO(38),               PORT_DATA_IO(39),
-
-        PORT_DATA_IO(40),               PORT_DATA_IO(41),
-        PORT_DATA_IO(42),               PORT_DATA_IO(43),
-        PORT_DATA_IO(44),               PORT_DATA_IO(45),
-        PORT_DATA_IO_PU(46),            PORT_DATA_IO_PU(47),
-        PORT_DATA_IO_PU(48),            PORT_DATA_IO_PU(49),
-
-        PORT_DATA_IO_PU(50),            PORT_DATA_IO_PU(51),
-        PORT_DATA_IO_PU(52),            PORT_DATA_IO_PU(53),
-        PORT_DATA_IO_PU(54),            PORT_DATA_IO_PU(55),
-        PORT_DATA_IO_PU(56),            PORT_DATA_IO_PU(57),
-        PORT_DATA_IO_PU(58),            PORT_DATA_IO_PU(59),
-
-        PORT_DATA_IO_PU(60),            PORT_DATA_IO_PU(61),
-        PORT_DATA_IO(62),               PORT_DATA_O(63),
-        PORT_DATA_O(64),                PORT_DATA_IO_PU(65),
-        PORT_DATA_O(66),                PORT_DATA_IO_PU(67),  /*66?*/
-        PORT_DATA_O(68),                PORT_DATA_IO(69),
-
-        PORT_DATA_IO(70),               PORT_DATA_IO(71),
-        PORT_DATA_O(72),                PORT_DATA_I_PU(73),
-        PORT_DATA_I_PU_PD(74),          PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO_PU_PD(82),         PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO_PU_PD(84),         PORT_DATA_IO_PU_PD(85),
-        PORT_DATA_IO_PU_PD(86),         PORT_DATA_IO_PU_PD(87),
-        PORT_DATA_IO_PU_PD(88),         PORT_DATA_IO_PU_PD(89),
-
-        PORT_DATA_IO_PU_PD(90),         PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU(96),            PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_O(99), /*99?*/
-
-        PORT_DATA_IO_PD(100),           PORT_DATA_IO_PD(101),
-        PORT_DATA_IO_PD(102),           PORT_DATA_IO_PD(103),
-        PORT_DATA_IO_PD(104),           PORT_DATA_IO_PD(105),
-        PORT_DATA_IO_PU(106),           PORT_DATA_IO_PU(107),
-        PORT_DATA_IO_PU(108),           PORT_DATA_IO_PU(109),
-
-        PORT_DATA_IO_PU(110),           PORT_DATA_IO_PU(111),
-        PORT_DATA_IO_PD(112),           PORT_DATA_IO_PD(113),
-        PORT_DATA_IO_PU(114),           PORT_DATA_IO_PU(115),
-        PORT_DATA_IO_PU(116),           PORT_DATA_IO_PU(117),
-        PORT_DATA_IO_PU(118),           PORT_DATA_IO_PU(119),
-
-        PORT_DATA_IO_PU(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO_PD(125),
-        PORT_DATA_IO_PD(126),           PORT_DATA_IO_PD(127),
-        PORT_DATA_IO_PD(128),           PORT_DATA_IO_PU_PD(129),
-
-        PORT_DATA_IO_PU_PD(130),        PORT_DATA_IO_PU_PD(131),
-        PORT_DATA_IO_PU_PD(132),        PORT_DATA_IO_PU_PD(133),
-        PORT_DATA_IO_PU_PD(134),        PORT_DATA_IO_PU_PD(135),
-        PORT_DATA_IO_PD(136),           PORT_DATA_IO_PD(137),
-        PORT_DATA_IO_PD(138),           PORT_DATA_IO_PD(139),
-
-        PORT_DATA_IO_PD(140),           PORT_DATA_IO_PD(141),
-        PORT_DATA_IO_PD(142),           PORT_DATA_IO_PU_PD(143),
-        PORT_DATA_IO_PD(144),           PORT_DATA_IO_PD(145),
-        PORT_DATA_IO_PD(146),           PORT_DATA_IO_PD(147),
-        PORT_DATA_IO_PD(148),           PORT_DATA_IO_PD(149),
-
-        PORT_DATA_IO_PD(150),           PORT_DATA_IO_PD(151),
-        PORT_DATA_IO_PU_PD(152),        PORT_DATA_I_PD(153),
-        PORT_DATA_IO_PU_PD(154),        PORT_DATA_I_PD(155),
-        PORT_DATA_IO_PD(156),           PORT_DATA_IO_PD(157),
-        PORT_DATA_I_PD(158),            PORT_DATA_IO_PD(159),
-
-        PORT_DATA_O(160),               PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_I_PD(164),            PORT_DATA_IO_PD(165),
-        PORT_DATA_I_PD(166),            PORT_DATA_I_PD(167),
-        PORT_DATA_I_PD(168),            PORT_DATA_I_PD(169),
-
-        PORT_DATA_I_PD(170),            PORT_DATA_O(171),
-        PORT_DATA_IO_PU_PD(172),        PORT_DATA_IO_PU_PD(173),
-        PORT_DATA_IO_PU_PD(174),        PORT_DATA_IO_PU_PD(175),
-        PORT_DATA_IO_PU_PD(176),        PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU_PD(178),        PORT_DATA_O(179),
-
-        PORT_DATA_IO_PU_PD(180),        PORT_DATA_IO_PU_PD(181),
-        PORT_DATA_IO_PU_PD(182),        PORT_DATA_IO_PU_PD(183),
-        PORT_DATA_IO_PU_PD(184),        PORT_DATA_O(185),
-        PORT_DATA_IO_PU_PD(186),        PORT_DATA_IO_PU_PD(187),
-        PORT_DATA_IO_PU_PD(188),        PORT_DATA_IO_PU_PD(189),
-
-        PORT_DATA_IO_PU_PD(190),
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(),
 
         /* IRQ */
         PINMUX_DATA(IRQ0_6_MARK,        PORT6_FN0,      MSEL1CR_0_0),
@@ -929,10 +839,582 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(MFIv4_MARK,         MSEL4CR_6_1),
 };
 
+#define SH7372_PIN(pin, cfgs)                                           \
+        {                                                               \
+                .name = __stringify(PORT##pin),                         \
+                .enum_id = PORT##pin##_DATA,                            \
+                .configs = cfgs,                                        \
+        }
+
+#define __I             (SH_PFC_PIN_CFG_INPUT)
+#define __O             (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU            (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define SH7372_PIN_I_PD(pin)            SH7372_PIN(pin, __I | __PD)
+#define SH7372_PIN_I_PU(pin)            SH7372_PIN(pin, __I | __PU)
+#define SH7372_PIN_I_PU_PD(pin)         SH7372_PIN(pin, __I | __PUD)
+#define SH7372_PIN_IO(pin)              SH7372_PIN(pin, __IO)
+#define SH7372_PIN_IO_PD(pin)           SH7372_PIN(pin, __IO | __PD)
+#define SH7372_PIN_IO_PU(pin)           SH7372_PIN(pin, __IO | __PU)
+#define SH7372_PIN_IO_PU_PD(pin)        SH7372_PIN(pin, __IO | __PUD)
+#define SH7372_PIN_O(pin)               SH7372_PIN(pin, __O)
+#define SH7372_PIN_O_PU_PD(pin)         SH7372_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-        GPIO_PORT_ALL(),
+        /* Table 57-1 (I/O and Pull U/D) */
+        SH7372_PIN_IO_PD(0),            SH7372_PIN_IO_PD(1),
+        SH7372_PIN_O(2),                SH7372_PIN_I_PD(3),
+        SH7372_PIN_I_PD(4),             SH7372_PIN_I_PD(5),
+        SH7372_PIN_IO_PU_PD(6),         SH7372_PIN_I_PD(7),
+        SH7372_PIN_IO_PD(8),            SH7372_PIN_O(9),
+        SH7372_PIN_O(10),               SH7372_PIN_O(11),
+        SH7372_PIN_IO_PU_PD(12),        SH7372_PIN_IO_PD(13),
+        SH7372_PIN_IO_PD(14),           SH7372_PIN_O(15),
+        SH7372_PIN_IO_PD(16),           SH7372_PIN_IO_PD(17),
+        SH7372_PIN_I_PD(18),            SH7372_PIN_IO(19),
+        SH7372_PIN_IO(20),              SH7372_PIN_IO(21),
+        SH7372_PIN_IO(22),              SH7372_PIN_IO(23),
+        SH7372_PIN_IO(24),              SH7372_PIN_IO(25),
+        SH7372_PIN_IO(26),              SH7372_PIN_IO(27),
+        SH7372_PIN_IO(28),              SH7372_PIN_IO(29),
+        SH7372_PIN_IO(30),              SH7372_PIN_IO(31),
+        SH7372_PIN_IO(32),              SH7372_PIN_IO(33),
+        SH7372_PIN_IO(34),              SH7372_PIN_IO(35),
+        SH7372_PIN_IO(36),              SH7372_PIN_IO(37),
+        SH7372_PIN_IO(38),              SH7372_PIN_IO(39),
+        SH7372_PIN_IO(40),              SH7372_PIN_IO(41),
+        SH7372_PIN_IO(42),              SH7372_PIN_IO(43),
+        SH7372_PIN_IO(44),              SH7372_PIN_IO(45),
+        SH7372_PIN_IO_PU(46),           SH7372_PIN_IO_PU(47),
+        SH7372_PIN_IO_PU(48),           SH7372_PIN_IO_PU(49),
+        SH7372_PIN_IO_PU(50),           SH7372_PIN_IO_PU(51),
+        SH7372_PIN_IO_PU(52),           SH7372_PIN_IO_PU(53),
+        SH7372_PIN_IO_PU(54),           SH7372_PIN_IO_PU(55),
+        SH7372_PIN_IO_PU(56),           SH7372_PIN_IO_PU(57),
+        SH7372_PIN_IO_PU(58),           SH7372_PIN_IO_PU(59),
+        SH7372_PIN_IO_PU(60),           SH7372_PIN_IO_PU(61),
+        SH7372_PIN_IO(62),              SH7372_PIN_O(63),
+        SH7372_PIN_O(64),               SH7372_PIN_IO_PU(65),
+        SH7372_PIN_O_PU_PD(66),         SH7372_PIN_IO_PU(67),
+        SH7372_PIN_O(68),               SH7372_PIN_IO(69),
+        SH7372_PIN_IO(70),              SH7372_PIN_IO(71),
+        SH7372_PIN_O(72),               SH7372_PIN_I_PU(73),
+        SH7372_PIN_I_PU_PD(74),         SH7372_PIN_IO_PU_PD(75),
+        SH7372_PIN_IO_PU_PD(76),        SH7372_PIN_IO_PU_PD(77),
+        SH7372_PIN_IO_PU_PD(78),        SH7372_PIN_IO_PU_PD(79),
+        SH7372_PIN_IO_PU_PD(80),        SH7372_PIN_IO_PU_PD(81),
+        SH7372_PIN_IO_PU_PD(82),        SH7372_PIN_IO_PU_PD(83),
+        SH7372_PIN_IO_PU_PD(84),        SH7372_PIN_IO_PU_PD(85),
+        SH7372_PIN_IO_PU_PD(86),        SH7372_PIN_IO_PU_PD(87),
+        SH7372_PIN_IO_PU_PD(88),        SH7372_PIN_IO_PU_PD(89),
+        SH7372_PIN_IO_PU_PD(90),        SH7372_PIN_IO_PU_PD(91),
+        SH7372_PIN_IO_PU_PD(92),        SH7372_PIN_IO_PU_PD(93),
+        SH7372_PIN_IO_PU_PD(94),        SH7372_PIN_IO_PU_PD(95),
+        SH7372_PIN_IO_PU(96),           SH7372_PIN_IO_PU_PD(97),
+        SH7372_PIN_IO_PU_PD(98),        SH7372_PIN_O_PU_PD(99),
+        SH7372_PIN_IO_PD(100),          SH7372_PIN_IO_PD(101),
+        SH7372_PIN_IO_PD(102),          SH7372_PIN_IO_PD(103),
+        SH7372_PIN_IO_PD(104),          SH7372_PIN_IO_PD(105),
+        SH7372_PIN_IO_PU(106),          SH7372_PIN_IO_PU(107),
+        SH7372_PIN_IO_PU(108),          SH7372_PIN_IO_PU(109),
+        SH7372_PIN_IO_PU(110),          SH7372_PIN_IO_PU(111),
+        SH7372_PIN_IO_PD(112),          SH7372_PIN_IO_PD(113),
+        SH7372_PIN_IO_PU(114),          SH7372_PIN_IO_PU(115),
+        SH7372_PIN_IO_PU(116),          SH7372_PIN_IO_PU(117),
+        SH7372_PIN_IO_PU(118),          SH7372_PIN_IO_PU(119),
+        SH7372_PIN_IO_PU(120),          SH7372_PIN_IO_PD(121),
+        SH7372_PIN_IO_PD(122),          SH7372_PIN_IO_PD(123),
+        SH7372_PIN_IO_PD(124),          SH7372_PIN_IO_PD(125),
+        SH7372_PIN_IO_PD(126),          SH7372_PIN_IO_PD(127),
+        SH7372_PIN_IO_PD(128),          SH7372_PIN_IO_PU_PD(129),
+        SH7372_PIN_IO_PU_PD(130),       SH7372_PIN_IO_PU_PD(131),
+        SH7372_PIN_IO_PU_PD(132),       SH7372_PIN_IO_PU_PD(133),
+        SH7372_PIN_IO_PU_PD(134),       SH7372_PIN_IO_PU_PD(135),
+        SH7372_PIN_IO_PD(136),          SH7372_PIN_IO_PD(137),
+        SH7372_PIN_IO_PD(138),          SH7372_PIN_IO_PD(139),
+        SH7372_PIN_IO_PD(140),          SH7372_PIN_IO_PD(141),
+        SH7372_PIN_IO_PD(142),          SH7372_PIN_IO_PU_PD(143),
+        SH7372_PIN_IO_PD(144),          SH7372_PIN_IO_PD(145),
+        SH7372_PIN_IO_PD(146),          SH7372_PIN_IO_PD(147),
+        SH7372_PIN_IO_PD(148),          SH7372_PIN_IO_PD(149),
+        SH7372_PIN_IO_PD(150),          SH7372_PIN_IO_PD(151),
+        SH7372_PIN_IO_PU_PD(152),       SH7372_PIN_I_PD(153),
+        SH7372_PIN_IO_PU_PD(154),       SH7372_PIN_I_PD(155),
+        SH7372_PIN_IO_PD(156),          SH7372_PIN_IO_PD(157),
+        SH7372_PIN_I_PD(158),           SH7372_PIN_IO_PD(159),
+        SH7372_PIN_O(160),              SH7372_PIN_IO_PD(161),
+        SH7372_PIN_IO_PD(162),          SH7372_PIN_IO_PD(163),
+        SH7372_PIN_I_PD(164),           SH7372_PIN_IO_PD(165),
+        SH7372_PIN_I_PD(166),           SH7372_PIN_I_PD(167),
+        SH7372_PIN_I_PD(168),           SH7372_PIN_I_PD(169),
+        SH7372_PIN_I_PD(170),           SH7372_PIN_O(171),
+        SH7372_PIN_IO_PU_PD(172),       SH7372_PIN_IO_PU_PD(173),
+        SH7372_PIN_IO_PU_PD(174),       SH7372_PIN_IO_PU_PD(175),
+        SH7372_PIN_IO_PU_PD(176),       SH7372_PIN_IO_PU_PD(177),
+        SH7372_PIN_IO_PU_PD(178),       SH7372_PIN_O(179),
+        SH7372_PIN_IO_PU_PD(180),       SH7372_PIN_IO_PU_PD(181),
+        SH7372_PIN_IO_PU_PD(182),       SH7372_PIN_IO_PU_PD(183),
+        SH7372_PIN_IO_PU_PD(184),       SH7372_PIN_O(185),
+        SH7372_PIN_IO_PU_PD(186),       SH7372_PIN_IO_PU_PD(187),
+        SH7372_PIN_IO_PU_PD(188),       SH7372_PIN_IO_PU_PD(189),
+        SH7372_PIN_IO_PU_PD(190),
 };
 
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+        /* D[0:7] */
+        46, 47, 48, 49, 50, 51, 52, 53,
+};
+static const unsigned int bsc_data8_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+        /* D[0:15] */
+        46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int bsc_data16_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+        /* CS */
+        62,
+};
+static const unsigned int bsc_cs0_mux[] = {
+        CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+        /* CS */
+        63,
+};
+static const unsigned int bsc_cs2_mux[] = {
+        CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+        /* CS */
+        64,
+};
+static const unsigned int bsc_cs4_mux[] = {
+        CS4_MARK,
+};
+static const unsigned int bsc_cs5a_pins[] = {
+        /* CS */
+        65,
+};
+static const unsigned int bsc_cs5a_mux[] = {
+        CS5A_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+        /* CS */
+        66,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+        CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+        /* CS */
+        67,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+        CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+        /* RD, WE[0] */
+        69, 70,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+        /* RD, WE[0:1] */
+        69, 70, 71,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+        /* BS */
+        19,
+};
+static const unsigned int bsc_bs_mux[] = {
+        BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+        /* RDWR */
+        75,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+        RDWR_MARK,
+};
+static const unsigned int bsc_wait_pins[] = {
+        /* WAIT */
+        74,
+};
+static const unsigned int bsc_wait_mux[] = {
+        WAIT_MARK,
+};
+/* - CEU -------------------------------------------------------------------- */
+static const unsigned int ceu_data_0_7_pins[] = {
+        /* D[0:7] */
+        102, 103, 104, 105, 106, 107, 108, 109,
+};
+static const unsigned int ceu_data_0_7_mux[] = {
+        VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
+        VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
+};
+static const unsigned int ceu_data_8_15_pins[] = {
+        /* D[8:15] */
+        110, 111, 112, 113, 114, 115, 116, 117,
+};
+static const unsigned int ceu_data_8_15_mux[] = {
+        VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
+        VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
+};
+static const unsigned int ceu_clk_0_pins[] = {
+        /* CKO */
+        120,
+};
+static const unsigned int ceu_clk_0_mux[] = {
+        VIO_CKO_MARK,
+};
+static const unsigned int ceu_clk_1_pins[] = {
+        /* CKO */
+        16,
+};
+static const unsigned int ceu_clk_1_mux[] = {
+        VIO_CKO1_MARK,
+};
+static const unsigned int ceu_clk_2_pins[] = {
+        /* CKO */
+        17,
+};
+static const unsigned int ceu_clk_2_mux[] = {
+        VIO_CKO2_MARK,
+};
+static const unsigned int ceu_sync_pins[] = {
+        /* CLK, VD, HD */
+        118, 100, 101,
+};
+static const unsigned int ceu_sync_mux[] = {
+        VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
+};
+static const unsigned int ceu_field_pins[] = {
+        /* FIELD */
+        119,
+};
+static const unsigned int ceu_field_mux[] = {
+        VIO_FIELD_MARK,
+};
+/* - FLCTL ------------------------------------------------------------------ */
+static const unsigned int flctl_data_pins[] = {
+        /* NAF[0:15] */
+        46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int flctl_data_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int flctl_ce0_pins[] = {
+        /* CE */
+        68,
+};
+static const unsigned int flctl_ce0_mux[] = {
+        FCE0_MARK,
+};
+static const unsigned int flctl_ce1_pins[] = {
+        /* CE */
+        66,
+};
+static const unsigned int flctl_ce1_mux[] = {
+        FCE1_MARK,
+};
+static const unsigned int flctl_ctrl_pins[] = {
+        /* FCDE, FOE, FSC, FWE, FRB */
+        24, 23, 69, 70, 73,
+};
+static const unsigned int flctl_ctrl_mux[] = {
+        A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+        /* CK */
+        4,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+        FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+        /* OMC */
+        8,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+        FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+        /* ILR, IBT */
+        5, 6,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+        FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+        /* OLR, OBT */
+        9, 10,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+        FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_pins[] = {
+        /* ISLD */
+        7,
+};
+static const unsigned int fsia_data_in_mux[] = {
+        FSIAISLD_MARK,
+};
+static const unsigned int fsia_data_out_pins[] = {
+        /* OSLD */
+        11,
+};
+static const unsigned int fsia_data_out_mux[] = {
+        FSIAOSLD_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+        /* SPDIF */
+        11,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+        FSIASPDIF_11_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+        /* SPDIF */
+        15,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+        FSIASPDIF_15_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+        /* CK */
+        4,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+        FSIBCK_MARK,
+};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+        /* HPD, CEC */
+        169, 170,
+};
+static const unsigned int hdmi_mux[] = {
+        HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 6, 162);
+IRQC_PIN_MUX(1, 12);
+IRQC_PINS_MUX(2, 4, 5);
+IRQC_PINS_MUX(3, 8, 16);
+IRQC_PINS_MUX(4, 17, 163);
+IRQC_PIN_MUX(5, 18);
+IRQC_PINS_MUX(6, 39, 164);
+IRQC_PINS_MUX(7, 40, 167);
+IRQC_PINS_MUX(8, 41, 168);
+IRQC_PINS_MUX(9, 42, 169);
+IRQC_PIN_MUX(10, 65);
+IRQC_PIN_MUX(11, 67);
+IRQC_PINS_MUX(12, 80, 137);
+IRQC_PINS_MUX(13, 81, 145);
+IRQC_PINS_MUX(14, 82, 146);
+IRQC_PINS_MUX(15, 83, 147);
+IRQC_PINS_MUX(16, 84, 170);
+IRQC_PIN_MUX(17, 85);
+IRQC_PIN_MUX(18, 86);
+IRQC_PIN_MUX(19, 87);
+IRQC_PIN_MUX(20, 92);
+IRQC_PIN_MUX(21, 93);
+IRQC_PIN_MUX(22, 94);
+IRQC_PIN_MUX(23, 95);
+IRQC_PIN_MUX(24, 112);
+IRQC_PIN_MUX(25, 119);
+IRQC_PINS_MUX(26, 121, 172);
+IRQC_PINS_MUX(27, 122, 180);
+IRQC_PINS_MUX(28, 123, 181);
+IRQC_PINS_MUX(29, 129, 182);
+IRQC_PINS_MUX(30, 130, 183);
+IRQC_PINS_MUX(31, 138, 184);
+/* - KEYSC ------------------------------------------------------------------ */
+static const unsigned int keysc_in04_0_pins[] = {
+        /* KEYIN[0:4] */
+        136, 135, 134, 133, 132,
+};
+static const unsigned int keysc_in04_0_mux[] = {
+        KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
+        KEYIN4_MARK,
+};
+static const unsigned int keysc_in04_1_pins[] = {
+        /* KEYIN[0:4] */
+        121, 122, 123, 124, 132,
+};
+static const unsigned int keysc_in04_1_mux[] = {
+        KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
+        KEYIN4_MARK,
+};
+static const unsigned int keysc_in5_pins[] = {
+        /* KEYIN5 */
+        131,
+};
+static const unsigned int keysc_in5_mux[] = {
+        KEYIN5_MARK,
+};
+static const unsigned int keysc_in6_pins[] = {
+        /* KEYIN6 */
+        130,
+};
+static const unsigned int keysc_in6_mux[] = {
+        KEYIN6_MARK,
+};
+static const unsigned int keysc_in7_pins[] = {
+        /* KEYIN7 */
+        129,
+};
+static const unsigned int keysc_in7_mux[] = {
+        KEYIN7_MARK,
+};
+static const unsigned int keysc_out4_pins[] = {
+        /* KEYOUT[0:3] */
+        128, 127, 126, 125,
+};
+static const unsigned int keysc_out4_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+};
+static const unsigned int keysc_out5_pins[] = {
+        /* KEYOUT[0:4] */
+        128, 127, 126, 125, 124,
+};
+static const unsigned int keysc_out5_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK,
+};
+static const unsigned int keysc_out6_pins[] = {
+        /* KEYOUT[0:5] */
+        128, 127, 126, 125, 124, 123,
+};
+static const unsigned int keysc_out6_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK, KEYOUT5_MARK,
+};
+static const unsigned int keysc_out8_pins[] = {
+        /* KEYOUT[0:7] */
+        128, 127, 126, 125, 124, 123, 122, 121,
+};
+static const unsigned int keysc_out8_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
+};
+/* - LCD -------------------------------------------------------------------- */
+static const unsigned int lcd_data8_pins[] = {
+        /* D[0:7] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+};
+static const unsigned int lcd_data8_mux[] = {
+        /* LCDC */
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+};
+static const unsigned int lcd_data9_pins[] = {
+        /* D[0:8] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129,
+        137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data9_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK,
+};
+static const unsigned int lcd_data12_pins[] = {
+        /* D[0:11] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132,
+};
+static const unsigned int lcd_data12_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+};
+static const unsigned int lcd_data16_pins[] = {
+        /* D[0:15] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+};
+static const unsigned int lcd_data16_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+};
+static const unsigned int lcd_data18_pins[] = {
+        /* D[0:17] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+        137, 138,
+};
+static const unsigned int lcd_data18_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK,
+};
+static const unsigned int lcd_data24_pins[] = {
+        /* D[0:23] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+        137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data24_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
+        LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
+};
+static const unsigned int lcd_display_pins[] = {
+        /* DON */
+        151,
+};
+static const unsigned int lcd_display_mux[] = {
+        LCDDON_MARK,
+};
+static const unsigned int lcd_lclk_pins[] = {
+        /* LCLK */
+        150,
+};
+static const unsigned int lcd_lclk_mux[] = {
+        LCDLCLK_MARK,
+};
+static const unsigned int lcd_sync_pins[] = {
+        /* VSYN, HSYN, DCK, DISP */
+        146, 145, 147, 149,
+};
+static const unsigned int lcd_sync_mux[] = {
+        LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
+};
+static const unsigned int lcd_sys_pins[] = {
+        /* CS, WR, RD, RS */
+        145, 147, 148, 149,
+};
+static const unsigned int lcd_sys_mux[] = {
+        LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
         /* D[0] */
@@ -993,6 +1475,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
         MMCCMD1_MARK, MMCCLK1_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        153, 152,
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        156,
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        157, 158,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        155, 154,
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        159,
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        160, 161,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        97, 96,
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+        /* SCK */
+        98,
+};
+static const unsigned int scifa2_clk_mux[] = {
+        SCIFA2_SCK1_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        95, 94,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+        /* RXD, TXD */
+        144, 143,
+};
+static const unsigned int scifa3_data_mux[] = {
+        SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_clk_pins[] = {
+        /* SCK */
+        142,
+};
+static const unsigned int scifa3_clk_mux[] = {
+        SCIFA3_SCK_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        44, 43,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+        SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        141, 140,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+        SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+        /* RXD, TXD */
+        5, 6,
+};
+static const unsigned int scifa4_data_mux[] = {
+        SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_pins[] = {
+        /* RXD, TXD */
+        8, 12,
+};
+static const unsigned int scifa5_data_mux[] = {
+        SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_pins[] = {
+        /* RXD, TXD */
+        166, 165,
+};
+static const unsigned int scifb_data_mux[] = {
+        SCIFB_RXD_MARK, SCIFB_TXD_MARK,
+};
+static const unsigned int scifb_clk_pins[] = {
+        /* SCK */
+        162,
+};
+static const unsigned int scifb_clk_mux[] = {
+        SCIFB_SCK_MARK,
+};
+static const unsigned int scifb_ctrl_pins[] = {
+        /* RTS, CTS */
+        163, 164,
+};
+static const unsigned int scifb_ctrl_mux[] = {
+        SCIFB_RTS_MARK, SCIFB_CTS_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
@@ -1073,8 +1688,169 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
         SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_vbus_pins[] = {
+        /* VBUS */
+        167,
+};
+static const unsigned int usb0_vbus_mux[] = {
+        VBUS0_0_MARK,
+};
+static const unsigned int usb0_otg_id_pins[] = {
+        /* IDIN */
+        113,
+};
+static const unsigned int usb0_otg_id_mux[] = {
+        IDIN_0_MARK,
+};
+static const unsigned int usb0_otg_ctrl_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        116, 114, 117, 115,
+};
+static const unsigned int usb0_otg_ctrl_mux[] = {
+        PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_vbus_pins[] = {
+        /* VBUS */
+        168,
+};
+static const unsigned int usb1_vbus_mux[] = {
+        VBUS0_1_MARK,
+};
+static const unsigned int usb1_otg_id_0_pins[] = {
+        /* IDIN */
+        113,
+};
+static const unsigned int usb1_otg_id_0_mux[] = {
+        IDIN_1_113_MARK,
+};
+static const unsigned int usb1_otg_id_1_pins[] = {
+        /* IDIN */
+        18,
+};
+static const unsigned int usb1_otg_id_1_mux[] = {
+        IDIN_1_18_MARK,
+};
+static const unsigned int usb1_otg_ctrl_0_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        115, 116, 114, 117, 113,
+};
+static const unsigned int usb1_otg_ctrl_0_mux[] = {
+        PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
+};
+static const unsigned int usb1_otg_ctrl_1_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        138, 116, 162, 117, 18,
+};
+static const unsigned int usb1_otg_ctrl_1_mux[] = {
+        PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(bsc_data8),
+        SH_PFC_PIN_GROUP(bsc_data16),
+        SH_PFC_PIN_GROUP(bsc_cs0),
+        SH_PFC_PIN_GROUP(bsc_cs2),
+        SH_PFC_PIN_GROUP(bsc_cs4),
+        SH_PFC_PIN_GROUP(bsc_cs5a),
+        SH_PFC_PIN_GROUP(bsc_cs5b),
+        SH_PFC_PIN_GROUP(bsc_cs6a),
+        SH_PFC_PIN_GROUP(bsc_rd_we8),
+        SH_PFC_PIN_GROUP(bsc_rd_we16),
+        SH_PFC_PIN_GROUP(bsc_bs),
+        SH_PFC_PIN_GROUP(bsc_rdwr),
+        SH_PFC_PIN_GROUP(ceu_data_0_7),
+        SH_PFC_PIN_GROUP(ceu_data_8_15),
+        SH_PFC_PIN_GROUP(ceu_clk_0),
+        SH_PFC_PIN_GROUP(ceu_clk_1),
+        SH_PFC_PIN_GROUP(ceu_clk_2),
+        SH_PFC_PIN_GROUP(ceu_sync),
+        SH_PFC_PIN_GROUP(ceu_field),
+        SH_PFC_PIN_GROUP(flctl_data),
+        SH_PFC_PIN_GROUP(flctl_ce0),
+        SH_PFC_PIN_GROUP(flctl_ce1),
+        SH_PFC_PIN_GROUP(flctl_ctrl),
+        SH_PFC_PIN_GROUP(fsia_mclk_in),
+        SH_PFC_PIN_GROUP(fsia_mclk_out),
+        SH_PFC_PIN_GROUP(fsia_sclk_in),
+        SH_PFC_PIN_GROUP(fsia_sclk_out),
+        SH_PFC_PIN_GROUP(fsia_data_in),
+        SH_PFC_PIN_GROUP(fsia_data_out),
+        SH_PFC_PIN_GROUP(fsia_spdif_0),
+        SH_PFC_PIN_GROUP(fsia_spdif_1),
+        SH_PFC_PIN_GROUP(fsib_mclk_in),
+        SH_PFC_PIN_GROUP(hdmi),
+        SH_PFC_PIN_GROUP(intc_irq0_0),
+        SH_PFC_PIN_GROUP(intc_irq0_1),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2_0),
+        SH_PFC_PIN_GROUP(intc_irq2_1),
+        SH_PFC_PIN_GROUP(intc_irq3_0),
+        SH_PFC_PIN_GROUP(intc_irq3_1),
+        SH_PFC_PIN_GROUP(intc_irq4_0),
+        SH_PFC_PIN_GROUP(intc_irq4_1),
+        SH_PFC_PIN_GROUP(intc_irq5),
+        SH_PFC_PIN_GROUP(intc_irq6_0),
+        SH_PFC_PIN_GROUP(intc_irq6_1),
+        SH_PFC_PIN_GROUP(intc_irq7_0),
+        SH_PFC_PIN_GROUP(intc_irq7_1),
+        SH_PFC_PIN_GROUP(intc_irq8_0),
+        SH_PFC_PIN_GROUP(intc_irq8_1),
+        SH_PFC_PIN_GROUP(intc_irq9_0),
+        SH_PFC_PIN_GROUP(intc_irq9_1),
+        SH_PFC_PIN_GROUP(intc_irq10),
+        SH_PFC_PIN_GROUP(intc_irq11),
+        SH_PFC_PIN_GROUP(intc_irq12_0),
+        SH_PFC_PIN_GROUP(intc_irq12_1),
+        SH_PFC_PIN_GROUP(intc_irq13_0),
+        SH_PFC_PIN_GROUP(intc_irq13_1),
+        SH_PFC_PIN_GROUP(intc_irq14_0),
+        SH_PFC_PIN_GROUP(intc_irq14_1),
+        SH_PFC_PIN_GROUP(intc_irq15_0),
+        SH_PFC_PIN_GROUP(intc_irq15_1),
+        SH_PFC_PIN_GROUP(intc_irq16_0),
+        SH_PFC_PIN_GROUP(intc_irq16_1),
+        SH_PFC_PIN_GROUP(intc_irq17),
+        SH_PFC_PIN_GROUP(intc_irq18),
+        SH_PFC_PIN_GROUP(intc_irq19),
+        SH_PFC_PIN_GROUP(intc_irq20),
+        SH_PFC_PIN_GROUP(intc_irq21),
+        SH_PFC_PIN_GROUP(intc_irq22),
+        SH_PFC_PIN_GROUP(intc_irq23),
+        SH_PFC_PIN_GROUP(intc_irq24),
+        SH_PFC_PIN_GROUP(intc_irq25),
+        SH_PFC_PIN_GROUP(intc_irq26_0),
+        SH_PFC_PIN_GROUP(intc_irq26_1),
+        SH_PFC_PIN_GROUP(intc_irq27_0),
+        SH_PFC_PIN_GROUP(intc_irq27_1),
+        SH_PFC_PIN_GROUP(intc_irq28_0),
+        SH_PFC_PIN_GROUP(intc_irq28_1),
+        SH_PFC_PIN_GROUP(intc_irq29_0),
+        SH_PFC_PIN_GROUP(intc_irq29_1),
+        SH_PFC_PIN_GROUP(intc_irq30_0),
+        SH_PFC_PIN_GROUP(intc_irq30_1),
+        SH_PFC_PIN_GROUP(intc_irq31_0),
+        SH_PFC_PIN_GROUP(intc_irq31_1),
+        SH_PFC_PIN_GROUP(keysc_in04_0),
+        SH_PFC_PIN_GROUP(keysc_in04_1),
+        SH_PFC_PIN_GROUP(keysc_in5),
+        SH_PFC_PIN_GROUP(keysc_in6),
+        SH_PFC_PIN_GROUP(keysc_in7),
+        SH_PFC_PIN_GROUP(keysc_out4),
+        SH_PFC_PIN_GROUP(keysc_out5),
+        SH_PFC_PIN_GROUP(keysc_out6),
+        SH_PFC_PIN_GROUP(keysc_out8),
+        SH_PFC_PIN_GROUP(lcd_data8),
+        SH_PFC_PIN_GROUP(lcd_data9),
+        SH_PFC_PIN_GROUP(lcd_data12),
+        SH_PFC_PIN_GROUP(lcd_data16),
+        SH_PFC_PIN_GROUP(lcd_data18),
+        SH_PFC_PIN_GROUP(lcd_data24),
+        SH_PFC_PIN_GROUP(lcd_display),
+        SH_PFC_PIN_GROUP(lcd_lclk),
+        SH_PFC_PIN_GROUP(lcd_sync),
+        SH_PFC_PIN_GROUP(lcd_sys),
         SH_PFC_PIN_GROUP(mmc0_data1_0),
         SH_PFC_PIN_GROUP(mmc0_data4_0),
         SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1083,6 +1859,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(mmc0_data4_1),
         SH_PFC_PIN_GROUP(mmc0_data8_1),
         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa3_data),
+        SH_PFC_PIN_GROUP(scifa3_clk),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa4_data),
+        SH_PFC_PIN_GROUP(scifa5_data),
+        SH_PFC_PIN_GROUP(scifb_data),
+        SH_PFC_PIN_GROUP(scifb_clk),
+        SH_PFC_PIN_GROUP(scifb_ctrl),
         SH_PFC_PIN_GROUP(sdhi0_data1),
         SH_PFC_PIN_GROUP(sdhi0_data4),
         SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -1094,6 +1888,144 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_data1),
         SH_PFC_PIN_GROUP(sdhi2_data4),
         SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(usb0_vbus),
+        SH_PFC_PIN_GROUP(usb0_otg_id),
+        SH_PFC_PIN_GROUP(usb0_otg_ctrl),
+        SH_PFC_PIN_GROUP(usb1_vbus),
+        SH_PFC_PIN_GROUP(usb1_otg_id_0),
+        SH_PFC_PIN_GROUP(usb1_otg_id_1),
+        SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
+        SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
+};
+
+static const char * const bsc_groups[] = {
+        "bsc_data8",
+        "bsc_data16",
+        "bsc_cs0",
+        "bsc_cs2",
+        "bsc_cs4",
+        "bsc_cs5a",
+        "bsc_cs5b",
+        "bsc_cs6a",
+        "bsc_rd_we8",
+        "bsc_rd_we16",
+        "bsc_bs",
+        "bsc_rdwr",
+};
+
+static const char * const ceu_groups[] = {
+        "ceu_data_0_7",
+        "ceu_data_8_15",
+        "ceu_clk_0",
+        "ceu_clk_1",
+        "ceu_clk_2",
+        "ceu_sync",
+        "ceu_field",
+};
+
+static const char * const flctl_groups[] = {
+        "flctl_data",
+        "flctl_ce0",
+        "flctl_ce1",
+        "flctl_ctrl",
+};
+
+static const char * const fsia_groups[] = {
+        "fsia_mclk_in",
+        "fsia_mclk_out",
+        "fsia_sclk_in",
+        "fsia_sclk_out",
+        "fsia_data_in",
+        "fsia_data_out",
+        "fsia_spdif_0",
+        "fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+        "fsib_mclk_in",
+};
+
+static const char * const hdmi_groups[] = {
+        "hdmi",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0_0",
+        "intc_irq0_1",
+        "intc_irq1",
+        "intc_irq2_0",
+        "intc_irq2_1",
+        "intc_irq3_0",
+        "intc_irq3_1",
+        "intc_irq4_0",
+        "intc_irq4_1",
+        "intc_irq5",
+        "intc_irq6_0",
+        "intc_irq6_1",
+        "intc_irq7_0",
+        "intc_irq7_1",
+        "intc_irq8_0",
+        "intc_irq8_1",
+        "intc_irq9_0",
+        "intc_irq9_1",
+        "intc_irq10",
+        "intc_irq11",
+        "intc_irq12_0",
+        "intc_irq12_1",
+        "intc_irq13_0",
+        "intc_irq13_1",
+        "intc_irq14_0",
+        "intc_irq14_1",
+        "intc_irq15_0",
+        "intc_irq15_1",
+        "intc_irq16_0",
+        "intc_irq16_1",
+        "intc_irq17",
+        "intc_irq18",
+        "intc_irq19",
+        "intc_irq20",
+        "intc_irq21",
+        "intc_irq22",
+        "intc_irq23",
+        "intc_irq24",
+        "intc_irq25",
+        "intc_irq26_0",
+        "intc_irq26_1",
+        "intc_irq27_0",
+        "intc_irq27_1",
+        "intc_irq28_0",
+        "intc_irq28_1",
+        "intc_irq29_0",
+        "intc_irq29_1",
+        "intc_irq30_0",
+        "intc_irq30_1",
+        "intc_irq31_0",
+        "intc_irq31_1",
+};
+
+static const char * const keysc_groups[] = {
+        "keysc_in04_0",
+        "keysc_in04_1",
+        "keysc_in5",
+        "keysc_in6",
+        "keysc_in7",
+        "keysc_out4",
+        "keysc_out5",
+        "keysc_out6",
+        "keysc_out8",
+};
+
+static const char * const lcd_groups[] = {
+        "lcd_data8",
+        "lcd_data9",
+        "lcd_data12",
+        "lcd_data16",
+        "lcd_data18",
+        "lcd_data24",
+        "lcd_display",
+        "lcd_lclk",
+        "lcd_sync",
+        "lcd_sys",
 };
 
 static const char * const mmc0_groups[] = {
@@ -1107,6 +2039,45 @@ static const char * const mmc0_groups[] = {
         "mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk",
+        "scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+        "scifa3_data",
+        "scifa3_clk",
+        "scifa3_ctrl_0",
+        "scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+        "scifa4_data",
+};
+
+static const char * const scifa5_groups[] = {
+        "scifa5_data",
+};
+
+static const char * const scifb_groups[] = {
+        "scifb_data",
+        "scifb_clk",
+        "scifb_ctrl",
+};
+
 static const char * const sdhi0_groups[] = {
         "sdhi0_data1",
         "sdhi0_data4",
@@ -1127,256 +2098,55 @@ static const char * const sdhi2_groups[] = {
         "sdhi2_ctrl",
 };
 
+static const char * const usb0_groups[] = {
+        "usb0_vbus",
+        "usb0_otg_id",
+        "usb0_otg_ctrl",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1_vbus",
+        "usb1_otg_id_0",
+        "usb1_otg_id_1",
+        "usb1_otg_ctrl_0",
+        "usb1_otg_ctrl_1",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(bsc),
+        SH_PFC_FUNCTION(ceu),
+        SH_PFC_FUNCTION(flctl),
+        SH_PFC_FUNCTION(fsia),
+        SH_PFC_FUNCTION(fsib),
+        SH_PFC_FUNCTION(hdmi),
+        SH_PFC_FUNCTION(intc),
+        SH_PFC_FUNCTION(keysc),
+        SH_PFC_FUNCTION(lcd),
         SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifa3),
+        SH_PFC_FUNCTION(scifa4),
+        SH_PFC_FUNCTION(scifa5),
+        SH_PFC_FUNCTION(scifb),
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
 };
 
-#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* IRQ */
-        GPIO_FN(IRQ0_6),        GPIO_FN(IRQ0_162),      GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_4),        GPIO_FN(IRQ2_5),        GPIO_FN(IRQ3_8),
-        GPIO_FN(IRQ3_16),       GPIO_FN(IRQ4_17),       GPIO_FN(IRQ4_163),
-        GPIO_FN(IRQ5),          GPIO_FN(IRQ6_39),       GPIO_FN(IRQ6_164),
-        GPIO_FN(IRQ7_40),       GPIO_FN(IRQ7_167),      GPIO_FN(IRQ8_41),
-        GPIO_FN(IRQ8_168),      GPIO_FN(IRQ9_42),       GPIO_FN(IRQ9_169),
-        GPIO_FN(IRQ10),         GPIO_FN(IRQ11),         GPIO_FN(IRQ12_80),
-        GPIO_FN(IRQ12_137),     GPIO_FN(IRQ13_81),      GPIO_FN(IRQ13_145),
-        GPIO_FN(IRQ14_82),      GPIO_FN(IRQ14_146),     GPIO_FN(IRQ15_83),
-        GPIO_FN(IRQ15_147),     GPIO_FN(IRQ16_84),      GPIO_FN(IRQ16_170),
-        GPIO_FN(IRQ17),         GPIO_FN(IRQ18),         GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),         GPIO_FN(IRQ21),         GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),         GPIO_FN(IRQ24),         GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_121),     GPIO_FN(IRQ26_172),     GPIO_FN(IRQ27_122),
-        GPIO_FN(IRQ27_180),     GPIO_FN(IRQ28_123),     GPIO_FN(IRQ28_181),
-        GPIO_FN(IRQ29_129),     GPIO_FN(IRQ29_182),     GPIO_FN(IRQ30_130),
-        GPIO_FN(IRQ30_183),     GPIO_FN(IRQ31_138),     GPIO_FN(IRQ31_184),
-
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_TSYNC),  GPIO_FN(MSIOF0_TSCK),   GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(MSIOF0_MCK1),   GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(MSIOF0_TXD),
-
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_TSCK_39),        GPIO_FN(MSIOF1_TSCK_88),
-        GPIO_FN(MSIOF1_TSYNC_40),       GPIO_FN(MSIOF1_TSYNC_89),
-        GPIO_FN(MSIOF1_TXD_41),         GPIO_FN(MSIOF1_TXD_90),
-        GPIO_FN(MSIOF1_RXD_42),         GPIO_FN(MSIOF1_RXD_91),
-        GPIO_FN(MSIOF1_SS1_43),         GPIO_FN(MSIOF1_SS1_92),
-        GPIO_FN(MSIOF1_SS2_44),         GPIO_FN(MSIOF1_SS2_93),
-        GPIO_FN(MSIOF1_RSCK),           GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),           GPIO_FN(MSIOF1_MCK1),
-
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_RSCK),   GPIO_FN(MSIOF2_RSYNC),  GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_SS1),    GPIO_FN(MSIOF2_SS2),
-        GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_TSCK),   GPIO_FN(MSIOF2_RXD),
-        GPIO_FN(MSIOF2_TXD),
-
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TSYNC),   GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BB_RX_FLOW_N),
-
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TSCK1),   GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TXD1),    GPIO_FN(BBIF2_RXD),
-
-        /* FSI */
-        GPIO_FN(FSIACK),        GPIO_FN(FSIBCK),        GPIO_FN(FSIAILR),
-        GPIO_FN(FSIAIBT),       GPIO_FN(FSIAISLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIAOLR),       GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),
-        GPIO_FN(FSIASPDIF_11),  GPIO_FN(FSIASPDIF_15),
-
-        /* FMSI */
-        GPIO_FN(FMSOCK),        GPIO_FN(FMSOOLR),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSOOBT),       GPIO_FN(FMSIOBT),       GPIO_FN(FMSOSLD),
-        GPIO_FN(FMSOILR),       GPIO_FN(FMSIILR),       GPIO_FN(FMSOIBT),
-        GPIO_FN(FMSIIBT),       GPIO_FN(FMSISLD),       GPIO_FN(FMSICK),
-
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_TXD),    GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_SCK),
-        GPIO_FN(SCIFA0_RTS),    GPIO_FN(SCIFA0_CTS),
-
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RTS),    GPIO_FN(SCIFA1_CTS),
-
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_CTS1),   GPIO_FN(SCIFA2_RTS1),   GPIO_FN(SCIFA2_TXD1),
-        GPIO_FN(SCIFA2_RXD1),   GPIO_FN(SCIFA2_SCK1),
-
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_CTS_43),         GPIO_FN(SCIFA3_CTS_140),
-        GPIO_FN(SCIFA3_RTS_44),         GPIO_FN(SCIFA3_RTS_141),
-        GPIO_FN(SCIFA3_SCK),            GPIO_FN(SCIFA3_TXD),
-        GPIO_FN(SCIFA3_RXD),
-
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD),    GPIO_FN(SCIFA4_TXD),
-
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_RXD),    GPIO_FN(SCIFA5_TXD),
-
-        /* SCIFB */
-        GPIO_FN(SCIFB_SCK),     GPIO_FN(SCIFB_RTS),     GPIO_FN(SCIFB_CTS),
-        GPIO_FN(SCIFB_TXD),     GPIO_FN(SCIFB_RXD),
-
-        /* CEU */
-        GPIO_FN(VIO_HD),        GPIO_FN(VIO_CKO1),      GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_VD),        GPIO_FN(VIO_CLK),       GPIO_FN(VIO_FIELD),
-        GPIO_FN(VIO_CKO),       GPIO_FN(VIO_D0),        GPIO_FN(VIO_D1),
-        GPIO_FN(VIO_D2),        GPIO_FN(VIO_D3),        GPIO_FN(VIO_D4),
-        GPIO_FN(VIO_D5),        GPIO_FN(VIO_D6),        GPIO_FN(VIO_D7),
-        GPIO_FN(VIO_D8),        GPIO_FN(VIO_D9),        GPIO_FN(VIO_D10),
-        GPIO_FN(VIO_D11),       GPIO_FN(VIO_D12),       GPIO_FN(VIO_D13),
-        GPIO_FN(VIO_D14),       GPIO_FN(VIO_D15),
-
-        /* USB0 */
-        GPIO_FN(IDIN_0),        GPIO_FN(EXTLP_0),       GPIO_FN(OVCN2_0),
-        GPIO_FN(PWEN_0),        GPIO_FN(OVCN_0),        GPIO_FN(VBUS0_0),
-
-        /* USB1 */
-        GPIO_FN(IDIN_1_18),     GPIO_FN(IDIN_1_113),
-        GPIO_FN(OVCN_1_114),    GPIO_FN(OVCN_1_162),
-        GPIO_FN(PWEN_1_115),    GPIO_FN(PWEN_1_138),
-        GPIO_FN(EXTLP_1),       GPIO_FN(OVCN2_1),
-        GPIO_FN(VBUS0_1),
-
-        /* GPIO */
-        GPIO_FN(GPI0),  GPIO_FN(GPI1),  GPIO_FN(GPO0),  GPIO_FN(GPO1),
-
-        /* BSC */
-        GPIO_FN(BS),    GPIO_FN(WE1),   GPIO_FN(CKO),
-        GPIO_FN(WAIT),  GPIO_FN(RDWR),
-
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),
-        GPIO_FN(A3),    GPIO_FN(A6),    GPIO_FN(A7),
-        GPIO_FN(A8),    GPIO_FN(A9),    GPIO_FN(A10),
-        GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),
-        GPIO_FN(A17),   GPIO_FN(A18),   GPIO_FN(A19),
-        GPIO_FN(A20),   GPIO_FN(A21),   GPIO_FN(A22),
-        GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5A),  GPIO_FN(CS5B),  GPIO_FN(CS6A),
-
-        /* BSC/FLCTL */
-        GPIO_FN(RD_FSC),        GPIO_FN(WE0_FWE),       GPIO_FN(A4_FOE),
-        GPIO_FN(A5_FCDE),       GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       GPIO_FN(D4_NAF4),
-        GPIO_FN(D5_NAF5),       GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       GPIO_FN(D10_NAF10),
-        GPIO_FN(D11_NAF11),     GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),
-
-        /* SPU2 */
-        GPIO_FN(VINT_I),
-
-        /* FLCTL */
-        GPIO_FN(FCE1),  GPIO_FN(FCE0),  GPIO_FN(FRB),
-
-        /* HSI */
-        GPIO_FN(GP_RX_FLAG),    GPIO_FN(GP_RX_DATA),    GPIO_FN(GP_TX_READY),
-        GPIO_FN(GP_RX_WAKE),    GPIO_FN(MP_TX_FLAG),    GPIO_FN(MP_TX_DATA),
-        GPIO_FN(MP_RX_READY),   GPIO_FN(MP_TX_WAKE),
-
-        /* MFI */
-        GPIO_FN(MFIv6),
-        GPIO_FN(MFIv4),
-
-        GPIO_FN(MEMC_BUSCLK_MEMC_A0),   GPIO_FN(MEMC_ADV_MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT_MEMC_DREQ1),  GPIO_FN(MEMC_CS1_MEMC_A1),
-        GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_NOE),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_INT),
-
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),
-
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),       GPIO_FN(SIM_D),
-
-        /* TPU */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO2_93),
-        GPIO_FN(TPU0TO2_99),    GPIO_FN(TPU0TO3),
-
-        /* I2C2 */
-        GPIO_FN(I2C_SCL2),      GPIO_FN(I2C_SDA2),
-
-        /* I2C3(1) */
-        GPIO_FN(I2C_SCL3),      GPIO_FN(I2C_SDA3),
-
-        /* I2C3(2) */
-        GPIO_FN(I2C_SCL3S),     GPIO_FN(I2C_SDA3S),
-
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4),      GPIO_FN(I2C_SDA4),
-
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4S),     GPIO_FN(I2C_SDA4S),
-
-        /* KEYSC */
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYIN0_121),    GPIO_FN(KEYIN0_136),
-        GPIO_FN(KEYOUT1),       GPIO_FN(KEYIN1_122),    GPIO_FN(KEYIN1_135),
-        GPIO_FN(KEYOUT2),       GPIO_FN(KEYIN2_123),    GPIO_FN(KEYIN2_134),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYIN3_124),    GPIO_FN(KEYIN3_133),
-        GPIO_FN(KEYOUT4),       GPIO_FN(KEYIN4),        GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYIN5),        GPIO_FN(KEYOUT6),       GPIO_FN(KEYIN6),
-        GPIO_FN(KEYOUT7),       GPIO_FN(KEYIN7),
-
-        /* LCDC */
-        GPIO_FN(LCDHSYN),       GPIO_FN(LCDCS), GPIO_FN(LCDVSYN),
-        GPIO_FN(LCDDCK),        GPIO_FN(LCDWR), GPIO_FN(LCDRD),
-        GPIO_FN(LCDDISP),       GPIO_FN(LCDRS), GPIO_FN(LCDLCLK),
-        GPIO_FN(LCDDON),
-
-        GPIO_FN(LCDD0),         GPIO_FN(LCDD1),         GPIO_FN(LCDD2),
-        GPIO_FN(LCDD3),         GPIO_FN(LCDD4),         GPIO_FN(LCDD5),
-        GPIO_FN(LCDD6),         GPIO_FN(LCDD7),         GPIO_FN(LCDD8),
-        GPIO_FN(LCDD9),         GPIO_FN(LCDD10),        GPIO_FN(LCDD11),
-        GPIO_FN(LCDD12),        GPIO_FN(LCDD13),        GPIO_FN(LCDD14),
-        GPIO_FN(LCDD15),        GPIO_FN(LCDD16),        GPIO_FN(LCDD17),
-        GPIO_FN(LCDD18),        GPIO_FN(LCDD19),        GPIO_FN(LCDD20),
-        GPIO_FN(LCDD21),        GPIO_FN(LCDD22),        GPIO_FN(LCDD23),
-
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-
-        /* IRDA */
-        GPIO_FN(IRDA_OUT),      GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_FIRSEL),
-        GPIO_FN(IROUT_139),     GPIO_FN(IROUT_140),
-
-        /* TSIF1 */
-        GPIO_FN(TS0_1SELECT),
-        GPIO_FN(TS0_2SELECT),
-        GPIO_FN(TS1_1SELECT),
-        GPIO_FN(TS1_2SELECT),
-
-        GPIO_FN(TS_SPSYNC1),    GPIO_FN(TS_SDAT1),
-        GPIO_FN(TS_SDEN1),      GPIO_FN(TS_SCK1),
-
-        /* TSIF2 */
-        GPIO_FN(TS_SPSYNC2),    GPIO_FN(TS_SDAT2),
-        GPIO_FN(TS_SDEN2),      GPIO_FN(TS_SCK2),
-
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),      GPIO_FN(HDMI_CEC),
-
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-};
+#undef PORTCR
+#define PORTCR(nr, reg)                                                 \
+        {                                                               \
+                PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
+                        _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1,         \
+                                PORT##nr##_FN2, PORT##nr##_FN3,         \
+                                PORT##nr##_FN4, PORT##nr##_FN5,         \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xE6051000), /* PORT0CR */
@@ -1776,45 +2546,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
 #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
 static const struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
-        PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
-        PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
-        PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
-        PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
-        PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
-        PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
-        PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
-        PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
-        PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
-        PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
-        PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
-        PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
-        PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
-        PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
-        PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
-        PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
-        PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
-        PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
-        PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
-        PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
-        PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
-        PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
-        PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
-        PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
-        PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
-        PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
-        PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
-        PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
-        PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
-        PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
-        PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
+        PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
+        PINMUX_IRQ(EXT_IRQ16L(1), 12),
+        PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
+        PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
+        PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
+        PINMUX_IRQ(EXT_IRQ16L(5), 18),
+        PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
+        PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
+        PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
+        PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
+        PINMUX_IRQ(EXT_IRQ16L(10), 65),
+        PINMUX_IRQ(EXT_IRQ16L(11), 67),
+        PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
+        PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
+        PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
+        PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
+        PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
+        PINMUX_IRQ(EXT_IRQ16H(17), 85),
+        PINMUX_IRQ(EXT_IRQ16H(18), 86),
+        PINMUX_IRQ(EXT_IRQ16H(19), 87),
+        PINMUX_IRQ(EXT_IRQ16H(20), 92),
+        PINMUX_IRQ(EXT_IRQ16H(21), 93),
+        PINMUX_IRQ(EXT_IRQ16H(22), 94),
+        PINMUX_IRQ(EXT_IRQ16H(23), 95),
+        PINMUX_IRQ(EXT_IRQ16H(24), 112),
+        PINMUX_IRQ(EXT_IRQ16H(25), 119),
+        PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
+        PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
+        PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
+        PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
+        PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
+        PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
+};
+
+#define PORTnCR_PULMD_OFF       (0 << 6)
+#define PORTnCR_PULMD_DOWN      (2 << 6)
+#define PORTnCR_PULMD_UP        (3 << 6)
+#define PORTnCR_PULMD_MASK      (3 << 6)
+
+struct sh7372_portcr_group {
+        unsigned int end_pin;
+        unsigned int offset;
+};
+
+static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
+        { 45,  0x1000 }, { 75,  0x2000 }, { 99,  0x0000 }, { 120, 0x3000 },
+        { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
+};
+
+static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
+                const struct sh7372_portcr_group *group =
+                        &sh7372_portcr_offsets[i];
+
+                if (i <= group->end_pin)
+                        return pfc->window->virt + group->offset + pin;
+        }
+
+        return NULL;
+}
+
+static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+        void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+        switch (value) {
+        case PORTnCR_PULMD_UP:
+                return PIN_CONFIG_BIAS_PULL_UP;
+        case PORTnCR_PULMD_DOWN:
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+        case PORTnCR_PULMD_OFF:
+        default:
+                return PIN_CONFIG_BIAS_DISABLE;
+        }
+}
+
+static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                   unsigned int bias)
+{
+        void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+        switch (bias) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                value |= PORTnCR_PULMD_UP;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                value |= PORTnCR_PULMD_DOWN;
+                break;
+        }
+
+        iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
+        .get_bias = sh7372_pinmux_get_bias,
+        .set_bias = sh7372_pinmux_set_bias,
 };
 
 const struct sh_pfc_soc_info sh7372_pinmux_info = {
         .name = "sh7372_pfc",
+        .ops = &sh7372_pinmux_ops,
+
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
@@ -1825,9 +2664,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = {
         .functions = pinmux_functions,
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios = pinmux_func_gpios,
-        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 587f7772abf2..7956df58d751 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -20,9 +20,12 @@
  */
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/pinctrl/pinconf-generic.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/slab.h>
 
-#include <mach/sh73a0.h>
 #include <mach/irqs.h>
 
 #include "core.h"
@@ -2538,6 +2541,157 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
         SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        55,
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        59,
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+        /* TO */
+        140,
+};
+static const unsigned int tpu0_to2_mux[] = {
+        TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        141,
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
+/* - TPU1 ------------------------------------------------------------------- */
+static const unsigned int tpu1_to0_pins[] = {
+        /* TO */
+        246,
+};
+static const unsigned int tpu1_to0_mux[] = {
+        TPU1TO0_MARK,
+};
+static const unsigned int tpu1_to1_0_pins[] = {
+        /* TO */
+        28,
+};
+static const unsigned int tpu1_to1_0_mux[] = {
+        PORT28_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to1_1_pins[] = {
+        /* TO */
+        29,
+};
+static const unsigned int tpu1_to1_1_mux[] = {
+        PORT29_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to2_pins[] = {
+        /* TO */
+        153,
+};
+static const unsigned int tpu1_to2_mux[] = {
+        TPU1TO2_MARK,
+};
+static const unsigned int tpu1_to3_pins[] = {
+        /* TO */
+        145,
+};
+static const unsigned int tpu1_to3_mux[] = {
+        TPU1TO3_MARK,
+};
+/* - TPU2 ------------------------------------------------------------------- */
+static const unsigned int tpu2_to0_pins[] = {
+        /* TO */
+        248,
+};
+static const unsigned int tpu2_to0_mux[] = {
+        TPU2TO0_MARK,
+};
+static const unsigned int tpu2_to1_pins[] = {
+        /* TO */
+        197,
+};
+static const unsigned int tpu2_to1_mux[] = {
+        TPU2TO1_MARK,
+};
+static const unsigned int tpu2_to2_pins[] = {
+        /* TO */
+        50,
+};
+static const unsigned int tpu2_to2_mux[] = {
+        TPU2TO2_MARK,
+};
+static const unsigned int tpu2_to3_pins[] = {
+        /* TO */
+        51,
+};
+static const unsigned int tpu2_to3_mux[] = {
+        TPU2TO3_MARK,
+};
+/* - TPU3 ------------------------------------------------------------------- */
+static const unsigned int tpu3_to0_pins[] = {
+        /* TO */
+        163,
+};
+static const unsigned int tpu3_to0_mux[] = {
+        TPU3TO0_MARK,
+};
+static const unsigned int tpu3_to1_pins[] = {
+        /* TO */
+        247,
+};
+static const unsigned int tpu3_to1_mux[] = {
+        TPU3TO1_MARK,
+};
+static const unsigned int tpu3_to2_pins[] = {
+        /* TO */
+        54,
+};
+static const unsigned int tpu3_to2_mux[] = {
+        TPU3TO2_MARK,
+};
+static const unsigned int tpu3_to3_pins[] = {
+        /* TO */
+        53,
+};
+static const unsigned int tpu3_to3_mux[] = {
+        TPU3TO3_MARK,
+};
+/* - TPU4 ------------------------------------------------------------------- */
+static const unsigned int tpu4_to0_pins[] = {
+        /* TO */
+        241,
+};
+static const unsigned int tpu4_to0_mux[] = {
+        TPU4TO0_MARK,
+};
+static const unsigned int tpu4_to1_pins[] = {
+        /* TO */
+        199,
+};
+static const unsigned int tpu4_to1_mux[] = {
+        TPU4TO1_MARK,
+};
+static const unsigned int tpu4_to2_pins[] = {
+        /* TO */
+        58,
+};
+static const unsigned int tpu4_to2_mux[] = {
+        TPU4TO2_MARK,
+};
+static const unsigned int tpu4_to3_pins[] = {
+        /* TO */
+};
+static const unsigned int tpu4_to3_mux[] = {
+        TPU4TO3_MARK,
+};
 /* - USB -------------------------------------------------------------------- */
 static const unsigned int usb_vbus_pins[] = {
         /* VBUS */
@@ -2689,6 +2843,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_data1),
         SH_PFC_PIN_GROUP(sdhi2_data4),
         SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+        SH_PFC_PIN_GROUP(tpu1_to0),
+        SH_PFC_PIN_GROUP(tpu1_to1_0),
+        SH_PFC_PIN_GROUP(tpu1_to1_1),
+        SH_PFC_PIN_GROUP(tpu1_to2),
+        SH_PFC_PIN_GROUP(tpu1_to3),
+        SH_PFC_PIN_GROUP(tpu2_to0),
+        SH_PFC_PIN_GROUP(tpu2_to1),
+        SH_PFC_PIN_GROUP(tpu2_to2),
+        SH_PFC_PIN_GROUP(tpu2_to3),
+        SH_PFC_PIN_GROUP(tpu3_to0),
+        SH_PFC_PIN_GROUP(tpu3_to1),
+        SH_PFC_PIN_GROUP(tpu3_to2),
+        SH_PFC_PIN_GROUP(tpu3_to3),
+        SH_PFC_PIN_GROUP(tpu4_to0),
+        SH_PFC_PIN_GROUP(tpu4_to1),
+        SH_PFC_PIN_GROUP(tpu4_to2),
+        SH_PFC_PIN_GROUP(tpu4_to3),
         SH_PFC_PIN_GROUP(usb_vbus),
 };
 
@@ -2908,6 +3083,42 @@ static const char * const usb_groups[] = {
         "usb_vbus",
 };
 
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2",
+        "tpu0_to3",
+};
+
+static const char * const tpu1_groups[] = {
+        "tpu1_to0",
+        "tpu1_to1_0",
+        "tpu1_to1_1",
+        "tpu1_to2",
+        "tpu1_to3",
+};
+
+static const char * const tpu2_groups[] = {
+        "tpu2_to0",
+        "tpu2_to1",
+        "tpu2_to2",
+        "tpu2_to3",
+};
+
+static const char * const tpu3_groups[] = {
+        "tpu3_to0",
+        "tpu3_to1",
+        "tpu3_to2",
+        "tpu3_to3",
+};
+
+static const char * const tpu4_groups[] = {
+        "tpu4_to0",
+        "tpu4_to1",
+        "tpu4_to2",
+        "tpu4_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(bsc),
         SH_PFC_FUNCTION(fsia),
@@ -2933,400 +3144,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(tpu0),
+        SH_PFC_FUNCTION(tpu1),
+        SH_PFC_FUNCTION(tpu2),
+        SH_PFC_FUNCTION(tpu3),
+        SH_PFC_FUNCTION(tpu4),
         SH_PFC_FUNCTION(usb),
 };
 
-#define PINMUX_FN_BASE  GPIO_FN_GPI0
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* Table 25-1 (Functions 0-7) */
-        GPIO_FN(GPI0),
-        GPIO_FN(GPI1),
-        GPIO_FN(GPI2),
-        GPIO_FN(GPI3),
-        GPIO_FN(GPI4),
-        GPIO_FN(GPI5),
-        GPIO_FN(GPI6),
-        GPIO_FN(GPI7),
-        GPIO_FN(GPO7), \
-        GPIO_FN(MFG0_OUT2),
-        GPIO_FN(GPO6), \
-        GPIO_FN(MFG1_OUT2),
-        GPIO_FN(GPO5), \
-        GPIO_FN(PORT16_VIO_CKOR),
-        GPIO_FN(PORT19_VIO_CKO2),
-        GPIO_FN(GPO0),
-        GPIO_FN(GPO1),
-        GPIO_FN(GPO2), \
-        GPIO_FN(STATUS0),
-        GPIO_FN(GPO3), \
-        GPIO_FN(STATUS1),
-        GPIO_FN(GPO4), \
-        GPIO_FN(STATUS2),
-        GPIO_FN(VINT),
-        GPIO_FN(TCKON),
-        GPIO_FN(XDVFS1), \
-        GPIO_FN(MFG0_OUT1), \
-        GPIO_FN(PORT27_IROUT),
-        GPIO_FN(XDVFS2), \
-        GPIO_FN(PORT28_TPU1TO1),
-        GPIO_FN(SIM_RST), \
-        GPIO_FN(PORT29_TPU1TO1),
-        GPIO_FN(SIM_CLK), \
-        GPIO_FN(PORT30_VIO_CKOR),
-        GPIO_FN(SIM_D), \
-        GPIO_FN(PORT31_IROUT),
-        GPIO_FN(XWUP),
-        GPIO_FN(VACK),
-        GPIO_FN(XTAL1L),
-        GPIO_FN(PORT49_IROUT), \
-        GPIO_FN(BBIF2_TSYNC2), \
-        GPIO_FN(TPU2TO2), \
-
-        GPIO_FN(BBIF2_TSCK2), \
-        GPIO_FN(TPU2TO3), \
-        GPIO_FN(BBIF2_TXD2),
-        GPIO_FN(TPU3TO3), \
-        GPIO_FN(TPU3TO2), \
-        GPIO_FN(TPU0TO0),
-        GPIO_FN(A0), \
-        GPIO_FN(BS_),
-        GPIO_FN(A12), \
-        GPIO_FN(TPU4TO2),
-        GPIO_FN(A13), \
-        GPIO_FN(TPU0TO1),
-        GPIO_FN(A14), \
-        GPIO_FN(A15), \
-        GPIO_FN(A16), \
-        GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17), \
-        GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18), \
-        GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19), \
-        GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20), \
-        GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21), \
-        GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22), \
-        GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23), \
-        GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24), \
-        GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25), \
-        GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), \
-        GPIO_FN(FCE1_),
-        GPIO_FN(DACK0),
-        GPIO_FN(FCE0_), \
-        GPIO_FN(WAIT_), \
-        GPIO_FN(DREQ0),
-        GPIO_FN(FRB),
-        GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT_),
-        GPIO_FN(NBRST_),
-        GPIO_FN(BBIF2_TXD),
-        GPIO_FN(BBIF2_RXD),
-        GPIO_FN(BBIF2_SYNC),
-        GPIO_FN(BBIF2_SCK),
-        GPIO_FN(MFG3_IN2),
-        GPIO_FN(MFG3_IN1),
-        GPIO_FN(BBIF1_SS2), \
-        GPIO_FN(MFG3_OUT1),
-        GPIO_FN(HSI_RX_DATA), \
-        GPIO_FN(BBIF1_RXD),
-        GPIO_FN(HSI_TX_WAKE), \
-        GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(HSI_TX_DATA), \
-        GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(HSI_TX_READY), \
-        GPIO_FN(BBIF1_TXD),
-        GPIO_FN(HSI_RX_READY), \
-        GPIO_FN(BBIF1_RSCK), \
-        GPIO_FN(HSI_RX_WAKE), \
-        GPIO_FN(BBIF1_RSYNC), \
-        GPIO_FN(HSI_RX_FLAG), \
-        GPIO_FN(BBIF1_SS1), \
-        GPIO_FN(BBIF1_FLOW),
-        GPIO_FN(HSI_TX_FLAG),
-        GPIO_FN(VIO_VD), \
-        GPIO_FN(VIO2_VD), \
-
-        GPIO_FN(VIO_HD), \
-        GPIO_FN(VIO2_HD), \
-        GPIO_FN(VIO_D0), \
-        GPIO_FN(PORT130_MSIOF2_RXD), \
-        GPIO_FN(VIO_D1), \
-        GPIO_FN(PORT131_MSIOF2_SS1), \
-        GPIO_FN(VIO_D2), \
-        GPIO_FN(PORT132_MSIOF2_SS2), \
-        GPIO_FN(VIO_D3), \
-        GPIO_FN(MSIOF2_TSYNC), \
-        GPIO_FN(VIO_D4), \
-        GPIO_FN(MSIOF2_TXD), \
-        GPIO_FN(VIO_D5), \
-        GPIO_FN(MSIOF2_TSCK), \
-        GPIO_FN(VIO_D6), \
-        GPIO_FN(VIO_D7), \
-        GPIO_FN(VIO_D8), \
-        GPIO_FN(VIO2_D0), \
-        GPIO_FN(VIO_D9), \
-        GPIO_FN(VIO2_D1), \
-        GPIO_FN(VIO_D10), \
-        GPIO_FN(TPU0TO2), \
-        GPIO_FN(VIO2_D2), \
-        GPIO_FN(VIO_D11), \
-        GPIO_FN(TPU0TO3), \
-        GPIO_FN(VIO2_D3), \
-        GPIO_FN(VIO_D12), \
-        GPIO_FN(VIO2_D4), \
-        GPIO_FN(VIO_D13), \
-        GPIO_FN(VIO2_D5), \
-        GPIO_FN(VIO_D14), \
-        GPIO_FN(VIO2_D6), \
-        GPIO_FN(VIO_D15), \
-        GPIO_FN(TPU1TO3), \
-        GPIO_FN(VIO2_D7), \
-        GPIO_FN(VIO_CLK), \
-        GPIO_FN(VIO2_CLK), \
-        GPIO_FN(VIO_FIELD), \
-        GPIO_FN(VIO2_FIELD), \
-        GPIO_FN(VIO_CKO),
-        GPIO_FN(A27), \
-        GPIO_FN(MFG0_IN1), \
-        GPIO_FN(MFG0_IN2),
-        GPIO_FN(TS_SPSYNC3), \
-        GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(TS_SDAT3), \
-        GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(TPU1TO2), \
-        GPIO_FN(TS_SDEN3), \
-        GPIO_FN(PORT153_MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(PORT156_MSIOF2_SS2),
-        GPIO_FN(PORT157_MSIOF2_RXD),
-        GPIO_FN(DINT_), \
-        GPIO_FN(TS_SCK3),
-        GPIO_FN(NMI),
-        GPIO_FN(TPU3TO0),
-        GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(MFG2_OUT2), \
-        GPIO_FN(TPU2TO1),
-        GPIO_FN(TPU4TO1), \
-        GPIO_FN(MFG4_OUT2),
-        GPIO_FN(D16),
-        GPIO_FN(D17),
-        GPIO_FN(D18),
-        GPIO_FN(D19),
-        GPIO_FN(D20),
-        GPIO_FN(D21),
-        GPIO_FN(D22),
-        GPIO_FN(PORT207_MSIOF0L_SS1), \
-        GPIO_FN(D23),
-        GPIO_FN(PORT208_MSIOF0L_SS2), \
-        GPIO_FN(D24),
-        GPIO_FN(D25),
-        GPIO_FN(DREQ2), \
-        GPIO_FN(PORT210_MSIOF0L_SS1), \
-        GPIO_FN(D26),
-        GPIO_FN(PORT211_MSIOF0L_SS2), \
-        GPIO_FN(D27),
-        GPIO_FN(TS_SPSYNC1), \
-        GPIO_FN(MSIOF0L_MCK0), \
-        GPIO_FN(D28),
-        GPIO_FN(TS_SDAT1), \
-        GPIO_FN(MSIOF0L_MCK1), \
-        GPIO_FN(D29),
-        GPIO_FN(TS_SDEN1), \
-        GPIO_FN(MSIOF0L_RSCK), \
-        GPIO_FN(D30),
-        GPIO_FN(TS_SCK1), \
-        GPIO_FN(MSIOF0L_RSYNC), \
-        GPIO_FN(D31),
-        GPIO_FN(DACK2), \
-        GPIO_FN(MSIOF0L_TSYNC), \
-        GPIO_FN(VIO2_FIELD3), \
-        GPIO_FN(DACK3), \
-        GPIO_FN(PORT218_VIO_CKOR),
-        GPIO_FN(DREQ3), \
-        GPIO_FN(MSIOF0L_TSCK), \
-        GPIO_FN(VIO2_CLK3), \
-        GPIO_FN(DREQ1), \
-        GPIO_FN(PWEN), \
-        GPIO_FN(MSIOF0L_RXD), \
-        GPIO_FN(VIO2_HD3), \
-        GPIO_FN(DACK1), \
-        GPIO_FN(OVCN), \
-        GPIO_FN(MSIOF0L_TXD), \
-        GPIO_FN(VIO2_VD3), \
-
-        GPIO_FN(OVCN2),
-        GPIO_FN(EXTLP), \
-        GPIO_FN(PORT226_VIO_CKO2),
-        GPIO_FN(IDIN),
-        GPIO_FN(MFG1_IN1),
-        GPIO_FN(MSIOF1_TXD), \
-        GPIO_FN(MSIOF1_TSYNC), \
-        GPIO_FN(MSIOF1_TSCK), \
-        GPIO_FN(MSIOF1_RXD), \
-        GPIO_FN(MSIOF1_RSCK), \
-        GPIO_FN(VIO2_CLK2), \
-        GPIO_FN(MSIOF1_RSYNC), \
-        GPIO_FN(MFG1_IN2), \
-        GPIO_FN(VIO2_VD2), \
-        GPIO_FN(MSIOF1_MCK0), \
-        GPIO_FN(MSIOF1_MCK1), \
-        GPIO_FN(MSIOF1_SS1), \
-        GPIO_FN(VIO2_FIELD2), \
-        GPIO_FN(MSIOF1_SS2), \
-        GPIO_FN(VIO2_HD2), \
-        GPIO_FN(PORT241_IROUT), \
-        GPIO_FN(MFG4_OUT1), \
-        GPIO_FN(TPU4TO0),
-        GPIO_FN(MFG4_IN2),
-        GPIO_FN(PORT243_VIO_CKO2),
-        GPIO_FN(MFG2_IN1), \
-        GPIO_FN(MSIOF2R_RXD),
-        GPIO_FN(MFG2_IN2), \
-        GPIO_FN(MSIOF2R_TXD),
-        GPIO_FN(MFG1_OUT1), \
-        GPIO_FN(TPU1TO0),
-        GPIO_FN(MFG3_OUT2), \
-        GPIO_FN(TPU3TO1),
-        GPIO_FN(MFG2_OUT1), \
-        GPIO_FN(TPU2TO0), \
-        GPIO_FN(MSIOF2R_TSCK),
-        GPIO_FN(PORT249_IROUT), \
-        GPIO_FN(MFG4_IN1), \
-        GPIO_FN(MSIOF2R_TSYNC),
-        GPIO_FN(SDHICLK0),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0),
-        GPIO_FN(SDHID0_1),
-        GPIO_FN(SDHID0_2),
-        GPIO_FN(SDHID0_3),
-        GPIO_FN(SDHICMD0),
-        GPIO_FN(SDHIWP0),
-        GPIO_FN(SDHICLK1),
-        GPIO_FN(SDHID1_0), \
-        GPIO_FN(TS_SPSYNC2),
-        GPIO_FN(SDHID1_1), \
-        GPIO_FN(TS_SDAT2),
-        GPIO_FN(SDHID1_2), \
-        GPIO_FN(TS_SDEN2),
-        GPIO_FN(SDHID1_3), \
-        GPIO_FN(TS_SCK2),
-        GPIO_FN(SDHICMD1),
-        GPIO_FN(SDHICLK2),
-        GPIO_FN(SDHID2_0), \
-        GPIO_FN(TS_SPSYNC4),
-        GPIO_FN(SDHID2_1), \
-        GPIO_FN(TS_SDAT4),
-        GPIO_FN(SDHID2_2), \
-        GPIO_FN(TS_SDEN4),
-        GPIO_FN(SDHID2_3), \
-        GPIO_FN(TS_SCK4),
-        GPIO_FN(SDHICMD2),
-        GPIO_FN(MMCCLK0),
-        GPIO_FN(MMCD0_0),
-        GPIO_FN(MMCD0_1),
-        GPIO_FN(MMCD0_2),
-        GPIO_FN(MMCD0_3),
-        GPIO_FN(MMCD0_4), \
-        GPIO_FN(TS_SPSYNC5),
-        GPIO_FN(MMCD0_5), \
-        GPIO_FN(TS_SDAT5),
-        GPIO_FN(MMCD0_6), \
-        GPIO_FN(TS_SDEN5),
-        GPIO_FN(MMCD0_7), \
-        GPIO_FN(TS_SCK5),
-        GPIO_FN(MMCCMD0),
-        GPIO_FN(RESETOUTS_), \
-        GPIO_FN(EXTAL2OUT),
-        GPIO_FN(MCP_WAIT__MCP_FRB),
-        GPIO_FN(MCP_CKO), \
-        GPIO_FN(MMCCLK1),
-        GPIO_FN(MCP_D15_MCP_NAF15),
-        GPIO_FN(MCP_D14_MCP_NAF14),
-        GPIO_FN(MCP_D13_MCP_NAF13),
-        GPIO_FN(MCP_D12_MCP_NAF12),
-        GPIO_FN(MCP_D11_MCP_NAF11),
-        GPIO_FN(MCP_D10_MCP_NAF10),
-        GPIO_FN(MCP_D9_MCP_NAF9),
-        GPIO_FN(MCP_D8_MCP_NAF8), \
-        GPIO_FN(MMCCMD1),
-        GPIO_FN(MCP_D7_MCP_NAF7), \
-        GPIO_FN(MMCD1_7),
-
-        GPIO_FN(MCP_D6_MCP_NAF6), \
-        GPIO_FN(MMCD1_6),
-        GPIO_FN(MCP_D5_MCP_NAF5), \
-        GPIO_FN(MMCD1_5),
-        GPIO_FN(MCP_D4_MCP_NAF4), \
-        GPIO_FN(MMCD1_4),
-        GPIO_FN(MCP_D3_MCP_NAF3), \
-        GPIO_FN(MMCD1_3),
-        GPIO_FN(MCP_D2_MCP_NAF2), \
-        GPIO_FN(MMCD1_2),
-        GPIO_FN(MCP_D1_MCP_NAF1), \
-        GPIO_FN(MMCD1_1),
-        GPIO_FN(MCP_D0_MCP_NAF0), \
-        GPIO_FN(MMCD1_0),
-        GPIO_FN(MCP_NBRSTOUT_),
-        GPIO_FN(MCP_WE0__MCP_FWE), \
-        GPIO_FN(MCP_RDWR_MCP_FWE),
-
-        /* MSEL2 special cases */
-        GPIO_FN(TSIF2_TS_XX1),
-        GPIO_FN(TSIF2_TS_XX2),
-        GPIO_FN(TSIF2_TS_XX3),
-        GPIO_FN(TSIF2_TS_XX4),
-        GPIO_FN(TSIF2_TS_XX5),
-        GPIO_FN(TSIF1_TS_XX1),
-        GPIO_FN(TSIF1_TS_XX2),
-        GPIO_FN(TSIF1_TS_XX3),
-        GPIO_FN(TSIF1_TS_XX4),
-        GPIO_FN(TSIF1_TS_XX5),
-        GPIO_FN(TSIF0_TS_XX1),
-        GPIO_FN(TSIF0_TS_XX2),
-        GPIO_FN(TSIF0_TS_XX3),
-        GPIO_FN(TSIF0_TS_XX4),
-        GPIO_FN(TSIF0_TS_XX5),
-        GPIO_FN(MST1_TS_XX1),
-        GPIO_FN(MST1_TS_XX2),
-        GPIO_FN(MST1_TS_XX3),
-        GPIO_FN(MST1_TS_XX4),
-        GPIO_FN(MST1_TS_XX5),
-        GPIO_FN(MST0_TS_XX1),
-        GPIO_FN(MST0_TS_XX2),
-        GPIO_FN(MST0_TS_XX3),
-        GPIO_FN(MST0_TS_XX4),
-        GPIO_FN(MST0_TS_XX5),
-
-        /* MSEL3 special cases */
-        GPIO_FN(SDHI0_VCCQ_MC0_ON),
-        GPIO_FN(SDHI0_VCCQ_MC0_OFF),
-        GPIO_FN(DEBUG_MON_VIO),
-        GPIO_FN(DEBUG_MON_LCDD),
-        GPIO_FN(LCDC_LCDC0),
-        GPIO_FN(LCDC_LCDC1),
-
-        /* MSEL4 special cases */
-        GPIO_FN(IRQ9_MEM_INT),
-        GPIO_FN(IRQ9_MCP_INT),
-        GPIO_FN(A11),
-        GPIO_FN(TPU4TO3),
-        GPIO_FN(RESETA_N_PU_ON),
-        GPIO_FN(RESETA_N_PU_OFF),
-        GPIO_FN(EDBGREQ_PD),
-        GPIO_FN(EDBGREQ_PU),
-};
-
 #undef PORTCR
 #define PORTCR(nr, reg)                                                 \
         {                                                               \
@@ -3888,6 +3713,92 @@ static const struct pinmux_irq pinmux_irqs[] = {
         PINMUX_IRQ(EXT_IRQ16L(9), 308),
 };
 
+/* -----------------------------------------------------------------------------
+ * VCCQ MC0 regulator
+ */
+
+static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
+{
+        struct sh_pfc *pfc = reg->reg_data;
+        void __iomem *addr = pfc->window[1].virt + 4;
+        unsigned long flags;
+        u32 value;
+
+        spin_lock_irqsave(&pfc->lock, flags);
+
+        value = ioread32(addr);
+
+        if (enable)
+                value |= BIT(28);
+        else
+                value &= ~BIT(28);
+
+        iowrite32(value, addr);
+
+        spin_unlock_irqrestore(&pfc->lock, flags);
+}
+
+static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
+{
+        sh73a0_vccq_mc0_endisable(reg, true);
+        return 0;
+}
+
+static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
+{
+        sh73a0_vccq_mc0_endisable(reg, false);
+        return 0;
+}
+
+static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
+{
+        struct sh_pfc *pfc = reg->reg_data;
+        void __iomem *addr = pfc->window[1].virt + 4;
+        unsigned long flags;
+        u32 value;
+
+        spin_lock_irqsave(&pfc->lock, flags);
+        value = ioread32(addr);
+        spin_unlock_irqrestore(&pfc->lock, flags);
+
+        return !!(value & BIT(28));
+}
+
+static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
+{
+        return 3300000;
+}
+
+static struct regulator_ops sh73a0_vccq_mc0_ops = {
+        .enable = sh73a0_vccq_mc0_enable,
+        .disable = sh73a0_vccq_mc0_disable,
+        .is_enabled = sh73a0_vccq_mc0_is_enabled,
+        .get_voltage = sh73a0_vccq_mc0_get_voltage,
+};
+
+static const struct regulator_desc sh73a0_vccq_mc0_desc = {
+        .owner = THIS_MODULE,
+        .name = "vccq_mc0",
+        .type = REGULATOR_VOLTAGE,
+        .ops = &sh73a0_vccq_mc0_ops,
+};
+
+static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
+        .consumer_supplies = sh73a0_vccq_mc0_consumers,
+};
+
+/* -----------------------------------------------------------------------------
+ * Pin bias
+ */
+
 #define PORTnCR_PULMD_OFF       (0 << 6)
 #define PORTnCR_PULMD_DOWN      (2 << 6)
 #define PORTnCR_PULMD_UP        (3 << 6)
@@ -3934,7 +3845,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
         iowrite8(value, addr);
 }
 
+/* -----------------------------------------------------------------------------
+ * SoC information
+ */
+
+struct sh73a0_pinmux_data {
+        struct regulator_dev *vccq_mc0;
+};
+
+static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
+{
+        struct sh73a0_pinmux_data *data;
+        struct regulator_config cfg = { };
+        int ret;
+
+        data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
+        if (data == NULL)
+                return -ENOMEM;
+
+        cfg.dev = pfc->dev;
+        cfg.init_data = &sh73a0_vccq_mc0_init_data;
+        cfg.driver_data = pfc;
+
+        data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
+        if (IS_ERR(data->vccq_mc0)) {
+                ret = PTR_ERR(data->vccq_mc0);
+                dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
+                        ret);
+                return ret;
+        }
+
+        pfc->soc_data = data;
+
+        return 0;
+}
+
+static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
+{
+        struct sh73a0_pinmux_data *data = pfc->soc_data;
+
+        regulator_unregister(data->vccq_mc0);
+}
+
 static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
+        .init = sh73a0_pinmux_soc_init,
+        .exit = sh73a0_pinmux_soc_exit,
         .get_bias = sh73a0_pinmux_get_bias,
         .set_bias = sh73a0_pinmux_set_bias,
 };
@@ -3956,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
         .functions = pinmux_functions,
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios = pinmux_func_gpios,
-        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 3b785fc428d5..830ae1ffd0b5 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -11,8 +11,8 @@
 #ifndef __SH_PFC_H
 #define __SH_PFC_H
 
+#include <linux/bug.h>
 #include <linux/stringify.h>
-#include <asm-generic/gpio.h>
 
 typedef unsigned short pinmux_enum_t;
 
@@ -129,6 +129,8 @@ struct pinmux_range {
 struct sh_pfc;
 
 struct sh_pfc_soc_operations {
+        int (*init)(struct sh_pfc *pfc);
+        void (*exit)(struct sh_pfc *pfc);
         unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
         void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
                          unsigned int bias);
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 0eab77b22340..f296f3f7db9b 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -25,6 +25,7 @@
 #include <linux/rtc.h>
 #include <linux/bcd.h>
 #include <linux/interrupt.h>
+#include <linux/spinlock.h>
 #include <linux/ioctl.h>
 #include <linux/completion.h>
 #include <linux/io.h>
@@ -42,10 +43,65 @@
 
 #define AT91_RTC_EPOCH          1900UL  /* just like arch/arm/common/rtctime.c */
 
+struct at91_rtc_config {
+        bool use_shadow_imr;
+};
+
+static const struct at91_rtc_config *at91_rtc_config;
 static DECLARE_COMPLETION(at91_rtc_updated);
 static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
 static void __iomem *at91_rtc_regs;
 static int irq;
+static DEFINE_SPINLOCK(at91_rtc_lock);
+static u32 at91_rtc_shadow_imr;
+
+static void at91_rtc_write_ier(u32 mask)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&at91_rtc_lock, flags);
+        at91_rtc_shadow_imr |= mask;
+        at91_rtc_write(AT91_RTC_IER, mask);
+        spin_unlock_irqrestore(&at91_rtc_lock, flags);
+}
+
+static void at91_rtc_write_idr(u32 mask)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&at91_rtc_lock, flags);
+        at91_rtc_write(AT91_RTC_IDR, mask);
+        /*
+         * Register read back (of any RTC-register) needed to make sure
+         * IDR-register write has reached the peripheral before updating
+         * shadow mask.
+         *
+         * Note that there is still a possibility that the mask is updated
+         * before interrupts have actually been disabled in hardware. The only
+         * way to be certain would be to poll the IMR-register, which is is
+         * the very register we are trying to emulate. The register read back
+         * is a reasonable heuristic.
+         */
+        at91_rtc_read(AT91_RTC_SR);
+        at91_rtc_shadow_imr &= ~mask;
+        spin_unlock_irqrestore(&at91_rtc_lock, flags);
+}
+
+static u32 at91_rtc_read_imr(void)
+{
+        unsigned long flags;
+        u32 mask;
+
+        if (at91_rtc_config->use_shadow_imr) {
+                spin_lock_irqsave(&at91_rtc_lock, flags);
+                mask = at91_rtc_shadow_imr;
+                spin_unlock_irqrestore(&at91_rtc_lock, flags);
+        } else {
+                mask = at91_rtc_read(AT91_RTC_IMR);
+        }
+
+        return mask;
+}
 
 /*
  * Decode time/date into rtc_time structure
@@ -110,9 +166,9 @@ static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
         cr = at91_rtc_read(AT91_RTC_CR);
         at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
 
-        at91_rtc_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
+        at91_rtc_write_ier(AT91_RTC_ACKUPD);
         wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
+        at91_rtc_write_idr(AT91_RTC_ACKUPD);
 
         at91_rtc_write(AT91_RTC_TIMR,
                           bin2bcd(tm->tm_sec) << 0
@@ -144,7 +200,7 @@ static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
         tm->tm_year = at91_alarm_year - 1900;
 
-        alrm->enabled = (at91_rtc_read(AT91_RTC_IMR) & AT91_RTC_ALARM)
+        alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
                         ? 1 : 0;
 
         dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -169,7 +225,7 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm.tm_min = alrm->time.tm_min;
         tm.tm_sec = alrm->time.tm_sec;
 
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
+        at91_rtc_write_idr(AT91_RTC_ALARM);
         at91_rtc_write(AT91_RTC_TIMALR,
                   bin2bcd(tm.tm_sec) << 0
                 | bin2bcd(tm.tm_min) << 8
@@ -182,7 +238,7 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 
         if (alrm->enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
+                at91_rtc_write_ier(AT91_RTC_ALARM);
         }
 
         dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -198,9 +254,9 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 
         if (enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
+                at91_rtc_write_ier(AT91_RTC_ALARM);
         } else
-                at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
+                at91_rtc_write_idr(AT91_RTC_ALARM);
 
         return 0;
 }
@@ -209,7 +265,7 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  */
 static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
 {
-        unsigned long imr = at91_rtc_read(AT91_RTC_IMR);
+        unsigned long imr = at91_rtc_read_imr();
 
         seq_printf(seq, "update_IRQ\t: %s\n",
                         (imr & AT91_RTC_ACKUPD) ? "yes" : "no");
@@ -229,7 +285,7 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
         unsigned int rtsr;
         unsigned long events = 0;
 
-        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read(AT91_RTC_IMR);
+        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
         if (rtsr) {             /* this interrupt is shared!  Is it ours? */
                 if (rtsr & AT91_RTC_ALARM)
                         events |= (RTC_AF | RTC_IRQF);
@@ -250,6 +306,43 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
         return IRQ_NONE;                /* not handled */
 }
 
+static const struct at91_rtc_config at91rm9200_config = {
+};
+
+static const struct at91_rtc_config at91sam9x5_config = {
+        .use_shadow_imr = true,
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id at91_rtc_dt_ids[] = {
+        {
+                .compatible = "atmel,at91rm9200-rtc",
+                .data = &at91rm9200_config,
+        }, {
+                .compatible = "atmel,at91sam9x5-rtc",
+                .data = &at91sam9x5_config,
+        }, {
+                /* sentinel */
+        }
+};
+MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
+#endif
+
+static const struct at91_rtc_config *
+at91_rtc_get_config(struct platform_device *pdev)
+{
+        const struct of_device_id *match;
+
+        if (pdev->dev.of_node) {
+                match = of_match_node(at91_rtc_dt_ids, pdev->dev.of_node);
+                if (!match)
+                        return NULL;
+                return (const struct at91_rtc_config *)match->data;
+        }
+
+        return &at91rm9200_config;
+}
+
 static const struct rtc_class_ops at91_rtc_ops = {
         .read_time      = at91_rtc_readtime,
         .set_time       = at91_rtc_settime,
@@ -268,6 +361,10 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
         struct resource *regs;
         int ret = 0;
 
+        at91_rtc_config = at91_rtc_get_config(pdev);
+        if (!at91_rtc_config)
+                return -ENODEV;
+
         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!regs) {
                 dev_err(&pdev->dev, "no mmio resource defined\n");
@@ -290,7 +387,7 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
         at91_rtc_write(AT91_RTC_MR, 0);         /* 24 hour mode */
 
         /* Disable all interrupts */
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+        at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
 
@@ -335,7 +432,7 @@ static int __exit at91_rtc_remove(struct platform_device *pdev)
         struct rtc_device *rtc = platform_get_drvdata(pdev);
 
         /* Disable all interrupts */
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+        at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
         free_irq(irq, pdev);
@@ -358,13 +455,13 @@ static int at91_rtc_suspend(struct device *dev)
         /* this IRQ is shared with DBGU and other hardware which isn't
          * necessarily doing PM like we are...
          */
-        at91_rtc_imr = at91_rtc_read(AT91_RTC_IMR)
+        at91_rtc_imr = at91_rtc_read_imr()
                         & (AT91_RTC_ALARM|AT91_RTC_SECEV);
         if (at91_rtc_imr) {
                 if (device_may_wakeup(dev))
                         enable_irq_wake(irq);
                 else
-                        at91_rtc_write(AT91_RTC_IDR, at91_rtc_imr);
+                        at91_rtc_write_idr(at91_rtc_imr);
         }
         return 0;
 }
@@ -375,7 +472,7 @@ static int at91_rtc_resume(struct device *dev)
                 if (device_may_wakeup(dev))
                         disable_irq_wake(irq);
                 else
-                        at91_rtc_write(AT91_RTC_IER, at91_rtc_imr);
+                        at91_rtc_write_ier(at91_rtc_imr);
         }
         return 0;
 }
@@ -383,12 +480,6 @@ static int at91_rtc_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
 
-static const struct of_device_id at91_rtc_dt_ids[] = {
-        { .compatible = "atmel,at91rm9200-rtc" },
-        { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
-
 static struct platform_driver at91_rtc_driver = {
         .remove         = __exit_p(at91_rtc_remove),
         .driver         = {
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index cc5bea9c4b1c..f1cb706445c7 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -854,6 +854,9 @@ static int cmos_resume(struct device *dev)
                 }
 
                 spin_lock_irq(&rtc_lock);
+                if (device_may_wakeup(dev))
+                        hpet_rtc_timer_init();
+
                 do {
                         CMOS_WRITE(tmp, RTC_CONTROL);
                         hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK);
@@ -869,7 +872,6 @@ static int cmos_resume(struct device *dev)
                         rtc_update_irq(cmos->rtc, 1, mask);
                         tmp &= ~RTC_AIE;
                         hpet_mask_rtc_irq_bit(RTC_AIE);
-                        hpet_rtc_timer_init();
                 } while (mask & RTC_AIE);
                 spin_unlock_irq(&rtc_lock);
         }
diff --git a/drivers/rtc/rtc-tps6586x.c b/drivers/rtc/rtc-tps6586x.c
index 459c2ffc95a6..426901cef14f 100644
--- a/drivers/rtc/rtc-tps6586x.c
+++ b/drivers/rtc/rtc-tps6586x.c
@@ -273,6 +273,8 @@ static int tps6586x_rtc_probe(struct platform_device *pdev)
                 return ret;
         }
 
+        device_init_wakeup(&pdev->dev, 1);
+
         platform_set_drvdata(pdev, rtc);
         rtc->rtc = devm_rtc_device_register(&pdev->dev, dev_name(&pdev->dev),
                                        &tps6586x_rtc_ops, THIS_MODULE);
@@ -292,7 +294,6 @@ static int tps6586x_rtc_probe(struct platform_device *pdev)
                 goto fail_rtc_register;
         }
         disable_irq(rtc->irq);
-        device_set_wakeup_capable(&pdev->dev, 1);
         return 0;
 
 fail_rtc_register:
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8751a5240c99..b2eab34f38d9 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -524,6 +524,7 @@ static int twl_rtc_probe(struct platform_device *pdev)
         }
 
         platform_set_drvdata(pdev, rtc);
+        device_init_wakeup(&pdev->dev, 1);
         return 0;
 
 out2:
diff --git a/drivers/s390/net/netiucv.c b/drivers/s390/net/netiucv.c
index 4ffa66c87ea5..9ca3996f65b2 100644
--- a/drivers/s390/net/netiucv.c
+++ b/drivers/s390/net/netiucv.c
@@ -2040,6 +2040,7 @@ static struct net_device *netiucv_init_netdevice(char *username, char *userdata)
                            netiucv_setup_netdevice);
         if (!dev)
                 return NULL;
+        rtnl_lock();
         if (dev_alloc_name(dev, dev->name) < 0)
                 goto out_netdev;
 
@@ -2061,6 +2062,7 @@ static struct net_device *netiucv_init_netdevice(char *username, char *userdata)
 out_fsm:
         kfree_fsm(privptr->fsm);
 out_netdev:
+        rtnl_unlock();
         free_netdev(dev);
         return NULL;
 }
@@ -2100,6 +2102,7 @@ static ssize_t conn_write(struct device_driver *drv,
 
         rc = netiucv_register_device(dev);
         if (rc) {
+                rtnl_unlock();
                 IUCV_DBF_TEXT_(setup, 2,
                         "ret %d from netiucv_register_device\n", rc);
                 goto out_free_ndev;
@@ -2109,7 +2112,8 @@ static ssize_t conn_write(struct device_driver *drv,
         priv = netdev_priv(dev);
         SET_NETDEV_DEV(dev, priv->dev);
 
-        rc = register_netdev(dev);
+        rc = register_netdevice(dev);
+        rtnl_unlock();
         if (rc)
                 goto out_unreg;
 
diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c
index 60cfae51c713..eab593eaaafa 100644
--- a/drivers/spi/spi-sh-hspi.c
+++ b/drivers/spi/spi-sh-hspi.c
@@ -89,7 +89,7 @@ static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
                 if ((mask & hspi_read(hspi, SPSR)) == val)
                         return 0;
 
-                msleep(20);
+                udelay(10);
         }
 
         dev_err(hspi->dev, "timeout\n");
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 35f60bd252dd..637d728fbeb5 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -1487,7 +1487,7 @@ static int pch_spi_pd_probe(struct platform_device *plat_dev)
         return 0;
 
 err_spi_register_master:
-        free_irq(board_dat->pdev->irq, board_dat);
+        free_irq(board_dat->pdev->irq, data);
 err_request_irq:
         pch_spi_free_resources(board_dat, data);
 err_spi_get_resources:
@@ -1667,6 +1667,7 @@ static int pch_spi_probe(struct pci_dev *pdev,
                 pd_dev = platform_device_alloc("pch-spi", i);
                 if (!pd_dev) {
                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
+                        retval = -ENOMEM;
                         goto err_platform_device;
                 }
                 pd_dev_save->pd_save[i] = pd_dev;
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index e1d769607425..34d18dcfa0db 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -267,7 +267,6 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 {
         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
         u32 ipif_ier;
-        u16 cr;
 
         /* We get here with transmitter inhibited */
 
@@ -276,7 +275,6 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
         xspi->remaining_bytes = t->len;
         INIT_COMPLETION(xspi->done);
 
-        xilinx_spi_fill_tx_fifo(xspi);
 
         /* Enable the transmit empty interrupt, which we use to determine
          * progress on the transmission.
@@ -285,12 +283,41 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
         xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
                 xspi->regs + XIPIF_V123B_IIER_OFFSET);
 
-        /* Start the transfer by not inhibiting the transmitter any longer */
-        cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
-                ~XSPI_CR_TRANS_INHIBIT;
-        xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
+        for (;;) {
+                u16 cr;
+                u8 sr;
+
+                xilinx_spi_fill_tx_fifo(xspi);
+
+                /* Start the transfer by not inhibiting the transmitter any
+                 * longer
+                 */
+                cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
+                                                        ~XSPI_CR_TRANS_INHIBIT;
+                xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
+
+                wait_for_completion(&xspi->done);
+
+                /* A transmit has just completed. Process received data and
+                 * check for more data to transmit. Always inhibit the
+                 * transmitter while the Isr refills the transmit register/FIFO,
+                 * or make sure it is stopped if we're done.
+                 */
+                cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
+                xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
+                               xspi->regs + XSPI_CR_OFFSET);
+
+                /* Read out all the data from the Rx FIFO */
+                sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
+                while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
+                        xspi->rx_fn(xspi);
+                        sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
+                }
 
-        wait_for_completion(&xspi->done);
+                /* See if there is more data to send */
+                if (!xspi->remaining_bytes > 0)
+                        break;
+        }
 
         /* Disable the transmit empty interrupt */
         xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
@@ -314,38 +341,7 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
         xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
 
         if (ipif_isr & XSPI_INTR_TX_EMPTY) {    /* Transmission completed */
-                u16 cr;
-                u8 sr;
-
-                /* A transmit has just completed. Process received data and
-                 * check for more data to transmit. Always inhibit the
-                 * transmitter while the Isr refills the transmit register/FIFO,
-                 * or make sure it is stopped if we're done.
-                 */
-                cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
-                xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
-                        xspi->regs + XSPI_CR_OFFSET);
-
-                /* Read out all the data from the Rx FIFO */
-                sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
-                while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
-                        xspi->rx_fn(xspi);
-                        sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
-                }
-
-                /* See if there is more data to send */
-                if (xspi->remaining_bytes > 0) {
-                        xilinx_spi_fill_tx_fifo(xspi);
-                        /* Start the transfer by not inhibiting the
-                         * transmitter any longer
-                         */
-                        xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
-                } else {
-                        /* No more data to send.
-                         * Indicate the transfer is completed.
-                         */
-                        complete(&xspi->done);
-                }
+                complete(&xspi->done);
         }
 
         return IRQ_HANDLED;
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 49b098bedf9b..475c9c114689 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -276,8 +276,9 @@ static void ci_role_work(struct work_struct *work)
 
                 ci_role_stop(ci);
                 ci_role_start(ci, role);
-                enable_irq(ci->irq);
         }
+
+        enable_irq(ci->irq);
 }
 
 static irqreturn_t ci_irq(int irq, void *data)
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 519ead2443c5..b501346484ae 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1678,8 +1678,11 @@ static int udc_start(struct ci13xxx *ci)
 
         ci->gadget.ep0 = &ci->ep0in->ep;
 
-        if (ci->global_phy)
+        if (ci->global_phy) {
                 ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+                if (IS_ERR(ci->transceiver))
+                        ci->transceiver = NULL;
+        }
 
         if (ci->platdata->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
                 if (ci->transceiver == NULL) {
@@ -1694,7 +1697,7 @@ static int udc_start(struct ci13xxx *ci)
                         goto put_transceiver;
         }
 
-        if (!IS_ERR_OR_NULL(ci->transceiver)) {
+        if (ci->transceiver) {
                 retval = otg_set_peripheral(ci->transceiver->otg,
                                                 &ci->gadget);
                 if (retval)
@@ -1711,7 +1714,7 @@ static int udc_start(struct ci13xxx *ci)
         return retval;
 
 remove_trans:
-        if (!IS_ERR_OR_NULL(ci->transceiver)) {
+        if (ci->transceiver) {
                 otg_set_peripheral(ci->transceiver->otg, NULL);
                 if (ci->global_phy)
                         usb_put_phy(ci->transceiver);
@@ -1719,7 +1722,7 @@ remove_trans:
 
         dev_err(dev, "error = %i\n", retval);
 put_transceiver:
-        if (!IS_ERR_OR_NULL(ci->transceiver) && ci->global_phy)
+        if (ci->transceiver && ci->global_phy)
                 usb_put_phy(ci->transceiver);
 destroy_eps:
         destroy_eps(ci);
@@ -1747,7 +1750,7 @@ static void udc_stop(struct ci13xxx *ci)
         dma_pool_destroy(ci->td_pool);
         dma_pool_destroy(ci->qh_pool);
 
-        if (!IS_ERR_OR_NULL(ci->transceiver)) {
+        if (ci->transceiver) {
                 otg_set_peripheral(ci->transceiver->otg, NULL);
                 if (ci->global_phy)
                         usb_put_phy(ci->transceiver);
diff --git a/drivers/usb/serial/f81232.c b/drivers/usb/serial/f81232.c
index 090b411d893f..7d8dd5aad236 100644
--- a/drivers/usb/serial/f81232.c
+++ b/drivers/usb/serial/f81232.c
@@ -165,11 +165,12 @@ static void f81232_set_termios(struct tty_struct *tty,
         /* FIXME - Stubbed out for now */
 
         /* Don't change anything if nothing has changed */
-        if (!tty_termios_hw_change(&tty->termios, old_termios))
+        if (old_termios && !tty_termios_hw_change(&tty->termios, old_termios))
                 return;
 
         /* Do the real work here... */
-        tty_termios_copy_hw(&tty->termios, old_termios);
+        if (old_termios)
+                tty_termios_copy_hw(&tty->termios, old_termios);
 }
 
 static int f81232_tiocmget(struct tty_struct *tty)
@@ -187,12 +188,11 @@ static int f81232_tiocmset(struct tty_struct *tty,
 
 static int f81232_open(struct tty_struct *tty, struct usb_serial_port *port)
 {
-        struct ktermios tmp_termios;
         int result;
 
         /* Setup termios */
         if (tty)
-                f81232_set_termios(tty, port, &tmp_termios);
+                f81232_set_termios(tty, port, NULL);
 
         result = usb_submit_urb(port->interrupt_in_urb, GFP_KERNEL);
         if (result) {
diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c
index 7151659367a0..048cd44d51b1 100644
--- a/drivers/usb/serial/pl2303.c
+++ b/drivers/usb/serial/pl2303.c
@@ -284,7 +284,7 @@ static void pl2303_set_termios(struct tty_struct *tty,
            serial settings even to the same values as before. Thus
            we actually need to filter in this specific case */
 
-        if (!tty_termios_hw_change(&tty->termios, old_termios))
+        if (old_termios && !tty_termios_hw_change(&tty->termios, old_termios))
                 return;
 
         cflag = tty->termios.c_cflag;
@@ -293,7 +293,8 @@ static void pl2303_set_termios(struct tty_struct *tty,
         if (!buf) {
                 dev_err(&port->dev, "%s - out of memory.\n", __func__);
                 /* Report back no change occurred */
-                tty->termios = *old_termios;
+                if (old_termios)
+                        tty->termios = *old_termios;
                 return;
         }
 
@@ -433,7 +434,7 @@ static void pl2303_set_termios(struct tty_struct *tty,
         control = priv->line_control;
         if ((cflag & CBAUD) == B0)
                 priv->line_control &= ~(CONTROL_DTR | CONTROL_RTS);
-        else if ((old_termios->c_cflag & CBAUD) == B0)
+        else if (old_termios && (old_termios->c_cflag & CBAUD) == B0)
                 priv->line_control |= (CONTROL_DTR | CONTROL_RTS);
         if (control != priv->line_control) {
                 control = priv->line_control;
@@ -492,7 +493,6 @@ static void pl2303_close(struct usb_serial_port *port)
 
 static int pl2303_open(struct tty_struct *tty, struct usb_serial_port *port)
 {
-        struct ktermios tmp_termios;
         struct usb_serial *serial = port->serial;
         struct pl2303_serial_private *spriv = usb_get_serial_data(serial);
         int result;
@@ -508,7 +508,7 @@ static int pl2303_open(struct tty_struct *tty, struct usb_serial_port *port)
 
         /* Setup termios */
         if (tty)
-                pl2303_set_termios(tty, port, &tmp_termios);
+                pl2303_set_termios(tty, port, NULL);
 
         result = usb_submit_urb(port->interrupt_in_urb, GFP_KERNEL);
         if (result) {
diff --git a/drivers/usb/serial/spcp8x5.c b/drivers/usb/serial/spcp8x5.c
index cf3df793c2b7..ddf6c47137dc 100644
--- a/drivers/usb/serial/spcp8x5.c
+++ b/drivers/usb/serial/spcp8x5.c
@@ -291,7 +291,6 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
         struct spcp8x5_private *priv = usb_get_serial_port_data(port);
         unsigned long flags;
         unsigned int cflag = tty->termios.c_cflag;
-        unsigned int old_cflag = old_termios->c_cflag;
         unsigned short uartdata;
         unsigned char buf[2] = {0, 0};
         int baud;
@@ -299,15 +298,15 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
         u8 control;
 
         /* check that they really want us to change something */
-        if (!tty_termios_hw_change(&tty->termios, old_termios))
+        if (old_termios && !tty_termios_hw_change(&tty->termios, old_termios))
                 return;
 
         /* set DTR/RTS active */
         spin_lock_irqsave(&priv->lock, flags);
         control = priv->line_control;
-        if ((old_cflag & CBAUD) == B0) {
+        if (old_termios && (old_termios->c_cflag & CBAUD) == B0) {
                 priv->line_control |= MCR_DTR;
-                if (!(old_cflag & CRTSCTS))
+                if (!(old_termios->c_cflag & CRTSCTS))
                         priv->line_control |= MCR_RTS;
         }
         if (control != priv->line_control) {
@@ -394,7 +393,6 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
 
 static int spcp8x5_open(struct tty_struct *tty, struct usb_serial_port *port)
 {
-        struct ktermios tmp_termios;
         struct usb_serial *serial = port->serial;
         struct spcp8x5_private *priv = usb_get_serial_port_data(port);
         int ret;
@@ -411,7 +409,7 @@ static int spcp8x5_open(struct tty_struct *tty, struct usb_serial_port *port)
         spcp8x5_set_ctrl_line(port, priv->line_control);
 
         if (tty)
-                spcp8x5_set_termios(tty, port, &tmp_termios);
+                spcp8x5_set_termios(tty, port, NULL);
 
         port->port.drain_delay = 256;
 
diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c
index 2b51e2336aa2..f80d3dd41d8c 100644
--- a/drivers/vhost/net.c
+++ b/drivers/vhost/net.c
@@ -155,14 +155,11 @@ static void vhost_net_ubuf_put_and_wait(struct vhost_net_ubuf_ref *ubufs)
 
 static void vhost_net_clear_ubuf_info(struct vhost_net *n)
 {
-
-        bool zcopy;
         int i;
 
-        for (i = 0; i < n->dev.nvqs; ++i) {
-                zcopy = vhost_net_zcopy_mask & (0x1 << i);
-                if (zcopy)
-                        kfree(n->vqs[i].ubuf_info);
+        for (i = 0; i < VHOST_NET_VQ_MAX; ++i) {
+                kfree(n->vqs[i].ubuf_info);
+                n->vqs[i].ubuf_info = NULL;
         }
 }
 
@@ -171,7 +168,7 @@ int vhost_net_set_ubuf_info(struct vhost_net *n)
         bool zcopy;
         int i;
 
-        for (i = 0; i < n->dev.nvqs; ++i) {
+        for (i = 0; i < VHOST_NET_VQ_MAX; ++i) {
                 zcopy = vhost_net_zcopy_mask & (0x1 << i);
                 if (!zcopy)
                         continue;
@@ -183,12 +180,7 @@ int vhost_net_set_ubuf_info(struct vhost_net *n)
         return 0;
 
 err:
-        while (i--) {
-                zcopy = vhost_net_zcopy_mask & (0x1 << i);
-                if (!zcopy)
-                        continue;
-                kfree(n->vqs[i].ubuf_info);
-        }
+        vhost_net_clear_ubuf_info(n);
         return -ENOMEM;
 }
 
@@ -196,12 +188,12 @@ void vhost_net_vq_reset(struct vhost_net *n)
 {
         int i;
 
+        vhost_net_clear_ubuf_info(n);
+
         for (i = 0; i < VHOST_NET_VQ_MAX; i++) {
                 n->vqs[i].done_idx = 0;
                 n->vqs[i].upend_idx = 0;
                 n->vqs[i].ubufs = NULL;
-                kfree(n->vqs[i].ubuf_info);
-                n->vqs[i].ubuf_info = NULL;
                 n->vqs[i].vhost_hlen = 0;
                 n->vqs[i].sock_hlen = 0;
         }
@@ -436,7 +428,8 @@ static void handle_tx(struct vhost_net *net)
                                 kref_get(&ubufs->kref);
                         }
                         nvq->upend_idx = (nvq->upend_idx + 1) % UIO_MAXIOV;
-                }
+                } else
+                        msg.msg_control = NULL;
                 /* TODO: Check specific error and bomb out unless ENOBUFS? */
                 err = sock->ops->sendmsg(NULL, sock, &msg, len);
                 if (unlikely(err < 0)) {
@@ -1053,6 +1046,10 @@ static long vhost_net_set_owner(struct vhost_net *n)
         int r;
 
         mutex_lock(&n->dev.mutex);
+        if (vhost_dev_has_owner(&n->dev)) {
+                r = -EBUSY;
+                goto out;
+        }
         r = vhost_net_set_ubuf_info(n);
         if (r)
                 goto out;
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index beee7f5787e6..60aa5ad09a2f 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -344,13 +344,19 @@ static int vhost_attach_cgroups(struct vhost_dev *dev)
 }
 
 /* Caller should have device mutex */
+bool vhost_dev_has_owner(struct vhost_dev *dev)
+{
+        return dev->mm;
+}
+
+/* Caller should have device mutex */
 long vhost_dev_set_owner(struct vhost_dev *dev)
 {
         struct task_struct *worker;
         int err;
 
         /* Is there an owner already? */
-        if (dev->mm) {
+        if (vhost_dev_has_owner(dev)) {
                 err = -EBUSY;
                 goto err_mm;
         }
diff --git a/drivers/vhost/vhost.h b/drivers/vhost/vhost.h
index a7ad63592987..64adcf99ff33 100644
--- a/drivers/vhost/vhost.h
+++ b/drivers/vhost/vhost.h
@@ -133,6 +133,7 @@ struct vhost_dev {
 
 long vhost_dev_init(struct vhost_dev *, struct vhost_virtqueue **vqs, int nvqs);
 long vhost_dev_set_owner(struct vhost_dev *dev);
+bool vhost_dev_has_owner(struct vhost_dev *dev);
 long vhost_dev_check_owner(struct vhost_dev *);
 struct vhost_memory *vhost_dev_reset_owner_prepare(void);
 void vhost_dev_reset_owner(struct vhost_dev *, struct vhost_memory *);
diff --git a/drivers/xen/tmem.c b/drivers/xen/tmem.c
index cc072c66c766..0f0493c63371 100644
--- a/drivers/xen/tmem.c
+++ b/drivers/xen/tmem.c
@@ -379,10 +379,10 @@ static int xen_tmem_init(void)
 #ifdef CONFIG_FRONTSWAP
         if (tmem_enabled && frontswap) {
                 char *s = "";
-                struct frontswap_ops *old_ops =
-                        frontswap_register_ops(&tmem_frontswap_ops);
+                struct frontswap_ops *old_ops;
 
                 tmem_frontswap_poolid = -1;
+                old_ops = frontswap_register_ops(&tmem_frontswap_ops);
                 if (IS_ERR(old_ops) || old_ops) {
                         if (IS_ERR(old_ops))
                                 return PTR_ERR(old_ops);
diff --git a/fs/aio.c b/fs/aio.c
index 7fe5bdee1630..2bbcacf74d0c 100644
--- a/fs/aio.c
+++ b/fs/aio.c
@@ -141,9 +141,6 @@ static void aio_free_ring(struct kioctx *ctx)
         for (i = 0; i < ctx->nr_pages; i++)
                 put_page(ctx->ring_pages[i]);
 
-        if (ctx->mmap_size)
-                vm_munmap(ctx->mmap_base, ctx->mmap_size);
-
         if (ctx->ring_pages && ctx->ring_pages != ctx->internal_pages)
                 kfree(ctx->ring_pages);
 }
@@ -322,11 +319,6 @@ static void free_ioctx(struct kioctx *ctx)
 
         aio_free_ring(ctx);
 
-        spin_lock(&aio_nr_lock);
-        BUG_ON(aio_nr - ctx->max_reqs > aio_nr);
-        aio_nr -= ctx->max_reqs;
-        spin_unlock(&aio_nr_lock);
-
         pr_debug("freeing %p\n", ctx);
 
         /*
@@ -435,17 +427,24 @@ static void kill_ioctx(struct kioctx *ctx)
 {
         if (!atomic_xchg(&ctx->dead, 1)) {
                 hlist_del_rcu(&ctx->list);
-                /* Between hlist_del_rcu() and dropping the initial ref */
-                synchronize_rcu();
 
                 /*
-                 * We can't punt to workqueue here because put_ioctx() ->
-                 * free_ioctx() will unmap the ringbuffer, and that has to be
-                 * done in the original process's context. kill_ioctx_rcu/work()
-                 * exist for exit_aio(), as in that path free_ioctx() won't do
-                 * the unmap.
+                 * It'd be more correct to do this in free_ioctx(), after all
+                 * the outstanding kiocbs have finished - but by then io_destroy
+                 * has already returned, so io_setup() could potentially return
+                 * -EAGAIN with no ioctxs actually in use (as far as userspace
+                 *  could tell).
                  */
-                kill_ioctx_work(&ctx->rcu_work);
+                spin_lock(&aio_nr_lock);
+                BUG_ON(aio_nr - ctx->max_reqs > aio_nr);
+                aio_nr -= ctx->max_reqs;
+                spin_unlock(&aio_nr_lock);
+
+                if (ctx->mmap_size)
+                        vm_munmap(ctx->mmap_base, ctx->mmap_size);
+
+                /* Between hlist_del_rcu() and dropping the initial ref */
+                call_rcu(&ctx->rcu_head, kill_ioctx_rcu);
         }
 }
 
@@ -495,10 +494,7 @@ void exit_aio(struct mm_struct *mm)
                  */
                 ctx->mmap_size = 0;
 
-                if (!atomic_xchg(&ctx->dead, 1)) {
-                        hlist_del_rcu(&ctx->list);
-                        call_rcu(&ctx->rcu_head, kill_ioctx_rcu);
-                }
+                kill_ioctx(ctx);
         }
 }
 
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index e7b3cb5286a5..b8b60b660c8f 100644
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -2859,8 +2859,8 @@ fail_qgroup:
         btrfs_free_qgroup_config(fs_info);
 fail_trans_kthread:
         kthread_stop(fs_info->transaction_kthread);
-        del_fs_roots(fs_info);
         btrfs_cleanup_transaction(fs_info->tree_root);
+        del_fs_roots(fs_info);
 fail_cleaner:
         kthread_stop(fs_info->cleaner_kthread);
 
@@ -3512,15 +3512,15 @@ int close_ctree(struct btrfs_root *root)
                        percpu_counter_sum(&fs_info->delalloc_bytes));
         }
 
-        free_root_pointers(fs_info, 1);
-
         btrfs_free_block_groups(fs_info);
 
+        btrfs_stop_all_workers(fs_info);
+
         del_fs_roots(fs_info);
 
-        iput(fs_info->btree_inode);
+        free_root_pointers(fs_info, 1);
 
-        btrfs_stop_all_workers(fs_info);
+        iput(fs_info->btree_inode);
 
 #ifdef CONFIG_BTRFS_FS_CHECK_INTEGRITY
         if (btrfs_test_opt(root, CHECK_INTEGRITY))
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index af978f7682b3..17f3064b4a3e 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -8012,6 +8012,9 @@ int btrfs_drop_inode(struct inode *inode)
 {
         struct btrfs_root *root = BTRFS_I(inode)->root;
 
+        if (root == NULL)
+                return 1;
+
         /* the snap/subvol tree is on deleting */
         if (btrfs_root_refs(&root->root_item) == 0 &&
             root != root->fs_info->tree_root)
diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c
index 395b82031a42..4febca4fc2de 100644
--- a/fs/btrfs/relocation.c
+++ b/fs/btrfs/relocation.c
@@ -4082,7 +4082,7 @@ out:
         return inode;
 }
 
-static struct reloc_control *alloc_reloc_control(void)
+static struct reloc_control *alloc_reloc_control(struct btrfs_fs_info *fs_info)
 {
         struct reloc_control *rc;
 
@@ -4093,7 +4093,8 @@ static struct reloc_control *alloc_reloc_control(void)
         INIT_LIST_HEAD(&rc->reloc_roots);
         backref_cache_init(&rc->backref_cache);
         mapping_tree_init(&rc->reloc_root_tree);
-        extent_io_tree_init(&rc->processed_blocks, NULL);
+        extent_io_tree_init(&rc->processed_blocks,
+                            fs_info->btree_inode->i_mapping);
         return rc;
 }
 
@@ -4110,7 +4111,7 @@ int btrfs_relocate_block_group(struct btrfs_root *extent_root, u64 group_start)
         int rw = 0;
         int err = 0;
 
-        rc = alloc_reloc_control();
+        rc = alloc_reloc_control(fs_info);
         if (!rc)
                 return -ENOMEM;
 
@@ -4311,7 +4312,7 @@ int btrfs_recover_relocation(struct btrfs_root *root)
         if (list_empty(&reloc_roots))
                 goto out;
 
-        rc = alloc_reloc_control();
+        rc = alloc_reloc_control(root->fs_info);
         if (!rc) {
                 err = -ENOMEM;
                 goto out;
diff --git a/fs/ceph/locks.c b/fs/ceph/locks.c
index 202dd3d68be0..ebbf680378e2 100644
--- a/fs/ceph/locks.c
+++ b/fs/ceph/locks.c
@@ -191,27 +191,23 @@ void ceph_count_locks(struct inode *inode, int *fcntl_count, int *flock_count)
 }
 
 /**
- * Encode the flock and fcntl locks for the given inode into the pagelist.
- * Format is: #fcntl locks, sequential fcntl locks, #flock locks,
- * sequential flock locks.
- * Must be called with lock_flocks() already held.
- * If we encounter more of a specific lock type than expected,
- * we return the value 1.
+ * Encode the flock and fcntl locks for the given inode into the ceph_filelock
+ * array. Must be called with lock_flocks() already held.
+ * If we encounter more of a specific lock type than expected, return -ENOSPC.
  */
-int ceph_encode_locks(struct inode *inode, struct ceph_pagelist *pagelist,
-                      int num_fcntl_locks, int num_flock_locks)
+int ceph_encode_locks_to_buffer(struct inode *inode,
+                                struct ceph_filelock *flocks,
+                                int num_fcntl_locks, int num_flock_locks)
 {
         struct file_lock *lock;
-        struct ceph_filelock cephlock;
         int err = 0;
         int seen_fcntl = 0;
         int seen_flock = 0;
+        int l = 0;
 
         dout("encoding %d flock and %d fcntl locks", num_flock_locks,
              num_fcntl_locks);
-        err = ceph_pagelist_append(pagelist, &num_fcntl_locks, sizeof(u32));
-        if (err)
-                goto fail;
+
         for (lock = inode->i_flock; lock != NULL; lock = lock->fl_next) {
                 if (lock->fl_flags & FL_POSIX) {
                         ++seen_fcntl;
@@ -219,19 +215,12 @@ int ceph_encode_locks(struct inode *inode, struct ceph_pagelist *pagelist,
                                 err = -ENOSPC;
                                 goto fail;
                         }
-                        err = lock_to_ceph_filelock(lock, &cephlock);
+                        err = lock_to_ceph_filelock(lock, &flocks[l]);
                         if (err)
                                 goto fail;
-                        err = ceph_pagelist_append(pagelist, &cephlock,
-                                           sizeof(struct ceph_filelock));
+                        ++l;
                 }
-                if (err)
-                        goto fail;
         }
-
-        err = ceph_pagelist_append(pagelist, &num_flock_locks, sizeof(u32));
-        if (err)
-                goto fail;
         for (lock = inode->i_flock; lock != NULL; lock = lock->fl_next) {
                 if (lock->fl_flags & FL_FLOCK) {
                         ++seen_flock;
@@ -239,19 +228,51 @@ int ceph_encode_locks(struct inode *inode, struct ceph_pagelist *pagelist,
                                 err = -ENOSPC;
                                 goto fail;
                         }
-                        err = lock_to_ceph_filelock(lock, &cephlock);
+                        err = lock_to_ceph_filelock(lock, &flocks[l]);
                         if (err)
                                 goto fail;
-                        err = ceph_pagelist_append(pagelist, &cephlock,
-                                           sizeof(struct ceph_filelock));
+                        ++l;
                 }
-                if (err)
-                        goto fail;
         }
 fail:
         return err;
 }
 
+/**
+ * Copy the encoded flock and fcntl locks into the pagelist.
+ * Format is: #fcntl locks, sequential fcntl locks, #flock locks,
+ * sequential flock locks.
+ * Returns zero on success.
+ */
+int ceph_locks_to_pagelist(struct ceph_filelock *flocks,
+                           struct ceph_pagelist *pagelist,
+                           int num_fcntl_locks, int num_flock_locks)
+{
+        int err = 0;
+        __le32 nlocks;
+
+        nlocks = cpu_to_le32(num_fcntl_locks);
+        err = ceph_pagelist_append(pagelist, &nlocks, sizeof(nlocks));
+        if (err)
+                goto out_fail;
+
+        err = ceph_pagelist_append(pagelist, flocks,
+                                   num_fcntl_locks * sizeof(*flocks));
+        if (err)
+                goto out_fail;
+
+        nlocks = cpu_to_le32(num_flock_locks);
+        err = ceph_pagelist_append(pagelist, &nlocks, sizeof(nlocks));
+        if (err)
+                goto out_fail;
+
+        err = ceph_pagelist_append(pagelist,
+                                   &flocks[num_fcntl_locks],
+                                   num_flock_locks * sizeof(*flocks));
+out_fail:
+        return err;
+}
+
 /*
  * Given a pointer to a lock, convert it to a ceph filelock
  */
diff --git a/fs/ceph/mds_client.c b/fs/ceph/mds_client.c
index 4f22671a5bd4..4d2920304be8 100644
--- a/fs/ceph/mds_client.c
+++ b/fs/ceph/mds_client.c
@@ -2478,39 +2478,44 @@ static int encode_caps_cb(struct inode *inode, struct ceph_cap *cap,
 
         if (recon_state->flock) {
                 int num_fcntl_locks, num_flock_locks;
-                struct ceph_pagelist_cursor trunc_point;
-
-                ceph_pagelist_set_cursor(pagelist, &trunc_point);
-                do {
-                        lock_flocks();
-                        ceph_count_locks(inode, &num_fcntl_locks,
-                                         &num_flock_locks);
-                        rec.v2.flock_len = (2*sizeof(u32) +
-                                            (num_fcntl_locks+num_flock_locks) *
-                                            sizeof(struct ceph_filelock));
-                        unlock_flocks();
-
-                        /* pre-alloc pagelist */
-                        ceph_pagelist_truncate(pagelist, &trunc_point);
-                        err = ceph_pagelist_append(pagelist, &rec, reclen);
-                        if (!err)
-                                err = ceph_pagelist_reserve(pagelist,
-                                                            rec.v2.flock_len);
-
-                        /* encode locks */
-                        if (!err) {
-                                lock_flocks();
-                                err = ceph_encode_locks(inode,
-                                                        pagelist,
-                                                        num_fcntl_locks,
-                                                        num_flock_locks);
-                                unlock_flocks();
-                        }
-                } while (err == -ENOSPC);
+                struct ceph_filelock *flocks;
+
+encode_again:
+                lock_flocks();
+                ceph_count_locks(inode, &num_fcntl_locks, &num_flock_locks);
+                unlock_flocks();
+                flocks = kmalloc((num_fcntl_locks+num_flock_locks) *
+                                 sizeof(struct ceph_filelock), GFP_NOFS);
+                if (!flocks) {
+                        err = -ENOMEM;
+                        goto out_free;
+                }
+                lock_flocks();
+                err = ceph_encode_locks_to_buffer(inode, flocks,
+                                                  num_fcntl_locks,
+                                                  num_flock_locks);
+                unlock_flocks();
+                if (err) {
+                        kfree(flocks);
+                        if (err == -ENOSPC)
+                                goto encode_again;
+                        goto out_free;
+                }
+                /*
+                 * number of encoded locks is stable, so copy to pagelist
+                 */
+                rec.v2.flock_len = cpu_to_le32(2*sizeof(u32) +
+                                    (num_fcntl_locks+num_flock_locks) *
+                                    sizeof(struct ceph_filelock));
+                err = ceph_pagelist_append(pagelist, &rec, reclen);
+                if (!err)
+                        err = ceph_locks_to_pagelist(flocks, pagelist,
+                                                     num_fcntl_locks,
+                                                     num_flock_locks);
+                kfree(flocks);
         } else {
                 err = ceph_pagelist_append(pagelist, &rec, reclen);
         }
-
 out_free:
         kfree(path);
 out_dput:
diff --git a/fs/ceph/super.h b/fs/ceph/super.h
index 8696be2ff679..7ccfdb4aea2e 100644
--- a/fs/ceph/super.h
+++ b/fs/ceph/super.h
@@ -822,8 +822,13 @@ extern const struct export_operations ceph_export_ops;
 extern int ceph_lock(struct file *file, int cmd, struct file_lock *fl);
 extern int ceph_flock(struct file *file, int cmd, struct file_lock *fl);
 extern void ceph_count_locks(struct inode *inode, int *p_num, int *f_num);
-extern int ceph_encode_locks(struct inode *i, struct ceph_pagelist *p,
-                             int p_locks, int f_locks);
+extern int ceph_encode_locks_to_buffer(struct inode *inode,
+                                       struct ceph_filelock *flocks,
+                                       int num_fcntl_locks,
+                                       int num_flock_locks);
+extern int ceph_locks_to_pagelist(struct ceph_filelock *flocks,
+                                  struct ceph_pagelist *pagelist,
+                                  int num_fcntl_locks, int num_flock_locks);
 extern int lock_to_ceph_filelock(struct file_lock *fl, struct ceph_filelock *c);
 
 /* debugfs.c */
diff --git a/fs/file_table.c b/fs/file_table.c
index cd4d87a82951..485dc0eddd67 100644
--- a/fs/file_table.c
+++ b/fs/file_table.c
@@ -306,17 +306,18 @@ void fput(struct file *file)
 {
         if (atomic_long_dec_and_test(&file->f_count)) {
                 struct task_struct *task = current;
+                unsigned long flags;
+
                 file_sb_list_del(file);
-                if (unlikely(in_interrupt() || task->flags & PF_KTHREAD)) {
-                        unsigned long flags;
-                        spin_lock_irqsave(&delayed_fput_lock, flags);
-                        list_add(&file->f_u.fu_list, &delayed_fput_list);
-                        schedule_work(&delayed_fput_work);
-                        spin_unlock_irqrestore(&delayed_fput_lock, flags);
-                        return;
+                if (likely(!in_interrupt() && !(task->flags & PF_KTHREAD))) {
+                        init_task_work(&file->f_u.fu_rcuhead, ____fput);
+                        if (!task_work_add(task, &file->f_u.fu_rcuhead, true))
+                                return;
                 }
-                init_task_work(&file->f_u.fu_rcuhead, ____fput);
-                task_work_add(task, &file->f_u.fu_rcuhead, true);
+                spin_lock_irqsave(&delayed_fput_lock, flags);
+                list_add(&file->f_u.fu_list, &delayed_fput_list);
+                schedule_work(&delayed_fput_work);
+                spin_unlock_irqrestore(&delayed_fput_lock, flags);
         }
 }
 
diff --git a/fs/namei.c b/fs/namei.c
index 85e40d1c0a8f..9ed9361223c0 100644
--- a/fs/namei.c
+++ b/fs/namei.c
@@ -1976,7 +1976,7 @@ static int path_lookupat(int dfd, const char *name,
                 err = complete_walk(nd);
 
         if (!err && nd->flags & LOOKUP_DIRECTORY) {
-                if (!nd->inode->i_op->lookup) {
+                if (!can_lookup(nd->inode)) {
                         path_put(&nd->path);
                         err = -ENOTDIR;
                 }
@@ -2850,7 +2850,7 @@ finish_lookup:
         if ((open_flag & O_CREAT) && S_ISDIR(nd->inode->i_mode))
                 goto out;
         error = -ENOTDIR;
-        if ((nd->flags & LOOKUP_DIRECTORY) && !nd->inode->i_op->lookup)
+        if ((nd->flags & LOOKUP_DIRECTORY) && !can_lookup(nd->inode))
                 goto out;
         audit_inode(name, nd->path.dentry, 0);
 finish_open:
diff --git a/fs/ncpfs/dir.c b/fs/ncpfs/dir.c
index 816326093656..6792ce11f2bf 100644
--- a/fs/ncpfs/dir.c
+++ b/fs/ncpfs/dir.c
@@ -1029,15 +1029,6 @@ static int ncp_rmdir(struct inode *dir, struct dentry *dentry)
         DPRINTK("ncp_rmdir: removing %s/%s\n",
                 dentry->d_parent->d_name.name, dentry->d_name.name);
 
-        /*
-         * fail with EBUSY if there are still references to this
-         * directory.
-         */
-        dentry_unhash(dentry);
-        error = -EBUSY;
-        if (!d_unhashed(dentry))
-                goto out;
-
         len = sizeof(__name);
         error = ncp_io2vol(server, __name, &len, dentry->d_name.name,
                            dentry->d_name.len, !ncp_preserve_case(dir));
diff --git a/fs/ocfs2/dlm/dlmrecovery.c b/fs/ocfs2/dlm/dlmrecovery.c
index b3fdd1a323d6..e68588e6b1e8 100644
--- a/fs/ocfs2/dlm/dlmrecovery.c
+++ b/fs/ocfs2/dlm/dlmrecovery.c
@@ -1408,6 +1408,7 @@ int dlm_mig_lockres_handler(struct o2net_msg *msg, u32 len, void *data,
                                      mres->lockname_len, mres->lockname);
                                 ret = -EFAULT;
                                 spin_unlock(&res->spinlock);
+                                dlm_lockres_put(res);
                                 goto leave;
                         }
                         res->state |= DLM_LOCK_RES_MIGRATING;
diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c
index 04ee1b57c243..b4a5cdf9dbc5 100644
--- a/fs/ocfs2/namei.c
+++ b/fs/ocfs2/namei.c
@@ -947,7 +947,7 @@ leave:
         ocfs2_free_dir_lookup_result(&orphan_insert);
         ocfs2_free_dir_lookup_result(&lookup);
 
-        if (status)
+        if (status && (status != -ENOTEMPTY))
                 mlog_errno(status);
 
         return status;
@@ -2216,7 +2216,7 @@ out:
 
         brelse(orphan_dir_bh);
 
-        return 0;
+        return ret;
 }
 
 int ocfs2_create_inode_in_orphan(struct inode *dir,
diff --git a/fs/proc/kmsg.c b/fs/proc/kmsg.c
index bd4b5a740ff1..bdfabdaefdce 100644
--- a/fs/proc/kmsg.c
+++ b/fs/proc/kmsg.c
@@ -21,12 +21,12 @@ extern wait_queue_head_t log_wait;
 
 static int kmsg_open(struct inode * inode, struct file * file)
 {
-        return do_syslog(SYSLOG_ACTION_OPEN, NULL, 0, SYSLOG_FROM_FILE);
+        return do_syslog(SYSLOG_ACTION_OPEN, NULL, 0, SYSLOG_FROM_PROC);
 }
 
 static int kmsg_release(struct inode * inode, struct file * file)
 {
-        (void) do_syslog(SYSLOG_ACTION_CLOSE, NULL, 0, SYSLOG_FROM_FILE);
+        (void) do_syslog(SYSLOG_ACTION_CLOSE, NULL, 0, SYSLOG_FROM_PROC);
         return 0;
 }
 
@@ -34,15 +34,15 @@ static ssize_t kmsg_read(struct file *file, char __user *buf,
                          size_t count, loff_t *ppos)
 {
         if ((file->f_flags & O_NONBLOCK) &&
-            !do_syslog(SYSLOG_ACTION_SIZE_UNREAD, NULL, 0, SYSLOG_FROM_FILE))
+            !do_syslog(SYSLOG_ACTION_SIZE_UNREAD, NULL, 0, SYSLOG_FROM_PROC))
                 return -EAGAIN;
-        return do_syslog(SYSLOG_ACTION_READ, buf, count, SYSLOG_FROM_FILE);
+        return do_syslog(SYSLOG_ACTION_READ, buf, count, SYSLOG_FROM_PROC);
 }
 
 static unsigned int kmsg_poll(struct file *file, poll_table *wait)
 {
         poll_wait(file, &log_wait, wait);
-        if (do_syslog(SYSLOG_ACTION_SIZE_UNREAD, NULL, 0, SYSLOG_FROM_FILE))
+        if (do_syslog(SYSLOG_ACTION_SIZE_UNREAD, NULL, 0, SYSLOG_FROM_PROC))
                 return POLLIN | POLLRDNORM;
         return 0;
 }
diff --git a/fs/xfs/xfs_attr_leaf.h b/fs/xfs/xfs_attr_leaf.h
index f9d7846097e2..444a7704596c 100644
--- a/fs/xfs/xfs_attr_leaf.h
+++ b/fs/xfs/xfs_attr_leaf.h
@@ -128,6 +128,7 @@ struct xfs_attr3_leaf_hdr {
         __u8                    holes;
         __u8                    pad1;
         struct xfs_attr_leaf_map freemap[XFS_ATTR_LEAF_MAPSIZE];
+        __be32                  pad2;           /* 64 bit alignment */
 };
 
 #define XFS_ATTR3_LEAF_CRC_OFF  (offsetof(struct xfs_attr3_leaf_hdr, info.crc))
diff --git a/fs/xfs/xfs_btree.c b/fs/xfs/xfs_btree.c
index 8804b8a3c310..0903960410a2 100644
--- a/fs/xfs/xfs_btree.c
+++ b/fs/xfs/xfs_btree.c
@@ -2544,7 +2544,17 @@ xfs_btree_new_iroot(
         if (error)
                 goto error0;
 
+        /*
+         * we can't just memcpy() the root in for CRC enabled btree blocks.
+         * In that case have to also ensure the blkno remains correct
+         */
         memcpy(cblock, block, xfs_btree_block_len(cur));
+        if (cur->bc_flags & XFS_BTREE_CRC_BLOCKS) {
+                if (cur->bc_flags & XFS_BTREE_LONG_PTRS)
+                        cblock->bb_u.l.bb_blkno = cpu_to_be64(cbp->b_bn);
+                else
+                        cblock->bb_u.s.bb_blkno = cpu_to_be64(cbp->b_bn);
+        }
 
         be16_add_cpu(&block->bb_level, 1);
         xfs_btree_set_numrecs(block, 1);
diff --git a/fs/xfs/xfs_dir2_format.h b/fs/xfs/xfs_dir2_format.h
index 995f1f505a52..7826782b8d78 100644
--- a/fs/xfs/xfs_dir2_format.h
+++ b/fs/xfs/xfs_dir2_format.h
@@ -266,6 +266,7 @@ struct xfs_dir3_blk_hdr {
 struct xfs_dir3_data_hdr {
         struct xfs_dir3_blk_hdr hdr;
         xfs_dir2_data_free_t    best_free[XFS_DIR2_DATA_FD_COUNT];
+        __be32                  pad;    /* 64 bit alignment */
 };
 
 #define XFS_DIR3_DATA_CRC_OFF  offsetof(struct xfs_dir3_data_hdr, hdr.crc)
@@ -477,7 +478,7 @@ struct xfs_dir3_leaf_hdr {
         struct xfs_da3_blkinfo  info;           /* header for da routines */
         __be16                  count;          /* count of entries */
         __be16                  stale;          /* count of stale entries */
-        __be32                  pad;
+        __be32                  pad;            /* 64 bit alignment */
 };
 
 struct xfs_dir3_icleaf_hdr {
@@ -715,7 +716,7 @@ struct xfs_dir3_free_hdr {
         __be32                  firstdb;        /* db of first entry */
         __be32                  nvalid;         /* count of valid entries */
         __be32                  nused;          /* count of used entries */
-        __be32                  pad;            /* 64 bit alignment. */
+        __be32                  pad;            /* 64 bit alignment */
 };
 
 struct xfs_dir3_free {
diff --git a/fs/xfs/xfs_log_recover.c b/fs/xfs/xfs_log_recover.c
index 45a85ff84da1..7cf5e4eafe28 100644
--- a/fs/xfs/xfs_log_recover.c
+++ b/fs/xfs/xfs_log_recover.c
@@ -1845,7 +1845,13 @@ xlog_recover_do_inode_buffer(
         xfs_agino_t             *buffer_nextp;
 
         trace_xfs_log_recover_buf_inode_buf(mp->m_log, buf_f);
-        bp->b_ops = &xfs_inode_buf_ops;
+
+        /*
+         * Post recovery validation only works properly on CRC enabled
+         * filesystems.
+         */
+        if (xfs_sb_version_hascrc(&mp->m_sb))
+                bp->b_ops = &xfs_inode_buf_ops;
 
         inodes_per_buf = BBTOB(bp->b_io_length) >> mp->m_sb.sb_inodelog;
         for (i = 0; i < inodes_per_buf; i++) {
@@ -2205,7 +2211,16 @@ xlog_recover_do_reg_buffer(
         /* Shouldn't be any more regions */
         ASSERT(i == item->ri_total);
 
-        xlog_recovery_validate_buf_type(mp, bp, buf_f);
+        /*
+         * We can only do post recovery validation on items on CRC enabled
+         * fielsystems as we need to know when the buffer was written to be able
+         * to determine if we should have replayed the item. If we replay old
+         * metadata over a newer buffer, then it will enter a temporarily
+         * inconsistent state resulting in verification failures. Hence for now
+         * just avoid the verification stage for non-crc filesystems
+         */
+        if (xfs_sb_version_hascrc(&mp->m_sb))
+                xlog_recovery_validate_buf_type(mp, bp, buf_f);
 }
 
 /*
diff --git a/fs/xfs/xfs_mount.c b/fs/xfs/xfs_mount.c
index f6bfbd734669..e8e310c05097 100644
--- a/fs/xfs/xfs_mount.c
+++ b/fs/xfs/xfs_mount.c
@@ -314,7 +314,8 @@ STATIC int
 xfs_mount_validate_sb(
         xfs_mount_t     *mp,
         xfs_sb_t        *sbp,
-        bool            check_inprogress)
+        bool            check_inprogress,
+        bool            check_version)
 {
 
         /*
@@ -337,9 +338,10 @@ xfs_mount_validate_sb(
 
         /*
          * Version 5 superblock feature mask validation. Reject combinations the
-         * kernel cannot support up front before checking anything else.
+         * kernel cannot support up front before checking anything else. For
+         * write validation, we don't need to check feature masks.
          */
-        if (XFS_SB_VERSION_NUM(sbp) == XFS_SB_VERSION_5) {
+        if (check_version && XFS_SB_VERSION_NUM(sbp) == XFS_SB_VERSION_5) {
                 xfs_alert(mp,
 "Version 5 superblock detected. This kernel has EXPERIMENTAL support enabled!\n"
 "Use of these features in this kernel is at your own risk!");
@@ -675,7 +677,8 @@ xfs_sb_to_disk(
 
 static int
 xfs_sb_verify(
-        struct xfs_buf  *bp)
+        struct xfs_buf  *bp,
+        bool            check_version)
 {
         struct xfs_mount *mp = bp->b_target->bt_mount;
         struct xfs_sb   sb;
@@ -686,7 +689,8 @@ xfs_sb_verify(
          * Only check the in progress field for the primary superblock as
          * mkfs.xfs doesn't clear it from secondary superblocks.
          */
-        return xfs_mount_validate_sb(mp, &sb, bp->b_bn == XFS_SB_DADDR);
+        return xfs_mount_validate_sb(mp, &sb, bp->b_bn == XFS_SB_DADDR,
+                                     check_version);
 }
 
 /*
@@ -719,7 +723,7 @@ xfs_sb_read_verify(
                         goto out_error;
                 }
         }
-        error = xfs_sb_verify(bp);
+        error = xfs_sb_verify(bp, true);
 
 out_error:
         if (error) {
@@ -758,7 +762,7 @@ xfs_sb_write_verify(
         struct xfs_buf_log_item *bip = bp->b_fspriv;
         int                     error;
 
-        error = xfs_sb_verify(bp);
+        error = xfs_sb_verify(bp, false);
         if (error) {
                 XFS_CORRUPTION_ERROR(__func__, XFS_ERRLEVEL_LOW, mp, bp->b_addr);
                 xfs_buf_ioerror(bp, error);
diff --git a/include/asm-generic/kvm_para.h b/include/asm-generic/kvm_para.h
index 9d96605f160a..fa25becbdcaf 100644
--- a/include/asm-generic/kvm_para.h
+++ b/include/asm-generic/kvm_para.h
@@ -18,4 +18,9 @@ static inline unsigned int kvm_arch_para_features(void)
         return 0;
 }
 
+static inline bool kvm_para_available(void)
+{
+        return false;
+}
+
 #endif
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c6f6e0839b61..9f3c7e81270a 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -175,6 +175,8 @@ extern struct bus_type cpu_subsys;
 
 extern void get_online_cpus(void);
 extern void put_online_cpus(void);
+extern void cpu_hotplug_disable(void);
+extern void cpu_hotplug_enable(void);
 #define hotcpu_notifier(fn, pri)        cpu_notifier(fn, pri)
 #define register_hotcpu_notifier(nb)    register_cpu_notifier(nb)
 #define unregister_hotcpu_notifier(nb)  unregister_cpu_notifier(nb)
@@ -198,6 +200,8 @@ static inline void cpu_hotplug_driver_unlock(void)
 
 #define get_online_cpus()       do { } while (0)
 #define put_online_cpus()       do { } while (0)
+#define cpu_hotplug_disable()   do { } while (0)
+#define cpu_hotplug_enable()    do { } while (0)
 #define hotcpu_notifier(fn, pri)        do { (void)(fn); } while (0)
 /* These aren't inline functions due to a GCC bug. */
 #define register_hotcpu_notifier(nb)    ({ (void)(nb); 0; })
diff --git a/include/linux/filter.h b/include/linux/filter.h
index c050dcc322a4..f65f5a69db8f 100644
--- a/include/linux/filter.h
+++ b/include/linux/filter.h
@@ -46,6 +46,7 @@ extern int sk_attach_filter(struct sock_fprog *fprog, struct sock *sk);
 extern int sk_detach_filter(struct sock *sk);
 extern int sk_chk_filter(struct sock_filter *filter, unsigned int flen);
 extern int sk_get_filter(struct sock *sk, struct sock_filter __user *filter, unsigned len);
+extern void sk_decode_filter(struct sock_filter *filt, struct sock_filter *to);
 
 #ifdef CONFIG_BPF_JIT
 #include <stdarg.h>
diff --git a/include/linux/if_team.h b/include/linux/if_team.h
index 4474557904f6..16fae6436d0e 100644
--- a/include/linux/if_team.h
+++ b/include/linux/if_team.h
@@ -249,12 +249,12 @@ team_get_first_port_txable_rcu(struct team *team, struct team_port *port)
                 return port;
         cur = port;
         list_for_each_entry_continue_rcu(cur, &team->port_list, list)
-                if (team_port_txable(port))
+                if (team_port_txable(cur))
                         return cur;
         list_for_each_entry_rcu(cur, &team->port_list, list) {
                 if (cur == port)
                         break;
-                if (team_port_txable(port))
+                if (team_port_txable(cur))
                         return cur;
         }
         return NULL;
diff --git a/include/linux/math64.h b/include/linux/math64.h
index b8ba85544721..2913b86eb12a 100644
--- a/include/linux/math64.h
+++ b/include/linux/math64.h
@@ -6,7 +6,8 @@
 
 #if BITS_PER_LONG == 64
 
-#define div64_long(x,y) div64_s64((x),(y))
+#define div64_long(x, y) div64_s64((x), (y))
+#define div64_ul(x, y)   div64_u64((x), (y))
 
 /**
  * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
@@ -47,7 +48,8 @@ static inline s64 div64_s64(s64 dividend, s64 divisor)
 
 #elif BITS_PER_LONG == 32
 
-#define div64_long(x,y) div_s64((x),(y))
+#define div64_long(x, y) div_s64((x), (y))
+#define div64_ul(x, y)   div_u64((x), (y))
 
 #ifndef div_u64_rem
 static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index b253f77a7ddf..2d8d69432813 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -17,10 +17,13 @@
 #define __GPIO_RCAR_H__
 
 struct gpio_rcar_config {
-        unsigned int gpio_base;
+        int gpio_base;
         unsigned int irq_base;
         unsigned int number_of_pins;
         const char *pctl_name;
+        unsigned has_both_edge_trigger:1;
 };
 
+#define RCAR_GP_PIN(bank, pin)          (((bank) * 32) + (pin))
+
 #endif /* __GPIO_RCAR_H__ */
diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
index 5951e3f38878..26806775b11b 100644
--- a/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@ -111,6 +111,9 @@ static inline struct page *sg_page(struct scatterlist *sg)
 static inline void sg_set_buf(struct scatterlist *sg, const void *buf,
                               unsigned int buflen)
 {
+#ifdef CONFIG_DEBUG_SG
+        BUG_ON(!virt_addr_valid(buf));
+#endif
         sg_set_page(sg, virt_to_page(buf), buflen, offset_in_page(buf));
 }
 
diff --git a/include/linux/smp.h b/include/linux/smp.h
index e6564c1dc552..c8488763277f 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -11,6 +11,7 @@
 #include <linux/list.h>
 #include <linux/cpumask.h>
 #include <linux/init.h>
+#include <linux/irqflags.h>
 
 extern void cpu_idle(void);
 
@@ -139,13 +140,17 @@ static inline int up_smp_call_function(smp_call_func_t func, void *info)
 }
 #define smp_call_function(func, info, wait) \
                         (up_smp_call_function(func, info))
-#define on_each_cpu(func,info,wait)             \
-        ({                                      \
-                local_irq_disable();            \
-                func(info);                     \
-                local_irq_enable();             \
-                0;                              \
-        })
+
+static inline int on_each_cpu(smp_call_func_t func, void *info, int wait)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        func(info);
+        local_irq_restore(flags);
+        return 0;
+}
+
 /*
  * Note we still need to test the mask even for UP
  * because we actually can get an empty mask from
diff --git a/include/linux/swapops.h b/include/linux/swapops.h
index 47ead515c811..c5fd30d2a415 100644
--- a/include/linux/swapops.h
+++ b/include/linux/swapops.h
@@ -137,6 +137,7 @@ static inline void make_migration_entry_read(swp_entry_t *entry)
 
 extern void migration_entry_wait(struct mm_struct *mm, pmd_t *pmd,
                                         unsigned long address);
+extern void migration_entry_wait_huge(struct mm_struct *mm, pte_t *pte);
 #else
 
 #define make_migration_entry(page, write) swp_entry(0, 0)
@@ -148,6 +149,8 @@ static inline int is_migration_entry(swp_entry_t swp)
 static inline void make_migration_entry_read(swp_entry_t *entryp) { }
 static inline void migration_entry_wait(struct mm_struct *mm, pmd_t *pmd,
                                          unsigned long address) { }
+static inline void migration_entry_wait_huge(struct mm_struct *mm,
+                                        pte_t *pte) { }
 static inline int is_write_migration_entry(swp_entry_t entry)
 {
         return 0;
diff --git a/include/linux/syslog.h b/include/linux/syslog.h
index 38911391a139..98a3153c0f96 100644
--- a/include/linux/syslog.h
+++ b/include/linux/syslog.h
@@ -44,8 +44,8 @@
 /* Return size of the log buffer */
 #define SYSLOG_ACTION_SIZE_BUFFER   10
 
-#define SYSLOG_FROM_CALL 0
-#define SYSLOG_FROM_FILE 1
+#define SYSLOG_FROM_READER           0
+#define SYSLOG_FROM_PROC             1
 
 int do_syslog(int type, char __user *buf, int count, bool from_file);
 
diff --git a/include/linux/tracepoint.h b/include/linux/tracepoint.h
index 2f322c38bd4d..f8e084d0fc77 100644
--- a/include/linux/tracepoint.h
+++ b/include/linux/tracepoint.h
@@ -145,8 +145,8 @@ static inline void tracepoint_synchronize_unregister(void)
                                 TP_PROTO(data_proto),                   \
                                 TP_ARGS(data_args),                     \
                                 TP_CONDITION(cond),                     \
-                                rcu_idle_exit(),                        \
-                                rcu_idle_enter());                      \
+                                rcu_irq_enter(),                        \
+                                rcu_irq_exit());                        \
         }
 #else
 #define __DECLARE_TRACE_RCU(name, proto, args, cond, data_proto, data_args)
diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index 35a57cd1704c..7cb6d360d147 100644
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -1117,6 +1117,7 @@ void hci_sock_dev_event(struct hci_dev *hdev, int event);
 int mgmt_control(struct sock *sk, struct msghdr *msg, size_t len);
 int mgmt_index_added(struct hci_dev *hdev);
 int mgmt_index_removed(struct hci_dev *hdev);
+int mgmt_set_powered_failed(struct hci_dev *hdev, int err);
 int mgmt_powered(struct hci_dev *hdev, u8 powered);
 int mgmt_discoverable(struct hci_dev *hdev, u8 discoverable);
 int mgmt_connectable(struct hci_dev *hdev, u8 connectable);
diff --git a/include/net/bluetooth/mgmt.h b/include/net/bluetooth/mgmt.h
index 22980a7c3873..9944c3e68c5d 100644
--- a/include/net/bluetooth/mgmt.h
+++ b/include/net/bluetooth/mgmt.h
@@ -42,6 +42,7 @@
 #define MGMT_STATUS_NOT_POWERED         0x0f
 #define MGMT_STATUS_CANCELLED           0x10
 #define MGMT_STATUS_INVALID_INDEX       0x11
+#define MGMT_STATUS_RFKILLED            0x12
 
 struct mgmt_hdr {
         __le16  opcode;
diff --git a/include/net/ip_tunnels.h b/include/net/ip_tunnels.h
index 4b6f0b28f41f..09b1360e10bf 100644
--- a/include/net/ip_tunnels.h
+++ b/include/net/ip_tunnels.h
@@ -95,10 +95,10 @@ struct ip_tunnel_net {
 int ip_tunnel_init(struct net_device *dev);
 void ip_tunnel_uninit(struct net_device *dev);
 void  ip_tunnel_dellink(struct net_device *dev, struct list_head *head);
-int __net_init ip_tunnel_init_net(struct net *net, int ip_tnl_net_id,
-                                  struct rtnl_link_ops *ops, char *devname);
+int ip_tunnel_init_net(struct net *net, int ip_tnl_net_id,
+                       struct rtnl_link_ops *ops, char *devname);
 
-void __net_exit ip_tunnel_delete_net(struct ip_tunnel_net *itn);
+void ip_tunnel_delete_net(struct ip_tunnel_net *itn);
 
 void ip_tunnel_xmit(struct sk_buff *skb, struct net_device *dev,
                     const struct iphdr *tnl_params);
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index d4609029f014..385c6329a967 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -450,7 +450,8 @@ enum snd_soc_dapm_type {
         snd_soc_dapm_aif_in,            /* audio interface input */
         snd_soc_dapm_aif_out,           /* audio interface output */
         snd_soc_dapm_siggen,            /* signal generator */
-        snd_soc_dapm_dai,               /* link to DAI structure */
+        snd_soc_dapm_dai_in,            /* link to DAI structure */
+        snd_soc_dapm_dai_out,
         snd_soc_dapm_dai_link,          /* link between two DAI structures */
 };
 
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index a5c86fc34a37..d88c8ee00c8b 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -783,6 +783,7 @@ struct kvm_dirty_tlb {
 #define KVM_REG_IA64            0x3000000000000000ULL
 #define KVM_REG_ARM             0x4000000000000000ULL
 #define KVM_REG_S390            0x5000000000000000ULL
+#define KVM_REG_MIPS            0x7000000000000000ULL
 
 #define KVM_REG_SIZE_SHIFT      52
 #define KVM_REG_SIZE_MASK       0x00f0000000000000ULL
diff --git a/init/Kconfig b/init/Kconfig
index 9d3a7887a6d3..2d9b83104dcf 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -431,6 +431,7 @@ choice
 config TREE_RCU
         bool "Tree-based hierarchical RCU"
         depends on !PREEMPT && SMP
+        select IRQ_WORK
         help
           This option selects the RCU implementation that is
           designed for very large SMP system with hundreds or
diff --git a/kernel/audit.c b/kernel/audit.c
index 21c7fa615bd3..91e53d04b6a9 100644
--- a/kernel/audit.c
+++ b/kernel/audit.c
@@ -1056,7 +1056,7 @@ static inline void audit_get_stamp(struct audit_context *ctx,
 static void wait_for_auditd(unsigned long sleep_time)
 {
         DECLARE_WAITQUEUE(wait, current);
-        set_current_state(TASK_INTERRUPTIBLE);
+        set_current_state(TASK_UNINTERRUPTIBLE);
         add_wait_queue(&audit_backlog_wait, &wait);
 
         if (audit_backlog_limit &&
diff --git a/kernel/audit_tree.c b/kernel/audit_tree.c
index a291aa23fb3f..43c307dc9453 100644
--- a/kernel/audit_tree.c
+++ b/kernel/audit_tree.c
@@ -658,6 +658,7 @@ int audit_add_tree_rule(struct audit_krule *rule)
         struct vfsmount *mnt;
         int err;
 
+        rule->tree = NULL;
         list_for_each_entry(tree, &tree_list, list) {
                 if (!strcmp(seed->pathname, tree->pathname)) {
                         put_tree(seed);
diff --git a/kernel/cpu.c b/kernel/cpu.c
index b5e4ab2d427e..198a38883e64 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -133,6 +133,27 @@ static void cpu_hotplug_done(void)
         mutex_unlock(&cpu_hotplug.lock);
 }
 
+/*
+ * Wait for currently running CPU hotplug operations to complete (if any) and
+ * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' protects
+ * the 'cpu_hotplug_disabled' flag. The same lock is also acquired by the
+ * hotplug path before performing hotplug operations. So acquiring that lock
+ * guarantees mutual exclusion from any currently running hotplug operations.
+ */
+void cpu_hotplug_disable(void)
+{
+        cpu_maps_update_begin();
+        cpu_hotplug_disabled = 1;
+        cpu_maps_update_done();
+}
+
+void cpu_hotplug_enable(void)
+{
+        cpu_maps_update_begin();
+        cpu_hotplug_disabled = 0;
+        cpu_maps_update_done();
+}
+
 #else /* #if CONFIG_HOTPLUG_CPU */
 static void cpu_hotplug_begin(void) {}
 static void cpu_hotplug_done(void) {}
@@ -541,36 +562,6 @@ static int __init alloc_frozen_cpus(void)
 core_initcall(alloc_frozen_cpus);
 
 /*
- * Prevent regular CPU hotplug from racing with the freezer, by disabling CPU
- * hotplug when tasks are about to be frozen. Also, don't allow the freezer
- * to continue until any currently running CPU hotplug operation gets
- * completed.
- * To modify the 'cpu_hotplug_disabled' flag, we need to acquire the
- * 'cpu_add_remove_lock'. And this same lock is also taken by the regular
- * CPU hotplug path and released only after it is complete. Thus, we
- * (and hence the freezer) will block here until any currently running CPU
- * hotplug operation gets completed.
- */
-void cpu_hotplug_disable_before_freeze(void)
-{
-        cpu_maps_update_begin();
-        cpu_hotplug_disabled = 1;
-        cpu_maps_update_done();
-}
-
-
-/*
- * When tasks have been thawed, re-enable regular CPU hotplug (which had been
- * disabled while beginning to freeze tasks).
- */
-void cpu_hotplug_enable_after_thaw(void)
-{
-        cpu_maps_update_begin();
-        cpu_hotplug_disabled = 0;
-        cpu_maps_update_done();
-}
-
-/*
  * When callbacks for CPU hotplug notifications are being executed, we must
  * ensure that the state of the system with respect to the tasks being frozen
  * or not, as reported by the notification, remains unchanged *throughout the
@@ -589,12 +580,12 @@ cpu_hotplug_pm_callback(struct notifier_block *nb,
 
         case PM_SUSPEND_PREPARE:
         case PM_HIBERNATION_PREPARE:
-                cpu_hotplug_disable_before_freeze();
+                cpu_hotplug_disable();
                 break;
 
         case PM_POST_SUSPEND:
         case PM_POST_HIBERNATION:
-                cpu_hotplug_enable_after_thaw();
+                cpu_hotplug_enable();
                 break;
 
         default:
diff --git a/kernel/exit.c b/kernel/exit.c
index af2eb3cbd499..7bb73f9d09db 100644
--- a/kernel/exit.c
+++ b/kernel/exit.c
@@ -649,7 +649,6 @@ static void exit_notify(struct task_struct *tsk, int group_dead)
          *      jobs, send them a SIGHUP and then a SIGCONT.  (POSIX 3.2.2.2)
          */
         forget_original_parent(tsk);
-        exit_task_namespaces(tsk);
 
         write_lock_irq(&tasklist_lock);
         if (group_dead)
@@ -795,6 +794,7 @@ void do_exit(long code)
         exit_shm(tsk);
         exit_files(tsk);
         exit_fs(tsk);
+        exit_task_namespaces(tsk);
         exit_task_work(tsk);
         check_stack_usage();
         exit_thread();
diff --git a/kernel/printk.c b/kernel/printk.c
index fa36e1494420..8212c1aef125 100644
--- a/kernel/printk.c
+++ b/kernel/printk.c
@@ -363,6 +363,53 @@ static void log_store(int facility, int level,
         log_next_seq++;
 }
 
+#ifdef CONFIG_SECURITY_DMESG_RESTRICT
+int dmesg_restrict = 1;
+#else
+int dmesg_restrict;
+#endif
+
+static int syslog_action_restricted(int type)
+{
+        if (dmesg_restrict)
+                return 1;
+        /*
+         * Unless restricted, we allow "read all" and "get buffer size"
+         * for everybody.
+         */
+        return type != SYSLOG_ACTION_READ_ALL &&
+               type != SYSLOG_ACTION_SIZE_BUFFER;
+}
+
+static int check_syslog_permissions(int type, bool from_file)
+{
+        /*
+         * If this is from /proc/kmsg and we've already opened it, then we've
+         * already done the capabilities checks at open time.
+         */
+        if (from_file && type != SYSLOG_ACTION_OPEN)
+                return 0;
+
+        if (syslog_action_restricted(type)) {
+                if (capable(CAP_SYSLOG))
+                        return 0;
+                /*
+                 * For historical reasons, accept CAP_SYS_ADMIN too, with
+                 * a warning.
+                 */
+                if (capable(CAP_SYS_ADMIN)) {
+                        pr_warn_once("%s (%d): Attempt to access syslog with "
+                                     "CAP_SYS_ADMIN but no CAP_SYSLOG "
+                                     "(deprecated).\n",
+                                 current->comm, task_pid_nr(current));
+                        return 0;
+                }
+                return -EPERM;
+        }
+        return security_syslog(type);
+}
+
+
 /* /dev/kmsg - userspace message inject/listen interface */
 struct devkmsg_user {
         u64 seq;
@@ -620,7 +667,8 @@ static int devkmsg_open(struct inode *inode, struct file *file)
         if ((file->f_flags & O_ACCMODE) == O_WRONLY)
                 return 0;
 
-        err = security_syslog(SYSLOG_ACTION_READ_ALL);
+        err = check_syslog_permissions(SYSLOG_ACTION_READ_ALL,
+                                       SYSLOG_FROM_READER);
         if (err)
                 return err;
 
@@ -813,45 +861,6 @@ static inline void boot_delay_msec(int level)
 }
 #endif
 
-#ifdef CONFIG_SECURITY_DMESG_RESTRICT
-int dmesg_restrict = 1;
-#else
-int dmesg_restrict;
-#endif
-
-static int syslog_action_restricted(int type)
-{
-        if (dmesg_restrict)
-                return 1;
-        /* Unless restricted, we allow "read all" and "get buffer size" for everybody */
-        return type != SYSLOG_ACTION_READ_ALL && type != SYSLOG_ACTION_SIZE_BUFFER;
-}
-
-static int check_syslog_permissions(int type, bool from_file)
-{
-        /*
-         * If this is from /proc/kmsg and we've already opened it, then we've
-         * already done the capabilities checks at open time.
-         */
-        if (from_file && type != SYSLOG_ACTION_OPEN)
-                return 0;
-
-        if (syslog_action_restricted(type)) {
-                if (capable(CAP_SYSLOG))
-                        return 0;
-                /* For historical reasons, accept CAP_SYS_ADMIN too, with a warning */
-                if (capable(CAP_SYS_ADMIN)) {
-                        printk_once(KERN_WARNING "%s (%d): "
-                                 "Attempt to access syslog with CAP_SYS_ADMIN "
-                                 "but no CAP_SYSLOG (deprecated).\n",
-                                 current->comm, task_pid_nr(current));
-                        return 0;
-                }
-                return -EPERM;
-        }
-        return 0;
-}
-
 #if defined(CONFIG_PRINTK_TIME)
 static bool printk_time = 1;
 #else
@@ -1249,7 +1258,7 @@ out:
 
 SYSCALL_DEFINE3(syslog, int, type, char __user *, buf, int, len)
 {
-        return do_syslog(type, buf, len, SYSLOG_FROM_CALL);
+        return do_syslog(type, buf, len, SYSLOG_FROM_READER);
 }
 
 /*
diff --git a/kernel/rcutree.c b/kernel/rcutree.c
index 16ea67925015..35380019f0fc 100644
--- a/kernel/rcutree.c
+++ b/kernel/rcutree.c
@@ -1451,9 +1451,9 @@ static int rcu_gp_init(struct rcu_state *rsp)
                                             rnp->grphi, rnp->qsmask);
                 raw_spin_unlock_irq(&rnp->lock);
 #ifdef CONFIG_PROVE_RCU_DELAY
-                if ((prandom_u32() % (rcu_num_nodes * 8)) == 0 &&
+                if ((prandom_u32() % (rcu_num_nodes + 1)) == 0 &&
                     system_state == SYSTEM_RUNNING)
-                        schedule_timeout_uninterruptible(2);
+                        udelay(200);
 #endif /* #ifdef CONFIG_PROVE_RCU_DELAY */
                 cond_resched();
         }
@@ -1613,6 +1613,14 @@ static int __noreturn rcu_gp_kthread(void *arg)
         }
 }
 
+static void rsp_wakeup(struct irq_work *work)
+{
+        struct rcu_state *rsp = container_of(work, struct rcu_state, wakeup_work);
+
+        /* Wake up rcu_gp_kthread() to start the grace period. */
+        wake_up(&rsp->gp_wq);
+}
+
 /*
  * Start a new RCU grace period if warranted, re-initializing the hierarchy
  * in preparation for detecting the next grace period.  The caller must hold
@@ -1637,8 +1645,12 @@ rcu_start_gp_advanced(struct rcu_state *rsp, struct rcu_node *rnp,
         }
         rsp->gp_flags = RCU_GP_FLAG_INIT;
 
-        /* Wake up rcu_gp_kthread() to start the grace period. */
-        wake_up(&rsp->gp_wq);
+        /*
+         * We can't do wakeups while holding the rnp->lock, as that
+         * could cause possible deadlocks with the rq->lock. Deter
+         * the wakeup to interrupt context.
+         */
+        irq_work_queue(&rsp->wakeup_work);
 }
 
 /*
@@ -3235,6 +3247,7 @@ static void __init rcu_init_one(struct rcu_state *rsp,
 
         rsp->rda = rda;
         init_waitqueue_head(&rsp->gp_wq);
+        init_irq_work(&rsp->wakeup_work, rsp_wakeup);
         rnp = rsp->level[rcu_num_lvls - 1];
         for_each_possible_cpu(i) {
                 while (i > rnp->grphi)
diff --git a/kernel/rcutree.h b/kernel/rcutree.h
index da77a8f57ff9..4df503470e42 100644
--- a/kernel/rcutree.h
+++ b/kernel/rcutree.h
@@ -27,6 +27,7 @@
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 #include <linux/seqlock.h>
+#include <linux/irq_work.h>
 
 /*
  * Define shape of hierarchy based on NR_CPUS, CONFIG_RCU_FANOUT, and
@@ -442,6 +443,7 @@ struct rcu_state {
         char *name;                             /* Name of structure. */
         char abbr;                              /* Abbreviated name. */
         struct list_head flavors;               /* List of RCU flavors. */
+        struct irq_work wakeup_work;            /* Postponed wakeups */
 };
 
 /* Values for rcu_state structure's gp_flags field. */
diff --git a/kernel/softirq.c b/kernel/softirq.c
index b5197dcb0dad..3d6833f125d3 100644
--- a/kernel/softirq.c
+++ b/kernel/softirq.c
@@ -195,8 +195,12 @@ void local_bh_enable_ip(unsigned long ip)
 EXPORT_SYMBOL(local_bh_enable_ip);
 
 /*
- * We restart softirq processing for at most 2 ms,
- * and if need_resched() is not set.
+ * We restart softirq processing for at most MAX_SOFTIRQ_RESTART times,
+ * but break the loop if need_resched() is set or after 2 ms.
+ * The MAX_SOFTIRQ_TIME provides a nice upper bound in most cases, but in
+ * certain cases, such as stop_machine(), jiffies may cease to
+ * increment and so we need the MAX_SOFTIRQ_RESTART limit as
+ * well to make sure we eventually return from this method.
  *
  * These limits have been established via experimentation.
  * The two things to balance is latency against fairness -
@@ -204,6 +208,7 @@ EXPORT_SYMBOL(local_bh_enable_ip);
  * should not be able to lock up the box.
  */
 #define MAX_SOFTIRQ_TIME  msecs_to_jiffies(2)
+#define MAX_SOFTIRQ_RESTART 10
 
 asmlinkage void __do_softirq(void)
 {
@@ -212,6 +217,7 @@ asmlinkage void __do_softirq(void)
         unsigned long end = jiffies + MAX_SOFTIRQ_TIME;
         int cpu;
         unsigned long old_flags = current->flags;
+        int max_restart = MAX_SOFTIRQ_RESTART;
 
         /*
          * Mask out PF_MEMALLOC s current task context is borrowed for the
@@ -265,7 +271,8 @@ restart:
 
         pending = local_softirq_pending();
         if (pending) {
-                if (time_before(jiffies, end) && !need_resched())
+                if (time_before(jiffies, end) && !need_resched() &&
+                    --max_restart)
                         goto restart;
 
                 wakeup_softirqd();
diff --git a/kernel/sys.c b/kernel/sys.c
index b95d3c72ba21..2bbd9a73b54c 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -362,6 +362,29 @@ int unregister_reboot_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_reboot_notifier);
 
+/* Add backwards compatibility for stable trees. */
+#ifndef PF_NO_SETAFFINITY
+#define PF_NO_SETAFFINITY               PF_THREAD_BOUND
+#endif
+
+static void migrate_to_reboot_cpu(void)
+{
+        /* The boot cpu is always logical cpu 0 */
+        int cpu = 0;
+
+        cpu_hotplug_disable();
+
+        /* Make certain the cpu I'm about to reboot on is online */
+        if (!cpu_online(cpu))
+                cpu = cpumask_first(cpu_online_mask);
+
+        /* Prevent races with other tasks migrating this task */
+        current->flags |= PF_NO_SETAFFINITY;
+
+        /* Make certain I only run on the appropriate processor */
+        set_cpus_allowed_ptr(current, cpumask_of(cpu));
+}
+
 /**
  *      kernel_restart - reboot the system
  *      @cmd: pointer to buffer containing command to execute for restart
@@ -373,7 +396,7 @@ EXPORT_SYMBOL(unregister_reboot_notifier);
 void kernel_restart(char *cmd)
 {
         kernel_restart_prepare(cmd);
-        disable_nonboot_cpus();
+        migrate_to_reboot_cpu();
         syscore_shutdown();
         if (!cmd)
                 printk(KERN_EMERG "Restarting system.\n");
@@ -400,7 +423,7 @@ static void kernel_shutdown_prepare(enum system_states state)
 void kernel_halt(void)
 {
         kernel_shutdown_prepare(SYSTEM_HALT);
-        disable_nonboot_cpus();
+        migrate_to_reboot_cpu();
         syscore_shutdown();
         printk(KERN_EMERG "System halted.\n");
         kmsg_dump(KMSG_DUMP_HALT);
@@ -419,7 +442,7 @@ void kernel_power_off(void)
         kernel_shutdown_prepare(SYSTEM_POWER_OFF);
         if (pm_power_off_prepare)
                 pm_power_off_prepare();
-        disable_nonboot_cpus();
+        migrate_to_reboot_cpu();
         syscore_shutdown();
         printk(KERN_EMERG "Power down.\n");
         kmsg_dump(KMSG_DUMP_POWEROFF);
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index 1a41023a1f88..e71a8be4a6ee 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -652,8 +652,6 @@ static struct {
         ARCH_TRACE_CLOCKS
 };
 
-int trace_clock_id;
-
 /*
  * trace_parser_get_init - gets the buffer for trace parser
  */
@@ -2826,7 +2824,7 @@ __tracing_open(struct inode *inode, struct file *file, bool snapshot)
                 iter->iter_flags |= TRACE_FILE_ANNOTATE;
 
         /* Output in nanoseconds only if we are using a clock in nanoseconds. */
-        if (trace_clocks[trace_clock_id].in_ns)
+        if (trace_clocks[tr->clock_id].in_ns)
                 iter->iter_flags |= TRACE_FILE_TIME_IN_NS;
 
         /* stop the trace while dumping if we are not opening "snapshot" */
@@ -3825,7 +3823,7 @@ static int tracing_open_pipe(struct inode *inode, struct file *filp)
                 iter->iter_flags |= TRACE_FILE_LAT_FMT;
 
         /* Output in nanoseconds only if we are using a clock in nanoseconds. */
-        if (trace_clocks[trace_clock_id].in_ns)
+        if (trace_clocks[tr->clock_id].in_ns)
                 iter->iter_flags |= TRACE_FILE_TIME_IN_NS;
 
         iter->cpu_file = tc->cpu;
@@ -5095,7 +5093,7 @@ tracing_stats_read(struct file *filp, char __user *ubuf,
         cnt = ring_buffer_bytes_cpu(trace_buf->buffer, cpu);
         trace_seq_printf(s, "bytes: %ld\n", cnt);
 
-        if (trace_clocks[trace_clock_id].in_ns) {
+        if (trace_clocks[tr->clock_id].in_ns) {
                 /* local or global for trace_clock */
                 t = ns2usecs(ring_buffer_oldest_event_ts(trace_buf->buffer, cpu));
                 usec_rem = do_div(t, USEC_PER_SEC);
diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
index 711ca7d3e7f1..20572ed88c5c 100644
--- a/kernel/trace/trace.h
+++ b/kernel/trace/trace.h
@@ -700,8 +700,6 @@ enum print_line_t print_trace_line(struct trace_iterator *iter);
 
 extern unsigned long trace_flags;
 
-extern int trace_clock_id;
-
 /* Standard output formatting function used for function return traces */
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
 
diff --git a/lib/mpi/mpicoder.c b/lib/mpi/mpicoder.c
index 5f9c44cdf1f5..4cc6442733f4 100644
--- a/lib/mpi/mpicoder.c
+++ b/lib/mpi/mpicoder.c
@@ -37,7 +37,7 @@ MPI mpi_read_raw_data(const void *xbuffer, size_t nbytes)
         mpi_limb_t a;
         MPI val = NULL;
 
-        while (nbytes >= 0 && buffer[0] == 0) {
+        while (nbytes > 0 && buffer[0] == 0) {
                 buffer++;
                 nbytes--;
         }
diff --git a/mm/frontswap.c b/mm/frontswap.c
index 538367ef1372..1b24bdcb3197 100644
--- a/mm/frontswap.c
+++ b/mm/frontswap.c
@@ -319,7 +319,7 @@ void __frontswap_invalidate_area(unsigned type)
                         return;
                 frontswap_ops->invalidate_area(type);
                 atomic_set(&sis->frontswap_pages, 0);
-                memset(sis->frontswap_map, 0, sis->max / sizeof(long));
+                bitmap_zero(sis->frontswap_map, sis->max);
         }
         clear_bit(type, need_init);
 }
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index f8feeeca6686..e2bfbf73a551 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -2839,7 +2839,7 @@ int hugetlb_fault(struct mm_struct *mm, struct vm_area_struct *vma,
         if (ptep) {
                 entry = huge_ptep_get(ptep);
                 if (unlikely(is_hugetlb_entry_migration(entry))) {
-                        migration_entry_wait(mm, (pmd_t *)ptep, address);
+                        migration_entry_wait_huge(mm, ptep);
                         return 0;
                 } else if (unlikely(is_hugetlb_entry_hwpoisoned(entry)))
                         return VM_FAULT_HWPOISON_LARGE |
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index 010d6c14129a..194721839cf5 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -1199,7 +1199,6 @@ struct mem_cgroup *mem_cgroup_iter(struct mem_cgroup *root,
 
                         mz = mem_cgroup_zoneinfo(root, nid, zid);
                         iter = &mz->reclaim_iter[reclaim->priority];
-                        last_visited = iter->last_visited;
                         if (prev && reclaim->generation != iter->generation) {
                                 iter->last_visited = NULL;
                                 goto out_unlock;
@@ -1218,13 +1217,12 @@ struct mem_cgroup *mem_cgroup_iter(struct mem_cgroup *root,
                          * is alive.
                          */
                         dead_count = atomic_read(&root->dead_count);
-                        smp_rmb();
-                        last_visited = iter->last_visited;
-                        if (last_visited) {
-                                if ((dead_count != iter->last_dead_count) ||
-                                        !css_tryget(&last_visited->css)) {
+                        if (dead_count == iter->last_dead_count) {
+                                smp_rmb();
+                                last_visited = iter->last_visited;
+                                if (last_visited &&
+                                    !css_tryget(&last_visited->css))
                                         last_visited = NULL;
-                                }
                         }
                 }
 
@@ -3141,8 +3139,6 @@ int memcg_update_cache_size(struct kmem_cache *s, int num_groups)
                         return -ENOMEM;
                 }
 
-                INIT_WORK(&s->memcg_params->destroy,
-                                kmem_cache_destroy_work_func);
                 s->memcg_params->is_root_cache = true;
 
                 /*
diff --git a/mm/migrate.c b/mm/migrate.c
index b1f57501de9c..6f0c24438bba 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -200,15 +200,14 @@ static void remove_migration_ptes(struct page *old, struct page *new)
  * get to the page and wait until migration is finished.
  * When we return from this function the fault will be retried.
  */
-void migration_entry_wait(struct mm_struct *mm, pmd_t *pmd,
-                                unsigned long address)
+static void __migration_entry_wait(struct mm_struct *mm, pte_t *ptep,
+                                spinlock_t *ptl)
 {
-        pte_t *ptep, pte;
-        spinlock_t *ptl;
+        pte_t pte;
         swp_entry_t entry;
         struct page *page;
 
-        ptep = pte_offset_map_lock(mm, pmd, address, &ptl);
+        spin_lock(ptl);
         pte = *ptep;
         if (!is_swap_pte(pte))
                 goto out;
@@ -236,6 +235,20 @@ out:
         pte_unmap_unlock(ptep, ptl);
 }
 
+void migration_entry_wait(struct mm_struct *mm, pmd_t *pmd,
+                                unsigned long address)
+{
+        spinlock_t *ptl = pte_lockptr(mm, pmd);
+        pte_t *ptep = pte_offset_map(pmd, address);
+        __migration_entry_wait(mm, ptep, ptl);
+}
+
+void migration_entry_wait_huge(struct mm_struct *mm, pte_t *pte)
+{
+        spinlock_t *ptl = &(mm)->page_table_lock;
+        __migration_entry_wait(mm, pte, ptl);
+}
+
 #ifdef CONFIG_BLOCK
 /* Returns true if all buffers are successfully locked */
 static bool buffer_migrate_lock_buffers(struct buffer_head *head,
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 378a15bcd649..c3edb624fccf 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -1628,6 +1628,7 @@ static bool __zone_watermark_ok(struct zone *z, int order, unsigned long mark,
         long min = mark;
         long lowmem_reserve = z->lowmem_reserve[classzone_idx];
         int o;
+        long free_cma = 0;
 
         free_pages -= (1 << order) - 1;
         if (alloc_flags & ALLOC_HIGH)
@@ -1637,9 +1638,10 @@ static bool __zone_watermark_ok(struct zone *z, int order, unsigned long mark,
 #ifdef CONFIG_CMA
         /* If allocation can't use CMA areas don't use free CMA pages */
         if (!(alloc_flags & ALLOC_CMA))
-                free_pages -= zone_page_state(z, NR_FREE_CMA_PAGES);
+                free_cma = zone_page_state(z, NR_FREE_CMA_PAGES);
 #endif
-        if (free_pages <= min + lowmem_reserve)
+
+        if (free_pages - free_cma <= min + lowmem_reserve)
                 return false;
         for (o = 0; o < order; o++) {
                 /* At the next order, this order's pages become unavailable */
diff --git a/mm/swap_state.c b/mm/swap_state.c
index b3d40dcf3624..f24ab0dff554 100644
--- a/mm/swap_state.c
+++ b/mm/swap_state.c
@@ -336,8 +336,24 @@ struct page *read_swap_cache_async(swp_entry_t entry, gfp_t gfp_mask,
                  * Swap entry may have been freed since our caller observed it.
                  */
                 err = swapcache_prepare(entry);
-                if (err == -EEXIST) {   /* seems racy */
+                if (err == -EEXIST) {
                         radix_tree_preload_end();
+                        /*
+                         * We might race against get_swap_page() and stumble
+                         * across a SWAP_HAS_CACHE swap_map entry whose page
+                         * has not been brought into the swapcache yet, while
+                         * the other end is scheduled away waiting on discard
+                         * I/O completion at scan_swap_map().
+                         *
+                         * In order to avoid turning this transitory state
+                         * into a permanent loop around this -EEXIST case
+                         * if !CONFIG_PREEMPT and the I/O completion happens
+                         * to be waiting on the CPU waitqueue where we are now
+                         * busy looping, we just conditionally invoke the
+                         * scheduler here, if there are some more important
+                         * tasks to run.
+                         */
+                        cond_resched();
                         continue;
                 }
                 if (err) {              /* swp entry is obsolete ? */
diff --git a/mm/swapfile.c b/mm/swapfile.c
index 6c340d908b27..746af55b8455 100644
--- a/mm/swapfile.c
+++ b/mm/swapfile.c
@@ -2116,7 +2116,7 @@ SYSCALL_DEFINE2(swapon, const char __user *, specialfile, int, swap_flags)
         }
         /* frontswap enabled? set up bit-per-page map for frontswap */
         if (frontswap_enabled)
-                frontswap_map = vzalloc(maxpages / sizeof(long));
+                frontswap_map = vzalloc(BITS_TO_LONGS(maxpages) * sizeof(long));
 
         if (p->bdev) {
                 if (blk_queue_nonrot(bdev_get_queue(p->bdev))) {
diff --git a/net/9p/client.c b/net/9p/client.c
index 8eb75425e6e6..addc116cecf0 100644
--- a/net/9p/client.c
+++ b/net/9p/client.c
@@ -562,36 +562,19 @@ static int p9_check_zc_errors(struct p9_client *c, struct p9_req_t *req,
 
         if (!p9_is_proto_dotl(c)) {
                 /* Error is reported in string format */
-                uint16_t len;
-                /* 7 = header size for RERROR, 2 is the size of string len; */
-                int inline_len = in_hdrlen - (7 + 2);
+                int len;
+                /* 7 = header size for RERROR; */
+                int inline_len = in_hdrlen - 7;
 
-                /* Read the size of error string */
-                err = p9pdu_readf(req->rc, c->proto_version, "w", &len);
-                if (err)
-                        goto out_err;
-
-                ename = kmalloc(len + 1, GFP_NOFS);
-                if (!ename) {
-                        err = -ENOMEM;
+                len =  req->rc->size - req->rc->offset;
+                if (len > (P9_ZC_HDR_SZ - 7)) {
+                        err = -EFAULT;
                         goto out_err;
                 }
-                if (len <= inline_len) {
-                        /* We have error in protocol buffer itself */
-                        if (pdu_read(req->rc, ename, len)) {
-                                err = -EFAULT;
-                                goto out_free;
 
-                        }
-                } else {
-                        /*
-                         *  Part of the data is in user space buffer.
-                         */
-                        if (pdu_read(req->rc, ename, inline_len)) {
-                                err = -EFAULT;
-                                goto out_free;
-
-                        }
+                ename = &req->rc->sdata[req->rc->offset];
+                if (len > inline_len) {
+                        /* We have error in external buffer */
                         if (kern_buf) {
                                 memcpy(ename + inline_len, uidata,
                                        len - inline_len);
@@ -600,19 +583,19 @@ static int p9_check_zc_errors(struct p9_client *c, struct p9_req_t *req,
                                                      uidata, len - inline_len);
                                 if (err) {
                                         err = -EFAULT;
-                                        goto out_free;
+                                        goto out_err;
                                 }
                         }
                 }
-                ename[len] = 0;
-                if (p9_is_proto_dotu(c)) {
-                        /* For dotu we also have error code */
-                        err = p9pdu_readf(req->rc,
-                                          c->proto_version, "d", &ecode);
-                        if (err)
-                                goto out_free;
+                ename = NULL;
+                err = p9pdu_readf(req->rc, c->proto_version, "s?d",
+                                  &ename, &ecode);
+                if (err)
+                        goto out_err;
+
+                if (p9_is_proto_dotu(c))
                         err = -ecode;
-                }
+
                 if (!err || !IS_ERR_VALUE(err)) {
                         err = p9_errstr2errno(ename, strlen(ename));
 
@@ -628,8 +611,6 @@ static int p9_check_zc_errors(struct p9_client *c, struct p9_req_t *req,
         }
         return err;
 
-out_free:
-        kfree(ename);
 out_err:
         p9_debug(P9_DEBUG_ERROR, "couldn't parse error%d\n", err);
         return err;
diff --git a/net/batman-adv/bat_iv_ogm.c b/net/batman-adv/bat_iv_ogm.c
index 071f288b77a8..f680ee101878 100644
--- a/net/batman-adv/bat_iv_ogm.c
+++ b/net/batman-adv/bat_iv_ogm.c
@@ -29,6 +29,21 @@
 #include "bat_algo.h"
 #include "network-coding.h"
 
+/**
+ * batadv_dup_status - duplicate status
+ * @BATADV_NO_DUP: the packet is a duplicate
+ * @BATADV_ORIG_DUP: OGM is a duplicate in the originator (but not for the
+ *  neighbor)
+ * @BATADV_NEIGH_DUP: OGM is a duplicate for the neighbor
+ * @BATADV_PROTECTED: originator is currently protected (after reboot)
+ */
+enum batadv_dup_status {
+        BATADV_NO_DUP = 0,
+        BATADV_ORIG_DUP,
+        BATADV_NEIGH_DUP,
+        BATADV_PROTECTED,
+};
+
 static struct batadv_neigh_node *
 batadv_iv_ogm_neigh_new(struct batadv_hard_iface *hard_iface,
                         const uint8_t *neigh_addr,
@@ -650,7 +665,7 @@ batadv_iv_ogm_orig_update(struct batadv_priv *bat_priv,
                           const struct batadv_ogm_packet *batadv_ogm_packet,
                           struct batadv_hard_iface *if_incoming,
                           const unsigned char *tt_buff,
-                          int is_duplicate)
+                          enum batadv_dup_status dup_status)
 {
         struct batadv_neigh_node *neigh_node = NULL, *tmp_neigh_node = NULL;
         struct batadv_neigh_node *router = NULL;
@@ -676,7 +691,7 @@ batadv_iv_ogm_orig_update(struct batadv_priv *bat_priv,
                         continue;
                 }
 
-                if (is_duplicate)
+                if (dup_status != BATADV_NO_DUP)
                         continue;
 
                 spin_lock_bh(&tmp_neigh_node->lq_update_lock);
@@ -718,7 +733,7 @@ batadv_iv_ogm_orig_update(struct batadv_priv *bat_priv,
         neigh_node->tq_avg = batadv_ring_buffer_avg(neigh_node->tq_recv);
         spin_unlock_bh(&neigh_node->lq_update_lock);
 
-        if (!is_duplicate) {
+        if (dup_status == BATADV_NO_DUP) {
                 orig_node->last_ttl = batadv_ogm_packet->header.ttl;
                 neigh_node->last_ttl = batadv_ogm_packet->header.ttl;
         }
@@ -902,15 +917,16 @@ out:
         return ret;
 }
 
-/* processes a batman packet for all interfaces, adjusts the sequence number and
- * finds out whether it is a duplicate.
- * returns:
- *   1 the packet is a duplicate
- *   0 the packet has not yet been received
- *  -1 the packet is old and has been received while the seqno window
- *     was protected. Caller should drop it.
+/**
+ * batadv_iv_ogm_update_seqnos -  process a batman packet for all interfaces,
+ *  adjust the sequence number and find out whether it is a duplicate
+ * @ethhdr: ethernet header of the packet
+ * @batadv_ogm_packet: OGM packet to be considered
+ * @if_incoming: interface on which the OGM packet was received
+ *
+ * Returns duplicate status as enum batadv_dup_status
  */
-static int
+static enum batadv_dup_status
 batadv_iv_ogm_update_seqnos(const struct ethhdr *ethhdr,
                             const struct batadv_ogm_packet *batadv_ogm_packet,
                             const struct batadv_hard_iface *if_incoming)
@@ -918,17 +934,18 @@ batadv_iv_ogm_update_seqnos(const struct ethhdr *ethhdr,
         struct batadv_priv *bat_priv = netdev_priv(if_incoming->soft_iface);
         struct batadv_orig_node *orig_node;
         struct batadv_neigh_node *tmp_neigh_node;
-        int is_duplicate = 0;
+        int is_dup;
         int32_t seq_diff;
         int need_update = 0;
-        int set_mark, ret = -1;
+        int set_mark;
+        enum batadv_dup_status ret = BATADV_NO_DUP;
         uint32_t seqno = ntohl(batadv_ogm_packet->seqno);
         uint8_t *neigh_addr;
         uint8_t packet_count;
 
         orig_node = batadv_get_orig_node(bat_priv, batadv_ogm_packet->orig);
         if (!orig_node)
-                return 0;
+                return BATADV_NO_DUP;
 
         spin_lock_bh(&orig_node->ogm_cnt_lock);
         seq_diff = seqno - orig_node->last_real_seqno;
@@ -936,22 +953,29 @@ batadv_iv_ogm_update_seqnos(const struct ethhdr *ethhdr,
         /* signalize caller that the packet is to be dropped. */
         if (!hlist_empty(&orig_node->neigh_list) &&
             batadv_window_protected(bat_priv, seq_diff,
-                                    &orig_node->batman_seqno_reset))
+                                    &orig_node->batman_seqno_reset)) {
+                ret = BATADV_PROTECTED;
                 goto out;
+        }
 
         rcu_read_lock();
         hlist_for_each_entry_rcu(tmp_neigh_node,
                                  &orig_node->neigh_list, list) {
-                is_duplicate |= batadv_test_bit(tmp_neigh_node->real_bits,
-                                                orig_node->last_real_seqno,
-                                                seqno);
-
                 neigh_addr = tmp_neigh_node->addr;
+                is_dup = batadv_test_bit(tmp_neigh_node->real_bits,
+                                         orig_node->last_real_seqno,
+                                         seqno);
+
                 if (batadv_compare_eth(neigh_addr, ethhdr->h_source) &&
-                    tmp_neigh_node->if_incoming == if_incoming)
+                    tmp_neigh_node->if_incoming == if_incoming) {
                         set_mark = 1;
-                else
+                        if (is_dup)
+                                ret = BATADV_NEIGH_DUP;
+                } else {
                         set_mark = 0;
+                        if (is_dup && (ret != BATADV_NEIGH_DUP))
+                                ret = BATADV_ORIG_DUP;
+                }
 
                 /* if the window moved, set the update flag. */
                 need_update |= batadv_bit_get_packet(bat_priv,
@@ -971,8 +995,6 @@ batadv_iv_ogm_update_seqnos(const struct ethhdr *ethhdr,
                 orig_node->last_real_seqno = seqno;
         }
 
-        ret = is_duplicate;
-
 out:
         spin_unlock_bh(&orig_node->ogm_cnt_lock);
         batadv_orig_node_free_ref(orig_node);
@@ -994,7 +1016,8 @@ static void batadv_iv_ogm_process(const struct ethhdr *ethhdr,
         int is_broadcast = 0, is_bidirect;
         bool is_single_hop_neigh = false;
         bool is_from_best_next_hop = false;
-        int is_duplicate, sameseq, simlar_ttl;
+        int sameseq, similar_ttl;
+        enum batadv_dup_status dup_status;
         uint32_t if_incoming_seqno;
         uint8_t *prev_sender;
 
@@ -1138,10 +1161,10 @@ static void batadv_iv_ogm_process(const struct ethhdr *ethhdr,
         if (!orig_node)
                 return;
 
-        is_duplicate = batadv_iv_ogm_update_seqnos(ethhdr, batadv_ogm_packet,
-                                                   if_incoming);
+        dup_status = batadv_iv_ogm_update_seqnos(ethhdr, batadv_ogm_packet,
+                                                 if_incoming);
 
-        if (is_duplicate == -1) {
+        if (dup_status == BATADV_PROTECTED) {
                 batadv_dbg(BATADV_DBG_BATMAN, bat_priv,
                            "Drop packet: packet within seqno protection time (sender: %pM)\n",
                            ethhdr->h_source);
@@ -1211,11 +1234,12 @@ static void batadv_iv_ogm_process(const struct ethhdr *ethhdr,
          * seqno and similar ttl as the non-duplicate
          */
         sameseq = orig_node->last_real_seqno == ntohl(batadv_ogm_packet->seqno);
-        simlar_ttl = orig_node->last_ttl - 3 <= batadv_ogm_packet->header.ttl;
-        if (is_bidirect && (!is_duplicate || (sameseq && simlar_ttl)))
+        similar_ttl = orig_node->last_ttl - 3 <= batadv_ogm_packet->header.ttl;
+        if (is_bidirect && ((dup_status == BATADV_NO_DUP) ||
+                            (sameseq && similar_ttl)))
                 batadv_iv_ogm_orig_update(bat_priv, orig_node, ethhdr,
                                           batadv_ogm_packet, if_incoming,
-                                          tt_buff, is_duplicate);
+                                          tt_buff, dup_status);
 
         /* is single hop (direct) neighbor */
         if (is_single_hop_neigh) {
@@ -1236,7 +1260,7 @@ static void batadv_iv_ogm_process(const struct ethhdr *ethhdr,
                 goto out_neigh;
         }
 
-        if (is_duplicate) {
+        if (dup_status == BATADV_NEIGH_DUP) {
                 batadv_dbg(BATADV_DBG_BATMAN, bat_priv,
                            "Drop packet: duplicate packet received\n");
                 goto out_neigh;
diff --git a/net/batman-adv/bridge_loop_avoidance.c b/net/batman-adv/bridge_loop_avoidance.c
index 379061c72549..de27b3175cfd 100644
--- a/net/batman-adv/bridge_loop_avoidance.c
+++ b/net/batman-adv/bridge_loop_avoidance.c
@@ -1067,6 +1067,10 @@ void batadv_bla_update_orig_address(struct batadv_priv *bat_priv,
         group = htons(crc16(0, primary_if->net_dev->dev_addr, ETH_ALEN));
         bat_priv->bla.claim_dest.group = group;
 
+        /* purge everything when bridge loop avoidance is turned off */
+        if (!atomic_read(&bat_priv->bridge_loop_avoidance))
+                oldif = NULL;
+
         if (!oldif) {
                 batadv_bla_purge_claims(bat_priv, NULL, 1);
                 batadv_bla_purge_backbone_gw(bat_priv, 1);
diff --git a/net/batman-adv/sysfs.c b/net/batman-adv/sysfs.c
index 15a22efa9a67..929e304dacb2 100644
--- a/net/batman-adv/sysfs.c
+++ b/net/batman-adv/sysfs.c
@@ -582,10 +582,7 @@ static ssize_t batadv_store_mesh_iface(struct kobject *kobj,
             (strncmp(hard_iface->soft_iface->name, buff, IFNAMSIZ) == 0))
                 goto out;
 
-        if (!rtnl_trylock()) {
-                ret = -ERESTARTSYS;
-                goto out;
-        }
+        rtnl_lock();
 
         if (status_tmp == BATADV_IF_NOT_IN_USE) {
                 batadv_hardif_disable_interface(hard_iface,
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index 33843c5c4939..d817c932d634 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -1555,11 +1555,15 @@ static const struct rfkill_ops hci_rfkill_ops = {
 static void hci_power_on(struct work_struct *work)
 {
         struct hci_dev *hdev = container_of(work, struct hci_dev, power_on);
+        int err;
 
         BT_DBG("%s", hdev->name);
 
-        if (hci_dev_open(hdev->id) < 0)
+        err = hci_dev_open(hdev->id);
+        if (err < 0) {
+                mgmt_set_powered_failed(hdev, err);
                 return;
+        }
 
         if (test_bit(HCI_AUTO_OFF, &hdev->dev_flags))
                 queue_delayed_work(hdev->req_workqueue, &hdev->power_off,
diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
index a76d1ac0321b..24bee07ee4ce 100644
--- a/net/bluetooth/l2cap_core.c
+++ b/net/bluetooth/l2cap_core.c
@@ -3677,10 +3677,14 @@ static void l2cap_conf_rfc_get(struct l2cap_chan *chan, void *rsp, int len)
 }
 
 static inline int l2cap_command_rej(struct l2cap_conn *conn,
-                                    struct l2cap_cmd_hdr *cmd, u8 *data)
+                                    struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                    u8 *data)
 {
         struct l2cap_cmd_rej_unk *rej = (struct l2cap_cmd_rej_unk *) data;
 
+        if (cmd_len < sizeof(*rej))
+                return -EPROTO;
+
         if (rej->reason != L2CAP_REJ_NOT_UNDERSTOOD)
                 return 0;
 
@@ -3829,11 +3833,14 @@ sendresp:
 }
 
 static int l2cap_connect_req(struct l2cap_conn *conn,
-                             struct l2cap_cmd_hdr *cmd, u8 *data)
+                             struct l2cap_cmd_hdr *cmd, u16 cmd_len, u8 *data)
 {
         struct hci_dev *hdev = conn->hcon->hdev;
         struct hci_conn *hcon = conn->hcon;
 
+        if (cmd_len < sizeof(struct l2cap_conn_req))
+                return -EPROTO;
+
         hci_dev_lock(hdev);
         if (test_bit(HCI_MGMT, &hdev->dev_flags) &&
             !test_and_set_bit(HCI_CONN_MGMT_CONNECTED, &hcon->flags))
@@ -3847,7 +3854,8 @@ static int l2cap_connect_req(struct l2cap_conn *conn,
 }
 
 static int l2cap_connect_create_rsp(struct l2cap_conn *conn,
-                                    struct l2cap_cmd_hdr *cmd, u8 *data)
+                                    struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                    u8 *data)
 {
         struct l2cap_conn_rsp *rsp = (struct l2cap_conn_rsp *) data;
         u16 scid, dcid, result, status;
@@ -3855,6 +3863,9 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn,
         u8 req[128];
         int err;
 
+        if (cmd_len < sizeof(*rsp))
+                return -EPROTO;
+
         scid   = __le16_to_cpu(rsp->scid);
         dcid   = __le16_to_cpu(rsp->dcid);
         result = __le16_to_cpu(rsp->result);
@@ -3952,6 +3963,9 @@ static inline int l2cap_config_req(struct l2cap_conn *conn,
         struct l2cap_chan *chan;
         int len, err = 0;
 
+        if (cmd_len < sizeof(*req))
+                return -EPROTO;
+
         dcid  = __le16_to_cpu(req->dcid);
         flags = __le16_to_cpu(req->flags);
 
@@ -3975,7 +3989,7 @@ static inline int l2cap_config_req(struct l2cap_conn *conn,
 
         /* Reject if config buffer is too small. */
         len = cmd_len - sizeof(*req);
-        if (len < 0 || chan->conf_len + len > sizeof(chan->conf_req)) {
+        if (chan->conf_len + len > sizeof(chan->conf_req)) {
                 l2cap_send_cmd(conn, cmd->ident, L2CAP_CONF_RSP,
                                l2cap_build_conf_rsp(chan, rsp,
                                L2CAP_CONF_REJECT, flags), rsp);
@@ -4053,14 +4067,18 @@ unlock:
 }
 
 static inline int l2cap_config_rsp(struct l2cap_conn *conn,
-                                   struct l2cap_cmd_hdr *cmd, u8 *data)
+                                   struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                   u8 *data)
 {
         struct l2cap_conf_rsp *rsp = (struct l2cap_conf_rsp *)data;
         u16 scid, flags, result;
         struct l2cap_chan *chan;
-        int len = le16_to_cpu(cmd->len) - sizeof(*rsp);
+        int len = cmd_len - sizeof(*rsp);
         int err = 0;
 
+        if (cmd_len < sizeof(*rsp))
+                return -EPROTO;
+
         scid   = __le16_to_cpu(rsp->scid);
         flags  = __le16_to_cpu(rsp->flags);
         result = __le16_to_cpu(rsp->result);
@@ -4161,7 +4179,8 @@ done:
 }
 
 static inline int l2cap_disconnect_req(struct l2cap_conn *conn,
-                                       struct l2cap_cmd_hdr *cmd, u8 *data)
+                                       struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                       u8 *data)
 {
         struct l2cap_disconn_req *req = (struct l2cap_disconn_req *) data;
         struct l2cap_disconn_rsp rsp;
@@ -4169,6 +4188,9 @@ static inline int l2cap_disconnect_req(struct l2cap_conn *conn,
         struct l2cap_chan *chan;
         struct sock *sk;
 
+        if (cmd_len != sizeof(*req))
+                return -EPROTO;
+
         scid = __le16_to_cpu(req->scid);
         dcid = __le16_to_cpu(req->dcid);
 
@@ -4208,12 +4230,16 @@ static inline int l2cap_disconnect_req(struct l2cap_conn *conn,
 }
 
 static inline int l2cap_disconnect_rsp(struct l2cap_conn *conn,
-                                       struct l2cap_cmd_hdr *cmd, u8 *data)
+                                       struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                       u8 *data)
 {
         struct l2cap_disconn_rsp *rsp = (struct l2cap_disconn_rsp *) data;
         u16 dcid, scid;
         struct l2cap_chan *chan;
 
+        if (cmd_len != sizeof(*rsp))
+                return -EPROTO;
+
         scid = __le16_to_cpu(rsp->scid);
         dcid = __le16_to_cpu(rsp->dcid);
 
@@ -4243,11 +4269,15 @@ static inline int l2cap_disconnect_rsp(struct l2cap_conn *conn,
 }
 
 static inline int l2cap_information_req(struct l2cap_conn *conn,
-                                        struct l2cap_cmd_hdr *cmd, u8 *data)
+                                        struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                        u8 *data)
 {
         struct l2cap_info_req *req = (struct l2cap_info_req *) data;
         u16 type;
 
+        if (cmd_len != sizeof(*req))
+                return -EPROTO;
+
         type = __le16_to_cpu(req->type);
 
         BT_DBG("type 0x%4.4x", type);
@@ -4294,11 +4324,15 @@ static inline int l2cap_information_req(struct l2cap_conn *conn,
 }
 
 static inline int l2cap_information_rsp(struct l2cap_conn *conn,
-                                        struct l2cap_cmd_hdr *cmd, u8 *data)
+                                        struct l2cap_cmd_hdr *cmd, u16 cmd_len,
+                                        u8 *data)
 {
         struct l2cap_info_rsp *rsp = (struct l2cap_info_rsp *) data;
         u16 type, result;
 
+        if (cmd_len != sizeof(*rsp))
+                return -EPROTO;
+
         type   = __le16_to_cpu(rsp->type);
         result = __le16_to_cpu(rsp->result);
 
@@ -5164,16 +5198,16 @@ static inline int l2cap_bredr_sig_cmd(struct l2cap_conn *conn,
 
         switch (cmd->code) {
         case L2CAP_COMMAND_REJ:
-                l2cap_command_rej(conn, cmd, data);
+                l2cap_command_rej(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_CONN_REQ:
-                err = l2cap_connect_req(conn, cmd, data);
+                err = l2cap_connect_req(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_CONN_RSP:
         case L2CAP_CREATE_CHAN_RSP:
-                err = l2cap_connect_create_rsp(conn, cmd, data);
+                err = l2cap_connect_create_rsp(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_CONF_REQ:
@@ -5181,15 +5215,15 @@ static inline int l2cap_bredr_sig_cmd(struct l2cap_conn *conn,
                 break;
 
         case L2CAP_CONF_RSP:
-                err = l2cap_config_rsp(conn, cmd, data);
+                err = l2cap_config_rsp(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_DISCONN_REQ:
-                err = l2cap_disconnect_req(conn, cmd, data);
+                err = l2cap_disconnect_req(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_DISCONN_RSP:
-                err = l2cap_disconnect_rsp(conn, cmd, data);
+                err = l2cap_disconnect_rsp(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_ECHO_REQ:
@@ -5200,11 +5234,11 @@ static inline int l2cap_bredr_sig_cmd(struct l2cap_conn *conn,
                 break;
 
         case L2CAP_INFO_REQ:
-                err = l2cap_information_req(conn, cmd, data);
+                err = l2cap_information_req(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_INFO_RSP:
-                err = l2cap_information_rsp(conn, cmd, data);
+                err = l2cap_information_rsp(conn, cmd, cmd_len, data);
                 break;
 
         case L2CAP_CREATE_CHAN_REQ:
diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index 35fef22703e9..f8ecbc70293d 100644
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -2700,7 +2700,7 @@ static int start_discovery(struct sock *sk, struct hci_dev *hdev,
                 break;
 
         case DISCOV_TYPE_LE:
-                if (!lmp_host_le_capable(hdev)) {
+                if (!test_bit(HCI_LE_ENABLED, &hdev->dev_flags)) {
                         err = cmd_status(sk, hdev->id, MGMT_OP_START_DISCOVERY,
                                          MGMT_STATUS_NOT_SUPPORTED);
                         mgmt_pending_remove(cmd);
@@ -3418,6 +3418,27 @@ new_settings:
         return err;
 }
 
+int mgmt_set_powered_failed(struct hci_dev *hdev, int err)
+{
+        struct pending_cmd *cmd;
+        u8 status;
+
+        cmd = mgmt_pending_find(MGMT_OP_SET_POWERED, hdev);
+        if (!cmd)
+                return -ENOENT;
+
+        if (err == -ERFKILL)
+                status = MGMT_STATUS_RFKILLED;
+        else
+                status = MGMT_STATUS_FAILED;
+
+        err = cmd_status(cmd->sk, hdev->id, MGMT_OP_SET_POWERED, status);
+
+        mgmt_pending_remove(cmd);
+
+        return err;
+}
+
 int mgmt_discoverable(struct hci_dev *hdev, u8 discoverable)
 {
         struct cmd_lookup match = { NULL, hdev };
diff --git a/net/bluetooth/smp.c b/net/bluetooth/smp.c
index b2296d3857a0..b5562abdd6e0 100644
--- a/net/bluetooth/smp.c
+++ b/net/bluetooth/smp.c
@@ -770,7 +770,7 @@ int smp_conn_security(struct hci_conn *hcon, __u8 sec_level)
 
         BT_DBG("conn %p hcon %p level 0x%2.2x", conn, hcon, sec_level);
 
-        if (!lmp_host_le_capable(hcon->hdev))
+        if (!test_bit(HCI_LE_ENABLED, &hcon->hdev->dev_flags))
                 return 1;
 
         if (sec_level == BT_SECURITY_LOW)
@@ -851,7 +851,7 @@ int smp_sig_channel(struct l2cap_conn *conn, struct sk_buff *skb)
         __u8 reason;
         int err = 0;
 
-        if (!lmp_host_le_capable(conn->hcon->hdev)) {
+        if (!test_bit(HCI_LE_ENABLED, &conn->hcon->hdev->dev_flags)) {
                 err = -ENOTSUPP;
                 reason = SMP_PAIRING_NOTSUPP;
                 goto done;
diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c
index d5953b87918c..3a246a6cab47 100644
--- a/net/ceph/osd_client.c
+++ b/net/ceph/osd_client.c
@@ -1675,13 +1675,13 @@ static void kick_requests(struct ceph_osd_client *osdc, int force_resend)
                 __register_request(osdc, req);
                 __unregister_linger_request(osdc, req);
         }
+        reset_changed_osds(osdc);
         mutex_unlock(&osdc->request_mutex);
 
         if (needmap) {
                 dout("%d requests for down osds, need new map\n", needmap);
                 ceph_monc_request_next_osdmap(&osdc->client->monc);
         }
-        reset_changed_osds(osdc);
 }
 
 
diff --git a/net/core/filter.c b/net/core/filter.c
index dad2a178f9f8..6438f29ff266 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -778,7 +778,7 @@ int sk_detach_filter(struct sock *sk)
 }
 EXPORT_SYMBOL_GPL(sk_detach_filter);
 
-static void sk_decode_filter(struct sock_filter *filt, struct sock_filter *to)
+void sk_decode_filter(struct sock_filter *filt, struct sock_filter *to)
 {
         static const u16 decodes[] = {
                 [BPF_S_ALU_ADD_K]       = BPF_ALU|BPF_ADD|BPF_K,
diff --git a/net/core/sock_diag.c b/net/core/sock_diag.c
index d5bef0b0f639..a0e9cf6379de 100644
--- a/net/core/sock_diag.c
+++ b/net/core/sock_diag.c
@@ -73,8 +73,13 @@ int sock_diag_put_filterinfo(struct user_namespace *user_ns, struct sock *sk,
                 goto out;
         }
 
-        if (filter)
-                memcpy(nla_data(attr), filter->insns, len);
+        if (filter) {
+                struct sock_filter *fb = (struct sock_filter *)nla_data(attr);
+                int i;
+
+                for (i = 0; i < filter->len; i++, fb++)
+                        sk_decode_filter(&filter->insns[i], fb);
+        }
 
 out:
         rcu_read_unlock();
diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c
index be2f8da0ae8e..7fa8f08fa7ae 100644
--- a/net/ipv4/ip_tunnel.c
+++ b/net/ipv4/ip_tunnel.c
@@ -853,7 +853,7 @@ void ip_tunnel_dellink(struct net_device *dev, struct list_head *head)
 }
 EXPORT_SYMBOL_GPL(ip_tunnel_dellink);
 
-int __net_init ip_tunnel_init_net(struct net *net, int ip_tnl_net_id,
+int ip_tunnel_init_net(struct net *net, int ip_tnl_net_id,
                                   struct rtnl_link_ops *ops, char *devname)
 {
         struct ip_tunnel_net *itn = net_generic(net, ip_tnl_net_id);
@@ -899,7 +899,7 @@ static void ip_tunnel_destroy(struct ip_tunnel_net *itn, struct list_head *head)
                 unregister_netdevice_queue(itn->fb_tunnel_dev, head);
 }
 
-void __net_exit ip_tunnel_delete_net(struct ip_tunnel_net *itn)
+void ip_tunnel_delete_net(struct ip_tunnel_net *itn)
 {
         LIST_HEAD(list);
 
diff --git a/net/ipv4/ip_vti.c b/net/ipv4/ip_vti.c
index 9d2bdb2c1d3f..c118f6b576bb 100644
--- a/net/ipv4/ip_vti.c
+++ b/net/ipv4/ip_vti.c
@@ -361,8 +361,7 @@ static netdev_tx_t vti_tunnel_xmit(struct sk_buff *skb, struct net_device *dev)
                         tunnel->err_count = 0;
         }
 
-        IPCB(skb)->flags &= ~(IPSKB_XFRM_TUNNEL_SIZE | IPSKB_XFRM_TRANSFORMED |
-                              IPSKB_REROUTED);
+        memset(IPCB(skb), 0, sizeof(*IPCB(skb)));
         skb_dst_drop(skb);
         skb_dst_set(skb, &rt->dst);
         nf_reset(skb);
diff --git a/net/l2tp/l2tp_ppp.c b/net/l2tp/l2tp_ppp.c
index 637a341c1e2d..8dec6876dc50 100644
--- a/net/l2tp/l2tp_ppp.c
+++ b/net/l2tp/l2tp_ppp.c
@@ -346,19 +346,19 @@ static int pppol2tp_sendmsg(struct kiocb *iocb, struct socket *sock, struct msgh
         skb_put(skb, 2);
 
         /* Copy user data into skb */
-        error = memcpy_fromiovec(skb->data, m->msg_iov, total_len);
+        error = memcpy_fromiovec(skb_put(skb, total_len), m->msg_iov,
+                                 total_len);
         if (error < 0) {
                 kfree_skb(skb);
                 goto error_put_sess_tun;
         }
-        skb_put(skb, total_len);
 
         l2tp_xmit_skb(session, skb, session->hdr_len);
 
         sock_put(ps->tunnel_sock);
         sock_put(sk);
 
-        return error;
+        return total_len;
 
 error_put_sess_tun:
         sock_put(ps->tunnel_sock);
diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c
index 5b142fb16480..9e6c2a075a4c 100644
--- a/net/netfilter/ipvs/ip_vs_ctl.c
+++ b/net/netfilter/ipvs/ip_vs_ctl.c
@@ -2542,6 +2542,7 @@ __ip_vs_get_dest_entries(struct net *net, const struct ip_vs_get_dests *get,
                 struct ip_vs_dest *dest;
                 struct ip_vs_dest_entry entry;
 
+                memset(&entry, 0, sizeof(entry));
                 list_for_each_entry(dest, &svc->destinations, n_list) {
                         if (count >= get->num_dests)
                                 break;
diff --git a/net/netfilter/nfnetlink_acct.c b/net/netfilter/nfnetlink_acct.c
index dc3fd5d44464..c7b6d466a662 100644
--- a/net/netfilter/nfnetlink_acct.c
+++ b/net/netfilter/nfnetlink_acct.c
@@ -149,9 +149,12 @@ nfnl_acct_dump(struct sk_buff *skb, struct netlink_callback *cb)
 
         rcu_read_lock();
         list_for_each_entry_rcu(cur, &nfnl_acct_list, head) {
-                if (last && cur != last)
-                        continue;
+                if (last) {
+                        if (cur != last)
+                                continue;
 
+                        last = NULL;
+                }
                 if (nfnl_acct_fill_info(skb, NETLINK_CB(cb->skb).portid,
                                        cb->nlh->nlmsg_seq,
                                        NFNL_MSG_TYPE(cb->nlh->nlmsg_type),
diff --git a/net/netfilter/nfnetlink_cttimeout.c b/net/netfilter/nfnetlink_cttimeout.c
index 701c88a20fea..65074dfb9383 100644
--- a/net/netfilter/nfnetlink_cttimeout.c
+++ b/net/netfilter/nfnetlink_cttimeout.c
@@ -220,9 +220,12 @@ ctnl_timeout_dump(struct sk_buff *skb, struct netlink_callback *cb)
 
         rcu_read_lock();
         list_for_each_entry_rcu(cur, &cttimeout_list, head) {
-                if (last && cur != last)
-                        continue;
+                if (last) {
+                        if (cur != last)
+                                continue;
 
+                        last = NULL;
+                }
                 if (ctnl_timeout_fill_info(skb, NETLINK_CB(cb->skb).portid,
                                            cb->nlh->nlmsg_seq,
                                            NFNL_MSG_TYPE(cb->nlh->nlmsg_type),
diff --git a/net/netfilter/nfnetlink_queue_core.c b/net/netfilter/nfnetlink_queue_core.c
index 4e27fa035814..5352b2d2d5bf 100644
--- a/net/netfilter/nfnetlink_queue_core.c
+++ b/net/netfilter/nfnetlink_queue_core.c
@@ -637,9 +637,6 @@ nfqnl_enqueue_packet(struct nf_queue_entry *entry, unsigned int queuenum)
         if (queue->copy_mode == NFQNL_COPY_NONE)
                 return -EINVAL;
 
-        if ((queue->flags & NFQA_CFG_F_GSO) || !skb_is_gso(entry->skb))
-                return __nfqnl_enqueue_packet(net, queue, entry);
-
         skb = entry->skb;
 
         switch (entry->pf) {
@@ -651,6 +648,9 @@ nfqnl_enqueue_packet(struct nf_queue_entry *entry, unsigned int queuenum)
                 break;
         }
 
+        if ((queue->flags & NFQA_CFG_F_GSO) || !skb_is_gso(skb))
+                return __nfqnl_enqueue_packet(net, queue, entry);
+
         nf_bridge_adjust_skb_data(skb);
         segs = skb_gso_segment(skb, 0);
         /* Does not use PTR_ERR to limit the number of error codes that can be
diff --git a/net/netfilter/xt_TCPMSS.c b/net/netfilter/xt_TCPMSS.c
index a75240f0d42b..afaebc766933 100644
--- a/net/netfilter/xt_TCPMSS.c
+++ b/net/netfilter/xt_TCPMSS.c
@@ -125,6 +125,12 @@ tcpmss_mangle_packet(struct sk_buff *skb,
 
         skb_put(skb, TCPOLEN_MSS);
 
+        /* RFC 879 states that the default MSS is 536 without specific
+         * knowledge that the destination host is prepared to accept larger.
+         * Since no MSS was provided, we MUST NOT set a value > 536.
+         */
+        newmss = min(newmss, (u16)536);
+
         opt = (u_int8_t *)tcph + sizeof(struct tcphdr);
         memmove(opt + TCPOLEN_MSS, opt, tcplen - sizeof(struct tcphdr));
 
diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c
index d0b3dd60d386..57ee84d21470 100644
--- a/net/netlink/af_netlink.c
+++ b/net/netlink/af_netlink.c
@@ -371,7 +371,7 @@ static int netlink_mmap(struct file *file, struct socket *sock,
         err = 0;
 out:
         mutex_unlock(&nlk->pg_vec_lock);
-        return 0;
+        return err;
 }
 
 static void netlink_frame_flush_dcache(const struct nl_mmap_hdr *hdr)
diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index 8ec1bca7f859..20a1bd0e6549 100644
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -2851,12 +2851,11 @@ static int packet_getname_spkt(struct socket *sock, struct sockaddr *uaddr,
                 return -EOPNOTSUPP;
 
         uaddr->sa_family = AF_PACKET;
+        memset(uaddr->sa_data, 0, sizeof(uaddr->sa_data));
         rcu_read_lock();
         dev = dev_get_by_index_rcu(sock_net(sk), pkt_sk(sk)->ifindex);
         if (dev)
-                strncpy(uaddr->sa_data, dev->name, 14);
-        else
-                memset(uaddr->sa_data, 0, 14);
+                strlcpy(uaddr->sa_data, dev->name, sizeof(uaddr->sa_data));
         rcu_read_unlock();
         *uaddr_len = sizeof(*uaddr);
 
diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c
index 2b935e7cfe7b..281c1bded1f6 100644
--- a/net/sched/sch_api.c
+++ b/net/sched/sch_api.c
@@ -291,17 +291,18 @@ struct qdisc_rate_table *qdisc_get_rtab(struct tc_ratespec *r, struct nlattr *ta
 {
         struct qdisc_rate_table *rtab;
 
+        if (tab == NULL || r->rate == 0 || r->cell_log == 0 ||
+            nla_len(tab) != TC_RTAB_SIZE)
+                return NULL;
+
         for (rtab = qdisc_rtab_list; rtab; rtab = rtab->next) {
-                if (memcmp(&rtab->rate, r, sizeof(struct tc_ratespec)) == 0) {
+                if (!memcmp(&rtab->rate, r, sizeof(struct tc_ratespec)) &&
+                    !memcmp(&rtab->data, nla_data(tab), 1024)) {
                         rtab->refcnt++;
                         return rtab;
                 }
         }
 
-        if (tab == NULL || r->rate == 0 || r->cell_log == 0 ||
-            nla_len(tab) != TC_RTAB_SIZE)
-                return NULL;
-
         rtab = kmalloc(sizeof(*rtab), GFP_KERNEL);
         if (rtab) {
                 rtab->rate = *r;
diff --git a/net/sctp/outqueue.c b/net/sctp/outqueue.c
index 32a4625fef77..be35e2dbcc9a 100644
--- a/net/sctp/outqueue.c
+++ b/net/sctp/outqueue.c
@@ -206,6 +206,8 @@ static inline int sctp_cacc_skip(struct sctp_transport *primary,
  */
 void sctp_outq_init(struct sctp_association *asoc, struct sctp_outq *q)
 {
+        memset(q, 0, sizeof(struct sctp_outq));
+
         q->asoc = asoc;
         INIT_LIST_HEAD(&q->out_chunk_list);
         INIT_LIST_HEAD(&q->control_chunk_list);
@@ -213,11 +215,7 @@ void sctp_outq_init(struct sctp_association *asoc, struct sctp_outq *q)
         INIT_LIST_HEAD(&q->sacked);
         INIT_LIST_HEAD(&q->abandoned);
 
-        q->fast_rtx = 0;
-        q->outstanding_bytes = 0;
         q->empty = 1;
-        q->cork  = 0;
-        q->out_qlen = 0;
 }
 
 /* Free the outqueue structure and any related pending chunks.
diff --git a/net/sctp/socket.c b/net/sctp/socket.c
index f631c5ff4dbf..6abb1caf9836 100644
--- a/net/sctp/socket.c
+++ b/net/sctp/socket.c
@@ -4003,6 +4003,12 @@ SCTP_STATIC void sctp_destroy_sock(struct sock *sk)
 
         /* Release our hold on the endpoint. */
         sp = sctp_sk(sk);
+        /* This could happen during socket init, thus we bail out
+         * early, since the rest of the below is not setup either.
+         */
+        if (sp->ep == NULL)
+                return;
+
         if (sp->do_auto_asconf) {
                 sp->do_auto_asconf = 0;
                 list_del(&sp->auto_asconf_list);
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 8337663aa298..f97869f1f09b 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -149,7 +149,7 @@ cpp_flags      = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE)     \
 
 ld_flags       = $(LDFLAGS) $(ldflags-y)
 
-dtc_cpp_flags  = -Wp,-MD,$(depfile).pre -nostdinc                        \
+dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc                    \
                  -I$(srctree)/arch/$(SRCARCH)/boot/dts                   \
                  -I$(srctree)/arch/$(SRCARCH)/boot/dts/include           \
                  -undef -D__DTS__
@@ -265,13 +265,13 @@ quiet_cmd_dtc = DTC     $@
 cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
         $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 \
                 -i $(dir $<) $(DTC_FLAGS) \
-                -d $(depfile).dtc $(dtc-tmp) ; \
-        cat $(depfile).pre $(depfile).dtc > $(depfile)
+                -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+        cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
 
 $(obj)/%.dtb: $(src)/%.dts FORCE
         $(call if_changed_dep,dtc)
 
-dtc-tmp = $(subst $(comma),_,$(dot-target).dts)
+dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
 
 # Bzip2
 # ---------------------------------------------------------------------------
diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
index 254d5af88956..3b41bfca636c 100644
--- a/scripts/dtc/dtc-lexer.l
+++ b/scripts/dtc/dtc-lexer.l
@@ -71,7 +71,7 @@ static int pop_input_file(void);
                         push_input_file(name);
                 }
 
-<*>^"#"(line)?{WS}+[0-9]+{WS}+{STRING}({WS}+[0-9]+)? {
+<*>^"#"(line)?[ \t]+[0-9]+[ \t]+{STRING}([ \t]+[0-9]+)? {
                         char *line, *tmp, *fn;
                         /* skip text before line # */
                         line = yytext;
diff --git a/scripts/dtc/dtc-lexer.lex.c_shipped b/scripts/dtc/dtc-lexer.lex.c_shipped
index a6c5fcdfc032..2d30f41778b7 100644
--- a/scripts/dtc/dtc-lexer.lex.c_shipped
+++ b/scripts/dtc/dtc-lexer.lex.c_shipped
@@ -405,19 +405,19 @@ static yyconst flex_int16_t yy_accept[161] =
 static yyconst flex_int32_t yy_ec[256] =
     {   0,
         1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
-        2,    2,    2,    1,    1,    1,    1,    1,    1,    1,
+        4,    4,    4,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    2,    4,    5,    6,    1,    1,    7,    8,    1,
-        1,    9,   10,   10,   11,   10,   12,   13,   14,   15,
-       15,   15,   15,   15,   15,   15,   15,   16,    1,   17,
-       18,   19,   10,   10,   20,   20,   20,   20,   20,   20,
-       21,   21,   21,   21,   21,   22,   21,   21,   21,   21,
-       21,   21,   21,   21,   23,   21,   21,   24,   21,   21,
-        1,   25,   26,    1,   21,    1,   20,   27,   28,   29,
-
-       30,   20,   21,   21,   31,   21,   21,   32,   33,   34,
-       35,   36,   21,   37,   38,   39,   40,   41,   21,   24,
-       42,   21,   43,   44,   45,    1,    1,    1,    1,    1,
+        1,    2,    5,    6,    7,    1,    1,    8,    9,    1,
+        1,   10,   11,   11,   12,   11,   13,   14,   15,   16,
+       16,   16,   16,   16,   16,   16,   16,   17,    1,   18,
+       19,   20,   11,   11,   21,   21,   21,   21,   21,   21,
+       22,   22,   22,   22,   22,   23,   22,   22,   22,   22,
+       22,   22,   22,   22,   24,   22,   22,   25,   22,   22,
+        1,   26,   27,    1,   22,    1,   21,   28,   29,   30,
+
+       31,   21,   22,   22,   32,   22,   22,   33,   34,   35,
+       36,   37,   22,   38,   39,   40,   41,   42,   22,   25,
+       43,   22,   44,   45,   46,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
@@ -434,36 +434,36 @@ static yyconst flex_int32_t yy_ec[256] =
         1,    1,    1,    1,    1
     } ;
 
-static yyconst flex_int32_t yy_meta[46] =
+static yyconst flex_int32_t yy_meta[47] =
     {   0,
-        1,    1,    1,    1,    1,    2,    3,    1,    2,    2,
-        2,    4,    5,    5,    5,    6,    1,    1,    1,    7,
-        8,    8,    8,    8,    1,    1,    7,    7,    7,    7,
-        8,    8,    8,    8,    8,    8,    8,    8,    8,    8,
-        8,    8,    3,    1,    1
+        1,    1,    1,    1,    1,    1,    2,    3,    1,    2,
+        2,    2,    4,    5,    5,    5,    6,    1,    1,    1,
+        7,    8,    8,    8,    8,    1,    1,    7,    7,    7,
+        7,    8,    8,    8,    8,    8,    8,    8,    8,    8,
+        8,    8,    8,    3,    1,    1
     } ;
 
 static yyconst flex_int16_t yy_base[175] =
     {   0,
-        0,  388,  381,   40,   41,  386,   71,  385,   34,   44,
-      390,  395,   60,   62,  371,  112,  111,  111,  111,  104,
-      370,  106,  371,  342,  124,  119,    0,  144,  395,    0,
-      123,    0,  159,  153,  165,  167,  395,  130,  395,  382,
-      395,    0,  372,  122,  395,  157,  374,  379,  350,   21,
-      346,  349,  395,  395,  395,  395,  395,  362,  395,  395,
-      181,  346,  342,  395,  359,    0,  191,  343,  190,  351,
-      350,    0,    0,    0,  173,  362,  177,  367,  357,  329,
-      335,  328,  337,  331,  206,  329,  334,  327,  395,  338,
-      170,  314,  346,  345,  318,  325,  343,  158,  316,  212,
-
-      322,  319,  320,  395,  340,  336,  308,  305,  314,  304,
-      295,  138,  208,  220,  395,  292,  305,  265,  264,  254,
-      201,  222,  285,  275,  273,  270,  236,  235,  225,  115,
-      395,  395,  252,  216,  216,  217,  214,  230,  209,  220,
-      213,  239,  211,  217,  216,  209,  229,  395,  240,  225,
-      206,  169,  395,  395,  116,  106,   99,   54,  395,  395,
-      254,  260,  268,  272,  276,  282,  289,  293,  301,  309,
-      313,  319,  327,  335
+        0,  385,  378,   40,   41,  383,   72,  382,   34,   44,
+      388,  393,   61,  117,  368,  116,  115,  115,  115,   48,
+      367,  107,  368,  339,  127,  120,    0,  147,  393,    0,
+      127,    0,  133,  156,  168,  153,  393,  125,  393,  380,
+      393,    0,  369,  127,  393,  160,  371,  377,  347,   21,
+      343,  346,  393,  393,  393,  393,  393,  359,  393,  393,
+      183,  343,  339,  393,  356,    0,  183,  340,  187,  348,
+      347,    0,    0,    0,  178,  359,  195,  365,  354,  326,
+      332,  325,  334,  328,  204,  326,  331,  324,  393,  335,
+      150,  311,  343,  342,  315,  322,  340,  179,  313,  207,
+
+      319,  316,  317,  393,  337,  333,  305,  302,  311,  301,
+      310,  190,  338,  337,  393,  307,  322,  301,  305,  277,
+      208,  311,  307,  278,  271,  270,  248,  246,  213,  130,
+      393,  393,  263,  235,  207,  221,  218,  229,  213,  213,
+      206,  234,  218,  210,  208,  193,  219,  393,  223,  204,
+      176,  157,  393,  393,  120,  106,   97,  119,  393,  393,
+      245,  251,  259,  263,  267,  273,  280,  284,  292,  300,
+      304,  310,  318,  326
     } ;
 
 static yyconst flex_int16_t yy_def[175] =
@@ -489,108 +489,108 @@ static yyconst flex_int16_t yy_def[175] =
       160,  160,  160,  160
     } ;
 
-static yyconst flex_int16_t yy_nxt[441] =
+static yyconst flex_int16_t yy_nxt[440] =
     {   0,
-       12,   13,   14,   15,   16,   12,   17,   18,   12,   12,
-       12,   19,   12,   12,   12,   12,   20,   21,   22,   23,
-       23,   23,   23,   23,   12,   12,   23,   23,   23,   23,
+       12,   13,   14,   13,   15,   16,   12,   17,   18,   12,
+       12,   12,   19,   12,   12,   12,   12,   20,   21,   22,
+       23,   23,   23,   23,   23,   12,   12,   23,   23,   23,
        23,   23,   23,   23,   23,   23,   23,   23,   23,   23,
-       23,   23,   12,   24,   12,   25,   34,   35,   35,   25,
-       81,   26,   26,   27,   27,   27,   34,   35,   35,   82,
-       28,   36,   36,   36,   36,  159,   29,   28,   28,   28,
-       28,   12,   13,   14,   15,   16,   30,   17,   18,   30,
-       30,   30,   26,   30,   30,   30,   12,   20,   21,   22,
-       31,   31,   31,   31,   31,   32,   12,   31,   31,   31,
+       23,   23,   23,   12,   24,   12,   25,   34,   35,   35,
+       25,   81,   26,   26,   27,   27,   27,   34,   35,   35,
+       82,   28,   36,   36,   36,   53,   54,   29,   28,   28,
+       28,   28,   12,   13,   14,   13,   15,   16,   30,   17,
+       18,   30,   30,   30,   26,   30,   30,   30,   12,   20,
+       21,   22,   31,   31,   31,   31,   31,   32,   12,   31,
 
        31,   31,   31,   31,   31,   31,   31,   31,   31,   31,
-       31,   31,   31,   12,   24,   12,   39,   41,   45,   47,
-       53,   54,   48,   56,   57,   61,   61,   47,   66,   45,
-       48,   66,   66,   66,   39,   46,   40,   49,   59,   50,
-      158,   51,  122,   52,  157,   49,   46,   50,  136,   63,
-      137,   52,  156,   43,   40,   62,   65,   65,   65,   59,
-       61,   61,  123,   65,   75,   69,   69,   69,   36,   36,
-       65,   65,   65,   65,   70,   71,   72,   69,   69,   69,
-       45,   46,   61,   61,  109,   77,   70,   71,   93,  110,
-       68,   70,   71,   85,   85,   85,   66,   46,  155,   66,
-
-       66,   66,   69,   69,   69,  122,   59,  100,  100,   61,
-       61,   70,   71,  100,  100,  148,  112,  154,   85,   85,
-       85,   61,   61,  129,  129,  123,  129,  129,  135,  135,
-      135,  142,  142,  148,  143,  149,  153,  135,  135,  135,
-      142,  142,  160,  143,  152,  151,  150,  146,  145,  144,
-      141,  140,  139,  149,   38,   38,   38,   38,   38,   38,
-       38,   38,   42,  138,  134,  133,   42,   42,   44,   44,
-       44,   44,   44,   44,   44,   44,   58,   58,   58,   58,
-       64,  132,   64,   66,  131,  130,   66,  160,   66,   66,
-       67,  128,  127,   67,   67,   67,   67,   73,  126,   73,
-
-       73,   76,   76,   76,   76,   76,   76,   76,   76,   78,
-       78,   78,   78,   78,   78,   78,   78,   91,  125,   91,
-       92,  124,   92,   92,  120,   92,   92,  121,  121,  121,
-      121,  121,  121,  121,  121,  147,  147,  147,  147,  147,
-      147,  147,  147,  119,  118,  117,  116,  115,   47,  114,
-      110,  113,  111,  108,  107,  106,   48,  105,  104,   89,
-      103,  102,  101,   99,   98,   97,   96,   95,   94,   79,
-       77,   90,   89,   88,   59,   87,   86,   59,   84,   83,
-       80,   79,   77,   74,  160,   60,   59,   55,   37,  160,
-       33,   25,   26,   25,   11,  160,  160,  160,  160,  160,
+       31,   31,   31,   31,   31,   12,   24,   12,   36,   36,
+       36,   39,   41,   45,   47,   56,   57,   48,   61,   47,
+       39,  159,   48,   66,   61,   45,   66,   66,   66,  158,
+       46,   40,   49,   59,   50,  157,   51,   49,   52,   50,
+       40,   63,   46,   52,   36,   36,   36,  156,   43,   62,
+       65,   65,   65,   59,  136,   68,  137,   65,   75,   69,
+       69,   69,   70,   71,   65,   65,   65,   65,   70,   71,
+       72,   69,   69,   69,   61,   46,   45,  155,  154,   66,
+       70,   71,   66,   66,   66,  122,   85,   85,   85,   59,
+
+       69,   69,   69,   46,   77,  100,  109,   93,  100,   70,
+       71,  110,  112,  122,  129,  123,  153,   85,   85,   85,
+      135,  135,  135,  148,  148,  160,  135,  135,  135,  152,
+      142,  142,  142,  123,  143,  142,  142,  142,  151,  143,
+      150,  146,  145,  149,  149,   38,   38,   38,   38,   38,
+       38,   38,   38,   42,  144,  141,  140,   42,   42,   44,
+       44,   44,   44,   44,   44,   44,   44,   58,   58,   58,
+       58,   64,  139,   64,   66,  138,  134,   66,  133,   66,
+       66,   67,  132,  131,   67,   67,   67,   67,   73,  130,
+       73,   73,   76,   76,   76,   76,   76,   76,   76,   76,
+
+       78,   78,   78,   78,   78,   78,   78,   78,   91,  160,
+       91,   92,  129,   92,   92,  128,   92,   92,  121,  121,
+      121,  121,  121,  121,  121,  121,  147,  147,  147,  147,
+      147,  147,  147,  147,  127,  126,  125,  124,   61,   61,
+      120,  119,  118,  117,  116,  115,   47,  114,  110,  113,
+      111,  108,  107,  106,   48,  105,  104,   89,  103,  102,
+      101,   99,   98,   97,   96,   95,   94,   79,   77,   90,
+       89,   88,   59,   87,   86,   59,   84,   83,   80,   79,
+       77,   74,  160,   60,   59,   55,   37,  160,   33,   25,
+       26,   25,   11,  160,  160,  160,  160,  160,  160,  160,
 
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
-      160,  160,  160,  160,  160,  160,  160,  160,  160,  160
+      160,  160,  160,  160,  160,  160,  160,  160,  160
     } ;
 
-static yyconst flex_int16_t yy_chk[441] =
+static yyconst flex_int16_t yy_chk[440] =
     {   0,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
         1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    4,    9,    9,    9,   10,
-       50,    4,    5,    5,    5,    5,   10,   10,   10,   50,
-        5,   13,   13,   14,   14,  158,    5,    5,    5,    5,
-        5,    7,    7,    7,    7,    7,    7,    7,    7,    7,
+        1,    1,    1,    1,    1,    1,    4,    9,    9,    9,
+       10,   50,    4,    5,    5,    5,    5,   10,   10,   10,
+       50,    5,   13,   13,   13,   20,   20,    5,    5,    5,
+        5,    5,    7,    7,    7,    7,    7,    7,    7,    7,
         7,    7,    7,    7,    7,    7,    7,    7,    7,    7,
         7,    7,    7,    7,    7,    7,    7,    7,    7,    7,
 
         7,    7,    7,    7,    7,    7,    7,    7,    7,    7,
-        7,    7,    7,    7,    7,    7,   16,   17,   18,   19,
-       20,   20,   19,   22,   22,   25,   25,   26,   31,   44,
-       26,   31,   31,   31,   38,   18,   16,   19,   31,   19,
-      157,   19,  112,   19,  156,   26,   44,   26,  130,   26,
-      130,   26,  155,   17,   38,   25,   28,   28,   28,   28,
-       33,   33,  112,   28,   46,   34,   34,   34,   36,   36,
-       28,   28,   28,   28,   34,   34,   34,   35,   35,   35,
-       75,   46,   61,   61,   98,   77,   35,   35,   77,   98,
-       33,   91,   91,   61,   61,   61,   67,   75,  152,   67,
-
-       67,   67,   69,   69,   69,  121,   67,   85,   85,  113,
-      113,   69,   69,  100,  100,  143,  100,  151,   85,   85,
-       85,  114,  114,  122,  122,  121,  129,  129,  135,  135,
-      135,  138,  138,  147,  138,  143,  150,  129,  129,  129,
-      142,  142,  149,  142,  146,  145,  144,  141,  140,  139,
-      137,  136,  134,  147,  161,  161,  161,  161,  161,  161,
-      161,  161,  162,  133,  128,  127,  162,  162,  163,  163,
-      163,  163,  163,  163,  163,  163,  164,  164,  164,  164,
-      165,  126,  165,  166,  125,  124,  166,  123,  166,  166,
-      167,  120,  119,  167,  167,  167,  167,  168,  118,  168,
-
-      168,  169,  169,  169,  169,  169,  169,  169,  169,  170,
-      170,  170,  170,  170,  170,  170,  170,  171,  117,  171,
-      172,  116,  172,  172,  111,  172,  172,  173,  173,  173,
-      173,  173,  173,  173,  173,  174,  174,  174,  174,  174,
-      174,  174,  174,  110,  109,  108,  107,  106,  105,  103,
-      102,  101,   99,   97,   96,   95,   94,   93,   92,   90,
-       88,   87,   86,   84,   83,   82,   81,   80,   79,   78,
-       76,   71,   70,   68,   65,   63,   62,   58,   52,   51,
-       49,   48,   47,   43,   40,   24,   23,   21,   15,   11,
-        8,    6,    3,    2,  160,  160,  160,  160,  160,  160,
+        7,    7,    7,    7,    7,    7,    7,    7,   14,   14,
+       14,   16,   17,   18,   19,   22,   22,   19,   25,   26,
+       38,  158,   26,   31,   33,   44,   31,   31,   31,  157,
+       18,   16,   19,   31,   19,  156,   19,   26,   19,   26,
+       38,   26,   44,   26,   36,   36,   36,  155,   17,   25,
+       28,   28,   28,   28,  130,   33,  130,   28,   46,   34,
+       34,   34,   91,   91,   28,   28,   28,   28,   34,   34,
+       34,   35,   35,   35,   61,   46,   75,  152,  151,   67,
+       35,   35,   67,   67,   67,  112,   61,   61,   61,   67,
+
+       69,   69,   69,   75,   77,   85,   98,   77,  100,   69,
+       69,   98,  100,  121,  129,  112,  150,   85,   85,   85,
+      135,  135,  135,  143,  147,  149,  129,  129,  129,  146,
+      138,  138,  138,  121,  138,  142,  142,  142,  145,  142,
+      144,  141,  140,  143,  147,  161,  161,  161,  161,  161,
+      161,  161,  161,  162,  139,  137,  136,  162,  162,  163,
+      163,  163,  163,  163,  163,  163,  163,  164,  164,  164,
+      164,  165,  134,  165,  166,  133,  128,  166,  127,  166,
+      166,  167,  126,  125,  167,  167,  167,  167,  168,  124,
+      168,  168,  169,  169,  169,  169,  169,  169,  169,  169,
+
+      170,  170,  170,  170,  170,  170,  170,  170,  171,  123,
+      171,  172,  122,  172,  172,  120,  172,  172,  173,  173,
+      173,  173,  173,  173,  173,  173,  174,  174,  174,  174,
+      174,  174,  174,  174,  119,  118,  117,  116,  114,  113,
+      111,  110,  109,  108,  107,  106,  105,  103,  102,  101,
+       99,   97,   96,   95,   94,   93,   92,   90,   88,   87,
+       86,   84,   83,   82,   81,   80,   79,   78,   76,   71,
+       70,   68,   65,   63,   62,   58,   52,   51,   49,   48,
+       47,   43,   40,   24,   23,   21,   15,   11,    8,    6,
+        3,    2,  160,  160,  160,  160,  160,  160,  160,  160,
 
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
       160,  160,  160,  160,  160,  160,  160,  160,  160,  160,
-      160,  160,  160,  160,  160,  160,  160,  160,  160,  160
+      160,  160,  160,  160,  160,  160,  160,  160,  160
     } ;
 
 static yy_state_type yy_last_accepting_state;
diff --git a/scripts/dtc/dtc-parser.tab.c_shipped b/scripts/dtc/dtc-parser.tab.c_shipped
index 4af55900a15b..ee1d8c3042fb 100644
--- a/scripts/dtc/dtc-parser.tab.c_shipped
+++ b/scripts/dtc/dtc-parser.tab.c_shipped
@@ -1,10 +1,8 @@
+/* A Bison parser, made by GNU Bison 2.5.  */
 
-/* A Bison parser, made by GNU Bison 2.4.1.  */
-
-/* Skeleton implementation for Bison's Yacc-like parsers in C
+/* Bison implementation for Yacc-like parsers in C
    
-      Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
-   Free Software Foundation, Inc.
+      Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc.
    
    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -46,7 +44,7 @@
 #define YYBISON 1
 
 /* Bison version.  */
-#define YYBISON_VERSION "2.4.1"
+#define YYBISON_VERSION "2.5"
 
 /* Skeleton name.  */
 #define YYSKELETON_NAME "yacc.c"
@@ -67,7 +65,7 @@
 
 /* Copy the first part of user declarations.  */
 
-/* Line 189 of yacc.c  */
+/* Line 268 of yacc.c  */
 #line 21 "dtc-parser.y"
 
 #include <stdio.h>
@@ -88,8 +86,8 @@ static unsigned long long eval_literal(const char *s, int base, int bits);
 static unsigned char eval_char_literal(const char *s);
 
 
-/* Line 189 of yacc.c  */
-#line 93 "dtc-parser.tab.c"
+/* Line 268 of yacc.c  */
+#line 91 "dtc-parser.tab.c"
 
 /* Enabling traces.  */
 #ifndef YYDEBUG
@@ -147,7 +145,7 @@ static unsigned char eval_char_literal(const char *s);
 typedef union YYSTYPE
 {
 
-/* Line 214 of yacc.c  */
+/* Line 293 of yacc.c  */
 #line 40 "dtc-parser.y"
 
         char *propnodename;
@@ -171,8 +169,8 @@ typedef union YYSTYPE
 
 
 
-/* Line 214 of yacc.c  */
-#line 176 "dtc-parser.tab.c"
+/* Line 293 of yacc.c  */
+#line 174 "dtc-parser.tab.c"
 } YYSTYPE;
 # define YYSTYPE_IS_TRIVIAL 1
 # define yystype YYSTYPE /* obsolescent; will be withdrawn */
@@ -183,8 +181,8 @@ typedef union YYSTYPE
 /* Copy the second part of user declarations.  */
 
 
-/* Line 264 of yacc.c  */
-#line 188 "dtc-parser.tab.c"
+/* Line 343 of yacc.c  */
+#line 186 "dtc-parser.tab.c"
 
 #ifdef short
 # undef short
@@ -234,7 +232,7 @@ typedef short int yytype_int16;
 #define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
 
 #ifndef YY_
-# if YYENABLE_NLS
+# if defined YYENABLE_NLS && YYENABLE_NLS
 #  if ENABLE_NLS
 #   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
 #   define YY_(msgid) dgettext ("bison-runtime", msgid)
@@ -287,11 +285,11 @@ YYID (yyi)
 #    define alloca _alloca
 #   else
 #    define YYSTACK_ALLOC alloca
-#    if ! defined _ALLOCA_H && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+#    if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
      || defined __cplusplus || defined _MSC_VER)
 #     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#     ifndef _STDLIB_H
-#      define _STDLIB_H 1
+#     ifndef EXIT_SUCCESS
+#      define EXIT_SUCCESS 0
 #     endif
 #    endif
 #   endif
@@ -314,24 +312,24 @@ YYID (yyi)
 #  ifndef YYSTACK_ALLOC_MAXIMUM
 #   define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
 #  endif
-#  if (defined __cplusplus && ! defined _STDLIB_H \
+#  if (defined __cplusplus && ! defined EXIT_SUCCESS \
        && ! ((defined YYMALLOC || defined malloc) \
              && (defined YYFREE || defined free)))
 #   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#   ifndef _STDLIB_H
-#    define _STDLIB_H 1
+#   ifndef EXIT_SUCCESS
+#    define EXIT_SUCCESS 0
 #   endif
 #  endif
 #  ifndef YYMALLOC
 #   define YYMALLOC malloc
-#   if ! defined malloc && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+#   if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
      || defined __cplusplus || defined _MSC_VER)
 void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
 #   endif
 #  endif
 #  ifndef YYFREE
 #   define YYFREE free
-#   if ! defined free && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+#   if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
      || defined __cplusplus || defined _MSC_VER)
 void free (void *); /* INFRINGES ON USER NAME SPACE */
 #   endif
@@ -360,23 +358,7 @@ union yyalloc
      ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
       + YYSTACK_GAP_MAXIMUM)
 
-/* Copy COUNT objects from FROM to TO.  The source and destination do
-   not overlap.  */
-# ifndef YYCOPY
-#  if defined __GNUC__ && 1 < __GNUC__
-#   define YYCOPY(To, From, Count) \
-      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
-#  else
-#   define YYCOPY(To, From, Count)              \
-      do                                        \
-        {                                       \
-          YYSIZE_T yyi;                         \
-          for (yyi = 0; yyi < (Count); yyi++)   \
-            (To)[yyi] = (From)[yyi];            \
-        }                                       \
-      while (YYID (0))
-#  endif
-# endif
+# define YYCOPY_NEEDED 1
 
 /* Relocate STACK from its old location to the new one.  The
    local variables YYSIZE and YYSTACKSIZE give the old and new number of
@@ -396,6 +378,26 @@ union yyalloc
 
 #endif
 
+#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
+/* Copy COUNT objects from FROM to TO.  The source and destination do
+   not overlap.  */
+# ifndef YYCOPY
+#  if defined __GNUC__ && 1 < __GNUC__
+#   define YYCOPY(To, From, Count) \
+      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
+#  else
+#   define YYCOPY(To, From, Count)              \
+      do                                        \
+        {                                       \
+          YYSIZE_T yyi;                         \
+          for (yyi = 0; yyi < (Count); yyi++)   \
+            (To)[yyi] = (From)[yyi];            \
+        }                                       \
+      while (YYID (0))
+#  endif
+# endif
+#endif /* !YYCOPY_NEEDED */
+
 /* YYFINAL -- State number of the termination state.  */
 #define YYFINAL  4
 /* YYLAST -- Last index in YYTABLE.  */
@@ -571,8 +573,8 @@ static const yytype_uint8 yyr2[] =
        2,     0,     2,     2,     0,     2,     2,     2,     3,     2
 };
 
-/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
-   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
+/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM.
+   Performed when YYTABLE doesn't specify something else to do.  Zero
    means the default is an error.  */
 static const yytype_uint8 yydefact[] =
 {
@@ -633,8 +635,7 @@ static const yytype_int8 yypgoto[] =
 
 /* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
    positive, shift that token.  If negative, reduce the rule which
-   number is the opposite.  If zero, do what YYDEFACT says.
-   If YYTABLE_NINF, syntax error.  */
+   number is the opposite.  If YYTABLE_NINF, syntax error.  */
 #define YYTABLE_NINF -1
 static const yytype_uint8 yytable[] =
 {
@@ -654,6 +655,12 @@ static const yytype_uint8 yytable[] =
      137,     0,    73,   139
 };
 
+#define yypact_value_is_default(yystate) \
+  ((yystate) == (-78))
+
+#define yytable_value_is_error(yytable_value) \
+  YYID (0)
+
 static const yytype_int16 yycheck[] =
 {
        5,    38,    39,    17,    18,    19,    12,    12,    17,    18,
@@ -705,9 +712,18 @@ static const yytype_uint8 yystos[] =
 
 /* Like YYERROR except do call yyerror.  This remains here temporarily
    to ease the transition to the new meaning of YYERROR, for GCC.
-   Once GCC version 2 has supplanted version 1, this can go.  */
+   Once GCC version 2 has supplanted version 1, this can go.  However,
+   YYFAIL appears to be in use.  Nevertheless, it is formally deprecated
+   in Bison 2.4.2's NEWS entry, where a plan to phase it out is
+   discussed.  */
 
 #define YYFAIL          goto yyerrlab
+#if defined YYFAIL
+  /* This is here to suppress warnings from the GCC cpp's
+     -Wunused-macros.  Normally we don't worry about that warning, but
+     some users do, and we want to make it easy for users to remove
+     YYFAIL uses, which will produce warnings from Bison 2.5.  */
+#endif
 
 #define YYRECOVERING()  (!!yyerrstatus)
 
@@ -717,7 +733,6 @@ do								\
     {                                                           \
       yychar = (Token);                                         \
       yylval = (Value);                                         \
-      yytoken = YYTRANSLATE (yychar);                           \
       YYPOPSTACK (1);                                           \
       goto yybackup;                                            \
     }                                                           \
@@ -759,19 +774,10 @@ while (YYID (0))
 #endif
 
 
-/* YY_LOCATION_PRINT -- Print the location on the stream.
-   This macro was not mandated originally: define only if we know
-   we won't break user code: when these are the locations we know.  */
+/* This macro is provided for backward compatibility. */
 
 #ifndef YY_LOCATION_PRINT
-# if YYLTYPE_IS_TRIVIAL
-#  define YY_LOCATION_PRINT(File, Loc)                  \
-     fprintf (File, "%d.%d-%d.%d",                      \
-              (Loc).first_line, (Loc).first_column,     \
-              (Loc).last_line,  (Loc).last_column)
-# else
-#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
-# endif
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
 #endif
 
 
@@ -963,7 +969,6 @@ int yydebug;
 # define YYMAXDEPTH 10000
 #endif
 
-
 
 #if YYERROR_VERBOSE
 
@@ -1066,115 +1071,142 @@ yytnamerr (char *yyres, const char *yystr)
 }
 # endif
 
-/* Copy into YYRESULT an error message about the unexpected token
-   YYCHAR while in state YYSTATE.  Return the number of bytes copied,
-   including the terminating null byte.  If YYRESULT is null, do not
-   copy anything; just return the number of bytes that would be
-   copied.  As a special case, return 0 if an ordinary "syntax error"
-   message will do.  Return YYSIZE_MAXIMUM if overflow occurs during
-   size calculation.  */
-static YYSIZE_T
-yysyntax_error (char *yyresult, int yystate, int yychar)
-{
-  int yyn = yypact[yystate];
+/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
+   about the unexpected token YYTOKEN for the state stack whose top is
+   YYSSP.
 
-  if (! (YYPACT_NINF < yyn && yyn <= YYLAST))
-    return 0;
-  else
+   Return 0 if *YYMSG was successfully written.  Return 1 if *YYMSG is
+   not large enough to hold the message.  In that case, also set
+   *YYMSG_ALLOC to the required number of bytes.  Return 2 if the
+   required number of bytes is too large to store.  */
+static int
+yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
+                yytype_int16 *yyssp, int yytoken)
+{
+  YYSIZE_T yysize0 = yytnamerr (0, yytname[yytoken]);
+  YYSIZE_T yysize = yysize0;
+  YYSIZE_T yysize1;
+  enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+  /* Internationalized format string. */
+  const char *yyformat = 0;
+  /* Arguments of yyformat. */
+  char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+  /* Number of reported tokens (one for the "unexpected", one per
+     "expected"). */
+  int yycount = 0;
+
+  /* There are many possibilities here to consider:
+     - Assume YYFAIL is not used.  It's too flawed to consider.  See
+       <http://lists.gnu.org/archive/html/bison-patches/2009-12/msg00024.html>
+       for details.  YYERROR is fine as it does not invoke this
+       function.
+     - If this state is a consistent state with a default action, then
+       the only way this function was invoked is if the default action
+       is an error action.  In that case, don't check for expected
+       tokens because there are none.
+     - The only way there can be no lookahead present (in yychar) is if
+       this state is a consistent state with a default action.  Thus,
+       detecting the absence of a lookahead is sufficient to determine
+       that there is no unexpected or expected token to report.  In that
+       case, just report a simple "syntax error".
+     - Don't assume there isn't a lookahead just because this state is a
+       consistent state with a default action.  There might have been a
+       previous inconsistent state, consistent state with a non-default
+       action, or user semantic action that manipulated yychar.
+     - Of course, the expected token list depends on states to have
+       correct lookahead information, and it depends on the parser not
+       to perform extra reductions after fetching a lookahead from the
+       scanner and before detecting a syntax error.  Thus, state merging
+       (from LALR or IELR) and default reductions corrupt the expected
+       token list.  However, the list is correct for canonical LR with
+       one exception: it will still contain any token that will not be
+       accepted due to an error action in a later state.
+  */
+  if (yytoken != YYEMPTY)
     {
-      int yytype = YYTRANSLATE (yychar);
-      YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
-      YYSIZE_T yysize = yysize0;
-      YYSIZE_T yysize1;
-      int yysize_overflow = 0;
-      enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
-      char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
-      int yyx;
-
-# if 0
-      /* This is so xgettext sees the translatable formats that are
-         constructed on the fly.  */
-      YY_("syntax error, unexpected %s");
-      YY_("syntax error, unexpected %s, expecting %s");
-      YY_("syntax error, unexpected %s, expecting %s or %s");
-      YY_("syntax error, unexpected %s, expecting %s or %s or %s");
-      YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
-# endif
-      char *yyfmt;
-      char const *yyf;
-      static char const yyunexpected[] = "syntax error, unexpected %s";
-      static char const yyexpecting[] = ", expecting %s";
-      static char const yyor[] = " or %s";
-      char yyformat[sizeof yyunexpected
-                    + sizeof yyexpecting - 1
-                    + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
-                       * (sizeof yyor - 1))];
-      char const *yyprefix = yyexpecting;
-
-      /* Start YYX at -YYN if negative to avoid negative indexes in
-         YYCHECK.  */
-      int yyxbegin = yyn < 0 ? -yyn : 0;
-
-      /* Stay within bounds of both yycheck and yytname.  */
-      int yychecklim = YYLAST - yyn + 1;
-      int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
-      int yycount = 1;
-
-      yyarg[0] = yytname[yytype];
-      yyfmt = yystpcpy (yyformat, yyunexpected);
-
-      for (yyx = yyxbegin; yyx < yyxend; ++yyx)
-        if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
-          {
-            if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
-              {
-                yycount = 1;
-                yysize = yysize0;
-                yyformat[sizeof yyunexpected - 1] = '\0';
-                break;
-              }
-            yyarg[yycount++] = yytname[yyx];
-            yysize1 = yysize + yytnamerr (0, yytname[yyx]);
-            yysize_overflow |= (yysize1 < yysize);
-            yysize = yysize1;
-            yyfmt = yystpcpy (yyfmt, yyprefix);
-            yyprefix = yyor;
-          }
+      int yyn = yypact[*yyssp];
+      yyarg[yycount++] = yytname[yytoken];
+      if (!yypact_value_is_default (yyn))
+        {
+          /* Start YYX at -YYN if negative to avoid negative indexes in
+             YYCHECK.  In other words, skip the first -YYN actions for
+             this state because they are default actions.  */
+          int yyxbegin = yyn < 0 ? -yyn : 0;
+          /* Stay within bounds of both yycheck and yytname.  */
+          int yychecklim = YYLAST - yyn + 1;
+          int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+          int yyx;
+
+          for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+            if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
+                && !yytable_value_is_error (yytable[yyx + yyn]))
+              {
+                if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+                  {
+                    yycount = 1;
+                    yysize = yysize0;
+                    break;
+                  }
+                yyarg[yycount++] = yytname[yyx];
+                yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+                if (! (yysize <= yysize1
+                       && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+                  return 2;
+                yysize = yysize1;
+              }
+        }
+    }
 
-      yyf = YY_(yyformat);
-      yysize1 = yysize + yystrlen (yyf);
-      yysize_overflow |= (yysize1 < yysize);
-      yysize = yysize1;
+  switch (yycount)
+    {
+# define YYCASE_(N, S)                      \
+      case N:                               \
+        yyformat = S;                       \
+      break
+      YYCASE_(0, YY_("syntax error"));
+      YYCASE_(1, YY_("syntax error, unexpected %s"));
+      YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
+      YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
+      YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
+      YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
+# undef YYCASE_
+    }
 
-      if (yysize_overflow)
-        return YYSIZE_MAXIMUM;
+  yysize1 = yysize + yystrlen (yyformat);
+  if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+    return 2;
+  yysize = yysize1;
 
-      if (yyresult)
-        {
-          /* Avoid sprintf, as that infringes on the user's name space.
-             Don't have undefined behavior even if the translation
-             produced a string with the wrong number of "%s"s.  */
-          char *yyp = yyresult;
-          int yyi = 0;
-          while ((*yyp = *yyf) != '\0')
-            {
-              if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
-                {
-                  yyp += yytnamerr (yyp, yyarg[yyi++]);
-                  yyf += 2;
-                }
-              else
-                {
-                  yyp++;
-                  yyf++;
-                }
-            }
-        }
-      return yysize;
+  if (*yymsg_alloc < yysize)
+    {
+      *yymsg_alloc = 2 * yysize;
+      if (! (yysize <= *yymsg_alloc
+             && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
+        *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
+      return 1;
     }
+
+  /* Avoid sprintf, as that infringes on the user's name space.
+     Don't have undefined behavior even if the translation
+     produced a string with the wrong number of "%s"s.  */
+  {
+    char *yyp = *yymsg;
+    int yyi = 0;
+    while ((*yyp = *yyformat) != '\0')
+      if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
+        {
+          yyp += yytnamerr (yyp, yyarg[yyi++]);
+          yyformat += 2;
+        }
+      else
+        {
+          yyp++;
+          yyformat++;
+        }
+  }
+  return 0;
 }
 #endif /* YYERROR_VERBOSE */
-
 
 /*-----------------------------------------------.
 | Release the memory associated to this symbol.  |
@@ -1207,6 +1239,7 @@ yydestruct (yymsg, yytype, yyvaluep)
     }
 }
 
+
 /* Prevent warnings from -Wmissing-prototypes.  */
 #ifdef YYPARSE_PARAM
 #if defined __STDC__ || defined __cplusplus
@@ -1233,10 +1266,9 @@ YYSTYPE yylval;
 int yynerrs;
 
 
-
-/*-------------------------.
-| yyparse or yypush_parse.  |
-`-------------------------*/
+/*----------.
+| yyparse.  |
+`----------*/
 
 #ifdef YYPARSE_PARAM
 #if (defined __STDC__ || defined __C99__FUNC__ \
@@ -1260,8 +1292,6 @@ yyparse ()
 #endif
 #endif
 {
-
-
     int yystate;
     /* Number of tokens to shift before error messages enabled.  */
     int yyerrstatus;
@@ -1416,7 +1446,7 @@ yybackup:
 
   /* First try to decide what to do without reference to lookahead token.  */
   yyn = yypact[yystate];
-  if (yyn == YYPACT_NINF)
+  if (yypact_value_is_default (yyn))
     goto yydefault;
 
   /* Not known => get a lookahead token if don't already have one.  */
@@ -1447,8 +1477,8 @@ yybackup:
   yyn = yytable[yyn];
   if (yyn <= 0)
     {
-      if (yyn == 0 || yyn == YYTABLE_NINF)
-        goto yyerrlab;
+      if (yytable_value_is_error (yyn))
+        goto yyerrlab;
       yyn = -yyn;
       goto yyreduce;
     }
@@ -1503,72 +1533,72 @@ yyreduce:
     {
         case 2:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 110 "dtc-parser.y"
     {
                         the_boot_info = build_boot_info((yyvsp[(3) - (4)].re), (yyvsp[(4) - (4)].node),
                                                         guess_boot_cpuid((yyvsp[(4) - (4)].node)));
-                ;}
+                }
     break;
 
   case 3:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 118 "dtc-parser.y"
     {
                         (yyval.re) = NULL;
-                ;}
+                }
     break;
 
   case 4:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 122 "dtc-parser.y"
     {
                         (yyval.re) = chain_reserve_entry((yyvsp[(1) - (2)].re), (yyvsp[(2) - (2)].re));
-                ;}
+                }
     break;
 
   case 5:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 129 "dtc-parser.y"
     {
                         (yyval.re) = build_reserve_entry((yyvsp[(2) - (4)].integer), (yyvsp[(3) - (4)].integer));
-                ;}
+                }
     break;
 
   case 6:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 133 "dtc-parser.y"
     {
                         add_label(&(yyvsp[(2) - (2)].re)->labels, (yyvsp[(1) - (2)].labelref));
                         (yyval.re) = (yyvsp[(2) - (2)].re);
-                ;}
+                }
     break;
 
   case 7:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 141 "dtc-parser.y"
     {
                         (yyval.node) = name_node((yyvsp[(2) - (2)].node), "");
-                ;}
+                }
     break;
 
   case 8:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 145 "dtc-parser.y"
     {
                         (yyval.node) = merge_nodes((yyvsp[(1) - (3)].node), (yyvsp[(3) - (3)].node));
-                ;}
+                }
     break;
 
   case 9:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 149 "dtc-parser.y"
     {
                         struct node *target = get_node_by_ref((yyvsp[(1) - (3)].node), (yyvsp[(2) - (3)].labelref));
@@ -1578,12 +1608,12 @@ yyreduce:
                         else
                                 print_error("label or path, '%s', not found", (yyvsp[(2) - (3)].labelref));
                         (yyval.node) = (yyvsp[(1) - (3)].node);
-                ;}
+                }
     break;
 
   case 10:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 159 "dtc-parser.y"
     {
                         struct node *target = get_node_by_ref((yyvsp[(1) - (4)].node), (yyvsp[(3) - (4)].labelref));
@@ -1594,112 +1624,112 @@ yyreduce:
                                 delete_node(target);
 
                         (yyval.node) = (yyvsp[(1) - (4)].node);
-                ;}
+                }
     break;
 
   case 11:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 173 "dtc-parser.y"
     {
                         (yyval.node) = build_node((yyvsp[(2) - (5)].proplist), (yyvsp[(3) - (5)].nodelist));
-                ;}
+                }
     break;
 
   case 12:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 180 "dtc-parser.y"
     {
                         (yyval.proplist) = NULL;
-                ;}
+                }
     break;
 
   case 13:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 184 "dtc-parser.y"
     {
                         (yyval.proplist) = chain_property((yyvsp[(2) - (2)].prop), (yyvsp[(1) - (2)].proplist));
-                ;}
+                }
     break;
 
   case 14:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 191 "dtc-parser.y"
     {
                         (yyval.prop) = build_property((yyvsp[(1) - (4)].propnodename), (yyvsp[(3) - (4)].data));
-                ;}
+                }
     break;
 
   case 15:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 195 "dtc-parser.y"
     {
                         (yyval.prop) = build_property((yyvsp[(1) - (2)].propnodename), empty_data);
-                ;}
+                }
     break;
 
   case 16:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 199 "dtc-parser.y"
     {
                         (yyval.prop) = build_property_delete((yyvsp[(2) - (3)].propnodename));
-                ;}
+                }
     break;
 
   case 17:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 203 "dtc-parser.y"
     {
                         add_label(&(yyvsp[(2) - (2)].prop)->labels, (yyvsp[(1) - (2)].labelref));
                         (yyval.prop) = (yyvsp[(2) - (2)].prop);
-                ;}
+                }
     break;
 
   case 18:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 211 "dtc-parser.y"
     {
                         (yyval.data) = data_merge((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].data));
-                ;}
+                }
     break;
 
   case 19:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 215 "dtc-parser.y"
     {
                         (yyval.data) = data_merge((yyvsp[(1) - (3)].data), (yyvsp[(2) - (3)].array).data);
-                ;}
+                }
     break;
 
   case 20:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 219 "dtc-parser.y"
     {
                         (yyval.data) = data_merge((yyvsp[(1) - (4)].data), (yyvsp[(3) - (4)].data));
-                ;}
+                }
     break;
 
   case 21:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 223 "dtc-parser.y"
     {
                         (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), REF_PATH, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 22:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 227 "dtc-parser.y"
     {
                         FILE *f = srcfile_relative_open((yyvsp[(4) - (9)].data).val, NULL);
@@ -1716,12 +1746,12 @@ yyreduce:
 
                         (yyval.data) = data_merge((yyvsp[(1) - (9)].data), d);
                         fclose(f);
-                ;}
+                }
     break;
 
   case 23:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 244 "dtc-parser.y"
     {
                         FILE *f = srcfile_relative_open((yyvsp[(4) - (5)].data).val, NULL);
@@ -1731,48 +1761,48 @@ yyreduce:
 
                         (yyval.data) = data_merge((yyvsp[(1) - (5)].data), d);
                         fclose(f);
-                ;}
+                }
     break;
 
   case 24:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 254 "dtc-parser.y"
     {
                         (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 25:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 261 "dtc-parser.y"
     {
                         (yyval.data) = empty_data;
-                ;}
+                }
     break;
 
   case 26:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 265 "dtc-parser.y"
     {
                         (yyval.data) = (yyvsp[(1) - (2)].data);
-                ;}
+                }
     break;
 
   case 27:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 269 "dtc-parser.y"
     {
                         (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 28:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 276 "dtc-parser.y"
     {
                         (yyval.array).data = empty_data;
@@ -1787,22 +1817,22 @@ yyreduce:
                                             " are currently supported");
                                 (yyval.array).bits = 32;
                         }
-                ;}
+                }
     break;
 
   case 29:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 291 "dtc-parser.y"
     {
                         (yyval.array).data = empty_data;
                         (yyval.array).bits = 32;
-                ;}
+                }
     break;
 
   case 30:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 296 "dtc-parser.y"
     {
                         if ((yyvsp[(1) - (2)].array).bits < 64) {
@@ -1822,12 +1852,12 @@ yyreduce:
                         }
 
                         (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, (yyvsp[(2) - (2)].integer), (yyvsp[(1) - (2)].array).bits);
-                ;}
+                }
     break;
 
   case 31:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 316 "dtc-parser.y"
     {
                         uint64_t val = ~0ULL >> (64 - (yyvsp[(1) - (2)].array).bits);
@@ -1841,288 +1871,299 @@ yyreduce:
                                             "arrays with 32-bit elements.");
 
                         (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, val, (yyvsp[(1) - (2)].array).bits);
-                ;}
+                }
     break;
 
   case 32:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 330 "dtc-parser.y"
     {
                         (yyval.array).data = data_add_marker((yyvsp[(1) - (2)].array).data, LABEL, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 33:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 337 "dtc-parser.y"
     {
                         (yyval.integer) = eval_literal((yyvsp[(1) - (1)].literal), 0, 64);
-                ;}
+                }
     break;
 
   case 34:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 341 "dtc-parser.y"
     {
                         (yyval.integer) = eval_char_literal((yyvsp[(1) - (1)].literal));
-                ;}
+                }
     break;
 
   case 35:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 345 "dtc-parser.y"
     {
                         (yyval.integer) = (yyvsp[(2) - (3)].integer);
-                ;}
+                }
     break;
 
   case 38:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 356 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (5)].integer) ? (yyvsp[(3) - (5)].integer) : (yyvsp[(5) - (5)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (5)].integer) ? (yyvsp[(3) - (5)].integer) : (yyvsp[(5) - (5)].integer); }
     break;
 
   case 40:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 361 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) || (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) || (yyvsp[(3) - (3)].integer); }
     break;
 
   case 42:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 366 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) && (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) && (yyvsp[(3) - (3)].integer); }
     break;
 
   case 44:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 371 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) | (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) | (yyvsp[(3) - (3)].integer); }
     break;
 
   case 46:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 376 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) ^ (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) ^ (yyvsp[(3) - (3)].integer); }
     break;
 
   case 48:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 381 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) & (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) & (yyvsp[(3) - (3)].integer); }
     break;
 
   case 50:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 386 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) == (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) == (yyvsp[(3) - (3)].integer); }
     break;
 
   case 51:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 387 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) != (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) != (yyvsp[(3) - (3)].integer); }
     break;
 
   case 53:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 392 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) < (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) < (yyvsp[(3) - (3)].integer); }
     break;
 
   case 54:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 393 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) > (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) > (yyvsp[(3) - (3)].integer); }
     break;
 
   case 55:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 394 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) <= (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) <= (yyvsp[(3) - (3)].integer); }
     break;
 
   case 56:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 395 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) >= (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) >= (yyvsp[(3) - (3)].integer); }
     break;
 
   case 57:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 399 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) << (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) << (yyvsp[(3) - (3)].integer); }
     break;
 
   case 58:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 400 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) >> (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) >> (yyvsp[(3) - (3)].integer); }
     break;
 
   case 60:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 405 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) + (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) + (yyvsp[(3) - (3)].integer); }
     break;
 
   case 61:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 406 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) - (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) - (yyvsp[(3) - (3)].integer); }
     break;
 
   case 63:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 411 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) * (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) * (yyvsp[(3) - (3)].integer); }
     break;
 
   case 64:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 412 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) / (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) / (yyvsp[(3) - (3)].integer); }
     break;
 
   case 65:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 413 "dtc-parser.y"
-    { (yyval.integer) = (yyvsp[(1) - (3)].integer) % (yyvsp[(3) - (3)].integer); ;}
+    { (yyval.integer) = (yyvsp[(1) - (3)].integer) % (yyvsp[(3) - (3)].integer); }
     break;
 
   case 68:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 419 "dtc-parser.y"
-    { (yyval.integer) = -(yyvsp[(2) - (2)].integer); ;}
+    { (yyval.integer) = -(yyvsp[(2) - (2)].integer); }
     break;
 
   case 69:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 420 "dtc-parser.y"
-    { (yyval.integer) = ~(yyvsp[(2) - (2)].integer); ;}
+    { (yyval.integer) = ~(yyvsp[(2) - (2)].integer); }
     break;
 
   case 70:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 421 "dtc-parser.y"
-    { (yyval.integer) = !(yyvsp[(2) - (2)].integer); ;}
+    { (yyval.integer) = !(yyvsp[(2) - (2)].integer); }
     break;
 
   case 71:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 426 "dtc-parser.y"
     {
                         (yyval.data) = empty_data;
-                ;}
+                }
     break;
 
   case 72:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 430 "dtc-parser.y"
     {
                         (yyval.data) = data_append_byte((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].byte));
-                ;}
+                }
     break;
 
   case 73:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 434 "dtc-parser.y"
     {
                         (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref));
-                ;}
+                }
     break;
 
   case 74:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 441 "dtc-parser.y"
     {
                         (yyval.nodelist) = NULL;
-                ;}
+                }
     break;
 
   case 75:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 445 "dtc-parser.y"
     {
                         (yyval.nodelist) = chain_node((yyvsp[(1) - (2)].node), (yyvsp[(2) - (2)].nodelist));
-                ;}
+                }
     break;
 
   case 76:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 449 "dtc-parser.y"
     {
                         print_error("syntax error: properties must precede subnodes");
                         YYERROR;
-                ;}
+                }
     break;
 
   case 77:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 457 "dtc-parser.y"
     {
                         (yyval.node) = name_node((yyvsp[(2) - (2)].node), (yyvsp[(1) - (2)].propnodename));
-                ;}
+                }
     break;
 
   case 78:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 461 "dtc-parser.y"
     {
                         (yyval.node) = name_node(build_node_delete(), (yyvsp[(2) - (3)].propnodename));
-                ;}
+                }
     break;
 
   case 79:
 
-/* Line 1455 of yacc.c  */
+/* Line 1806 of yacc.c  */
 #line 465 "dtc-parser.y"
     {
                         add_label(&(yyvsp[(2) - (2)].node)->labels, (yyvsp[(1) - (2)].labelref));
                         (yyval.node) = (yyvsp[(2) - (2)].node);
-                ;}
+                }
     break;
 
 
 
-/* Line 1455 of yacc.c  */
-#line 2124 "dtc-parser.tab.c"
+/* Line 1806 of yacc.c  */
+#line 2154 "dtc-parser.tab.c"
       default: break;
     }
+  /* User semantic actions sometimes alter yychar, and that requires
+     that yytoken be updated with the new translation.  We take the
+     approach of translating immediately before every use of yytoken.
+     One alternative is translating here after every semantic action,
+     but that translation would be missed if the semantic action invokes
+     YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
+     if it invokes YYBACKUP.  In the case of YYABORT or YYACCEPT, an
+     incorrect destructor might then be invoked immediately.  In the
+     case of YYERROR or YYBACKUP, subsequent parser actions might lead
+     to an incorrect destructor call or verbose syntax error message
+     before the lookahead is translated.  */
   YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
 
   YYPOPSTACK (yylen);
@@ -2150,6 +2191,10 @@ yyreduce:
 | yyerrlab -- here on detecting error |
 `------------------------------------*/
 yyerrlab:
+  /* Make sure we have latest lookahead translation.  See comments at
+     user semantic actions for why this is necessary.  */
+  yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
+
   /* If not already recovering from an error, report this error.  */
   if (!yyerrstatus)
     {
@@ -2157,37 +2202,36 @@ yyerrlab:
 #if ! YYERROR_VERBOSE
       yyerror (YY_("syntax error"));
 #else
+# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
+                                        yyssp, yytoken)
       {
-        YYSIZE_T yysize = yysyntax_error (0, yystate, yychar);
-        if (yymsg_alloc < yysize && yymsg_alloc < YYSTACK_ALLOC_MAXIMUM)
-          {
-            YYSIZE_T yyalloc = 2 * yysize;
-            if (! (yysize <= yyalloc && yyalloc <= YYSTACK_ALLOC_MAXIMUM))
-              yyalloc = YYSTACK_ALLOC_MAXIMUM;
-            if (yymsg != yymsgbuf)
-              YYSTACK_FREE (yymsg);
-            yymsg = (char *) YYSTACK_ALLOC (yyalloc);
-            if (yymsg)
-              yymsg_alloc = yyalloc;
-            else
-              {
-                yymsg = yymsgbuf;
-                yymsg_alloc = sizeof yymsgbuf;
-              }
-          }
-
-        if (0 < yysize && yysize <= yymsg_alloc)
-          {
-            (void) yysyntax_error (yymsg, yystate, yychar);
-            yyerror (yymsg);
-          }
-        else
-          {
-            yyerror (YY_("syntax error"));
-            if (yysize != 0)
-              goto yyexhaustedlab;
-          }
+        char const *yymsgp = YY_("syntax error");
+        int yysyntax_error_status;
+        yysyntax_error_status = YYSYNTAX_ERROR;
+        if (yysyntax_error_status == 0)
+          yymsgp = yymsg;
+        else if (yysyntax_error_status == 1)
+          {
+            if (yymsg != yymsgbuf)
+              YYSTACK_FREE (yymsg);
+            yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
+            if (!yymsg)
+              {
+                yymsg = yymsgbuf;
+                yymsg_alloc = sizeof yymsgbuf;
+                yysyntax_error_status = 2;
+              }
+            else
+              {
+                yysyntax_error_status = YYSYNTAX_ERROR;
+                yymsgp = yymsg;
+              }
+          }
+        yyerror (yymsgp);
+        if (yysyntax_error_status == 2)
+          goto yyexhaustedlab;
       }
+# undef YYSYNTAX_ERROR
 #endif
     }
 
@@ -2246,7 +2290,7 @@ yyerrlab1:
   for (;;)
     {
       yyn = yypact[yystate];
-      if (yyn != YYPACT_NINF)
+      if (!yypact_value_is_default (yyn))
         {
           yyn += YYTERROR;
           if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
@@ -2305,8 +2349,13 @@ yyexhaustedlab:
 
 yyreturn:
   if (yychar != YYEMPTY)
-     yydestruct ("Cleanup: discarding lookahead",
-                 yytoken, &yylval);
+    {
+      /* Make sure we have latest lookahead translation.  See comments at
+         user semantic actions for why this is necessary.  */
+      yytoken = YYTRANSLATE (yychar);
+      yydestruct ("Cleanup: discarding lookahead",
+                  yytoken, &yylval);
+    }
   /* Do not reclaim the symbols of the rule which action triggered
      this YYABORT or YYACCEPT.  */
   YYPOPSTACK (yylen);
@@ -2331,7 +2380,7 @@ yyreturn:
 
 
 
-/* Line 1675 of yacc.c  */
+/* Line 2067 of yacc.c  */
 #line 471 "dtc-parser.y"
 
 
diff --git a/scripts/dtc/dtc-parser.tab.h_shipped b/scripts/dtc/dtc-parser.tab.h_shipped
index 9d2dce41211f..25d3b88c6132 100644
--- a/scripts/dtc/dtc-parser.tab.h_shipped
+++ b/scripts/dtc/dtc-parser.tab.h_shipped
@@ -1,10 +1,8 @@
+/* A Bison parser, made by GNU Bison 2.5.  */
 
-/* A Bison parser, made by GNU Bison 2.4.1.  */
-
-/* Skeleton interface for Bison's Yacc-like parsers in C
+/* Bison interface for Yacc-like parsers in C
    
-      Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
-   Free Software Foundation, Inc.
+      Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc.
    
    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -70,7 +68,7 @@
 typedef union YYSTYPE
 {
 
-/* Line 1676 of yacc.c  */
+/* Line 2068 of yacc.c  */
 #line 40 "dtc-parser.y"
 
         char *propnodename;
@@ -94,8 +92,8 @@ typedef union YYSTYPE
 
 
 
-/* Line 1676 of yacc.c  */
-#line 99 "dtc-parser.tab.h"
+/* Line 2068 of yacc.c  */
+#line 97 "dtc-parser.tab.h"
 } YYSTYPE;
 # define YYSTYPE_IS_TRIVIAL 1
 # define yystype YYSTYPE /* obsolescent; will be withdrawn */
diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index ccfa383f1fda..f92818155958 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -1649,6 +1649,7 @@ static int snd_pcm_link(struct snd_pcm_substream *substream, int fd)
         }
         if (!snd_pcm_stream_linked(substream)) {
                 substream->group = group;
+                group = NULL;
                 spin_lock_init(&substream->group->lock);
                 INIT_LIST_HEAD(&substream->group->substreams);
                 list_add_tail(&substream->link_list, &substream->group->substreams);
@@ -1663,8 +1664,7 @@ static int snd_pcm_link(struct snd_pcm_substream *substream, int fd)
  _nolock:
         snd_card_unref(substream1->pcm->card);
         fput_light(file, fput_needed);
-        if (res < 0)
-                kfree(group);
+        kfree(group);
         return res;
 }
 
diff --git a/sound/soc/codecs/cs42l52.c b/sound/soc/codecs/cs42l52.c
index 030f53c96ec0..987f728718c5 100644
--- a/sound/soc/codecs/cs42l52.c
+++ b/sound/soc/codecs/cs42l52.c
@@ -193,6 +193,8 @@ static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
 
 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
 
+static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
+
 static const unsigned int limiter_tlv[] = {
         TLV_DB_RANGE_HEAD(2),
         0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
@@ -260,7 +262,7 @@ static const char * const hp_gain_num_text[] = {
 };
 
 static const struct soc_enum hp_gain_enum =
-        SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 4,
+        SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 5,
                 ARRAY_SIZE(hp_gain_num_text), hp_gain_num_text);
 
 static const char * const beep_pitch_text[] = {
@@ -441,7 +443,7 @@ static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
 
         SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
                             CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
-                                0, 0x7f, 0x19, hl_tlv),
+                                0, 0x7f, 0x19, mix_tlv),
         SOC_DOUBLE_R("PCM Mixer Switch",
                      CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
 
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 65d09d60b7c6..1514bf845e4b 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -187,14 +187,14 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
 
                         break;
                 }
-
-                if (found)
-                        snd_soc_dapm_sync(widget->dapm);
         }
 
-        ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
-
         mutex_unlock(&widget->codec->mutex);
+
+        if (found)
+                snd_soc_dapm_sync(widget->dapm);
+
+        ret = snd_soc_update_bits_locked(widget->codec, reg, val_mask, val);
         return ret;
 }
 
diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c
index e895d3939eef..100fdadda56a 100644
--- a/sound/soc/codecs/wm5102.c
+++ b/sound/soc/codecs/wm5102.c
@@ -1120,7 +1120,8 @@ SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0,
 ARIZONA_DSP_WIDGETS(DSP1, "DSP1"),
 
 SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
-                       ARIZONA_AEC_LOOPBACK_ENA, 0, &wm5102_aec_loopback_mux),
+                       ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0,
+                       &wm5102_aec_loopback_mux),
 
 SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM,
                    ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev,
diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c
index ba38f0679662..88ad7db52dde 100644
--- a/sound/soc/codecs/wm5110.c
+++ b/sound/soc/codecs/wm5110.c
@@ -503,7 +503,8 @@ SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0,
                  NULL, 0),
 
 SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
-                       ARIZONA_AEC_LOOPBACK_ENA, 0, &wm5110_aec_loopback_mux),
+                       ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0,
+                       &wm5110_aec_loopback_mux),
 
 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
                      ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0),
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index dfd997aaadfc..29e95f93d482 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -3836,12 +3836,13 @@ static irqreturn_t wm8958_mic_irq(int irq, void *data)
                                 ret);
                 } else if (!(ret & WM1811_JACKDET_LVL)) {
                         dev_dbg(codec->dev, "Ignoring removed jack\n");
-                        return IRQ_HANDLED;
+                        goto out;
                 }
         } else if (!(reg & WM8958_MICD_STS)) {
                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
                                     wm8994->btn_mask);
+                wm8994->mic_detecting = true;
                 goto out;
         }
 
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index a80c883bb8be..c7051c457b75 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -55,7 +55,8 @@ static int dapm_up_seq[] = {
         [snd_soc_dapm_clock_supply] = 1,
         [snd_soc_dapm_micbias] = 2,
         [snd_soc_dapm_dai_link] = 2,
-        [snd_soc_dapm_dai] = 3,
+        [snd_soc_dapm_dai_in] = 3,
+        [snd_soc_dapm_dai_out] = 3,
         [snd_soc_dapm_aif_in] = 3,
         [snd_soc_dapm_aif_out] = 3,
         [snd_soc_dapm_mic] = 4,
@@ -92,7 +93,8 @@ static int dapm_down_seq[] = {
         [snd_soc_dapm_value_mux] = 9,
         [snd_soc_dapm_aif_in] = 10,
         [snd_soc_dapm_aif_out] = 10,
-        [snd_soc_dapm_dai] = 10,
+        [snd_soc_dapm_dai_in] = 10,
+        [snd_soc_dapm_dai_out] = 10,
         [snd_soc_dapm_dai_link] = 11,
         [snd_soc_dapm_clock_supply] = 12,
         [snd_soc_dapm_regulator_supply] = 12,
@@ -419,7 +421,8 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w,
         case snd_soc_dapm_clock_supply:
         case snd_soc_dapm_aif_in:
         case snd_soc_dapm_aif_out:
-        case snd_soc_dapm_dai:
+        case snd_soc_dapm_dai_in:
+        case snd_soc_dapm_dai_out:
         case snd_soc_dapm_hp:
         case snd_soc_dapm_mic:
         case snd_soc_dapm_spk:
@@ -820,7 +823,7 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget,
         switch (widget->id) {
         case snd_soc_dapm_adc:
         case snd_soc_dapm_aif_out:
-        case snd_soc_dapm_dai:
+        case snd_soc_dapm_dai_out:
                 if (widget->active) {
                         widget->outputs = snd_soc_dapm_suspend_check(widget);
                         return widget->outputs;
@@ -916,7 +919,7 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget,
         switch (widget->id) {
         case snd_soc_dapm_dac:
         case snd_soc_dapm_aif_in:
-        case snd_soc_dapm_dai:
+        case snd_soc_dapm_dai_in:
                 if (widget->active) {
                         widget->inputs = snd_soc_dapm_suspend_check(widget);
                         return widget->inputs;
@@ -1135,16 +1138,6 @@ static int dapm_generic_check_power(struct snd_soc_dapm_widget *w)
         return out != 0 && in != 0;
 }
 
-static int dapm_dai_check_power(struct snd_soc_dapm_widget *w)
-{
-        DAPM_UPDATE_STAT(w, power_checks);
-
-        if (w->active)
-                return w->active;
-
-        return dapm_generic_check_power(w);
-}
-
 /* Check to see if an ADC has power */
 static int dapm_adc_check_power(struct snd_soc_dapm_widget *w)
 {
@@ -2318,7 +2311,8 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm,
         case snd_soc_dapm_clock_supply:
         case snd_soc_dapm_aif_in:
         case snd_soc_dapm_aif_out:
-        case snd_soc_dapm_dai:
+        case snd_soc_dapm_dai_in:
+        case snd_soc_dapm_dai_out:
         case snd_soc_dapm_dai_link:
                 list_add(&path->list, &dapm->card->paths);
                 list_add(&path->list_sink, &wsink->sources);
@@ -3129,10 +3123,12 @@ snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm,
                 break;
         case snd_soc_dapm_adc:
         case snd_soc_dapm_aif_out:
+        case snd_soc_dapm_dai_out:
                 w->power_check = dapm_adc_check_power;
                 break;
         case snd_soc_dapm_dac:
         case snd_soc_dapm_aif_in:
+        case snd_soc_dapm_dai_in:
                 w->power_check = dapm_dac_check_power;
                 break;
         case snd_soc_dapm_pga:
@@ -3152,9 +3148,6 @@ snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm,
         case snd_soc_dapm_clock_supply:
                 w->power_check = dapm_supply_check_power;
                 break;
-        case snd_soc_dapm_dai:
-                w->power_check = dapm_dai_check_power;
-                break;
         default:
                 w->power_check = dapm_always_on_check_power;
                 break;
@@ -3375,7 +3368,7 @@ int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm,
         template.reg = SND_SOC_NOPM;
 
         if (dai->driver->playback.stream_name) {
-                template.id = snd_soc_dapm_dai;
+                template.id = snd_soc_dapm_dai_in;
                 template.name = dai->driver->playback.stream_name;
                 template.sname = dai->driver->playback.stream_name;
 
@@ -3393,7 +3386,7 @@ int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm,
         }
 
         if (dai->driver->capture.stream_name) {
-                template.id = snd_soc_dapm_dai;
+                template.id = snd_soc_dapm_dai_out;
                 template.name = dai->driver->capture.stream_name;
                 template.sname = dai->driver->capture.stream_name;
 
@@ -3423,8 +3416,13 @@ int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card)
 
         /* For each DAI widget... */
         list_for_each_entry(dai_w, &card->widgets, list) {
-                if (dai_w->id != snd_soc_dapm_dai)
+                switch (dai_w->id) {
+                case snd_soc_dapm_dai_in:
+                case snd_soc_dapm_dai_out:
+                        break;
+                default:
                         continue;
+                }
 
                 dai = dai_w->priv;
 
@@ -3433,8 +3431,13 @@ int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card)
                         if (w->dapm != dai_w->dapm)
                                 continue;
 
-                        if (w->id == snd_soc_dapm_dai)
+                        switch (w->id) {
+                        case snd_soc_dapm_dai_in:
+                        case snd_soc_dapm_dai_out:
                                 continue;
+                        default:
+                                break;
+                        }
 
                         if (!w->sname)
                                 continue;
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index 73bb8eefa491..ccb6be4d658d 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -928,8 +928,13 @@ static int dpcm_add_paths(struct snd_soc_pcm_runtime *fe, int stream,
         /* Create any new FE <--> BE connections */
         for (i = 0; i < list->num_widgets; i++) {
 
-                if (list->widgets[i]->id != snd_soc_dapm_dai)
+                switch (list->widgets[i]->id) {
+                case snd_soc_dapm_dai_in:
+                case snd_soc_dapm_dai_out:
+                        break;
+                default:
                         continue;
+                }
 
                 /* is there a valid BE rtd for this widget */
                 be = dpcm_get_be(card, list->widgets[i], stream);
@@ -2011,9 +2016,11 @@ int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num)
                 if (cpu_dai->driver->capture.channels_min)
                         capture = 1;
         } else {
-                if (codec_dai->driver->playback.channels_min)
+                if (codec_dai->driver->playback.channels_min &&
+                    cpu_dai->driver->playback.channels_min)
                         playback = 1;
-                if (codec_dai->driver->capture.channels_min)
+                if (codec_dai->driver->capture.channels_min &&
+                    cpu_dai->driver->capture.channels_min)
                         capture = 1;
         }
 
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 9e9d34871195..fe702076ca46 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -2191,7 +2191,7 @@ int initialize_counters(int cpu_id)
 
 void allocate_output_buffer()
 {
-        output_buffer = calloc(1, (1 + topo.num_cpus) * 128);
+        output_buffer = calloc(1, (1 + topo.num_cpus) * 256);
         outp = output_buffer;
         if (outp == NULL) {
                 perror("calloc");