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authorArnd Bergmann <arnd@arndb.de>2013-06-21 09:00:24 -0400
committerArnd Bergmann <arnd@arndb.de>2013-06-21 09:00:24 -0400
commite8f2ca97151892ab723dd8317313063cef79839d (patch)
tree147047c432e3af4cad25b4672b493b93edc32844
parent704b1005d1e23fa35a32e591a32183c309917bbd (diff)
parenteff4e7c7f32a4e4be60b19b209ffab5cb430b385 (diff)
Merge tag 'soc-exynos5420-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/late
From Kukjin Kim: based on tags/common-clk-audio - add support for exynos5420 SoC * tag 'soc-exynos5420-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: extend soft-reset support for EXYNOS5420 ARM: EXYNOS: add secondary CPU boot base location for EXYNOS5420 clocksource: exynos_mct: use (request/free)_irq calls for local timer registration ARM: dts: Add initial device tree support for EXYNOS5420 clk: exynos5420: register clocks using common clock framework ARM: EXYNOS: use four additional chipid bits to identify EXYNOS family serial: samsung: select EXYNOS specific driver data if ARCH_EXYNOS is defined ARM: EXYNOS: Add support for EXYNOS5420 SoC ARM: dts: list the CPU nodes for EXYNOS5250 ARM: dts: fork out common EXYNOS5 nodes Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/clk-exynos-audss.txt64
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5420-clock.txt201
-rw-r--r--Documentation/devicetree/bindings/gpu/samsung-g2d.txt5
-rw-r--r--Documentation/devicetree/bindings/media/s5p-mfc.txt5
-rw-r--r--Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt44
-rw-r--r--Documentation/devicetree/bindings/sound/samsung-i2s.txt46
-rw-r--r--Documentation/devicetree/bindings/usb/exynos-usb.txt34
-rw-r--r--Documentation/devicetree/bindings/video/exynos_dp.txt6
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts171
-rw-r--r--arch/arm/boot/dts/exynos4210-pinctrl.dtsi89
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi9
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx.dts199
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts68
-rw-r--r--arch/arm/boot/dts/exynos4412-smdk4412.dts87
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4x12-pinctrl.dtsi56
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi14
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi111
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts33
-rw-r--r--arch/arm/boot/dts/exynos5250-pinctrl.dtsi7
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts42
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts8
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi126
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts33
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi103
-rw-r--r--arch/arm/boot/dts/exynos5440-sd5v1.dts4
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts43
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi68
-rw-r--r--arch/arm/boot/dts/s3c2416-pinctrl.dtsi173
-rw-r--r--arch/arm/boot/dts/s3c2416-smdk2416.dts72
-rw-r--r--arch/arm/boot/dts/s3c2416.dtsi79
-rw-r--r--arch/arm/boot/dts/s3c24xx.dtsi92
-rw-r--r--arch/arm/mach-exynos/Kconfig10
-rw-r--r--arch/arm/mach-exynos/common.c18
-rw-r--r--arch/arm/mach-exynos/include/mach/uncompress.h7
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c1
-rw-r--r--arch/arm/mach-exynos/platsmp.c12
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig12
-rw-r--r--arch/arm/mach-s3c24xx/Makefile1
-rw-r--r--arch/arm/mach-s3c24xx/mach-s3c2416-dt.c91
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h8
-rw-r--r--drivers/clk/samsung/Makefile2
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c133
-rw-r--r--drivers/clk/samsung/clk-exynos4.c9
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c5
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c762
-rw-r--r--drivers/clocksource/exynos_mct.c35
-rw-r--r--drivers/tty/serial/samsung.c4
-rw-r--r--include/dt-bindings/clk/exynos-audss-clk.h25
56 files changed, 2986 insertions, 260 deletions
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
new file mode 100644
index 000000000000..a1201802f90d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -0,0 +1,64 @@
1* Samsung Audio Subsystem Clock Controller
2
3The Samsung Audio Subsystem clock controller generates and supplies clocks
4to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
5binding described here is applicable to all SoC's in Exynos family.
6
7Required Properties:
8
9- compatible: should be one of the following:
10 - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
11 - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
12
13- reg: physical base address and length of the controller's register set.
14
15- #clock-cells: should be 1.
16
17The following is the list of clocks generated by the controller. Each clock is
18assigned an identifier and client nodes use this identifier to specify the
19clock which they consume. Some of the clocks are available only on a particular
20Exynos4 SoC and this is specified where applicable.
21
22Provided clocks:
23
24Clock ID SoC (if specific)
25-----------------------------------------------
26
27mout_audss 0
28mout_i2s 1
29dout_srp 2
30dout_aud_bus 3
31dout_i2s 4
32srp_clk 5
33i2s_bus 6
34sclk_i2s 7
35pcm_bus 8
36sclk_pcm 9
37
38Example 1: An example of a clock controller node is listed below.
39
40clock_audss: audss-clock-controller@3810000 {
41 compatible = "samsung,exynos5250-audss-clock";
42 reg = <0x03810000 0x0C>;
43 #clock-cells = <1>;
44};
45
46Example 2: I2S controller node that consumes the clock generated by the clock
47 controller. Refer to the standard clock bindings for information
48 about 'clocks' and 'clock-names' property.
49
50i2s0: i2s@03830000 {
51 compatible = "samsung,i2s-v5";
52 reg = <0x03830000 0x100>;
53 dmas = <&pdma0 10
54 &pdma0 9
55 &pdma0 8>;
56 dma-names = "tx", "rx", "tx-sec";
57 clocks = <&clock_audss EXYNOS_I2S_BUS>,
58 <&clock_audss EXYNOS_I2S_BUS>,
59 <&clock_audss EXYNOS_SCLK_I2S>,
60 <&clock_audss EXYNOS_MOUT_AUDSS>,
61 <&clock_audss EXYNOS_MOUT_I2S>;
62 clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
63 "mout_audss", "mout_i2s";
64};
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index ea5e26f16aec..14d5c2af26f4 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable.
102 sclk_spi0_isp 174 Exynos4x12 102 sclk_spi0_isp 174 Exynos4x12
103 sclk_spi1_isp 175 Exynos4x12 103 sclk_spi1_isp 175 Exynos4x12
104 sclk_uart_isp 176 Exynos4x12 104 sclk_uart_isp 176 Exynos4x12
105 sclk_fimg2d 177
105 106
106 [Peripheral Clock Gates] 107 [Peripheral Clock Gates]
107 108
@@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable.
129 smmu_mfcl 274 130 smmu_mfcl 274
130 smmu_mfcr 275 131 smmu_mfcr 275
131 g3d 276 132 g3d 276
132 g2d 277 Exynos4210 133 g2d 277
133 rotator 278 Exynos4210 134 rotator 278 Exynos4210
134 mdma 279 Exynos4210 135 mdma 279 Exynos4210
135 smmu_g2d 280 Exynos4210 136 smmu_g2d 280 Exynos4210
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
new file mode 100644
index 000000000000..9bcc4b1bff51
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -0,0 +1,201 @@
1* Samsung Exynos5420 Clock Controller
2
3The Exynos5420 clock controller generates and supplies clock to various
4controllers within the Exynos5420 SoC.
5
6Required Properties:
7
8- comptible: should be one of the following.
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10
11- reg: physical base address of the controller and length of memory mapped
12 region.
13
14- #clock-cells: should be 1.
15
16The following is the list of clocks generated by the controller. Each clock is
17assigned an identifier and client nodes use this identifier to specify the
18clock which they consume.
19
20
21 [Core Clocks]
22
23 Clock ID
24 ----------------------------
25
26 fin_pll 1
27
28 [Clock Gate for Special Clocks]
29
30 Clock ID
31 ----------------------------
32 sclk_uart0 128
33 sclk_uart1 129
34 sclk_uart2 130
35 sclk_uart3 131
36 sclk_mmc0 132
37 sclk_mmc1 133
38 sclk_mmc2 134
39 sclk_spi0 135
40 sclk_spi1 136
41 sclk_spi2 137
42 sclk_i2s1 138
43 sclk_i2s2 139
44 sclk_pcm1 140
45 sclk_pcm2 141
46 sclk_spdif 142
47 sclk_hdmi 143
48 sclk_pixel 144
49 sclk_dp1 145
50 sclk_mipi1 146
51 sclk_fimd1 147
52 sclk_maudio0 148
53 sclk_maupcm0 149
54 sclk_usbd300 150
55 sclk_usbd301 151
56 sclk_usbphy300 152
57 sclk_usbphy301 153
58 sclk_unipro 154
59 sclk_pwm 155
60 sclk_gscl_wa 156
61 sclk_gscl_wb 157
62
63 [Peripheral Clock Gates]
64
65 Clock ID
66 ----------------------------
67
68 aclk66_peric 256
69 uart0 257
70 uart1 258
71 uart2 259
72 uart3 260
73 i2c0 261
74 i2c1 262
75 i2c2 263
76 i2c3 264
77 i2c4 265
78 i2c5 266
79 i2c6 267
80 i2c7 268
81 i2c_hdmi 269
82 tsadc 270
83 spi0 271
84 spi1 272
85 spi2 273
86 keyif 274
87 i2s1 275
88 i2s2 276
89 pcm1 277
90 pcm2 278
91 pwm 279
92 spdif 280
93 i2c8 281
94 i2c9 282
95 i2c10 283
96 aclk66_psgen 300
97 chipid 301
98 sysreg 302
99 tzpc0 303
100 tzpc1 304
101 tzpc2 305
102 tzpc3 306
103 tzpc4 307
104 tzpc5 308
105 tzpc6 309
106 tzpc7 310
107 tzpc8 311
108 tzpc9 312
109 hdmi_cec 313
110 seckey 314
111 mct 315
112 wdt 316
113 rtc 317
114 tmu 318
115 tmu_gpu 319
116 pclk66_gpio 330
117 aclk200_fsys2 350
118 mmc0 351
119 mmc1 352
120 mmc2 353
121 sromc 354
122 ufs 355
123 aclk200_fsys 360
124 tsi 361
125 pdma0 362
126 pdma1 363
127 rtic 364
128 usbh20 365
129 usbd300 366
130 usbd301 377
131 aclk400_mscl 380
132 mscl0 381
133 mscl1 382
134 mscl2 383
135 smmu_mscl0 384
136 smmu_mscl1 385
137 smmu_mscl2 386
138 aclk333 400
139 mfc 401
140 smmu_mfcl 402
141 smmu_mfcr 403
142 aclk200_disp1 410
143 dsim1 411
144 dp1 412
145 hdmi 413
146 aclk300_disp1 420
147 fimd1 421
148 smmu_fimd1 422
149 aclk166 430
150 mixer 431
151 aclk266 440
152 rotator 441
153 mdma1 442
154 smmu_rotator 443
155 smmu_mdma1 444
156 aclk300_jpeg 450
157 jpeg 451
158 jpeg2 452
159 smmu_jpeg 453
160 aclk300_gscl 460
161 smmu_gscl0 461
162 smmu_gscl1 462
163 gscl_wa 463
164 gscl_wb 464
165 gscl0 465
166 gscl1 466
167 clk_3aa 467
168 aclk266_g2d 470
169 sss 471
170 slim_sss 472
171 mdma0 473
172 aclk333_g2d 480
173 g2d 481
174 aclk333_432_gscl 490
175 smmu_3aa 491
176 smmu_fimcl0 492
177 smmu_fimcl1 493
178 smmu_fimcl3 494
179 fimc_lite3 495
180 aclk_g3d 500
181 g3d 501
182
183Example 1: An example of a clock controller node is listed below.
184
185 clock: clock-controller@0x10010000 {
186 compatible = "samsung,exynos5420-clock";
187 reg = <0x10010000 0x30000>;
188 #clock-cells = <1>;
189 };
190
191Example 2: UART controller node that consumes the clock generated by the clock
192 controller. Refer to the standard clock bindings for information
193 about 'clocks' and 'clock-names' property.
194
195 serial@13820000 {
196 compatible = "samsung,exynos4210-uart";
197 reg = <0x13820000 0x100>;
198 interrupts = <0 54 0>;
199 clocks = <&clock 259>, <&clock 130>;
200 clock-names = "uart", "clk_uart_baud0";
201 };
diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
index 2b14a940eb75..3f454ffc654a 100644
--- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
+++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
@@ -10,11 +10,16 @@ Required properties:
10 mapped region. 10 mapped region.
11 11
12 - interrupts : G2D interrupt number to the CPU. 12 - interrupts : G2D interrupt number to the CPU.
13 - clocks : from common clock binding: handle to G2D clocks.
14 - clock-names : from common clock binding: must contain "sclk_fimg2d" and
15 "fimg2d", corresponding to entries in the clocks property.
13 16
14Example: 17Example:
15 g2d@12800000 { 18 g2d@12800000 {
16 compatible = "samsung,s5pv210-g2d"; 19 compatible = "samsung,s5pv210-g2d";
17 reg = <0x12800000 0x1000>; 20 reg = <0x12800000 0x1000>;
18 interrupts = <0 89 0>; 21 interrupts = <0 89 0>;
22 clocks = <&clock 177>, <&clock 277>;
23 clock-names = "sclk_fimg2d", "fimg2d";
19 status = "disabled"; 24 status = "disabled";
20 }; 25 };
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index bf0182d8da25..df37b0230c75 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -15,6 +15,9 @@ Required properties:
15 mapped region. 15 mapped region.
16 16
17 - interrupts : MFC interrupt number to the CPU. 17 - interrupts : MFC interrupt number to the CPU.
18 - clocks : from common clock binding: handle to mfc clocks.
19 - clock-names : from common clock binding: must contain "sclk_mfc" and "mfc",
20 corresponding to entries in the clocks property.
18 21
19 - samsung,mfc-r : Base address of the first memory bank used by MFC 22 - samsung,mfc-r : Base address of the first memory bank used by MFC
20 for DMA contiguous memory allocation and its size. 23 for DMA contiguous memory allocation and its size.
@@ -34,6 +37,8 @@ mfc: codec@13400000 {
34 reg = <0x13400000 0x10000>; 37 reg = <0x13400000 0x10000>;
35 interrupts = <0 94 0>; 38 interrupts = <0 94 0>;
36 samsung,power-domain = <&pd_mfc>; 39 samsung,power-domain = <&pd_mfc>;
40 clocks = <&clock 170>, <&clock 273>;
41 clock-names = "sclk_mfc", "mfc";
37}; 42};
38 43
39Board specific DT entry: 44Board specific DT entry:
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index c70fca146e91..e15cfc4bb39e 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -21,8 +21,18 @@ Required Properties:
21 21
22 - gpio-controller: identifies the node as a gpio controller and pin bank. 22 - gpio-controller: identifies the node as a gpio controller and pin bank.
23 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 23 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
24 binding is used, the amount of cells must be specified as 2. See generic 24 binding is used, the amount of cells must be specified as 2. See the below
25 GPIO binding documentation for description of particular cells. 25 mentioned gpio binding representation for description of particular cells.
26
27 Eg: <&gpx2 6 0>
28 <[phandle of the gpio controller node]
29 [pin number within the gpio controller]
30 [flags]>
31
32 Values for gpio specifier:
33 - Pin number: is a value between 0 to 7.
34 - Flags: 0 - Active High
35 1 - Active Low
26 36
27- Pin mux/config groups as child nodes: The pin mux (selecting pin function 37- Pin mux/config groups as child nodes: The pin mux (selecting pin function
28 mode) and pin config (pull up/down, driver strength) settings are represented 38 mode) and pin config (pull up/down, driver strength) settings are represented
@@ -266,3 +276,33 @@ Example 4: Set up the default pin state for uart controller.
266 276
267 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 277 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
268 } 278 }
279
280Example 5: A display port client node that supports 'default' pinctrl state
281 and gpio binding.
282
283 display-port-controller {
284 /* ... */
285
286 samsung,hpd-gpio = <&gpx2 6 0>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&dp_hpd>;
289 };
290
291Example 6: Request the gpio for display port controller
292
293 static int exynos_dp_probe(struct platform_device *pdev)
294 {
295 int hpd_gpio, ret;
296 struct device *dev = &pdev->dev;
297 struct device_node *dp_node = dev->of_node;
298
299 /* ... */
300
301 hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0);
302
303 /* ... */
304
305 ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN,
306 "hpd_gpio");
307 /* ... */
308 }
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 3070046da2e5..025e66b85a43 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -8,6 +8,16 @@ Required SoC Specific Properties:
8- dmas: list of DMA controller phandle and DMA request line ordered pairs. 8- dmas: list of DMA controller phandle and DMA request line ordered pairs.
9- dma-names: identifier string for each DMA request line in the dmas property. 9- dma-names: identifier string for each DMA request line in the dmas property.
10 These strings correspond 1:1 with the ordered pairs in dmas. 10 These strings correspond 1:1 with the ordered pairs in dmas.
11- clocks: Handle to iis clock and RCLK source clk.
12- clock-names:
13 i2s0 uses some base clks from CMU and some are from audio subsystem internal
14 clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
15 "i2s_opclk1" as shown in the example below.
16 i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
17 be "iis" and "i2s_opclk0".
18 "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
19 clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
20 doesn't have any such mux.
11 21
12Optional SoC Specific Properties: 22Optional SoC Specific Properties:
13 23
@@ -20,44 +30,26 @@ Optional SoC Specific Properties:
20 then this flag is enabled. 30 then this flag is enabled.
21- samsung,idma-addr: Internal DMA register base address of the audio 31- samsung,idma-addr: Internal DMA register base address of the audio
22 sub system(used in secondary sound source). 32 sub system(used in secondary sound source).
23 33- pinctrl-0: Should specify pin control groups used for this controller.
24Required Board Specific Properties: 34- pinctrl-names: Should contain only one value - "default".
25
26- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
27 interface lines. The format of the gpio specifier depends on the gpio
28 controller.
29 The syntax of samsung gpio specifier is
30 <[phandle of the gpio controller node]
31 [pin number within the gpio controller]
32 [mux function]
33 [flags and pull up/down]
34 [drive strength]>
35 35
36Example: 36Example:
37 37
38- SoC Specific Portion: 38i2s0: i2s@03830000 {
39
40i2s@03830000 {
41 compatible = "samsung,i2s-v5"; 39 compatible = "samsung,i2s-v5";
42 reg = <0x03830000 0x100>; 40 reg = <0x03830000 0x100>;
43 dmas = <&pdma0 10 41 dmas = <&pdma0 10
44 &pdma0 9 42 &pdma0 9
45 &pdma0 8>; 43 &pdma0 8>;
46 dma-names = "tx", "rx", "tx-sec"; 44 dma-names = "tx", "rx", "tx-sec";
45 clocks = <&clock_audss EXYNOS_I2S_BUS>,
46 <&clock_audss EXYNOS_I2S_BUS>,
47 <&clock_audss EXYNOS_SCLK_I2S>;
48 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
47 samsung,supports-6ch; 49 samsung,supports-6ch;
48 samsung,supports-rstclr; 50 samsung,supports-rstclr;
49 samsung,supports-secdai; 51 samsung,supports-secdai;
50 samsung,idma-addr = <0x03000000>; 52 samsung,idma-addr = <0x03000000>;
51}; 53 pinctrl-names = "default";
52 54 pinctrl-0 = <&i2s0_bus>;
53- Board Specific Portion:
54
55i2s@03830000 {
56 gpios = <&gpz 0 2 0 0>, /* I2S_0_SCLK */
57 <&gpz 1 2 0 0>, /* I2S_0_CDCLK */
58 <&gpz 2 2 0 0>, /* I2S_0_LRCK */
59 <&gpz 3 2 0 0>, /* I2S_0_SDI */
60 <&gpz 4 2 0 0>, /* I2S_0_SDO[1] */
61 <&gpz 5 2 0 0>, /* I2S_0_SDO[2] */
62 <&gpz 6 2 0 0>; /* I2S_0_SDO[3] */
63}; 55};
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index b3abde736017..d967ba16de60 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -48,3 +48,37 @@ Example:
48 clocks = <&clock 285>; 48 clocks = <&clock 285>;
49 clock-names = "usbhost"; 49 clock-names = "usbhost";
50 }; 50 };
51
52DWC3
53Required properties:
54 - compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3
55 controller.
56 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
57 with 'reg' property.
58 - ranges: allows valid 1:1 translation between child's address space and
59 parent's address space
60 - clocks: Clock IDs array as required by the controller.
61 - clock-names: names of clocks correseponding to IDs in the clock property
62
63Sub-nodes:
64The dwc3 core should be added as subnode to Exynos dwc3 glue.
65- dwc3 :
66 The binding details of dwc3 can be found in:
67 Documentation/devicetree/bindings/usb/dwc3.txt
68
69Example:
70 usb@12000000 {
71 compatible = "samsung,exynos5250-dwusb3";
72 clocks = <&clock 286>;
73 clock-names = "usbdrd30";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges;
77
78 dwc3 {
79 compatible = "synopsys,dwc3";
80 reg = <0x12000000 0x10000>;
81 interrupts = <0 72 0>;
82 usb-phy = <&usb2_phy &usb3_phy>;
83 };
84 };
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index c60da67a5d76..84f10c16cb38 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -21,6 +21,10 @@ Required properties for dp-controller:
21 of memory mapped region. 21 of memory mapped region.
22 -interrupts: 22 -interrupts:
23 interrupt combiner values. 23 interrupt combiner values.
24 -clocks:
25 from common clock binding: handle to dp clock.
26 -clock-names:
27 from common clock binding: Shall be "dp".
24 -interrupt-parent: 28 -interrupt-parent:
25 phandle to Interrupt combiner node. 29 phandle to Interrupt combiner node.
26 -samsung,color-space: 30 -samsung,color-space:
@@ -61,6 +65,8 @@ SOC specific portion:
61 reg = <0x145b0000 0x10000>; 65 reg = <0x145b0000 0x10000>;
62 interrupts = <10 3>; 66 interrupts = <10 3>;
63 interrupt-parent = <&combiner>; 67 interrupt-parent = <&combiner>;
68 clocks = <&clock 342>;
69 clock-names = "dp";
64 70
65 dptx-phy { 71 dptx-phy {
66 reg = <0x10040720>; 72 reg = <0x10040720>;
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f0895c581a89..13575103594d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
57 exynos5440-sd5v1.dtb \ 57 exynos5440-sd5v1.dtb \
58 exynos5250-smdk5250.dtb \ 58 exynos5250-smdk5250.dtb \
59 exynos5250-snow.dtb \ 59 exynos5250-snow.dtb \
60 exynos5420-smdk5420.dtb \
60 exynos5440-ssdk5440.dtb 61 exynos5440-ssdk5440.dtb
61dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 62dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
62 ecx-2000.dtb 63 ecx-2000.dtb
@@ -159,6 +160,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
159 hrefprev60.dtb \ 160 hrefprev60.dtb \
160 hrefv60plus.dtb \ 161 hrefv60plus.dtb \
161 ccu9540.dtb 162 ccu9540.dtb
163dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
162dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 164dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
163 r8a7740-armadillo800eva.dtb \ 165 r8a7740-armadillo800eva.dtb \
164 r8a7778-bockw.dtb \ 166 r8a7778-bockw.dtb \
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 359694c78918..3f94fe8e3706 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
19 * published by the Free Software Foundation. 19 * published by the Free Software Foundation.
20 */ 20 */
21 21
22/include/ "skeleton.dtsi" 22#include "skeleton.dtsi"
23 23
24/ { 24/ {
25 interrupt-parent = <&gic>; 25 interrupt-parent = <&gic>;
@@ -160,6 +160,8 @@
160 reg = <0x13400000 0x10000>; 160 reg = <0x13400000 0x10000>;
161 interrupts = <0 94 0>; 161 interrupts = <0 94 0>;
162 samsung,power-domain = <&pd_mfc>; 162 samsung,power-domain = <&pd_mfc>;
163 clocks = <&clock 170>, <&clock 273>;
164 clock-names = "sclk_mfc", "mfc";
163 status = "disabled"; 165 status = "disabled";
164 }; 166 };
165 167
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 524b90846df5..382d8c7e2906 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
15*/ 15*/
16 16
17/dts-v1/; 17/dts-v1/;
18/include/ "exynos4210.dtsi" 18#include "exynos4210.dtsi"
19 19
20/ { 20/ {
21 model = "Insignal Origen evaluation board based on Exynos4210"; 21 model = "Insignal Origen evaluation board based on Exynos4210";
@@ -41,6 +41,10 @@
41 enable-active-high; 41 enable-active-high;
42 }; 42 };
43 43
44 tmu@100C0000 {
45 status = "okay";
46 };
47
44 sdhci@12530000 { 48 sdhci@12530000 {
45 bus-width = <4>; 49 bus-width = <4>;
46 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; 50 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
@@ -83,6 +87,150 @@
83 status = "okay"; 87 status = "okay";
84 }; 88 };
85 89
90 i2c@13860000 {
91 status = "okay";
92 samsung,i2c-sda-delay = <100>;
93 samsung,i2c-max-bus-freq = <20000>;
94 pinctrl-0 = <&i2c0_bus>;
95 pinctrl-names = "default";
96
97 max8997_pmic@66 {
98 compatible = "maxim,max8997-pmic";
99 reg = <0x66>;
100 interrupt-parent = <&gpx0>;
101 interrupts = <4 0>, <3 0>;
102
103 max8997,pmic-buck1-dvs-voltage = <1350000>;
104 max8997,pmic-buck2-dvs-voltage = <1100000>;
105 max8997,pmic-buck5-dvs-voltage = <1200000>;
106
107 regulators {
108 ldo1_reg: LDO1 {
109 regulator-name = "VDD_ABB_3.3V";
110 regulator-min-microvolt = <3300000>;
111 regulator-max-microvolt = <3300000>;
112 };
113
114 ldo2_reg: LDO2 {
115 regulator-name = "VDD_ALIVE_1.1V";
116 regulator-min-microvolt = <1100000>;
117 regulator-max-microvolt = <1100000>;
118 regulator-always-on;
119 };
120
121 ldo3_reg: LDO3 {
122 regulator-name = "VMIPI_1.1V";
123 regulator-min-microvolt = <1100000>;
124 regulator-max-microvolt = <1100000>;
125 };
126
127 ldo4_reg: LDO4 {
128 regulator-name = "VDD_RTC_1.8V";
129 regulator-min-microvolt = <1800000>;
130 regulator-max-microvolt = <1800000>;
131 regulator-always-on;
132 };
133
134 ldo6_reg: LDO6 {
135 regulator-name = "VMIPI_1.8V";
136 regulator-min-microvolt = <1800000>;
137 regulator-max-microvolt = <1800000>;
138 regulator-always-on;
139 };
140
141 ldo7_reg: LDO7 {
142 regulator-name = "VDD_AUD_1.8V";
143 regulator-min-microvolt = <1800000>;
144 regulator-max-microvolt = <1800000>;
145 };
146
147 ldo8_reg: LDO8 {
148 regulator-name = "VADC_3.3V";
149 regulator-min-microvolt = <3300000>;
150 regulator-max-microvolt = <3300000>;
151 };
152
153 ldo9_reg: LDO9 {
154 regulator-name = "DVDD_SWB_2.8V";
155 regulator-min-microvolt = <2800000>;
156 regulator-max-microvolt = <2800000>;
157 regulator-always-on;
158 };
159
160 ldo10_reg: LDO10 {
161 regulator-name = "VDD_PLL_1.1V";
162 regulator-min-microvolt = <1100000>;
163 regulator-max-microvolt = <1100000>;
164 regulator-always-on;
165 };
166
167 ldo11_reg: LDO11 {
168 regulator-name = "VDD_AUD_3V";
169 regulator-min-microvolt = <3000000>;
170 regulator-max-microvolt = <3000000>;
171 };
172
173 ldo14_reg: LDO14 {
174 regulator-name = "AVDD18_SWB_1.8V";
175 regulator-min-microvolt = <1800000>;
176 regulator-max-microvolt = <1800000>;
177 regulator-always-on;
178 };
179
180 ldo17_reg: LDO17 {
181 regulator-name = "VDD_SWB_3.3V";
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
184 regulator-always-on;
185 };
186
187 ldo21_reg: LDO21 {
188 regulator-name = "VDD_MIF_1.2V";
189 regulator-min-microvolt = <1200000>;
190 regulator-max-microvolt = <1200000>;
191 regulator-always-on;
192 };
193
194 buck1_reg: BUCK1 {
195 regulator-name = "VDD_ARM_1.2V";
196 regulator-min-microvolt = <950000>;
197 regulator-max-microvolt = <1350000>;
198 regulator-always-on;
199 regulator-boot-on;
200 };
201
202 buck2_reg: BUCK2 {
203 regulator-name = "VDD_INT_1.1V";
204 regulator-min-microvolt = <900000>;
205 regulator-max-microvolt = <1100000>;
206 regulator-always-on;
207 regulator-boot-on;
208 };
209
210 buck3_reg: BUCK3 {
211 regulator-name = "VDD_G3D_1.1V";
212 regulator-min-microvolt = <900000>;
213 regulator-max-microvolt = <1100000>;
214 };
215
216 buck5_reg: BUCK5 {
217 regulator-name = "VDDQ_M1M2_1.2V";
218 regulator-min-microvolt = <1200000>;
219 regulator-max-microvolt = <1200000>;
220 regulator-always-on;
221 };
222
223 buck7_reg: BUCK7 {
224 regulator-name = "VDD_LCD_3.3V";
225 regulator-min-microvolt = <3300000>;
226 regulator-max-microvolt = <3300000>;
227 regulator-boot-on;
228 regulator-always-on;
229 };
230 };
231 };
232 };
233
86 gpio_keys { 234 gpio_keys {
87 compatible = "gpio-keys"; 235 compatible = "gpio-keys";
88 #address-cells = <1>; 236 #address-cells = <1>;
@@ -143,4 +291,25 @@
143 clock-frequency = <24000000>; 291 clock-frequency = <24000000>;
144 }; 292 };
145 }; 293 };
294
295 fimd@11c00000 {
296 pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>;
297 pinctrl-names = "default";
298 status = "okay";
299 };
300
301 display-timings {
302 native-mode = <&timing0>;
303 timing0: timing {
304 clock-frequency = <50000>;
305 hactive = <1024>;
306 vactive = <600>;
307 hfront-porch = <64>;
308 hback-porch = <16>;
309 hsync-len = <48>;
310 vback-porch = <64>;
311 vfront-porch = <16>;
312 vsync-len = <3>;
313 };
314 };
146}; 315};
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 55a2efb763d1..553bceae8967 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -330,6 +330,95 @@
330 samsung,pin-pud = <3>; 330 samsung,pin-pud = <3>;
331 samsung,pin-drv = <0>; 331 samsung,pin-drv = <0>;
332 }; 332 };
333
334 pwm0_out: pwm0-out {
335 samsung,pins = "gpd0-0";
336 samsung,pin-function = <2>;
337 samsung,pin-pud = <0>;
338 samsung,pin-drv = <0>;
339 };
340
341 pwm1_out: pwm1-out {
342 samsung,pins = "gpd0-1";
343 samsung,pin-function = <2>;
344 samsung,pin-pud = <0>;
345 samsung,pin-drv = <0>;
346 };
347
348 pwm2_out: pwm2-out {
349 samsung,pins = "gpd0-2";
350 samsung,pin-function = <2>;
351 samsung,pin-pud = <0>;
352 samsung,pin-drv = <0>;
353 };
354
355 pwm3_out: pwm3-out {
356 samsung,pins = "gpd0-3";
357 samsung,pin-function = <2>;
358 samsung,pin-pud = <0>;
359 samsung,pin-drv = <0>;
360 };
361
362 lcd_ctrl: lcd-ctrl {
363 samsung,pins = "gpd0-0", "gpd0-1";
364 samsung,pin-function = <3>;
365 samsung,pin-pud = <0>;
366 samsung,pin-drv = <0>;
367 };
368
369 lcd_sync: lcd-sync {
370 samsung,pins = "gpf0-0", "gpf0-1";
371 samsung,pin-function = <2>;
372 samsung,pin-pud = <0>;
373 samsung,pin-drv = <0>;
374 };
375
376 lcd_en: lcd-en {
377 samsung,pins = "gpe3-4";
378 samsung,pin-function = <2>;
379 samsung,pin-pud = <0>;
380 samsung,pin-drv = <0>;
381 };
382
383 lcd_clk: lcd-clk {
384 samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
385 samsung,pin-function = <2>;
386 samsung,pin-pud = <0>;
387 samsung,pin-drv = <0>;
388 };
389
390 lcd_data16: lcd-data-width16 {
391 samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
392 "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
393 "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
394 "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
395 samsung,pin-function = <2>;
396 samsung,pin-pud = <0>;
397 samsung,pin-drv = <0>;
398 };
399
400 lcd_data18: lcd-data-width18 {
401 samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
402 "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
403 "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
404 "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
405 "gpf3-2", "gpf3-3";
406 samsung,pin-function = <2>;
407 samsung,pin-pud = <0>;
408 samsung,pin-drv = <0>;
409 };
410
411 lcd_data24: lcd-data-width24 {
412 samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
413 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
414 "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
415 "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
416 "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
417 "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
418 samsung,pin-function = <2>;
419 samsung,pin-pud = <0>;
420 samsung,pin-drv = <0>;
421 };
333 }; 422 };
334 423
335 pinctrl@11000000 { 424 pinctrl@11000000 {
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b72acf5..9c01b718d29d 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
15*/ 15*/
16 16
17/dts-v1/; 17/dts-v1/;
18/include/ "exynos4210.dtsi" 18#include "exynos4210.dtsi"
19 19
20/ { 20/ {
21 model = "Samsung smdkv310 evaluation board based on Exynos4210"; 21 model = "Samsung smdkv310 evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484c7bb1..94eebffe3044 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
13*/ 13*/
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "exynos4210.dtsi" 16#include "exynos4210.dtsi"
17 17
18/ { 18/ {
19 model = "Samsung Trats based on Exynos4210"; 19 model = "Samsung Trats based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb51dcb7..889cdada1ce9 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
13*/ 13*/
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "exynos4210.dtsi" 16#include "exynos4210.dtsi"
17 17
18/ { 18/ {
19 model = "Samsung Universal C210 based on Exynos4210 rev0"; 19 model = "Samsung Universal C210 based on Exynos4210 rev0";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 54710de82908..b7f358a93bcb 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
19 * published by the Free Software Foundation. 19 * published by the Free Software Foundation.
20*/ 20*/
21 21
22/include/ "exynos4.dtsi" 22#include "exynos4.dtsi"
23/include/ "exynos4210-pinctrl.dtsi" 23#include "exynos4210-pinctrl.dtsi"
24 24
25/ { 25/ {
26 compatible = "samsung,exynos4210"; 26 compatible = "samsung,exynos4210";
@@ -112,12 +112,17 @@
112 interrupt-parent = <&combiner>; 112 interrupt-parent = <&combiner>;
113 reg = <0x100C0000 0x100>; 113 reg = <0x100C0000 0x100>;
114 interrupts = <2 4>; 114 interrupts = <2 4>;
115 clocks = <&clock 383>;
116 clock-names = "tmu_apbif";
117 status = "disabled";
115 }; 118 };
116 119
117 g2d@12800000 { 120 g2d@12800000 {
118 compatible = "samsung,s5pv210-g2d"; 121 compatible = "samsung,s5pv210-g2d";
119 reg = <0x12800000 0x1000>; 122 reg = <0x12800000 0x1000>;
120 interrupts = <0 89 0>; 123 interrupts = <0 89 0>;
124 clocks = <&clock 177>, <&clock 277>;
125 clock-names = "sclk_fimg2d", "fimg2d";
121 status = "disabled"; 126 status = "disabled";
122 }; 127 };
123}; 128};
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f49cea6..6f34d7f6ba7e 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20/include/ "exynos4x12.dtsi" 20#include "exynos4x12.dtsi"
21 21
22/ { 22/ {
23 compatible = "samsung,exynos4212"; 23 compatible = "samsung,exynos4212";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf77984..46c678ee119c 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
12*/ 12*/
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "exynos4412.dtsi" 15#include "exynos4412.dtsi"
16 16
17/ { 17/ {
18 model = "Hardkernel ODROID-X board based on Exynos4412"; 18 model = "Hardkernel ODROID-X board based on Exynos4412";
@@ -43,6 +43,7 @@
43 #size-cells = <0>; 43 #size-cells = <0>;
44 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 44 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
45 pinctrl-names = "default"; 45 pinctrl-names = "default";
46 vmmc-supply = <&ldo20_reg &buck8_reg>;
46 status = "okay"; 47 status = "okay";
47 48
48 num-slots = <1>; 49 num-slots = <1>;
@@ -78,6 +79,7 @@
78 bus-width = <4>; 79 bus-width = <4>;
79 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 80 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
80 pinctrl-names = "default"; 81 pinctrl-names = "default";
82 vmmc-supply = <&ldo4_reg &ldo21_reg>;
81 status = "okay"; 83 status = "okay";
82 }; 84 };
83 85
@@ -108,4 +110,199 @@
108 clock-frequency = <24000000>; 110 clock-frequency = <24000000>;
109 }; 111 };
110 }; 112 };
113
114 i2c@13860000 {
115 pinctrl-0 = <&i2c0_bus>;
116 pinctrl-names = "default";
117 status = "okay";
118
119 max77686: pmic@09 {
120 compatible = "maxim,max77686";
121 reg = <0x09>;
122
123 voltage-regulators {
124 ldo1_reg: LDO1 {
125 regulator-name = "VDD_ALIVE_1.0V";
126 regulator-min-microvolt = <1000000>;
127 regulator-max-microvolt = <1000000>;
128 regulator-always-on;
129 };
130
131 ldo2_reg: LDO2 {
132 regulator-name = "VDDQ_M1_2_1.8V";
133 regulator-min-microvolt = <1800000>;
134 regulator-max-microvolt = <1800000>;
135 regulator-always-on;
136 };
137
138 ldo3_reg: LDO3 {
139 regulator-name = "VDDQ_EXT_1.8V";
140 regulator-min-microvolt = <1800000>;
141 regulator-max-microvolt = <1800000>;
142 regulator-always-on;
143 };
144
145 ldo4_reg: LDO4 {
146 regulator-name = "VDDQ_MMC2_2.8V";
147 regulator-min-microvolt = <2800000>;
148 regulator-max-microvolt = <2800000>;
149 regulator-always-on;
150 regulator-boot-on;
151 };
152
153 ldo5_reg: LDO5 {
154 regulator-name = "VDDQ_MMC1_3_1.8V";
155 regulator-min-microvolt = <1800000>;
156 regulator-max-microvolt = <1800000>;
157 regulator-always-on;
158 regulator-boot-on;
159 };
160
161 ldo6_reg: LDO6 {
162 regulator-name = "VDD10_MPLL_1.0V";
163 regulator-min-microvolt = <1000000>;
164 regulator-max-microvolt = <1000000>;
165 regulator-always-on;
166 };
167
168 ldo7_reg: LDO7 {
169 regulator-name = "VDD10_XPLL_1.0V";
170 regulator-min-microvolt = <1000000>;
171 regulator-max-microvolt = <1000000>;
172 regulator-always-on;
173 };
174
175 ldo11_reg: LDO11 {
176 regulator-name = "VDD18_ABB1_1.8V";
177 regulator-min-microvolt = <1800000>;
178 regulator-max-microvolt = <1800000>;
179 regulator-always-on;
180 };
181
182 ldo12_reg: LDO12 {
183 regulator-name = "VDD33_USB_3.3V";
184 regulator-min-microvolt = <3300000>;
185 regulator-max-microvolt = <3300000>;
186 regulator-always-on;
187 regulator-boot-on;
188 };
189
190 ldo13_reg: LDO13 {
191 regulator-name = "VDDQ_C2C_W_1.8V";
192 regulator-min-microvolt = <1800000>;
193 regulator-max-microvolt = <1800000>;
194 regulator-always-on;
195 regulator-boot-on;
196 };
197
198 ldo14_reg: LDO14 {
199 regulator-name = "VDD18_ABB0_2_1.8V";
200 regulator-min-microvolt = <1800000>;
201 regulator-max-microvolt = <1800000>;
202 regulator-always-on;
203 regulator-boot-on;
204 };
205
206 ldo15_reg: LDO15 {
207 regulator-name = "VDD10_HSIC_1.0V";
208 regulator-min-microvolt = <1000000>;
209 regulator-max-microvolt = <1000000>;
210 regulator-always-on;
211 regulator-boot-on;
212 };
213
214 ldo16_reg: LDO16 {
215 regulator-name = "VDD18_HSIC_1.8V";
216 regulator-min-microvolt = <1800000>;
217 regulator-max-microvolt = <1800000>;
218 regulator-always-on;
219 regulator-boot-on;
220 };
221
222 ldo20_reg: LDO20 {
223 regulator-name = "LDO20_1.8V";
224 regulator-min-microvolt = <1800000>;
225 regulator-max-microvolt = <1800000>;
226 regulator-boot-on;
227 };
228
229 ldo21_reg: LDO21 {
230 regulator-name = "LDO21_3.3V";
231 regulator-min-microvolt = <3300000>;
232 regulator-max-microvolt = <3300000>;
233 regulator-always-on;
234 regulator-boot-on;
235 };
236
237 ldo25_reg: LDO25 {
238 regulator-name = "VDDQ_LCD_1.8V";
239 regulator-min-microvolt = <1800000>;
240 regulator-max-microvolt = <1800000>;
241 regulator-always-on;
242 regulator-boot-on;
243 };
244
245 buck1_reg: BUCK1 {
246 regulator-name = "vdd_mif";
247 regulator-min-microvolt = <1000000>;
248 regulator-max-microvolt = <1000000>;
249 regulator-always-on;
250 regulator-boot-on;
251 };
252
253 buck2_reg: BUCK2 {
254 regulator-name = "vdd_arm";
255 regulator-min-microvolt = <900000>;
256 regulator-max-microvolt = <1300000>;
257 regulator-always-on;
258 regulator-boot-on;
259 };
260
261 buck3_reg: BUCK3 {
262 regulator-name = "vdd_int";
263 regulator-min-microvolt = <1000000>;
264 regulator-max-microvolt = <1000000>;
265 regulator-always-on;
266 regulator-boot-on;
267 };
268
269 buck4_reg: BUCK4 {
270 regulator-name = "vdd_g3d";
271 regulator-min-microvolt = <900000>;
272 regulator-max-microvolt = <1100000>;
273 regulator-microvolt-offset = <50000>;
274 };
275
276 buck5_reg: BUCK5 {
277 regulator-name = "VDDQ_CKEM1_2_1.2V";
278 regulator-min-microvolt = <1200000>;
279 regulator-max-microvolt = <1200000>;
280 regulator-always-on;
281 regulator-boot-on;
282 };
283
284 buck6_reg: BUCK6 {
285 regulator-name = "BUCK6_1.35V";
286 regulator-min-microvolt = <1350000>;
287 regulator-max-microvolt = <1350000>;
288 regulator-always-on;
289 regulator-boot-on;
290 };
291
292 buck7_reg: BUCK7 {
293 regulator-name = "BUCK7_2.0V";
294 regulator-min-microvolt = <2000000>;
295 regulator-max-microvolt = <2000000>;
296 regulator-always-on;
297 };
298
299 buck8_reg: BUCK8 {
300 regulator-name = "BUCK8_2.8V";
301 regulator-min-microvolt = <2800000>;
302 regulator-max-microvolt = <2800000>;
303 regulator-always-on;
304 };
305 };
306 };
307 };
111}; 308};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 1c21bad32ca9..7993641cb32a 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
13*/ 13*/
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "exynos4412.dtsi" 16#include "exynos4412.dtsi"
17 17
18/ { 18/ {
19 model = "Insignal Origen evaluation board based on Exynos4412"; 19 model = "Insignal Origen evaluation board based on Exynos4412";
@@ -36,6 +36,72 @@
36 enable-active-high; 36 enable-active-high;
37 }; 37 };
38 38
39 pinctrl@11000000 {
40 keypad_rows: keypad-rows {
41 samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
42 samsung,pin-function = <3>;
43 samsung,pin-pud = <3>;
44 samsung,pin-drv = <0>;
45 };
46
47 keypad_cols: keypad-cols {
48 samsung,pins = "gpx1-0", "gpx1-1";
49 samsung,pin-function = <3>;
50 samsung,pin-pud = <0>;
51 samsung,pin-drv = <0>;
52 };
53 };
54
55 keypad@100A0000 {
56 samsung,keypad-num-rows = <3>;
57 samsung,keypad-num-columns = <2>;
58 linux,keypad-no-autorepeat;
59 linux,keypad-wakeup;
60 pinctrl-0 = <&keypad_rows &keypad_cols>;
61 pinctrl-names = "default";
62 status = "okay";
63
64 key_home {
65 keypad,row = <0>;
66 keypad,column = <0>;
67 linux,code = <102>;
68 };
69
70 key_down {
71 keypad,row = <0>;
72 keypad,column = <1>;
73 linux,code = <108>;
74 };
75
76 key_up {
77 keypad,row = <1>;
78 keypad,column = <0>;
79 linux,code = <103>;
80 };
81
82 key_menu {
83 keypad,row = <1>;
84 keypad,column = <1>;
85 linux,code = <139>;
86 };
87
88 key_back {
89 keypad,row = <2>;
90 keypad,column = <0>;
91 linux,code = <158>;
92 };
93
94 key_enter {
95 keypad,row = <2>;
96 keypad,column = <1>;
97 linux,code = <28>;
98 };
99 };
100
101 g2d@10800000 {
102 status = "okay";
103 };
104
39 sdhci@12530000 { 105 sdhci@12530000 {
40 bus-width = <4>; 106 bus-width = <4>;
41 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; 107 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index dd564310d4a5..ad316a1ee9e0 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
13*/ 13*/
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "exynos4412.dtsi" 16#include "exynos4412.dtsi"
17 17
18/ { 18/ {
19 model = "Samsung SMDK evaluation board based on Exynos4412"; 19 model = "Samsung SMDK evaluation board based on Exynos4412";
@@ -31,8 +31,91 @@
31 status = "okay"; 31 status = "okay";
32 }; 32 };
33 33
34 g2d@10800000 { 34 pinctrl@11000000 {
35 keypad_rows: keypad-rows {
36 samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
37 samsung,pin-function = <3>;
38 samsung,pin-pud = <3>;
39 samsung,pin-drv = <0>;
40 };
41
42 keypad_cols: keypad-cols {
43 samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
44 "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
45 samsung,pin-function = <3>;
46 samsung,pin-pud = <0>;
47 samsung,pin-drv = <0>;
48 };
49 };
50
51 keypad@100A0000 {
52 samsung,keypad-num-rows = <3>;
53 samsung,keypad-num-columns = <8>;
54 linux,keypad-no-autorepeat;
55 linux,keypad-wakeup;
56 pinctrl-0 = <&keypad_rows &keypad_cols>;
57 pinctrl-names = "default";
35 status = "okay"; 58 status = "okay";
59
60 key_1 {
61 keypad,row = <1>;
62 keypad,column = <3>;
63 linux,code = <2>;
64 };
65
66 key_2 {
67 keypad,row = <1>;
68 keypad,column = <4>;
69 linux,code = <3>;
70 };
71
72 key_3 {
73 keypad,row = <1>;
74 keypad,column = <5>;
75 linux,code = <4>;
76 };
77
78 key_4 {
79 keypad,row = <1>;
80 keypad,column = <6>;
81 linux,code = <5>;
82 };
83
84 key_5 {
85 keypad,row = <1>;
86 keypad,column = <7>;
87 linux,code = <6>;
88 };
89
90 key_A {
91 keypad,row = <2>;
92 keypad,column = <6>;
93 linux,code = <30>;
94 };
95
96 key_B {
97 keypad,row = <2>;
98 keypad,column = <7>;
99 linux,code = <48>;
100 };
101
102 key_C {
103 keypad,row = <0>;
104 keypad,column = <5>;
105 linux,code = <46>;
106 };
107
108 key_D {
109 keypad,row = <2>;
110 keypad,column = <5>;
111 linux,code = <32>;
112 };
113
114 key_E {
115 keypad,row = <0>;
116 keypad,column = <7>;
117 linux,code = <18>;
118 };
36 }; 119 };
37 120
38 sdhci@12530000 { 121 sdhci@12530000 {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 270b389e0a1b..e743e677a9e2 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20/include/ "exynos4x12.dtsi" 20#include "exynos4x12.dtsi"
21 21
22/ { 22/ {
23 compatible = "samsung,exynos4412"; 23 compatible = "samsung,exynos4412";
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 099cec79e2ae..704290f7c5c0 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -778,62 +778,6 @@
778 samsung,pin-drv = <3>; 778 samsung,pin-drv = <3>;
779 }; 779 };
780 780
781 keypad_col0: keypad-col0 {
782 samsung,pins = "gpl2-0";
783 samsung,pin-function = <3>;
784 samsung,pin-pud = <0>;
785 samsung,pin-drv = <0>;
786 };
787
788 keypad_col1: keypad-col1 {
789 samsung,pins = "gpl2-1";
790 samsung,pin-function = <3>;
791 samsung,pin-pud = <0>;
792 samsung,pin-drv = <0>;
793 };
794
795 keypad_col2: keypad-col2 {
796 samsung,pins = "gpl2-2";
797 samsung,pin-function = <3>;
798 samsung,pin-pud = <0>;
799 samsung,pin-drv = <0>;
800 };
801
802 keypad_col3: keypad-col3 {
803 samsung,pins = "gpl2-3";
804 samsung,pin-function = <3>;
805 samsung,pin-pud = <0>;
806 samsung,pin-drv = <0>;
807 };
808
809 keypad_col4: keypad-col4 {
810 samsung,pins = "gpl2-4";
811 samsung,pin-function = <3>;
812 samsung,pin-pud = <0>;
813 samsung,pin-drv = <0>;
814 };
815
816 keypad_col5: keypad-col5 {
817 samsung,pins = "gpl2-5";
818 samsung,pin-function = <3>;
819 samsung,pin-pud = <0>;
820 samsung,pin-drv = <0>;
821 };
822
823 keypad_col6: keypad-col6 {
824 samsung,pins = "gpl2-6";
825 samsung,pin-function = <3>;
826 samsung,pin-pud = <0>;
827 samsung,pin-drv = <0>;
828 };
829
830 keypad_col7: keypad-col7 {
831 samsung,pins = "gpl2-7";
832 samsung,pin-function = <3>;
833 samsung,pin-pud = <0>;
834 samsung,pin-drv = <0>;
835 };
836
837 cam_port_b: cam-port-b { 781 cam_port_b: cam-port-b {
838 samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", 782 samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
839 "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", 783 "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7a285c..01da194ba329 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -17,8 +17,8 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20/include/ "exynos4.dtsi" 20#include "exynos4.dtsi"
21/include/ "exynos4x12-pinctrl.dtsi" 21#include "exynos4x12-pinctrl.dtsi"
22 22
23/ { 23/ {
24 aliases { 24 aliases {
@@ -28,14 +28,6 @@
28 pinctrl3 = &pinctrl_3; 28 pinctrl3 = &pinctrl_3;
29 }; 29 };
30 30
31 combiner:interrupt-controller@10440000 {
32 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
33 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
34 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
35 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
36 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
37 };
38
39 clock: clock-controller@0x10030000 { 31 clock: clock-controller@0x10030000 {
40 compatible = "samsung,exynos4412-clock"; 32 compatible = "samsung,exynos4412-clock";
41 reg = <0x10030000 0x20000>; 33 reg = <0x10030000 0x20000>;
@@ -77,6 +69,8 @@
77 compatible = "samsung,exynos4212-g2d"; 69 compatible = "samsung,exynos4212-g2d";
78 reg = <0x10800000 0x1000>; 70 reg = <0x10800000 0x1000>;
79 interrupts = <0 89 0>; 71 interrupts = <0 89 0>;
72 clocks = <&clock 177>, <&clock 277>;
73 clock-names = "sclk_fimg2d", "fimg2d";
80 status = "disabled"; 74 status = "disabled";
81 }; 75 };
82}; 76};
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
new file mode 100644
index 000000000000..f65e124c04a6
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -0,0 +1,111 @@
1/*
2 * Samsung's Exynos5 SoC series common device tree source
3 *
4 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
8 * SoCs from Exynos5 series can include this file and provide values for SoCs
9 * specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include "skeleton.dtsi"
17
18/ {
19 interrupt-parent = <&gic>;
20
21 chipid@10000000 {
22 compatible = "samsung,exynos4210-chipid";
23 reg = <0x10000000 0x100>;
24 };
25
26 combiner:interrupt-controller@10440000 {
27 compatible = "samsung,exynos4210-combiner";
28 #interrupt-cells = <2>;
29 interrupt-controller;
30 samsung,combiner-nr = <32>;
31 reg = <0x10440000 0x1000>;
32 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
33 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
34 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
35 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
36 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
37 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
38 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
39 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
40 };
41
42 gic:interrupt-controller@10481000 {
43 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
44 #interrupt-cells = <3>;
45 interrupt-controller;
46 reg = <0x10481000 0x1000>,
47 <0x10482000 0x1000>,
48 <0x10484000 0x2000>,
49 <0x10486000 0x2000>;
50 interrupts = <1 9 0xf04>;
51 };
52
53 dwmmc_0: dwmmc0@12200000 {
54 compatible = "samsung,exynos5250-dw-mshc";
55 interrupts = <0 75 0>;
56 #address-cells = <1>;
57 #size-cells = <0>;
58 };
59
60 dwmmc_1: dwmmc1@12210000 {
61 compatible = "samsung,exynos5250-dw-mshc";
62 interrupts = <0 76 0>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 };
66
67 dwmmc_2: dwmmc2@12220000 {
68 compatible = "samsung,exynos5250-dw-mshc";
69 interrupts = <0 77 0>;
70 #address-cells = <1>;
71 #size-cells = <0>;
72 };
73
74 serial@12C00000 {
75 compatible = "samsung,exynos4210-uart";
76 reg = <0x12C00000 0x100>;
77 interrupts = <0 51 0>;
78 };
79
80 serial@12C10000 {
81 compatible = "samsung,exynos4210-uart";
82 reg = <0x12C10000 0x100>;
83 interrupts = <0 52 0>;
84 };
85
86 serial@12C20000 {
87 compatible = "samsung,exynos4210-uart";
88 reg = <0x12C20000 0x100>;
89 interrupts = <0 53 0>;
90 };
91
92 serial@12C30000 {
93 compatible = "samsung,exynos4210-uart";
94 reg = <0x12C30000 0x100>;
95 interrupts = <0 54 0>;
96 };
97
98 rtc {
99 compatible = "samsung,s3c6410-rtc";
100 reg = <0x101E0000 0x100>;
101 interrupts = <0 43 0>, <0 44 0>;
102 status = "disabled";
103 };
104
105 watchdog {
106 compatible = "samsung,s3c2410-wdt";
107 reg = <0x101D0000 0x100>;
108 interrupts = <0 42 0>;
109 status = "disabled";
110 };
111};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 02cfc76d002f..abc7272c7afd 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -10,7 +10,7 @@
10*/ 10*/
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "exynos5250.dtsi" 13#include "exynos5250.dtsi"
14 14
15/ { 15/ {
16 model = "Insignal Arndale evaluation board based on EXYNOS5250"; 16 model = "Insignal Arndale evaluation board based on EXYNOS5250";
@@ -449,4 +449,35 @@
449 clock-frequency = <24000000>; 449 clock-frequency = <24000000>;
450 }; 450 };
451 }; 451 };
452
453 dp-controller {
454 samsung,color-space = <0>;
455 samsung,dynamic-range = <0>;
456 samsung,ycbcr-coeff = <0>;
457 samsung,color-depth = <1>;
458 samsung,link-rate = <0x0a>;
459 samsung,lane-count = <4>;
460 };
461
462 fimd: fimd@14400000 {
463 display-timings {
464 native-mode = <&timing0>;
465 timing0: timing@0 {
466 /* 2560x1600 DP panel */
467 clock-frequency = <50000>;
468 hactive = <2560>;
469 vactive = <1600>;
470 hfront-porch = <48>;
471 hback-porch = <80>;
472 hsync-len = <32>;
473 vback-porch = <16>;
474 vfront-porch = <8>;
475 vsync-len = <6>;
476 };
477 };
478 };
479
480 rtc {
481 status = "okay";
482 };
452}; 483};
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index d1650fb34c0a..e9cdee385092 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -553,6 +553,13 @@
553 samsung,pin-pud = <0>; 553 samsung,pin-pud = <0>;
554 samaung,pin-drv = <0>; 554 samaung,pin-drv = <0>;
555 }; 555 };
556
557 dp_hpd: dp_hpd {
558 samsung,pins = "gpx0-7";
559 samsung,pin-function = <3>;
560 samsung,pin-pud = <0>;
561 samaung,pin-drv = <0>;
562 };
556 }; 563 };
557 564
558 pinctrl@13400000 { 565 pinctrl@13400000 {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e0c792e2767..35a66dee4011 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
10*/ 10*/
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "exynos5250.dtsi" 13#include "exynos5250.dtsi"
14 14
15/ { 15/ {
16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; 16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
@@ -37,6 +37,30 @@
37 }; 37 };
38 }; 38 };
39 39
40 vdd:fixed-regulator@0 {
41 compatible = "regulator-fixed";
42 regulator-name = "vdd-supply";
43 regulator-min-microvolt = <1800000>;
44 regulator-max-microvolt = <1800000>;
45 regulator-always-on;
46 };
47
48 dbvdd:fixed-regulator@1 {
49 compatible = "regulator-fixed";
50 regulator-name = "dbvdd-supply";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-always-on;
54 };
55
56 spkvdd:fixed-regulator@2 {
57 compatible = "regulator-fixed";
58 regulator-name = "spkvdd-supply";
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
61 regulator-always-on;
62 };
63
40 i2c@12C70000 { 64 i2c@12C70000 {
41 samsung,i2c-sda-delay = <100>; 65 samsung,i2c-sda-delay = <100>;
42 samsung,i2c-max-bus-freq = <20000>; 66 samsung,i2c-max-bus-freq = <20000>;
@@ -47,8 +71,17 @@
47 }; 71 };
48 72
49 wm8994: wm8994@1a { 73 wm8994: wm8994@1a {
50 compatible = "wlf,wm8994"; 74 compatible = "wlf,wm8994";
51 reg = <0x1a>; 75 reg = <0x1a>;
76
77 gpio-controller;
78 #gpio-cells = <2>;
79
80 AVDD2-supply = <&vdd>;
81 CPVDD-supply = <&vdd>;
82 DBVDD-supply = <&dbvdd>;
83 SPKVDD1-supply = <&spkvdd>;
84 SPKVDD2-supply = <&spkvdd>;
52 }; 85 };
53 }; 86 };
54 87
@@ -224,6 +257,9 @@
224 samsung,color-depth = <1>; 257 samsung,color-depth = <1>;
225 samsung,link-rate = <0x0a>; 258 samsung,link-rate = <0x0a>;
226 samsung,lane-count = <4>; 259 samsung,lane-count = <4>;
260
261 pinctrl-names = "default";
262 pinctrl-0 = <&dp_hpd>;
227 }; 263 };
228 264
229 display-timings { 265 display-timings {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index d449feb7e143..e79331dba12d 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
9*/ 9*/
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "exynos5250.dtsi" 12#include "exynos5250.dtsi"
13/include/ "cros5250-common.dtsi" 13#include "cros5250-common.dtsi"
14 14
15/ { 15/ {
16 model = "Google Snow"; 16 model = "Google Snow";
@@ -171,6 +171,10 @@
171 }; 171 };
172 }; 172 };
173 173
174 rtc {
175 status = "okay";
176 };
177
174 /* 178 /*
175 * On Snow we've got SIP WiFi and so can keep drive strengths low to 179 * On Snow we've got SIP WiFi and so can keep drive strengths low to
176 * reduce EMI. 180 * reduce EMI.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 0673524238a6..d04ab0ad791a 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,12 +17,13 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20/include/ "skeleton.dtsi" 20#include "exynos5.dtsi"
21/include/ "exynos5250-pinctrl.dtsi" 21#include "exynos5250-pinctrl.dtsi"
22
23#include <dt-bindings/clk/exynos-audss-clk.h>
22 24
23/ { 25/ {
24 compatible = "samsung,exynos5250"; 26 compatible = "samsung,exynos5250";
25 interrupt-parent = <&gic>;
26 27
27 aliases { 28 aliases {
28 spi0 = &spi_0; 29 spi0 = &spi_0;
@@ -51,9 +52,20 @@
51 pinctrl3 = &pinctrl_3; 52 pinctrl3 = &pinctrl_3;
52 }; 53 };
53 54
54 chipid@10000000 { 55 cpus {
55 compatible = "samsung,exynos4210-chipid"; 56 #address-cells = <1>;
56 reg = <0x10000000 0x100>; 57 #size-cells = <0>;
58
59 cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0>;
63 };
64 cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 };
57 }; 69 };
58 70
59 pd_gsc: gsc-power-domain@0x10044000 { 71 pd_gsc: gsc-power-domain@0x10044000 {
@@ -72,15 +84,10 @@
72 #clock-cells = <1>; 84 #clock-cells = <1>;
73 }; 85 };
74 86
75 gic:interrupt-controller@10481000 { 87 clock_audss: audss-clock-controller@3810000 {
76 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 88 compatible = "samsung,exynos5250-audss-clock";
77 #interrupt-cells = <3>; 89 reg = <0x03810000 0x0C>;
78 interrupt-controller; 90 #clock-cells = <1>;
79 reg = <0x10481000 0x1000>,
80 <0x10482000 0x1000>,
81 <0x10484000 0x2000>,
82 <0x10486000 0x2000>;
83 interrupts = <1 9 0xf04>;
84 }; 91 };
85 92
86 timer { 93 timer {
@@ -91,22 +98,6 @@
91 <1 10 0xf08>; 98 <1 10 0xf08>;
92 }; 99 };
93 100
94 combiner:interrupt-controller@10440000 {
95 compatible = "samsung,exynos4210-combiner";
96 #interrupt-cells = <2>;
97 interrupt-controller;
98 samsung,combiner-nr = <32>;
99 reg = <0x10440000 0x1000>;
100 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
101 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
102 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
103 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
104 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
105 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
106 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
107 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
108 };
109
110 mct@101C0000 { 101 mct@101C0000 {
111 compatible = "samsung,exynos4210-mct"; 102 compatible = "samsung,exynos4210-mct";
112 reg = <0x101C0000 0x800>; 103 reg = <0x101C0000 0x800>;
@@ -168,9 +159,6 @@
168 }; 159 };
169 160
170 watchdog { 161 watchdog {
171 compatible = "samsung,s3c2410-wdt";
172 reg = <0x101D0000 0x100>;
173 interrupts = <0 42 0>;
174 clocks = <&clock 336>; 162 clocks = <&clock 336>;
175 clock-names = "watchdog"; 163 clock-names = "watchdog";
176 }; 164 };
@@ -183,12 +171,8 @@
183 }; 171 };
184 172
185 rtc { 173 rtc {
186 compatible = "samsung,s3c6410-rtc";
187 reg = <0x101E0000 0x100>;
188 interrupts = <0 43 0>, <0 44 0>;
189 clocks = <&clock 337>; 174 clocks = <&clock 337>;
190 clock-names = "rtc"; 175 clock-names = "rtc";
191 status = "disabled";
192 }; 176 };
193 177
194 tmu@10060000 { 178 tmu@10060000 {
@@ -200,33 +184,21 @@
200 }; 184 };
201 185
202 serial@12C00000 { 186 serial@12C00000 {
203 compatible = "samsung,exynos4210-uart";
204 reg = <0x12C00000 0x100>;
205 interrupts = <0 51 0>;
206 clocks = <&clock 289>, <&clock 146>; 187 clocks = <&clock 289>, <&clock 146>;
207 clock-names = "uart", "clk_uart_baud0"; 188 clock-names = "uart", "clk_uart_baud0";
208 }; 189 };
209 190
210 serial@12C10000 { 191 serial@12C10000 {
211 compatible = "samsung,exynos4210-uart";
212 reg = <0x12C10000 0x100>;
213 interrupts = <0 52 0>;
214 clocks = <&clock 290>, <&clock 147>; 192 clocks = <&clock 290>, <&clock 147>;
215 clock-names = "uart", "clk_uart_baud0"; 193 clock-names = "uart", "clk_uart_baud0";
216 }; 194 };
217 195
218 serial@12C20000 { 196 serial@12C20000 {
219 compatible = "samsung,exynos4210-uart";
220 reg = <0x12C20000 0x100>;
221 interrupts = <0 53 0>;
222 clocks = <&clock 291>, <&clock 148>; 197 clocks = <&clock 291>, <&clock 148>;
223 clock-names = "uart", "clk_uart_baud0"; 198 clock-names = "uart", "clk_uart_baud0";
224 }; 199 };
225 200
226 serial@12C30000 { 201 serial@12C30000 {
227 compatible = "samsung,exynos4210-uart";
228 reg = <0x12C30000 0x100>;
229 interrupts = <0 54 0>;
230 clocks = <&clock 292>, <&clock 149>; 202 clocks = <&clock 292>, <&clock 149>;
231 clock-names = "uart", "clk_uart_baud0"; 203 clock-names = "uart", "clk_uart_baud0";
232 }; 204 };
@@ -405,31 +377,19 @@
405 }; 377 };
406 378
407 dwmmc_0: dwmmc0@12200000 { 379 dwmmc_0: dwmmc0@12200000 {
408 compatible = "samsung,exynos5250-dw-mshc";
409 reg = <0x12200000 0x1000>; 380 reg = <0x12200000 0x1000>;
410 interrupts = <0 75 0>;
411 #address-cells = <1>;
412 #size-cells = <0>;
413 clocks = <&clock 280>, <&clock 139>; 381 clocks = <&clock 280>, <&clock 139>;
414 clock-names = "biu", "ciu"; 382 clock-names = "biu", "ciu";
415 }; 383 };
416 384
417 dwmmc_1: dwmmc1@12210000 { 385 dwmmc_1: dwmmc1@12210000 {
418 compatible = "samsung,exynos5250-dw-mshc";
419 reg = <0x12210000 0x1000>; 386 reg = <0x12210000 0x1000>;
420 interrupts = <0 76 0>;
421 #address-cells = <1>;
422 #size-cells = <0>;
423 clocks = <&clock 281>, <&clock 140>; 387 clocks = <&clock 281>, <&clock 140>;
424 clock-names = "biu", "ciu"; 388 clock-names = "biu", "ciu";
425 }; 389 };
426 390
427 dwmmc_2: dwmmc2@12220000 { 391 dwmmc_2: dwmmc2@12220000 {
428 compatible = "samsung,exynos5250-dw-mshc";
429 reg = <0x12220000 0x1000>; 392 reg = <0x12220000 0x1000>;
430 interrupts = <0 77 0>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 clocks = <&clock 282>, <&clock 141>; 393 clocks = <&clock 282>, <&clock 141>;
434 clock-names = "biu", "ciu"; 394 clock-names = "biu", "ciu";
435 }; 395 };
@@ -451,6 +411,10 @@
451 &pdma0 9 411 &pdma0 9
452 &pdma0 8>; 412 &pdma0 8>;
453 dma-names = "tx", "rx", "tx-sec"; 413 dma-names = "tx", "rx", "tx-sec";
414 clocks = <&clock_audss EXYNOS_I2S_BUS>,
415 <&clock_audss EXYNOS_I2S_BUS>,
416 <&clock_audss EXYNOS_SCLK_I2S>;
417 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
454 samsung,supports-6ch; 418 samsung,supports-6ch;
455 samsung,supports-rstclr; 419 samsung,supports-rstclr;
456 samsung,supports-secdai; 420 samsung,supports-secdai;
@@ -465,6 +429,8 @@
465 dmas = <&pdma1 12 429 dmas = <&pdma1 12
466 &pdma1 11>; 430 &pdma1 11>;
467 dma-names = "tx", "rx"; 431 dma-names = "tx", "rx";
432 clocks = <&clock 307>, <&clock 157>;
433 clock-names = "iis", "i2s_opclk0";
468 pinctrl-names = "default"; 434 pinctrl-names = "default";
469 pinctrl-0 = <&i2s1_bus>; 435 pinctrl-0 = <&i2s1_bus>;
470 }; 436 };
@@ -475,10 +441,42 @@
475 dmas = <&pdma0 12 441 dmas = <&pdma0 12
476 &pdma0 11>; 442 &pdma0 11>;
477 dma-names = "tx", "rx"; 443 dma-names = "tx", "rx";
444 clocks = <&clock 308>, <&clock 158>;
445 clock-names = "iis", "i2s_opclk0";
478 pinctrl-names = "default"; 446 pinctrl-names = "default";
479 pinctrl-0 = <&i2s2_bus>; 447 pinctrl-0 = <&i2s2_bus>;
480 }; 448 };
481 449
450 usb@12000000 {
451 compatible = "samsung,exynos5250-dwusb3";
452 clocks = <&clock 286>;
453 clock-names = "usbdrd30";
454 #address-cells = <1>;
455 #size-cells = <1>;
456 ranges;
457
458 dwc3 {
459 compatible = "synopsys,dwc3";
460 reg = <0x12000000 0x10000>;
461 interrupts = <0 72 0>;
462 usb-phy = <&usb2_phy &usb3_phy>;
463 };
464 };
465
466 usb3_phy: usbphy@12100000 {
467 compatible = "samsung,exynos5250-usb3phy";
468 reg = <0x12100000 0x100>;
469 clocks = <&clock 1>, <&clock 286>;
470 clock-names = "ext_xtal", "usbdrd30";
471 #address-cells = <1>;
472 #size-cells = <1>;
473 ranges;
474
475 usbphy-sys {
476 reg = <0x10040704 0x8>;
477 };
478 };
479
482 usb@12110000 { 480 usb@12110000 {
483 compatible = "samsung,exynos4210-ehci"; 481 compatible = "samsung,exynos4210-ehci";
484 reg = <0x12110000 0x100>; 482 reg = <0x12110000 0x100>;
@@ -497,7 +495,7 @@
497 clock-names = "usbhost"; 495 clock-names = "usbhost";
498 }; 496 };
499 497
500 usbphy@12130000 { 498 usb2_phy: usbphy@12130000 {
501 compatible = "samsung,exynos5250-usb2phy"; 499 compatible = "samsung,exynos5250-usb2phy";
502 reg = <0x12130000 0x100>; 500 reg = <0x12130000 0x100>;
503 clocks = <&clock 1>, <&clock 285>; 501 clocks = <&clock 1>, <&clock 285>;
@@ -621,6 +619,8 @@
621 reg = <0x145b0000 0x1000>; 619 reg = <0x145b0000 0x1000>;
622 interrupts = <10 3>; 620 interrupts = <10 3>;
623 interrupt-parent = <&combiner>; 621 interrupt-parent = <&combiner>;
622 clocks = <&clock 342>;
623 clock-names = "dp";
624 #address-cells = <1>; 624 #address-cells = <1>;
625 #size-cells = <0>; 625 #size-cells = <0>;
626 626
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
new file mode 100644
index 000000000000..08607df6a180
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,33 @@
1/*
2 * SAMSUNG SMDK5420 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13#include "exynos5420.dtsi"
14
15/ {
16 model = "Samsung SMDK5420 board based on EXYNOS5420";
17 compatible = "samsung,smdk5420", "samsung,exynos5420";
18
19 memory {
20 reg = <0x20000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttySAC2,115200 init=/linuxrc";
25 };
26
27 fixed-rate-clocks {
28 oscclk {
29 compatible = "samsung,exynos5420-oscclk";
30 clock-frequency = <24000000>;
31 };
32 };
33};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
new file mode 100644
index 000000000000..8474d63fc5e5
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -0,0 +1,103 @@
1/*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include "exynos5.dtsi"
17/ {
18 compatible = "samsung,exynos5420";
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu0: cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a15";
27 reg = <0x0>;
28 clock-frequency = <1800000000>;
29 };
30
31 cpu1: cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a15";
34 reg = <0x1>;
35 clock-frequency = <1800000000>;
36 };
37
38 cpu2: cpu@2 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a15";
41 reg = <0x2>;
42 clock-frequency = <1800000000>;
43 };
44
45 cpu3: cpu@3 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a15";
48 reg = <0x3>;
49 clock-frequency = <1800000000>;
50 };
51 };
52
53 clock: clock-controller@0x10010000 {
54 compatible = "samsung,exynos5420-clock";
55 reg = <0x10010000 0x30000>;
56 #clock-cells = <1>;
57 };
58
59 mct@101C0000 {
60 compatible = "samsung,exynos4210-mct";
61 reg = <0x101C0000 0x800>;
62 interrupt-controller;
63 #interrups-cells = <1>;
64 interrupt-parent = <&mct_map>;
65 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
66 clocks = <&clock 1>, <&clock 315>;
67 clock-names = "fin_pll", "mct";
68
69 mct_map: mct-map {
70 #interrupt-cells = <1>;
71 #address-cells = <0>;
72 #size-cells = <0>;
73 interrupt-map = <0 &combiner 23 3>,
74 <1 &combiner 23 4>,
75 <2 &combiner 25 2>,
76 <3 &combiner 25 3>,
77 <4 &gic 0 120 0>,
78 <5 &gic 0 121 0>,
79 <6 &gic 0 122 0>,
80 <7 &gic 0 123 0>;
81 };
82 };
83
84 serial@12C00000 {
85 clocks = <&clock 257>, <&clock 128>;
86 clock-names = "uart", "clk_uart_baud0";
87 };
88
89 serial@12C10000 {
90 clocks = <&clock 258>, <&clock 129>;
91 clock-names = "uart", "clk_uart_baud0";
92 };
93
94 serial@12C20000 {
95 clocks = <&clock 259>, <&clock 130>;
96 clock-names = "uart", "clk_uart_baud0";
97 };
98
99 serial@12C30000 {
100 clocks = <&clock 260>, <&clock 131>;
101 clock-names = "uart", "clk_uart_baud0";
102 };
103};
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index ef747b52b674..5b22508050da 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -10,14 +10,14 @@
10*/ 10*/
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "exynos5440.dtsi" 13#include "exynos5440.dtsi"
14 14
15/ { 15/ {
16 model = "SAMSUNG SD5v1 board based on EXYNOS5440"; 16 model = "SAMSUNG SD5v1 board based on EXYNOS5440";
17 compatible = "samsung,sd5v1", "samsung,exynos5440"; 17 compatible = "samsung,sd5v1", "samsung,exynos5440";
18 18
19 chosen { 19 chosen {
20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200"; 20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
21 }; 21 };
22 22
23 fixed-rate-clocks { 23 fixed-rate-clocks {
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042beb5c5..f32cd77930a6 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -10,18 +10,53 @@
10*/ 10*/
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "exynos5440.dtsi" 13#include "exynos5440.dtsi"
14 14
15/ { 15/ {
16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; 16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
17 compatible = "samsung,ssdk5440", "samsung,exynos5440"; 17 compatible = "samsung,ssdk5440", "samsung,exynos5440";
18 18
19 chosen { 19 chosen {
20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200"; 20 bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
21 }; 21 };
22 22
23 spi { 23 spi_0: spi@D0000 {
24 status = "disabled"; 24
25 flash: w25q128@0 {
26 #address-cells = <1>;
27 #size-cells = <1>;
28 compatible = "winbond,w25q128";
29 spi-max-frequency = <15625000>;
30 reg = <0>;
31 controller-data {
32 samsung,spi-feedback-delay = <0>;
33 };
34
35 partition@00000 {
36 label = "BootLoader";
37 reg = <0x60000 0x80000>;
38 read-only;
39 };
40
41 partition@e0000 {
42 label = "Recovery-Kernel";
43 reg = <0xe0000 0x300000>;
44 read-only;
45 };
46
47 partition@3e0000 {
48 label = "CRAM-FS";
49 reg = <0x3e0000 0x700000>;
50 read-only;
51 };
52
53 partition@ae0000 {
54 label = "User-Data";
55 reg = <0xae0000 0x520000>;
56 };
57
58 };
59
25 }; 60 };
26 61
27 fixed-rate-clocks { 62 fixed-rate-clocks {
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c8973845..8b6f8f0c9171 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,13 +9,17 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12/include/ "skeleton.dtsi" 12#include "skeleton.dtsi"
13 13
14/ { 14/ {
15 compatible = "samsung,exynos5440"; 15 compatible = "samsung,exynos5440";
16 16
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 18
19 aliases {
20 spi0 = &spi_0;
21 };
22
19 clock: clock-controller@0x160000 { 23 clock: clock-controller@0x160000 {
20 compatible = "samsung,exynos5440-clock"; 24 compatible = "samsung,exynos5440-clock";
21 reg = <0x160000 0x1000>; 25 reg = <0x160000 0x1000>;
@@ -79,8 +83,13 @@
79 interrupts = <0 57 0>; 83 interrupts = <0 57 0>;
80 operating-points = < 84 operating-points = <
81 /* KHz uV */ 85 /* KHz uV */
86 1500000 1100000
87 1400000 1075000
88 1300000 1050000
82 1200000 1025000 89 1200000 1025000
90 1100000 1000000
83 1000000 975000 91 1000000 975000
92 900000 950000
84 800000 925000 93 800000 925000
85 >; 94 >;
86 }; 95 };
@@ -101,14 +110,14 @@
101 clock-names = "uart", "clk_uart_baud0"; 110 clock-names = "uart", "clk_uart_baud0";
102 }; 111 };
103 112
104 spi { 113 spi_0: spi@D0000 {
105 compatible = "samsung,exynos4210-spi"; 114 compatible = "samsung,exynos5440-spi";
106 reg = <0xD0000 0x1000>; 115 reg = <0xD0000 0x100>;
107 interrupts = <0 4 0>; 116 interrupts = <0 4 0>;
108 tx-dma-channel = <&pdma0 5>; /* preliminary */
109 rx-dma-channel = <&pdma0 4>; /* preliminary */
110 #address-cells = <1>; 117 #address-cells = <1>;
111 #size-cells = <0>; 118 #size-cells = <0>;
119 samsung,spi-src-clk = <0>;
120 num-cs = <1>;
112 clocks = <&clock 21>, <&clock 16>; 121 clocks = <&clock 21>, <&clock 16>;
113 clock-names = "spi", "spi_busclk0"; 122 clock-names = "spi", "spi_busclk0";
114 }; 123 };
@@ -184,28 +193,6 @@
184 compatible = "arm,amba-bus"; 193 compatible = "arm,amba-bus";
185 interrupt-parent = <&gic>; 194 interrupt-parent = <&gic>;
186 ranges; 195 ranges;
187
188 pdma0: pdma@00121000 {
189 compatible = "arm,pl330", "arm,primecell";
190 reg = <0x121000 0x1000>;
191 interrupts = <0 46 0>;
192 clocks = <&clock 8>;
193 clock-names = "apb_pclk";
194 #dma-cells = <1>;
195 #dma-channels = <8>;
196 #dma-requests = <32>;
197 };
198
199 pdma1: pdma@00120000 {
200 compatible = "arm,pl330", "arm,primecell";
201 reg = <0x120000 0x1000>;
202 interrupts = <0 47 0>;
203 clocks = <&clock 8>;
204 clock-names = "apb_pclk";
205 #dma-cells = <1>;
206 #dma-channels = <8>;
207 #dma-requests = <32>;
208 };
209 }; 196 };
210 197
211 rtc { 198 rtc {
@@ -214,6 +201,29 @@
214 interrupts = <0 17 0>, <0 16 0>; 201 interrupts = <0 17 0>, <0 16 0>;
215 clocks = <&clock 21>; 202 clocks = <&clock 21>;
216 clock-names = "rtc"; 203 clock-names = "rtc";
217 status = "disabled"; 204 };
205
206 sata@210000 {
207 compatible = "snps,exynos5440-ahci";
208 reg = <0x210000 0x10000>;
209 interrupts = <0 30 0>;
210 clocks = <&clock 23>;
211 clock-names = "sata";
212 };
213
214 ohci@220000 {
215 compatible = "samsung,exynos5440-ohci";
216 reg = <0x220000 0x1000>;
217 interrupts = <0 29 0>;
218 clocks = <&clock 24>;
219 clock-names = "usbhost";
220 };
221
222 ehci@221000 {
223 compatible = "samsung,exynos5440-ehci";
224 reg = <0x221000 0x1000>;
225 interrupts = <0 29 0>;
226 clocks = <&clock 24>;
227 clock-names = "usbhost";
218 }; 228 };
219}; 229};
diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
new file mode 100644
index 000000000000..527e3193817f
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
@@ -0,0 +1,173 @@
1/*
2 * Samsung S3C2416 pinctrl settings
3 *
4 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11&pinctrl_0 {
12 /*
13 * Pin banks
14 */
15
16 gpa: gpa {
17 gpio-controller;
18 #gpio-cells = <2>;
19 };
20
21 gpb: gpb {
22 gpio-controller;
23 #gpio-cells = <2>;
24 };
25
26 gpc: gpc {
27 gpio-controller;
28 #gpio-cells = <2>;
29 };
30
31 gpd: gpd {
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35
36 gpe: gpe {
37 gpio-controller;
38 #gpio-cells = <2>;
39 };
40
41 gpf: gpf {
42 gpio-controller;
43 #gpio-cells = <2>;
44 interrupt-controller;
45 #interrupt-cells = <2>;
46 };
47
48 gpg: gpg {
49 gpio-controller;
50 #gpio-cells = <2>;
51 interrupt-controller;
52 #interrupt-cells = <2>;
53 };
54
55 gph: gph {
56 gpio-controller;
57 #gpio-cells = <2>;
58 };
59
60 gpj: gpj {
61 gpio-controller;
62 #gpio-cells = <2>;
63 };
64
65 gpk: gpk {
66 gpio-controller;
67 #gpio-cells = <2>;
68 };
69
70 gpl: gpl {
71 gpio-controller;
72 #gpio-cells = <2>;
73 };
74
75 gpm: gpm {
76 gpio-controller;
77 #gpio-cells = <2>;
78 };
79
80 /*
81 * Pin groups
82 */
83
84 uart0_data: uart0-data {
85 samsung,pins = "gph-0", "gph-1";
86 samsung,pin-function = <2>;
87 };
88
89 uart0_fctl: uart0-fctl {
90 samsung,pins = "gph-8", "gph-9";
91 samsung,pin-function = <2>;
92 };
93
94 uart1_data: uart1-data {
95 samsung,pins = "gph-2", "gph-3";
96 samsung,pin-function = <2>;
97 };
98
99 uart1_fctl: uart1-fctl {
100 samsung,pins = "gph-10", "gph-11";
101 samsung,pin-function = <2>;
102 };
103
104 uart2_data: uart2-data {
105 samsung,pins = "gph-4", "gph-5";
106 samsung,pin-function = <2>;
107 };
108
109 uart2_fctl: uart2-fctl {
110 samsung,pins = "gph-6", "gph-7";
111 samsung,pin-function = <2>;
112 };
113
114 uart3_data: uart3-data {
115 samsung,pins = "gph-6", "gph-7";
116 samsung,pin-function = <2>;
117 };
118
119 extuart_clk: extuart-clk {
120 samsung,pins = "gph-12";
121 samsung,pin-function = <2>;
122 };
123
124 i2c0_bus: i2c0-bus {
125 samsung,pins = "gpe-14", "gpe-15";
126 samsung,pin-function = <2>;
127 };
128
129 spi0_bus: spi0-bus {
130 samsung,pins = "gpe-11", "gpe-12", "gpe-13";
131 samsung,pin-function = <2>;
132 };
133
134 sd0_clk: sd0-clk {
135 samsung,pins = "gpe-5";
136 samsung,pin-function = <2>;
137 };
138
139 sd0_cmd: sd0-cmd {
140 samsung,pins = "gpe-6";
141 samsung,pin-function = <2>;
142 };
143
144 sd0_bus1: sd0-bus1 {
145 samsung,pins = "gpe-7";
146 samsung,pin-function = <2>;
147 };
148
149 sd0_bus4: sd0-bus4 {
150 samsung,pins = "gpe-8", "gpe-9", "gpe-10";
151 samsung,pin-function = <2>;
152 };
153
154 sd1_cmd: sd1-cmd {
155 samsung,pins = "gpl-8";
156 samsung,pin-function = <2>;
157 };
158
159 sd1_clk: sd1-clk {
160 samsung,pins = "gpl-9";
161 samsung,pin-function = <2>;
162 };
163
164 sd1_bus1: sd1-bus1 {
165 samsung,pins = "gpl-0";
166 samsung,pin-function = <2>;
167 };
168
169 sd1_bus4: sd1-bus4 {
170 samsung,pins = "gpl-1", "gpl-2", "gpl-3";
171 samsung,pin-function = <2>;
172 };
173};
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
new file mode 100644
index 000000000000..59594cf15998
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -0,0 +1,72 @@
1/*
2 * SAMSUNG SMDK2416 board device tree source
3 *
4 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/dts-v1/;
12#include "s3c2416.dtsi"
13
14/ {
15 model = "SMDK2416";
16 compatible = "samsung,s3c2416";
17
18 memory {
19 reg = <0x30000000 0x4000000>;
20 };
21
22 serial@50000000 {
23 status = "okay";
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
26 };
27
28 serial@50004000 {
29 status = "okay";
30 pinctrl-names = "default";
31 pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
32 };
33
34 serial@50008000 {
35 status = "okay";
36 pinctrl-names = "default";
37 pinctrl-0 = <&uart2_data>;
38 };
39
40 serial@5000C000 {
41 status = "okay";
42 pinctrl-names = "default";
43 pinctrl-0 = <&uart3_data>;
44 };
45
46 watchdog@53000000 {
47 status = "okay";
48 };
49
50 rtc@57000000 {
51 status = "okay";
52 };
53
54 sdhci@4AC00000 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>,
57 <&sd0_bus1>, <&sd0_bus4>;
58 bus-width = <4>;
59 cd-gpios = <&gpf 1 0>;
60 cd-inverted;
61 status = "okay";
62 };
63
64 sdhci@4A800000 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&sd1_clk>, <&sd1_cmd>,
67 <&sd1_bus1>, <&sd1_bus4>;
68 bus-width = <4>;
69 broken-cd;
70 status = "okay";
71 };
72};
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
new file mode 100644
index 000000000000..e6555bdd81b8
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -0,0 +1,79 @@
1/*
2 * Samsung's S3C2416 SoC device tree source
3 *
4 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include "s3c24xx.dtsi"
12#include "s3c2416-pinctrl.dtsi"
13
14/ {
15 model = "Samsung S3C2416 SoC";
16 compatible = "samsung,s3c2416";
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu {
23 compatible = "arm,arm926ejs";
24 };
25 };
26
27 interrupt-controller@4a000000 {
28 compatible = "samsung,s3c2416-irq";
29 };
30
31 pinctrl@56000000 {
32 compatible = "samsung,s3c2416-pinctrl";
33 };
34
35 serial@50000000 {
36 compatible = "samsung,s3c2440-uart";
37 };
38
39 serial@50004000 {
40 compatible = "samsung,s3c2440-uart";
41 };
42
43 serial@50008000 {
44 compatible = "samsung,s3c2440-uart";
45 };
46
47 serial@5000C000 {
48 compatible = "samsung,s3c2440-uart";
49 reg = <0x5000C000 0x4000>;
50 interrupts = <1 18 24 4>, <1 18 25 4>;
51 status = "disabled";
52 };
53
54 sdhci@4AC00000 {
55 compatible = "samsung,s3c6410-sdhci";
56 reg = <0x4AC00000 0x100>;
57 interrupts = <0 0 21 3>;
58 status = "disabled";
59 };
60
61 sdhci@4A800000 {
62 compatible = "samsung,s3c6410-sdhci";
63 reg = <0x4A800000 0x100>;
64 interrupts = <0 0 20 3>;
65 status = "disabled";
66 };
67
68 watchdog@53000000 {
69 interrupts = <1 9 27 3>;
70 };
71
72 rtc@57000000 {
73 compatible = "samsung,s3c2416-rtc";
74 };
75
76 i2c@54000000 {
77 compatible = "samsung,s3c2440-i2c";
78 };
79};
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
new file mode 100644
index 000000000000..2d1d7dc9418a
--- /dev/null
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -0,0 +1,92 @@
1/*
2 * Samsung's S3C24XX family device tree source
3 *
4 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include "skeleton.dtsi"
12
13/ {
14 compatible = "samsung,s3c24xx";
15 interrupt-parent = <&intc>;
16
17 aliases {
18 pinctrl0 = &pinctrl_0;
19 };
20
21 intc:interrupt-controller@4a000000 {
22 compatible = "samsung,s3c2410-irq";
23 reg = <0x4a000000 0x100>;
24 interrupt-controller;
25 #interrupt-cells = <4>;
26 };
27
28 pinctrl_0: pinctrl@56000000 {
29 reg = <0x56000000 0x1000>;
30
31 wakeup-interrupt-controller {
32 compatible = "samsung,s3c2410-wakeup-eint";
33 interrupts = <0 0 0 3>,
34 <0 0 1 3>,
35 <0 0 2 3>,
36 <0 0 3 3>,
37 <0 0 4 4>,
38 <0 0 5 4>;
39 };
40 };
41
42 timer@51000000 {
43 compatible = "samsung,s3c2410-pwm";
44 reg = <0x51000000 0x1000>;
45 interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>;
46 #pwm-cells = <4>;
47 };
48
49 serial@50000000 {
50 compatible = "samsung,s3c2410-uart";
51 reg = <0x50000000 0x4000>;
52 interrupts = <1 28 0 4>, <1 28 1 4>;
53 status = "disabled";
54 };
55
56 serial@50004000 {
57 compatible = "samsung,s3c2410-uart";
58 reg = <0x50004000 0x4000>;
59 interrupts = <1 23 3 4>, <1 23 4 4>;
60 status = "disabled";
61 };
62
63 serial@50008000 {
64 compatible = "samsung,s3c2410-uart";
65 reg = <0x50008000 0x4000>;
66 interrupts = <1 15 6 4>, <1 15 7 4>;
67 status = "disabled";
68 };
69
70 watchdog@53000000 {
71 compatible = "samsung,s3c2410-wdt";
72 reg = <0x53000000 0x100>;
73 interrupts = <0 0 9 3>;
74 status = "disabled";
75 };
76
77 rtc@57000000 {
78 compatible = "samsung,s3c2410-rtc";
79 reg = <0x57000000 0x100>;
80 interrupts = <0 0 30 3>, <0 0 8 3>;
81 status = "disabled";
82 };
83
84 i2c@54000000 {
85 compatible = "samsung,s3c2410-i2c";
86 reg = <0x54000000 0x100>;
87 interrupts = <0 0 27 3>;
88 #address-cells = <1>;
89 #size-cells = <0>;
90 status = "disabled";
91 };
92};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index ff18fc2ea46f..5ae41ecb0a02 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -71,6 +71,16 @@ config SOC_EXYNOS5250
71 help 71 help
72 Enable EXYNOS5250 SoC support 72 Enable EXYNOS5250 SoC support
73 73
74config SOC_EXYNOS5420
75 bool "SAMSUNG EXYNOS5420"
76 default y
77 depends on ARCH_EXYNOS5
78 select PM_GENERIC_DOMAINS if PM
79 select S5P_PM if PM
80 select S5P_SLEEP if PM
81 help
82 Enable EXYNOS5420 SoC support
83
74config SOC_EXYNOS5440 84config SOC_EXYNOS5440
75 bool "SAMSUNG EXYNOS5440" 85 bool "SAMSUNG EXYNOS5440"
76 default y 86 default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f7e504b7874d..8bc587cb165a 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -64,6 +64,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
64static const char name_exynos4212[] = "EXYNOS4212"; 64static const char name_exynos4212[] = "EXYNOS4212";
65static const char name_exynos4412[] = "EXYNOS4412"; 65static const char name_exynos4412[] = "EXYNOS4412";
66static const char name_exynos5250[] = "EXYNOS5250"; 66static const char name_exynos5250[] = "EXYNOS5250";
67static const char name_exynos5420[] = "EXYNOS5420";
67static const char name_exynos5440[] = "EXYNOS5440"; 68static const char name_exynos5440[] = "EXYNOS5440";
68 69
69static void exynos4_map_io(void); 70static void exynos4_map_io(void);
@@ -103,6 +104,12 @@ static struct cpu_table cpu_ids[] __initdata = {
103 .init = exynos_init, 104 .init = exynos_init,
104 .name = name_exynos5250, 105 .name = name_exynos5250,
105 }, { 106 }, {
107 .idcode = EXYNOS5420_SOC_ID,
108 .idmask = EXYNOS5_SOC_MASK,
109 .map_io = exynos5_map_io,
110 .init = exynos_init,
111 .name = name_exynos5420,
112 }, {
106 .idcode = EXYNOS5440_SOC_ID, 113 .idcode = EXYNOS5440_SOC_ID,
107 .idmask = EXYNOS5_SOC_MASK, 114 .idmask = EXYNOS5_SOC_MASK,
108 .map_io = exynos5440_map_io, 115 .map_io = exynos5440_map_io,
@@ -322,10 +329,10 @@ void exynos5_restart(char mode, const char *cmd)
322 u32 val; 329 u32 val;
323 void __iomem *addr; 330 void __iomem *addr;
324 331
325 if (of_machine_is_compatible("samsung,exynos5250")) { 332 val = 0x1;
326 val = 0x1; 333 addr = EXYNOS_SWRESET;
327 addr = EXYNOS_SWRESET; 334
328 } else if (of_machine_is_compatible("samsung,exynos5440")) { 335 if (of_machine_is_compatible("samsung,exynos5440")) {
329 u32 status; 336 u32 status;
330 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); 337 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
331 338
@@ -336,9 +343,6 @@ void exynos5_restart(char mode, const char *cmd)
336 val = __raw_readl(addr); 343 val = __raw_readl(addr);
337 344
338 val = (val & 0xffff0000) | (status & 0xffff); 345 val = (val & 0xffff0000) | (status & 0xffff);
339 } else {
340 pr_err("%s: cannot support non-DT\n", __func__);
341 return;
342 } 346 }
343 347
344 __raw_writel(val, addr); 348 __raw_writel(val, addr);
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 2979995d5a6a..1937e0fb7375 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -31,13 +31,12 @@ static void arch_detect_cpu(void)
31 31
32 /* 32 /*
33 * product_id is bits 31:12 33 * product_id is bits 31:12
34 * bits 23:20 describe the exynosX family 34 * bits 23:20 describe the exynosX family
35 * 35 * bits 27:24 describe the exynosX family in exynos5420
36 */ 36 */
37 chip_id >>= 20; 37 chip_id >>= 20;
38 chip_id &= 0xf;
39 38
40 if (chip_id == 0x5) 39 if ((chip_id & 0x0f) == 0x5 || (chip_id & 0xf0) == 0x50)
41 uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); 40 uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
42 else 41 else
43 uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); 42 uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 753b94f3fca7..050a5b1247ef 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -57,6 +57,7 @@ static void __init exynos5_dt_machine_init(void)
57 57
58static char const *exynos5_dt_compat[] __initdata = { 58static char const *exynos5_dt_compat[] __initdata = {
59 "samsung,exynos5250", 59 "samsung,exynos5250",
60 "samsung,exynos5420",
60 "samsung,exynos5440", 61 "samsung,exynos5440",
61 NULL 62 NULL
62}; 63};
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a0e8ff7758a4..b2e8a5ebad40 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -50,6 +50,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
50 boot_reg = cpu_boot_reg_base(); 50 boot_reg = cpu_boot_reg_base();
51 if (soc_is_exynos4412()) 51 if (soc_is_exynos4412())
52 boot_reg += 4*cpu; 52 boot_reg += 4*cpu;
53 else if (soc_is_exynos5420())
54 boot_reg += 4;
53 return boot_reg; 55 return boot_reg;
54} 56}
55 57
@@ -180,10 +182,14 @@ static void __init exynos_smp_init_cpus(void)
180 void __iomem *scu_base = scu_base_addr(); 182 void __iomem *scu_base = scu_base_addr();
181 unsigned int i, ncores; 183 unsigned int i, ncores;
182 184
183 if (soc_is_exynos5250()) 185 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
184 ncores = 2;
185 else
186 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 186 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
187 else
188 /*
189 * CPU Nodes are passed thru DT and set_cpu_possible
190 * is set by "arm_dt_init_cpu_maps".
191 */
192 return;
187 193
188 /* sanity check */ 194 /* sanity check */
189 if (ncores > nr_cpu_ids) { 195 if (ncores > nr_cpu_ids) {
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index f2f7088bfd22..e52d5e42af4e 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -490,6 +490,18 @@ config MACH_SMDK2416
490 help 490 help
491 Say Y here if you are using an SMDK2416 491 Say Y here if you are using an SMDK2416
492 492
493config MACH_S3C2416_DT
494 bool "Samsung S3C2416 machine using devicetree"
495 select CLKSRC_OF
496 select USE_OF
497 select PINCTRL
498 select PINCTRL_S3C24XX
499 help
500 Machine support for Samsung S3C2416 machines with device tree enabled.
501 Select this if a fdt blob is available for the S3C2416 SoC based board.
502 Note: This is under development and not all peripherals can be supported
503 with this machine file.
504
493endif # CPU_S3C2416 505endif # CPU_S3C2416
494 506
495if CPU_S3C2440 507if CPU_S3C2440
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 6f46ecfc8396..6de730bada4d 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -85,6 +85,7 @@ obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o
85obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o 85obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o
86 86
87obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o 87obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o
88obj-$(CONFIG_MACH_S3C2416_DT) += mach-s3c2416-dt.o
88 89
89obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o 90obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
90obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o 91obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
new file mode 100644
index 000000000000..f50454a34f72
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -0,0 +1,91 @@
1/*
2 * Samsung's S3C2416 flattened device tree enabled machine
3 *
4 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
5 *
6 * based on mach-exynos/mach-exynos4-dt.c
7 *
8 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2010-2011 Linaro Ltd.
11 * www.linaro.org
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#include <linux/clocksource.h>
19#include <linux/irqchip.h>
20#include <linux/of_platform.h>
21#include <linux/serial_core.h>
22
23#include <asm/mach/arch.h>
24#include <mach/map.h>
25
26#include <plat/cpu.h>
27#include <plat/pm.h>
28#include <plat/regs-serial.h>
29
30#include "common.h"
31
32/*
33 * The following lookup table is used to override device names when devices
34 * are registered from device tree. This is temporarily added to enable
35 * device tree support addition for the S3C2416 architecture.
36 *
37 * For drivers that require platform data to be provided from the machine
38 * file, a platform data pointer can also be supplied along with the
39 * devices names. Usually, the platform data elements that cannot be parsed
40 * from the device tree by the drivers (example: function pointers) are
41 * supplied. But it should be noted that this is a temporary mechanism and
42 * at some point, the drivers should be capable of parsing all the platform
43 * data from the device tree.
44 */
45static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = {
46 OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART,
47 "s3c2440-uart.0", NULL),
48 OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000,
49 "s3c2440-uart.1", NULL),
50 OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000,
51 "s3c2440-uart.2", NULL),
52 OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000,
53 "s3c2440-uart.3", NULL),
54 OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0,
55 "s3c-sdhci.0", NULL),
56 OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1,
57 "s3c-sdhci.1", NULL),
58 OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC,
59 "s3c2440-i2c.0", NULL),
60 {},
61};
62
63static void __init s3c2416_dt_map_io(void)
64{
65 s3c24xx_init_io(NULL, 0);
66 s3c24xx_init_clocks(12000000);
67}
68
69static void __init s3c2416_dt_machine_init(void)
70{
71 of_platform_populate(NULL, of_default_bus_match_table,
72 s3c2416_auxdata_lookup, NULL);
73
74 s3c_pm_init();
75}
76
77static char const *s3c2416_dt_compat[] __initdata = {
78 "samsung,s3c2416",
79 "samsung,s3c2450",
80 NULL
81};
82
83DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
84 /* Maintainer: Heiko Stuebner <heiko@sntech.de> */
85 .dt_compat = s3c2416_dt_compat,
86 .map_io = s3c2416_dt_map_io,
87 .init_irq = irqchip_init,
88 .init_machine = s3c2416_dt_machine_init,
89 .init_time = clocksource_of_init,
90 .restart = s3c2416_restart,
91MACHINE_END
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 989fefe18be6..4fb1f03a10d1 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
46#define EXYNOS4_CPU_MASK 0xFFFE0000 46#define EXYNOS4_CPU_MASK 0xFFFE0000
47 47
48#define EXYNOS5250_SOC_ID 0x43520000 48#define EXYNOS5250_SOC_ID 0x43520000
49#define EXYNOS5420_SOC_ID 0xE5420000
49#define EXYNOS5440_SOC_ID 0xE5440000 50#define EXYNOS5440_SOC_ID 0xE5440000
50#define EXYNOS5_SOC_MASK 0xFFFFF000 51#define EXYNOS5_SOC_MASK 0xFFFFF000
51 52
@@ -67,6 +68,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
67IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) 68IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
68IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) 69IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
69IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) 70IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
71IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
70IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK) 72IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
71 73
72#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 74#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
@@ -142,6 +144,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
142# define soc_is_exynos5250() 0 144# define soc_is_exynos5250() 0
143#endif 145#endif
144 146
147#if defined(CONFIG_SOC_EXYNOS5420)
148# define soc_is_exynos5420() is_samsung_exynos5420()
149#else
150# define soc_is_exynos5420() 0
151#endif
152
145#if defined(CONFIG_SOC_EXYNOS5440) 153#if defined(CONFIG_SOC_EXYNOS5440)
146# define soc_is_exynos5440() is_samsung_exynos5440() 154# define soc_is_exynos5440() is_samsung_exynos5440()
147#else 155#else
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e67425..5d4d432cc4ac 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,4 +5,6 @@
5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o 5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o 6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o 7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
8obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
8obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 9obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
10obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
new file mode 100644
index 000000000000..9b1bbd52fd1f
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -0,0 +1,133 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Padmavathi Venna <padma.v@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Audio Subsystem Clock Controller.
10*/
11
12#include <linux/clkdev.h>
13#include <linux/io.h>
14#include <linux/clk-provider.h>
15#include <linux/of_address.h>
16#include <linux/syscore_ops.h>
17
18#include <dt-bindings/clk/exynos-audss-clk.h>
19
20static DEFINE_SPINLOCK(lock);
21static struct clk **clk_table;
22static void __iomem *reg_base;
23static struct clk_onecell_data clk_data;
24
25#define ASS_CLK_SRC 0x0
26#define ASS_CLK_DIV 0x4
27#define ASS_CLK_GATE 0x8
28
29static unsigned long reg_save[][2] = {
30 {ASS_CLK_SRC, 0},
31 {ASS_CLK_DIV, 0},
32 {ASS_CLK_GATE, 0},
33};
34
35/* list of all parent clock list */
36static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
37static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
38
39#ifdef CONFIG_PM_SLEEP
40static int exynos_audss_clk_suspend(void)
41{
42 int i;
43
44 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
45 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
46
47 return 0;
48}
49
50static void exynos_audss_clk_resume(void)
51{
52 int i;
53
54 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
55 writel(reg_save[i][1], reg_base + reg_save[i][0]);
56}
57
58static struct syscore_ops exynos_audss_clk_syscore_ops = {
59 .suspend = exynos_audss_clk_suspend,
60 .resume = exynos_audss_clk_resume,
61};
62#endif /* CONFIG_PM_SLEEP */
63
64/* register exynos_audss clocks */
65void __init exynos_audss_clk_init(struct device_node *np)
66{
67 reg_base = of_iomap(np, 0);
68 if (!reg_base) {
69 pr_err("%s: failed to map audss registers\n", __func__);
70 return;
71 }
72
73 clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
74 GFP_KERNEL);
75 if (!clk_table) {
76 pr_err("%s: could not allocate clk lookup table\n", __func__);
77 return;
78 }
79
80 clk_data.clks = clk_table;
81 clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
82 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
83
84 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
85 mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
86 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
87
88 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
89 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
90 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
91
92 clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
93 "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
94 0, &lock);
95
96 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
97 "dout_aud_bus", "dout_srp", 0,
98 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
99
100 clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
101 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
102 &lock);
103
104 clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
105 "dout_srp", CLK_SET_RATE_PARENT,
106 reg_base + ASS_CLK_GATE, 0, 0, &lock);
107
108 clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
109 "dout_aud_bus", CLK_SET_RATE_PARENT,
110 reg_base + ASS_CLK_GATE, 2, 0, &lock);
111
112 clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
113 "dout_i2s", CLK_SET_RATE_PARENT,
114 reg_base + ASS_CLK_GATE, 3, 0, &lock);
115
116 clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
117 "sclk_pcm", CLK_SET_RATE_PARENT,
118 reg_base + ASS_CLK_GATE, 4, 0, &lock);
119
120 clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
121 "div_pcm0", CLK_SET_RATE_PARENT,
122 reg_base + ASS_CLK_GATE, 5, 0, &lock);
123
124#ifdef CONFIG_PM_SLEEP
125 register_syscore_ops(&exynos_audss_clk_syscore_ops);
126#endif
127
128 pr_info("Exynos: Audss: clock setup completed\n");
129}
130CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
131 exynos_audss_clk_init);
132CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
133 exynos_audss_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 3c1f88868f29..addc738a06fb 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -151,7 +151,7 @@ enum exynos4_clks {
151 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, 151 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
152 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, 152 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
153 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, 153 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
154 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, 154 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
155 155
156 /* gate clocks */ 156 /* gate clocks */
157 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, 157 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -484,6 +484,9 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
484 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 484 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
485 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 485 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
486 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 486 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
487 MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
488 MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
489 MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
487}; 490};
488 491
489/* list of divider clocks supported in all exynos4 soc's */ 492/* list of divider clocks supported in all exynos4 soc's */
@@ -552,7 +555,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
552/* list of divider clocks supported in exynos4210 soc */ 555/* list of divider clocks supported in exynos4210 soc */
553struct samsung_div_clock exynos4210_div_clks[] __initdata = { 556struct samsung_div_clock exynos4210_div_clks[] __initdata = {
554 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), 557 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
555 DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4), 558 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
556 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), 559 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
557 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), 560 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
558 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 561 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
@@ -582,6 +585,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
582 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 585 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
583 DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3), 586 DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
584 DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3), 587 DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
588 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
585}; 589};
586 590
587/* list of gate clocks supported in all exynos4 soc's */ 591/* list of gate clocks supported in all exynos4 soc's */
@@ -909,6 +913,7 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
909 CLK_IGNORE_UNUSED, 0), 913 CLK_IGNORE_UNUSED, 0),
910 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 914 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
911 CLK_IGNORE_UNUSED, 0), 915 CLK_IGNORE_UNUSED, 0),
916 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
912}; 917};
913 918
914/* 919/*
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75924a8..7c6885058cef 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -87,6 +87,7 @@ enum exynos5250_clks {
87 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3, 87 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
88 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm, 88 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
89 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, 89 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
90 div_i2s1, div_i2s2,
90 91
91 /* gate clocks */ 92 /* gate clocks */
92 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0, 93 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
291 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8), 292 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
292 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4), 293 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
293 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8), 294 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
294 DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6), 295 DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
295 DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), 296 DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
296 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4), 297 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
297 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"), 298 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
298 DIV_F(none, "div_mipi1_pre", "div_mipi1", 299 DIV_F(none, "div_mipi1_pre", "div_mipi1",
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
new file mode 100644
index 000000000000..68a96cbd4936
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -0,0 +1,762 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Authors: Thomas Abraham <thomas.ab@samsung.com>
4 * Chander Kashyap <k.chander@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5420 SoC.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include "clk.h"
20#include "clk-pll.h"
21
22#define SRC_CPU 0x200
23#define DIV_CPU0 0x500
24#define DIV_CPU1 0x504
25#define GATE_BUS_CPU 0x700
26#define GATE_SCLK_CPU 0x800
27#define SRC_TOP0 0x10200
28#define SRC_TOP1 0x10204
29#define SRC_TOP2 0x10208
30#define SRC_TOP3 0x1020c
31#define SRC_TOP4 0x10210
32#define SRC_TOP5 0x10214
33#define SRC_TOP6 0x10218
34#define SRC_TOP7 0x1021c
35#define SRC_DISP10 0x1022c
36#define SRC_MAU 0x10240
37#define SRC_FSYS 0x10244
38#define SRC_PERIC0 0x10250
39#define SRC_PERIC1 0x10254
40#define SRC_TOP10 0x10280
41#define SRC_TOP11 0x10284
42#define SRC_TOP12 0x10288
43#define SRC_MASK_DISP10 0x1032c
44#define SRC_MASK_FSYS 0x10340
45#define SRC_MASK_PERIC0 0x10350
46#define SRC_MASK_PERIC1 0x10354
47#define DIV_TOP0 0x10500
48#define DIV_TOP1 0x10504
49#define DIV_TOP2 0x10508
50#define DIV_DISP10 0x1052c
51#define DIV_MAU 0x10544
52#define DIV_FSYS0 0x10548
53#define DIV_FSYS1 0x1054c
54#define DIV_FSYS2 0x10550
55#define DIV_PERIC0 0x10558
56#define DIV_PERIC1 0x1055c
57#define DIV_PERIC2 0x10560
58#define DIV_PERIC3 0x10564
59#define DIV_PERIC4 0x10568
60#define GATE_BUS_TOP 0x10700
61#define GATE_BUS_FSYS0 0x10740
62#define GATE_BUS_PERIC 0x10750
63#define GATE_BUS_PERIC1 0x10754
64#define GATE_BUS_PERIS0 0x10760
65#define GATE_BUS_PERIS1 0x10764
66#define GATE_IP_GSCL0 0x10910
67#define GATE_IP_GSCL1 0x10920
68#define GATE_IP_MFC 0x1092c
69#define GATE_IP_DISP1 0x10928
70#define GATE_IP_G3D 0x10930
71#define GATE_IP_GEN 0x10934
72#define GATE_IP_MSCL 0x10970
73#define GATE_TOP_SCLK_GSCL 0x10820
74#define GATE_TOP_SCLK_DISP1 0x10828
75#define GATE_TOP_SCLK_MAU 0x1083c
76#define GATE_TOP_SCLK_FSYS 0x10840
77#define GATE_TOP_SCLK_PERIC 0x10850
78#define SRC_CDREX 0x20200
79#define SRC_KFC 0x28200
80#define DIV_KFC0 0x28500
81
82enum exynos5420_clks {
83 none,
84
85 /* core clocks */
86 fin_pll,
87
88 /* gate for special clocks (sclk) */
89 sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
90 sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
91 sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
92 sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
93 sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
94 sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
95
96 /* gate clocks */
97 aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
98 i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
99 i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
100 chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
101 tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
102 pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
103 aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
104 aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
105 smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
106 aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
107 smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
108 smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
109 aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
110 gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
111 aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
112 smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
113
114 nr_clks,
115};
116
117/*
118 * list of controller registers to be saved and restored during a
119 * suspend/resume cycle.
120 */
121static __initdata unsigned long exynos5420_clk_regs[] = {
122 SRC_CPU,
123 DIV_CPU0,
124 DIV_CPU1,
125 GATE_BUS_CPU,
126 GATE_SCLK_CPU,
127 SRC_TOP0,
128 SRC_TOP1,
129 SRC_TOP2,
130 SRC_TOP3,
131 SRC_TOP4,
132 SRC_TOP5,
133 SRC_TOP6,
134 SRC_TOP7,
135 SRC_DISP10,
136 SRC_MAU,
137 SRC_FSYS,
138 SRC_PERIC0,
139 SRC_PERIC1,
140 SRC_TOP10,
141 SRC_TOP11,
142 SRC_TOP12,
143 SRC_MASK_DISP10,
144 SRC_MASK_FSYS,
145 SRC_MASK_PERIC0,
146 SRC_MASK_PERIC1,
147 DIV_TOP0,
148 DIV_TOP1,
149 DIV_TOP2,
150 DIV_DISP10,
151 DIV_MAU,
152 DIV_FSYS0,
153 DIV_FSYS1,
154 DIV_FSYS2,
155 DIV_PERIC0,
156 DIV_PERIC1,
157 DIV_PERIC2,
158 DIV_PERIC3,
159 DIV_PERIC4,
160 GATE_BUS_TOP,
161 GATE_BUS_FSYS0,
162 GATE_BUS_PERIC,
163 GATE_BUS_PERIC1,
164 GATE_BUS_PERIS0,
165 GATE_BUS_PERIS1,
166 GATE_IP_GSCL0,
167 GATE_IP_GSCL1,
168 GATE_IP_MFC,
169 GATE_IP_DISP1,
170 GATE_IP_G3D,
171 GATE_IP_GEN,
172 GATE_IP_MSCL,
173 GATE_TOP_SCLK_GSCL,
174 GATE_TOP_SCLK_DISP1,
175 GATE_TOP_SCLK_MAU,
176 GATE_TOP_SCLK_FSYS,
177 GATE_TOP_SCLK_PERIC,
178 SRC_CDREX,
179 SRC_KFC,
180 DIV_KFC0,
181};
182
183/* list of all parent clocks */
184PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll",
185 "sclk_mpll", "sclk_spll" };
186PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" };
187PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" };
188PNAME(apll_p) = { "fin_pll", "fout_apll", };
189PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
190PNAME(cpll_p) = { "fin_pll", "fout_cpll", };
191PNAME(dpll_p) = { "fin_pll", "fout_dpll", };
192PNAME(epll_p) = { "fin_pll", "fout_epll", };
193PNAME(ipll_p) = { "fin_pll", "fout_ipll", };
194PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
195PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
196PNAME(rpll_p) = { "fin_pll", "fout_rpll", };
197PNAME(spll_p) = { "fin_pll", "fout_spll", };
198PNAME(vpll_p) = { "fin_pll", "fout_vpll", };
199
200PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" };
201PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
202 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
203PNAME(group3_p) = { "sclk_rpll", "sclk_spll" };
204PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" };
205PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" };
206
207PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" };
208PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" };
209
210PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"};
211PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" };
212
213PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"};
214PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" };
215
216PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"};
217PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" };
218
219PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"};
220PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" };
221
222PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"};
223PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" };
224
225PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"};
226PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" };
227
228PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"};
229PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" };
230
231PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"};
232PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" };
233
234PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"};
235PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" };
236
237PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"};
238PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" };
239
240PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"};
241PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" };
242
243PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"};
244PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" };
245
246PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"};
247PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" };
248
249PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"};
250PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" };
251
252PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll",
253 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
254PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll",
255 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
256PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
257 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
258PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
259 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
260PNAME(hdmi_p) = { "sclk_hdmiphy", "dout_hdmi_pixel" };
261PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
262 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
263
264/* fixed rate clocks generated outside the soc */
265struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
266 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
267};
268
269/* fixed rate clocks generated inside the soc */
270struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
271 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
272 FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
273 FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
274 FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
275 FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
276};
277
278struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
279 FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
280};
281
282struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
283 MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
284 MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
285 MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1),
286 MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
287 MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
288 MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
289
290 MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
291
292 MUX_A(none, "mout_aclk400_mscl", group1_p,
293 SRC_TOP0, 4, 2, "aclk400_mscl"),
294 MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
295 MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
296 MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
297
298 MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
299 MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
300 MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
301 MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
302 MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
303
304 MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
305 MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
306 MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
307 MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
308 MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
309 MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
310
311 MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
312 SRC_TOP3, 4, 1),
313 MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p,
314 SRC_TOP3, 8, 1, "aclk200_disp1"),
315 MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
316 SRC_TOP3, 12, 1),
317 MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
318 SRC_TOP3, 28, 1),
319
320 MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
321 SRC_TOP4, 0, 1),
322 MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
323 MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
324 MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
325 MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
326
327 MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
328 MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
329 MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
330 MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p,
331 SRC_TOP5, 16, 1, "aclkg3d"),
332 MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
333 SRC_TOP5, 20, 1),
334 MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
335 SRC_TOP5, 24, 1),
336 MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
337 SRC_TOP5, 28, 1),
338
339 MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
340 MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
341 MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
342 MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
343 MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
344 MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
345 MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
346 MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
347
348 MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
349 MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
350 MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
351 SRC_TOP10, 12, 1),
352 MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
353
354 MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
355 SRC_TOP11, 0, 1),
356 MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
357 MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
358 MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
359 MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
360
361 MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
362 MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
363 MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
364 MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
365 MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
366 SRC_TOP12, 24, 1),
367 MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
368
369 /* DISP1 Block */
370 MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
371 MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
372 MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
373 MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
374 MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
375
376 /* MAU Block */
377 MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
378
379 /* FSYS Block */
380 MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
381 MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
382 MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
383 MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
384 MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
385 MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
386
387 /* PERIC Block */
388 MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
389 MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
390 MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
391 MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
392 MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
393 MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
394 MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
395 MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
396 MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
397 MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
398 MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
399 MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
400};
401
402struct samsung_div_clock exynos5420_div_clks[] __initdata = {
403 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
404 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
405 DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3),
406 DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
407 DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
408
409 DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
410 DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
411 DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
412 DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
413 DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
414
415 DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
416 DIV_TOP1, 0, 3),
417 DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
418 DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
419 DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
420 DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
421
422 DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
423 DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
424 DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
425 DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
426 DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1",
427 DIV_TOP2, 24, 3, "aclk300_disp1"),
428 DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
429
430 /* DISP1 Block */
431 DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
432 DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
433 DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
434 DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
435
436 /* Audio Block */
437 DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
438 DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
439
440 /* USB3.0 */
441 DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
442 DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
443 DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
444 DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
445
446 /* MMC */
447 DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
448 DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
449 DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
450
451 DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
452
453 /* UART and PWM */
454 DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
455 DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
456 DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
457 DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
458 DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
459
460 /* SPI */
461 DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
462 DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
463 DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
464
465 /* PCM */
466 DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
467 DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
468
469 /* Audio - I2S */
470 DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
471 DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
472 DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
473 DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
474 DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
475
476 /* SPI Pre-Ratio */
477 DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
478 DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
479 DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
480};
481
482struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
483 /* TODO: Re-verify the CG bits for all the gate clocks */
484 GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"),
485
486 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
487 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
488 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
489 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
490
491 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
492 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
493 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
494 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
495 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
496 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
497 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
498 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
499 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
500 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
501 GATE(0, "pclk66_gpio", "mout_sw_aclk66",
502 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
503 GATE(0, "aclk66_psgen", "mout_aclk66_psgen",
504 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
505 GATE(0, "aclk66_peric", "mout_aclk66_peric",
506 GATE_BUS_TOP, 11, 0, 0),
507 GATE(0, "aclk166", "mout_user_aclk166",
508 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
509 GATE(0, "aclk333", "mout_aclk333",
510 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
511
512 /* sclk */
513 GATE(sclk_uart0, "sclk_uart0", "dout_uart0",
514 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
515 GATE(sclk_uart1, "sclk_uart1", "dout_uart1",
516 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
517 GATE(sclk_uart2, "sclk_uart2", "dout_uart2",
518 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
519 GATE(sclk_uart3, "sclk_uart3", "dout_uart3",
520 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
521 GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0",
522 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
523 GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1",
524 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
525 GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2",
526 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
527 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
528 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
529 GATE(sclk_pwm, "sclk_pwm", "dout_pwm",
530 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
531 GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1",
532 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
533 GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2",
534 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
535 GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1",
536 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
537 GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2",
538 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
539
540 GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0",
541 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
542 GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1",
543 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
544 GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2",
545 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
546 GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301",
547 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
548 GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300",
549 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
550 GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300",
551 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
552 GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301",
553 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
554
555 GATE(sclk_usbd301, "sclk_unipro", "dout_unipro",
556 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
557
558 GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl",
559 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
560 GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl",
561 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
562
563 /* Display */
564 GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1",
565 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
566 GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1",
567 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
568 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
569 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
570 GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel",
571 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
572 GATE(sclk_dp1, "sclk_dp1", "dout_dp1",
573 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
574
575 /* Maudio Block */
576 GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0",
577 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
578 GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0",
579 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
580 /* FSYS */
581 GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
582 GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
583 GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
584 GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
585 GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
586 GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
587 GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
588 GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
589 GATE(sromc, "sromc", "aclk200_fsys2",
590 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
591 GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
592 GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
593 GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
594
595 /* UART */
596 GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
597 GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
598 GATE_A(uart2, "uart2", "aclk66_peric",
599 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
600 GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
601 /* I2C */
602 GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
603 GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
604 GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
605 GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
606 GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
607 GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
608 GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
609 GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
610 GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0),
611 GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
612 /* SPI */
613 GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
614 GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
615 GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
616 GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
617 /* I2S */
618 GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
619 GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
620 /* PCM */
621 GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
622 GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
623 /* PWM */
624 GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
625 /* SPDIF */
626 GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
627
628 GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
629 GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
630 GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
631
632 GATE(chipid, "chipid", "aclk66_psgen",
633 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
634 GATE(sysreg, "sysreg", "aclk66_psgen",
635 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
636 GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
637 GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
638 GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
639 GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
640 GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
641 GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
642 GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
643 GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
644 GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
645 GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
646
647 GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0),
648 GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
649 GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
650 GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
651 GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
652 GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
653
654 GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
655 GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
656 GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
657
658 GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0),
659 GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl",
660 GATE_IP_GSCL1, 3, 0, 0),
661 GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl",
662 GATE_IP_GSCL1, 4, 0, 0),
663 GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0),
664 GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0),
665 GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
666 GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
667 GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl",
668 GATE_IP_GSCL1, 16, 0, 0),
669 GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl",
670 GATE_IP_GSCL1, 17, 0, 0),
671
672 GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
673 GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
674 GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
675 GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
676 GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
677 GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0),
678
679 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
680 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
681 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
682
683 GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
684
685 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
686 GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
687 GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
688 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
689 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
690 GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
691 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
692
693 GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
694 GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
695 GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
696 GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
697 GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
698 GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
699};
700
701static __initdata struct of_device_id ext_clk_match[] = {
702 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
703 { },
704};
705
706/* register exynos5420 clocks */
707void __init exynos5420_clk_init(struct device_node *np)
708{
709 void __iomem *reg_base;
710 struct clk *apll, *bpll, *cpll, *dpll, *epll, *ipll, *kpll, *mpll;
711 struct clk *rpll, *spll, *vpll;
712
713 if (np) {
714 reg_base = of_iomap(np, 0);
715 if (!reg_base)
716 panic("%s: failed to map registers\n", __func__);
717 } else {
718 panic("%s: unable to determine soc\n", __func__);
719 }
720
721 samsung_clk_init(np, reg_base, nr_clks,
722 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs),
723 NULL, 0);
724 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
725 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
726 ext_clk_match);
727
728 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
729 reg_base + 0x100);
730 bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
731 reg_base + 0x20110);
732 cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
733 reg_base + 0x10120);
734 dpll = samsung_clk_register_pll35xx("fout_dpll", "fin_pll",
735 reg_base + 0x10128);
736 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
737 reg_base + 0x10130);
738 ipll = samsung_clk_register_pll35xx("fout_ipll", "fin_pll",
739 reg_base + 0x10150);
740 kpll = samsung_clk_register_pll35xx("fout_kpll", "fin_pll",
741 reg_base + 0x28100);
742 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
743 reg_base + 0x10180);
744 rpll = samsung_clk_register_pll36xx("fout_rpll", "fin_pll",
745 reg_base + 0x10140);
746 spll = samsung_clk_register_pll35xx("fout_spll", "fin_pll",
747 reg_base + 0x10160);
748 vpll = samsung_clk_register_pll35xx("fout_vpll", "fin_pll",
749 reg_base + 0x10170);
750
751 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
752 ARRAY_SIZE(exynos5420_fixed_rate_clks));
753 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
754 ARRAY_SIZE(exynos5420_fixed_factor_clks));
755 samsung_clk_register_mux(exynos5420_mux_clks,
756 ARRAY_SIZE(exynos5420_mux_clks));
757 samsung_clk_register_div(exynos5420_div_clks,
758 ARRAY_SIZE(exynos5420_div_clks));
759 samsung_clk_register_gate(exynos5420_gate_clks,
760 ARRAY_SIZE(exynos5420_gate_clks));
761}
762CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 662fcc065821..a70480409ea5 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -400,18 +400,6 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
400 return IRQ_HANDLED; 400 return IRQ_HANDLED;
401} 401}
402 402
403static struct irqaction mct_tick0_event_irq = {
404 .name = "mct_tick0_irq",
405 .flags = IRQF_TIMER | IRQF_NOBALANCING,
406 .handler = exynos4_mct_tick_isr,
407};
408
409static struct irqaction mct_tick1_event_irq = {
410 .name = "mct_tick1_irq",
411 .flags = IRQF_TIMER | IRQF_NOBALANCING,
412 .handler = exynos4_mct_tick_isr,
413};
414
415static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) 403static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
416{ 404{
417 struct mct_clock_event_device *mevt; 405 struct mct_clock_event_device *mevt;
@@ -435,16 +423,15 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
435 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); 423 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
436 424
437 if (mct_int_type == MCT_INT_SPI) { 425 if (mct_int_type == MCT_INT_SPI) {
438 if (cpu == 0) { 426 evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
439 mct_tick0_event_irq.dev_id = mevt; 427 if (request_irq(evt->irq, exynos4_mct_tick_isr,
440 evt->irq = mct_irqs[MCT_L0_IRQ]; 428 IRQF_TIMER | IRQF_NOBALANCING,
441 setup_irq(evt->irq, &mct_tick0_event_irq); 429 evt->name, mevt)) {
442 } else { 430 pr_err("exynos-mct: cannot register IRQ %d\n",
443 mct_tick1_event_irq.dev_id = mevt; 431 evt->irq);
444 evt->irq = mct_irqs[MCT_L1_IRQ]; 432 return -EIO;
445 setup_irq(evt->irq, &mct_tick1_event_irq);
446 irq_set_affinity(evt->irq, cpumask_of(1));
447 } 433 }
434 irq_set_affinity(evt->irq, cpumask_of(cpu));
448 } else { 435 } else {
449 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); 436 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
450 } 437 }
@@ -454,13 +441,9 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
454 441
455static void exynos4_local_timer_stop(struct clock_event_device *evt) 442static void exynos4_local_timer_stop(struct clock_event_device *evt)
456{ 443{
457 unsigned int cpu = smp_processor_id();
458 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); 444 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
459 if (mct_int_type == MCT_INT_SPI) 445 if (mct_int_type == MCT_INT_SPI)
460 if (cpu == 0) 446 free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
461 remove_irq(evt->irq, &mct_tick0_event_irq);
462 else
463 remove_irq(evt->irq, &mct_tick1_event_irq);
464 else 447 else
465 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); 448 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
466} 449}
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 0c8a9fa2be6c..94a91c2b7ca0 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1713,9 +1713,7 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1713#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL 1713#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1714#endif 1714#endif
1715 1715
1716#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \ 1716#if defined(CONFIG_ARCH_EXYNOS)
1717 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1718 defined(CONFIG_SOC_EXYNOS5440)
1719static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { 1717static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1720 .info = &(struct s3c24xx_uart_info) { 1718 .info = &(struct s3c24xx_uart_info) {
1721 .name = "Samsung Exynos4 UART", 1719 .name = "Samsung Exynos4 UART",
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
new file mode 100644
index 000000000000..8279f427c60f
--- /dev/null
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -0,0 +1,25 @@
1/*
2 * This header provides constants for Samsung audio subsystem
3 * clock controller.
4 *
5 * The constants defined in this header are being used in dts
6 * and exynos audss driver.
7 */
8
9#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
10#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
11
12#define EXYNOS_MOUT_AUDSS 0
13#define EXYNOS_MOUT_I2S 1
14#define EXYNOS_DOUT_SRP 2
15#define EXYNOS_DOUT_AUD_BUS 3
16#define EXYNOS_DOUT_I2S 4
17#define EXYNOS_SRP_CLK 5
18#define EXYNOS_I2S_BUS 6
19#define EXYNOS_SCLK_I2S 7
20#define EXYNOS_PCM_BUS 8
21#define EXYNOS_SCLK_PCM 9
22
23#define EXYNOS_AUDSS_MAX_CLKS 10
24
25#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 07:11:21 -0500