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-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c1
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c3
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c3
-rw-r--r--arch/arm/mach-omap2/board-flash.c3
-rw-r--r--arch/arm/mach-omap2/board-flash.h1
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c2
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c3
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c3
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.h27
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c3
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.h24
-rw-r--r--arch/arm/mach-omap2/gpmc.c63
-rw-r--r--arch/arm/mach-omap2/gpmc.h227
-rw-r--r--arch/arm/mach-omap2/pm34xx.c2
-rw-r--r--include/linux/omap-gpmc.h199
16 files changed, 271 insertions, 295 deletions
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 212c3160de18..8168ddabaeda 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -24,6 +24,7 @@
24#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h> 25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
27#include <linux/omap-gpmc.h>
27 28
28#include <asm/mach-types.h> 29#include <asm/mach-types.h>
29#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index c6df8eec4553..91738a14ecbe 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -25,6 +25,7 @@
25#include <linux/input/matrix_keypad.h> 25#include <linux/input/matrix_keypad.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/omap-gpmc.h>
28#include <linux/platform_data/gpio-omap.h> 29#include <linux/platform_data/gpio-omap.h>
29 30
30#include <linux/platform_data/at24.h> 31#include <linux/platform_data/at24.h>
@@ -51,8 +52,6 @@
51#include "sdram-micron-mt46h32m32lf-6.h" 52#include "sdram-micron-mt46h32m32lf-6.h"
52#include "hsmmc.h" 53#include "hsmmc.h"
53#include "common-board-devices.h" 54#include "common-board-devices.h"
54#include "gpmc.h"
55#include "gpmc-nand.h"
56 55
57#define CM_T35_GPIO_PENDOWN 57 56#define CM_T35_GPIO_PENDOWN 57
58#define SB_T35_USB_HUB_RESET_GPIO 167 57#define SB_T35_USB_HUB_RESET_GPIO 167
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 8a2c1677964c..794756df8529 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -28,6 +28,7 @@
28#include <linux/delay.h> 28#include <linux/delay.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/leds.h> 30#include <linux/leds.h>
31#include <linux/omap-gpmc.h>
31#include <linux/rtc-v3020.h> 32#include <linux/rtc-v3020.h>
32#include <linux/mtd/mtd.h> 33#include <linux/mtd/mtd.h>
33#include <linux/mtd/nand.h> 34#include <linux/mtd/nand.h>
@@ -41,7 +42,6 @@
41 42
42#include "common.h" 43#include "common.h"
43#include <linux/platform_data/mtd-nand-omap2.h> 44#include <linux/platform_data/mtd-nand-omap2.h>
44#include "gpmc.h"
45 45
46#include "am35xx.h" 46#include "am35xx.h"
47 47
@@ -50,7 +50,6 @@
50#include "hsmmc.h" 50#include "hsmmc.h"
51#include "common-board-devices.h" 51#include "common-board-devices.h"
52#include "am35xx-emac.h" 52#include "am35xx-emac.h"
53#include "gpmc-nand.h"
54 53
55#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) 54#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
56static struct gpio_led cm_t3517_leds[] = { 55static struct gpio_led cm_t3517_leds[] = {
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 2d245c2e641c..70b21cc279ba 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -13,6 +13,7 @@
13 */ 13 */
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/omap-gpmc.h>
16#include <linux/platform_device.h> 17#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h> 18#include <linux/mtd/physmap.h>
18#include <linux/io.h> 19#include <linux/io.h>
@@ -23,8 +24,6 @@
23#include "soc.h" 24#include "soc.h"
24#include "common.h" 25#include "common.h"
25#include "board-flash.h" 26#include "board-flash.h"
26#include "gpmc-onenand.h"
27#include "gpmc-nand.h"
28 27
29#define REG_FPGA_REV 0x10 28#define REG_FPGA_REV 0x10
30#define REG_FPGA_DIP_SWITCH_INPUT2 0x60 29#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index 2fb5d41a9fae..ea9aaebe11e7 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -12,7 +12,6 @@
12 */ 12 */
13#include <linux/mtd/mtd.h> 13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h> 14#include <linux/mtd/partitions.h>
15#include "gpmc.h"
16 15
17#define PDC_NOR 1 16#define PDC_NOR 1
18#define PDC_NAND 2 17#define PDC_NAND 2
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 97767a27ca9d..49c3c25808e7 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -22,7 +22,6 @@
22#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
23#include <linux/usb/musb.h> 23#include <linux/usb/musb.h>
24#include <linux/platform_data/spi-omap2-mcspi.h> 24#include <linux/platform_data/spi-omap2-mcspi.h>
25#include <linux/platform_data/mtd-onenand-omap2.h>
26#include <linux/mfd/menelaus.h> 25#include <linux/mfd/menelaus.h>
27#include <sound/tlv320aic3x.h> 26#include <sound/tlv320aic3x.h>
28 27
@@ -32,7 +31,6 @@
32#include "common.h" 31#include "common.h"
33#include "mmc.h" 32#include "mmc.h"
34#include "soc.h" 33#include "soc.h"
35#include "gpmc-onenand.h"
36#include "common-board-devices.h" 34#include "common-board-devices.h"
37 35
38#define TUSB6010_ASYNC_CS 1 36#define TUSB6010_ASYNC_CS 1
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index f32201656cf3..7f1708738c30 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -24,6 +24,7 @@
24#include <linux/spi/spi.h> 24#include <linux/spi/spi.h>
25#include <linux/regulator/machine.h> 25#include <linux/regulator/machine.h>
26#include <linux/i2c/twl.h> 26#include <linux/i2c/twl.h>
27#include <linux/omap-gpmc.h>
27#include <linux/wl12xx.h> 28#include <linux/wl12xx.h>
28#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h> 30#include <linux/mtd/nand.h>
@@ -51,7 +52,6 @@
51#include "sdram-micron-mt46h32m32lf-6.h" 52#include "sdram-micron-mt46h32m32lf-6.h"
52#include "hsmmc.h" 53#include "hsmmc.h"
53#include "common-board-devices.h" 54#include "common-board-devices.h"
54#include "gpmc-nand.h"
55 55
56#define PANDORA_WIFI_IRQ_GPIO 21 56#define PANDORA_WIFI_IRQ_GPIO 21
57#define PANDORA_WIFI_NRESET_GPIO 23 57#define PANDORA_WIFI_NRESET_GPIO 23
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 30e7d4ce7b8d..e2ad48b5d9c0 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -23,6 +23,7 @@
23#include <linux/regulator/machine.h> 23#include <linux/regulator/machine.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/gpio_keys.h> 25#include <linux/gpio_keys.h>
26#include <linux/omap-gpmc.h>
26#include <linux/mmc/host.h> 27#include <linux/mmc/host.h>
27#include <linux/power/isp1704_charger.h> 28#include <linux/power/isp1704_charger.h>
28#include <linux/platform_data/spi-omap2-mcspi.h> 29#include <linux/platform_data/spi-omap2-mcspi.h>
@@ -54,8 +55,6 @@
54#include "omap-pm.h" 55#include "omap-pm.h"
55#include "hsmmc.h" 56#include "hsmmc.h"
56#include "common-board-devices.h" 57#include "common-board-devices.h"
57#include "gpmc.h"
58#include "gpmc-onenand.h"
59#include "soc.h" 58#include "soc.h"
60#include "omap-secure.h" 59#include "omap-secure.h"
61 60
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index cb7764314f17..d5951b17b736 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -12,14 +12,13 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/omap-gpmc.h>
15#include <linux/mtd/nand.h> 16#include <linux/mtd/nand.h>
16#include <linux/platform_data/mtd-nand-omap2.h> 17#include <linux/platform_data/mtd-nand-omap2.h>
17 18
18#include <asm/mach/flash.h> 19#include <asm/mach/flash.h>
19 20
20#include "gpmc.h"
21#include "soc.h" 21#include "soc.h"
22#include "gpmc-nand.h"
23 22
24/* minimum size for IO mapping */ 23/* minimum size for IO mapping */
25#define NAND_IO_SIZE 4 24#define NAND_IO_SIZE 4
diff --git a/arch/arm/mach-omap2/gpmc-nand.h b/arch/arm/mach-omap2/gpmc-nand.h
deleted file mode 100644
index d59e1281e851..000000000000
--- a/arch/arm/mach-omap2/gpmc-nand.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-omap2/gpmc-nand.h
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __OMAP2_GPMC_NAND_H
11#define __OMAP2_GPMC_NAND_H
12
13#include "gpmc.h"
14#include <linux/platform_data/mtd-nand-omap2.h>
15
16#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
17extern int gpmc_nand_init(struct omap_nand_platform_data *d,
18 struct gpmc_timings *gpmc_t);
19#else
20static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
21 struct gpmc_timings *gpmc_t)
22{
23 return 0;
24}
25#endif
26
27#endif
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 8b6876c98ce1..53d197e0c1f3 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -15,14 +15,13 @@
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/mtd/onenand_regs.h> 16#include <linux/mtd/onenand_regs.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/omap-gpmc.h>
18#include <linux/platform_data/mtd-onenand-omap2.h> 19#include <linux/platform_data/mtd-onenand-omap2.h>
19#include <linux/err.h> 20#include <linux/err.h>
20 21
21#include <asm/mach/flash.h> 22#include <asm/mach/flash.h>
22 23
23#include "gpmc.h"
24#include "soc.h" 24#include "soc.h"
25#include "gpmc-onenand.h"
26 25
27#define ONENAND_IO_SIZE SZ_128K 26#define ONENAND_IO_SIZE SZ_128K
28 27
diff --git a/arch/arm/mach-omap2/gpmc-onenand.h b/arch/arm/mach-omap2/gpmc-onenand.h
deleted file mode 100644
index 216f23a8b45c..000000000000
--- a/arch/arm/mach-omap2/gpmc-onenand.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/mach-omap2/gpmc-onenand.h
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __OMAP2_GPMC_ONENAND_H
11#define __OMAP2_GPMC_ONENAND_H
12
13#include <linux/platform_data/mtd-onenand-omap2.h>
14
15#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
16extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
17#else
18#define board_onenand_data NULL
19static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
20{
21}
22#endif
23
24#endif
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9ea92b6f180d..0753a046fed2 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -29,18 +29,17 @@
29#include <linux/of_address.h> 29#include <linux/of_address.h>
30#include <linux/of_mtd.h> 30#include <linux/of_mtd.h>
31#include <linux/of_device.h> 31#include <linux/of_device.h>
32#include <linux/omap-gpmc.h>
32#include <linux/mtd/nand.h> 33#include <linux/mtd/nand.h>
33#include <linux/pm_runtime.h> 34#include <linux/pm_runtime.h>
34 35
35#include <linux/platform_data/mtd-nand-omap2.h> 36#include <linux/platform_data/mtd-nand-omap2.h>
36 37#include <linux/platform_data/mtd-onenand-omap2.h>
37#include <asm/mach-types.h>
38 38
39#include "soc.h" 39#include "soc.h"
40#include "omap_device.h" 40#include "omap_device.h"
41#include "gpmc.h" 41
42#include "gpmc-nand.h" 42#include <asm/mach-types.h>
43#include "gpmc-onenand.h"
44 43
45#define DEVICE_NAME "omap-gpmc" 44#define DEVICE_NAME "omap-gpmc"
46 45
@@ -115,6 +114,60 @@
115 114
116#define GPMC_NR_WAITPINS 4 115#define GPMC_NR_WAITPINS 4
117 116
117#define GPMC_CS_CONFIG1 0x00
118#define GPMC_CS_CONFIG2 0x04
119#define GPMC_CS_CONFIG3 0x08
120#define GPMC_CS_CONFIG4 0x0c
121#define GPMC_CS_CONFIG5 0x10
122#define GPMC_CS_CONFIG6 0x14
123#define GPMC_CS_CONFIG7 0x18
124#define GPMC_CS_NAND_COMMAND 0x1c
125#define GPMC_CS_NAND_ADDRESS 0x20
126#define GPMC_CS_NAND_DATA 0x24
127
128/* Control Commands */
129#define GPMC_CONFIG_RDY_BSY 0x00000001
130#define GPMC_CONFIG_DEV_SIZE 0x00000002
131#define GPMC_CONFIG_DEV_TYPE 0x00000003
132#define GPMC_SET_IRQ_STATUS 0x00000004
133
134#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
135#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
136#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
137#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
138#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
139#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
140#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
141#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
142#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
143#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
144#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
145#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
146#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
147#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
148#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
149#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
150#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
151#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
152#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
153#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
154#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
155#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
156#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
157#define GPMC_CONFIG7_CSVALID (1 << 6)
158
159#define GPMC_DEVICETYPE_NOR 0
160#define GPMC_DEVICETYPE_NAND 2
161#define GPMC_CONFIG_WRITEPROTECT 0x00000010
162#define WR_RD_PIN_MONITORING 0x00600000
163
164#define GPMC_ENABLE_IRQ 0x0000000d
165
166/* ECC commands */
167#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
168#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
169#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
170
118/* XXX: Only NAND irq has been considered,currently these are the only ones used 171/* XXX: Only NAND irq has been considered,currently these are the only ones used
119 */ 172 */
120#define GPMC_NR_IRQ 2 173#define GPMC_NR_IRQ 2
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index 707f6d58edd5..9caa41a6cb04 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -6,226 +6,9 @@
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 *
10 * Do not include this file in any new code, this will get removed
11 * once omap3 boots in device tree only mode.
12 *
9 */ 13 */
10 14#include <linux/omap-gpmc.h>
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14#include <linux/platform_data/mtd-nand-omap2.h>
15
16/* Maximum Number of Chip Selects */
17#define GPMC_CS_NUM 8
18
19#define GPMC_CS_CONFIG1 0x00
20#define GPMC_CS_CONFIG2 0x04
21#define GPMC_CS_CONFIG3 0x08
22#define GPMC_CS_CONFIG4 0x0c
23#define GPMC_CS_CONFIG5 0x10
24#define GPMC_CS_CONFIG6 0x14
25#define GPMC_CS_CONFIG7 0x18
26#define GPMC_CS_NAND_COMMAND 0x1c
27#define GPMC_CS_NAND_ADDRESS 0x20
28#define GPMC_CS_NAND_DATA 0x24
29
30/* Control Commands */
31#define GPMC_CONFIG_RDY_BSY 0x00000001
32#define GPMC_CONFIG_DEV_SIZE 0x00000002
33#define GPMC_CONFIG_DEV_TYPE 0x00000003
34#define GPMC_SET_IRQ_STATUS 0x00000004
35#define GPMC_CONFIG_WP 0x00000005
36
37#define GPMC_ENABLE_IRQ 0x0000000d
38
39/* ECC commands */
40#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
41#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
42#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
43
44#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
45#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
46#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
47#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
48#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
49#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
50#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
51#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
52#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
53#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
54#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
55#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
56#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
57#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
58#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
59#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
60#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
61#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
62#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
63#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
64#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
65#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
66#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
67#define GPMC_CONFIG7_CSVALID (1 << 6)
68
69#define GPMC_DEVICETYPE_NOR 0
70#define GPMC_DEVICETYPE_NAND 2
71#define GPMC_CONFIG_WRITEPROTECT 0x00000010
72#define WR_RD_PIN_MONITORING 0x00600000
73#define GPMC_IRQ_FIFOEVENTENABLE 0x01
74#define GPMC_IRQ_COUNT_EVENT 0x02
75
76#define GPMC_BURST_4 4 /* 4 word burst */
77#define GPMC_BURST_8 8 /* 8 word burst */
78#define GPMC_BURST_16 16 /* 16 word burst */
79#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
80#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
81#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
82#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
83
84/* bool type time settings */
85struct gpmc_bool_timings {
86 bool cycle2cyclediffcsen;
87 bool cycle2cyclesamecsen;
88 bool we_extra_delay;
89 bool oe_extra_delay;
90 bool adv_extra_delay;
91 bool cs_extra_delay;
92 bool time_para_granularity;
93};
94
95/*
96 * Note that all values in this struct are in nanoseconds except sync_clk
97 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
98 */
99struct gpmc_timings {
100 /* Minimum clock period for synchronous mode (in picoseconds) */
101 u32 sync_clk;
102
103 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
104 u32 cs_on; /* Assertion time */
105 u32 cs_rd_off; /* Read deassertion time */
106 u32 cs_wr_off; /* Write deassertion time */
107
108 /* ADV signal timings corresponding to GPMC_CONFIG3 */
109 u32 adv_on; /* Assertion time */
110 u32 adv_rd_off; /* Read deassertion time */
111 u32 adv_wr_off; /* Write deassertion time */
112
113 /* WE signals timings corresponding to GPMC_CONFIG4 */
114 u32 we_on; /* WE assertion time */
115 u32 we_off; /* WE deassertion time */
116
117 /* OE signals timings corresponding to GPMC_CONFIG4 */
118 u32 oe_on; /* OE assertion time */
119 u32 oe_off; /* OE deassertion time */
120
121 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
122 u32 page_burst_access; /* Multiple access word delay */
123 u32 access; /* Start-cycle to first data valid delay */
124 u32 rd_cycle; /* Total read cycle time */
125 u32 wr_cycle; /* Total write cycle time */
126
127 u32 bus_turnaround;
128 u32 cycle2cycle_delay;
129
130 u32 wait_monitoring;
131 u32 clk_activation;
132
133 /* The following are only on OMAP3430 */
134 u32 wr_access; /* WRACCESSTIME */
135 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
136
137 struct gpmc_bool_timings bool_timings;
138};
139
140/* Device timings in picoseconds */
141struct gpmc_device_timings {
142 u32 t_ceasu; /* address setup to CS valid */
143 u32 t_avdasu; /* address setup to ADV valid */
144 /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
145 * of tusb using these timings even for sync whilst
146 * ideally for adv_rd/(wr)_off it should have considered
147 * t_avdh instead. This indirectly necessitates r/w
148 * variations of t_avdp as it is possible to have one
149 * sync & other async
150 */
151 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
152 u32 t_avdp_w;
153 u32 t_aavdh; /* address hold time */
154 u32 t_oeasu; /* address setup to OE valid */
155 u32 t_aa; /* access time from ADV assertion */
156 u32 t_iaa; /* initial access time */
157 u32 t_oe; /* access time from OE assertion */
158 u32 t_ce; /* access time from CS asertion */
159 u32 t_rd_cycle; /* read cycle time */
160 u32 t_cez_r; /* read CS deassertion to high Z */
161 u32 t_cez_w; /* write CS deassertion to high Z */
162 u32 t_oez; /* OE deassertion to high Z */
163 u32 t_weasu; /* address setup to WE valid */
164 u32 t_wpl; /* write assertion time */
165 u32 t_wph; /* write deassertion time */
166 u32 t_wr_cycle; /* write cycle time */
167
168 u32 clk;
169 u32 t_bacc; /* burst access valid clock to output delay */
170 u32 t_ces; /* CS setup time to clk */
171 u32 t_avds; /* ADV setup time to clk */
172 u32 t_avdh; /* ADV hold time from clk */
173 u32 t_ach; /* address hold time from clk */
174 u32 t_rdyo; /* clk to ready valid */
175
176 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
177 u32 t_ce_avd; /* CS on to ADV on delay */
178
179 /* XXX: check the possibility of combining
180 * cyc_aavhd_oe & cyc_aavdh_we
181 */
182 u8 cyc_aavdh_oe;/* read address hold time in cycles */
183 u8 cyc_aavdh_we;/* write address hold time in cycles */
184 u8 cyc_oe; /* access time from OE assertion in cycles */
185 u8 cyc_wpl; /* write deassertion time in cycles */
186 u32 cyc_iaa; /* initial access time in cycles */
187
188 /* extra delays */
189 bool ce_xdelay;
190 bool avd_xdelay;
191 bool oe_xdelay;
192 bool we_xdelay;
193};
194
195struct gpmc_settings {
196 bool burst_wrap; /* enables wrap bursting */
197 bool burst_read; /* enables read page/burst mode */
198 bool burst_write; /* enables write page/burst mode */
199 bool device_nand; /* device is NAND */
200 bool sync_read; /* enables synchronous reads */
201 bool sync_write; /* enables synchronous writes */
202 bool wait_on_read; /* monitor wait on reads */
203 bool wait_on_write; /* monitor wait on writes */
204 u32 burst_len; /* page/burst length */
205 u32 device_width; /* device bus width (8 or 16 bit) */
206 u32 mux_add_data; /* multiplex address & data */
207 u32 wait_pin; /* wait-pin to be used */
208};
209
210extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
211 struct gpmc_settings *gpmc_s,
212 struct gpmc_device_timings *dev_t);
213
214extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
215extern int gpmc_get_client_irq(unsigned irq_config);
216
217extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
218
219extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
220extern int gpmc_calc_divider(unsigned int sync_clk);
221extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
222extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
223extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
224extern void gpmc_cs_free(int cs);
225extern void omap3_gpmc_save_context(void);
226extern void omap3_gpmc_restore_context(void);
227extern int gpmc_configure(int cmd, int wval);
228extern void gpmc_read_settings_dt(struct device_node *np,
229 struct gpmc_settings *p);
230
231#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 175564c88a30..88721df6001d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,7 @@
29#include <linux/delay.h> 29#include <linux/delay.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31#include <linux/omap-dma.h> 31#include <linux/omap-dma.h>
32#include <linux/omap-gpmc.h>
32#include <linux/platform_data/gpio-omap.h> 33#include <linux/platform_data/gpio-omap.h>
33 34
34#include <trace/events/power.h> 35#include <trace/events/power.h>
@@ -43,7 +44,6 @@
43#include "common.h" 44#include "common.h"
44#include "cm3xxx.h" 45#include "cm3xxx.h"
45#include "cm-regbits-34xx.h" 46#include "cm-regbits-34xx.h"
46#include "gpmc.h"
47#include "prm-regbits-34xx.h" 47#include "prm-regbits-34xx.h"
48#include "prm3xxx.h" 48#include "prm3xxx.h"
49#include "pm.h" 49#include "pm.h"
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
new file mode 100644
index 000000000000..c2080eebbb47
--- /dev/null
+++ b/include/linux/omap-gpmc.h
@@ -0,0 +1,199 @@
1/*
2 * OMAP GPMC (General Purpose Memory Controller) defines
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10/* Maximum Number of Chip Selects */
11#define GPMC_CS_NUM 8
12
13#define GPMC_CONFIG_WP 0x00000005
14
15#define GPMC_IRQ_FIFOEVENTENABLE 0x01
16#define GPMC_IRQ_COUNT_EVENT 0x02
17
18#define GPMC_BURST_4 4 /* 4 word burst */
19#define GPMC_BURST_8 8 /* 8 word burst */
20#define GPMC_BURST_16 16 /* 16 word burst */
21#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
22#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
23#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
24#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
25
26/* bool type time settings */
27struct gpmc_bool_timings {
28 bool cycle2cyclediffcsen;
29 bool cycle2cyclesamecsen;
30 bool we_extra_delay;
31 bool oe_extra_delay;
32 bool adv_extra_delay;
33 bool cs_extra_delay;
34 bool time_para_granularity;
35};
36
37/*
38 * Note that all values in this struct are in nanoseconds except sync_clk
39 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
40 */
41struct gpmc_timings {
42 /* Minimum clock period for synchronous mode (in picoseconds) */
43 u32 sync_clk;
44
45 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
46 u32 cs_on; /* Assertion time */
47 u32 cs_rd_off; /* Read deassertion time */
48 u32 cs_wr_off; /* Write deassertion time */
49
50 /* ADV signal timings corresponding to GPMC_CONFIG3 */
51 u32 adv_on; /* Assertion time */
52 u32 adv_rd_off; /* Read deassertion time */
53 u32 adv_wr_off; /* Write deassertion time */
54
55 /* WE signals timings corresponding to GPMC_CONFIG4 */
56 u32 we_on; /* WE assertion time */
57 u32 we_off; /* WE deassertion time */
58
59 /* OE signals timings corresponding to GPMC_CONFIG4 */
60 u32 oe_on; /* OE assertion time */
61 u32 oe_off; /* OE deassertion time */
62
63 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
64 u32 page_burst_access; /* Multiple access word delay */
65 u32 access; /* Start-cycle to first data valid delay */
66 u32 rd_cycle; /* Total read cycle time */
67 u32 wr_cycle; /* Total write cycle time */
68
69 u32 bus_turnaround;
70 u32 cycle2cycle_delay;
71
72 u32 wait_monitoring;
73 u32 clk_activation;
74
75 /* The following are only on OMAP3430 */
76 u32 wr_access; /* WRACCESSTIME */
77 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
78
79 struct gpmc_bool_timings bool_timings;
80};
81
82/* Device timings in picoseconds */
83struct gpmc_device_timings {
84 u32 t_ceasu; /* address setup to CS valid */
85 u32 t_avdasu; /* address setup to ADV valid */
86 /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
87 * of tusb using these timings even for sync whilst
88 * ideally for adv_rd/(wr)_off it should have considered
89 * t_avdh instead. This indirectly necessitates r/w
90 * variations of t_avdp as it is possible to have one
91 * sync & other async
92 */
93 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
94 u32 t_avdp_w;
95 u32 t_aavdh; /* address hold time */
96 u32 t_oeasu; /* address setup to OE valid */
97 u32 t_aa; /* access time from ADV assertion */
98 u32 t_iaa; /* initial access time */
99 u32 t_oe; /* access time from OE assertion */
100 u32 t_ce; /* access time from CS asertion */
101 u32 t_rd_cycle; /* read cycle time */
102 u32 t_cez_r; /* read CS deassertion to high Z */
103 u32 t_cez_w; /* write CS deassertion to high Z */
104 u32 t_oez; /* OE deassertion to high Z */
105 u32 t_weasu; /* address setup to WE valid */
106 u32 t_wpl; /* write assertion time */
107 u32 t_wph; /* write deassertion time */
108 u32 t_wr_cycle; /* write cycle time */
109
110 u32 clk;
111 u32 t_bacc; /* burst access valid clock to output delay */
112 u32 t_ces; /* CS setup time to clk */
113 u32 t_avds; /* ADV setup time to clk */
114 u32 t_avdh; /* ADV hold time from clk */
115 u32 t_ach; /* address hold time from clk */
116 u32 t_rdyo; /* clk to ready valid */
117
118 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
119 u32 t_ce_avd; /* CS on to ADV on delay */
120
121 /* XXX: check the possibility of combining
122 * cyc_aavhd_oe & cyc_aavdh_we
123 */
124 u8 cyc_aavdh_oe;/* read address hold time in cycles */
125 u8 cyc_aavdh_we;/* write address hold time in cycles */
126 u8 cyc_oe; /* access time from OE assertion in cycles */
127 u8 cyc_wpl; /* write deassertion time in cycles */
128 u32 cyc_iaa; /* initial access time in cycles */
129
130 /* extra delays */
131 bool ce_xdelay;
132 bool avd_xdelay;
133 bool oe_xdelay;
134 bool we_xdelay;
135};
136
137struct gpmc_settings {
138 bool burst_wrap; /* enables wrap bursting */
139 bool burst_read; /* enables read page/burst mode */
140 bool burst_write; /* enables write page/burst mode */
141 bool device_nand; /* device is NAND */
142 bool sync_read; /* enables synchronous reads */
143 bool sync_write; /* enables synchronous writes */
144 bool wait_on_read; /* monitor wait on reads */
145 bool wait_on_write; /* monitor wait on writes */
146 u32 burst_len; /* page/burst length */
147 u32 device_width; /* device bus width (8 or 16 bit) */
148 u32 mux_add_data; /* multiplex address & data */
149 u32 wait_pin; /* wait-pin to be used */
150};
151
152extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
153 struct gpmc_settings *gpmc_s,
154 struct gpmc_device_timings *dev_t);
155
156struct gpmc_nand_regs;
157struct device_node;
158
159extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
160extern int gpmc_get_client_irq(unsigned irq_config);
161
162extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
163
164extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
165extern int gpmc_calc_divider(unsigned int sync_clk);
166extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
167extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
168extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
169extern void gpmc_cs_free(int cs);
170extern int gpmc_configure(int cmd, int wval);
171extern void gpmc_read_settings_dt(struct device_node *np,
172 struct gpmc_settings *p);
173
174extern void omap3_gpmc_save_context(void);
175extern void omap3_gpmc_restore_context(void);
176
177struct gpmc_timings;
178struct omap_nand_platform_data;
179struct omap_onenand_platform_data;
180
181#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
182extern int gpmc_nand_init(struct omap_nand_platform_data *d,
183 struct gpmc_timings *gpmc_t);
184#else
185static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
186 struct gpmc_timings *gpmc_t)
187{
188 return 0;
189}
190#endif
191
192#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
193extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
194#else
195#define board_onenand_data NULL
196static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
197{
198}
199#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 19:47:39 -0500