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-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-ap148.dts8
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi33
2 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index 95e64955fb8e..55b2910efd87 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -81,5 +81,13 @@
81 }; 81 };
82 }; 82 };
83 }; 83 };
84
85 sata-phy@1b400000 {
86 status = "ok";
87 };
88
89 sata@29000000 {
90 status = "ok";
91 };
84 }; 92 };
85}; 93};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 244f857f0e6f..63b2146f563b 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -234,6 +234,39 @@
234 }; 234 };
235 }; 235 };
236 236
237 sata_phy: sata-phy@1b400000 {
238 compatible = "qcom,ipq806x-sata-phy";
239 reg = <0x1b400000 0x200>;
240
241 clocks = <&gcc SATA_PHY_CFG_CLK>;
242 clock-names = "cfg";
243
244 #phy-cells = <0>;
245 status = "disabled";
246 };
247
248 sata@29000000 {
249 compatible = "qcom,ipq806x-ahci", "generic-ahci";
250 reg = <0x29000000 0x180>;
251
252 interrupts = <0 209 0x0>;
253
254 clocks = <&gcc SFAB_SATA_S_H_CLK>,
255 <&gcc SATA_H_CLK>,
256 <&gcc SATA_A_CLK>,
257 <&gcc SATA_RXOOB_CLK>,
258 <&gcc SATA_PMALIVE_CLK>;
259 clock-names = "slave_face", "iface", "core",
260 "rxoob", "pmalive";
261
262 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
263 assigned-clock-rates = <100000000>, <100000000>;
264
265 phys = <&sata_phy>;
266 phy-names = "sata-phy";
267 status = "disabled";
268 };
269
237 qcom,ssbi@500000 { 270 qcom,ssbi@500000 {
238 compatible = "qcom,ssbi"; 271 compatible = "qcom,ssbi";
239 reg = <0x00500000 0x1000>; 272 reg = <0x00500000 0x1000>;