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-rw-r--r--drivers/pci/host/pci-keystone.c2
-rw-r--r--drivers/pci/host/pci-xgene.c2
-rw-r--r--drivers/pci/host/pcie-xilinx.c4
3 files changed, 4 insertions, 4 deletions
diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
index 23a1d97db1dd..75333b0c4f0a 100644
--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
@@ -119,7 +119,7 @@ static void ks_pcie_msi_irq_handler(unsigned int irq, struct irq_desc *desc)
119 struct pcie_port *pp = &ks_pcie->pp; 119 struct pcie_port *pp = &ks_pcie->pp;
120 struct irq_chip *chip = irq_desc_get_chip(desc); 120 struct irq_chip *chip = irq_desc_get_chip(desc);
121 121
122 dev_dbg(pp->dev, "ks_pci_msi_irq_handler, irq %d\n", irq); 122 dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
123 123
124 /* 124 /*
125 * The chained irq handler installation would have replaced normal 125 * The chained irq handler installation would have replaced normal
diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index b1d0596457c5..fdb348d3ccd3 100644
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -16,7 +16,7 @@
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 */ 18 */
19#include <linux/clk-private.h> 19#include <linux/clk.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/jiffies.h> 22#include <linux/jiffies.h>
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index ef3ebaf9a738..ce1c61d85b2c 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -148,10 +148,10 @@ static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
148 */ 148 */
149static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port) 149static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
150{ 150{
151 u32 val = pcie_read(port, XILINX_PCIE_REG_RPEFR); 151 unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
152 152
153 if (val & XILINX_PCIE_RPEFR_ERR_VALID) { 153 if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
154 dev_dbg(port->dev, "Requester ID %d\n", 154 dev_dbg(port->dev, "Requester ID %lu\n",
155 val & XILINX_PCIE_RPEFR_REQ_ID); 155 val & XILINX_PCIE_RPEFR_REQ_ID);
156 pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK, 156 pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
157 XILINX_PCIE_REG_RPEFR); 157 XILINX_PCIE_REG_RPEFR);