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-rw-r--r--Documentation/devicetree/bindings/ata/ahci-platform.txt45
-rw-r--r--Documentation/devicetree/bindings/ata/ahci-st.txt31
-rw-r--r--Documentation/devicetree/bindings/ata/imx-sata.txt36
-rw-r--r--Documentation/devicetree/bindings/ata/tegra-sata.txt30
-rw-r--r--drivers/ata/Kconfig9
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/acard-ahci.c2
-rw-r--r--drivers/ata/ahci.c3
-rw-r--r--drivers/ata/ahci.h19
-rw-r--r--drivers/ata/ahci_da850.c3
-rw-r--r--drivers/ata/ahci_imx.c187
-rw-r--r--drivers/ata/ahci_mvebu.c3
-rw-r--r--drivers/ata/ahci_platform.c8
-rw-r--r--drivers/ata/ahci_st.c4
-rw-r--r--drivers/ata/ahci_sunxi.c8
-rw-r--r--drivers/ata/ahci_tegra.c376
-rw-r--r--drivers/ata/ahci_xgene.c29
-rw-r--r--drivers/ata/libahci.c19
-rw-r--r--drivers/ata/libahci_platform.c215
-rw-r--r--drivers/ata/pata_samsung_cf.c13
-rw-r--r--drivers/ata/sata_fsl.c5
-rw-r--r--drivers/ata/sata_highbank.c2
-rw-r--r--drivers/ata/sata_sil24.c4
-rw-r--r--include/linux/ahci_platform.h5
-rw-r--r--include/linux/platform_data/ata-samsung_cf.h1
25 files changed, 917 insertions, 141 deletions
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index c96d8dcf98fd..4ab09f2202d4 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -3,28 +3,43 @@
3SATA nodes are defined to describe on-chip Serial ATA controllers. 3SATA nodes are defined to describe on-chip Serial ATA controllers.
4Each SATA controller should have its own node. 4Each SATA controller should have its own node.
5 5
6It is possible, but not required, to represent each port as a sub-node.
7It allows to enable each port independently when dealing with multiple
8PHYs.
9
6Required properties: 10Required properties:
7- compatible : compatible string, one of: 11- compatible : compatible string, one of:
8 - "allwinner,sun4i-a10-ahci" 12 - "allwinner,sun4i-a10-ahci"
9 - "fsl,imx53-ahci"
10 - "fsl,imx6q-ahci"
11 - "hisilicon,hisi-ahci" 13 - "hisilicon,hisi-ahci"
12 - "ibm,476gtr-ahci" 14 - "ibm,476gtr-ahci"
13 - "marvell,armada-380-ahci" 15 - "marvell,armada-380-ahci"
14 - "snps,dwc-ahci" 16 - "snps,dwc-ahci"
15 - "snps,exynos5440-ahci" 17 - "snps,exynos5440-ahci"
16 - "snps,spear-ahci" 18 - "snps,spear-ahci"
19 - "generic-ahci"
17- interrupts : <interrupt mapping for SATA IRQ> 20- interrupts : <interrupt mapping for SATA IRQ>
18- reg : <registers mapping> 21- reg : <registers mapping>
19 22
23Please note that when using "generic-ahci" you must also specify a SoC specific
24compatible:
25 compatible = "manufacturer,soc-model-ahci", "generic-ahci";
26
20Optional properties: 27Optional properties:
21- dma-coherent : Present if dma operations are coherent 28- dma-coherent : Present if dma operations are coherent
22- clocks : a list of phandle + clock specifier pairs 29- clocks : a list of phandle + clock specifier pairs
23- target-supply : regulator for SATA target power 30- target-supply : regulator for SATA target power
31- phys : reference to the SATA PHY node
32- phy-names : must be "sata-phy"
33
34Required properties when using sub-nodes:
35- #address-cells : number of cells to encode an address
36- #size-cells : number of cells representing the size of an address
37
38
39Sub-nodes required properties:
40- reg : the port number
41- phys : reference to the SATA PHY node
24 42
25"fsl,imx53-ahci", "fsl,imx6q-ahci" required properties:
26- clocks : must contain the sata, sata_ref and ahb clocks
27- clock-names : must contain "ahb" for the ahb clock
28 43
29Examples: 44Examples:
30 sata@ffe08000 { 45 sata@ffe08000 {
@@ -40,3 +55,23 @@ Examples:
40 clocks = <&pll6 0>, <&ahb_gates 25>; 55 clocks = <&pll6 0>, <&ahb_gates 25>;
41 target-supply = <&reg_ahci_5v>; 56 target-supply = <&reg_ahci_5v>;
42 }; 57 };
58
59With sub-nodes:
60 sata@f7e90000 {
61 compatible = "marvell,berlin2q-achi", "generic-ahci";
62 reg = <0xe90000 0x1000>;
63 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&chip CLKID_SATA>;
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 sata0: sata-port@0 {
69 reg = <0>;
70 phys = <&sata_phy 0>;
71 };
72
73 sata1: sata-port@1 {
74 reg = <1>;
75 phys = <&sata_phy 1>;
76 };
77 };
diff --git a/Documentation/devicetree/bindings/ata/ahci-st.txt b/Documentation/devicetree/bindings/ata/ahci-st.txt
new file mode 100644
index 000000000000..0574a77a0b9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-st.txt
@@ -0,0 +1,31 @@
1STMicroelectronics STi SATA controller
2
3This binding describes a SATA device.
4
5Required properties:
6 - compatible : Must be "st,sti-ahci"
7 - reg : Physical base addresses and length of register sets
8 - interrupts : Interrupt associated with the SATA device
9 - interrupt-names : Associated name must be; "hostc"
10 - resets : The power-down and soft-reset lines of SATA IP
11 - reset-names : Associated names must be; "pwr-dwn" and "sw-rst"
12 - clocks : The phandle for the clock
13 - clock-names : Associated name must be; "ahci_clk"
14 - phys : The phandle for the PHY device
15 - phy-names : Associated name must be; "ahci_phy"
16
17Example:
18
19 sata0: sata@fe380000 {
20 compatible = "st,sti-ahci";
21 reg = <0xfe380000 0x1000>;
22 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
23 interrupt-names = "hostc";
24 phys = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>;
25 phy-names = "ahci_phy";
26 resets = <&powerdown STIH416_SATA0_POWERDOWN>,
27 <&softreset STIH416_SATA0_SOFTRESET>;
28 reset-names = "pwr-dwn", "sw-rst";
29 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
30 clock-names = "ahci_clk";
31 };
diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt
new file mode 100644
index 000000000000..fa511db18408
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/imx-sata.txt
@@ -0,0 +1,36 @@
1* Freescale i.MX AHCI SATA Controller
2
3The Freescale i.MX SATA controller mostly conforms to the AHCI interface
4with some special extensions at integration level.
5
6Required properties:
7- compatible : should be one of the following:
8 - "fsl,imx53-ahci" for i.MX53 SATA controller
9 - "fsl,imx6q-ahci" for i.MX6Q SATA controller
10- interrupts : interrupt mapping for SATA IRQ
11- reg : registers mapping
12- clocks : list of clock specifiers, must contain an entry for each
13 required entry in clock-names
14- clock-names : should include "sata", "sata_ref" and "ahb" entries
15
16Optional properties:
17- fsl,transmit-level-mV : transmit voltage level, in millivolts.
18- fsl,transmit-boost-mdB : transmit boost level, in milli-decibels
19- fsl,transmit-atten-16ths : transmit attenuation, in 16ths
20- fsl,receive-eq-mdB : receive equalisation, in milli-decibels
21 Please refer to the technical documentation or the driver source code
22 for the list of legal values for these options.
23- fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA
24 link.
25
26Examples:
27
28sata@02200000 {
29 compatible = "fsl,imx6q-ahci";
30 reg = <0x02200000 0x4000>;
31 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&clks IMX6QDL_CLK_SATA>,
33 <&clks IMX6QDL_CLK_SATA_REF_100M>,
34 <&clks IMX6QDL_CLK_AHB>;
35 clock-names = "sata", "sata_ref", "ahb";
36};
diff --git a/Documentation/devicetree/bindings/ata/tegra-sata.txt b/Documentation/devicetree/bindings/ata/tegra-sata.txt
new file mode 100644
index 000000000000..946f2072570b
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/tegra-sata.txt
@@ -0,0 +1,30 @@
1Tegra124 SoC SATA AHCI controller
2
3Required properties :
4- compatible : "nvidia,tegra124-ahci".
5- reg : Should contain 2 entries:
6 - AHCI register set (SATA BAR5)
7 - SATA register set
8- interrupts : Defines the interrupt used by SATA
9- clocks : Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11- clock-names : Must include the following entries:
12 - sata
13 - sata-oob
14 - cml1
15 - pll_e
16- resets : Must contain an entry for each entry in reset-names.
17 See ../reset/reset.txt for details.
18- reset-names : Must include the following entries:
19 - sata
20 - sata-oob
21 - sata-cold
22- phys : Must contain an entry for each entry in phy-names.
23 See ../phy/phy-bindings.txt for details.
24- phy-names : Must include the following entries:
25 - sata-phy : XUSB PADCTL SATA PHY
26- hvdd-supply : Defines the SATA HVDD regulator
27- vddio-supply : Defines the SATA VDDIO regulator
28- avdd-supply : Defines the SATA AVDD regulator
29- target-5v-supply : Defines the SATA 5V power regulator
30- target-12v-supply : Defines the SATA 12V power regulator
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 7671dbac6015..e65d400efd44 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -141,6 +141,15 @@ config AHCI_SUNXI
141 141
142 If unsure, say N. 142 If unsure, say N.
143 143
144config AHCI_TEGRA
145 tristate "NVIDIA Tegra124 AHCI SATA support"
146 depends on ARCH_TEGRA
147 help
148 This option enables support for the NVIDIA Tegra124 SoC's
149 onboard AHCI SATA.
150
151 If unsure, say N.
152
144config AHCI_XGENE 153config AHCI_XGENE
145 tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support" 154 tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
146 depends on PHY_XGENE 155 depends on PHY_XGENE
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 5a02aeecef5b..ae41107afc1f 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
15obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o 15obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
16obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o 16obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
17obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o 17obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
18obj-$(CONFIG_AHCI_TEGRA) += ahci_tegra.o libahci.o libahci_platform.o
18obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o 19obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
19 20
20# SFF w/ custom DMA 21# SFF w/ custom DMA
diff --git a/drivers/ata/acard-ahci.c b/drivers/ata/acard-ahci.c
index 0cd7c7a39e5b..25d0ac32e721 100644
--- a/drivers/ata/acard-ahci.c
+++ b/drivers/ata/acard-ahci.c
@@ -441,7 +441,7 @@ static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id
441 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; 441 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
442 442
443 /* save initial config */ 443 /* save initial config */
444 ahci_save_initial_config(&pdev->dev, hpriv, 0, 0); 444 ahci_save_initial_config(&pdev->dev, hpriv);
445 445
446 /* prepare host */ 446 /* prepare host */
447 if (hpriv->cap & HOST_CAP_NCQ) 447 if (hpriv->cap & HOST_CAP_NCQ)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 4cd52a4541a9..a29f8012fb08 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -526,8 +526,7 @@ static void ahci_pci_save_initial_config(struct pci_dev *pdev,
526 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 526 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
527 } 527 }
528 528
529 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map, 529 ahci_save_initial_config(&pdev->dev, hpriv);
530 mask_port_map);
531} 530}
532 531
533static int ahci_pci_reset_controller(struct ata_host *host) 532static int ahci_pci_reset_controller(struct ata_host *host)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 5513296e5e2e..59ae0ee00149 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -53,7 +53,7 @@
53 53
54enum { 54enum {
55 AHCI_MAX_PORTS = 32, 55 AHCI_MAX_PORTS = 32,
56 AHCI_MAX_CLKS = 3, 56 AHCI_MAX_CLKS = 4,
57 AHCI_MAX_SG = 168, /* hardware max is 64K */ 57 AHCI_MAX_SG = 168, /* hardware max is 64K */
58 AHCI_DMA_BOUNDARY = 0xffffffff, 58 AHCI_DMA_BOUNDARY = 0xffffffff,
59 AHCI_MAX_CMDS = 32, 59 AHCI_MAX_CMDS = 32,
@@ -316,8 +316,12 @@ struct ahci_port_priv {
316}; 316};
317 317
318struct ahci_host_priv { 318struct ahci_host_priv {
319 void __iomem * mmio; /* bus-independent mem map */ 319 /* Input fields */
320 unsigned int flags; /* AHCI_HFLAG_* */ 320 unsigned int flags; /* AHCI_HFLAG_* */
321 u32 force_port_map; /* force port map */
322 u32 mask_port_map; /* mask out particular bits */
323
324 void __iomem * mmio; /* bus-independent mem map */
321 u32 cap; /* cap to use */ 325 u32 cap; /* cap to use */
322 u32 cap2; /* cap2 to use */ 326 u32 cap2; /* cap2 to use */
323 u32 port_map; /* port map to use */ 327 u32 port_map; /* port map to use */
@@ -330,7 +334,12 @@ struct ahci_host_priv {
330 bool got_runtime_pm; /* Did we do pm_runtime_get? */ 334 bool got_runtime_pm; /* Did we do pm_runtime_get? */
331 struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ 335 struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
332 struct regulator *target_pwr; /* Optional */ 336 struct regulator *target_pwr; /* Optional */
333 struct phy *phy; /* If platform uses phy */ 337 /*
338 * If platform uses PHYs. There is a 1:1 relation between the port number and
339 * the PHY position in this array.
340 */
341 struct phy **phys;
342 unsigned nports; /* Number of ports */
334 void *plat_data; /* Other platform data */ 343 void *plat_data; /* Other platform data */
335 /* 344 /*
336 * Optional ahci_start_engine override, if not set this gets set to the 345 * Optional ahci_start_engine override, if not set this gets set to the
@@ -361,9 +370,7 @@ unsigned int ahci_dev_classify(struct ata_port *ap);
361void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 370void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
362 u32 opts); 371 u32 opts);
363void ahci_save_initial_config(struct device *dev, 372void ahci_save_initial_config(struct device *dev,
364 struct ahci_host_priv *hpriv, 373 struct ahci_host_priv *hpriv);
365 unsigned int force_port_map,
366 unsigned int mask_port_map);
367void ahci_init_controller(struct ata_host *host); 374void ahci_init_controller(struct ata_host *host);
368int ahci_reset_controller(struct ata_host *host); 375int ahci_reset_controller(struct ata_host *host);
369 376
diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c
index 2b77d53bccf8..ad1e71ec10cf 100644
--- a/drivers/ata/ahci_da850.c
+++ b/drivers/ata/ahci_da850.c
@@ -85,8 +85,7 @@ static int ahci_da850_probe(struct platform_device *pdev)
85 85
86 da850_sata_init(dev, pwrdn_reg, hpriv->mmio); 86 da850_sata_init(dev, pwrdn_reg, hpriv->mmio);
87 87
88 rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info, 88 rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info);
89 0, 0, 0);
90 if (rc) 89 if (rc)
91 goto disable_resources; 90 goto disable_resources;
92 91
diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index cac4360f272a..f3970b4ed889 100644
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
@@ -64,6 +64,7 @@ struct imx_ahci_priv {
64 struct regmap *gpr; 64 struct regmap *gpr;
65 bool no_device; 65 bool no_device;
66 bool first_time; 66 bool first_time;
67 u32 phy_params;
67}; 68};
68 69
69static int ahci_imx_hotplug; 70static int ahci_imx_hotplug;
@@ -248,14 +249,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
248 IMX6Q_GPR13_SATA_TX_LVL_MASK | 249 IMX6Q_GPR13_SATA_TX_LVL_MASK |
249 IMX6Q_GPR13_SATA_MPLL_CLK_EN | 250 IMX6Q_GPR13_SATA_MPLL_CLK_EN |
250 IMX6Q_GPR13_SATA_TX_EDGE_RATE, 251 IMX6Q_GPR13_SATA_TX_EDGE_RATE,
251 IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB | 252 imxpriv->phy_params);
252 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
253 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
254 IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
255 IMX6Q_GPR13_SATA_MPLL_SS_EN |
256 IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
257 IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
258 IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
259 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 253 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
260 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 254 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
261 IMX6Q_GPR13_SATA_MPLL_CLK_EN); 255 IMX6Q_GPR13_SATA_MPLL_CLK_EN);
@@ -265,7 +259,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
265 ret = imx_sata_phy_reset(hpriv); 259 ret = imx_sata_phy_reset(hpriv);
266 if (ret) { 260 if (ret) {
267 dev_err(dev, "failed to reset phy: %d\n", ret); 261 dev_err(dev, "failed to reset phy: %d\n", ret);
268 goto disable_regulator; 262 goto disable_clk;
269 } 263 }
270 } 264 }
271 265
@@ -273,6 +267,8 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
273 267
274 return 0; 268 return 0;
275 269
270disable_clk:
271 clk_disable_unprepare(imxpriv->sata_ref_clk);
276disable_regulator: 272disable_regulator:
277 if (hpriv->target_pwr) 273 if (hpriv->target_pwr)
278 regulator_disable(hpriv->target_pwr); 274 regulator_disable(hpriv->target_pwr);
@@ -369,6 +365,165 @@ static const struct of_device_id imx_ahci_of_match[] = {
369}; 365};
370MODULE_DEVICE_TABLE(of, imx_ahci_of_match); 366MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
371 367
368struct reg_value {
369 u32 of_value;
370 u32 reg_value;
371};
372
373struct reg_property {
374 const char *name;
375 const struct reg_value *values;
376 size_t num_values;
377 u32 def_value;
378 u32 set_value;
379};
380
381static const struct reg_value gpr13_tx_level[] = {
382 { 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
383 { 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
384 { 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
385 { 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
386 { 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
387 { 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
388 { 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
389 { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
390 { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
391 { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
392 { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
393 { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
394 { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
395 { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
396 { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
397 { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
398 { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
399 { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
400 { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
401 { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
402 { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
403 { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
404 { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
405 { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
406 { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
407 { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
408 { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
409 { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
410 { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
411 { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
412 { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
413 { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
414};
415
416static const struct reg_value gpr13_tx_boost[] = {
417 { 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
418 { 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
419 { 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
420 { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
421 { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
422 { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
423 { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
424 { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
425 { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
426 { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
427 { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
428 { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
429 { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
430 { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
431 { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
432 { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
433};
434
435static const struct reg_value gpr13_tx_atten[] = {
436 { 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
437 { 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
438 { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
439 { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
440 { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
441 { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
442};
443
444static const struct reg_value gpr13_rx_eq[] = {
445 { 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
446 { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
447 { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
448 { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
449 { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
450 { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
451 { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
452 { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
453};
454
455static const struct reg_property gpr13_props[] = {
456 {
457 .name = "fsl,transmit-level-mV",
458 .values = gpr13_tx_level,
459 .num_values = ARRAY_SIZE(gpr13_tx_level),
460 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
461 }, {
462 .name = "fsl,transmit-boost-mdB",
463 .values = gpr13_tx_boost,
464 .num_values = ARRAY_SIZE(gpr13_tx_boost),
465 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
466 }, {
467 .name = "fsl,transmit-atten-16ths",
468 .values = gpr13_tx_atten,
469 .num_values = ARRAY_SIZE(gpr13_tx_atten),
470 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
471 }, {
472 .name = "fsl,receive-eq-mdB",
473 .values = gpr13_rx_eq,
474 .num_values = ARRAY_SIZE(gpr13_rx_eq),
475 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
476 }, {
477 .name = "fsl,no-spread-spectrum",
478 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
479 .set_value = 0,
480 },
481};
482
483static u32 imx_ahci_parse_props(struct device *dev,
484 const struct reg_property *prop, size_t num)
485{
486 struct device_node *np = dev->of_node;
487 u32 reg_value = 0;
488 int i, j;
489
490 for (i = 0; i < num; i++, prop++) {
491 u32 of_val;
492
493 if (prop->num_values == 0) {
494 if (of_property_read_bool(np, prop->name))
495 reg_value |= prop->set_value;
496 else
497 reg_value |= prop->def_value;
498 continue;
499 }
500
501 if (of_property_read_u32(np, prop->name, &of_val)) {
502 dev_info(dev, "%s not specified, using %08x\n",
503 prop->name, prop->def_value);
504 reg_value |= prop->def_value;
505 continue;
506 }
507
508 for (j = 0; j < prop->num_values; j++) {
509 if (prop->values[j].of_value == of_val) {
510 dev_info(dev, "%s value %u, using %08x\n",
511 prop->name, of_val, prop->values[j].reg_value);
512 reg_value |= prop->values[j].reg_value;
513 break;
514 }
515 }
516
517 if (j == prop->num_values) {
518 dev_err(dev, "DT property %s is not a valid value\n",
519 prop->name);
520 reg_value |= prop->def_value;
521 }
522 }
523
524 return reg_value;
525}
526
372static int imx_ahci_probe(struct platform_device *pdev) 527static int imx_ahci_probe(struct platform_device *pdev)
373{ 528{
374 struct device *dev = &pdev->dev; 529 struct device *dev = &pdev->dev;
@@ -410,6 +565,8 @@ static int imx_ahci_probe(struct platform_device *pdev)
410 } 565 }
411 566
412 if (imxpriv->type == AHCI_IMX6Q) { 567 if (imxpriv->type == AHCI_IMX6Q) {
568 u32 reg_value;
569
413 imxpriv->gpr = syscon_regmap_lookup_by_compatible( 570 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
414 "fsl,imx6q-iomuxc-gpr"); 571 "fsl,imx6q-iomuxc-gpr");
415 if (IS_ERR(imxpriv->gpr)) { 572 if (IS_ERR(imxpriv->gpr)) {
@@ -417,6 +574,15 @@ static int imx_ahci_probe(struct platform_device *pdev)
417 "failed to find fsl,imx6q-iomux-gpr regmap\n"); 574 "failed to find fsl,imx6q-iomux-gpr regmap\n");
418 return PTR_ERR(imxpriv->gpr); 575 return PTR_ERR(imxpriv->gpr);
419 } 576 }
577
578 reg_value = imx_ahci_parse_props(dev, gpr13_props,
579 ARRAY_SIZE(gpr13_props));
580
581 imxpriv->phy_params =
582 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
583 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
584 IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
585 reg_value;
420 } 586 }
421 587
422 hpriv = ahci_platform_get_resources(pdev); 588 hpriv = ahci_platform_get_resources(pdev);
@@ -454,8 +620,7 @@ static int imx_ahci_probe(struct platform_device *pdev)
454 reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; 620 reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
455 writel(reg_val, hpriv->mmio + IMX_TIMER1MS); 621 writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
456 622
457 ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 623 ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info);
458 0, 0, 0);
459 if (ret) 624 if (ret)
460 goto disable_sata; 625 goto disable_sata;
461 626
diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index fd3dfd733b84..68672d2692ee 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_mvebu.c
@@ -88,8 +88,7 @@ static int ahci_mvebu_probe(struct platform_device *pdev)
88 ahci_mvebu_mbus_config(hpriv, dram); 88 ahci_mvebu_mbus_config(hpriv, dram);
89 ahci_mvebu_regret_option(hpriv); 89 ahci_mvebu_regret_option(hpriv);
90 90
91 rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info, 91 rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info);
92 0, 0, 0);
93 if (rc) 92 if (rc)
94 goto disable_resources; 93 goto disable_resources;
95 94
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index b10d81ddb528..f61ddb9146d6 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -34,7 +34,6 @@ static int ahci_probe(struct platform_device *pdev)
34 struct device *dev = &pdev->dev; 34 struct device *dev = &pdev->dev;
35 struct ahci_platform_data *pdata = dev_get_platdata(dev); 35 struct ahci_platform_data *pdata = dev_get_platdata(dev);
36 struct ahci_host_priv *hpriv; 36 struct ahci_host_priv *hpriv;
37 unsigned long hflags = 0;
38 int rc; 37 int rc;
39 38
40 hpriv = ahci_platform_get_resources(pdev); 39 hpriv = ahci_platform_get_resources(pdev);
@@ -58,10 +57,9 @@ static int ahci_probe(struct platform_device *pdev)
58 } 57 }
59 58
60 if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci")) 59 if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci"))
61 hflags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ; 60 hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ;
62 61
63 rc = ahci_platform_init_host(pdev, hpriv, &ahci_port_info, 62 rc = ahci_platform_init_host(pdev, hpriv, &ahci_port_info);
64 hflags, 0, 0);
65 if (rc) 63 if (rc)
66 goto pdata_exit; 64 goto pdata_exit;
67 65
@@ -78,6 +76,8 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
78 ahci_platform_resume); 76 ahci_platform_resume);
79 77
80static const struct of_device_id ahci_of_match[] = { 78static const struct of_device_id ahci_of_match[] = {
79 { .compatible = "generic-ahci", },
80 /* Keep the following compatibles for device tree compatibility */
81 { .compatible = "snps,spear-ahci", }, 81 { .compatible = "snps,spear-ahci", },
82 { .compatible = "snps,exynos5440-ahci", }, 82 { .compatible = "snps,exynos5440-ahci", },
83 { .compatible = "ibm,476gtr-ahci", }, 83 { .compatible = "ibm,476gtr-ahci", },
diff --git a/drivers/ata/ahci_st.c b/drivers/ata/ahci_st.c
index 2595598df9ce..835d6eea84fd 100644
--- a/drivers/ata/ahci_st.c
+++ b/drivers/ata/ahci_st.c
@@ -166,7 +166,7 @@ static int st_ahci_probe(struct platform_device *pdev)
166 if (err) 166 if (err)
167 return err; 167 return err;
168 168
169 err = ahci_platform_init_host(pdev, hpriv, &st_ahci_port_info, 0, 0, 0); 169 err = ahci_platform_init_host(pdev, hpriv, &st_ahci_port_info);
170 if (err) { 170 if (err) {
171 ahci_platform_disable_resources(hpriv); 171 ahci_platform_disable_resources(hpriv);
172 return err; 172 return err;
@@ -221,7 +221,7 @@ static int st_ahci_resume(struct device *dev)
221 221
222static SIMPLE_DEV_PM_OPS(st_ahci_pm_ops, st_ahci_suspend, st_ahci_resume); 222static SIMPLE_DEV_PM_OPS(st_ahci_pm_ops, st_ahci_suspend, st_ahci_resume);
223 223
224static struct of_device_id st_ahci_match[] = { 224static const struct of_device_id st_ahci_match[] = {
225 { .compatible = "st,ahci", }, 225 { .compatible = "st,ahci", },
226 {}, 226 {},
227}; 227};
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 02002f125bd4..e44d675a30ec 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -167,7 +167,6 @@ static int ahci_sunxi_probe(struct platform_device *pdev)
167{ 167{
168 struct device *dev = &pdev->dev; 168 struct device *dev = &pdev->dev;
169 struct ahci_host_priv *hpriv; 169 struct ahci_host_priv *hpriv;
170 unsigned long hflags;
171 int rc; 170 int rc;
172 171
173 hpriv = ahci_platform_get_resources(pdev); 172 hpriv = ahci_platform_get_resources(pdev);
@@ -184,11 +183,10 @@ static int ahci_sunxi_probe(struct platform_device *pdev)
184 if (rc) 183 if (rc)
185 goto disable_resources; 184 goto disable_resources;
186 185
187 hflags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI | 186 hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
188 AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ; 187 AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
189 188
190 rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info, 189 rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info);
191 hflags, 0, 0);
192 if (rc) 190 if (rc)
193 goto disable_resources; 191 goto disable_resources;
194 192
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
new file mode 100644
index 000000000000..fc3df47fca35
--- /dev/null
+++ b/drivers/ata/ahci_tegra.c
@@ -0,0 +1,376 @@
1/*
2 * drivers/ata/ahci_tegra.c
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author:
7 * Mikko Perttunen <mperttunen@nvidia.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/ahci_platform.h>
21#include <linux/reset.h>
22#include <linux/errno.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/tegra-powergate.h>
28#include <linux/regulator/consumer.h>
29#include "ahci.h"
30
31#define SATA_CONFIGURATION_0 0x180
32#define SATA_CONFIGURATION_EN_FPCI BIT(0)
33
34#define SCFG_OFFSET 0x1000
35
36#define T_SATA0_CFG_1 0x04
37#define T_SATA0_CFG_1_IO_SPACE BIT(0)
38#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
39#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
40#define T_SATA0_CFG_1_SERR BIT(8)
41
42#define T_SATA0_CFG_9 0x24
43#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
44
45#define SATA_FPCI_BAR5 0x94
46#define SATA_FPCI_BAR5_START_SHIFT 4
47
48#define SATA_INTR_MASK 0x188
49#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
50
51#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
52
53#define T_SATA0_BKDOOR_CC 0x4a4
54
55#define T_SATA0_CFG_SATA 0x54c
56#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
57
58#define T_SATA0_CFG_MISC 0x550
59
60#define T_SATA0_INDEX 0x680
61
62#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
63#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
64#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
65#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
66#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
67
68#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
69#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
70#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
71#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
72#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
73
74#define T_SATA0_CHX_PHY_CTRL2 0x69c
75#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
76
77#define T_SATA0_CHX_PHY_CTRL11 0x6d0
78#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
79
80#define FUSE_SATA_CALIB 0x124
81#define FUSE_SATA_CALIB_MASK 0x3
82
83struct sata_pad_calibration {
84 u8 gen1_tx_amp;
85 u8 gen1_tx_peak;
86 u8 gen2_tx_amp;
87 u8 gen2_tx_peak;
88};
89
90static const struct sata_pad_calibration tegra124_pad_calibration[] = {
91 {0x18, 0x04, 0x18, 0x0a},
92 {0x0e, 0x04, 0x14, 0x0a},
93 {0x0e, 0x07, 0x1a, 0x0e},
94 {0x14, 0x0e, 0x1a, 0x0e},
95};
96
97struct tegra_ahci_priv {
98 struct platform_device *pdev;
99 void __iomem *sata_regs;
100 struct reset_control *sata_rst;
101 struct reset_control *sata_oob_rst;
102 struct reset_control *sata_cold_rst;
103 /* Needs special handling, cannot use ahci_platform */
104 struct clk *sata_clk;
105 struct regulator_bulk_data supplies[5];
106};
107
108static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
109{
110 struct tegra_ahci_priv *tegra = hpriv->plat_data;
111 int ret;
112
113 ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
114 tegra->supplies);
115 if (ret)
116 return ret;
117
118 ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
119 tegra->sata_clk,
120 tegra->sata_rst);
121 if (ret)
122 goto disable_regulators;
123
124 reset_control_assert(tegra->sata_oob_rst);
125 reset_control_assert(tegra->sata_cold_rst);
126
127 ret = ahci_platform_enable_resources(hpriv);
128 if (ret)
129 goto disable_power;
130
131 reset_control_deassert(tegra->sata_cold_rst);
132 reset_control_deassert(tegra->sata_oob_rst);
133
134 return 0;
135
136disable_power:
137 clk_disable_unprepare(tegra->sata_clk);
138
139 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
140
141disable_regulators:
142 regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
143
144 return ret;
145}
146
147static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
148{
149 struct tegra_ahci_priv *tegra = hpriv->plat_data;
150
151 ahci_platform_disable_resources(hpriv);
152
153 reset_control_assert(tegra->sata_rst);
154 reset_control_assert(tegra->sata_oob_rst);
155 reset_control_assert(tegra->sata_cold_rst);
156
157 clk_disable_unprepare(tegra->sata_clk);
158 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
159
160 regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
161}
162
163static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
164{
165 struct tegra_ahci_priv *tegra = hpriv->plat_data;
166 int ret;
167 unsigned int val;
168 struct sata_pad_calibration calib;
169
170 ret = tegra_ahci_power_on(hpriv);
171 if (ret) {
172 dev_err(&tegra->pdev->dev,
173 "failed to power on AHCI controller: %d\n", ret);
174 return ret;
175 }
176
177 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
178 val |= SATA_CONFIGURATION_EN_FPCI;
179 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
180
181 /* Pad calibration */
182
183 /* FIXME Always use calibration 0. Change this to read the calibration
184 * fuse once the fuse driver has landed. */
185 val = 0;
186
187 calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
188
189 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
190
191 val = readl(tegra->sata_regs +
192 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
193 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
194 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
195 val |= calib.gen1_tx_amp <<
196 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
197 val |= calib.gen1_tx_peak <<
198 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
199 writel(val, tegra->sata_regs + SCFG_OFFSET +
200 T_SATA0_CHX_PHY_CTRL1_GEN1);
201
202 val = readl(tegra->sata_regs +
203 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
204 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
205 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
206 val |= calib.gen2_tx_amp <<
207 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
208 val |= calib.gen2_tx_peak <<
209 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
210 writel(val, tegra->sata_regs + SCFG_OFFSET +
211 T_SATA0_CHX_PHY_CTRL1_GEN2);
212
213 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
214 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
215 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
216 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
217
218 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
219
220 /* Program controller device ID */
221
222 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
223 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
224 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
225
226 writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
227
228 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
229 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
230 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
231
232 /* Enable IO & memory access, bus master mode */
233
234 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
235 val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
236 T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
237 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
238
239 /* Program SATA MMIO */
240
241 writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
242 tegra->sata_regs + SATA_FPCI_BAR5);
243
244 writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
245 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
246
247 /* Unmask SATA interrupts */
248
249 val = readl(tegra->sata_regs + SATA_INTR_MASK);
250 val |= SATA_INTR_MASK_IP_INT_MASK;
251 writel(val, tegra->sata_regs + SATA_INTR_MASK);
252
253 return 0;
254}
255
256static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
257{
258 tegra_ahci_power_off(hpriv);
259}
260
261static void tegra_ahci_host_stop(struct ata_host *host)
262{
263 struct ahci_host_priv *hpriv = host->private_data;
264
265 tegra_ahci_controller_deinit(hpriv);
266}
267
268static struct ata_port_operations ahci_tegra_port_ops = {
269 .inherits = &ahci_ops,
270 .host_stop = tegra_ahci_host_stop,
271};
272
273static const struct ata_port_info ahci_tegra_port_info = {
274 .flags = AHCI_FLAG_COMMON,
275 .pio_mask = ATA_PIO4,
276 .udma_mask = ATA_UDMA6,
277 .port_ops = &ahci_tegra_port_ops,
278};
279
280static const struct of_device_id tegra_ahci_of_match[] = {
281 { .compatible = "nvidia,tegra124-ahci" },
282 {}
283};
284MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
285
286static int tegra_ahci_probe(struct platform_device *pdev)
287{
288 struct ahci_host_priv *hpriv;
289 struct tegra_ahci_priv *tegra;
290 struct resource *res;
291 int ret;
292
293 hpriv = ahci_platform_get_resources(pdev);
294 if (IS_ERR(hpriv))
295 return PTR_ERR(hpriv);
296
297 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
298 if (!tegra)
299 return -ENOMEM;
300
301 hpriv->plat_data = tegra;
302
303 tegra->pdev = pdev;
304
305 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
306 tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
307 if (IS_ERR(tegra->sata_regs))
308 return PTR_ERR(tegra->sata_regs);
309
310 tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
311 if (IS_ERR(tegra->sata_rst)) {
312 dev_err(&pdev->dev, "Failed to get sata reset\n");
313 return PTR_ERR(tegra->sata_rst);
314 }
315
316 tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
317 if (IS_ERR(tegra->sata_oob_rst)) {
318 dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
319 return PTR_ERR(tegra->sata_oob_rst);
320 }
321
322 tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
323 if (IS_ERR(tegra->sata_cold_rst)) {
324 dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
325 return PTR_ERR(tegra->sata_cold_rst);
326 }
327
328 tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
329 if (IS_ERR(tegra->sata_clk)) {
330 dev_err(&pdev->dev, "Failed to get sata clock\n");
331 return PTR_ERR(tegra->sata_clk);
332 }
333
334 tegra->supplies[0].supply = "avdd";
335 tegra->supplies[1].supply = "hvdd";
336 tegra->supplies[2].supply = "vddio";
337 tegra->supplies[3].supply = "target-5v";
338 tegra->supplies[4].supply = "target-12v";
339
340 ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
341 tegra->supplies);
342 if (ret) {
343 dev_err(&pdev->dev, "Failed to get regulators\n");
344 return ret;
345 }
346
347 ret = tegra_ahci_controller_init(hpriv);
348 if (ret)
349 return ret;
350
351 ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info);
352 if (ret)
353 goto deinit_controller;
354
355 return 0;
356
357deinit_controller:
358 tegra_ahci_controller_deinit(hpriv);
359
360 return ret;
361};
362
363static struct platform_driver tegra_ahci_driver = {
364 .probe = tegra_ahci_probe,
365 .remove = ata_platform_remove_one,
366 .driver = {
367 .name = "tegra-ahci",
368 .of_match_table = tegra_ahci_of_match,
369 },
370 /* LP0 suspend support not implemented */
371};
372module_platform_driver(tegra_ahci_driver);
373
374MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
375MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
376MODULE_LICENSE("GPL v2");
diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c
index ee3a3659bd9e..bc281115490b 100644
--- a/drivers/ata/ahci_xgene.c
+++ b/drivers/ata/ahci_xgene.c
@@ -67,6 +67,9 @@
67#define PORTAXICFG 0x000000bc 67#define PORTAXICFG 0x000000bc
68#define PORTAXICFG_OUTTRANS_SET(dst, src) \ 68#define PORTAXICFG_OUTTRANS_SET(dst, src) \
69 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000)) 69 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
70#define PORTRANSCFG 0x000000c8
71#define PORTRANSCFG_RXWM_SET(dst, src) \
72 (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
70 73
71/* SATA host controller AXI CSR */ 74/* SATA host controller AXI CSR */
72#define INT_SLV_TMOMASK 0x00000010 75#define INT_SLV_TMOMASK 0x00000010
@@ -193,11 +196,11 @@ static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
193 /* Disable fix rate */ 196 /* Disable fix rate */
194 writel(0x0001fffe, mmio + PORTPHY1CFG); 197 writel(0x0001fffe, mmio + PORTPHY1CFG);
195 readl(mmio + PORTPHY1CFG); /* Force a barrier */ 198 readl(mmio + PORTPHY1CFG); /* Force a barrier */
196 writel(0x5018461c, mmio + PORTPHY2CFG); 199 writel(0x28183219, mmio + PORTPHY2CFG);
197 readl(mmio + PORTPHY2CFG); /* Force a barrier */ 200 readl(mmio + PORTPHY2CFG); /* Force a barrier */
198 writel(0x1c081907, mmio + PORTPHY3CFG); 201 writel(0x13081008, mmio + PORTPHY3CFG);
199 readl(mmio + PORTPHY3CFG); /* Force a barrier */ 202 readl(mmio + PORTPHY3CFG); /* Force a barrier */
200 writel(0x1c080815, mmio + PORTPHY4CFG); 203 writel(0x00480815, mmio + PORTPHY4CFG);
201 readl(mmio + PORTPHY4CFG); /* Force a barrier */ 204 readl(mmio + PORTPHY4CFG); /* Force a barrier */
202 /* Set window negotiation */ 205 /* Set window negotiation */
203 val = readl(mmio + PORTPHY5CFG); 206 val = readl(mmio + PORTPHY5CFG);
@@ -209,6 +212,10 @@ static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
209 val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */ 212 val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
210 writel(val, mmio + PORTAXICFG); 213 writel(val, mmio + PORTAXICFG);
211 readl(mmio + PORTAXICFG); /* Force a barrier */ 214 readl(mmio + PORTAXICFG); /* Force a barrier */
215 /* Set the watermark threshold of the receive FIFO */
216 val = readl(mmio + PORTRANSCFG);
217 val = PORTRANSCFG_RXWM_SET(val, 0x30);
218 writel(val, mmio + PORTRANSCFG);
212} 219}
213 220
214/** 221/**
@@ -415,7 +422,6 @@ static int xgene_ahci_probe(struct platform_device *pdev)
415 struct ahci_host_priv *hpriv; 422 struct ahci_host_priv *hpriv;
416 struct xgene_ahci_context *ctx; 423 struct xgene_ahci_context *ctx;
417 struct resource *res; 424 struct resource *res;
418 unsigned long hflags;
419 int rc; 425 int rc;
420 426
421 hpriv = ahci_platform_get_resources(pdev); 427 hpriv = ahci_platform_get_resources(pdev);
@@ -474,20 +480,9 @@ static int xgene_ahci_probe(struct platform_device *pdev)
474 /* Configure the host controller */ 480 /* Configure the host controller */
475 xgene_ahci_hw_init(hpriv); 481 xgene_ahci_hw_init(hpriv);
476 482
477 /* 483 hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
478 * Setup DMA mask. This is preliminary until the DMA range is sorted
479 * out.
480 */
481 rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
482 if (rc) {
483 dev_err(dev, "Unable to set dma mask\n");
484 goto disable_resources;
485 }
486
487 hflags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
488 484
489 rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info, 485 rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info);
490 hflags, 0, 0);
491 if (rc) 486 if (rc)
492 goto disable_resources; 487 goto disable_resources;
493 488
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index d72ce0470309..b784e9de426a 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -382,8 +382,6 @@ static ssize_t ahci_show_em_supported(struct device *dev,
382 * ahci_save_initial_config - Save and fixup initial config values 382 * ahci_save_initial_config - Save and fixup initial config values
383 * @dev: target AHCI device 383 * @dev: target AHCI device
384 * @hpriv: host private area to store config values 384 * @hpriv: host private area to store config values
385 * @force_port_map: force port map to a specified value
386 * @mask_port_map: mask out particular bits from port map
387 * 385 *
388 * Some registers containing configuration info might be setup by 386 * Some registers containing configuration info might be setup by
389 * BIOS and might be cleared on reset. This function saves the 387 * BIOS and might be cleared on reset. This function saves the
@@ -398,10 +396,7 @@ static ssize_t ahci_show_em_supported(struct device *dev,
398 * LOCKING: 396 * LOCKING:
399 * None. 397 * None.
400 */ 398 */
401void ahci_save_initial_config(struct device *dev, 399void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
402 struct ahci_host_priv *hpriv,
403 unsigned int force_port_map,
404 unsigned int mask_port_map)
405{ 400{
406 void __iomem *mmio = hpriv->mmio; 401 void __iomem *mmio = hpriv->mmio;
407 u32 cap, cap2, vers, port_map; 402 u32 cap, cap2, vers, port_map;
@@ -468,17 +463,17 @@ void ahci_save_initial_config(struct device *dev,
468 cap &= ~HOST_CAP_FBS; 463 cap &= ~HOST_CAP_FBS;
469 } 464 }
470 465
471 if (force_port_map && port_map != force_port_map) { 466 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
472 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 467 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
473 port_map, force_port_map); 468 port_map, hpriv->force_port_map);
474 port_map = force_port_map; 469 port_map = hpriv->force_port_map;
475 } 470 }
476 471
477 if (mask_port_map) { 472 if (hpriv->mask_port_map) {
478 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 473 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
479 port_map, 474 port_map,
480 port_map & mask_port_map); 475 port_map & hpriv->mask_port_map);
481 port_map &= mask_port_map; 476 port_map &= hpriv->mask_port_map;
482 } 477 }
483 478
484 /* cross check port_map and cap.n_ports */ 479 /* cross check port_map and cap.n_ports */
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index b0077589f065..5b92c290e6c6 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -39,6 +39,67 @@ static struct scsi_host_template ahci_platform_sht = {
39}; 39};
40 40
41/** 41/**
42 * ahci_platform_enable_phys - Enable PHYs
43 * @hpriv: host private area to store config values
44 *
45 * This function enables all the PHYs found in hpriv->phys, if any.
46 * If a PHY fails to be enabled, it disables all the PHYs already
47 * enabled in reverse order and returns an error.
48 *
49 * RETURNS:
50 * 0 on success otherwise a negative error code
51 */
52int ahci_platform_enable_phys(struct ahci_host_priv *hpriv)
53{
54 int rc, i;
55
56 for (i = 0; i < hpriv->nports; i++) {
57 if (!hpriv->phys[i])
58 continue;
59
60 rc = phy_init(hpriv->phys[i]);
61 if (rc)
62 goto disable_phys;
63
64 rc = phy_power_on(hpriv->phys[i]);
65 if (rc) {
66 phy_exit(hpriv->phys[i]);
67 goto disable_phys;
68 }
69 }
70
71 return 0;
72
73disable_phys:
74 while (--i >= 0) {
75 phy_power_off(hpriv->phys[i]);
76 phy_exit(hpriv->phys[i]);
77 }
78 return rc;
79}
80EXPORT_SYMBOL_GPL(ahci_platform_enable_phys);
81
82/**
83 * ahci_platform_disable_phys - Disable PHYs
84 * @hpriv: host private area to store config values
85 *
86 * This function disables all PHYs found in hpriv->phys.
87 */
88void ahci_platform_disable_phys(struct ahci_host_priv *hpriv)
89{
90 int i;
91
92 for (i = 0; i < hpriv->nports; i++) {
93 if (!hpriv->phys[i])
94 continue;
95
96 phy_power_off(hpriv->phys[i]);
97 phy_exit(hpriv->phys[i]);
98 }
99}
100EXPORT_SYMBOL_GPL(ahci_platform_disable_phys);
101
102/**
42 * ahci_platform_enable_clks - Enable platform clocks 103 * ahci_platform_enable_clks - Enable platform clocks
43 * @hpriv: host private area to store config values 104 * @hpriv: host private area to store config values
44 * 105 *
@@ -92,7 +153,7 @@ EXPORT_SYMBOL_GPL(ahci_platform_disable_clks);
92 * following order: 153 * following order:
93 * 1) Regulator 154 * 1) Regulator
94 * 2) Clocks (through ahci_platform_enable_clks) 155 * 2) Clocks (through ahci_platform_enable_clks)
95 * 3) Phy 156 * 3) Phys
96 * 157 *
97 * If resource enabling fails at any point the previous enabled resources 158 * If resource enabling fails at any point the previous enabled resources
98 * are disabled in reverse order. 159 * are disabled in reverse order.
@@ -114,17 +175,9 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
114 if (rc) 175 if (rc)
115 goto disable_regulator; 176 goto disable_regulator;
116 177
117 if (hpriv->phy) { 178 rc = ahci_platform_enable_phys(hpriv);
118 rc = phy_init(hpriv->phy); 179 if (rc)
119 if (rc) 180 goto disable_clks;
120 goto disable_clks;
121
122 rc = phy_power_on(hpriv->phy);
123 if (rc) {
124 phy_exit(hpriv->phy);
125 goto disable_clks;
126 }
127 }
128 181
129 return 0; 182 return 0;
130 183
@@ -144,16 +197,13 @@ EXPORT_SYMBOL_GPL(ahci_platform_enable_resources);
144 * 197 *
145 * This function disables all ahci_platform managed resources in the 198 * This function disables all ahci_platform managed resources in the
146 * following order: 199 * following order:
147 * 1) Phy 200 * 1) Phys
148 * 2) Clocks (through ahci_platform_disable_clks) 201 * 2) Clocks (through ahci_platform_disable_clks)
149 * 3) Regulator 202 * 3) Regulator
150 */ 203 */
151void ahci_platform_disable_resources(struct ahci_host_priv *hpriv) 204void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
152{ 205{
153 if (hpriv->phy) { 206 ahci_platform_disable_phys(hpriv);
154 phy_power_off(hpriv->phy);
155 phy_exit(hpriv->phy);
156 }
157 207
158 ahci_platform_disable_clks(hpriv); 208 ahci_platform_disable_clks(hpriv);
159 209
@@ -187,7 +237,7 @@ static void ahci_platform_put_resources(struct device *dev, void *res)
187 * 2) regulator for controlling the targets power (optional) 237 * 2) regulator for controlling the targets power (optional)
188 * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node, 238 * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node,
189 * or for non devicetree enabled platforms a single clock 239 * or for non devicetree enabled platforms a single clock
190 * 4) phy (optional) 240 * 4) phys (optional)
191 * 241 *
192 * RETURNS: 242 * RETURNS:
193 * The allocated ahci_host_priv on success, otherwise an ERR_PTR value 243 * The allocated ahci_host_priv on success, otherwise an ERR_PTR value
@@ -197,7 +247,9 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev)
197 struct device *dev = &pdev->dev; 247 struct device *dev = &pdev->dev;
198 struct ahci_host_priv *hpriv; 248 struct ahci_host_priv *hpriv;
199 struct clk *clk; 249 struct clk *clk;
200 int i, rc = -ENOMEM; 250 struct device_node *child;
251 int i, enabled_ports = 0, rc = -ENOMEM;
252 u32 mask_port_map = 0;
201 253
202 if (!devres_open_group(dev, NULL, GFP_KERNEL)) 254 if (!devres_open_group(dev, NULL, GFP_KERNEL))
203 return ERR_PTR(-ENOMEM); 255 return ERR_PTR(-ENOMEM);
@@ -246,28 +298,89 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev)
246 hpriv->clks[i] = clk; 298 hpriv->clks[i] = clk;
247 } 299 }
248 300
249 hpriv->phy = devm_phy_get(dev, "sata-phy"); 301 hpriv->nports = of_get_child_count(dev->of_node);
250 if (IS_ERR(hpriv->phy)) { 302
251 rc = PTR_ERR(hpriv->phy); 303 if (hpriv->nports) {
252 switch (rc) { 304 hpriv->phys = devm_kzalloc(dev,
253 case -ENOSYS: 305 hpriv->nports * sizeof(*hpriv->phys),
254 /* No PHY support. Check if PHY is required. */ 306 GFP_KERNEL);
255 if (of_find_property(dev->of_node, "phys", NULL)) { 307 if (!hpriv->phys) {
256 dev_err(dev, "couldn't get sata-phy: ENOSYS\n"); 308 rc = -ENOMEM;
309 goto err_out;
310 }
311
312 for_each_child_of_node(dev->of_node, child) {
313 u32 port;
314
315 if (!of_device_is_available(child))
316 continue;
317
318 if (of_property_read_u32(child, "reg", &port)) {
319 rc = -EINVAL;
257 goto err_out; 320 goto err_out;
258 } 321 }
259 case -ENODEV:
260 /* continue normally */
261 hpriv->phy = NULL;
262 break;
263 322
264 case -EPROBE_DEFER: 323 if (port >= hpriv->nports) {
265 goto err_out; 324 dev_warn(dev, "invalid port number %d\n", port);
325 continue;
326 }
327
328 mask_port_map |= BIT(port);
266 329
267 default: 330 hpriv->phys[port] = devm_of_phy_get(dev, child, NULL);
268 dev_err(dev, "couldn't get sata-phy\n"); 331 if (IS_ERR(hpriv->phys[port])) {
332 rc = PTR_ERR(hpriv->phys[port]);
333 dev_err(dev,
334 "couldn't get PHY in node %s: %d\n",
335 child->name, rc);
336 goto err_out;
337 }
338
339 enabled_ports++;
340 }
341 if (!enabled_ports) {
342 dev_warn(dev, "No port enabled\n");
343 rc = -ENODEV;
269 goto err_out; 344 goto err_out;
270 } 345 }
346
347 if (!hpriv->mask_port_map)
348 hpriv->mask_port_map = mask_port_map;
349 } else {
350 /*
351 * If no sub-node was found, keep this for device tree
352 * compatibility
353 */
354 struct phy *phy = devm_phy_get(dev, "sata-phy");
355 if (!IS_ERR(phy)) {
356 hpriv->phys = devm_kzalloc(dev, sizeof(*hpriv->phys),
357 GFP_KERNEL);
358 if (!hpriv->phys) {
359 rc = -ENOMEM;
360 goto err_out;
361 }
362
363 hpriv->phys[0] = phy;
364 hpriv->nports = 1;
365 } else {
366 rc = PTR_ERR(phy);
367 switch (rc) {
368 case -ENOSYS:
369 /* No PHY support. Check if PHY is required. */
370 if (of_find_property(dev->of_node, "phys", NULL)) {
371 dev_err(dev, "couldn't get sata-phy: ENOSYS\n");
372 goto err_out;
373 }
374 case -ENODEV:
375 /* continue normally */
376 hpriv->phys = NULL;
377 break;
378
379 default:
380 goto err_out;
381
382 }
383 }
271 } 384 }
272 385
273 pm_runtime_enable(dev); 386 pm_runtime_enable(dev);
@@ -288,12 +401,9 @@ EXPORT_SYMBOL_GPL(ahci_platform_get_resources);
288 * @pdev: platform device pointer for the host 401 * @pdev: platform device pointer for the host
289 * @hpriv: ahci-host private data for the host 402 * @hpriv: ahci-host private data for the host
290 * @pi_template: template for the ata_port_info to use 403 * @pi_template: template for the ata_port_info to use
291 * @host_flags: ahci host flags used in ahci_host_priv
292 * @force_port_map: param passed to ahci_save_initial_config
293 * @mask_port_map: param passed to ahci_save_initial_config
294 * 404 *
295 * This function does all the usual steps needed to bring up an 405 * This function does all the usual steps needed to bring up an
296 * ahci-platform host, note any necessary resources (ie clks, phy, etc.) 406 * ahci-platform host, note any necessary resources (ie clks, phys, etc.)
297 * must be initialized / enabled before calling this. 407 * must be initialized / enabled before calling this.
298 * 408 *
299 * RETURNS: 409 * RETURNS:
@@ -301,10 +411,7 @@ EXPORT_SYMBOL_GPL(ahci_platform_get_resources);
301 */ 411 */
302int ahci_platform_init_host(struct platform_device *pdev, 412int ahci_platform_init_host(struct platform_device *pdev,
303 struct ahci_host_priv *hpriv, 413 struct ahci_host_priv *hpriv,
304 const struct ata_port_info *pi_template, 414 const struct ata_port_info *pi_template)
305 unsigned long host_flags,
306 unsigned int force_port_map,
307 unsigned int mask_port_map)
308{ 415{
309 struct device *dev = &pdev->dev; 416 struct device *dev = &pdev->dev;
310 struct ata_port_info pi = *pi_template; 417 struct ata_port_info pi = *pi_template;
@@ -319,10 +426,9 @@ int ahci_platform_init_host(struct platform_device *pdev,
319 } 426 }
320 427
321 /* prepare host */ 428 /* prepare host */
322 pi.private_data = (void *)host_flags; 429 pi.private_data = (void *)(unsigned long)hpriv->flags;
323 hpriv->flags |= host_flags;
324 430
325 ahci_save_initial_config(dev, hpriv, force_port_map, mask_port_map); 431 ahci_save_initial_config(dev, hpriv);
326 432
327 if (hpriv->cap & HOST_CAP_NCQ) 433 if (hpriv->cap & HOST_CAP_NCQ)
328 pi.flags |= ATA_FLAG_NCQ; 434 pi.flags |= ATA_FLAG_NCQ;
@@ -369,6 +475,19 @@ int ahci_platform_init_host(struct platform_device *pdev,
369 ap->ops = &ata_dummy_port_ops; 475 ap->ops = &ata_dummy_port_ops;
370 } 476 }
371 477
478 if (hpriv->cap & HOST_CAP_64) {
479 rc = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
480 if (rc) {
481 rc = dma_coerce_mask_and_coherent(dev,
482 DMA_BIT_MASK(32));
483 if (rc) {
484 dev_err(dev, "Failed to enable 64-bit DMA.\n");
485 return rc;
486 }
487 dev_warn(dev, "Enable 32-bit DMA instead of 64-bit.\n");
488 }
489 }
490
372 rc = ahci_reset_controller(host); 491 rc = ahci_reset_controller(host);
373 if (rc) 492 if (rc)
374 return rc; 493 return rc;
@@ -399,7 +518,7 @@ static void ahci_host_stop(struct ata_host *host)
399 * @dev: device pointer for the host 518 * @dev: device pointer for the host
400 * 519 *
401 * This function does all the usual steps needed to suspend an 520 * This function does all the usual steps needed to suspend an
402 * ahci-platform host, note any necessary resources (ie clks, phy, etc.) 521 * ahci-platform host, note any necessary resources (ie clks, phys, etc.)
403 * must be disabled after calling this. 522 * must be disabled after calling this.
404 * 523 *
405 * RETURNS: 524 * RETURNS:
@@ -436,7 +555,7 @@ EXPORT_SYMBOL_GPL(ahci_platform_suspend_host);
436 * @dev: device pointer for the host 555 * @dev: device pointer for the host
437 * 556 *
438 * This function does all the usual steps needed to resume an ahci-platform 557 * This function does all the usual steps needed to resume an ahci-platform
439 * host, note any necessary resources (ie clks, phy, etc.) must be 558 * host, note any necessary resources (ie clks, phys, etc.) must be
440 * initialized / enabled before calling this. 559 * initialized / enabled before calling this.
441 * 560 *
442 * RETURNS: 561 * RETURNS:
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
index fb528831fb92..2578fc16960a 100644
--- a/drivers/ata/pata_samsung_cf.c
+++ b/drivers/ata/pata_samsung_cf.c
@@ -54,7 +54,6 @@
54 54
55enum s3c_cpu_type { 55enum s3c_cpu_type {
56 TYPE_S3C64XX, 56 TYPE_S3C64XX,
57 TYPE_S5PC100,
58 TYPE_S5PV210, 57 TYPE_S5PV210,
59}; 58};
60 59
@@ -476,10 +475,6 @@ static void pata_s3c_hwinit(struct s3c_ide_info *info,
476 writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK); 475 writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
477 break; 476 break;
478 477
479 case TYPE_S5PC100:
480 pata_s3c_cfg_mode(info->sfr_addr);
481 /* FALLTHROUGH */
482
483 case TYPE_S5PV210: 478 case TYPE_S5PV210:
484 /* Configure as little endian */ 479 /* Configure as little endian */
485 pata_s3c_set_endian(info->ide_addr, 0); 480 pata_s3c_set_endian(info->ide_addr, 0);
@@ -549,11 +544,6 @@ static int __init pata_s3c_probe(struct platform_device *pdev)
549 info->sfr_addr = info->ide_addr + 0x1800; 544 info->sfr_addr = info->ide_addr + 0x1800;
550 info->ide_addr += 0x1900; 545 info->ide_addr += 0x1900;
551 info->fifo_status_reg = 0x94; 546 info->fifo_status_reg = 0x94;
552 } else if (cpu_type == TYPE_S5PC100) {
553 ap->ops = &pata_s5p_port_ops;
554 info->sfr_addr = info->ide_addr + 0x1800;
555 info->ide_addr += 0x1900;
556 info->fifo_status_reg = 0x84;
557 } else { 547 } else {
558 ap->ops = &pata_s5p_port_ops; 548 ap->ops = &pata_s5p_port_ops;
559 info->fifo_status_reg = 0x84; 549 info->fifo_status_reg = 0x84;
@@ -653,9 +643,6 @@ static struct platform_device_id pata_s3c_driver_ids[] = {
653 .name = "s3c64xx-pata", 643 .name = "s3c64xx-pata",
654 .driver_data = TYPE_S3C64XX, 644 .driver_data = TYPE_S3C64XX,
655 }, { 645 }, {
656 .name = "s5pc100-pata",
657 .driver_data = TYPE_S5PC100,
658 }, {
659 .name = "s5pv210-pata", 646 .name = "s5pv210-pata",
660 .driver_data = TYPE_S5PV210, 647 .driver_data = TYPE_S5PV210,
661 }, 648 },
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index 616a6d2ac20c..07bc7e4dbd04 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -734,13 +734,12 @@ static int sata_fsl_port_start(struct ata_port *ap)
734 if (!pp) 734 if (!pp)
735 return -ENOMEM; 735 return -ENOMEM;
736 736
737 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 737 mem = dma_zalloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
738 GFP_KERNEL); 738 GFP_KERNEL);
739 if (!mem) { 739 if (!mem) {
740 kfree(pp); 740 kfree(pp);
741 return -ENOMEM; 741 return -ENOMEM;
742 } 742 }
743 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
744 743
745 pp->cmdslot = mem; 744 pp->cmdslot = mem;
746 pp->cmdslot_paddr = mem_dma; 745 pp->cmdslot_paddr = mem_dma;
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index 65965cf5af06..da3bc2709c63 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -512,7 +512,7 @@ static int ahci_highbank_probe(struct platform_device *pdev)
512 return rc; 512 return rc;
513 513
514 514
515 ahci_save_initial_config(dev, hpriv, 0, 0); 515 ahci_save_initial_config(dev, hpriv);
516 516
517 /* prepare host */ 517 /* prepare host */
518 if (hpriv->cap & HOST_CAP_NCQ) 518 if (hpriv->cap & HOST_CAP_NCQ)
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c
index 0534890f118a..d81b20ddb527 100644
--- a/drivers/ata/sata_sil24.c
+++ b/drivers/ata/sata_sil24.c
@@ -1154,8 +1154,8 @@ static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1154 status = readl(host_base + HOST_IRQ_STAT); 1154 status = readl(host_base + HOST_IRQ_STAT);
1155 1155
1156 if (status == 0xffffffff) { 1156 if (status == 0xffffffff) {
1157 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " 1157 dev_err(host->dev, "IRQ status == 0xffffffff, "
1158 "PCI fault or device removal?\n"); 1158 "PCI fault or device removal?\n");
1159 goto out; 1159 goto out;
1160 } 1160 }
1161 1161
diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
index 6dfd51a04d77..09a947e8bc87 100644
--- a/include/linux/ahci_platform.h
+++ b/include/linux/ahci_platform.h
@@ -43,10 +43,7 @@ struct ahci_host_priv *ahci_platform_get_resources(
43 struct platform_device *pdev); 43 struct platform_device *pdev);
44int ahci_platform_init_host(struct platform_device *pdev, 44int ahci_platform_init_host(struct platform_device *pdev,
45 struct ahci_host_priv *hpriv, 45 struct ahci_host_priv *hpriv,
46 const struct ata_port_info *pi_template, 46 const struct ata_port_info *pi_template);
47 unsigned long host_flags,
48 unsigned int force_port_map,
49 unsigned int mask_port_map);
50 47
51int ahci_platform_suspend_host(struct device *dev); 48int ahci_platform_suspend_host(struct device *dev);
52int ahci_platform_resume_host(struct device *dev); 49int ahci_platform_resume_host(struct device *dev);
diff --git a/include/linux/platform_data/ata-samsung_cf.h b/include/linux/platform_data/ata-samsung_cf.h
index c2049e3d7444..748e71642c4a 100644
--- a/include/linux/platform_data/ata-samsung_cf.h
+++ b/include/linux/platform_data/ata-samsung_cf.h
@@ -29,7 +29,6 @@ extern void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata);
29 29
30/* architecture-specific IDE configuration */ 30/* architecture-specific IDE configuration */
31extern void s3c64xx_ide_setup_gpio(void); 31extern void s3c64xx_ide_setup_gpio(void);
32extern void s5pc100_ide_setup_gpio(void);
33extern void s5pv210_ide_setup_gpio(void); 32extern void s5pv210_ide_setup_gpio(void);
34 33
35#endif /*__ATA_SAMSUNG_CF_H */ 34#endif /*__ATA_SAMSUNG_CF_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-05 00:08:01 -0400