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-rw-r--r--drivers/net/can/Kconfig6
-rw-r--r--drivers/net/can/Makefile1
-rw-r--r--drivers/net/can/mcp251x.c1164
-rw-r--r--include/linux/can/platform/mcp251x.h36
4 files changed, 1207 insertions, 0 deletions
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 26d77cc0ded7..b819cc2a429e 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -102,6 +102,12 @@ config CAN_TI_HECC
102 Driver for TI HECC (High End CAN Controller) module found on many 102 Driver for TI HECC (High End CAN Controller) module found on many
103 TI devices. The device specifications are available from www.ti.com 103 TI devices. The device specifications are available from www.ti.com
104 104
105config CAN_MCP251X
106 tristate "Microchip MCP251x SPI CAN controllers"
107 depends on CAN_DEV && SPI
108 ---help---
109 Driver for the Microchip MCP251x SPI CAN controllers.
110
105config CAN_DEBUG_DEVICES 111config CAN_DEBUG_DEVICES
106 bool "CAN devices debugging messages" 112 bool "CAN devices debugging messages"
107 depends on CAN 113 depends on CAN
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 31f4ab5df28b..14891817ea5b 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -12,5 +12,6 @@ obj-y += usb/
12obj-$(CONFIG_CAN_SJA1000) += sja1000/ 12obj-$(CONFIG_CAN_SJA1000) += sja1000/
13obj-$(CONFIG_CAN_AT91) += at91_can.o 13obj-$(CONFIG_CAN_AT91) += at91_can.o
14obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o 14obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o
15obj-$(CONFIG_CAN_MCP251X) += mcp251x.o
15 16
16ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG 17ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/mcp251x.c b/drivers/net/can/mcp251x.c
new file mode 100644
index 000000000000..8f48f4b50b7c
--- /dev/null
+++ b/drivers/net/can/mcp251x.c
@@ -0,0 +1,1164 @@
1/*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 *
34 *
35 *
36 * Your platform definition file should specify something like:
37 *
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .model = CAN_MCP251X_MCP2510,
42 * .power_enable = mcp251x_power_enable,
43 * .transceiver_enable = NULL,
44 * };
45 *
46 * static struct spi_board_info spi_board_info[] = {
47 * {
48 * .modalias = "mcp251x",
49 * .platform_data = &mcp251x_info,
50 * .irq = IRQ_EINT13,
51 * .max_speed_hz = 2*1000*1000,
52 * .chip_select = 2,
53 * },
54 * };
55 *
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
58 *
59 */
60
61#include <linux/can.h>
62#include <linux/can/core.h>
63#include <linux/can/dev.h>
64#include <linux/can/platform/mcp251x.h>
65#include <linux/completion.h>
66#include <linux/delay.h>
67#include <linux/device.h>
68#include <linux/dma-mapping.h>
69#include <linux/freezer.h>
70#include <linux/interrupt.h>
71#include <linux/io.h>
72#include <linux/kernel.h>
73#include <linux/module.h>
74#include <linux/netdevice.h>
75#include <linux/platform_device.h>
76#include <linux/spi/spi.h>
77#include <linux/uaccess.h>
78
79/* SPI interface instruction set */
80#define INSTRUCTION_WRITE 0x02
81#define INSTRUCTION_READ 0x03
82#define INSTRUCTION_BIT_MODIFY 0x05
83#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85#define INSTRUCTION_RESET 0xC0
86
87/* MPC251x registers */
88#define CANSTAT 0x0e
89#define CANCTRL 0x0f
90# define CANCTRL_REQOP_MASK 0xe0
91# define CANCTRL_REQOP_CONF 0x80
92# define CANCTRL_REQOP_LISTEN_ONLY 0x60
93# define CANCTRL_REQOP_LOOPBACK 0x40
94# define CANCTRL_REQOP_SLEEP 0x20
95# define CANCTRL_REQOP_NORMAL 0x00
96# define CANCTRL_OSM 0x08
97# define CANCTRL_ABAT 0x10
98#define TEC 0x1c
99#define REC 0x1d
100#define CNF1 0x2a
101# define CNF1_SJW_SHIFT 6
102#define CNF2 0x29
103# define CNF2_BTLMODE 0x80
104# define CNF2_SAM 0x40
105# define CNF2_PS1_SHIFT 3
106#define CNF3 0x28
107# define CNF3_SOF 0x08
108# define CNF3_WAKFIL 0x04
109# define CNF3_PHSEG2_MASK 0x07
110#define CANINTE 0x2b
111# define CANINTE_MERRE 0x80
112# define CANINTE_WAKIE 0x40
113# define CANINTE_ERRIE 0x20
114# define CANINTE_TX2IE 0x10
115# define CANINTE_TX1IE 0x08
116# define CANINTE_TX0IE 0x04
117# define CANINTE_RX1IE 0x02
118# define CANINTE_RX0IE 0x01
119#define CANINTF 0x2c
120# define CANINTF_MERRF 0x80
121# define CANINTF_WAKIF 0x40
122# define CANINTF_ERRIF 0x20
123# define CANINTF_TX2IF 0x10
124# define CANINTF_TX1IF 0x08
125# define CANINTF_TX0IF 0x04
126# define CANINTF_RX1IF 0x02
127# define CANINTF_RX0IF 0x01
128#define EFLG 0x2d
129# define EFLG_EWARN 0x01
130# define EFLG_RXWAR 0x02
131# define EFLG_TXWAR 0x04
132# define EFLG_RXEP 0x08
133# define EFLG_TXEP 0x10
134# define EFLG_TXBO 0x20
135# define EFLG_RX0OVR 0x40
136# define EFLG_RX1OVR 0x80
137#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
138# define TXBCTRL_ABTF 0x40
139# define TXBCTRL_MLOA 0x20
140# define TXBCTRL_TXERR 0x10
141# define TXBCTRL_TXREQ 0x08
142#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
143# define SIDH_SHIFT 3
144#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
145# define SIDL_SID_MASK 7
146# define SIDL_SID_SHIFT 5
147# define SIDL_EXIDE_SHIFT 3
148# define SIDL_EID_SHIFT 16
149# define SIDL_EID_MASK 3
150#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
151#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
152#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
153# define DLC_RTR_SHIFT 6
154#define TXBCTRL_OFF 0
155#define TXBSIDH_OFF 1
156#define TXBSIDL_OFF 2
157#define TXBEID8_OFF 3
158#define TXBEID0_OFF 4
159#define TXBDLC_OFF 5
160#define TXBDAT_OFF 6
161#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
162# define RXBCTRL_BUKT 0x04
163# define RXBCTRL_RXM0 0x20
164# define RXBCTRL_RXM1 0x40
165#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
166# define RXBSIDH_SHIFT 3
167#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
168# define RXBSIDL_IDE 0x08
169# define RXBSIDL_EID 3
170# define RXBSIDL_SHIFT 5
171#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
172#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
173#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
174# define RXBDLC_LEN_MASK 0x0f
175# define RXBDLC_RTR 0x40
176#define RXBCTRL_OFF 0
177#define RXBSIDH_OFF 1
178#define RXBSIDL_OFF 2
179#define RXBEID8_OFF 3
180#define RXBEID0_OFF 4
181#define RXBDLC_OFF 5
182#define RXBDAT_OFF 6
183
184#define GET_BYTE(val, byte) \
185 (((val) >> ((byte) * 8)) & 0xff)
186#define SET_BYTE(val, byte) \
187 (((val) & 0xff) << ((byte) * 8))
188
189/*
190 * Buffer size required for the largest SPI transfer (i.e., reading a
191 * frame)
192 */
193#define CAN_FRAME_MAX_DATA_LEN 8
194#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
195#define CAN_FRAME_MAX_BITS 128
196
197#define TX_ECHO_SKB_MAX 1
198
199#define DEVICE_NAME "mcp251x"
200
201static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
202module_param(mcp251x_enable_dma, int, S_IRUGO);
203MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
204
205static struct can_bittiming_const mcp251x_bittiming_const = {
206 .name = DEVICE_NAME,
207 .tseg1_min = 3,
208 .tseg1_max = 16,
209 .tseg2_min = 2,
210 .tseg2_max = 8,
211 .sjw_max = 4,
212 .brp_min = 1,
213 .brp_max = 64,
214 .brp_inc = 1,
215};
216
217struct mcp251x_priv {
218 struct can_priv can;
219 struct net_device *net;
220 struct spi_device *spi;
221
222 struct mutex spi_lock; /* SPI buffer lock */
223 u8 *spi_tx_buf;
224 u8 *spi_rx_buf;
225 dma_addr_t spi_tx_dma;
226 dma_addr_t spi_rx_dma;
227
228 struct sk_buff *tx_skb;
229 int tx_len;
230 struct workqueue_struct *wq;
231 struct work_struct tx_work;
232 struct work_struct irq_work;
233 struct completion awake;
234 int wake;
235 int force_quit;
236 int after_suspend;
237#define AFTER_SUSPEND_UP 1
238#define AFTER_SUSPEND_DOWN 2
239#define AFTER_SUSPEND_POWER 4
240#define AFTER_SUSPEND_RESTART 8
241 int restart_tx;
242};
243
244static void mcp251x_clean(struct net_device *net)
245{
246 struct mcp251x_priv *priv = netdev_priv(net);
247
248 net->stats.tx_errors++;
249 if (priv->tx_skb)
250 dev_kfree_skb(priv->tx_skb);
251 if (priv->tx_len)
252 can_free_echo_skb(priv->net, 0);
253 priv->tx_skb = NULL;
254 priv->tx_len = 0;
255}
256
257/*
258 * Note about handling of error return of mcp251x_spi_trans: accessing
259 * registers via SPI is not really different conceptually than using
260 * normal I/O assembler instructions, although it's much more
261 * complicated from a practical POV. So it's not advisable to always
262 * check the return value of this function. Imagine that every
263 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
264 * error();", it would be a great mess (well there are some situation
265 * when exception handling C++ like could be useful after all). So we
266 * just check that transfers are OK at the beginning of our
267 * conversation with the chip and to avoid doing really nasty things
268 * (like injecting bogus packets in the network stack).
269 */
270static int mcp251x_spi_trans(struct spi_device *spi, int len)
271{
272 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
273 struct spi_transfer t = {
274 .tx_buf = priv->spi_tx_buf,
275 .rx_buf = priv->spi_rx_buf,
276 .len = len,
277 .cs_change = 0,
278 };
279 struct spi_message m;
280 int ret;
281
282 spi_message_init(&m);
283
284 if (mcp251x_enable_dma) {
285 t.tx_dma = priv->spi_tx_dma;
286 t.rx_dma = priv->spi_rx_dma;
287 m.is_dma_mapped = 1;
288 }
289
290 spi_message_add_tail(&t, &m);
291
292 ret = spi_sync(spi, &m);
293 if (ret)
294 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
295 return ret;
296}
297
298static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
299{
300 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
301 u8 val = 0;
302
303 mutex_lock(&priv->spi_lock);
304
305 priv->spi_tx_buf[0] = INSTRUCTION_READ;
306 priv->spi_tx_buf[1] = reg;
307
308 mcp251x_spi_trans(spi, 3);
309 val = priv->spi_rx_buf[2];
310
311 mutex_unlock(&priv->spi_lock);
312
313 return val;
314}
315
316static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
317{
318 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
319
320 mutex_lock(&priv->spi_lock);
321
322 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
323 priv->spi_tx_buf[1] = reg;
324 priv->spi_tx_buf[2] = val;
325
326 mcp251x_spi_trans(spi, 3);
327
328 mutex_unlock(&priv->spi_lock);
329}
330
331static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
332 u8 mask, uint8_t val)
333{
334 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
335
336 mutex_lock(&priv->spi_lock);
337
338 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
339 priv->spi_tx_buf[1] = reg;
340 priv->spi_tx_buf[2] = mask;
341 priv->spi_tx_buf[3] = val;
342
343 mcp251x_spi_trans(spi, 4);
344
345 mutex_unlock(&priv->spi_lock);
346}
347
348static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
349 int len, int tx_buf_idx)
350{
351 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
352 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
353
354 if (pdata->model == CAN_MCP251X_MCP2510) {
355 int i;
356
357 for (i = 1; i < TXBDAT_OFF + len; i++)
358 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
359 buf[i]);
360 } else {
361 mutex_lock(&priv->spi_lock);
362 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
363 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
364 mutex_unlock(&priv->spi_lock);
365 }
366}
367
368static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
369 int tx_buf_idx)
370{
371 u32 sid, eid, exide, rtr;
372 u8 buf[SPI_TRANSFER_BUF_LEN];
373
374 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
375 if (exide)
376 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
377 else
378 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
379 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
380 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
381
382 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
383 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
384 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
385 (exide << SIDL_EXIDE_SHIFT) |
386 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
387 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
388 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
389 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
390 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
391 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
392 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
393}
394
395static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
396 int buf_idx)
397{
398 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
399 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
400
401 if (pdata->model == CAN_MCP251X_MCP2510) {
402 int i, len;
403
404 for (i = 1; i < RXBDAT_OFF; i++)
405 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
406 len = buf[RXBDLC_OFF] & RXBDLC_LEN_MASK;
407 if (len > 8)
408 len = 8;
409 for (; i < (RXBDAT_OFF + len); i++)
410 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
411 } else {
412 mutex_lock(&priv->spi_lock);
413
414 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
415 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
416 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
417
418 mutex_unlock(&priv->spi_lock);
419 }
420}
421
422static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
423{
424 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
425 struct sk_buff *skb;
426 struct can_frame *frame;
427 u8 buf[SPI_TRANSFER_BUF_LEN];
428
429 skb = alloc_can_skb(priv->net, &frame);
430 if (!skb) {
431 dev_err(&spi->dev, "cannot allocate RX skb\n");
432 priv->net->stats.rx_dropped++;
433 return;
434 }
435
436 mcp251x_hw_rx_frame(spi, buf, buf_idx);
437 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
438 /* Extended ID format */
439 frame->can_id = CAN_EFF_FLAG;
440 frame->can_id |=
441 /* Extended ID part */
442 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
443 SET_BYTE(buf[RXBEID8_OFF], 1) |
444 SET_BYTE(buf[RXBEID0_OFF], 0) |
445 /* Standard ID part */
446 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
447 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
448 /* Remote transmission request */
449 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
450 frame->can_id |= CAN_RTR_FLAG;
451 } else {
452 /* Standard ID format */
453 frame->can_id =
454 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
455 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
456 }
457 /* Data length */
458 frame->can_dlc = buf[RXBDLC_OFF] & RXBDLC_LEN_MASK;
459 if (frame->can_dlc > 8) {
460 dev_warn(&spi->dev, "invalid frame recevied\n");
461 priv->net->stats.rx_errors++;
462 dev_kfree_skb(skb);
463 return;
464 }
465 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
466
467 priv->net->stats.rx_packets++;
468 priv->net->stats.rx_bytes += frame->can_dlc;
469 netif_rx(skb);
470}
471
472static void mcp251x_hw_sleep(struct spi_device *spi)
473{
474 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
475}
476
477static void mcp251x_hw_wakeup(struct spi_device *spi)
478{
479 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
480
481 priv->wake = 1;
482
483 /* Can only wake up by generating a wake-up interrupt. */
484 mcp251x_write_bits(spi, CANINTE, CANINTE_WAKIE, CANINTE_WAKIE);
485 mcp251x_write_bits(spi, CANINTF, CANINTF_WAKIF, CANINTF_WAKIF);
486
487 /* Wait until the device is awake */
488 if (!wait_for_completion_timeout(&priv->awake, HZ))
489 dev_err(&spi->dev, "MCP251x didn't wake-up\n");
490}
491
492static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
493 struct net_device *net)
494{
495 struct mcp251x_priv *priv = netdev_priv(net);
496 struct spi_device *spi = priv->spi;
497
498 if (priv->tx_skb || priv->tx_len) {
499 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
500 netif_stop_queue(net);
501 return NETDEV_TX_BUSY;
502 }
503
504 if (skb->len != sizeof(struct can_frame)) {
505 dev_err(&spi->dev, "dropping packet - bad length\n");
506 dev_kfree_skb(skb);
507 net->stats.tx_dropped++;
508 return NETDEV_TX_OK;
509 }
510
511 netif_stop_queue(net);
512 priv->tx_skb = skb;
513 net->trans_start = jiffies;
514 queue_work(priv->wq, &priv->tx_work);
515
516 return NETDEV_TX_OK;
517}
518
519static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
520{
521 struct mcp251x_priv *priv = netdev_priv(net);
522
523 switch (mode) {
524 case CAN_MODE_START:
525 /* We have to delay work since SPI I/O may sleep */
526 priv->can.state = CAN_STATE_ERROR_ACTIVE;
527 priv->restart_tx = 1;
528 if (priv->can.restart_ms == 0)
529 priv->after_suspend = AFTER_SUSPEND_RESTART;
530 queue_work(priv->wq, &priv->irq_work);
531 break;
532 default:
533 return -EOPNOTSUPP;
534 }
535
536 return 0;
537}
538
539static void mcp251x_set_normal_mode(struct spi_device *spi)
540{
541 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
542 unsigned long timeout;
543
544 /* Enable interrupts */
545 mcp251x_write_reg(spi, CANINTE,
546 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
547 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE |
548 CANINTF_MERRF);
549
550 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
551 /* Put device into loopback mode */
552 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
553 } else {
554 /* Put device into normal mode */
555 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
556
557 /* Wait for the device to enter normal mode */
558 timeout = jiffies + HZ;
559 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
560 schedule();
561 if (time_after(jiffies, timeout)) {
562 dev_err(&spi->dev, "MCP251x didn't"
563 " enter in normal mode\n");
564 return;
565 }
566 }
567 }
568 priv->can.state = CAN_STATE_ERROR_ACTIVE;
569}
570
571static int mcp251x_do_set_bittiming(struct net_device *net)
572{
573 struct mcp251x_priv *priv = netdev_priv(net);
574 struct can_bittiming *bt = &priv->can.bittiming;
575 struct spi_device *spi = priv->spi;
576
577 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
578 (bt->brp - 1));
579 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
580 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
581 CNF2_SAM : 0) |
582 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
583 (bt->prop_seg - 1));
584 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
585 (bt->phase_seg2 - 1));
586 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
587 mcp251x_read_reg(spi, CNF1),
588 mcp251x_read_reg(spi, CNF2),
589 mcp251x_read_reg(spi, CNF3));
590
591 return 0;
592}
593
594static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
595 struct spi_device *spi)
596{
597 int ret;
598
599 ret = open_candev(net);
600 if (ret) {
601 dev_err(&spi->dev, "unable to set initial baudrate!\n");
602 return ret;
603 }
604
605 /* Enable RX0->RX1 buffer roll over and disable filters */
606 mcp251x_write_bits(spi, RXBCTRL(0),
607 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1,
608 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
609 mcp251x_write_bits(spi, RXBCTRL(1),
610 RXBCTRL_RXM0 | RXBCTRL_RXM1,
611 RXBCTRL_RXM0 | RXBCTRL_RXM1);
612 return 0;
613}
614
615static void mcp251x_hw_reset(struct spi_device *spi)
616{
617 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
618 int ret;
619
620 mutex_lock(&priv->spi_lock);
621
622 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
623
624 ret = spi_write(spi, priv->spi_tx_buf, 1);
625
626 mutex_unlock(&priv->spi_lock);
627
628 if (ret)
629 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
630 /* Wait for reset to finish */
631 mdelay(10);
632}
633
634static int mcp251x_hw_probe(struct spi_device *spi)
635{
636 int st1, st2;
637
638 mcp251x_hw_reset(spi);
639
640 /*
641 * Please note that these are "magic values" based on after
642 * reset defaults taken from data sheet which allows us to see
643 * if we really have a chip on the bus (we avoid common all
644 * zeroes or all ones situations)
645 */
646 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
647 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
648
649 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
650
651 /* Check for power up default values */
652 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
653}
654
655static irqreturn_t mcp251x_can_isr(int irq, void *dev_id)
656{
657 struct net_device *net = (struct net_device *)dev_id;
658 struct mcp251x_priv *priv = netdev_priv(net);
659
660 /* Schedule bottom half */
661 if (!work_pending(&priv->irq_work))
662 queue_work(priv->wq, &priv->irq_work);
663
664 return IRQ_HANDLED;
665}
666
667static int mcp251x_open(struct net_device *net)
668{
669 struct mcp251x_priv *priv = netdev_priv(net);
670 struct spi_device *spi = priv->spi;
671 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
672 int ret;
673
674 if (pdata->transceiver_enable)
675 pdata->transceiver_enable(1);
676
677 priv->force_quit = 0;
678 priv->tx_skb = NULL;
679 priv->tx_len = 0;
680
681 ret = request_irq(spi->irq, mcp251x_can_isr,
682 IRQF_TRIGGER_FALLING, DEVICE_NAME, net);
683 if (ret) {
684 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
685 if (pdata->transceiver_enable)
686 pdata->transceiver_enable(0);
687 return ret;
688 }
689
690 mcp251x_hw_wakeup(spi);
691 mcp251x_hw_reset(spi);
692 ret = mcp251x_setup(net, priv, spi);
693 if (ret) {
694 free_irq(spi->irq, net);
695 if (pdata->transceiver_enable)
696 pdata->transceiver_enable(0);
697 return ret;
698 }
699 mcp251x_set_normal_mode(spi);
700 netif_wake_queue(net);
701
702 return 0;
703}
704
705static int mcp251x_stop(struct net_device *net)
706{
707 struct mcp251x_priv *priv = netdev_priv(net);
708 struct spi_device *spi = priv->spi;
709 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
710
711 close_candev(net);
712
713 /* Disable and clear pending interrupts */
714 mcp251x_write_reg(spi, CANINTE, 0x00);
715 mcp251x_write_reg(spi, CANINTF, 0x00);
716
717 priv->force_quit = 1;
718 free_irq(spi->irq, net);
719 flush_workqueue(priv->wq);
720
721 mcp251x_write_reg(spi, TXBCTRL(0), 0);
722 if (priv->tx_skb || priv->tx_len)
723 mcp251x_clean(net);
724
725 mcp251x_hw_sleep(spi);
726
727 if (pdata->transceiver_enable)
728 pdata->transceiver_enable(0);
729
730 priv->can.state = CAN_STATE_STOPPED;
731
732 return 0;
733}
734
735static void mcp251x_tx_work_handler(struct work_struct *ws)
736{
737 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
738 tx_work);
739 struct spi_device *spi = priv->spi;
740 struct net_device *net = priv->net;
741 struct can_frame *frame;
742
743 if (priv->tx_skb) {
744 frame = (struct can_frame *)priv->tx_skb->data;
745
746 if (priv->can.state == CAN_STATE_BUS_OFF) {
747 mcp251x_clean(net);
748 netif_wake_queue(net);
749 return;
750 }
751 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
752 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
753 mcp251x_hw_tx(spi, frame, 0);
754 priv->tx_len = 1 + frame->can_dlc;
755 can_put_echo_skb(priv->tx_skb, net, 0);
756 priv->tx_skb = NULL;
757 }
758}
759
760static void mcp251x_irq_work_handler(struct work_struct *ws)
761{
762 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
763 irq_work);
764 struct spi_device *spi = priv->spi;
765 struct net_device *net = priv->net;
766 u8 txbnctrl;
767 u8 intf;
768 enum can_state new_state;
769
770 if (priv->after_suspend) {
771 mdelay(10);
772 mcp251x_hw_reset(spi);
773 mcp251x_setup(net, priv, spi);
774 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
775 mcp251x_set_normal_mode(spi);
776 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
777 netif_device_attach(net);
778 /* Clean since we lost tx buffer */
779 if (priv->tx_skb || priv->tx_len) {
780 mcp251x_clean(net);
781 netif_wake_queue(net);
782 }
783 mcp251x_set_normal_mode(spi);
784 } else {
785 mcp251x_hw_sleep(spi);
786 }
787 priv->after_suspend = 0;
788 }
789
790 if (priv->can.restart_ms == 0 && priv->can.state == CAN_STATE_BUS_OFF)
791 return;
792
793 while (!priv->force_quit && !freezing(current)) {
794 u8 eflag = mcp251x_read_reg(spi, EFLG);
795 int can_id = 0, data1 = 0;
796
797 mcp251x_write_reg(spi, EFLG, 0x00);
798
799 if (priv->restart_tx) {
800 priv->restart_tx = 0;
801 mcp251x_write_reg(spi, TXBCTRL(0), 0);
802 if (priv->tx_skb || priv->tx_len)
803 mcp251x_clean(net);
804 netif_wake_queue(net);
805 can_id |= CAN_ERR_RESTARTED;
806 }
807
808 if (priv->wake) {
809 /* Wait whilst the device wakes up */
810 mdelay(10);
811 priv->wake = 0;
812 }
813
814 intf = mcp251x_read_reg(spi, CANINTF);
815 mcp251x_write_bits(spi, CANINTF, intf, 0x00);
816
817 /* Update can state */
818 if (eflag & EFLG_TXBO) {
819 new_state = CAN_STATE_BUS_OFF;
820 can_id |= CAN_ERR_BUSOFF;
821 } else if (eflag & EFLG_TXEP) {
822 new_state = CAN_STATE_ERROR_PASSIVE;
823 can_id |= CAN_ERR_CRTL;
824 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
825 } else if (eflag & EFLG_RXEP) {
826 new_state = CAN_STATE_ERROR_PASSIVE;
827 can_id |= CAN_ERR_CRTL;
828 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
829 } else if (eflag & EFLG_TXWAR) {
830 new_state = CAN_STATE_ERROR_WARNING;
831 can_id |= CAN_ERR_CRTL;
832 data1 |= CAN_ERR_CRTL_TX_WARNING;
833 } else if (eflag & EFLG_RXWAR) {
834 new_state = CAN_STATE_ERROR_WARNING;
835 can_id |= CAN_ERR_CRTL;
836 data1 |= CAN_ERR_CRTL_RX_WARNING;
837 } else {
838 new_state = CAN_STATE_ERROR_ACTIVE;
839 }
840
841 /* Update can state statistics */
842 switch (priv->can.state) {
843 case CAN_STATE_ERROR_ACTIVE:
844 if (new_state >= CAN_STATE_ERROR_WARNING &&
845 new_state <= CAN_STATE_BUS_OFF)
846 priv->can.can_stats.error_warning++;
847 case CAN_STATE_ERROR_WARNING: /* fallthrough */
848 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
849 new_state <= CAN_STATE_BUS_OFF)
850 priv->can.can_stats.error_passive++;
851 break;
852 default:
853 break;
854 }
855 priv->can.state = new_state;
856
857 if ((intf & CANINTF_ERRIF) || (can_id & CAN_ERR_RESTARTED)) {
858 struct sk_buff *skb;
859 struct can_frame *frame;
860
861 /* Create error frame */
862 skb = alloc_can_err_skb(net, &frame);
863 if (skb) {
864 /* Set error frame flags based on bus state */
865 frame->can_id = can_id;
866 frame->data[1] = data1;
867
868 /* Update net stats for overflows */
869 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
870 if (eflag & EFLG_RX0OVR)
871 net->stats.rx_over_errors++;
872 if (eflag & EFLG_RX1OVR)
873 net->stats.rx_over_errors++;
874 frame->can_id |= CAN_ERR_CRTL;
875 frame->data[1] |=
876 CAN_ERR_CRTL_RX_OVERFLOW;
877 }
878
879 netif_rx(skb);
880 } else {
881 dev_info(&spi->dev,
882 "cannot allocate error skb\n");
883 }
884 }
885
886 if (priv->can.state == CAN_STATE_BUS_OFF) {
887 if (priv->can.restart_ms == 0) {
888 can_bus_off(net);
889 mcp251x_hw_sleep(spi);
890 return;
891 }
892 }
893
894 if (intf == 0)
895 break;
896
897 if (intf & CANINTF_WAKIF)
898 complete(&priv->awake);
899
900 if (intf & CANINTF_MERRF) {
901 /* If there are pending Tx buffers, restart queue */
902 txbnctrl = mcp251x_read_reg(spi, TXBCTRL(0));
903 if (!(txbnctrl & TXBCTRL_TXREQ)) {
904 if (priv->tx_skb || priv->tx_len)
905 mcp251x_clean(net);
906 netif_wake_queue(net);
907 }
908 }
909
910 if (intf & (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)) {
911 net->stats.tx_packets++;
912 net->stats.tx_bytes += priv->tx_len - 1;
913 if (priv->tx_len) {
914 can_get_echo_skb(net, 0);
915 priv->tx_len = 0;
916 }
917 netif_wake_queue(net);
918 }
919
920 if (intf & CANINTF_RX0IF)
921 mcp251x_hw_rx(spi, 0);
922
923 if (intf & CANINTF_RX1IF)
924 mcp251x_hw_rx(spi, 1);
925 }
926}
927
928static const struct net_device_ops mcp251x_netdev_ops = {
929 .ndo_open = mcp251x_open,
930 .ndo_stop = mcp251x_stop,
931 .ndo_start_xmit = mcp251x_hard_start_xmit,
932};
933
934static int __devinit mcp251x_can_probe(struct spi_device *spi)
935{
936 struct net_device *net;
937 struct mcp251x_priv *priv;
938 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
939 int ret = -ENODEV;
940
941 if (!pdata)
942 /* Platform data is required for osc freq */
943 goto error_out;
944
945 /* Allocate can/net device */
946 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
947 if (!net) {
948 ret = -ENOMEM;
949 goto error_alloc;
950 }
951
952 net->netdev_ops = &mcp251x_netdev_ops;
953 net->flags |= IFF_ECHO;
954
955 priv = netdev_priv(net);
956 priv->can.bittiming_const = &mcp251x_bittiming_const;
957 priv->can.do_set_mode = mcp251x_do_set_mode;
958 priv->can.clock.freq = pdata->oscillator_frequency / 2;
959 priv->can.do_set_bittiming = mcp251x_do_set_bittiming;
960 priv->net = net;
961 dev_set_drvdata(&spi->dev, priv);
962
963 priv->spi = spi;
964 mutex_init(&priv->spi_lock);
965
966 /* If requested, allocate DMA buffers */
967 if (mcp251x_enable_dma) {
968 spi->dev.coherent_dma_mask = ~0;
969
970 /*
971 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
972 * that much and share it between Tx and Rx DMA buffers.
973 */
974 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
975 PAGE_SIZE,
976 &priv->spi_tx_dma,
977 GFP_DMA);
978
979 if (priv->spi_tx_buf) {
980 priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf +
981 (PAGE_SIZE / 2));
982 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
983 (PAGE_SIZE / 2));
984 } else {
985 /* Fall back to non-DMA */
986 mcp251x_enable_dma = 0;
987 }
988 }
989
990 /* Allocate non-DMA buffers */
991 if (!mcp251x_enable_dma) {
992 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
993 if (!priv->spi_tx_buf) {
994 ret = -ENOMEM;
995 goto error_tx_buf;
996 }
997 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
998 if (!priv->spi_tx_buf) {
999 ret = -ENOMEM;
1000 goto error_rx_buf;
1001 }
1002 }
1003
1004 if (pdata->power_enable)
1005 pdata->power_enable(1);
1006
1007 /* Call out to platform specific setup */
1008 if (pdata->board_specific_setup)
1009 pdata->board_specific_setup(spi);
1010
1011 SET_NETDEV_DEV(net, &spi->dev);
1012
1013 priv->wq = create_freezeable_workqueue("mcp251x_wq");
1014
1015 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
1016 INIT_WORK(&priv->irq_work, mcp251x_irq_work_handler);
1017
1018 init_completion(&priv->awake);
1019
1020 /* Configure the SPI bus */
1021 spi->mode = SPI_MODE_0;
1022 spi->bits_per_word = 8;
1023 spi_setup(spi);
1024
1025 if (!mcp251x_hw_probe(spi)) {
1026 dev_info(&spi->dev, "Probe failed\n");
1027 goto error_probe;
1028 }
1029 mcp251x_hw_sleep(spi);
1030
1031 if (pdata->transceiver_enable)
1032 pdata->transceiver_enable(0);
1033
1034 ret = register_candev(net);
1035 if (!ret) {
1036 dev_info(&spi->dev, "probed\n");
1037 return ret;
1038 }
1039error_probe:
1040 if (!mcp251x_enable_dma)
1041 kfree(priv->spi_rx_buf);
1042error_rx_buf:
1043 if (!mcp251x_enable_dma)
1044 kfree(priv->spi_tx_buf);
1045error_tx_buf:
1046 free_candev(net);
1047 if (mcp251x_enable_dma)
1048 dma_free_coherent(&spi->dev, PAGE_SIZE,
1049 priv->spi_tx_buf, priv->spi_tx_dma);
1050error_alloc:
1051 if (pdata->power_enable)
1052 pdata->power_enable(0);
1053 dev_err(&spi->dev, "probe failed\n");
1054error_out:
1055 return ret;
1056}
1057
1058static int __devexit mcp251x_can_remove(struct spi_device *spi)
1059{
1060 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1061 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1062 struct net_device *net = priv->net;
1063
1064 unregister_candev(net);
1065 free_candev(net);
1066
1067 priv->force_quit = 1;
1068 flush_workqueue(priv->wq);
1069 destroy_workqueue(priv->wq);
1070
1071 if (mcp251x_enable_dma) {
1072 dma_free_coherent(&spi->dev, PAGE_SIZE,
1073 priv->spi_tx_buf, priv->spi_tx_dma);
1074 } else {
1075 kfree(priv->spi_tx_buf);
1076 kfree(priv->spi_rx_buf);
1077 }
1078
1079 if (pdata->power_enable)
1080 pdata->power_enable(0);
1081
1082 return 0;
1083}
1084
1085#ifdef CONFIG_PM
1086static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1087{
1088 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1089 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1090 struct net_device *net = priv->net;
1091
1092 if (netif_running(net)) {
1093 netif_device_detach(net);
1094
1095 mcp251x_hw_sleep(spi);
1096 if (pdata->transceiver_enable)
1097 pdata->transceiver_enable(0);
1098 priv->after_suspend = AFTER_SUSPEND_UP;
1099 } else {
1100 priv->after_suspend = AFTER_SUSPEND_DOWN;
1101 }
1102
1103 if (pdata->power_enable) {
1104 pdata->power_enable(0);
1105 priv->after_suspend |= AFTER_SUSPEND_POWER;
1106 }
1107
1108 return 0;
1109}
1110
1111static int mcp251x_can_resume(struct spi_device *spi)
1112{
1113 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1114 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1115
1116 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1117 pdata->power_enable(1);
1118 queue_work(priv->wq, &priv->irq_work);
1119 } else {
1120 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1121 if (pdata->transceiver_enable)
1122 pdata->transceiver_enable(1);
1123 queue_work(priv->wq, &priv->irq_work);
1124 } else {
1125 priv->after_suspend = 0;
1126 }
1127 }
1128 return 0;
1129}
1130#else
1131#define mcp251x_can_suspend NULL
1132#define mcp251x_can_resume NULL
1133#endif
1134
1135static struct spi_driver mcp251x_can_driver = {
1136 .driver = {
1137 .name = DEVICE_NAME,
1138 .bus = &spi_bus_type,
1139 .owner = THIS_MODULE,
1140 },
1141
1142 .probe = mcp251x_can_probe,
1143 .remove = __devexit_p(mcp251x_can_remove),
1144 .suspend = mcp251x_can_suspend,
1145 .resume = mcp251x_can_resume,
1146};
1147
1148static int __init mcp251x_can_init(void)
1149{
1150 return spi_register_driver(&mcp251x_can_driver);
1151}
1152
1153static void __exit mcp251x_can_exit(void)
1154{
1155 spi_unregister_driver(&mcp251x_can_driver);
1156}
1157
1158module_init(mcp251x_can_init);
1159module_exit(mcp251x_can_exit);
1160
1161MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1162 "Christian Pellegrin <chripell@evolware.org>");
1163MODULE_DESCRIPTION("Microchip 251x CAN driver");
1164MODULE_LICENSE("GPL v2");
diff --git a/include/linux/can/platform/mcp251x.h b/include/linux/can/platform/mcp251x.h
new file mode 100644
index 000000000000..1448177d86d5
--- /dev/null
+++ b/include/linux/can/platform/mcp251x.h
@@ -0,0 +1,36 @@
1#ifndef __CAN_PLATFORM_MCP251X_H__
2#define __CAN_PLATFORM_MCP251X_H__
3
4/*
5 *
6 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
7 *
8 */
9
10#include <linux/spi/spi.h>
11
12/**
13 * struct mcp251x_platform_data - MCP251X SPI CAN controller platform data
14 * @oscillator_frequency: - oscillator frequency in Hz
15 * @model: - actual type of chip
16 * @board_specific_setup: - called before probing the chip (power,reset)
17 * @transceiver_enable: - called to power on/off the transceiver
18 * @power_enable: - called to power on/off the mcp *and* the
19 * transceiver
20 *
21 * Please note that you should define power_enable or transceiver_enable or
22 * none of them. Defining both of them is no use.
23 *
24 */
25
26struct mcp251x_platform_data {
27 unsigned long oscillator_frequency;
28 int model;
29#define CAN_MCP251X_MCP2510 0
30#define CAN_MCP251X_MCP2515 1
31 int (*board_specific_setup)(struct spi_device *spi);
32 int (*transceiver_enable)(int enable);
33 int (*power_enable) (int enable);
34};
35
36#endif /* __CAN_PLATFORM_MCP251X_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-19 21:38:21 -0400