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-rw-r--r--arch/i386/kernel/cpu/mcheck/k7.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/i386/kernel/cpu/mcheck/k7.c b/arch/i386/kernel/cpu/mcheck/k7.c
index b0862af595aa..7a2472557bbb 100644
--- a/arch/i386/kernel/cpu/mcheck/k7.c
+++ b/arch/i386/kernel/cpu/mcheck/k7.c
@@ -82,9 +82,13 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)
82 nr_mce_banks = l & 0xff; 82 nr_mce_banks = l & 0xff;
83 83
84 /* Clear status for MC index 0 separately, we don't touch CTL, 84 /* Clear status for MC index 0 separately, we don't touch CTL,
85 * as some Athlons cause spurious MCEs when its enabled. */ 85 * as some K7 Athlons cause spurious MCEs when its enabled. */
86 wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0); 86 if (boot_cpu_data.x86 == 6) {
87 for (i=1; i<nr_mce_banks; i++) { 87 wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
88 i = 1;
89 } else
90 i = 0;
91 for (; i<nr_mce_banks; i++) {
88 wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff); 92 wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
89 wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0); 93 wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
90 } 94 }