3 files changed, 6 insertions, 2 deletions

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 1ff88c7f45cf..aaa8101d3d80 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -301,6 +301,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         /* K6s reports MCEs but don't actually have all the MSRs */
         if (c->x86 < 6)
                 clear_bit(X86_FEATURE_MCE, c->x86_capability);
+
+        if (cpu_has_xmm)
+                set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
 }
 
 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 02409100f456..2139aa6ac469 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -746,8 +746,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
                 set_cpu_cap(c, X86_FEATURE_K8);
 
-        /* RDTSC can be speculated around */
-        clear_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
+        /* MFENCE stops RDTSC speculation */
+        set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 
         /* Family 10 doesn't support C states in MWAIT so don't use it */
         if (c->x86 == 0x10 && !force_mwait)
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 75e2f78a7fda..7d53eea8b946 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -79,6 +79,7 @@
 /* 14 free */
 #define X86_FEATURE_SYNC_RDTSC  (3*32+15)  /* RDTSC synchronizes the CPU */
 #define X86_FEATURE_REP_GOOD    (3*32+16) /* rep microcode works well on this CPU */
+#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */