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-rw-r--r--drivers/edac/edac_core.h350
-rw-r--r--include/linux/edac.h350
2 files changed, 351 insertions, 349 deletions
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h
index 55b8278bb172..fe90cd4a7ebc 100644
--- a/drivers/edac/edac_core.h
+++ b/drivers/edac/edac_core.h
@@ -34,11 +34,10 @@
34#include <linux/platform_device.h> 34#include <linux/platform_device.h>
35#include <linux/sysdev.h> 35#include <linux/sysdev.h>
36#include <linux/workqueue.h> 36#include <linux/workqueue.h>
37#include <linux/edac.h>
37 38
38#define EDAC_MC_LABEL_LEN 31
39#define EDAC_DEVICE_NAME_LEN 31 39#define EDAC_DEVICE_NAME_LEN 31
40#define EDAC_ATTRIB_VALUE_LEN 15 40#define EDAC_ATTRIB_VALUE_LEN 15
41#define MC_PROC_NAME_MAX_LEN 7
42 41
43#if PAGE_SHIFT < 20 42#if PAGE_SHIFT < 20
44#define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT)) 43#define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
@@ -101,353 +100,6 @@ extern int edac_debug_level;
101 100
102#define edac_dev_name(dev) (dev)->dev_name 101#define edac_dev_name(dev) (dev)->dev_name
103 102
104/* memory devices */
105enum dev_type {
106 DEV_UNKNOWN = 0,
107 DEV_X1,
108 DEV_X2,
109 DEV_X4,
110 DEV_X8,
111 DEV_X16,
112 DEV_X32, /* Do these parts exist? */
113 DEV_X64 /* Do these parts exist? */
114};
115
116#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
117#define DEV_FLAG_X1 BIT(DEV_X1)
118#define DEV_FLAG_X2 BIT(DEV_X2)
119#define DEV_FLAG_X4 BIT(DEV_X4)
120#define DEV_FLAG_X8 BIT(DEV_X8)
121#define DEV_FLAG_X16 BIT(DEV_X16)
122#define DEV_FLAG_X32 BIT(DEV_X32)
123#define DEV_FLAG_X64 BIT(DEV_X64)
124
125/* memory types */
126enum mem_type {
127 MEM_EMPTY = 0, /* Empty csrow */
128 MEM_RESERVED, /* Reserved csrow type */
129 MEM_UNKNOWN, /* Unknown csrow type */
130 MEM_FPM, /* Fast page mode */
131 MEM_EDO, /* Extended data out */
132 MEM_BEDO, /* Burst Extended data out */
133 MEM_SDR, /* Single data rate SDRAM */
134 MEM_RDR, /* Registered single data rate SDRAM */
135 MEM_DDR, /* Double data rate SDRAM */
136 MEM_RDDR, /* Registered Double data rate SDRAM */
137 MEM_RMBS, /* Rambus DRAM */
138 MEM_DDR2, /* DDR2 RAM */
139 MEM_FB_DDR2, /* fully buffered DDR2 */
140 MEM_RDDR2, /* Registered DDR2 RAM */
141 MEM_XDR, /* Rambus XDR */
142 MEM_DDR3, /* DDR3 RAM */
143 MEM_RDDR3, /* Registered DDR3 RAM */
144};
145
146#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
147#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
148#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
149#define MEM_FLAG_FPM BIT(MEM_FPM)
150#define MEM_FLAG_EDO BIT(MEM_EDO)
151#define MEM_FLAG_BEDO BIT(MEM_BEDO)
152#define MEM_FLAG_SDR BIT(MEM_SDR)
153#define MEM_FLAG_RDR BIT(MEM_RDR)
154#define MEM_FLAG_DDR BIT(MEM_DDR)
155#define MEM_FLAG_RDDR BIT(MEM_RDDR)
156#define MEM_FLAG_RMBS BIT(MEM_RMBS)
157#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
158#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
159#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
160#define MEM_FLAG_XDR BIT(MEM_XDR)
161#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
162#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
163
164/* chipset Error Detection and Correction capabilities and mode */
165enum edac_type {
166 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
167 EDAC_NONE, /* Doesn't support ECC */
168 EDAC_RESERVED, /* Reserved ECC type */
169 EDAC_PARITY, /* Detects parity errors */
170 EDAC_EC, /* Error Checking - no correction */
171 EDAC_SECDED, /* Single bit error correction, Double detection */
172 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
173 EDAC_S4ECD4ED, /* Chipkill x4 devices */
174 EDAC_S8ECD8ED, /* Chipkill x8 devices */
175 EDAC_S16ECD16ED, /* Chipkill x16 devices */
176};
177
178#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
179#define EDAC_FLAG_NONE BIT(EDAC_NONE)
180#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
181#define EDAC_FLAG_EC BIT(EDAC_EC)
182#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
183#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
184#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
185#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
186#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
187
188/* scrubbing capabilities */
189enum scrub_type {
190 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
191 SCRUB_NONE, /* No scrubber */
192 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
193 SCRUB_SW_SRC, /* Software scrub only errors */
194 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
195 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
196 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
197 SCRUB_HW_SRC, /* Hardware scrub only errors */
198 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
199 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
200};
201
202#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
203#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
204#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
205#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
206#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
207#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
208#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
209#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
210
211/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
212
213/* EDAC internal operation states */
214#define OP_ALLOC 0x100
215#define OP_RUNNING_POLL 0x201
216#define OP_RUNNING_INTERRUPT 0x202
217#define OP_RUNNING_POLL_INTR 0x203
218#define OP_OFFLINE 0x300
219
220/*
221 * There are several things to be aware of that aren't at all obvious:
222 *
223 *
224 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
225 *
226 * These are some of the many terms that are thrown about that don't always
227 * mean what people think they mean (Inconceivable!). In the interest of
228 * creating a common ground for discussion, terms and their definitions
229 * will be established.
230 *
231 * Memory devices: The individual chip on a memory stick. These devices
232 * commonly output 4 and 8 bits each. Grouping several
233 * of these in parallel provides 64 bits which is common
234 * for a memory stick.
235 *
236 * Memory Stick: A printed circuit board that aggregates multiple
237 * memory devices in parallel. This is the atomic
238 * memory component that is purchaseable by Joe consumer
239 * and loaded into a memory socket.
240 *
241 * Socket: A physical connector on the motherboard that accepts
242 * a single memory stick.
243 *
244 * Channel: Set of memory devices on a memory stick that must be
245 * grouped in parallel with one or more additional
246 * channels from other memory sticks. This parallel
247 * grouping of the output from multiple channels are
248 * necessary for the smallest granularity of memory access.
249 * Some memory controllers are capable of single channel -
250 * which means that memory sticks can be loaded
251 * individually. Other memory controllers are only
252 * capable of dual channel - which means that memory
253 * sticks must be loaded as pairs (see "socket set").
254 *
255 * Chip-select row: All of the memory devices that are selected together.
256 * for a single, minimum grain of memory access.
257 * This selects all of the parallel memory devices across
258 * all of the parallel channels. Common chip-select rows
259 * for single channel are 64 bits, for dual channel 128
260 * bits.
261 *
262 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
263 * Motherboards commonly drive two chip-select pins to
264 * a memory stick. A single-ranked stick, will occupy
265 * only one of those rows. The other will be unused.
266 *
267 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
268 * access different sets of memory devices. The two
269 * rows cannot be accessed concurrently.
270 *
271 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
272 * A double-sided stick has two chip-select rows which
273 * access different sets of memory devices. The two
274 * rows cannot be accessed concurrently. "Double-sided"
275 * is irrespective of the memory devices being mounted
276 * on both sides of the memory stick.
277 *
278 * Socket set: All of the memory sticks that are required for
279 * a single memory access or all of the memory sticks
280 * spanned by a chip-select row. A single socket set
281 * has two chip-select rows and if double-sided sticks
282 * are used these will occupy those chip-select rows.
283 *
284 * Bank: This term is avoided because it is unclear when
285 * needing to distinguish between chip-select rows and
286 * socket sets.
287 *
288 * Controller pages:
289 *
290 * Physical pages:
291 *
292 * Virtual pages:
293 *
294 *
295 * STRUCTURE ORGANIZATION AND CHOICES
296 *
297 *
298 *
299 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
300 */
301
302struct channel_info {
303 int chan_idx; /* channel index */
304 u32 ce_count; /* Correctable Errors for this CHANNEL */
305 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
306 struct csrow_info *csrow; /* the parent */
307};
308
309struct csrow_info {
310 unsigned long first_page; /* first page number in dimm */
311 unsigned long last_page; /* last page number in dimm */
312 unsigned long page_mask; /* used for interleaving -
313 * 0UL for non intlv
314 */
315 u32 nr_pages; /* number of pages in csrow */
316 u32 grain; /* granularity of reported error in bytes */
317 int csrow_idx; /* the chip-select row */
318 enum dev_type dtype; /* memory device type */
319 u32 ue_count; /* Uncorrectable Errors for this csrow */
320 u32 ce_count; /* Correctable Errors for this csrow */
321 enum mem_type mtype; /* memory csrow type */
322 enum edac_type edac_mode; /* EDAC mode for this csrow */
323 struct mem_ctl_info *mci; /* the parent */
324
325 struct kobject kobj; /* sysfs kobject for this csrow */
326
327 /* channel information for this csrow */
328 u32 nr_channels;
329 struct channel_info *channels;
330};
331
332struct mcidev_sysfs_group {
333 const char *name; /* group name */
334 const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
335};
336
337struct mcidev_sysfs_group_kobj {
338 struct list_head list; /* list for all instances within a mc */
339
340 struct kobject kobj; /* kobj for the group */
341
342 const struct mcidev_sysfs_group *grp; /* group description table */
343 struct mem_ctl_info *mci; /* the parent */
344};
345
346/* mcidev_sysfs_attribute structure
347 * used for driver sysfs attributes and in mem_ctl_info
348 * sysfs top level entries
349 */
350struct mcidev_sysfs_attribute {
351 /* It should use either attr or grp */
352 struct attribute attr;
353 const struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
354
355 /* Ops for show/store values at the attribute - not used on group */
356 ssize_t (*show)(struct mem_ctl_info *,char *);
357 ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
358};
359
360/* MEMORY controller information structure
361 */
362struct mem_ctl_info {
363 struct list_head link; /* for global list of mem_ctl_info structs */
364
365 struct module *owner; /* Module owner of this control struct */
366
367 unsigned long mtype_cap; /* memory types supported by mc */
368 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
369 unsigned long edac_cap; /* configuration capabilities - this is
370 * closely related to edac_ctl_cap. The
371 * difference is that the controller may be
372 * capable of s4ecd4ed which would be listed
373 * in edac_ctl_cap, but if channels aren't
374 * capable of s4ecd4ed then the edac_cap would
375 * not have that capability.
376 */
377 unsigned long scrub_cap; /* chipset scrub capabilities */
378 enum scrub_type scrub_mode; /* current scrub mode */
379
380 /* Translates sdram memory scrub rate given in bytes/sec to the
381 internal representation and configures whatever else needs
382 to be configured.
383 */
384 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
385
386 /* Get the current sdram memory scrub rate from the internal
387 representation and converts it to the closest matching
388 bandwidth in bytes/sec.
389 */
390 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
391
392
393 /* pointer to edac checking routine */
394 void (*edac_check) (struct mem_ctl_info * mci);
395
396 /*
397 * Remaps memory pages: controller pages to physical pages.
398 * For most MC's, this will be NULL.
399 */
400 /* FIXME - why not send the phys page to begin with? */
401 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
402 unsigned long page);
403 int mc_idx;
404 int nr_csrows;
405 struct csrow_info *csrows;
406 /*
407 * FIXME - what about controllers on other busses? - IDs must be
408 * unique. dev pointer should be sufficiently unique, but
409 * BUS:SLOT.FUNC numbers may not be unique.
410 */
411 struct device *dev;
412 const char *mod_name;
413 const char *mod_ver;
414 const char *ctl_name;
415 const char *dev_name;
416 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
417 void *pvt_info;
418 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
419 u32 ce_noinfo_count; /* Correctable Errors w/o info */
420 u32 ue_count; /* Total Uncorrectable Errors for this MC */
421 u32 ce_count; /* Total Correctable Errors for this MC */
422 unsigned long start_time; /* mci load start time (in jiffies) */
423
424 struct completion complete;
425
426 /* edac sysfs device control */
427 struct kobject edac_mci_kobj;
428
429 /* list for all grp instances within a mc */
430 struct list_head grp_kobj_list;
431
432 /* Additional top controller level attributes, but specified
433 * by the low level driver.
434 *
435 * Set by the low level driver to provide attributes at the
436 * controller level, same level as 'ue_count' and 'ce_count' above.
437 * An array of structures, NULL terminated
438 *
439 * If attributes are desired, then set to array of attributes
440 * If no attributes are desired, leave NULL
441 */
442 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
443
444 /* work struct for this MC */
445 struct delayed_work work;
446
447 /* the internal state of this controller instance */
448 int op_state;
449};
450
451/* 103/*
452 * The following are the structures to provide for a generic 104 * The following are the structures to provide for a generic
453 * or abstract 'edac_device'. This set of structures and the 105 * or abstract 'edac_device'. This set of structures and the
diff --git a/include/linux/edac.h b/include/linux/edac.h
index 4a73257b47d0..055b248bdd53 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -42,4 +42,354 @@ static inline void opstate_init(void)
42 return; 42 return;
43} 43}
44 44
45#define EDAC_MC_LABEL_LEN 31
46#define MC_PROC_NAME_MAX_LEN 7
47
48/* memory devices */
49enum dev_type {
50 DEV_UNKNOWN = 0,
51 DEV_X1,
52 DEV_X2,
53 DEV_X4,
54 DEV_X8,
55 DEV_X16,
56 DEV_X32, /* Do these parts exist? */
57 DEV_X64 /* Do these parts exist? */
58};
59
60#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
61#define DEV_FLAG_X1 BIT(DEV_X1)
62#define DEV_FLAG_X2 BIT(DEV_X2)
63#define DEV_FLAG_X4 BIT(DEV_X4)
64#define DEV_FLAG_X8 BIT(DEV_X8)
65#define DEV_FLAG_X16 BIT(DEV_X16)
66#define DEV_FLAG_X32 BIT(DEV_X32)
67#define DEV_FLAG_X64 BIT(DEV_X64)
68
69/* memory types */
70enum mem_type {
71 MEM_EMPTY = 0, /* Empty csrow */
72 MEM_RESERVED, /* Reserved csrow type */
73 MEM_UNKNOWN, /* Unknown csrow type */
74 MEM_FPM, /* Fast page mode */
75 MEM_EDO, /* Extended data out */
76 MEM_BEDO, /* Burst Extended data out */
77 MEM_SDR, /* Single data rate SDRAM */
78 MEM_RDR, /* Registered single data rate SDRAM */
79 MEM_DDR, /* Double data rate SDRAM */
80 MEM_RDDR, /* Registered Double data rate SDRAM */
81 MEM_RMBS, /* Rambus DRAM */
82 MEM_DDR2, /* DDR2 RAM */
83 MEM_FB_DDR2, /* fully buffered DDR2 */
84 MEM_RDDR2, /* Registered DDR2 RAM */
85 MEM_XDR, /* Rambus XDR */
86 MEM_DDR3, /* DDR3 RAM */
87 MEM_RDDR3, /* Registered DDR3 RAM */
88};
89
90#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
91#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
92#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
93#define MEM_FLAG_FPM BIT(MEM_FPM)
94#define MEM_FLAG_EDO BIT(MEM_EDO)
95#define MEM_FLAG_BEDO BIT(MEM_BEDO)
96#define MEM_FLAG_SDR BIT(MEM_SDR)
97#define MEM_FLAG_RDR BIT(MEM_RDR)
98#define MEM_FLAG_DDR BIT(MEM_DDR)
99#define MEM_FLAG_RDDR BIT(MEM_RDDR)
100#define MEM_FLAG_RMBS BIT(MEM_RMBS)
101#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
102#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
103#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
104#define MEM_FLAG_XDR BIT(MEM_XDR)
105#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
106#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
107
108/* chipset Error Detection and Correction capabilities and mode */
109enum edac_type {
110 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
111 EDAC_NONE, /* Doesn't support ECC */
112 EDAC_RESERVED, /* Reserved ECC type */
113 EDAC_PARITY, /* Detects parity errors */
114 EDAC_EC, /* Error Checking - no correction */
115 EDAC_SECDED, /* Single bit error correction, Double detection */
116 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
117 EDAC_S4ECD4ED, /* Chipkill x4 devices */
118 EDAC_S8ECD8ED, /* Chipkill x8 devices */
119 EDAC_S16ECD16ED, /* Chipkill x16 devices */
120};
121
122#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
123#define EDAC_FLAG_NONE BIT(EDAC_NONE)
124#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
125#define EDAC_FLAG_EC BIT(EDAC_EC)
126#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
127#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
128#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
129#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
130#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
131
132/* scrubbing capabilities */
133enum scrub_type {
134 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
135 SCRUB_NONE, /* No scrubber */
136 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
137 SCRUB_SW_SRC, /* Software scrub only errors */
138 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
139 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
140 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
141 SCRUB_HW_SRC, /* Hardware scrub only errors */
142 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
143 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
144};
145
146#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
147#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
148#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
149#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
150#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
151#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
152#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
153#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
154
155/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
156
157/* EDAC internal operation states */
158#define OP_ALLOC 0x100
159#define OP_RUNNING_POLL 0x201
160#define OP_RUNNING_INTERRUPT 0x202
161#define OP_RUNNING_POLL_INTR 0x203
162#define OP_OFFLINE 0x300
163
164/*
165 * There are several things to be aware of that aren't at all obvious:
166 *
167 *
168 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
169 *
170 * These are some of the many terms that are thrown about that don't always
171 * mean what people think they mean (Inconceivable!). In the interest of
172 * creating a common ground for discussion, terms and their definitions
173 * will be established.
174 *
175 * Memory devices: The individual chip on a memory stick. These devices
176 * commonly output 4 and 8 bits each. Grouping several
177 * of these in parallel provides 64 bits which is common
178 * for a memory stick.
179 *
180 * Memory Stick: A printed circuit board that aggregates multiple
181 * memory devices in parallel. This is the atomic
182 * memory component that is purchaseable by Joe consumer
183 * and loaded into a memory socket.
184 *
185 * Socket: A physical connector on the motherboard that accepts
186 * a single memory stick.
187 *
188 * Channel: Set of memory devices on a memory stick that must be
189 * grouped in parallel with one or more additional
190 * channels from other memory sticks. This parallel
191 * grouping of the output from multiple channels are
192 * necessary for the smallest granularity of memory access.
193 * Some memory controllers are capable of single channel -
194 * which means that memory sticks can be loaded
195 * individually. Other memory controllers are only
196 * capable of dual channel - which means that memory
197 * sticks must be loaded as pairs (see "socket set").
198 *
199 * Chip-select row: All of the memory devices that are selected together.
200 * for a single, minimum grain of memory access.
201 * This selects all of the parallel memory devices across
202 * all of the parallel channels. Common chip-select rows
203 * for single channel are 64 bits, for dual channel 128
204 * bits.
205 *
206 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
207 * Motherboards commonly drive two chip-select pins to
208 * a memory stick. A single-ranked stick, will occupy
209 * only one of those rows. The other will be unused.
210 *
211 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
212 * access different sets of memory devices. The two
213 * rows cannot be accessed concurrently.
214 *
215 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
216 * A double-sided stick has two chip-select rows which
217 * access different sets of memory devices. The two
218 * rows cannot be accessed concurrently. "Double-sided"
219 * is irrespective of the memory devices being mounted
220 * on both sides of the memory stick.
221 *
222 * Socket set: All of the memory sticks that are required for
223 * a single memory access or all of the memory sticks
224 * spanned by a chip-select row. A single socket set
225 * has two chip-select rows and if double-sided sticks
226 * are used these will occupy those chip-select rows.
227 *
228 * Bank: This term is avoided because it is unclear when
229 * needing to distinguish between chip-select rows and
230 * socket sets.
231 *
232 * Controller pages:
233 *
234 * Physical pages:
235 *
236 * Virtual pages:
237 *
238 *
239 * STRUCTURE ORGANIZATION AND CHOICES
240 *
241 *
242 *
243 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
244 */
245
246struct channel_info {
247 int chan_idx; /* channel index */
248 u32 ce_count; /* Correctable Errors for this CHANNEL */
249 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
250 struct csrow_info *csrow; /* the parent */
251};
252
253struct csrow_info {
254 unsigned long first_page; /* first page number in dimm */
255 unsigned long last_page; /* last page number in dimm */
256 unsigned long page_mask; /* used for interleaving -
257 * 0UL for non intlv
258 */
259 u32 nr_pages; /* number of pages in csrow */
260 u32 grain; /* granularity of reported error in bytes */
261 int csrow_idx; /* the chip-select row */
262 enum dev_type dtype; /* memory device type */
263 u32 ue_count; /* Uncorrectable Errors for this csrow */
264 u32 ce_count; /* Correctable Errors for this csrow */
265 enum mem_type mtype; /* memory csrow type */
266 enum edac_type edac_mode; /* EDAC mode for this csrow */
267 struct mem_ctl_info *mci; /* the parent */
268
269 struct kobject kobj; /* sysfs kobject for this csrow */
270
271 /* channel information for this csrow */
272 u32 nr_channels;
273 struct channel_info *channels;
274};
275
276struct mcidev_sysfs_group {
277 const char *name; /* group name */
278 const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
279};
280
281struct mcidev_sysfs_group_kobj {
282 struct list_head list; /* list for all instances within a mc */
283
284 struct kobject kobj; /* kobj for the group */
285
286 const struct mcidev_sysfs_group *grp; /* group description table */
287 struct mem_ctl_info *mci; /* the parent */
288};
289
290/* mcidev_sysfs_attribute structure
291 * used for driver sysfs attributes and in mem_ctl_info
292 * sysfs top level entries
293 */
294struct mcidev_sysfs_attribute {
295 /* It should use either attr or grp */
296 struct attribute attr;
297 const struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
298
299 /* Ops for show/store values at the attribute - not used on group */
300 ssize_t (*show)(struct mem_ctl_info *,char *);
301 ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
302};
303
304/* MEMORY controller information structure
305 */
306struct mem_ctl_info {
307 struct list_head link; /* for global list of mem_ctl_info structs */
308
309 struct module *owner; /* Module owner of this control struct */
310
311 unsigned long mtype_cap; /* memory types supported by mc */
312 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
313 unsigned long edac_cap; /* configuration capabilities - this is
314 * closely related to edac_ctl_cap. The
315 * difference is that the controller may be
316 * capable of s4ecd4ed which would be listed
317 * in edac_ctl_cap, but if channels aren't
318 * capable of s4ecd4ed then the edac_cap would
319 * not have that capability.
320 */
321 unsigned long scrub_cap; /* chipset scrub capabilities */
322 enum scrub_type scrub_mode; /* current scrub mode */
323
324 /* Translates sdram memory scrub rate given in bytes/sec to the
325 internal representation and configures whatever else needs
326 to be configured.
327 */
328 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
329
330 /* Get the current sdram memory scrub rate from the internal
331 representation and converts it to the closest matching
332 bandwidth in bytes/sec.
333 */
334 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
335
336
337 /* pointer to edac checking routine */
338 void (*edac_check) (struct mem_ctl_info * mci);
339
340 /*
341 * Remaps memory pages: controller pages to physical pages.
342 * For most MC's, this will be NULL.
343 */
344 /* FIXME - why not send the phys page to begin with? */
345 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
346 unsigned long page);
347 int mc_idx;
348 int nr_csrows;
349 struct csrow_info *csrows;
350 /*
351 * FIXME - what about controllers on other busses? - IDs must be
352 * unique. dev pointer should be sufficiently unique, but
353 * BUS:SLOT.FUNC numbers may not be unique.
354 */
355 struct device *dev;
356 const char *mod_name;
357 const char *mod_ver;
358 const char *ctl_name;
359 const char *dev_name;
360 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
361 void *pvt_info;
362 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
363 u32 ce_noinfo_count; /* Correctable Errors w/o info */
364 u32 ue_count; /* Total Uncorrectable Errors for this MC */
365 u32 ce_count; /* Total Correctable Errors for this MC */
366 unsigned long start_time; /* mci load start time (in jiffies) */
367
368 struct completion complete;
369
370 /* edac sysfs device control */
371 struct kobject edac_mci_kobj;
372
373 /* list for all grp instances within a mc */
374 struct list_head grp_kobj_list;
375
376 /* Additional top controller level attributes, but specified
377 * by the low level driver.
378 *
379 * Set by the low level driver to provide attributes at the
380 * controller level, same level as 'ue_count' and 'ce_count' above.
381 * An array of structures, NULL terminated
382 *
383 * If attributes are desired, then set to array of attributes
384 * If no attributes are desired, leave NULL
385 */
386 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
387
388 /* work struct for this MC */
389 struct delayed_work work;
390
391 /* the internal state of this controller instance */
392 int op_state;
393};
394
45#endif 395#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 15:53:48 -0500