diff options
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mem.c | 129 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_perf.c | 18 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_pm.c | 20 |
4 files changed, 110 insertions, 70 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 5a4947919f1c..760f85c85ccd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -448,14 +448,14 @@ struct nouveau_pm_memtiming { | |||
448 | u8 WR; | 448 | u8 WR; |
449 | }; | 449 | }; |
450 | 450 | ||
451 | struct nouveau_pm_tbl_header{ | 451 | struct nouveau_pm_tbl_header { |
452 | u8 version; | 452 | u8 version; |
453 | u8 header_len; | 453 | u8 header_len; |
454 | u8 entry_cnt; | 454 | u8 entry_cnt; |
455 | u8 entry_len; | 455 | u8 entry_len; |
456 | }; | 456 | }; |
457 | 457 | ||
458 | struct nouveau_pm_tbl_entry{ | 458 | struct nouveau_pm_tbl_entry { |
459 | u8 tWR; | 459 | u8 tWR; |
460 | u8 tUNK_1; | 460 | u8 tUNK_1; |
461 | u8 tCL; | 461 | u8 tCL; |
@@ -471,11 +471,6 @@ struct nouveau_pm_tbl_entry{ | |||
471 | u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; | 471 | u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; |
472 | }; | 472 | }; |
473 | 473 | ||
474 | /* nouveau_mem.c */ | ||
475 | void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, | ||
476 | struct nouveau_pm_tbl_entry *e, uint8_t magic_number, | ||
477 | struct nouveau_pm_memtiming *timing); | ||
478 | |||
479 | #define NOUVEAU_PM_MAX_LEVEL 8 | 474 | #define NOUVEAU_PM_MAX_LEVEL 8 |
480 | struct nouveau_pm_level { | 475 | struct nouveau_pm_level { |
481 | struct device_attribute dev_attr; | 476 | struct device_attribute dev_attr; |
@@ -918,6 +913,10 @@ extern void nv10_mem_put_tile_region(struct drm_device *dev, | |||
918 | struct nouveau_fence *fence); | 913 | struct nouveau_fence *fence); |
919 | extern const struct ttm_mem_type_manager_func nouveau_vram_manager; | 914 | extern const struct ttm_mem_type_manager_func nouveau_vram_manager; |
920 | extern const struct ttm_mem_type_manager_func nouveau_gart_manager; | 915 | extern const struct ttm_mem_type_manager_func nouveau_gart_manager; |
916 | void nv30_mem_timing_entry(struct drm_device *dev, | ||
917 | struct nouveau_pm_tbl_header *hdr, | ||
918 | struct nouveau_pm_tbl_entry *e, uint8_t magic_number, | ||
919 | struct nouveau_pm_memtiming *timing); | ||
921 | 920 | ||
922 | /* nouveau_notifier.c */ | 921 | /* nouveau_notifier.c */ |
923 | extern int nouveau_notifier_init_channel(struct nouveau_channel *); | 922 | extern int nouveau_notifier_init_channel(struct nouveau_channel *); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index c5ba6c2eab88..5eb9e3df0fec 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c | |||
@@ -473,16 +473,21 @@ nouveau_mem_gart_init(struct drm_device *dev) | |||
473 | 473 | ||
474 | /* XXX: For now a dummy. More samples required, possibly even a card | 474 | /* XXX: For now a dummy. More samples required, possibly even a card |
475 | * Called from nouveau_perf.c */ | 475 | * Called from nouveau_perf.c */ |
476 | void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, | 476 | void nv30_mem_timing_entry(struct drm_device *dev, |
477 | struct nouveau_pm_tbl_entry *e, uint8_t magic_number, | 477 | struct nouveau_pm_tbl_header *hdr, |
478 | struct nouveau_pm_memtiming *timing) { | 478 | struct nouveau_pm_tbl_entry *e, uint8_t magic_number, |
479 | struct nouveau_pm_memtiming *timing) | ||
480 | { | ||
479 | 481 | ||
480 | NV_DEBUG(dev,"Timing entry format unknown, please contact nouveau developers"); | 482 | NV_DEBUG(dev, "Timing entry format unknown, " |
483 | "please contact nouveau developers"); | ||
481 | } | 484 | } |
482 | 485 | ||
483 | void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, | 486 | void nv40_mem_timing_entry(struct drm_device *dev, |
484 | struct nouveau_pm_tbl_entry *e, uint8_t magic_number, | 487 | struct nouveau_pm_tbl_header *hdr, |
485 | struct nouveau_pm_memtiming *timing) { | 488 | struct nouveau_pm_tbl_entry *e, uint8_t magic_number, |
489 | struct nouveau_pm_memtiming *timing) | ||
490 | { | ||
486 | 491 | ||
487 | timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP); | 492 | timing->reg_0 = (e->tRC << 24 | e->tRFC << 16 | e->tRAS << 8 | e->tRP); |
488 | 493 | ||
@@ -492,15 +497,19 @@ void nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header | |||
492 | 1 << 16 | | 497 | 1 << 16 | |
493 | (e->tUNK_1 + 2 + magic_number) << 8 | | 498 | (e->tUNK_1 + 2 + magic_number) << 8 | |
494 | (e->tCL + 2 - magic_number); | 499 | (e->tCL + 2 - magic_number); |
495 | timing->reg_2 = (magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10); | 500 | timing->reg_2 = magic_number << 24 | e->tUNK_12 << 16 | |
501 | e->tUNK_11 << 8 | e->tUNK_10; | ||
496 | timing->reg_2 |= 0x20200000; | 502 | timing->reg_2 |= 0x20200000; |
497 | 503 | ||
498 | NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id, | 504 | NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id, |
499 | timing->reg_0, timing->reg_1,timing->reg_2); | 505 | timing->reg_0, timing->reg_1, timing->reg_2); |
500 | } | 506 | } |
501 | 507 | ||
502 | void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct nouveau_pm_tbl_header *hdr, | 508 | void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, |
503 | struct nouveau_pm_tbl_entry *e, uint8_t magic_number,struct nouveau_pm_memtiming *timing) { | 509 | struct nouveau_pm_tbl_header *hdr, |
510 | struct nouveau_pm_tbl_entry *e, uint8_t magic_number, | ||
511 | struct nouveau_pm_memtiming *timing) | ||
512 | { | ||
504 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 513 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
505 | 514 | ||
506 | uint8_t unk18 = 1, | 515 | uint8_t unk18 = 1, |
@@ -527,11 +536,11 @@ void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct n | |||
527 | timing->reg_1 = (e->tWR + unk19 + 1 + magic_number) << 24 | | 536 | timing->reg_1 = (e->tWR + unk19 + 1 + magic_number) << 24 | |
528 | max(unk18, (u8) 1) << 16 | | 537 | max(unk18, (u8) 1) << 16 | |
529 | (e->tUNK_1 + unk19 + 1 + magic_number) << 8; | 538 | (e->tUNK_1 + unk19 + 1 + magic_number) << 8; |
530 | if (dev_priv->chipset == 0xa8) { | 539 | if (dev_priv->chipset == 0xa8) |
531 | timing->reg_1 |= (e->tCL - 1); | 540 | timing->reg_1 |= (e->tCL - 1); |
532 | } else { | 541 | else |
533 | timing->reg_1 |= (e->tCL + 2 - magic_number); | 542 | timing->reg_1 |= (e->tCL + 2 - magic_number); |
534 | } | 543 | |
535 | timing->reg_2 = (e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10); | 544 | timing->reg_2 = (e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10); |
536 | 545 | ||
537 | timing->reg_5 = (e->tRAS << 24 | e->tRC); | 546 | timing->reg_5 = (e->tRAS << 24 | e->tRC); |
@@ -539,19 +548,24 @@ void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct n | |||
539 | 548 | ||
540 | if (P->version == 1) { | 549 | if (P->version == 1) { |
541 | timing->reg_2 |= magic_number << 24; | 550 | timing->reg_2 |= magic_number << 24; |
551 | |||
542 | timing->reg_3 = (0x14 + e->tCL) << 24 | | 552 | timing->reg_3 = (0x14 + e->tCL) << 24 | |
543 | 0x16 << 16 | | 553 | 0x16 << 16 | |
544 | (e->tCL - 1) << 8 | | 554 | (e->tCL - 1) << 8 | |
545 | (e->tCL - 1); | 555 | (e->tCL - 1); |
546 | timing->reg_4 = (nv_rd32(dev,0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13; | 556 | |
557 | timing->reg_4 = (nv_rd32(dev, 0x10022c) & 0xffff0000) | | ||
558 | e->tUNK_13 << 8 | e->tUNK_13; | ||
559 | |||
547 | timing->reg_5 |= (e->tCL + 2) << 8; | 560 | timing->reg_5 |= (e->tCL + 2) << 8; |
561 | |||
548 | timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16; | 562 | timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16; |
549 | } else { | 563 | } else { |
550 | timing->reg_2 |= (unk19 - 1) << 24; | 564 | timing->reg_2 |= (unk19 - 1) << 24; |
551 | /* XXX: reg_10022c for recentish cards pretty much unknown*/ | 565 | /* XXX: reg_10022c for recentish cards pretty much unknown*/ |
552 | timing->reg_3 = e->tCL - 1; | 566 | timing->reg_3 = e->tCL - 1; |
553 | timing->reg_4 = (unk20 << 24 | unk21 << 16 | | 567 | timing->reg_4 = (unk20 << 24 | unk21 << 16 | |
554 | e->tUNK_13 << 8 | e->tUNK_13); | 568 | e->tUNK_13 << 8 | e->tUNK_13); |
555 | /* XXX: +6? */ | 569 | /* XXX: +6? */ |
556 | timing->reg_5 |= (unk19 + 6) << 8; | 570 | timing->reg_5 |= (unk19 + 6) << 8; |
557 | 571 | ||
@@ -569,13 +583,26 @@ void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P, struct n | |||
569 | NV_DEBUG(dev, " 240: %08x\n", timing->reg_8); | 583 | NV_DEBUG(dev, " 240: %08x\n", timing->reg_8); |
570 | } | 584 | } |
571 | 585 | ||
572 | void nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, | 586 | void nvc0_mem_timing_entry(struct drm_device *dev, |
573 | struct nouveau_pm_tbl_entry *e, struct nouveau_pm_memtiming *timing) { | 587 | struct nouveau_pm_tbl_header *hdr, |
574 | timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | e->tRAS << 8 | e->tRP); | 588 | struct nouveau_pm_tbl_entry *e, |
575 | timing->reg_1 = (nv_rd32(dev,0x10f294) & 0xff000000) | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | (e->tCL & 0x0f); | 589 | struct nouveau_pm_memtiming *timing) |
576 | timing->reg_2 = (nv_rd32(dev,0x10f298) & 0xff0000ff) | e->tWR << 16 | e->tUNK_1 << 8; | 590 | { |
591 | timing->reg_0 = (e->tRC << 24 | (e->tRFC & 0x7f) << 17 | | ||
592 | e->tRAS << 8 | e->tRP); | ||
593 | |||
594 | timing->reg_1 = (nv_rd32(dev, 0x10f294) & 0xff000000) | | ||
595 | (e->tUNK_11&0x0f) << 20 | (e->tUNK_19 << 7) | | ||
596 | (e->tCL & 0x0f); | ||
597 | |||
598 | timing->reg_2 = (nv_rd32(dev, 0x10f298) & 0xff0000ff) | | ||
599 | e->tWR << 16 | e->tUNK_1 << 8; | ||
600 | |||
577 | timing->reg_3 = e->tUNK_20 << 9 | e->tUNK_13; | 601 | timing->reg_3 = e->tUNK_20 << 9 | e->tUNK_13; |
578 | timing->reg_4 = (nv_rd32(dev,0x10f2a0) & 0xfff000ff) | e->tUNK_12 << 15; | 602 | |
603 | timing->reg_4 = (nv_rd32(dev, 0x10f2a0) & 0xfff000ff) | | ||
604 | e->tUNK_12 << 15; | ||
605 | |||
579 | NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id, | 606 | NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id, |
580 | timing->reg_0, timing->reg_1, | 607 | timing->reg_0, timing->reg_1, |
581 | timing->reg_2, timing->reg_3); | 608 | timing->reg_2, timing->reg_3); |
@@ -607,13 +634,13 @@ nouveau_mem_timing_init(struct drm_device *dev) | |||
607 | return; | 634 | return; |
608 | 635 | ||
609 | if (P.version == 1) | 636 | if (P.version == 1) |
610 | hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[4]); | 637 | hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, |
638 | P.data[4]); | ||
639 | else if (P.version == 2) | ||
640 | hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, | ||
641 | P.data[8]); | ||
611 | else | 642 | else |
612 | if (P.version == 2) | ||
613 | hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev, P.data[8]); | ||
614 | else { | ||
615 | NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); | 643 | NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); |
616 | } | ||
617 | } else { | 644 | } else { |
618 | NV_DEBUG(dev, "BMP version too old for memory\n"); | 645 | NV_DEBUG(dev, "BMP version too old for memory\n"); |
619 | return; | 646 | return; |
@@ -625,32 +652,35 @@ nouveau_mem_timing_init(struct drm_device *dev) | |||
625 | } | 652 | } |
626 | 653 | ||
627 | if (hdr->version != 0x10) { | 654 | if (hdr->version != 0x10) { |
628 | NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version); | 655 | NV_WARN(dev, "memory timing table 0x%02x unknown\n", |
656 | hdr->version); | ||
629 | return; | 657 | return; |
630 | } | 658 | } |
631 | 659 | ||
632 | /* validate record length */ | 660 | /* validate record length */ |
633 | if (hdr->entry_len < 15) { | 661 | if (hdr->entry_len < 15) { |
634 | NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len); | 662 | NV_ERROR(dev, "mem timing table length unknown: %d\n", |
663 | hdr->entry_len); | ||
635 | return; | 664 | return; |
636 | } | 665 | } |
637 | 666 | ||
638 | /* parse vbios entries into common format */ | 667 | /* parse vbios entries into common format */ |
639 | memtimings->timing = | 668 | memtimings->timing = kcalloc(hdr->entry_cnt, |
640 | kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL); | 669 | sizeof(*memtimings->timing), GFP_KERNEL); |
641 | if (!memtimings->timing) | 670 | if (!memtimings->timing) |
642 | return; | 671 | return; |
643 | 672 | ||
644 | /* Get "some number" from the timing reg for NV_40 and NV_50 | 673 | /* Get "some number" from the timing reg for NV_40 and NV_50 |
645 | * Used in calculations later... source unknown */ | 674 | * Used in calculations later... source unknown */ |
646 | magic_number = 0; | 675 | magic_number = 0; |
647 | if (P.version == 1) { | 676 | if (P.version == 1) |
648 | magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24; | 677 | magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24; |
649 | } | ||
650 | 678 | ||
651 | entry = (u8*) hdr + hdr->header_len; | 679 | entry = (u8 *) hdr + hdr->header_len; |
652 | for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) { | 680 | for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) { |
653 | struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i]; | 681 | struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i]; |
682 | struct nouveau_pm_tbl_entry *entry_struct = | ||
683 | (struct nouveau_pm_tbl_entry *) entry; | ||
654 | if (entry[0] == 0) | 684 | if (entry[0] == 0) |
655 | continue; | 685 | continue; |
656 | 686 | ||
@@ -658,17 +688,22 @@ nouveau_mem_timing_init(struct drm_device *dev) | |||
658 | timing->WR = entry[0]; | 688 | timing->WR = entry[0]; |
659 | timing->CL = entry[2]; | 689 | timing->CL = entry[2]; |
660 | 690 | ||
661 | if(dev_priv->card_type <= NV_40) { | 691 | if (dev_priv->card_type <= NV_40) { |
662 | nv40_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); | 692 | nv40_mem_timing_entry(dev, hdr, entry_struct, |
663 | } else if(dev_priv->card_type == NV_50){ | 693 | magic_number, |
664 | nv50_mem_timing_entry(dev,&P,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); | 694 | &pm->memtimings.timing[i]); |
665 | } else if(dev_priv->card_type == NV_C0) { | 695 | } else if (dev_priv->card_type == NV_50) { |
666 | nvc0_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,&pm->memtimings.timing[i]); | 696 | nv50_mem_timing_entry(dev, &P, hdr, entry_struct, |
697 | magic_number, | ||
698 | &pm->memtimings.timing[i]); | ||
699 | } else if (dev_priv->card_type == NV_C0) { | ||
700 | nvc0_mem_timing_entry(dev, hdr, entry_struct, | ||
701 | &pm->memtimings.timing[i]); | ||
667 | } | 702 | } |
668 | } | 703 | } |
669 | 704 | ||
670 | memtimings->nr_timing = hdr->entry_cnt; | 705 | memtimings->nr_timing = hdr->entry_cnt; |
671 | memtimings->supported = P.version == 1; | 706 | memtimings->supported = (P.version == 1); |
672 | } | 707 | } |
673 | 708 | ||
674 | void | 709 | void |
@@ -677,10 +712,8 @@ nouveau_mem_timing_fini(struct drm_device *dev) | |||
677 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 712 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
678 | struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings; | 713 | struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings; |
679 | 714 | ||
680 | if(mem->timing) { | 715 | kfree(mem->timing); |
681 | kfree(mem->timing); | 716 | mem->timing = NULL; |
682 | mem->timing = NULL; | ||
683 | } | ||
684 | } | 717 | } |
685 | 718 | ||
686 | int | 719 | int |
diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c index 58f497343cec..54895cc60d2a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_perf.c +++ b/drivers/gpu/drm/nouveau/nouveau_perf.c | |||
@@ -230,18 +230,20 @@ nouveau_perf_init(struct drm_device *dev) | |||
230 | } | 230 | } |
231 | 231 | ||
232 | if (entries > NOUVEAU_PM_MAX_LEVEL) { | 232 | if (entries > NOUVEAU_PM_MAX_LEVEL) { |
233 | NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n"); | 233 | NV_DEBUG(dev, |
234 | "perf table has too many entries - buggy vbios?\n"); | ||
234 | entries = NOUVEAU_PM_MAX_LEVEL; | 235 | entries = NOUVEAU_PM_MAX_LEVEL; |
235 | } | 236 | } |
236 | 237 | ||
237 | entry = perf + headerlen; | 238 | entry = perf + headerlen; |
238 | 239 | ||
239 | /* For version 0x15, initialize memtiming table */ | 240 | /* For version 0x15, initialize memtiming table */ |
240 | if(version == 0x15) { | 241 | if (version == 0x15) { |
241 | memtimings->timing = | 242 | memtimings->timing = kcalloc(entries, |
242 | kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL); | 243 | sizeof(*memtimings->timing), |
244 | GFP_KERNEL); | ||
243 | if (!memtimings->timing) { | 245 | if (!memtimings->timing) { |
244 | NV_WARN(dev,"Could not allocate memtiming table\n"); | 246 | NV_WARN(dev, "Could not allocate memtiming table\n"); |
245 | return; | 247 | return; |
246 | } | 248 | } |
247 | 249 | ||
@@ -304,7 +306,7 @@ nouveau_perf_init(struct drm_device *dev) | |||
304 | perflvl->dom6 = ROM16(entry[20]) * 1000; | 306 | perflvl->dom6 = ROM16(entry[20]) * 1000; |
305 | break; | 307 | break; |
306 | case 0x40: | 308 | case 0x40: |
307 | #define subent(n) (ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000 | 309 | #define subent(n) ((ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000) |
308 | perflvl->fanspeed = 0; /*XXX*/ | 310 | perflvl->fanspeed = 0; /*XXX*/ |
309 | perflvl->volt_min = entry[2]; | 311 | perflvl->volt_min = entry[2]; |
310 | if (dev_priv->card_type == NV_50) { | 312 | if (dev_priv->card_type == NV_50) { |
@@ -342,7 +344,9 @@ nouveau_perf_init(struct drm_device *dev) | |||
342 | /* get the corresponding memory timings */ | 344 | /* get the corresponding memory timings */ |
343 | if (version == 0x15) { | 345 | if (version == 0x15) { |
344 | memtimings->timing[i].id = i; | 346 | memtimings->timing[i].id = i; |
345 | nv30_mem_timing_entry(dev,&mt_hdr,(struct nouveau_pm_tbl_entry*) &entry[41],0,&memtimings->timing[i]); | 347 | nv30_mem_timing_entry(dev, &mt_hdr, |
348 | (struct nouveau_pm_tbl_entry *) &entry[41], | ||
349 | 0, &memtimings->timing[i]); | ||
346 | perflvl->timing = &memtimings->timing[i]; | 350 | perflvl->timing = &memtimings->timing[i]; |
347 | } else if (version > 0x15) { | 351 | } else if (version > 0x15) { |
348 | /* last 3 args are for < 0x40, ignored for >= 0x40 */ | 352 | /* last 3 args are for < 0x40, ignored for >= 0x40 */ |
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c index 9064d7f19794..1770f1569c90 100644 --- a/drivers/gpu/drm/nouveau/nouveau_pm.c +++ b/drivers/gpu/drm/nouveau/nouveau_pm.c | |||
@@ -162,6 +162,7 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile) | |||
162 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 162 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
163 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; | 163 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; |
164 | struct nouveau_pm_level *perflvl = NULL; | 164 | struct nouveau_pm_level *perflvl = NULL; |
165 | long pl; | ||
165 | 166 | ||
166 | /* safety precaution, for now */ | 167 | /* safety precaution, for now */ |
167 | if (nouveau_perflvl_wr != 7777) | 168 | if (nouveau_perflvl_wr != 7777) |
@@ -170,8 +171,9 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile) | |||
170 | if (!strncmp(profile, "boot", 4)) | 171 | if (!strncmp(profile, "boot", 4)) |
171 | perflvl = &pm->boot; | 172 | perflvl = &pm->boot; |
172 | else { | 173 | else { |
173 | int pl = simple_strtol(profile, NULL, 10); | ||
174 | int i; | 174 | int i; |
175 | if (kstrtol(profile, 10, &pl) == -EINVAL) | ||
176 | return -EINVAL; | ||
175 | 177 | ||
176 | for (i = 0; i < pm->nr_perflvl; i++) { | 178 | for (i = 0; i < pm->nr_perflvl; i++) { |
177 | if (pm->perflvl[i].id == pl) { | 179 | if (pm->perflvl[i].id == pl) { |
@@ -397,7 +399,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a, | |||
397 | struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; | 399 | struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; |
398 | long value; | 400 | long value; |
399 | 401 | ||
400 | if (strict_strtol(buf, 10, &value) == -EINVAL) | 402 | if (kstrtol(buf, 10, &value) == -EINVAL) |
401 | return count; | 403 | return count; |
402 | 404 | ||
403 | temp->down_clock = value/1000; | 405 | temp->down_clock = value/1000; |
@@ -432,7 +434,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a, | |||
432 | struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; | 434 | struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; |
433 | long value; | 435 | long value; |
434 | 436 | ||
435 | if (strict_strtol(buf, 10, &value) == -EINVAL) | 437 | if (kstrtol(buf, 10, &value) == -EINVAL) |
436 | return count; | 438 | return count; |
437 | 439 | ||
438 | temp->critical = value/1000; | 440 | temp->critical = value/1000; |
@@ -529,7 +531,7 @@ nouveau_hwmon_set_pwm0(struct device *d, struct device_attribute *a, | |||
529 | if (nouveau_perflvl_wr != 7777) | 531 | if (nouveau_perflvl_wr != 7777) |
530 | return -EPERM; | 532 | return -EPERM; |
531 | 533 | ||
532 | if (strict_strtol(buf, 10, &value) == -EINVAL) | 534 | if (kstrtol(buf, 10, &value) == -EINVAL) |
533 | return -EINVAL; | 535 | return -EINVAL; |
534 | 536 | ||
535 | if (value < pm->fan.min_duty) | 537 | if (value < pm->fan.min_duty) |
@@ -568,7 +570,7 @@ nouveau_hwmon_set_pwm0_min(struct device *d, struct device_attribute *a, | |||
568 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; | 570 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; |
569 | long value; | 571 | long value; |
570 | 572 | ||
571 | if (strict_strtol(buf, 10, &value) == -EINVAL) | 573 | if (kstrtol(buf, 10, &value) == -EINVAL) |
572 | return -EINVAL; | 574 | return -EINVAL; |
573 | 575 | ||
574 | if (value < 0) | 576 | if (value < 0) |
@@ -609,7 +611,7 @@ nouveau_hwmon_set_pwm0_max(struct device *d, struct device_attribute *a, | |||
609 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; | 611 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; |
610 | long value; | 612 | long value; |
611 | 613 | ||
612 | if (strict_strtol(buf, 10, &value) == -EINVAL) | 614 | if (kstrtol(buf, 10, &value) == -EINVAL) |
613 | return -EINVAL; | 615 | return -EINVAL; |
614 | 616 | ||
615 | if (value < 0) | 617 | if (value < 0) |
@@ -731,8 +733,10 @@ nouveau_hwmon_fini(struct drm_device *dev) | |||
731 | 733 | ||
732 | if (pm->hwmon) { | 734 | if (pm->hwmon) { |
733 | sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup); | 735 | sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup); |
734 | sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_pwm_fan_attrgroup); | 736 | sysfs_remove_group(&dev->pdev->dev.kobj, |
735 | sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_fan_rpm_attrgroup); | 737 | &hwmon_pwm_fan_attrgroup); |
738 | sysfs_remove_group(&dev->pdev->dev.kobj, | ||
739 | &hwmon_fan_rpm_attrgroup); | ||
736 | 740 | ||
737 | hwmon_device_unregister(pm->hwmon); | 741 | hwmon_device_unregister(pm->hwmon); |
738 | } | 742 | } |