11 files changed, 229 insertions, 99 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cfb56d0ff367..0ad533f06af9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -46,6 +46,9 @@ module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
 unsigned int i915_powersave = 1;
 module_param_named(powersave, i915_powersave, int, 0600);
 
+unsigned int i915_enable_rc6 = 0;
+module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
+
 unsigned int i915_lvds_downclock = 0;
 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
 
@@ -360,7 +363,7 @@ static int i915_drm_thaw(struct drm_device *dev)
                 /* Resume the modeset for every activated CRTC */
                 drm_helper_resume_force_mode(dev);
 
-                if (dev_priv->renderctx && dev_priv->pwrctx)
+                if (IS_IRONLAKE_M(dev))
                         ironlake_enable_rc6(dev);
         }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0149c619cdd..65dfe81d0035 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -958,6 +958,7 @@ extern unsigned int i915_fbpercrtc;
 extern unsigned int i915_powersave;
 extern unsigned int i915_lvds_downclock;
 extern unsigned int i915_panel_use_ssc;
+extern unsigned int i915_enable_rc6;
 
 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
 extern int i915_resume(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5cfc68940f17..15d94c63918c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -174,7 +174,9 @@
  *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
  */
 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
-#define MI_FLUSH_DW             MI_INSTR(0x26, 2) /* for GEN6 */
+#define MI_FLUSH_DW             MI_INSTR(0x26, 1) /* for GEN6 */
+#define   MI_INVALIDATE_TLB     (1<<18)
+#define   MI_INVALIDATE_BSD     (1<<7)
 #define MI_BATCH_BUFFER         MI_INSTR(0x30, 1)
 #define   MI_BATCH_NON_SECURE   (1)
 #define   MI_BATCH_NON_SECURE_I965 (1<<8)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7e42aa586504..3b006536b3d2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5558,9 +5558,7 @@ static void intel_crtc_reset(struct drm_crtc *crtc)
         /* Reset flags back to the 'unknown' status so that they
          * will be correctly set on the initial modeset.
          */
-        intel_crtc->cursor_addr = 0;
         intel_crtc->dpms_mode = -1;
-        intel_crtc->active = true; /* force the pipe off on setup_init_config */
 }
 
 static struct drm_crtc_helper_funcs intel_helper_funcs = {
@@ -5666,6 +5664,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
 
         intel_crtc_reset(&intel_crtc->base);
+        intel_crtc->active = true; /* force the pipe off on setup_init_config */
 
         if (HAS_PCH_SPLIT(dev)) {
                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
@@ -6463,52 +6462,60 @@ void intel_enable_clock_gating(struct drm_device *dev)
         }
 }
 
-void intel_disable_clock_gating(struct drm_device *dev)
+static void ironlake_teardown_rc6(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         if (dev_priv->renderctx) {
-                struct drm_i915_gem_object *obj = dev_priv->renderctx;
-
-                I915_WRITE(CCID, 0);
-                POSTING_READ(CCID);
-
-                i915_gem_object_unpin(obj);
-                drm_gem_object_unreference(&obj->base);
+                i915_gem_object_unpin(dev_priv->renderctx);
+                drm_gem_object_unreference(&dev_priv->renderctx->base);
                 dev_priv->renderctx = NULL;
         }
 
         if (dev_priv->pwrctx) {
-                struct drm_i915_gem_object *obj = dev_priv->pwrctx;
+                i915_gem_object_unpin(dev_priv->pwrctx);
+                drm_gem_object_unreference(&dev_priv->pwrctx->base);
+                dev_priv->pwrctx = NULL;
+        }
+}
+
+static void ironlake_disable_rc6(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (I915_READ(PWRCTXA)) {
+                /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
+                I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
+                wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
+                         50);
 
                 I915_WRITE(PWRCTXA, 0);
                 POSTING_READ(PWRCTXA);
 
-                i915_gem_object_unpin(obj);
-                drm_gem_object_unreference(&obj->base);
-                dev_priv->pwrctx = NULL;
+                I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+                POSTING_READ(RSTDBYCTL);
         }
+
+        ironlake_disable_rc6(dev);
 }
 
-static void ironlake_disable_rc6(struct drm_device *dev)
+static int ironlake_setup_rc6(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
-        I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
-        wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
-                 10);
-        POSTING_READ(CCID);
-        I915_WRITE(PWRCTXA, 0);
-        POSTING_READ(PWRCTXA);
-        I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
-        POSTING_READ(RSTDBYCTL);
-        i915_gem_object_unpin(dev_priv->renderctx);
-        drm_gem_object_unreference(&dev_priv->renderctx->base);
-        dev_priv->renderctx = NULL;
-        i915_gem_object_unpin(dev_priv->pwrctx);
-        drm_gem_object_unreference(&dev_priv->pwrctx->base);
-        dev_priv->pwrctx = NULL;
+        if (dev_priv->renderctx == NULL)
+                dev_priv->renderctx = intel_alloc_context_page(dev);
+        if (!dev_priv->renderctx)
+                return -ENOMEM;
+
+        if (dev_priv->pwrctx == NULL)
+                dev_priv->pwrctx = intel_alloc_context_page(dev);
+        if (!dev_priv->pwrctx) {
+                ironlake_teardown_rc6(dev);
+                return -ENOMEM;
+        }
+
+        return 0;
 }