diff options
| -rw-r--r-- | drivers/clk/st/clkgen-pll.c | 30 |
1 files changed, 14 insertions, 16 deletions
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index d8b9b1a2aeda..cdf23dbd4ad4 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c | |||
| @@ -59,7 +59,7 @@ static const struct clk_ops st_pll800c65_ops; | |||
| 59 | static const struct clk_ops stm_pll3200c32_ops; | 59 | static const struct clk_ops stm_pll3200c32_ops; |
| 60 | static const struct clk_ops st_pll1200c32_ops; | 60 | static const struct clk_ops st_pll1200c32_ops; |
| 61 | 61 | ||
| 62 | static struct clkgen_pll_data st_pll1600c65_ax = { | 62 | static const struct clkgen_pll_data st_pll1600c65_ax = { |
| 63 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19), | 63 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19), |
| 64 | .locked_status = CLKGEN_FIELD(0x0, 0x1, 31), | 64 | .locked_status = CLKGEN_FIELD(0x0, 0x1, 31), |
| 65 | .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0), | 65 | .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0), |
| @@ -67,7 +67,7 @@ static struct clkgen_pll_data st_pll1600c65_ax = { | |||
| 67 | .ops = &st_pll1600c65_ops | 67 | .ops = &st_pll1600c65_ops |
| 68 | }; | 68 | }; |
| 69 | 69 | ||
| 70 | static struct clkgen_pll_data st_pll800c65_ax = { | 70 | static const struct clkgen_pll_data st_pll800c65_ax = { |
| 71 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19), | 71 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19), |
| 72 | .locked_status = CLKGEN_FIELD(0x0, 0x1, 31), | 72 | .locked_status = CLKGEN_FIELD(0x0, 0x1, 31), |
| 73 | .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0), | 73 | .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0), |
| @@ -76,7 +76,7 @@ static struct clkgen_pll_data st_pll800c65_ax = { | |||
| 76 | .ops = &st_pll800c65_ops | 76 | .ops = &st_pll800c65_ops |
| 77 | }; | 77 | }; |
| 78 | 78 | ||
| 79 | static struct clkgen_pll_data st_pll3200c32_a1x_0 = { | 79 | static const struct clkgen_pll_data st_pll3200c32_a1x_0 = { |
| 80 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 31), | 80 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 31), |
| 81 | .locked_status = CLKGEN_FIELD(0x4, 0x1, 31), | 81 | .locked_status = CLKGEN_FIELD(0x4, 0x1, 31), |
| 82 | .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0), | 82 | .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0), |
| @@ -93,7 +93,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_0 = { | |||
| 93 | .ops = &stm_pll3200c32_ops, | 93 | .ops = &stm_pll3200c32_ops, |
| 94 | }; | 94 | }; |
| 95 | 95 | ||
| 96 | static struct clkgen_pll_data st_pll3200c32_a1x_1 = { | 96 | static const struct clkgen_pll_data st_pll3200c32_a1x_1 = { |
| 97 | .pdn_status = CLKGEN_FIELD(0xC, 0x1, 31), | 97 | .pdn_status = CLKGEN_FIELD(0xC, 0x1, 31), |
| 98 | .locked_status = CLKGEN_FIELD(0x10, 0x1, 31), | 98 | .locked_status = CLKGEN_FIELD(0x10, 0x1, 31), |
| 99 | .ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0), | 99 | .ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0), |
| @@ -111,7 +111,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_1 = { | |||
| 111 | }; | 111 | }; |
| 112 | 112 | ||
| 113 | /* 415 specific */ | 113 | /* 415 specific */ |
| 114 | static struct clkgen_pll_data st_pll3200c32_a9_415 = { | 114 | static const struct clkgen_pll_data st_pll3200c32_a9_415 = { |
| 115 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), | 115 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), |
| 116 | .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0), | 116 | .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0), |
| 117 | .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9), | 117 | .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9), |
| @@ -122,7 +122,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_415 = { | |||
| 122 | .ops = &stm_pll3200c32_ops, | 122 | .ops = &stm_pll3200c32_ops, |
| 123 | }; | 123 | }; |
| 124 | 124 | ||
| 125 | static struct clkgen_pll_data st_pll3200c32_ddr_415 = { | 125 | static const struct clkgen_pll_data st_pll3200c32_ddr_415 = { |
| 126 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), | 126 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), |
| 127 | .locked_status = CLKGEN_FIELD(0x100, 0x1, 0), | 127 | .locked_status = CLKGEN_FIELD(0x100, 0x1, 0), |
| 128 | .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), | 128 | .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), |
| @@ -135,7 +135,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_415 = { | |||
| 135 | .ops = &stm_pll3200c32_ops, | 135 | .ops = &stm_pll3200c32_ops, |
| 136 | }; | 136 | }; |
| 137 | 137 | ||
| 138 | static struct clkgen_pll_data st_pll1200c32_gpu_415 = { | 138 | static const struct clkgen_pll_data st_pll1200c32_gpu_415 = { |
| 139 | .pdn_status = CLKGEN_FIELD(0x144, 0x1, 3), | 139 | .pdn_status = CLKGEN_FIELD(0x144, 0x1, 3), |
| 140 | .locked_status = CLKGEN_FIELD(0x168, 0x1, 0), | 140 | .locked_status = CLKGEN_FIELD(0x168, 0x1, 0), |
| 141 | .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3), | 141 | .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3), |
| @@ -146,7 +146,7 @@ static struct clkgen_pll_data st_pll1200c32_gpu_415 = { | |||
| 146 | }; | 146 | }; |
| 147 | 147 | ||
| 148 | /* 416 specific */ | 148 | /* 416 specific */ |
| 149 | static struct clkgen_pll_data st_pll3200c32_a9_416 = { | 149 | static const struct clkgen_pll_data st_pll3200c32_a9_416 = { |
| 150 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), | 150 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), |
| 151 | .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0), | 151 | .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0), |
| 152 | .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), | 152 | .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), |
| @@ -157,7 +157,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_416 = { | |||
| 157 | .ops = &stm_pll3200c32_ops, | 157 | .ops = &stm_pll3200c32_ops, |
| 158 | }; | 158 | }; |
| 159 | 159 | ||
| 160 | static struct clkgen_pll_data st_pll3200c32_ddr_416 = { | 160 | static const struct clkgen_pll_data st_pll3200c32_ddr_416 = { |
| 161 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), | 161 | .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), |
| 162 | .locked_status = CLKGEN_FIELD(0x10C, 0x1, 0), | 162 | .locked_status = CLKGEN_FIELD(0x10C, 0x1, 0), |
| 163 | .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), | 163 | .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), |
| @@ -170,7 +170,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_416 = { | |||
| 170 | .ops = &stm_pll3200c32_ops, | 170 | .ops = &stm_pll3200c32_ops, |
| 171 | }; | 171 | }; |
| 172 | 172 | ||
| 173 | static struct clkgen_pll_data st_pll1200c32_gpu_416 = { | 173 | static const struct clkgen_pll_data st_pll1200c32_gpu_416 = { |
| 174 | .pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3), | 174 | .pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3), |
| 175 | .locked_status = CLKGEN_FIELD(0x90C, 0x1, 0), | 175 | .locked_status = CLKGEN_FIELD(0x90C, 0x1, 0), |
| 176 | .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3), | 176 | .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3), |
| @@ -450,9 +450,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np) | |||
| 450 | * PLL0 HS (high speed) output | 450 | * PLL0 HS (high speed) output |
| 451 | */ | 451 | */ |
| 452 | clk_data->clks[0] = clkgen_pll_register(parent_name, | 452 | clk_data->clks[0] = clkgen_pll_register(parent_name, |
| 453 | &st_pll1600c65_ax, | 453 | (struct clkgen_pll_data *) &st_pll1600c65_ax, |
| 454 | reg + CLKGENAx_PLL0_OFFSET, | 454 | reg + CLKGENAx_PLL0_OFFSET, clk_name); |
| 455 | clk_name); | ||
| 456 | 455 | ||
| 457 | if (IS_ERR(clk_data->clks[0])) | 456 | if (IS_ERR(clk_data->clks[0])) |
| 458 | goto err; | 457 | goto err; |
| @@ -480,9 +479,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np) | |||
| 480 | * PLL1 output | 479 | * PLL1 output |
| 481 | */ | 480 | */ |
| 482 | clk_data->clks[2] = clkgen_pll_register(parent_name, | 481 | clk_data->clks[2] = clkgen_pll_register(parent_name, |
| 483 | &st_pll800c65_ax, | 482 | (struct clkgen_pll_data *) &st_pll800c65_ax, |
| 484 | reg + CLKGENAx_PLL1_OFFSET, | 483 | reg + CLKGENAx_PLL1_OFFSET, clk_name); |
| 485 | clk_name); | ||
| 486 | 484 | ||
| 487 | if (IS_ERR(clk_data->clks[2])) | 485 | if (IS_ERR(clk_data->clks[2])) |
| 488 | goto err; | 486 | goto err; |
