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-rw-r--r--arch/arm/boot/dts/omap3-n900.dts2
-rw-r--r--drivers/mfd/twl4030-power.c20
2 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index b15f1a77d684..1fe45d1f75ec 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -353,7 +353,7 @@
353 }; 353 };
354 354
355 twl_power: power { 355 twl_power: power {
356 compatible = "ti,twl4030-power-n900"; 356 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
357 ti,use_poweroff; 357 ti,use_poweroff;
358 }; 358 };
359}; 359};
diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
index 3bc969a5916b..4d3ff3771491 100644
--- a/drivers/mfd/twl4030-power.c
+++ b/drivers/mfd/twl4030-power.c
@@ -724,24 +724,24 @@ static struct twl4030_script *omap3_idle_scripts[] = {
724 * above. 724 * above.
725 */ 725 */
726static struct twl4030_resconfig omap3_idle_rconfig[] = { 726static struct twl4030_resconfig omap3_idle_rconfig[] = {
727 TWL_REMAP_SLEEP(RES_VAUX1, DEV_GRP_NULL, 0, 0), 727 TWL_REMAP_SLEEP(RES_VAUX1, TWL4030_RESCONFIG_UNDEF, 0, 0),
728 TWL_REMAP_SLEEP(RES_VAUX2, DEV_GRP_NULL, 0, 0), 728 TWL_REMAP_SLEEP(RES_VAUX2, TWL4030_RESCONFIG_UNDEF, 0, 0),
729 TWL_REMAP_SLEEP(RES_VAUX3, DEV_GRP_NULL, 0, 0), 729 TWL_REMAP_SLEEP(RES_VAUX3, TWL4030_RESCONFIG_UNDEF, 0, 0),
730 TWL_REMAP_SLEEP(RES_VAUX4, DEV_GRP_NULL, 0, 0), 730 TWL_REMAP_SLEEP(RES_VAUX4, TWL4030_RESCONFIG_UNDEF, 0, 0),
731 TWL_REMAP_SLEEP(RES_VMMC1, DEV_GRP_NULL, 0, 0), 731 TWL_REMAP_SLEEP(RES_VMMC1, TWL4030_RESCONFIG_UNDEF, 0, 0),
732 TWL_REMAP_SLEEP(RES_VMMC2, DEV_GRP_NULL, 0, 0), 732 TWL_REMAP_SLEEP(RES_VMMC2, TWL4030_RESCONFIG_UNDEF, 0, 0),
733 TWL_REMAP_OFF(RES_VPLL1, DEV_GRP_P1, 3, 1), 733 TWL_REMAP_OFF(RES_VPLL1, DEV_GRP_P1, 3, 1),
734 TWL_REMAP_SLEEP(RES_VPLL2, DEV_GRP_P1, 0, 0), 734 TWL_REMAP_SLEEP(RES_VPLL2, DEV_GRP_P1, 0, 0),
735 TWL_REMAP_SLEEP(RES_VSIM, DEV_GRP_NULL, 0, 0), 735 TWL_REMAP_SLEEP(RES_VSIM, TWL4030_RESCONFIG_UNDEF, 0, 0),
736 TWL_REMAP_SLEEP(RES_VDAC, DEV_GRP_NULL, 0, 0), 736 TWL_REMAP_SLEEP(RES_VDAC, TWL4030_RESCONFIG_UNDEF, 0, 0),
737 TWL_REMAP_SLEEP(RES_VINTANA1, TWL_DEV_GRP_P123, 1, 2), 737 TWL_REMAP_SLEEP(RES_VINTANA1, TWL_DEV_GRP_P123, 1, 2),
738 TWL_REMAP_SLEEP(RES_VINTANA2, TWL_DEV_GRP_P123, 0, 2), 738 TWL_REMAP_SLEEP(RES_VINTANA2, TWL_DEV_GRP_P123, 0, 2),
739 TWL_REMAP_SLEEP(RES_VINTDIG, TWL_DEV_GRP_P123, 1, 2), 739 TWL_REMAP_SLEEP(RES_VINTDIG, TWL_DEV_GRP_P123, 1, 2),
740 TWL_REMAP_SLEEP(RES_VIO, TWL_DEV_GRP_P123, 2, 2), 740 TWL_REMAP_SLEEP(RES_VIO, TWL_DEV_GRP_P123, 2, 2),
741 TWL_REMAP_OFF(RES_VDD1, DEV_GRP_P1, 4, 1), 741 TWL_REMAP_OFF(RES_VDD1, DEV_GRP_P1, 4, 1),
742 TWL_REMAP_OFF(RES_VDD2, DEV_GRP_P1, 3, 1), 742 TWL_REMAP_OFF(RES_VDD2, DEV_GRP_P1, 3, 1),
743 TWL_REMAP_SLEEP(RES_VUSB_1V5, DEV_GRP_NULL, 0, 0), 743 TWL_REMAP_SLEEP(RES_VUSB_1V5, TWL4030_RESCONFIG_UNDEF, 0, 0),
744 TWL_REMAP_SLEEP(RES_VUSB_1V8, DEV_GRP_NULL, 0, 0), 744 TWL_REMAP_SLEEP(RES_VUSB_1V8, TWL4030_RESCONFIG_UNDEF, 0, 0),
745 TWL_REMAP_SLEEP(RES_VUSB_3V1, TWL_DEV_GRP_P123, 0, 0), 745 TWL_REMAP_SLEEP(RES_VUSB_3V1, TWL_DEV_GRP_P123, 0, 0),
746 /* Resource #20 USB charge pump skipped */ 746 /* Resource #20 USB charge pump skipped */
747 TWL_REMAP_SLEEP(RES_REGEN, TWL_DEV_GRP_P123, 2, 1), 747 TWL_REMAP_SLEEP(RES_REGEN, TWL_DEV_GRP_P123, 2, 1),