aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mm/cache-l2x0.c502
1 files changed, 251 insertions, 251 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 3b6213838054..09fe0f5eada5 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -464,6 +464,175 @@ static int l2_wt_override;
464 * pass it though the device tree */ 464 * pass it though the device tree */
465static u32 cache_id_part_number_from_dt; 465static u32 cache_id_part_number_from_dt;
466 466
467static void __init l2x0_of_parse(const struct device_node *np,
468 u32 *aux_val, u32 *aux_mask)
469{
470 u32 data[2] = { 0, 0 };
471 u32 tag = 0;
472 u32 dirty = 0;
473 u32 val = 0, mask = 0;
474
475 of_property_read_u32(np, "arm,tag-latency", &tag);
476 if (tag) {
477 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
478 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
479 }
480
481 of_property_read_u32_array(np, "arm,data-latency",
482 data, ARRAY_SIZE(data));
483 if (data[0] && data[1]) {
484 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
485 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
486 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
487 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
488 }
489
490 of_property_read_u32(np, "arm,dirty-latency", &dirty);
491 if (dirty) {
492 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
493 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
494 }
495
496 *aux_val &= ~mask;
497 *aux_val |= val;
498 *aux_mask &= ~mask;
499}
500
501static void l2x0_resume(void)
502{
503 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
504 /* restore aux ctrl and enable l2 */
505 l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
506
507 writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
508 L2X0_AUX_CTRL);
509
510 l2x0_inv_all();
511
512 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
513 }
514}
515
516static const struct l2c_init_data of_l2x0_data __initconst = {
517 .of_parse = l2x0_of_parse,
518 .outer_cache = {
519 .inv_range = l2x0_inv_range,
520 .clean_range = l2x0_clean_range,
521 .flush_range = l2x0_flush_range,
522 .flush_all = l2x0_flush_all,
523 .disable = l2x0_disable,
524 .sync = l2x0_cache_sync,
525 .resume = l2x0_resume,
526 },
527};
528
529static void __init pl310_of_parse(const struct device_node *np,
530 u32 *aux_val, u32 *aux_mask)
531{
532 u32 data[3] = { 0, 0, 0 };
533 u32 tag[3] = { 0, 0, 0 };
534 u32 filter[2] = { 0, 0 };
535
536 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
537 if (tag[0] && tag[1] && tag[2])
538 writel_relaxed(
539 ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
540 ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
541 ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
542 l2x0_base + L2X0_TAG_LATENCY_CTRL);
543
544 of_property_read_u32_array(np, "arm,data-latency",
545 data, ARRAY_SIZE(data));
546 if (data[0] && data[1] && data[2])
547 writel_relaxed(
548 ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
549 ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
550 ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
551 l2x0_base + L2X0_DATA_LATENCY_CTRL);
552
553 of_property_read_u32_array(np, "arm,filter-ranges",
554 filter, ARRAY_SIZE(filter));
555 if (filter[1]) {
556 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
557 l2x0_base + L2X0_ADDR_FILTER_END);
558 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
559 l2x0_base + L2X0_ADDR_FILTER_START);
560 }
561}
562
563static void __init pl310_save(void __iomem *base)
564{
565 u32 l2x0_revision = readl_relaxed(base + L2X0_CACHE_ID) &
566 L2X0_CACHE_ID_RTL_MASK;
567
568 l2x0_saved_regs.tag_latency = readl_relaxed(base +
569 L2X0_TAG_LATENCY_CTRL);
570 l2x0_saved_regs.data_latency = readl_relaxed(base +
571 L2X0_DATA_LATENCY_CTRL);
572 l2x0_saved_regs.filter_end = readl_relaxed(base +
573 L2X0_ADDR_FILTER_END);
574 l2x0_saved_regs.filter_start = readl_relaxed(base +
575 L2X0_ADDR_FILTER_START);
576
577 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
578 /*
579 * From r2p0, there is Prefetch offset/control register
580 */
581 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
582 L2X0_PREFETCH_CTRL);
583 /*
584 * From r3p0, there is Power control register
585 */
586 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
587 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
588 L2X0_POWER_CTRL);
589 }
590}
591
592static void pl310_resume(void)
593{
594 u32 l2x0_revision;
595
596 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
597 /* restore pl310 setup */
598 writel_relaxed(l2x0_saved_regs.tag_latency,
599 l2x0_base + L2X0_TAG_LATENCY_CTRL);
600 writel_relaxed(l2x0_saved_regs.data_latency,
601 l2x0_base + L2X0_DATA_LATENCY_CTRL);
602 writel_relaxed(l2x0_saved_regs.filter_end,
603 l2x0_base + L2X0_ADDR_FILTER_END);
604 writel_relaxed(l2x0_saved_regs.filter_start,
605 l2x0_base + L2X0_ADDR_FILTER_START);
606
607 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
608 L2X0_CACHE_ID_RTL_MASK;
609
610 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
611 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
612 l2x0_base + L2X0_PREFETCH_CTRL);
613 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
614 writel_relaxed(l2x0_saved_regs.pwr_ctrl,
615 l2x0_base + L2X0_POWER_CTRL);
616 }
617 }
618
619 l2x0_resume();
620}
621
622static const struct l2c_init_data of_pl310_data __initconst = {
623 .of_parse = pl310_of_parse,
624 .save = pl310_save,
625 .outer_cache = {
626 .inv_range = l2x0_inv_range,
627 .clean_range = l2x0_clean_range,
628 .flush_range = l2x0_flush_range,
629 .flush_all = l2x0_flush_all,
630 .disable = l2x0_disable,
631 .sync = l2x0_cache_sync,
632 .resume = pl310_resume,
633 },
634};
635
467/* 636/*
468 * Note that the end addresses passed to Linux primitives are 637 * Note that the end addresses passed to Linux primitives are
469 * noninclusive, while the hardware cache range operations use 638 * noninclusive, while the hardware cache range operations use
@@ -562,6 +731,75 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
562 } 731 }
563} 732}
564 733
734static void aurora_save(void __iomem *base)
735{
736 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
737 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL);
738}
739
740static void aurora_resume(void)
741{
742 if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
743 writel_relaxed(l2x0_saved_regs.aux_ctrl,
744 l2x0_base + L2X0_AUX_CTRL);
745 writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
746 }
747}
748
749static void __init aurora_broadcast_l2_commands(void)
750{
751 __u32 u;
752 /* Enable Broadcasting of cache commands to L2*/
753 __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
754 u |= AURORA_CTRL_FW; /* Set the FW bit */
755 __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
756 isb();
757}
758
759static void __init aurora_of_parse(const struct device_node *np,
760 u32 *aux_val, u32 *aux_mask)
761{
762 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
763 u32 mask = AURORA_ACR_REPLACEMENT_MASK;
764
765 of_property_read_u32(np, "cache-id-part",
766 &cache_id_part_number_from_dt);
767
768 /* Determine and save the write policy */
769 l2_wt_override = of_property_read_bool(np, "wt-override");
770
771 if (l2_wt_override) {
772 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
773 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
774 }
775
776 *aux_val &= ~mask;
777 *aux_val |= val;
778 *aux_mask &= ~mask;
779}
780
781static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
782 .of_parse = aurora_of_parse,
783 .save = aurora_save,
784 .outer_cache = {
785 .inv_range = aurora_inv_range,
786 .clean_range = aurora_clean_range,
787 .flush_range = aurora_flush_range,
788 .flush_all = l2x0_flush_all,
789 .disable = l2x0_disable,
790 .sync = l2x0_cache_sync,
791 .resume = aurora_resume,
792 },
793};
794
795static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
796 .of_parse = aurora_of_parse,
797 .save = aurora_save,
798 .outer_cache = {
799 .resume = aurora_resume,
800 },
801};
802
565/* 803/*
566 * For certain Broadcom SoCs, depending on the address range, different offsets 804 * For certain Broadcom SoCs, depending on the address range, different offsets
567 * need to be added to the address before passing it to L2 for 805 * need to be added to the address before passing it to L2 for
@@ -703,108 +941,19 @@ static void bcm_flush_range(unsigned long start, unsigned long end)
703 new_end); 941 new_end);
704} 942}
705 943
706static void __init l2x0_of_parse(const struct device_node *np, 944static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
707 u32 *aux_val, u32 *aux_mask) 945 .of_parse = pl310_of_parse,
708{ 946 .save = pl310_save,
709 u32 data[2] = { 0, 0 }; 947 .outer_cache = {
710 u32 tag = 0; 948 .inv_range = bcm_inv_range,
711 u32 dirty = 0; 949 .clean_range = bcm_clean_range,
712 u32 val = 0, mask = 0; 950 .flush_range = bcm_flush_range,
713 951 .flush_all = l2x0_flush_all,
714 of_property_read_u32(np, "arm,tag-latency", &tag); 952 .disable = l2x0_disable,
715 if (tag) { 953 .sync = l2x0_cache_sync,
716 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; 954 .resume = pl310_resume,
717 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; 955 },
718 } 956};
719
720 of_property_read_u32_array(np, "arm,data-latency",
721 data, ARRAY_SIZE(data));
722 if (data[0] && data[1]) {
723 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
724 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
725 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
726 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
727 }
728
729 of_property_read_u32(np, "arm,dirty-latency", &dirty);
730 if (dirty) {
731 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
732 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
733 }
734
735 *aux_val &= ~mask;
736 *aux_val |= val;
737 *aux_mask &= ~mask;
738}
739
740static void __init pl310_of_parse(const struct device_node *np,
741 u32 *aux_val, u32 *aux_mask)
742{
743 u32 data[3] = { 0, 0, 0 };
744 u32 tag[3] = { 0, 0, 0 };
745 u32 filter[2] = { 0, 0 };
746
747 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
748 if (tag[0] && tag[1] && tag[2])
749 writel_relaxed(
750 ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
751 ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
752 ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
753 l2x0_base + L2X0_TAG_LATENCY_CTRL);
754
755 of_property_read_u32_array(np, "arm,data-latency",
756 data, ARRAY_SIZE(data));
757 if (data[0] && data[1] && data[2])
758 writel_relaxed(
759 ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
760 ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
761 ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
762 l2x0_base + L2X0_DATA_LATENCY_CTRL);
763
764 of_property_read_u32_array(np, "arm,filter-ranges",
765 filter, ARRAY_SIZE(filter));
766 if (filter[1]) {
767 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
768 l2x0_base + L2X0_ADDR_FILTER_END);
769 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
770 l2x0_base + L2X0_ADDR_FILTER_START);
771 }
772}
773
774static void __init pl310_save(void __iomem *base)
775{
776 u32 l2x0_revision = readl_relaxed(base + L2X0_CACHE_ID) &
777 L2X0_CACHE_ID_RTL_MASK;
778
779 l2x0_saved_regs.tag_latency = readl_relaxed(base +
780 L2X0_TAG_LATENCY_CTRL);
781 l2x0_saved_regs.data_latency = readl_relaxed(base +
782 L2X0_DATA_LATENCY_CTRL);
783 l2x0_saved_regs.filter_end = readl_relaxed(base +
784 L2X0_ADDR_FILTER_END);
785 l2x0_saved_regs.filter_start = readl_relaxed(base +
786 L2X0_ADDR_FILTER_START);
787
788 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
789 /*
790 * From r2p0, there is Prefetch offset/control register
791 */
792 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
793 L2X0_PREFETCH_CTRL);
794 /*
795 * From r3p0, there is Power control register
796 */
797 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
798 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
799 L2X0_POWER_CTRL);
800 }
801}
802
803static void aurora_save(void __iomem *base)
804{
805 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
806 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL);
807}
808 957
809static void __init tauros3_save(void __iomem *base) 958static void __init tauros3_save(void __iomem *base)
810{ 959{
@@ -814,60 +963,6 @@ static void __init tauros3_save(void __iomem *base)
814 readl_relaxed(base + L2X0_PREFETCH_CTRL); 963 readl_relaxed(base + L2X0_PREFETCH_CTRL);
815} 964}
816 965
817static void l2x0_resume(void)
818{
819 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
820 /* restore aux ctrl and enable l2 */
821 l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
822
823 writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
824 L2X0_AUX_CTRL);
825
826 l2x0_inv_all();
827
828 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
829 }
830}
831
832static void pl310_resume(void)
833{
834 u32 l2x0_revision;
835
836 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
837 /* restore pl310 setup */
838 writel_relaxed(l2x0_saved_regs.tag_latency,
839 l2x0_base + L2X0_TAG_LATENCY_CTRL);
840 writel_relaxed(l2x0_saved_regs.data_latency,
841 l2x0_base + L2X0_DATA_LATENCY_CTRL);
842 writel_relaxed(l2x0_saved_regs.filter_end,
843 l2x0_base + L2X0_ADDR_FILTER_END);
844 writel_relaxed(l2x0_saved_regs.filter_start,
845 l2x0_base + L2X0_ADDR_FILTER_START);
846
847 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
848 L2X0_CACHE_ID_RTL_MASK;
849
850 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
851 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
852 l2x0_base + L2X0_PREFETCH_CTRL);
853 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
854 writel_relaxed(l2x0_saved_regs.pwr_ctrl,
855 l2x0_base + L2X0_POWER_CTRL);
856 }
857 }
858
859 l2x0_resume();
860}
861
862static void aurora_resume(void)
863{
864 if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
865 writel_relaxed(l2x0_saved_regs.aux_ctrl,
866 l2x0_base + L2X0_AUX_CTRL);
867 writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
868 }
869}
870
871static void tauros3_resume(void) 966static void tauros3_resume(void)
872{ 967{
873 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 968 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
@@ -880,87 +975,6 @@ static void tauros3_resume(void)
880 l2x0_resume(); 975 l2x0_resume();
881} 976}
882 977
883static void __init aurora_broadcast_l2_commands(void)
884{
885 __u32 u;
886 /* Enable Broadcasting of cache commands to L2*/
887 __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
888 u |= AURORA_CTRL_FW; /* Set the FW bit */
889 __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
890 isb();
891}
892
893static void __init aurora_of_parse(const struct device_node *np,
894 u32 *aux_val, u32 *aux_mask)
895{
896 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
897 u32 mask = AURORA_ACR_REPLACEMENT_MASK;
898
899 of_property_read_u32(np, "cache-id-part",
900 &cache_id_part_number_from_dt);
901
902 /* Determine and save the write policy */
903 l2_wt_override = of_property_read_bool(np, "wt-override");
904
905 if (l2_wt_override) {
906 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
907 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
908 }
909
910 *aux_val &= ~mask;
911 *aux_val |= val;
912 *aux_mask &= ~mask;
913}
914
915static const struct l2c_init_data of_pl310_data __initconst = {
916 .of_parse = pl310_of_parse,
917 .save = pl310_save,
918 .outer_cache = {
919 .inv_range = l2x0_inv_range,
920 .clean_range = l2x0_clean_range,
921 .flush_range = l2x0_flush_range,
922 .flush_all = l2x0_flush_all,
923 .disable = l2x0_disable,
924 .sync = l2x0_cache_sync,
925 .resume = pl310_resume,
926 },
927};
928
929static const struct l2c_init_data of_l2x0_data __initconst = {
930 .of_parse = l2x0_of_parse,
931 .outer_cache = {
932 .inv_range = l2x0_inv_range,
933 .clean_range = l2x0_clean_range,
934 .flush_range = l2x0_flush_range,
935 .flush_all = l2x0_flush_all,
936 .disable = l2x0_disable,
937 .sync = l2x0_cache_sync,
938 .resume = l2x0_resume,
939 },
940};
941
942static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
943 .of_parse = aurora_of_parse,
944 .save = aurora_save,
945 .outer_cache = {
946 .inv_range = aurora_inv_range,
947 .clean_range = aurora_clean_range,
948 .flush_range = aurora_flush_range,
949 .flush_all = l2x0_flush_all,
950 .disable = l2x0_disable,
951 .sync = l2x0_cache_sync,
952 .resume = aurora_resume,
953 },
954};
955
956static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
957 .of_parse = aurora_of_parse,
958 .save = aurora_save,
959 .outer_cache = {
960 .resume = aurora_resume,
961 },
962};
963
964static const struct l2c_init_data of_tauros3_data __initconst = { 978static const struct l2c_init_data of_tauros3_data __initconst = {
965 .save = tauros3_save, 979 .save = tauros3_save,
966 /* Tauros3 broadcasts L1 cache operations to L2 */ 980 /* Tauros3 broadcasts L1 cache operations to L2 */
@@ -969,20 +983,6 @@ static const struct l2c_init_data of_tauros3_data __initconst = {
969 }, 983 },
970}; 984};
971 985
972static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
973 .of_parse = pl310_of_parse,
974 .save = pl310_save,
975 .outer_cache = {
976 .inv_range = bcm_inv_range,
977 .clean_range = bcm_clean_range,
978 .flush_range = bcm_flush_range,
979 .flush_all = l2x0_flush_all,
980 .disable = l2x0_disable,
981 .sync = l2x0_cache_sync,
982 .resume = pl310_resume,
983 },
984};
985
986#define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } 986#define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns }
987static const struct of_device_id l2x0_ids[] __initconst = { 987static const struct of_device_id l2x0_ids[] __initconst = {
988 L2C_ID("arm,l210-cache", of_l2x0_data), 988 L2C_ID("arm,l210-cache", of_l2x0_data),
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-15 17:33:10 -0400