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-rw-r--r--arch/arm/mach-orion5x/addr-map.c19
1 files changed, 3 insertions, 16 deletions
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 186f51ce7c11..e63fb05dc893 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -34,11 +34,7 @@
34 * Non-CPU Masters address decoding -- 34 * Non-CPU Masters address decoding --
35 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR 35 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
36 * banks only (the typical use case). 36 * banks only (the typical use case).
37 * Setup access for each master to DDR is issued by common.c. 37 * Setup access for each master to DDR is issued by platform device setup.
38 *
39 * Note: although orion_setbits() and orion_clrbits() are not atomic
40 * no locking is necessary here since code in this file is only called
41 * at boot time when there is no concurrency issues.
42 */ 38 */
43 39
44/* 40/*
@@ -48,10 +44,6 @@
48#define TARGET_DEV_BUS 1 44#define TARGET_DEV_BUS 1
49#define TARGET_PCI 3 45#define TARGET_PCI 3
50#define TARGET_PCIE 4 46#define TARGET_PCIE 4
51#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
52 ((n) == 1) ? 0xd : \
53 ((n) == 2) ? 0xb : \
54 ((n) == 3) ? 0x7 : 0xf)
55#define ATTR_PCIE_MEM 0x59 47#define ATTR_PCIE_MEM 0x59
56#define ATTR_PCIE_IO 0x51 48#define ATTR_PCIE_IO 0x51
57#define ATTR_PCIE_WA 0x79 49#define ATTR_PCIE_WA 0x79
@@ -61,17 +53,12 @@
61#define ATTR_DEV_CS1 0x1d 53#define ATTR_DEV_CS1 0x1d
62#define ATTR_DEV_CS2 0x1b 54#define ATTR_DEV_CS2 0x1b
63#define ATTR_DEV_BOOT 0xf 55#define ATTR_DEV_BOOT 0xf
64#define WIN_EN 1
65 56
66/* 57/*
67 * Helpers to get DDR bank info 58 * Helpers to get DDR bank info
68 */ 59 */
69#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) 60#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
70#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) 61#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
71#define DDR_MAX_CS 4
72#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
73#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
74#define DDR_BANK_EN 1
75 62
76/* 63/*
77 * CPU Address Decode Windows registers 64 * CPU Address Decode Windows registers