2 files changed, 33 insertions, 4 deletions

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 48b08eb9d9e4..b212ae12e5ac 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -8,6 +8,7 @@
  *   written by Ralf Baechle <ralf@linux-mips.org>
  */
 #include <linux/compiler.h>
+#include <linux/vmalloc.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/console.h>
@@ -1139,3 +1140,30 @@ static int __init edac_devinit(void)
         return err;
 }
 device_initcall(edac_devinit);
+
+static void __initdata *octeon_dummy_iospace;
+
+static int __init octeon_no_pci_init(void)
+{
+        /*
+         * Initially assume there is no PCI. The PCI/PCIe platform code will
+         * later re-initialize these to correct values if they are present.
+         */
+        octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
+        set_io_port_base((unsigned long)octeon_dummy_iospace);
+        ioport_resource.start = MAX_RESOURCE;
+        ioport_resource.end = 0;
+        return 0;
+}
+core_initcall(octeon_no_pci_init);
+
+static int __init octeon_no_pci_release(void)
+{
+        /*
+         * Release the allocated memory if a real IO space is there.
+         */
+        if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
+                vfree(octeon_dummy_iospace);
+        return 0;
+}
+late_initcall(octeon_no_pci_release);
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 95c2ea815cac..59cccd95688b 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -586,15 +586,16 @@ static int __init octeon_pci_setup(void)
         else
                 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
 
-        /* PCI I/O and PCI MEM values */
-        set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
-        ioport_resource.start = 0;
-        ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
         if (!octeon_is_pci_host()) {
                 pr_notice("Not in host mode, PCI Controller not initialized\n");
                 return 0;
         }
 
+        /* PCI I/O and PCI MEM values */
+        set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
+        ioport_resource.start = 0;
+        ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
+
         pr_notice("%s Octeon big bar support\n",
                   (octeon_dma_bar_type ==
                   OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");