2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index ecd016aef9d3..3add9ac252d7 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -473,8 +473,8 @@
                ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
                          0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
                          0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
-                          0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
+                          0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
-                          0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
+                          0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
                clocks = <&tegra_car TEGRA20_CLK_PEX>,
                         <&tegra_car TEGRA20_CLK_AFI>,
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index c8faccad0e65..d81c52e5b358 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -35,8 +35,8 @@
                          0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
                          0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
                          0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
-                          0x82000000 0 0x20000000 0x20000000 0 0x10000000   /* non-prefetchable memory */
+                          0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
-                          0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
+                          0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
                clocks = <&tegra_car TEGRA30_CLK_PCIE>,
                         <&tegra_car TEGRA30_CLK_AFI>,

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index ecd016aef9d3..3add9ac252d7 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -473,8 +473,8 @@
473	ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */	473	ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
474	0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */	474	0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
475	0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */	475	0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
476	0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */	476	0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
477	0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */	477	0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
478		478
479	clocks = <&tegra_car TEGRA20_CLK_PEX>,	479	clocks = <&tegra_car TEGRA20_CLK_PEX>,
480	<&tegra_car TEGRA20_CLK_AFI>,	480	<&tegra_car TEGRA20_CLK_AFI>,


diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index c8faccad0e65..d81c52e5b358 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -35,8 +35,8 @@
35	0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */	35	0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
36	0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */	36	0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
37	0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */	37	0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
38	0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */	38	0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
39	0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */	39	0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
40		40
41	clocks = <&tegra_car TEGRA30_CLK_PCIE>,	41	clocks = <&tegra_car TEGRA30_CLK_PCIE>,
42	<&tegra_car TEGRA30_CLK_AFI>,	42	<&tegra_car TEGRA30_CLK_AFI>,