25 files changed, 199 insertions, 165 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 64b49f549211..f8e0afb708b4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -974,7 +974,7 @@ S:	Maintained
 ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
 M:      Hans Ulli Kroll <ulli.kroll@googlemail.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-T:      git git://git.berlios.de/gemini-board
+T:      git git://github.com/ulli-kroll/linux.git
 S:      Maintained
 F:      arch/arm/mach-gemini/
 
@@ -1193,7 +1193,7 @@ ARM/MAGICIAN MACHINE SUPPORT
 M:      Philipp Zabel <philipp.zabel@gmail.com>
 S:      Maintained
 
-ARM/Marvell Armada 370 and Armada XP SOC support
+ARM/Marvell Kirkwood and Armada 370, 375, 38x, XP SOC support
 M:      Jason Cooper <jason@lakedaemon.net>
 M:      Andrew Lunn <andrew@lunn.ch>
 M:      Gregory Clement <gregory.clement@free-electrons.com>
@@ -1202,12 +1202,17 @@ L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      arch/arm/mach-mvebu/
 F:      drivers/rtc/rtc-armada38x.c
+F:      arch/arm/boot/dts/armada*
+F:      arch/arm/boot/dts/kirkwood*
+
 
 ARM/Marvell Berlin SoC support
 M:      Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      arch/arm/mach-berlin/
+F:      arch/arm/boot/dts/berlin*
+
 
 ARM/Marvell Dove/MV78xx0/Orion SOC support
 M:      Jason Cooper <jason@lakedaemon.net>
@@ -1220,6 +1225,9 @@ F:	arch/arm/mach-dove/
 F:      arch/arm/mach-mv78xx0/
 F:      arch/arm/mach-orion5x/
 F:      arch/arm/plat-orion/
+F:      arch/arm/boot/dts/dove*
+F:      arch/arm/boot/dts/orion5x*
+
 
 ARM/Orion SoC/Technologic Systems TS-78xx platform support
 M:      Alexander Clouter <alex@digriz.org.uk>
@@ -1371,6 +1379,7 @@ N:	rockchip
 
 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
 M:      Kukjin Kim <kgene@kernel.org>
+M:      Krzysztof Kozlowski <k.kozlowski@samsung.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 L:      linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
 S:      Maintained
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index c675257f2377..f076ff856d8b 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -69,7 +69,7 @@
                 mainpll: mainpll {
                         compatible = "fixed-clock";
                         #clock-cells = <0>;
-                        clock-frequency = <2000000000>;
+                        clock-frequency = <1000000000>;
                 };
                 /* 25 MHz reference crystal */
                 refclk: oscillator {
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index ed2dd8ba4080..218a2acd36e5 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -585,7 +585,7 @@
                 mainpll: mainpll {
                         compatible = "fixed-clock";
                         #clock-cells = <0>;
-                        clock-frequency = <2000000000>;
+                        clock-frequency = <1000000000>;
                 };
 
                 /* 25 MHz reference crystal */
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
index 0e85fc15ceda..ecd1318109ba 100644
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -502,7 +502,7 @@
                 mainpll: mainpll {
                         compatible = "fixed-clock";
                         #clock-cells = <0>;
-                        clock-frequency = <2000000000>;
+                        clock-frequency = <1000000000>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index aae7efc09b0b..e6fa251e17b9 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -87,6 +87,7 @@
 
                 /* connect xtal input to 25MHz reference */
                 clocks = <&ref25>;
+                clock-names = "xtal";
 
                 /* connect xtal input as source of pll0 and pll1 */
                 silabs,pll-source = <0 0>, <1 0>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 0788d08fb43e..146e71118a72 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -711,6 +711,7 @@
         num-slots = <1>;
         broken-cd;
         cap-sdio-irq;
+        keep-power-in-suspend;
         card-detect-delay = <200>;
         clock-frequency = <400000000>;
         samsung,dw-mshc-ciu-div = <1>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 412f41d62686..02eb8b15374f 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -674,6 +674,7 @@
         num-slots = <1>;
         broken-cd;
         cap-sdio-irq;
+        keep-power-in-suspend;
         card-detect-delay = <200>;
         clock-frequency = <400000000>;
         samsung,dw-mshc-ciu-div = <1>;
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index cf01c818b8ea..13cc7ca5e031 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -826,7 +826,7 @@
                          <&tegra_car TEGRA124_CLK_PLL_U>,
                          <&tegra_car TEGRA124_CLK_USBD>;
                 clock-names = "reg", "pll_u", "utmi-pads";
-                resets = <&tegra_car 59>, <&tegra_car 22>;
+                resets = <&tegra_car 22>, <&tegra_car 22>;
                 reset-names = "usb", "utmi-pads";
                 nvidia,hssync-start-delay = <0>;
                 nvidia,idle-wait-delay = <17>;
@@ -838,6 +838,7 @@
                 nvidia,hssquelch-level = <2>;
                 nvidia,hsdiscon-level = <5>;
                 nvidia,xcvr-hsslew = <12>;
+                nvidia,has-utmi-pad-registers;
                 status = "disabled";
         };
 
@@ -862,7 +863,7 @@
                          <&tegra_car TEGRA124_CLK_PLL_U>,
                          <&tegra_car TEGRA124_CLK_USBD>;
                 clock-names = "reg", "pll_u", "utmi-pads";
-                resets = <&tegra_car 22>, <&tegra_car 22>;
+                resets = <&tegra_car 58>, <&tegra_car 22>;
                 reset-names = "usb", "utmi-pads";
                 nvidia,hssync-start-delay = <0>;
                 nvidia,idle-wait-delay = <17>;
@@ -874,7 +875,6 @@
                 nvidia,hssquelch-level = <2>;
                 nvidia,hsdiscon-level = <5>;
                 nvidia,xcvr-hsslew = <12>;
-                nvidia,has-utmi-pad-registers;
                 status = "disabled";
         };
 
@@ -899,7 +899,7 @@
                          <&tegra_car TEGRA124_CLK_PLL_U>,
                          <&tegra_car TEGRA124_CLK_USBD>;
                 clock-names = "reg", "pll_u", "utmi-pads";
-                resets = <&tegra_car 58>, <&tegra_car 22>;
+                resets = <&tegra_car 59>, <&tegra_car 22>;
                 reset-names = "usb", "utmi-pads";
                 nvidia,hssync-start-delay = <0>;
                 nvidia,idle-wait-delay = <17>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 7a2aeacd62c0..107395c32d82 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -191,6 +191,7 @@
                 compatible = "arm,cortex-a15-pmu";
                 interrupts = <0 68 4>,
                              <0 69 4>;
+                interrupt-affinity = <&cpu0>, <&cpu1>;
         };
 
         oscclk6a: oscclk6a {
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 23662b5a5e9d..d949facba376 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -33,28 +33,28 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                cpu@0 {
+                A9_0: cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <0>;
                         next-level-cache = <&L2>;
                 };
 
-                cpu@1 {
+                A9_1: cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <1>;
                         next-level-cache = <&L2>;
                 };
 
-                cpu@2 {
+                A9_2: cpu@2 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <2>;
                         next-level-cache = <&L2>;
                 };
 
-                cpu@3 {
+                A9_3: cpu@3 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <3>;
@@ -170,6 +170,7 @@
                 compatible = "arm,pl310-cache";
                 reg = <0x1e00a000 0x1000>;
                 interrupts = <0 43 4>;
+                cache-unified;
                 cache-level = <2>;
                 arm,data-latency = <1 1 1>;
                 arm,tag-latency = <1 1 1>;
@@ -181,6 +182,8 @@
                              <0 61 4>,
                              <0 62 4>,
                              <0 63 4>;
+                interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
+
         };
 
         dcc {
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index acd5b560b728..5f5cd562c593 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -159,6 +159,8 @@ extern void exynos_enter_aftr(void);
 
 extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
 
+extern void exynos_set_delayed_reset_assertion(bool enable);
+
 extern void s5p_init_cpu(void __iomem *cpuid_addr);
 extern unsigned int samsung_rev(void);
 extern void __iomem *cpu_boot_reg_base(void);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index bcde0dd668df..5917a30eee33 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -167,6 +167,33 @@ static void __init exynos_init_io(void)
 }
 
 /*
+ * Set or clear the USE_DELAYED_RESET_ASSERTION option. Used by smp code
+ * and suspend.
+ *
+ * This is necessary only on Exynos4 SoCs. When system is running
+ * USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down
+ * feature could properly detect global idle state when secondary CPU is
+ * powered down.
+ *
+ * However this should not be set when such system is going into suspend.
+ */
+void exynos_set_delayed_reset_assertion(bool enable)
+{
+        if (of_machine_is_compatible("samsung,exynos4")) {
+                unsigned int tmp, core_id;
+
+                for (core_id = 0; core_id < num_possible_cpus(); core_id++) {
+                        tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
+                        if (enable)
+                                tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
+                        else
+                                tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
+                        pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
+                }
+        }
+}
+
+/*
  * Apparently, these SoCs are not able to wake-up from suspend using
  * the PMU. Too bad. Should they suddenly become capable of such a
  * feat, the matches below should be moved to suspend.c.
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index ebd135bb0995..a825bca2a2b6 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,30 +34,6 @@
 
 extern void exynos4_secondary_startup(void);
 
-/*
- * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs
- * during hot-(un)plugging CPUx.
- *
- * The feature can be cleared safely during first boot of secondary CPU.
- *
- * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering
- * down a CPU so the CPU idle clock down feature could properly detect global
- * idle state when CPUx is off.
- */
-static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable)
-{
-        if (soc_is_exynos4()) {
-                unsigned int tmp;
-
-                tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
-                if (enable)
-                        tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
-                else
-                        tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
-                pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
-        }
-}
-
 #ifdef CONFIG_HOTPLUG_CPU
 static inline void cpu_leave_lowpower(u32 core_id)
 {
@@ -73,8 +49,6 @@ static inline void cpu_leave_lowpower(u32 core_id)
           : "=&r" (v)
           : "Ir" (CR_C), "Ir" (0x40)
           : "cc");
-
-         exynos_set_delayed_reset_assertion(core_id, false);
 }
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
@@ -87,14 +61,6 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
                 /* Turn the CPU off on next WFI instruction. */
                 exynos_cpu_power_down(core_id);
 
-                /*
-                 * Exynos4 SoCs require setting
-                 * USE_DELAYED_RESET_ASSERTION so the CPU idle
-                 * clock down feature could properly detect
-                 * global idle state when CPUx is off.
-                 */
-                exynos_set_delayed_reset_assertion(core_id, true);
-
                 wfi();
 
                 if (pen_release == core_id) {
@@ -371,9 +337,6 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                 udelay(10);
         }
 
-        /* No harm if this is called during first boot of secondary CPU */
-        exynos_set_delayed_reset_assertion(core_id, false);
-
         /*
          * now the secondary core is starting up let it run its
          * calibrations, then wait for it to finish
@@ -420,6 +383,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 
         exynos_sysram_init();
 
+        exynos_set_delayed_reset_assertion(true);
+
         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
                 scu_enable(scu_base_addr());
 
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index cbe56b35aea0..a9686535f9ed 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -188,7 +188,7 @@ no_clk:
                 args.np = np;
                 args.args_count = 0;
                 child_domain = of_genpd_get_from_provider(&args);
-                if (!child_domain)
+                if (IS_ERR(child_domain))
                         continue;
 
                 if (of_parse_phandle_with_args(np, "power-domains",
@@ -196,7 +196,7 @@ no_clk:
                         continue;
 
                 parent_domain = of_genpd_get_from_provider(&args);
-                if (!parent_domain)
+                if (IS_ERR(parent_domain))
                         continue;
 
                 if (pm_genpd_add_subdomain(parent_domain, child_domain))
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 3e6aea7f83af..c0b6dccbf7bd 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -342,6 +342,8 @@ static void exynos_pm_enter_sleep_mode(void)
 
 static void exynos_pm_prepare(void)
 {
+        exynos_set_delayed_reset_assertion(false);
+
         /* Set wake-up mask registers */
         exynos_pm_set_wakeup_mask();
 
@@ -482,6 +484,7 @@ early_wakeup:
 
         /* Clear SLEEP mode set in INFORM1 */
         pmu_raw_writel(0x0, S5P_INFORM1);
+        exynos_set_delayed_reset_assertion(true);
 }
 
 static void exynos3250_pm_resume(void)
@@ -723,8 +726,10 @@ void __init exynos_pm_init(void)
                 return;
         }
 
-        if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL)))
+        if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
                 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
+                return;
+        }
 
         pm_data = (const struct exynos_pm_data *) match->data;
 
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h
index 38a45260a7c8..dd883698ff7e 100644
--- a/arch/arm/mach-gemini/common.h
+++ b/arch/arm/mach-gemini/common.h
@@ -12,6 +12,8 @@
 #ifndef __GEMINI_COMMON_H__
 #define __GEMINI_COMMON_H__
 
+#include <linux/reboot.h>
+
 struct mtd_partition;
 
 extern void gemini_map_io(void);
@@ -26,6 +28,6 @@ extern int platform_register_pflash(unsigned int size,
                                     struct mtd_partition *parts,
                                     unsigned int nr_parts);
 
-extern void gemini_restart(char mode, const char *cmd);
+extern void gemini_restart(enum reboot_mode mode, const char *cmd);
 
 #endif /* __GEMINI_COMMON_H__ */
diff --git a/arch/arm/mach-gemini/reset.c b/arch/arm/mach-gemini/reset.c
index b26659759e27..21a6d6d4f9c4 100644
--- a/arch/arm/mach-gemini/reset.c
+++ b/arch/arm/mach-gemini/reset.c
@@ -14,7 +14,9 @@
 #include <mach/hardware.h>
 #include <mach/global_reg.h>
 
-void gemini_restart(char mode, const char *cmd)
+#include "common.h"
+
+void gemini_restart(enum reboot_mode mode, const char *cmd)
 {
         __raw_writel(RESET_GLOBAL | RESET_CPU1,
                      IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 355b08936871..752969ff9de0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -171,6 +171,12 @@
  */
 #define LINKS_PER_OCP_IF                2
 
+/*
+ * Address offset (in bytes) between the reset control and the reset
+ * status registers: 4 bytes on OMAP4
+ */
+#define OMAP4_RST_CTRL_ST_OFFSET        4
+
 /**
  * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
  * @enable_module: function to enable a module (via MODULEMODE)
@@ -3016,10 +3022,12 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
         if (ohri->st_shift)
                 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
                        oh->name, ohri->name);
-        return omap_prm_deassert_hardreset(ohri->rst_shift, 0,
+        return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift,
                                            oh->clkdm->pwrdm.ptr->prcm_partition,
                                            oh->clkdm->pwrdm.ptr->prcm_offs,
-                                           oh->prcm.omap4.rstctrl_offs, 0);
+                                           oh->prcm.omap4.rstctrl_offs,
+                                           oh->prcm.omap4.rstctrl_offs +
+                                           OMAP4_RST_CTRL_ST_OFFSET);
 }
 
 /**
@@ -3048,27 +3056,6 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
 }
 
 /**
- * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args
- * @oh: struct omap_hwmod * to assert hardreset
- * @ohri: hardreset line data
- *
- * Call am33xx_prminst_assert_hardreset() with parameters extracted
- * from the hwmod @oh and the hardreset line data @ohri.  Only
- * intended for use as an soc_ops function pointer.  Passes along the
- * return value from am33xx_prminst_assert_hardreset().  XXX This
- * function is scheduled for removal when the PRM code is moved into
- * drivers/.
- */
-static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
-                                   struct omap_hwmod_rst_info *ohri)
-
-{
-        return omap_prm_assert_hardreset(ohri->rst_shift, 0,
-                                         oh->clkdm->pwrdm.ptr->prcm_offs,
-                                         oh->prcm.omap4.rstctrl_offs);
-}
-
-/**
  * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args
  * @oh: struct omap_hwmod * to deassert hardreset
  * @ohri: hardreset line data
@@ -3083,32 +3070,13 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
 static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
                                      struct omap_hwmod_rst_info *ohri)
 {
-        return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0,
+        return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift,
+                                           oh->clkdm->pwrdm.ptr->prcm_partition,
                                            oh->clkdm->pwrdm.ptr->prcm_offs,
                                            oh->prcm.omap4.rstctrl_offs,
                                            oh->prcm.omap4.rstst_offs);
 }
 
-/**
- * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args
- * @oh: struct omap_hwmod * to test hardreset
- * @ohri: hardreset line data
- *
- * Call am33xx_prminst_is_hardreset_asserted() with parameters
- * extracted from the hwmod @oh and the hardreset line data @ohri.
- * Only intended for use as an soc_ops function pointer.  Passes along
- * the return value from am33xx_prminst_is_hardreset_asserted().  XXX
- * This function is scheduled for removal when the PRM code is moved
- * into drivers/.
- */
-static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
-                                        struct omap_hwmod_rst_info *ohri)
-{
-        return omap_prm_is_hardreset_asserted(ohri->rst_shift, 0,
-                                              oh->clkdm->pwrdm.ptr->prcm_offs,
-                                              oh->prcm.omap4.rstctrl_offs);
-}
-
 /* Public functions */
 
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
@@ -3908,21 +3876,13 @@ void __init omap_hwmod_init(void)
                 soc_ops.init_clkdm = _init_clkdm;
                 soc_ops.update_context_lost = _omap4_update_context_lost;
                 soc_ops.get_context_lost = _omap4_get_context_lost;
-        } else if (soc_is_am43xx()) {
+        } else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) {
                 soc_ops.enable_module = _omap4_enable_module;
                 soc_ops.disable_module = _omap4_disable_module;
                 soc_ops.wait_target_ready = _omap4_wait_target_ready;
                 soc_ops.assert_hardreset = _omap4_assert_hardreset;
-                soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
-                soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
-                soc_ops.init_clkdm = _init_clkdm;
-        } else if (cpu_is_ti816x() || soc_is_am33xx()) {
-                soc_ops.enable_module = _omap4_enable_module;
-                soc_ops.disable_module = _omap4_disable_module;
-                soc_ops.wait_target_ready = _omap4_wait_target_ready;
-                soc_ops.assert_hardreset = _am33xx_assert_hardreset;
                 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
-                soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
+                soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
                 soc_ops.init_clkdm = _init_clkdm;
         } else {
                 WARN(1, "omap_hwmod: unknown SoC type\n");
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index e2223148ba4d..17e8004fc20f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -544,6 +544,44 @@ static struct omap_hwmod am43xx_hdq1w_hwmod = {
         },
 };
 
+static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x104,
+        .sysc_flags     = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                                MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
+        .name           = "vpfe",
+        .sysc           = &am43xx_vpfe_sysc,
+};
+
+static struct omap_hwmod am43xx_vpfe0_hwmod = {
+        .name           = "vpfe0",
+        .class          = &am43xx_vpfe_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                        .clkctrl_offs   = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
+                },
+        },
+};
+
+static struct omap_hwmod am43xx_vpfe1_hwmod = {
+        .name           = "vpfe1",
+        .class          = &am43xx_vpfe_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .prcm           = {
+                .omap4  = {
+                        .modulemode     = MODULEMODE_SWCTRL,
+                        .clkctrl_offs   = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
+                },
+        },
+};
+
 /* Interfaces */
 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
         .master         = &am33xx_l3_main_hwmod,
@@ -825,6 +863,34 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
+        .master         = &am43xx_vpfe0_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
+        .master         = &am43xx_vpfe1_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_vpfe0_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am43xx_vpfe1_hwmod,
+        .clk            = "l4ls_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_wkup__synctimer,
         &am43xx_l4_ls__timer8,
@@ -925,6 +991,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
         &am43xx_l4_ls__dss_dispc,
         &am43xx_l4_ls__dss_rfbi,
         &am43xx_l4_ls__hdq1w,
+        &am43xx_l3__vpfe0,
+        &am43xx_l3__vpfe1,
+        &am43xx_l4_ls__vpfe0,
+        &am43xx_l4_ls__vpfe1,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index 48df3b55057e..d0261996db6d 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -144,5 +144,6 @@
 #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET     0x05C0
 #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET                0x0a20
 #define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET              0x04a0
-
+#define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET              0x0068
+#define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET              0x0070
 #endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index c4859c4d3646..d0b15dbafa2e 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -87,12 +87,6 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
         return v;
 }
 
-/*
- * Address offset (in bytes) between the reset control and the reset
- * status registers: 4 bytes on OMAP4
- */
-#define OMAP4_RST_CTRL_ST_OFFSET                4
-
 /**
  * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
  * submodules contained in the hwmod module
@@ -141,11 +135,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
  * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
  * wait
  * @shift: register bit shift corresponding to the reset line to deassert
- * @st_shift: status bit offset, not used for OMAP4+
+ * @st_shift: status bit offset corresponding to the reset line
  * @part: PRM partition
  * @inst: PRM instance offset
  * @rstctrl_offs: reset register offset
- * @st_offs: reset status register offset, not used for OMAP4+
+ * @rstst_offs: reset status register offset
  *
  * Some IPs like dsp, ipu or iva contain processors that require an HW
  * reset line to be asserted / deasserted in order to fully enable the
@@ -157,11 +151,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
  * of reset, or -EBUSY if the submodule did not exit reset promptly.
  */
 int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
-                                     u16 rstctrl_offs, u16 st_offs)
+                                     u16 rstctrl_offs, u16 rstst_offs)
 {
         int c;
         u32 mask = 1 << shift;
-        u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
+        u32 st_mask = 1 << st_shift;
 
         /* Check the current status to avoid de-asserting the line twice */
         if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
@@ -169,13 +163,13 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
                 return -EEXIST;
 
         /* Clear the reset status by writing 1 to the status bit */
-        omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
+        omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
                                         rstst_offs);
         /* de-assert the reset control line */
         omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
         /* wait the status to be set */
-        omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
-                                                              rstst_offs),
+        omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
+                                                              inst, rstst_offs),
                           MAX_MODULE_HARDRESET_WAIT, c);
 
         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index cef67af9e9b8..cac46d852da1 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -298,14 +298,11 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         if (IS_ERR(src))
                 return PTR_ERR(src);
 
-        if (clk_get_parent(timer->fclk) != src) {
-                r = clk_set_parent(timer->fclk, src);
-                if (r < 0) {
-                        pr_warn("%s: %s cannot set source\n", __func__,
-                                oh->name);
-                        clk_put(src);
-                        return r;
-                }
+        r = clk_set_parent(timer->fclk, src);
+        if (r < 0) {
+                pr_warn("%s: %s cannot set source\n", __func__, oh->name);
+                clk_put(src);
+                return r;
         }
 
         clk_put(src);
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index 22812fe06460..b0dcbe28f78c 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -44,11 +44,9 @@ static void __iomem *rk3288_bootram_base;
 static phys_addr_t rk3288_bootram_phy;
 
 static struct regmap *pmu_regmap;
-static struct regmap *grf_regmap;
 static struct regmap *sgrf_regmap;
 
 static u32 rk3288_pmu_pwr_mode_con;
-static u32 rk3288_grf_soc_con0;
 static u32 rk3288_sgrf_soc_con0;
 
 static inline u32 rk3288_l2_config(void)
@@ -72,26 +70,12 @@ static void rk3288_slp_mode_set(int level)
 {
         u32 mode_set, mode_set1;
 
-        regmap_read(grf_regmap, RK3288_GRF_SOC_CON0, &rk3288_grf_soc_con0);
-
         regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
 
         regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
                     &rk3288_pmu_pwr_mode_con);
 
         /*
-         * We need set this bit GRF_FORCE_JTAG here, for the debug module,
-         * otherwise, it may become inaccessible after resume.
-         * This creates a potential security issue, as the sdmmc pins may
-         * accept jtag data for a short time during resume if no card is
-         * inserted.
-         * But this is of course also true for the regular boot, before we
-         * turn of the jtag/sdmmc autodetect.
-         */
-        regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, GRF_FORCE_JTAG |
-                     GRF_FORCE_JTAG_WRITE);
-
-        /*
          * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
          * PCLK_WDT_GATE - disable WDT during suspend.
          */
@@ -151,9 +135,6 @@ static void rk3288_slp_mode_set_resume(void)
         regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
                      rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
                      | SGRF_FAST_BOOT_EN_WRITE);
-
-        regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, rk3288_grf_soc_con0 |
-                     GRF_FORCE_JTAG_WRITE);
 }
 
 static int rockchip_lpmode_enter(unsigned long arg)
@@ -212,13 +193,6 @@ static int rk3288_suspend_init(struct device_node *np)
                 return PTR_ERR(pmu_regmap);
         }
 
-        grf_regmap = syscon_regmap_lookup_by_compatible(
-                                "rockchip,rk3288-grf");
-        if (IS_ERR(grf_regmap)) {
-                pr_err("%s: could not find grf regmap\n", __func__);
-                return PTR_ERR(pmu_regmap);
-        }
-
         sram_np = of_find_compatible_node(NULL, NULL,
                                           "rockchip,rk3288-pmu-sram");
         if (!sram_np) {
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
index f8a747bc1437..3e8d39c0c3d5 100644
--- a/arch/arm/mach-rockchip/pm.h
+++ b/arch/arm/mach-rockchip/pm.h
@@ -48,10 +48,6 @@ static inline void rockchip_suspend_init(void)
 #define RK3288_PMU_WAKEUP_RST_CLR_CNT   0x44
 #define RK3288_PMU_PWRMODE_CON1         0x90
 
-#define RK3288_GRF_SOC_CON0             0x244
-#define GRF_FORCE_JTAG                  BIT(12)
-#define GRF_FORCE_JTAG_WRITE            BIT(28)
-
 #define RK3288_SGRF_SOC_CON0            (0x0000)
 #define RK3288_SGRF_FAST_BOOT_ADDR      (0x0120)
 #define SGRF_PCLK_WDT_GATE              BIT(6)
diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
index c138b95a8356..351c95bda89e 100644
--- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
@@ -21,6 +21,20 @@
                         clock-output-names = "juno_mb:clk25mhz";
                 };
 
+                v2m_refclk1mhz: refclk1mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                        clock-output-names = "juno_mb:refclk1mhz";
+                };
+
+                v2m_refclk32khz: refclk32khz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "juno_mb:refclk32khz";
+                };
+
                 motherboard {
                         compatible = "arm,vexpress,v2p-p1", "simple-bus";
                         #address-cells = <2>;  /* SMB chipselect number and offset */
@@ -66,6 +80,15 @@
                                 #size-cells = <1>;
                                 ranges = <0 3 0 0x200000>;
 
+                                v2m_sysctl: sysctl@020000 {
+                                        compatible = "arm,sp810", "arm,primecell";
+                                        reg = <0x020000 0x1000>;
+                                        clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
+                                        clock-names = "refclk", "timclk", "apb_pclk";
+                                        #clock-cells = <1>;
+                                        clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+                                };
+
                                 mmci@050000 {
                                         compatible = "arm,pl180", "arm,primecell";
                                         reg = <0x050000 0x1000>;
@@ -106,16 +129,16 @@
                                         compatible = "arm,sp804", "arm,primecell";
                                         reg = <0x110000 0x10000>;
                                         interrupts = <9>;
-                                        clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
-                                        clock-names = "timclken1", "apb_pclk";
+                                        clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
+                                        clock-names = "timclken1", "timclken2", "apb_pclk";
                                 };
 
                                 v2m_timer23: timer@120000 {
                                         compatible = "arm,sp804", "arm,primecell";
                                         reg = <0x120000 0x10000>;
                                         interrupts = <9>;
-                                        clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
-                                        clock-names = "timclken1", "apb_pclk";
+                                        clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
+                                        clock-names = "timclken1", "timclken2", "apb_pclk";
                                 };
 
                                 rtc@170000 {