diff options
| -rw-r--r-- | arch/arm/mach-shmobile/smp-sh73a0.c | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 96ddb97babbe..624f00f70abf 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c | |||
| @@ -41,6 +41,9 @@ static void __iomem *scu_base_addr(void) | |||
| 41 | return (void __iomem *)0xf0000000; | 41 | return (void __iomem *)0xf0000000; |
| 42 | } | 42 | } |
| 43 | 43 | ||
| 44 | static DEFINE_SPINLOCK(scu_lock); | ||
| 45 | static unsigned long tmp; | ||
| 46 | |||
| 44 | #ifdef CONFIG_HAVE_ARM_TWD | 47 | #ifdef CONFIG_HAVE_ARM_TWD |
| 45 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); | 48 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); |
| 46 | void __init sh73a0_register_twd(void) | 49 | void __init sh73a0_register_twd(void) |
| @@ -49,6 +52,20 @@ void __init sh73a0_register_twd(void) | |||
| 49 | } | 52 | } |
| 50 | #endif | 53 | #endif |
| 51 | 54 | ||
| 55 | static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) | ||
| 56 | { | ||
| 57 | void __iomem *scu_base = scu_base_addr(); | ||
| 58 | |||
| 59 | spin_lock(&scu_lock); | ||
| 60 | tmp = __raw_readl(scu_base + 8); | ||
| 61 | tmp &= ~clr; | ||
| 62 | tmp |= set; | ||
| 63 | spin_unlock(&scu_lock); | ||
| 64 | |||
| 65 | /* disable cache coherency after releasing the lock */ | ||
| 66 | __raw_writel(tmp, scu_base + 8); | ||
| 67 | } | ||
| 68 | |||
| 52 | static unsigned int __init sh73a0_get_core_count(void) | 69 | static unsigned int __init sh73a0_get_core_count(void) |
| 53 | { | 70 | { |
| 54 | void __iomem *scu_base = scu_base_addr(); | 71 | void __iomem *scu_base = scu_base_addr(); |
| @@ -66,7 +83,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct | |||
| 66 | cpu = cpu_logical_map(cpu); | 83 | cpu = cpu_logical_map(cpu); |
| 67 | 84 | ||
| 68 | /* enable cache coherency */ | 85 | /* enable cache coherency */ |
| 69 | scu_power_mode(scu_base_addr(), 0); | 86 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); |
| 70 | 87 | ||
| 71 | if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3) | 88 | if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3) |
| 72 | __raw_writel(1 << cpu, WUPCR); /* wake up */ | 89 | __raw_writel(1 << cpu, WUPCR); /* wake up */ |
| @@ -78,6 +95,8 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct | |||
| 78 | 95 | ||
| 79 | static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) | 96 | static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) |
| 80 | { | 97 | { |
| 98 | int cpu = cpu_logical_map(0); | ||
| 99 | |||
| 81 | scu_enable(scu_base_addr()); | 100 | scu_enable(scu_base_addr()); |
| 82 | 101 | ||
| 83 | /* Map the reset vector (in headsmp.S) */ | 102 | /* Map the reset vector (in headsmp.S) */ |
| @@ -85,7 +104,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) | |||
| 85 | __raw_writel(__pa(shmobile_secondary_vector), SBAR); | 104 | __raw_writel(__pa(shmobile_secondary_vector), SBAR); |
| 86 | 105 | ||
| 87 | /* enable cache coherency on CPU0 */ | 106 | /* enable cache coherency on CPU0 */ |
| 88 | scu_power_mode(scu_base_addr(), 0); | 107 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); |
| 89 | } | 108 | } |
| 90 | 109 | ||
| 91 | static void __init sh73a0_smp_init_cpus(void) | 110 | static void __init sh73a0_smp_init_cpus(void) |
