diff options
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bios.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_gem.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mem.c | 30 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_instmem.c | 25 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_graph.c | 22 |
5 files changed, 47 insertions, 45 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index ff339df6f007..1aa73d3957e1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c | |||
@@ -135,13 +135,14 @@ static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) | |||
135 | int i; | 135 | int i; |
136 | 136 | ||
137 | if (dev_priv->card_type >= NV_50) { | 137 | if (dev_priv->card_type >= NV_50) { |
138 | uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8; | 138 | u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8; |
139 | 139 | if (!addr) { | |
140 | if (!vbios_vram) | 140 | addr = (u64)nv_rd32(dev, 0x1700) << 16; |
141 | vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000; | 141 | addr += 0xf0000; |
142 | } | ||
142 | 143 | ||
143 | old_bar0_pramin = nv_rd32(dev, 0x1700); | 144 | old_bar0_pramin = nv_rd32(dev, 0x1700); |
144 | nv_wr32(dev, 0x1700, vbios_vram >> 16); | 145 | nv_wr32(dev, 0x1700, addr >> 16); |
145 | } | 146 | } |
146 | 147 | ||
147 | /* bail if no rom signature */ | 148 | /* bail if no rom signature */ |
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 022393777805..5f0bc57fdaab 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c | |||
@@ -113,8 +113,10 @@ nouveau_gem_object_close(struct drm_gem_object *gem, struct drm_file *file_priv) | |||
113 | 113 | ||
114 | vma = nouveau_bo_vma_find(nvbo, fpriv->vm); | 114 | vma = nouveau_bo_vma_find(nvbo, fpriv->vm); |
115 | if (vma) { | 115 | if (vma) { |
116 | if (--vma->refcount == 0) | 116 | if (--vma->refcount == 0) { |
117 | nouveau_bo_vma_del(nvbo, vma); | 117 | nouveau_bo_vma_del(nvbo, vma); |
118 | kfree(vma); | ||
119 | } | ||
118 | } | 120 | } |
119 | ttm_bo_unreserve(&nvbo->bo); | 121 | ttm_bo_unreserve(&nvbo->bo); |
120 | } | 122 | } |
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 765f0e57da78..81dadeb9debc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c | |||
@@ -423,34 +423,6 @@ nouveau_mem_vram_init(struct drm_device *dev) | |||
423 | return ret; | 423 | return ret; |
424 | } | 424 | } |
425 | 425 | ||
426 | /* reserve space at end of VRAM for PRAMIN */ | ||
427 | if (dev_priv->card_type >= NV_50) { | ||
428 | dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024; | ||
429 | } else | ||
430 | if (dev_priv->card_type >= NV_40) { | ||
431 | u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8); | ||
432 | u32 rsvd; | ||
433 | |||
434 | /* estimate grctx size, the magics come from nv40_grctx.c */ | ||
435 | if (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs; | ||
436 | else if (dev_priv->chipset < 0x43) rsvd = 0x4f00 * vs; | ||
437 | else if (nv44_graph_class(dev)) rsvd = 0x4980 * vs; | ||
438 | else rsvd = 0x4a40 * vs; | ||
439 | rsvd += 16 * 1024; | ||
440 | rsvd *= dev_priv->engine.fifo.channels; | ||
441 | |||
442 | /* pciegart table */ | ||
443 | if (drm_pci_device_is_pcie(dev)) | ||
444 | rsvd += 512 * 1024; | ||
445 | |||
446 | /* object storage */ | ||
447 | rsvd += 512 * 1024; | ||
448 | |||
449 | dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096); | ||
450 | } else { | ||
451 | dev_priv->ramin_rsvd_vram = 512 * 1024; | ||
452 | } | ||
453 | |||
454 | NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20)); | 426 | NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20)); |
455 | if (dev_priv->vram_sys_base) { | 427 | if (dev_priv->vram_sys_base) { |
456 | NV_INFO(dev, "Stolen system memory at: 0x%010llx\n", | 428 | NV_INFO(dev, "Stolen system memory at: 0x%010llx\n", |
@@ -846,8 +818,8 @@ nouveau_gart_manager_del(struct ttm_mem_type_manager *man, | |||
846 | struct ttm_mem_reg *mem) | 818 | struct ttm_mem_reg *mem) |
847 | { | 819 | { |
848 | nouveau_mem_node_cleanup(mem->mm_node); | 820 | nouveau_mem_node_cleanup(mem->mm_node); |
849 | mem->mm_node = NULL; | ||
850 | kfree(mem->mm_node); | 821 | kfree(mem->mm_node); |
822 | mem->mm_node = NULL; | ||
851 | } | 823 | } |
852 | 824 | ||
853 | static int | 825 | static int |
diff --git a/drivers/gpu/drm/nouveau/nv04_instmem.c b/drivers/gpu/drm/nouveau/nv04_instmem.c index ae36bfc84853..e2075dec84a3 100644 --- a/drivers/gpu/drm/nouveau/nv04_instmem.c +++ b/drivers/gpu/drm/nouveau/nv04_instmem.c | |||
@@ -28,6 +28,31 @@ int nv04_instmem_init(struct drm_device *dev) | |||
28 | /* RAMIN always available */ | 28 | /* RAMIN always available */ |
29 | dev_priv->ramin_available = true; | 29 | dev_priv->ramin_available = true; |
30 | 30 | ||
31 | /* Reserve space at end of VRAM for PRAMIN */ | ||
32 | if (dev_priv->card_type >= NV_40) { | ||
33 | u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8); | ||
34 | u32 rsvd; | ||
35 | |||
36 | /* estimate grctx size, the magics come from nv40_grctx.c */ | ||
37 | if (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs; | ||
38 | else if (dev_priv->chipset < 0x43) rsvd = 0x4f00 * vs; | ||
39 | else if (nv44_graph_class(dev)) rsvd = 0x4980 * vs; | ||
40 | else rsvd = 0x4a40 * vs; | ||
41 | rsvd += 16 * 1024; | ||
42 | rsvd *= dev_priv->engine.fifo.channels; | ||
43 | |||
44 | /* pciegart table */ | ||
45 | if (drm_pci_device_is_pcie(dev)) | ||
46 | rsvd += 512 * 1024; | ||
47 | |||
48 | /* object storage */ | ||
49 | rsvd += 512 * 1024; | ||
50 | |||
51 | dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096); | ||
52 | } else { | ||
53 | dev_priv->ramin_rsvd_vram = 512 * 1024; | ||
54 | } | ||
55 | |||
31 | /* Setup shared RAMHT */ | 56 | /* Setup shared RAMHT */ |
32 | ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096, | 57 | ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096, |
33 | NVOBJ_FLAG_ZERO_ALLOC, &ramht); | 58 | NVOBJ_FLAG_ZERO_ALLOC, &ramht); |
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c index 39e9208a708c..3a97431996c5 100644 --- a/drivers/gpu/drm/nouveau/nvc0_graph.c +++ b/drivers/gpu/drm/nouveau/nvc0_graph.c | |||
@@ -106,7 +106,8 @@ nvc0_graph_construct_context(struct nouveau_channel *chan) | |||
106 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { | 106 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { |
107 | NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n"); | 107 | NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n"); |
108 | nvc0_graph_ctxctl_debug(dev); | 108 | nvc0_graph_ctxctl_debug(dev); |
109 | return -EBUSY; | 109 | ret = -EBUSY; |
110 | goto err; | ||
110 | } | 111 | } |
111 | } else { | 112 | } else { |
112 | nvc0_graph_load_context(chan); | 113 | nvc0_graph_load_context(chan); |
@@ -119,10 +120,8 @@ nvc0_graph_construct_context(struct nouveau_channel *chan) | |||
119 | } | 120 | } |
120 | 121 | ||
121 | ret = nvc0_grctx_generate(chan); | 122 | ret = nvc0_grctx_generate(chan); |
122 | if (ret) { | 123 | if (ret) |
123 | kfree(ctx); | 124 | goto err; |
124 | return ret; | ||
125 | } | ||
126 | 125 | ||
127 | if (!nouveau_ctxfw) { | 126 | if (!nouveau_ctxfw) { |
128 | nv_wr32(dev, 0x409840, 0x80000000); | 127 | nv_wr32(dev, 0x409840, 0x80000000); |
@@ -131,14 +130,13 @@ nvc0_graph_construct_context(struct nouveau_channel *chan) | |||
131 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { | 130 | if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) { |
132 | NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n"); | 131 | NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n"); |
133 | nvc0_graph_ctxctl_debug(dev); | 132 | nvc0_graph_ctxctl_debug(dev); |
134 | return -EBUSY; | 133 | ret = -EBUSY; |
134 | goto err; | ||
135 | } | 135 | } |
136 | } else { | 136 | } else { |
137 | ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst); | 137 | ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst); |
138 | if (ret) { | 138 | if (ret) |
139 | kfree(ctx); | 139 | goto err; |
140 | return ret; | ||
141 | } | ||
142 | } | 140 | } |
143 | 141 | ||
144 | for (i = 0; i < priv->grctx_size; i += 4) | 142 | for (i = 0; i < priv->grctx_size; i += 4) |
@@ -146,6 +144,10 @@ nvc0_graph_construct_context(struct nouveau_channel *chan) | |||
146 | 144 | ||
147 | priv->grctx_vals = ctx; | 145 | priv->grctx_vals = ctx; |
148 | return 0; | 146 | return 0; |
147 | |||
148 | err: | ||
149 | kfree(ctx); | ||
150 | return ret; | ||
149 | } | 151 | } |
150 | 152 | ||
151 | static int | 153 | static int |