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-rw-r--r--drivers/gpu/drm/radeon/r100.c413
-rw-r--r--drivers/gpu/drm/radeon/r100d.h107
-rw-r--r--drivers/gpu/drm/radeon/r200.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon.h3
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h50
-rw-r--r--drivers/gpu/drm/radeon/rs100d.h40
-rw-r--r--drivers/gpu/drm/radeon/rv200d.h36
-rw-r--r--drivers/gpu/drm/radeon/rv250d.h123
8 files changed, 586 insertions, 189 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index dc45ec1d4189..0a475617a70f 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -32,6 +32,9 @@
32#include "radeon_reg.h" 32#include "radeon_reg.h"
33#include "radeon.h" 33#include "radeon.h"
34#include "r100d.h" 34#include "r100d.h"
35#include "rs100d.h"
36#include "rv200d.h"
37#include "rv250d.h"
35 38
36#include <linux/firmware.h> 39#include <linux/firmware.h>
37#include <linux/platform_device.h> 40#include <linux/platform_device.h>
@@ -60,18 +63,7 @@ MODULE_FIRMWARE(FIRMWARE_R520);
60 63
61/* This files gather functions specifics to: 64/* This files gather functions specifics to:
62 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
63 *
64 * Some of these functions might be used by newer ASICs.
65 */ 66 */
66int r200_init(struct radeon_device *rdev);
67void r100_hdp_reset(struct radeon_device *rdev);
68void r100_gpu_init(struct radeon_device *rdev);
69int r100_gui_wait_for_idle(struct radeon_device *rdev);
70int r100_mc_wait_for_idle(struct radeon_device *rdev);
71void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
72void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
73int r100_debugfs_mc_info_init(struct radeon_device *rdev);
74
75 67
76/* 68/*
77 * PCI GART 69 * PCI GART
@@ -152,136 +144,6 @@ void r100_pci_gart_fini(struct radeon_device *rdev)
152 radeon_gart_fini(rdev); 144 radeon_gart_fini(rdev);
153} 145}
154 146
155
156/*
157 * MC
158 */
159void r100_mc_disable_clients(struct radeon_device *rdev)
160{
161 uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
162
163 /* FIXME: is this function correct for rs100,rs200,rs300 ? */
164 if (r100_gui_wait_for_idle(rdev)) {
165 printk(KERN_WARNING "Failed to wait GUI idle while "
166 "programming pipes. Bad things might happen.\n");
167 }
168
169 /* stop display and memory access */
170 ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
171 WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
172 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
173 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
174 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
175
176 r100_gpu_wait_for_vsync(rdev);
177
178 WREG32(RADEON_CRTC_GEN_CNTL,
179 (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
180 RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
181
182 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
183 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
184
185 r100_gpu_wait_for_vsync2(rdev);
186 WREG32(RADEON_CRTC2_GEN_CNTL,
187 (crtc2_gen_cntl &
188 ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
189 RADEON_CRTC2_DISP_REQ_EN_B);
190 }
191
192 udelay(500);
193}
194
195void r100_mc_setup(struct radeon_device *rdev)
196{
197 uint32_t tmp;
198 int r;
199
200 r = r100_debugfs_mc_info_init(rdev);
201 if (r) {
202 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
203 }
204 /* Write VRAM size in case we are limiting it */
205 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
206 /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
207 * if the aperture is 64MB but we have 32MB VRAM
208 * we report only 32MB VRAM but we have to set MC_FB_LOCATION
209 * to 64MB, otherwise the gpu accidentially dies */
210 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
211 tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
212 tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
213 WREG32(RADEON_MC_FB_LOCATION, tmp);
214
215 /* Enable bus mastering */
216 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
217 WREG32(RADEON_BUS_CNTL, tmp);
218
219 if (rdev->flags & RADEON_IS_AGP) {
220 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
221 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
222 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
223 WREG32(RADEON_MC_AGP_LOCATION, tmp);
224 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
225 } else {
226 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
227 WREG32(RADEON_AGP_BASE, 0);
228 }
229
230 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
231 tmp |= (7 << 28);
232 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
233 (void)RREG32(RADEON_HOST_PATH_CNTL);
234 WREG32(RADEON_HOST_PATH_CNTL, tmp);
235 (void)RREG32(RADEON_HOST_PATH_CNTL);
236}
237
238int r100_mc_init(struct radeon_device *rdev)
239{
240 int r;
241
242 if (r100_debugfs_rbbm_init(rdev)) {
243 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
244 }
245
246 r100_gpu_init(rdev);
247 /* Disable gart which also disable out of gart access */
248 r100_pci_gart_disable(rdev);
249
250 /* Setup GPU memory space */
251 rdev->mc.gtt_location = 0xFFFFFFFFUL;
252 if (rdev->flags & RADEON_IS_AGP) {
253 r = radeon_agp_init(rdev);
254 if (r) {
255 printk(KERN_WARNING "[drm] Disabling AGP\n");
256 rdev->flags &= ~RADEON_IS_AGP;
257 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
258 } else {
259 rdev->mc.gtt_location = rdev->mc.agp_base;
260 }
261 }
262 r = radeon_mc_setup(rdev);
263 if (r) {
264 return r;
265 }
266
267 r100_mc_disable_clients(rdev);
268 if (r100_mc_wait_for_idle(rdev)) {
269 printk(KERN_WARNING "Failed to wait MC idle while "
270 "programming pipes. Bad things might happen.\n");
271 }
272
273 r100_mc_setup(rdev);
274 return 0;
275}
276
277void r100_mc_fini(struct radeon_device *rdev)
278{
279}
280
281
282/*
283 * Interrupts
284 */
285int r100_irq_set(struct radeon_device *rdev) 147int r100_irq_set(struct radeon_device *rdev)
286{ 148{
287 uint32_t tmp = 0; 149 uint32_t tmp = 0;
@@ -358,10 +220,6 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
358 return RREG32(RADEON_CRTC2_CRNT_FRAME); 220 return RREG32(RADEON_CRTC2_CRNT_FRAME);
359} 221}
360 222
361
362/*
363 * Fence emission
364 */
365void r100_fence_ring_emit(struct radeon_device *rdev, 223void r100_fence_ring_emit(struct radeon_device *rdev,
366 struct radeon_fence *fence) 224 struct radeon_fence *fence)
367{ 225{
@@ -377,10 +235,6 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
377 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 235 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
378} 236}
379 237
380
381/*
382 * Writeback
383 */
384int r100_wb_init(struct radeon_device *rdev) 238int r100_wb_init(struct radeon_device *rdev)
385{ 239{
386 int r; 240 int r;
@@ -504,10 +358,6 @@ int r100_copy_blit(struct radeon_device *rdev,
504 return r; 358 return r;
505} 359}
506 360
507
508/*
509 * CP
510 */
511static int r100_cp_wait_for_idle(struct radeon_device *rdev) 361static int r100_cp_wait_for_idle(struct radeon_device *rdev)
512{ 362{
513 unsigned i; 363 unsigned i;
@@ -612,6 +462,7 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
612 } 462 }
613 return err; 463 return err;
614} 464}
465
615static void r100_cp_load_microcode(struct radeon_device *rdev) 466static void r100_cp_load_microcode(struct radeon_device *rdev)
616{ 467{
617 const __be32 *fw_data; 468 const __be32 *fw_data;
@@ -1976,7 +1827,7 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1976 r100_pll_errata_after_data(rdev); 1827 r100_pll_errata_after_data(rdev);
1977} 1828}
1978 1829
1979int r100_init(struct radeon_device *rdev) 1830void r100_set_safe_registers(struct radeon_device *rdev)
1980{ 1831{
1981 if (ASIC_IS_RN50(rdev)) { 1832 if (ASIC_IS_RN50(rdev)) {
1982 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 1833 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
@@ -1985,9 +1836,8 @@ int r100_init(struct radeon_device *rdev)
1985 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 1836 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
1986 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 1837 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
1987 } else { 1838 } else {
1988 return r200_init(rdev); 1839 r200_set_safe_registers(rdev);
1989 } 1840 }
1990 return 0;
1991} 1841}
1992 1842
1993/* 1843/*
@@ -3152,8 +3002,255 @@ void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3152 3002
3153void r100_vga_render_disable(struct radeon_device *rdev) 3003void r100_vga_render_disable(struct radeon_device *rdev)
3154{ 3004{
3155 u32 tmp; 3005 u32 tmp;
3156 3006
3157 tmp = RREG8(R_0003C2_GENMO_WT); 3007 tmp = RREG8(R_0003C2_GENMO_WT);
3158 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3008 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3159} 3009}
3010
3011static void r100_debugfs(struct radeon_device *rdev)
3012{
3013 int r;
3014
3015 r = r100_debugfs_mc_info_init(rdev);
3016 if (r)
3017 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3018}
3019
3020static void r100_mc_program(struct radeon_device *rdev)
3021{
3022 struct r100_mc_save save;
3023
3024 /* Stops all mc clients */
3025 r100_mc_stop(rdev, &save);
3026 if (rdev->flags & RADEON_IS_AGP) {
3027 WREG32(R_00014C_MC_AGP_LOCATION,
3028 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3029 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3030 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3031 if (rdev->family > CHIP_RV200)
3032 WREG32(R_00015C_AGP_BASE_2,
3033 upper_32_bits(rdev->mc.agp_base) & 0xff);
3034 } else {
3035 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3036 WREG32(R_000170_AGP_BASE, 0);
3037 if (rdev->family > CHIP_RV200)
3038 WREG32(R_00015C_AGP_BASE_2, 0);
3039 }
3040 /* Wait for mc idle */
3041 if (r100_mc_wait_for_idle(rdev))
3042 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3043 /* Program MC, should be a 32bits limited address space */
3044 WREG32(R_000148_MC_FB_LOCATION,
3045 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3046 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3047 r100_mc_resume(rdev, &save);
3048}
3049
3050void r100_clock_startup(struct radeon_device *rdev)
3051{
3052 u32 tmp;
3053
3054 if (radeon_dynclks != -1 && radeon_dynclks)
3055 radeon_legacy_set_clock_gating(rdev, 1);
3056 /* We need to force on some of the block */
3057 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3058 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3059 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3060 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3061 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3062}
3063
3064static int r100_startup(struct radeon_device *rdev)
3065{
3066 int r;
3067
3068 r100_mc_program(rdev);
3069 /* Resume clock */
3070 r100_clock_startup(rdev);
3071 /* Initialize GPU configuration (# pipes, ...) */
3072 r100_gpu_init(rdev);
3073 /* Initialize GART (initialize after TTM so we can allocate
3074 * memory through TTM but finalize after TTM) */
3075 if (rdev->flags & RADEON_IS_PCI) {
3076 r = r100_pci_gart_enable(rdev);
3077 if (r)
3078 return r;
3079 }
3080 /* Enable IRQ */
3081 rdev->irq.sw_int = true;
3082 r100_irq_set(rdev);
3083 /* 1M ring buffer */
3084 r = r100_cp_init(rdev, 1024 * 1024);
3085 if (r) {
3086 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3087 return r;
3088 }
3089 r = r100_wb_init(rdev);
3090 if (r)
3091 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3092 r = r100_ib_init(rdev);
3093 if (r) {
3094 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3095 return r;
3096 }
3097 return 0;
3098}
3099
3100int r100_resume(struct radeon_device *rdev)
3101{
3102 /* Make sur GART are not working */
3103 if (rdev->flags & RADEON_IS_PCI)
3104 r100_pci_gart_disable(rdev);
3105 /* Resume clock before doing reset */
3106 r100_clock_startup(rdev);
3107 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3108 if (radeon_gpu_reset(rdev)) {
3109 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3110 RREG32(R_000E40_RBBM_STATUS),
3111 RREG32(R_0007C0_CP_STAT));
3112 }
3113 /* post */
3114 radeon_combios_asic_init(rdev->ddev);
3115 /* Resume clock after posting */
3116 r100_clock_startup(rdev);
3117 return r100_startup(rdev);
3118}
3119
3120int r100_suspend(struct radeon_device *rdev)
3121{
3122 r100_cp_disable(rdev);
3123 r100_wb_disable(rdev);
3124 r100_irq_disable(rdev);
3125 if (rdev->flags & RADEON_IS_PCI)
3126 r100_pci_gart_disable(rdev);
3127 return 0;
3128}
3129
3130void r100_fini(struct radeon_device *rdev)
3131{
3132 r100_suspend(rdev);
3133 r100_cp_fini(rdev);
3134 r100_wb_fini(rdev);
3135 r100_ib_fini(rdev);
3136 radeon_gem_fini(rdev);
3137 if (rdev->flags & RADEON_IS_PCI)
3138 r100_pci_gart_fini(rdev);
3139 radeon_irq_kms_fini(rdev);
3140 radeon_fence_driver_fini(rdev);
3141 radeon_object_fini(rdev);
3142 radeon_atombios_fini(rdev);
3143 kfree(rdev->bios);
3144 rdev->bios = NULL;
3145}
3146
3147int r100_mc_init(struct radeon_device *rdev)
3148{
3149 int r;
3150 u32 tmp;
3151
3152 /* Setup GPU memory space */
3153 rdev->mc.vram_location = 0xFFFFFFFFUL;
3154 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3155 if (rdev->flags & RADEON_IS_IGP) {
3156 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3157 rdev->mc.vram_location = tmp << 16;
3158 }
3159 if (rdev->flags & RADEON_IS_AGP) {
3160 r = radeon_agp_init(rdev);
3161 if (r) {
3162 printk(KERN_WARNING "[drm] Disabling AGP\n");
3163 rdev->flags &= ~RADEON_IS_AGP;
3164 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3165 } else {
3166 rdev->mc.gtt_location = rdev->mc.agp_base;
3167 }
3168 }
3169 r = radeon_mc_setup(rdev);
3170 if (r)
3171 return r;
3172 return 0;
3173}
3174
3175int r100_init(struct radeon_device *rdev)
3176{
3177 int r;
3178
3179 rdev->new_init_path = true;
3180 /* Register debugfs file specific to this group of asics */
3181 r100_debugfs(rdev);
3182 /* Disable VGA */
3183 r100_vga_render_disable(rdev);
3184 /* Initialize scratch registers */
3185 radeon_scratch_init(rdev);
3186 /* Initialize surface registers */
3187 radeon_surface_init(rdev);
3188 /* TODO: disable VGA need to use VGA request */
3189 /* BIOS*/
3190 if (!radeon_get_bios(rdev)) {
3191 if (ASIC_IS_AVIVO(rdev))
3192 return -EINVAL;
3193 }
3194 if (rdev->is_atom_bios) {
3195 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3196 return -EINVAL;
3197 } else {
3198 r = radeon_combios_init(rdev);
3199 if (r)
3200 return r;
3201 }
3202 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3203 if (radeon_gpu_reset(rdev)) {
3204 dev_warn(rdev->dev,
3205 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3206 RREG32(R_000E40_RBBM_STATUS),
3207 RREG32(R_0007C0_CP_STAT));
3208 }
3209 /* check if cards are posted or not */
3210 if (!radeon_card_posted(rdev) && rdev->bios) {
3211 DRM_INFO("GPU not posted. posting now...\n");
3212 radeon_combios_asic_init(rdev->ddev);
3213 }
3214 /* Set asic errata */
3215 r100_errata(rdev);
3216 /* Initialize clocks */
3217 radeon_get_clock_info(rdev->ddev);
3218 /* Get vram informations */
3219 r100_vram_info(rdev);
3220 /* Initialize memory controller (also test AGP) */
3221 r = r100_mc_init(rdev);
3222 if (r)
3223 return r;
3224 /* Fence driver */
3225 r = radeon_fence_driver_init(rdev);
3226 if (r)
3227 return r;
3228 r = radeon_irq_kms_init(rdev);
3229 if (r)
3230 return r;
3231 /* Memory manager */
3232 r = radeon_object_init(rdev);
3233 if (r)
3234 return r;
3235 if (rdev->flags & RADEON_IS_PCI) {
3236 r = r100_pci_gart_init(rdev);
3237 if (r)
3238 return r;
3239 }
3240 r100_set_safe_registers(rdev);
3241 rdev->accel_working = true;
3242 r = r100_startup(rdev);
3243 if (r) {
3244 /* Somethings want wront with the accel init stop accel */
3245 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3246 r100_suspend(rdev);
3247 r100_cp_fini(rdev);
3248 r100_wb_fini(rdev);
3249 r100_ib_fini(rdev);
3250 if (rdev->flags & RADEON_IS_PCI)
3251 r100_pci_gart_fini(rdev);
3252 radeon_irq_kms_fini(rdev);
3253 rdev->accel_working = false;
3254 }
3255 return 0;
3256}
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
index 1595a5d132df..df29a630c466 100644
--- a/drivers/gpu/drm/radeon/r100d.h
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -381,6 +381,24 @@
381#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) 381#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24)
382#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) 382#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F)
383#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF 383#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF
384#define R_000148_MC_FB_LOCATION 0x000148
385#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
386#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
387#define C_000148_MC_FB_START 0xFFFF0000
388#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
389#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
390#define C_000148_MC_FB_TOP 0x0000FFFF
391#define R_00014C_MC_AGP_LOCATION 0x00014C
392#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
393#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
394#define C_00014C_MC_AGP_START 0xFFFF0000
395#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
396#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
397#define C_00014C_MC_AGP_TOP 0x0000FFFF
398#define R_000170_AGP_BASE 0x000170
399#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
400#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
401#define C_000170_AGP_BASE_ADDR 0x00000000
384#define R_00023C_DISPLAY_BASE_ADDR 0x00023C 402#define R_00023C_DISPLAY_BASE_ADDR 0x00023C
385#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 403#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
386#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 404#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
@@ -545,6 +563,46 @@
545#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) 563#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5)
546#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) 564#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF)
547#define C_000774_SCRATCH_ADDR 0x0000001F 565#define C_000774_SCRATCH_ADDR 0x0000001F
566#define R_0007C0_CP_STAT 0x0007C0
567#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
568#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
569#define C_0007C0_MRU_BUSY 0xFFFFFFFE
570#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
571#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
572#define C_0007C0_MWU_BUSY 0xFFFFFFFD
573#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
574#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
575#define C_0007C0_RSIU_BUSY 0xFFFFFFFB
576#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
577#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
578#define C_0007C0_RCIU_BUSY 0xFFFFFFF7
579#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
580#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
581#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
582#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
583#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
584#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
585#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
586#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
587#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
588#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
589#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
590#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
591#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
592#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
593#define C_0007C0_CSI_BUSY 0xFFFFDFFF
594#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
595#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
596#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
597#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
598#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
599#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
600#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
601#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
602#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
603#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
604#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
605#define C_0007C0_CP_BUSY 0x7FFFFFFF
548#define R_000E40_RBBM_STATUS 0x000E40 606#define R_000E40_RBBM_STATUS 0x000E40
549#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 607#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
550#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 608#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
@@ -604,4 +662,53 @@
604#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 662#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
605#define C_000E40_GUI_ACTIVE 0x7FFFFFFF 663#define C_000E40_GUI_ACTIVE 0x7FFFFFFF
606 664
665
666#define R_00000D_SCLK_CNTL 0x00000D
667#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
668#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
669#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
670#define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8)
671#define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7)
672#define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF
673#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)
674#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)
675#define C_00000D_FORCE_CP 0xFFFEFFFF
676#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)
677#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)
678#define C_00000D_FORCE_HDP 0xFFFDFFFF
679#define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18)
680#define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1)
681#define C_00000D_FORCE_DISP 0xFFFBFFFF
682#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)
683#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)
684#define C_00000D_FORCE_TOP 0xFFF7FFFF
685#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
686#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
687#define C_00000D_FORCE_E2 0xFFEFFFFF
688#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)
689#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)
690#define C_00000D_FORCE_SE 0xFFDFFFFF
691#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
692#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
693#define C_00000D_FORCE_IDCT 0xFFBFFFFF
694#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)
695#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)
696#define C_00000D_FORCE_VIP 0xFF7FFFFF
697#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
698#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
699#define C_00000D_FORCE_RE 0xFEFFFFFF
700#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)
701#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)
702#define C_00000D_FORCE_PB 0xFDFFFFFF
703#define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26)
704#define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1)
705#define C_00000D_FORCE_TAM 0xFBFFFFFF
706#define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27)
707#define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1)
708#define C_00000D_FORCE_TDM 0xF7FFFFFF
709#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)
710#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)
711#define C_00000D_FORCE_RB 0xEFFFFFFF
712
713
607#endif 714#endif
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index cf7fea5ff2e5..eb740fc3549f 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -447,9 +447,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
447 return 0; 447 return 0;
448} 448}
449 449
450int r200_init(struct radeon_device *rdev) 450void r200_set_safe_registers(struct radeon_device *rdev)
451{ 451{
452 rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; 452 rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
453 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); 453 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
454 return 0;
455} 454}
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index f31483d1749b..dde1b521aae5 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1042,6 +1042,9 @@ extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1042 struct radeon_cs_packet *pkt, 1042 struct radeon_cs_packet *pkt,
1043 unsigned idx); 1043 unsigned idx);
1044 1044
1045/* rv200,rv250,rv280 */
1046extern void r200_set_safe_registers(struct radeon_device *rdev);
1047
1045/* r300,r350,rv350,rv370,rv380 */ 1048/* r300,r350,rv350,rv370,rv380 */
1046extern void r300_set_reg_safe(struct radeon_device *rdev); 1049extern void r300_set_reg_safe(struct radeon_device *rdev);
1047extern void r300_mc_program(struct radeon_device *rdev); 1050extern void r300_mc_program(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 72562cf372b7..39f1bb656e61 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -41,27 +41,16 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
41/* 41/*
42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 42 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
43 */ 43 */
44int r100_init(struct radeon_device *rdev); 44extern int r100_init(struct radeon_device *rdev);
45int r200_init(struct radeon_device *rdev); 45extern void r100_fini(struct radeon_device *rdev);
46extern int r100_suspend(struct radeon_device *rdev);
47extern int r100_resume(struct radeon_device *rdev);
46uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); 48uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
47void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 49void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
48void r100_errata(struct radeon_device *rdev);
49void r100_vram_info(struct radeon_device *rdev);
50int r100_gpu_reset(struct radeon_device *rdev); 50int r100_gpu_reset(struct radeon_device *rdev);
51int r100_mc_init(struct radeon_device *rdev);
52void r100_mc_fini(struct radeon_device *rdev);
53u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 51u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
54int r100_wb_init(struct radeon_device *rdev);
55void r100_wb_fini(struct radeon_device *rdev);
56int r100_pci_gart_init(struct radeon_device *rdev);
57void r100_pci_gart_fini(struct radeon_device *rdev);
58int r100_pci_gart_enable(struct radeon_device *rdev);
59void r100_pci_gart_disable(struct radeon_device *rdev);
60void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 52void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
61int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 53int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
62int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
63void r100_cp_fini(struct radeon_device *rdev);
64void r100_cp_disable(struct radeon_device *rdev);
65void r100_cp_commit(struct radeon_device *rdev); 54void r100_cp_commit(struct radeon_device *rdev);
66void r100_ring_start(struct radeon_device *rdev); 55void r100_ring_start(struct radeon_device *rdev);
67int r100_irq_set(struct radeon_device *rdev); 56int r100_irq_set(struct radeon_device *rdev);
@@ -87,27 +76,30 @@ int r100_ring_test(struct radeon_device *rdev);
87 76
88static struct radeon_asic r100_asic = { 77static struct radeon_asic r100_asic = {
89 .init = &r100_init, 78 .init = &r100_init,
90 .errata = &r100_errata, 79 .fini = &r100_fini,
91 .vram_info = &r100_vram_info, 80 .suspend = &r100_suspend,
81 .resume = &r100_resume,
82 .errata = NULL,
83 .vram_info = NULL,
92 .gpu_reset = &r100_gpu_reset, 84 .gpu_reset = &r100_gpu_reset,
93 .mc_init = &r100_mc_init, 85 .mc_init = NULL,
94 .mc_fini = &r100_mc_fini, 86 .mc_fini = NULL,
95 .wb_init = &r100_wb_init, 87 .wb_init = NULL,
96 .wb_fini = &r100_wb_fini, 88 .wb_fini = NULL,
97 .gart_init = &r100_pci_gart_init, 89 .gart_init = NULL,
98 .gart_fini = &r100_pci_gart_fini, 90 .gart_fini = NULL,
99 .gart_enable = &r100_pci_gart_enable, 91 .gart_enable = NULL,
100 .gart_disable = &r100_pci_gart_disable, 92 .gart_disable = NULL,
101 .gart_tlb_flush = &r100_pci_gart_tlb_flush, 93 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
102 .gart_set_page = &r100_pci_gart_set_page, 94 .gart_set_page = &r100_pci_gart_set_page,
103 .cp_init = &r100_cp_init, 95 .cp_init = NULL,
104 .cp_fini = &r100_cp_fini, 96 .cp_fini = NULL,
105 .cp_disable = &r100_cp_disable, 97 .cp_disable = NULL,
106 .cp_commit = &r100_cp_commit, 98 .cp_commit = &r100_cp_commit,
107 .ring_start = &r100_ring_start, 99 .ring_start = &r100_ring_start,
108 .ring_test = &r100_ring_test, 100 .ring_test = &r100_ring_test,
109 .ring_ib_execute = &r100_ring_ib_execute, 101 .ring_ib_execute = &r100_ring_ib_execute,
110 .ib_test = &r100_ib_test, 102 .ib_test = NULL,
111 .irq_set = &r100_irq_set, 103 .irq_set = &r100_irq_set,
112 .irq_process = &r100_irq_process, 104 .irq_process = &r100_irq_process,
113 .get_vblank_counter = &r100_get_vblank_counter, 105 .get_vblank_counter = &r100_get_vblank_counter,
diff --git a/drivers/gpu/drm/radeon/rs100d.h b/drivers/gpu/drm/radeon/rs100d.h
new file mode 100644
index 000000000000..48a913a06cfd
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs100d.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RS100D_H__
29#define __RS100D_H__
30
31/* Registers */
32#define R_00015C_NB_TOM 0x00015C
33#define S_00015C_MC_FB_START(x) (((x) & 0xFFFF) << 0)
34#define G_00015C_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
35#define C_00015C_MC_FB_START 0xFFFF0000
36#define S_00015C_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
37#define G_00015C_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
38#define C_00015C_MC_FB_TOP 0x0000FFFF
39
40#endif
diff --git a/drivers/gpu/drm/radeon/rv200d.h b/drivers/gpu/drm/radeon/rv200d.h
new file mode 100644
index 000000000000..c5b398330c26
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv200d.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RV200D_H__
29#define __RV200D_H__
30
31#define R_00015C_AGP_BASE_2 0x00015C
32#define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
33#define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
34#define C_00015C_AGP_BASE_ADDR_2 0xFFFFFFF0
35
36#endif
diff --git a/drivers/gpu/drm/radeon/rv250d.h b/drivers/gpu/drm/radeon/rv250d.h
new file mode 100644
index 000000000000..e5a70b06fe1f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv250d.h
@@ -0,0 +1,123 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RV250D_H__
29#define __RV250D_H__
30
31#define R_00000D_SCLK_CNTL_M6 0x00000D
32#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)
33#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)
34#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8
35#define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3)
36#define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1)
37#define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7
38#define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4)
39#define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1)
40#define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF
41#define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5)
42#define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1)
43#define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF
44#define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6)
45#define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1)
46#define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF
47#define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7)
48#define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1)
49#define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F
50#define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8)
51#define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1)
52#define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF
53#define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9)
54#define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1)
55#define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF
56#define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10)
57#define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1)
58#define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF
59#define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11)
60#define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1)
61#define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF
62#define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12)
63#define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1)
64#define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF
65#define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13)
66#define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1)
67#define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF
68#define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14)
69#define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1)
70#define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF
71#define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15)
72#define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1)
73#define C_00000D_FORCE_DISP2 0xFFFF7FFF
74#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)
75#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)
76#define C_00000D_FORCE_CP 0xFFFEFFFF
77#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)
78#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)
79#define C_00000D_FORCE_HDP 0xFFFDFFFF
80#define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18)
81#define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1)
82#define C_00000D_FORCE_DISP1 0xFFFBFFFF
83#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)
84#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)
85#define C_00000D_FORCE_TOP 0xFFF7FFFF
86#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)
87#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)
88#define C_00000D_FORCE_E2 0xFFEFFFFF
89#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)
90#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)
91#define C_00000D_FORCE_SE 0xFFDFFFFF
92#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)
93#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)
94#define C_00000D_FORCE_IDCT 0xFFBFFFFF
95#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)
96#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)
97#define C_00000D_FORCE_VIP 0xFF7FFFFF
98#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)
99#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)
100#define C_00000D_FORCE_RE 0xFEFFFFFF
101#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)
102#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)
103#define C_00000D_FORCE_PB 0xFDFFFFFF
104#define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26)
105#define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1)
106#define C_00000D_FORCE_TAM 0xFBFFFFFF
107#define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27)
108#define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1)
109#define C_00000D_FORCE_TDM 0xF7FFFFFF
110#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)
111#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)
112#define C_00000D_FORCE_RB 0xEFFFFFFF
113#define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29)
114#define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1)
115#define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF
116#define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30)
117#define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1)
118#define C_00000D_FORCE_SUBPIC 0xBFFFFFFF
119#define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31)
120#define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1)
121#define C_00000D_FORCE_OV0 0x7FFFFFFF
122
123#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 16:53:22 -0500