aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt220
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c529
-rw-r--r--include/dt-bindings/clock/imx6qdl-clock.h224
3 files changed, 476 insertions, 497 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 90ec91fe5ce0..9252912a5b0e 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -7,223 +7,13 @@ Required properties:
7- #clock-cells: Should be <1> 7- #clock-cells: Should be <1>
8 8
9The clock consumer should specify the desired clock by having the clock 9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX6Q 10ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
11clocks and IDs. 11for the full list of i.MX6 Quad and DualLite clock IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 ckil 1
17 ckih 2
18 osc 3
19 pll2_pfd0_352m 4
20 pll2_pfd1_594m 5
21 pll2_pfd2_396m 6
22 pll3_pfd0_720m 7
23 pll3_pfd1_540m 8
24 pll3_pfd2_508m 9
25 pll3_pfd3_454m 10
26 pll2_198m 11
27 pll3_120m 12
28 pll3_80m 13
29 pll3_60m 14
30 twd 15
31 step 16
32 pll1_sw 17
33 periph_pre 18
34 periph2_pre 19
35 periph_clk2_sel 20
36 periph2_clk2_sel 21
37 axi_sel 22
38 esai_sel 23
39 asrc_sel 24
40 spdif_sel 25
41 gpu2d_axi 26
42 gpu3d_axi 27
43 gpu2d_core_sel 28
44 gpu3d_core_sel 29
45 gpu3d_shader_sel 30
46 ipu1_sel 31
47 ipu2_sel 32
48 ldb_di0_sel 33
49 ldb_di1_sel 34
50 ipu1_di0_pre_sel 35
51 ipu1_di1_pre_sel 36
52 ipu2_di0_pre_sel 37
53 ipu2_di1_pre_sel 38
54 ipu1_di0_sel 39
55 ipu1_di1_sel 40
56 ipu2_di0_sel 41
57 ipu2_di1_sel 42
58 hsi_tx_sel 43
59 pcie_axi_sel 44
60 ssi1_sel 45
61 ssi2_sel 46
62 ssi3_sel 47
63 usdhc1_sel 48
64 usdhc2_sel 49
65 usdhc3_sel 50
66 usdhc4_sel 51
67 enfc_sel 52
68 emi_sel 53
69 emi_slow_sel 54
70 vdo_axi_sel 55
71 vpu_axi_sel 56
72 cko1_sel 57
73 periph 58
74 periph2 59
75 periph_clk2 60
76 periph2_clk2 61
77 ipg 62
78 ipg_per 63
79 esai_pred 64
80 esai_podf 65
81 asrc_pred 66
82 asrc_podf 67
83 spdif_pred 68
84 spdif_podf 69
85 can_root 70
86 ecspi_root 71
87 gpu2d_core_podf 72
88 gpu3d_core_podf 73
89 gpu3d_shader 74
90 ipu1_podf 75
91 ipu2_podf 76
92 ldb_di0_podf 77
93 ldb_di1_podf 78
94 ipu1_di0_pre 79
95 ipu1_di1_pre 80
96 ipu2_di0_pre 81
97 ipu2_di1_pre 82
98 hsi_tx_podf 83
99 ssi1_pred 84
100 ssi1_podf 85
101 ssi2_pred 86
102 ssi2_podf 87
103 ssi3_pred 88
104 ssi3_podf 89
105 uart_serial_podf 90
106 usdhc1_podf 91
107 usdhc2_podf 92
108 usdhc3_podf 93
109 usdhc4_podf 94
110 enfc_pred 95
111 enfc_podf 96
112 emi_podf 97
113 emi_slow_podf 98
114 vpu_axi_podf 99
115 cko1_podf 100
116 axi 101
117 mmdc_ch0_axi_podf 102
118 mmdc_ch1_axi_podf 103
119 arm 104
120 ahb 105
121 apbh_dma 106
122 asrc 107
123 can1_ipg 108
124 can1_serial 109
125 can2_ipg 110
126 can2_serial 111
127 ecspi1 112
128 ecspi2 113
129 ecspi3 114
130 ecspi4 115
131 ecspi5 116
132 enet 117
133 esai 118
134 gpt_ipg 119
135 gpt_ipg_per 120
136 gpu2d_core 121
137 gpu3d_core 122
138 hdmi_iahb 123
139 hdmi_isfr 124
140 i2c1 125
141 i2c2 126
142 i2c3 127
143 iim 128
144 enfc 129
145 ipu1 130
146 ipu1_di0 131
147 ipu1_di1 132
148 ipu2 133
149 ipu2_di0 134
150 ldb_di0 135
151 ldb_di1 136
152 ipu2_di1 137
153 hsi_tx 138
154 mlb 139
155 mmdc_ch0_axi 140
156 mmdc_ch1_axi 141
157 ocram 142
158 openvg_axi 143
159 pcie_axi 144
160 pwm1 145
161 pwm2 146
162 pwm3 147
163 pwm4 148
164 per1_bch 149
165 gpmi_bch_apb 150
166 gpmi_bch 151
167 gpmi_io 152
168 gpmi_apb 153
169 sata 154
170 sdma 155
171 spba 156
172 ssi1 157
173 ssi2 158
174 ssi3 159
175 uart_ipg 160
176 uart_serial 161
177 usboh3 162
178 usdhc1 163
179 usdhc2 164
180 usdhc3 165
181 usdhc4 166
182 vdo_axi 167
183 vpu_axi 168
184 cko1 169
185 pll1_sys 170
186 pll2_bus 171
187 pll3_usb_otg 172
188 pll4_audio 173
189 pll5_video 174
190 pll8_mlb 175
191 pll7_usb_host 176
192 pll6_enet 177
193 ssi1_ipg 178
194 ssi2_ipg 179
195 ssi3_ipg 180
196 rom 181
197 usbphy1 182
198 usbphy2 183
199 ldb_di0_div_3_5 184
200 ldb_di1_div_3_5 185
201 sata_ref 186
202 sata_ref_100m 187
203 pcie_ref 188
204 pcie_ref_125m 189
205 enet_ref 190
206 usbphy1_gate 191
207 usbphy2_gate 192
208 pll4_post_div 193
209 pll5_post_div 194
210 pll5_video_div 195
211 eim_slow 196
212 spdif 197
213 cko2_sel 198
214 cko2_podf 199
215 cko2 200
216 cko 201
217 vdoa 202
218 pll4_audio_div 203
219 lvds1_sel 204
220 lvds2_sel 205
221 lvds1_gate 206
222 lvds2_gate 207
223 esai_ahb 208
224 12
225Examples: 13Examples:
226 14
15#include <dt-bindings/clock/imx6qdl-clock.h>
16
227clks: ccm@020c4000 { 17clks: ccm@020c4000 {
228 compatible = "fsl,imx6q-ccm"; 18 compatible = "fsl,imx6q-ccm";
229 reg = <0x020c4000 0x4000>; 19 reg = <0x020c4000 0x4000>;
@@ -235,7 +25,7 @@ uart1: serial@02020000 {
235 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 25 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
236 reg = <0x02020000 0x4000>; 26 reg = <0x02020000 0x4000>;
237 interrupts = <0 26 0x04>; 27 interrupts = <0 26 0x04>;
238 clocks = <&clks 160>, <&clks 161>; 28 clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
239 clock-names = "ipg", "per"; 29 clock-names = "ipg", "per";
240 status = "disabled"; 30 status = "disabled";
241}; 31};
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 56c897ef454b..8a827acdde70 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -19,6 +19,7 @@
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/of_address.h> 20#include <linux/of_address.h>
21#include <linux/of_irq.h> 21#include <linux/of_irq.h>
22#include <dt-bindings/clock/imx6qdl-clock.h>
22 23
23#include "clk.h" 24#include "clk.h"
24#include "common.h" 25#include "common.h"
@@ -73,48 +74,13 @@ static const char *lvds_sels[] = {
73 "pcie_ref_125m", "sata_ref_100m", 74 "pcie_ref_125m", "sata_ref_100m",
74}; 75};
75 76
76enum mx6q_clks { 77static struct clk *clk[IMX6QDL_CLK_END];
77 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
78 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
79 pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
80 periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
81 esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
82 gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
83 ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
84 ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
85 ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
86 usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
87 emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
88 periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
89 asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
90 gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
91 ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
92 ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
93 ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
94 usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
95 emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
96 mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
97 can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
98 esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
99 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
100 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
101 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
102 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
103 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
104 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
105 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
106 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
107 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
108 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
109 spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
110 lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
111};
112
113static struct clk *clk[clk_max];
114static struct clk_onecell_data clk_data; 78static struct clk_onecell_data clk_data;
115 79
116static enum mx6q_clks const clks_init_on[] __initconst = { 80static unsigned int const clks_init_on[] __initconst = {
117 mmdc_ch0_axi, rom, arm, 81 IMX6QDL_CLK_MMDC_CH0_AXI,
82 IMX6QDL_CLK_ROM,
83 IMX6QDL_CLK_ARM,
118}; 84};
119 85
120static struct clk_div_table clk_enet_ref_table[] = { 86static struct clk_div_table clk_enet_ref_table[] = {
@@ -149,10 +115,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
149 int i; 115 int i;
150 int ret; 116 int ret;
151 117
152 clk[dummy] = imx_clk_fixed("dummy", 0); 118 clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
153 clk[ckil] = imx_obtain_fixed_clock("ckil", 0); 119 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
154 clk[ckih] = imx_obtain_fixed_clock("ckih1", 0); 120 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
155 clk[osc] = imx_obtain_fixed_clock("osc", 0); 121 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
156 122
157 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 123 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
158 base = of_iomap(np, 0); 124 base = of_iomap(np, 0);
@@ -166,14 +132,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
166 video_div_table[2].div = 1; 132 video_div_table[2].div = 1;
167 }; 133 };
168 134
169 /* type name parent_name base div_mask */ 135 /* type name parent_name base div_mask */
170 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); 136 clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
171 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); 137 clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
172 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); 138 clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
173 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); 139 clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
174 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 140 clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
175 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 141 clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
176 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); 142 clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
177 143
178 /* 144 /*
179 * Bit 20 is the reserved and read-only bit, we do this only for: 145 * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -181,28 +147,28 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
181 * - Keep refcount when do usbphy clk_enable/disable, in that case, 147 * - Keep refcount when do usbphy clk_enable/disable, in that case,
182 * the clk framework may need to enable/disable usbphy's parent 148 * the clk framework may need to enable/disable usbphy's parent
183 */ 149 */
184 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); 150 clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
185 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); 151 clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
186 152
187 /* 153 /*
188 * usbphy*_gate needs to be on after system boots up, and software 154 * usbphy*_gate needs to be on after system boots up, and software
189 * never needs to control it anymore. 155 * never needs to control it anymore.
190 */ 156 */
191 clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); 157 clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
192 clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); 158 clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
193 159
194 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); 160 clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
195 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); 161 clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
196 162
197 clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); 163 clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
198 clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); 164 clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
199 165
200 clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 166 clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
201 base + 0xe0, 0, 2, 0, clk_enet_ref_table, 167 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
202 &imx_ccm_lock); 168 &imx_ccm_lock);
203 169
204 clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 170 clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
205 clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 171 clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
206 172
207 /* 173 /*
208 * lvds1_gate and lvds2_gate are pseudo-gates. Both can be 174 * lvds1_gate and lvds2_gate are pseudo-gates. Both can be
@@ -210,29 +176,29 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
210 * the "output_enable" bit as a gate, even though it's really just 176 * the "output_enable" bit as a gate, even though it's really just
211 * enabling clock output. 177 * enabling clock output.
212 */ 178 */
213 clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10); 179 clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
214 clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11); 180 clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
215 181
216 /* name parent_name reg idx */ 182 /* name parent_name reg idx */
217 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 183 clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
218 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); 184 clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
219 clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); 185 clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
220 clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); 186 clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
221 clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); 187 clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
222 clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); 188 clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
223 clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); 189 clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
224 190
225 /* name parent_name mult div */ 191 /* name parent_name mult div */
226 clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); 192 clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
227 clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); 193 clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
228 clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); 194 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
229 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 195 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
230 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); 196 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
231 197
232 clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 198 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
233 clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); 199 clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
234 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 200 clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
235 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 201 clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
236 202
237 np = ccm_node; 203 np = ccm_node;
238 base = of_iomap(np, 0); 204 base = of_iomap(np, 0);
@@ -240,198 +206,197 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
240 206
241 imx6q_pm_set_ccm_base(base); 207 imx6q_pm_set_ccm_base(base);
242 208
243 /* name reg shift width parent_names num_parents */ 209 /* name reg shift width parent_names num_parents */
244 clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); 210 clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
245 clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); 211 clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
246 clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 212 clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
247 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 213 clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
248 clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 214 clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
249 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); 215 clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
250 clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); 216 clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
251 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); 217 clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
252 clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); 218 clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
253 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); 219 clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
254 clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 220 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
255 clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 221 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
256 clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); 222 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
257 clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); 223 clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
258 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); 224 clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
259 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 225 clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
260 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 226 clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
261 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 227 clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
262 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 228 clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
263 clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 229 clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
264 clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 230 clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
265 clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 231 clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
266 clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 232 clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
267 clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); 233 clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
268 clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); 234 clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
269 clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); 235 clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
270 clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); 236 clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
271 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); 237 clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
272 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); 238 clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
273 clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 239 clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
274 clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 240 clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
275 clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 241 clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
276 clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 242 clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
277 clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 243 clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
278 clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 244 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
279 clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 245 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
280 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 246 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
281 clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); 247 clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
282 clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); 248 clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
283 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 249 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
284 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 250 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
285 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 251 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
286 clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); 252 clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
287 clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); 253 clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
288 254
289 /* name reg shift width busy: reg, shift parent_names num_parents */ 255 /* name reg shift width busy: reg, shift parent_names num_parents */
290 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); 256 clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
291 clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); 257 clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
292 258
293 /* name parent_name reg shift width */ 259 /* name parent_name reg shift width */
294 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); 260 clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
295 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); 261 clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
296 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); 262 clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
297 clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); 263 clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
298 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); 264 clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
299 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); 265 clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
300 clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); 266 clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
301 clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); 267 clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
302 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); 268 clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
303 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); 269 clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
304 clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); 270 clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
305 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); 271 clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
306 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); 272 clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
307 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); 273 clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
308 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); 274 clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
309 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); 275 clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
310 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); 276 clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
311 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); 277 clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
312 clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); 278 clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
313 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); 279 clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
314 clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); 280 clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
315 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); 281 clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
316 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); 282 clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
317 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); 283 clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
318 clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); 284 clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
319 clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); 285 clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
320 clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); 286 clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
321 clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); 287 clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
322 clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); 288 clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
323 clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); 289 clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
324 clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); 290 clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
325 clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); 291 clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
326 clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); 292 clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
327 clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); 293 clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
328 clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); 294 clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
329 clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); 295 clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
330 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 296 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
331 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 297 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
332 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 298 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
333 clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); 299 clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
334 clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); 300 clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
335 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 301 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
336 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 302 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
337 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); 303 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
338 304
339 /* name parent_name reg shift width busy: reg, shift */ 305 /* name parent_name reg shift width busy: reg, shift */
340 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); 306 clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
341 clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); 307 clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
342 clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); 308 clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
343 clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); 309 clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
344 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); 310 clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
345 311
346 /* name parent_name reg shift */ 312 /* name parent_name reg shift */
347 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); 313 clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
348 clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); 314 clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
349 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); 315 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
350 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); 316 clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
351 clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); 317 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
352 clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); 318 clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
353 clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); 319 clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
354 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); 320 clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
355 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); 321 clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
356 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); 322 clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
357 if (cpu_is_imx6dl()) 323 if (cpu_is_imx6dl())
358 /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */ 324 clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
359 clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
360 else 325 else
361 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); 326 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
362 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); 327 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
363 clk[esai] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai); 328 clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
364 clk[esai_ahb] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai); 329 clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
365 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 330 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
366 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 331 clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
367 if (cpu_is_imx6dl()) 332 if (cpu_is_imx6dl())
368 /* 333 /*
369 * The multiplexer and divider of imx6q clock gpu3d_shader get 334 * The multiplexer and divider of imx6q clock gpu3d_shader get
370 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. 335 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
371 */ 336 */
372 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); 337 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
373 else 338 else
374 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); 339 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
375 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); 340 clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
376 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); 341 clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
377 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); 342 clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
378 clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); 343 clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
379 clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); 344 clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
380 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); 345 clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
381 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); 346 clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
382 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); 347 clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
383 clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); 348 clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
384 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); 349 clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
385 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); 350 clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
386 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); 351 clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
387 clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); 352 clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
388 clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); 353 clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
389 clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); 354 clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
390 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); 355 clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
391 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); 356 clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
392 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); 357 clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
393 if (cpu_is_imx6dl()) 358 if (cpu_is_imx6dl())
394 /* 359 /*
395 * The multiplexer and divider of the imx6q clock gpu2d get 360 * The multiplexer and divider of the imx6q clock gpu2d get
396 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. 361 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
397 */ 362 */
398 clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); 363 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
399 else 364 else
400 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); 365 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
401 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); 366 clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
402 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); 367 clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
403 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); 368 clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
404 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); 369 clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
405 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); 370 clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
406 clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); 371 clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
407 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); 372 clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
408 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); 373 clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
409 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); 374 clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
410 clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); 375 clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
411 clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); 376 clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
412 clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); 377 clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
413 clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); 378 clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
414 clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); 379 clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
415 clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); 380 clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
416 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); 381 clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
417 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); 382 clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
418 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 383 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
419 clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); 384 clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
420 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); 385 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
421 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); 386 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
422 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); 387 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
423 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); 388 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
424 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); 389 clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
425 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 390 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
426 clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); 391 clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
427 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 392 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
428 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 393 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
429 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 394 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
430 clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); 395 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
431 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 396 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
432 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 397 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
433 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 398 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
434 clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); 399 clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
435 400
436 imx_check_clocks(clk, ARRAY_SIZE(clk)); 401 imx_check_clocks(clk, ARRAY_SIZE(clk));
437 402
@@ -439,54 +404,54 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
439 clk_data.clk_num = ARRAY_SIZE(clk); 404 clk_data.clk_num = ARRAY_SIZE(clk);
440 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 405 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
441 406
442 clk_register_clkdev(clk[enet_ref], "enet_ref", NULL); 407 clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
443 408
444 if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || 409 if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
445 cpu_is_imx6dl()) { 410 cpu_is_imx6dl()) {
446 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); 411 clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
447 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); 412 clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
448 } 413 }
449 414
450 clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); 415 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
451 clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); 416 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
452 clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); 417 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
453 clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); 418 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
454 clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); 419 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
455 clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); 420 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
456 clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); 421 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
457 clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); 422 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
458 423
459 /* 424 /*
460 * The gpmi needs 100MHz frequency in the EDO/Sync mode, 425 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
461 * We can not get the 100MHz from the pll2_pfd0_352m. 426 * We can not get the 100MHz from the pll2_pfd0_352m.
462 * So choose pll2_pfd2_396m as enfc_sel's parent. 427 * So choose pll2_pfd2_396m as enfc_sel's parent.
463 */ 428 */
464 clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); 429 clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
465 430
466 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 431 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
467 clk_prepare_enable(clk[clks_init_on[i]]); 432 clk_prepare_enable(clk[clks_init_on[i]]);
468 433
469 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { 434 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
470 clk_prepare_enable(clk[usbphy1_gate]); 435 clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
471 clk_prepare_enable(clk[usbphy2_gate]); 436 clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
472 } 437 }
473 438
474 /* 439 /*
475 * Let's initially set up CLKO with OSC24M, since this configuration 440 * Let's initially set up CLKO with OSC24M, since this configuration
476 * is widely used by imx6q board designs to clock audio codec. 441 * is widely used by imx6q board designs to clock audio codec.
477 */ 442 */
478 ret = clk_set_parent(clk[cko2_sel], clk[osc]); 443 ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
479 if (!ret) 444 if (!ret)
480 ret = clk_set_parent(clk[cko], clk[cko2]); 445 ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
481 if (ret) 446 if (ret)
482 pr_warn("failed to set up CLKO: %d\n", ret); 447 pr_warn("failed to set up CLKO: %d\n", ret);
483 448
484 /* Audio-related clocks configuration */ 449 /* Audio-related clocks configuration */
485 clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); 450 clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
486 451
487 /* All existing boards with PCIe use LVDS1 */ 452 /* All existing boards with PCIe use LVDS1 */
488 if (IS_ENABLED(CONFIG_PCI_IMX6)) 453 if (IS_ENABLED(CONFIG_PCI_IMX6))
489 clk_set_parent(clk[lvds1_sel], clk[sata_ref_100m]); 454 clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
490 455
491 /* Set initial power mode */ 456 /* Set initial power mode */
492 imx6q_set_lpm(WAIT_CLOCKED); 457 imx6q_set_lpm(WAIT_CLOCKED);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
new file mode 100644
index 000000000000..654151e24288
--- /dev/null
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -0,0 +1,224 @@
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
10#define __DT_BINDINGS_CLOCK_IMX6QDL_H
11
12#define IMX6QDL_CLK_DUMMY 0
13#define IMX6QDL_CLK_CKIL 1
14#define IMX6QDL_CLK_CKIH 2
15#define IMX6QDL_CLK_OSC 3
16#define IMX6QDL_CLK_PLL2_PFD0_352M 4
17#define IMX6QDL_CLK_PLL2_PFD1_594M 5
18#define IMX6QDL_CLK_PLL2_PFD2_396M 6
19#define IMX6QDL_CLK_PLL3_PFD0_720M 7
20#define IMX6QDL_CLK_PLL3_PFD1_540M 8
21#define IMX6QDL_CLK_PLL3_PFD2_508M 9
22#define IMX6QDL_CLK_PLL3_PFD3_454M 10
23#define IMX6QDL_CLK_PLL2_198M 11
24#define IMX6QDL_CLK_PLL3_120M 12
25#define IMX6QDL_CLK_PLL3_80M 13
26#define IMX6QDL_CLK_PLL3_60M 14
27#define IMX6QDL_CLK_TWD 15
28#define IMX6QDL_CLK_STEP 16
29#define IMX6QDL_CLK_PLL1_SW 17
30#define IMX6QDL_CLK_PERIPH_PRE 18
31#define IMX6QDL_CLK_PERIPH2_PRE 19
32#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
33#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
34#define IMX6QDL_CLK_AXI_SEL 22
35#define IMX6QDL_CLK_ESAI_SEL 23
36#define IMX6QDL_CLK_ASRC_SEL 24
37#define IMX6QDL_CLK_SPDIF_SEL 25
38#define IMX6QDL_CLK_GPU2D_AXI 26
39#define IMX6QDL_CLK_GPU3D_AXI 27
40#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
41#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
42#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
43#define IMX6QDL_CLK_IPU1_SEL 31
44#define IMX6QDL_CLK_IPU2_SEL 32
45#define IMX6QDL_CLK_LDB_DI0_SEL 33
46#define IMX6QDL_CLK_LDB_DI1_SEL 34
47#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
48#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
49#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
50#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
51#define IMX6QDL_CLK_IPU1_DI0_SEL 39
52#define IMX6QDL_CLK_IPU1_DI1_SEL 40
53#define IMX6QDL_CLK_IPU2_DI0_SEL 41
54#define IMX6QDL_CLK_IPU2_DI1_SEL 42
55#define IMX6QDL_CLK_HSI_TX_SEL 43
56#define IMX6QDL_CLK_PCIE_AXI_SEL 44
57#define IMX6QDL_CLK_SSI1_SEL 45
58#define IMX6QDL_CLK_SSI2_SEL 46
59#define IMX6QDL_CLK_SSI3_SEL 47
60#define IMX6QDL_CLK_USDHC1_SEL 48
61#define IMX6QDL_CLK_USDHC2_SEL 49
62#define IMX6QDL_CLK_USDHC3_SEL 50
63#define IMX6QDL_CLK_USDHC4_SEL 51
64#define IMX6QDL_CLK_ENFC_SEL 52
65#define IMX6QDL_CLK_EMI_SEL 53
66#define IMX6QDL_CLK_EMI_SLOW_SEL 54
67#define IMX6QDL_CLK_VDO_AXI_SEL 55
68#define IMX6QDL_CLK_VPU_AXI_SEL 56
69#define IMX6QDL_CLK_CKO1_SEL 57
70#define IMX6QDL_CLK_PERIPH 58
71#define IMX6QDL_CLK_PERIPH2 59
72#define IMX6QDL_CLK_PERIPH_CLK2 60
73#define IMX6QDL_CLK_PERIPH2_CLK2 61
74#define IMX6QDL_CLK_IPG 62
75#define IMX6QDL_CLK_IPG_PER 63
76#define IMX6QDL_CLK_ESAI_PRED 64
77#define IMX6QDL_CLK_ESAI_PODF 65
78#define IMX6QDL_CLK_ASRC_PRED 66
79#define IMX6QDL_CLK_ASRC_PODF 67
80#define IMX6QDL_CLK_SPDIF_PRED 68
81#define IMX6QDL_CLK_SPDIF_PODF 69
82#define IMX6QDL_CLK_CAN_ROOT 70
83#define IMX6QDL_CLK_ECSPI_ROOT 71
84#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
85#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
86#define IMX6QDL_CLK_GPU3D_SHADER 74
87#define IMX6QDL_CLK_IPU1_PODF 75
88#define IMX6QDL_CLK_IPU2_PODF 76
89#define IMX6QDL_CLK_LDB_DI0_PODF 77
90#define IMX6QDL_CLK_LDB_DI1_PODF 78
91#define IMX6QDL_CLK_IPU1_DI0_PRE 79
92#define IMX6QDL_CLK_IPU1_DI1_PRE 80
93#define IMX6QDL_CLK_IPU2_DI0_PRE 81
94#define IMX6QDL_CLK_IPU2_DI1_PRE 82
95#define IMX6QDL_CLK_HSI_TX_PODF 83
96#define IMX6QDL_CLK_SSI1_PRED 84
97#define IMX6QDL_CLK_SSI1_PODF 85
98#define IMX6QDL_CLK_SSI2_PRED 86
99#define IMX6QDL_CLK_SSI2_PODF 87
100#define IMX6QDL_CLK_SSI3_PRED 88
101#define IMX6QDL_CLK_SSI3_PODF 89
102#define IMX6QDL_CLK_UART_SERIAL_PODF 90
103#define IMX6QDL_CLK_USDHC1_PODF 91
104#define IMX6QDL_CLK_USDHC2_PODF 92
105#define IMX6QDL_CLK_USDHC3_PODF 93
106#define IMX6QDL_CLK_USDHC4_PODF 94
107#define IMX6QDL_CLK_ENFC_PRED 95
108#define IMX6QDL_CLK_ENFC_PODF 96
109#define IMX6QDL_CLK_EMI_PODF 97
110#define IMX6QDL_CLK_EMI_SLOW_PODF 98
111#define IMX6QDL_CLK_VPU_AXI_PODF 99
112#define IMX6QDL_CLK_CKO1_PODF 100
113#define IMX6QDL_CLK_AXI 101
114#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
115#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
116#define IMX6QDL_CLK_ARM 104
117#define IMX6QDL_CLK_AHB 105
118#define IMX6QDL_CLK_APBH_DMA 106
119#define IMX6QDL_CLK_ASRC 107
120#define IMX6QDL_CLK_CAN1_IPG 108
121#define IMX6QDL_CLK_CAN1_SERIAL 109
122#define IMX6QDL_CLK_CAN2_IPG 110
123#define IMX6QDL_CLK_CAN2_SERIAL 111
124#define IMX6QDL_CLK_ECSPI1 112
125#define IMX6QDL_CLK_ECSPI2 113
126#define IMX6QDL_CLK_ECSPI3 114
127#define IMX6QDL_CLK_ECSPI4 115
128#define IMX6Q_CLK_ECSPI5 116
129#define IMX6DL_CLK_I2C4 116
130#define IMX6QDL_CLK_ENET 117
131#define IMX6QDL_CLK_ESAI 118
132#define IMX6QDL_CLK_GPT_IPG 119
133#define IMX6QDL_CLK_GPT_IPG_PER 120
134#define IMX6QDL_CLK_GPU2D_CORE 121
135#define IMX6QDL_CLK_GPU3D_CORE 122
136#define IMX6QDL_CLK_HDMI_IAHB 123
137#define IMX6QDL_CLK_HDMI_ISFR 124
138#define IMX6QDL_CLK_I2C1 125
139#define IMX6QDL_CLK_I2C2 126
140#define IMX6QDL_CLK_I2C3 127
141#define IMX6QDL_CLK_IIM 128
142#define IMX6QDL_CLK_ENFC 129
143#define IMX6QDL_CLK_IPU1 130
144#define IMX6QDL_CLK_IPU1_DI0 131
145#define IMX6QDL_CLK_IPU1_DI1 132
146#define IMX6QDL_CLK_IPU2 133
147#define IMX6QDL_CLK_IPU2_DI0 134
148#define IMX6QDL_CLK_LDB_DI0 135
149#define IMX6QDL_CLK_LDB_DI1 136
150#define IMX6QDL_CLK_IPU2_DI1 137
151#define IMX6QDL_CLK_HSI_TX 138
152#define IMX6QDL_CLK_MLB 139
153#define IMX6QDL_CLK_MMDC_CH0_AXI 140
154#define IMX6QDL_CLK_MMDC_CH1_AXI 141
155#define IMX6QDL_CLK_OCRAM 142
156#define IMX6QDL_CLK_OPENVG_AXI 143
157#define IMX6QDL_CLK_PCIE_AXI 144
158#define IMX6QDL_CLK_PWM1 145
159#define IMX6QDL_CLK_PWM2 146
160#define IMX6QDL_CLK_PWM3 147
161#define IMX6QDL_CLK_PWM4 148
162#define IMX6QDL_CLK_PER1_BCH 149
163#define IMX6QDL_CLK_GPMI_BCH_APB 150
164#define IMX6QDL_CLK_GPMI_BCH 151
165#define IMX6QDL_CLK_GPMI_IO 152
166#define IMX6QDL_CLK_GPMI_APB 153
167#define IMX6QDL_CLK_SATA 154
168#define IMX6QDL_CLK_SDMA 155
169#define IMX6QDL_CLK_SPBA 156
170#define IMX6QDL_CLK_SSI1 157
171#define IMX6QDL_CLK_SSI2 158
172#define IMX6QDL_CLK_SSI3 159
173#define IMX6QDL_CLK_UART_IPG 160
174#define IMX6QDL_CLK_UART_SERIAL 161
175#define IMX6QDL_CLK_USBOH3 162
176#define IMX6QDL_CLK_USDHC1 163
177#define IMX6QDL_CLK_USDHC2 164
178#define IMX6QDL_CLK_USDHC3 165
179#define IMX6QDL_CLK_USDHC4 166
180#define IMX6QDL_CLK_VDO_AXI 167
181#define IMX6QDL_CLK_VPU_AXI 168
182#define IMX6QDL_CLK_CKO1 169
183#define IMX6QDL_CLK_PLL1_SYS 170
184#define IMX6QDL_CLK_PLL2_BUS 171
185#define IMX6QDL_CLK_PLL3_USB_OTG 172
186#define IMX6QDL_CLK_PLL4_AUDIO 173
187#define IMX6QDL_CLK_PLL5_VIDEO 174
188#define IMX6QDL_CLK_PLL8_MLB 175
189#define IMX6QDL_CLK_PLL7_USB_HOST 176
190#define IMX6QDL_CLK_PLL6_ENET 177
191#define IMX6QDL_CLK_SSI1_IPG 178
192#define IMX6QDL_CLK_SSI2_IPG 179
193#define IMX6QDL_CLK_SSI3_IPG 180
194#define IMX6QDL_CLK_ROM 181
195#define IMX6QDL_CLK_USBPHY1 182
196#define IMX6QDL_CLK_USBPHY2 183
197#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
198#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
199#define IMX6QDL_CLK_SATA_REF 186
200#define IMX6QDL_CLK_SATA_REF_100M 187
201#define IMX6QDL_CLK_PCIE_REF 188
202#define IMX6QDL_CLK_PCIE_REF_125M 189
203#define IMX6QDL_CLK_ENET_REF 190
204#define IMX6QDL_CLK_USBPHY1_GATE 191
205#define IMX6QDL_CLK_USBPHY2_GATE 192
206#define IMX6QDL_CLK_PLL4_POST_DIV 193
207#define IMX6QDL_CLK_PLL5_POST_DIV 194
208#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
209#define IMX6QDL_CLK_EIM_SLOW 196
210#define IMX6QDL_CLK_SPDIF 197
211#define IMX6QDL_CLK_CKO2_SEL 198
212#define IMX6QDL_CLK_CKO2_PODF 199
213#define IMX6QDL_CLK_CKO2 200
214#define IMX6QDL_CLK_CKO 201
215#define IMX6QDL_CLK_VDOA 202
216#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
217#define IMX6QDL_CLK_LVDS1_SEL 204
218#define IMX6QDL_CLK_LVDS2_SEL 205
219#define IMX6QDL_CLK_LVDS1_GATE 206
220#define IMX6QDL_CLK_LVDS2_GATE 207
221#define IMX6QDL_CLK_ESAI_AHB 208
222#define IMX6QDL_CLK_END 209
223
224#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-17 21:55:22 -0500