diff options
| -rw-r--r-- | arch/arm/mach-zynq/timer.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index 80bf4742fe37..4b81ae1153d3 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c | |||
| @@ -35,9 +35,9 @@ | |||
| 35 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 | 35 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 |
| 36 | * and use same offsets for Timer 2 | 36 | * and use same offsets for Timer 2 |
| 37 | */ | 37 | */ |
| 38 | #define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ | 38 | #define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ |
| 39 | #define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ | 39 | #define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ |
| 40 | #define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ | 40 | #define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ |
| 41 | #define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ | 41 | #define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ |
| 42 | #define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ | 42 | #define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ |
| 43 | #define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ | 43 | #define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ |