9 files changed, 81 insertions, 24 deletions

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 96f958d8cd45..bc4a088f9023 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -330,8 +330,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
         INTEL_I915GM_IDS(gen3_stolen_size),
         INTEL_I945G_IDS(gen3_stolen_size),
         INTEL_I945GM_IDS(gen3_stolen_size),
-        INTEL_VLV_M_IDS(gen3_stolen_size),
-        INTEL_VLV_D_IDS(gen3_stolen_size),
+        INTEL_VLV_M_IDS(gen6_stolen_size),
+        INTEL_VLV_D_IDS(gen6_stolen_size),
         INTEL_PINEVIEW_IDS(gen3_stolen_size),
         INTEL_I965G_IDS(gen3_stolen_size),
         INTEL_G33_IDS(gen3_stolen_size),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8600c315b4c4..ccdbecca070d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1816,6 +1816,7 @@ struct drm_i915_file_private {
 #define HAS_POWER_WELL(dev)     (IS_HASWELL(dev) || IS_BROADWELL(dev))
 #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev))
+#define HAS_PC8(dev)            (IS_HASWELL(dev)) /* XXX HSW:ULX */
 
 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 6dd622d733b9..e4fba39631a5 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -790,7 +790,12 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 
         /* Default to using SSC */
         dev_priv->vbt.lvds_use_ssc = 1;
-        dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
+        /*
+         * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
+         * clock for LVDS.
+         */
+        dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
+                        !HAS_PCH_SPLIT(dev));
         DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->vbt.lvds_ssc_freq);
 
         for (port = PORT_A; port < I915_MAX_PORTS; port++) {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1591576a6101..330077bcd0bd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1406,6 +1406,26 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
         default:
                 break;
         }
+
+        if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
+            pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
+                /*
+                 * This is a big fat ugly hack.
+                 *
+                 * Some machines in UEFI boot mode provide us a VBT that has 18
+                 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
+                 * unknown we fail to light up. Yet the same BIOS boots up with
+                 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
+                 * max, not what it tells us to use.
+                 *
+                 * Note: This will still be broken if the eDP panel is not lit
+                 * up by the BIOS, and thus we can't get the mode at module
+                 * load.
+                 */
+                DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
+                              pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
+                dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
+        }
 }
 
 static void intel_ddi_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3cddd508d110..7ec8b488bb1d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6518,6 +6518,9 @@ static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
 
 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
 {
+        if (!HAS_PC8(dev_priv->dev))
+                return;
+
         mutex_lock(&dev_priv->pc8.lock);
         __hsw_enable_package_c8(dev_priv);
         mutex_unlock(&dev_priv->pc8.lock);
@@ -6525,6 +6528,9 @@ void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
 
 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
 {
+        if (!HAS_PC8(dev_priv->dev))
+                return;
+
         mutex_lock(&dev_priv->pc8.lock);
         __hsw_disable_package_c8(dev_priv);
         mutex_unlock(&dev_priv->pc8.lock);
@@ -6562,6 +6568,9 @@ static void hsw_update_package_c8(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         bool allow;
 
+        if (!HAS_PC8(dev_priv->dev))
+                return;
+
         if (!i915_enable_pc8)
                 return;
 
@@ -6585,18 +6594,28 @@ done:
 
 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
 {
+        if (!HAS_PC8(dev_priv->dev))
+                return;
+
+        mutex_lock(&dev_priv->pc8.lock);
         if (!dev_priv->pc8.gpu_idle) {
                 dev_priv->pc8.gpu_idle = true;
-                hsw_enable_package_c8(dev_priv);
+                __hsw_enable_package_c8(dev_priv);
         }
+        mutex_unlock(&dev_priv->pc8.lock);
 }
 
 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
 {
+        if (!HAS_PC8(dev_priv->dev))
+                return;
+
+        mutex_lock(&dev_priv->pc8.lock);
         if (dev_priv->pc8.gpu_idle) {
                 dev_priv->pc8.gpu_idle = false;
-                hsw_disable_package_c8(dev_priv);
+                __hsw_disable_package_c8(dev_priv);
         }
+        mutex_unlock(&dev_priv->pc8.lock);
 }
 
 #define for_each_power_domain(domain, mask)                             \
@@ -7184,7 +7203,9 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
                 intel_crtc->cursor_visible = visible;
         }
         /* and commit changes on next vblank */
+        POSTING_READ(CURCNTR(pipe));
         I915_WRITE(CURBASE(pipe), base);
+        POSTING_READ(CURBASE(pipe));
 }
 
 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
@@ -7213,7 +7234,9 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
                 intel_crtc->cursor_visible = visible;
         }
         /* and commit changes on next vblank */
+        POSTING_READ(CURCNTR_IVB(pipe));
         I915_WRITE(CURBASE_IVB(pipe), base);