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-rw-r--r--arch/x86/kernel/early-quirks.c4
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c7
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c20
-rw-r--r--drivers/gpu/drm/i915/intel_display.c33
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c2
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c4
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c8
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c26
9 files changed, 81 insertions, 24 deletions
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 96f958d8cd45..bc4a088f9023 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -330,8 +330,8 @@ static struct pci_device_id intel_stolen_ids[] __initdata = {
330 INTEL_I915GM_IDS(gen3_stolen_size), 330 INTEL_I915GM_IDS(gen3_stolen_size),
331 INTEL_I945G_IDS(gen3_stolen_size), 331 INTEL_I945G_IDS(gen3_stolen_size),
332 INTEL_I945GM_IDS(gen3_stolen_size), 332 INTEL_I945GM_IDS(gen3_stolen_size),
333 INTEL_VLV_M_IDS(gen3_stolen_size), 333 INTEL_VLV_M_IDS(gen6_stolen_size),
334 INTEL_VLV_D_IDS(gen3_stolen_size), 334 INTEL_VLV_D_IDS(gen6_stolen_size),
335 INTEL_PINEVIEW_IDS(gen3_stolen_size), 335 INTEL_PINEVIEW_IDS(gen3_stolen_size),
336 INTEL_I965G_IDS(gen3_stolen_size), 336 INTEL_I965G_IDS(gen3_stolen_size),
337 INTEL_G33_IDS(gen3_stolen_size), 337 INTEL_G33_IDS(gen3_stolen_size),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8600c315b4c4..ccdbecca070d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1816,6 +1816,7 @@ struct drm_i915_file_private {
1816#define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 1816#define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1817#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 1817#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1818#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 1818#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1819#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
1819 1820
1820#define INTEL_PCH_DEVICE_ID_MASK 0xff00 1821#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1821#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1822#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 6dd622d733b9..e4fba39631a5 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -790,7 +790,12 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
790 790
791 /* Default to using SSC */ 791 /* Default to using SSC */
792 dev_priv->vbt.lvds_use_ssc = 1; 792 dev_priv->vbt.lvds_use_ssc = 1;
793 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1); 793 /*
794 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
795 * clock for LVDS.
796 */
797 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
798 !HAS_PCH_SPLIT(dev));
794 DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->vbt.lvds_ssc_freq); 799 DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->vbt.lvds_ssc_freq);
795 800
796 for (port = PORT_A; port < I915_MAX_PORTS; port++) { 801 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1591576a6101..330077bcd0bd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1406,6 +1406,26 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
1406 default: 1406 default:
1407 break; 1407 break;
1408 } 1408 }
1409
1410 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1411 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1412 /*
1413 * This is a big fat ugly hack.
1414 *
1415 * Some machines in UEFI boot mode provide us a VBT that has 18
1416 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1417 * unknown we fail to light up. Yet the same BIOS boots up with
1418 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1419 * max, not what it tells us to use.
1420 *
1421 * Note: This will still be broken if the eDP panel is not lit
1422 * up by the BIOS, and thus we can't get the mode at module
1423 * load.
1424 */
1425 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1426 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1427 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1428 }
1409} 1429}
1410 1430
1411static void intel_ddi_destroy(struct drm_encoder *encoder) 1431static void intel_ddi_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3cddd508d110..7ec8b488bb1d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6518,6 +6518,9 @@ static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6518 6518
6519void hsw_enable_package_c8(struct drm_i915_private *dev_priv) 6519void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6520{ 6520{
6521 if (!HAS_PC8(dev_priv->dev))
6522 return;
6523
6521 mutex_lock(&dev_priv->pc8.lock); 6524 mutex_lock(&dev_priv->pc8.lock);
6522 __hsw_enable_package_c8(dev_priv); 6525 __hsw_enable_package_c8(dev_priv);
6523 mutex_unlock(&dev_priv->pc8.lock); 6526 mutex_unlock(&dev_priv->pc8.lock);
@@ -6525,6 +6528,9 @@ void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6525 6528
6526void hsw_disable_package_c8(struct drm_i915_private *dev_priv) 6529void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6527{ 6530{
6531 if (!HAS_PC8(dev_priv->dev))
6532 return;
6533
6528 mutex_lock(&dev_priv->pc8.lock); 6534 mutex_lock(&dev_priv->pc8.lock);
6529 __hsw_disable_package_c8(dev_priv); 6535 __hsw_disable_package_c8(dev_priv);
6530 mutex_unlock(&dev_priv->pc8.lock); 6536 mutex_unlock(&dev_priv->pc8.lock);
@@ -6562,6 +6568,9 @@ static void hsw_update_package_c8(struct drm_device *dev)
6562 struct drm_i915_private *dev_priv = dev->dev_private; 6568 struct drm_i915_private *dev_priv = dev->dev_private;
6563 bool allow; 6569 bool allow;
6564 6570
6571 if (!HAS_PC8(dev_priv->dev))
6572 return;
6573
6565 if (!i915_enable_pc8) 6574 if (!i915_enable_pc8)
6566 return; 6575 return;
6567 6576
@@ -6585,18 +6594,28 @@ done:
6585 6594
6586static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) 6595static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6587{ 6596{
6597 if (!HAS_PC8(dev_priv->dev))
6598 return;
6599
6600 mutex_lock(&dev_priv->pc8.lock);
6588 if (!dev_priv->pc8.gpu_idle) { 6601 if (!dev_priv->pc8.gpu_idle) {
6589 dev_priv->pc8.gpu_idle = true; 6602 dev_priv->pc8.gpu_idle = true;
6590 hsw_enable_package_c8(dev_priv); 6603 __hsw_enable_package_c8(dev_priv);
6591 } 6604 }
6605 mutex_unlock(&dev_priv->pc8.lock);
6592} 6606}
6593 6607
6594static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) 6608static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6595{ 6609{
6610 if (!HAS_PC8(dev_priv->dev))
6611 return;
6612
6613 mutex_lock(&dev_priv->pc8.lock);
6596 if (dev_priv->pc8.gpu_idle) { 6614 if (dev_priv->pc8.gpu_idle) {
6597 dev_priv->pc8.gpu_idle = false; 6615 dev_priv->pc8.gpu_idle = false;
6598 hsw_disable_package_c8(dev_priv); 6616 __hsw_disable_package_c8(dev_priv);
6599 } 6617 }
6618 mutex_unlock(&dev_priv->pc8.lock);
6600} 6619}
6601 6620
6602#define for_each_power_domain(domain, mask) \ 6621#define for_each_power_domain(domain, mask) \
@@ -7184,7 +7203,9 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7184 intel_crtc->cursor_visible = visible; 7203 intel_crtc->cursor_visible = visible;
7185 } 7204 }
7186 /* and commit changes on next vblank */ 7205 /* and commit changes on next vblank */
7206 POSTING_READ(CURCNTR(pipe));
7187 I915_WRITE(CURBASE(pipe), base); 7207 I915_WRITE(CURBASE(pipe), base);
7208 POSTING_READ(CURBASE(pipe));
7188} 7209}
7189 7210
7190static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) 7211static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
@@ -7213,7 +7234,9 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7213 intel_crtc->cursor_visible = visible; 7234 intel_crtc->cursor_visible = visible;
7214 } 7235 }
7215 /* and commit changes on next vblank */ 7236 /* and commit changes on next vblank */
7237 POSTING_READ(CURCNTR_IVB(pipe));
7216 I915_WRITE(CURBASE_IVB(pipe), base); 7238 I915_WRITE(CURBASE_IVB(pipe), base);
7239 POSTING_READ(CURBASE_IVB(pipe));
7217} 7240}
7218 7241
7219/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 7242/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
@@ -9248,8 +9271,7 @@ check_crtc_state(struct drm_device *dev)
9248 enum pipe pipe; 9271 enum pipe pipe;
9249 if (encoder->base.crtc != &crtc->base) 9272 if (encoder->base.crtc != &crtc->base)
9250 continue; 9273 continue;
9251 if (encoder->get_config && 9274 if (encoder->get_hw_state(encoder, &pipe))
9252 encoder->get_hw_state(encoder, &pipe))
9253 encoder->get_config(encoder, &pipe_config); 9275 encoder->get_config(encoder, &pipe_config);
9254 } 9276 }
9255 9277
@@ -10909,8 +10931,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
10909 if (encoder->get_hw_state(encoder, &pipe)) { 10931 if (encoder->get_hw_state(encoder, &pipe)) {
10910 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 10932 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10911 encoder->base.crtc = &crtc->base; 10933 encoder->base.crtc = &crtc->base;
10912 if (encoder->get_config) 10934 encoder->get_config(encoder, &crtc->config);
10913 encoder->get_config(encoder, &crtc->config);
10914 } else { 10935 } else {
10915 encoder->base.crtc = NULL; 10936 encoder->base.crtc = NULL;
10916 } 10937 }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index eb8139da9763..0b2e842fef01 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1774,7 +1774,7 @@ static void intel_disable_dp(struct intel_encoder *encoder)
1774 * ensure that we have vdd while we switch off the panel. */ 1774 * ensure that we have vdd while we switch off the panel. */
1775 ironlake_edp_panel_vdd_on(intel_dp); 1775 ironlake_edp_panel_vdd_on(intel_dp);
1776 ironlake_edp_backlight_off(intel_dp); 1776 ironlake_edp_backlight_off(intel_dp);
1777 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1777 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1778 ironlake_edp_panel_off(intel_dp); 1778 ironlake_edp_panel_off(intel_dp);
1779 1779
1780 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1780 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0a07d7c9cafc..caf2ee4e5441 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1625,7 +1625,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1625 &to_intel_crtc(enabled)->config.adjusted_mode; 1625 &to_intel_crtc(enabled)->config.adjusted_mode;
1626 int clock = adjusted_mode->crtc_clock; 1626 int clock = adjusted_mode->crtc_clock;
1627 int htotal = adjusted_mode->htotal; 1627 int htotal = adjusted_mode->htotal;
1628 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1628 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1629 int pixel_size = enabled->fb->bits_per_pixel / 8; 1629 int pixel_size = enabled->fb->bits_per_pixel / 8;
1630 unsigned long line_time_us; 1630 unsigned long line_time_us;
1631 int entries; 1631 int entries;
@@ -3888,7 +3888,7 @@ static void gen6_enable_rps(struct drm_device *dev)
3888 3888
3889 I915_WRITE(GEN6_RC_SLEEP, 0); 3889 I915_WRITE(GEN6_RC_SLEEP, 0);
3890 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 3890 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3891 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) 3891 if (IS_IVYBRIDGE(dev))
3892 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); 3892 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3893 else 3893 else
3894 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 3894 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 18c406246a2d..22cf0f4ba248 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -902,6 +902,13 @@ intel_tv_mode_valid(struct drm_connector *connector,
902} 902}
903 903
904 904
905static void
906intel_tv_get_config(struct intel_encoder *encoder,
907 struct intel_crtc_config *pipe_config)
908{
909 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
910}
911
905static bool 912static bool
906intel_tv_compute_config(struct intel_encoder *encoder, 913intel_tv_compute_config(struct intel_encoder *encoder,
907 struct intel_crtc_config *pipe_config) 914 struct intel_crtc_config *pipe_config)
@@ -1621,6 +1628,7 @@ intel_tv_init(struct drm_device *dev)
1621 DRM_MODE_ENCODER_TVDAC); 1628 DRM_MODE_ENCODER_TVDAC);
1622 1629
1623 intel_encoder->compute_config = intel_tv_compute_config; 1630 intel_encoder->compute_config = intel_tv_compute_config;
1631 intel_encoder->get_config = intel_tv_get_config;
1624 intel_encoder->mode_set = intel_tv_mode_set; 1632 intel_encoder->mode_set = intel_tv_mode_set;
1625 intel_encoder->enable = intel_enable_tv; 1633 intel_encoder->enable = intel_enable_tv;
1626 intel_encoder->disable = intel_disable_tv; 1634 intel_encoder->disable = intel_disable_tv;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f9883ceff946..0b02078a0b84 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -217,6 +217,19 @@ static void gen6_force_wake_work(struct work_struct *work)
217 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 217 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
218} 218}
219 219
220static void intel_uncore_forcewake_reset(struct drm_device *dev)
221{
222 struct drm_i915_private *dev_priv = dev->dev_private;
223
224 if (IS_VALLEYVIEW(dev)) {
225 vlv_force_wake_reset(dev_priv);
226 } else if (INTEL_INFO(dev)->gen >= 6) {
227 __gen6_gt_force_wake_reset(dev_priv);
228 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
229 __gen6_gt_force_wake_mt_reset(dev_priv);
230 }
231}
232
220void intel_uncore_early_sanitize(struct drm_device *dev) 233void intel_uncore_early_sanitize(struct drm_device *dev)
221{ 234{
222 struct drm_i915_private *dev_priv = dev->dev_private; 235 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -234,19 +247,8 @@ void intel_uncore_early_sanitize(struct drm_device *dev)
234 dev_priv->ellc_size = 128; 247 dev_priv->ellc_size = 128;
235 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); 248 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
236 } 249 }
237}
238 250
239static void intel_uncore_forcewake_reset(struct drm_device *dev) 251 intel_uncore_forcewake_reset(dev);
240{
241 struct drm_i915_private *dev_priv = dev->dev_private;
242
243 if (IS_VALLEYVIEW(dev)) {
244 vlv_force_wake_reset(dev_priv);
245 } else if (INTEL_INFO(dev)->gen >= 6) {
246 __gen6_gt_force_wake_reset(dev_priv);
247 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
248 __gen6_gt_force_wake_mt_reset(dev_priv);
249 }
250} 252}
251 253
252void intel_uncore_sanitize(struct drm_device *dev) 254void intel_uncore_sanitize(struct drm_device *dev)