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-rw-r--r--Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt25
-rw-r--r--arch/arm/plat-mxc/include/mach/i2c.h4
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_psc.h13
-rw-r--r--drivers/i2c/busses/Kconfig16
-rw-r--r--drivers/i2c/busses/Makefile5
-rw-r--r--drivers/i2c/busses/i2c-au1550.c280
-rw-r--r--drivers/i2c/busses/i2c-designware-core.c (renamed from drivers/i2c/busses/i2c-designware.c)382
-rw-r--r--drivers/i2c/busses/i2c-designware-core.h105
-rw-r--r--drivers/i2c/busses/i2c-designware-pcidrv.c392
-rw-r--r--drivers/i2c/busses/i2c-designware-platdrv.c215
-rw-r--r--drivers/i2c/busses/i2c-eg20t.c270
-rw-r--r--drivers/i2c/busses/i2c-imx.c46
12 files changed, 1206 insertions, 547 deletions
diff --git a/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt b/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
new file mode 100644
index 000000000000..f3cf43b66f7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
@@ -0,0 +1,25 @@
1* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
2
3Required properties:
4- compatible : Should be "fsl,<chip>-i2c"
5- reg : Should contain I2C/HS-I2C registers location and length
6- interrupts : Should contain I2C/HS-I2C interrupt
7
8Optional properties:
9- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
10 The absence of the propoerty indicates the default frequency 100 kHz.
11
12Examples:
13
14i2c@83fc4000 { /* I2C2 on i.MX51 */
15 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
16 reg = <0x83fc4000 0x4000>;
17 interrupts = <63>;
18};
19
20i2c@70038000 { /* HS-I2C on i.MX51 */
21 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
22 reg = <0x70038000 0x4000>;
23 interrupts = <64>;
24 clock-frequency = <400000>;
25};
diff --git a/arch/arm/plat-mxc/include/mach/i2c.h b/arch/arm/plat-mxc/include/mach/i2c.h
index 4a5dc5c6d8e8..375cdd0cf876 100644
--- a/arch/arm/plat-mxc/include/mach/i2c.h
+++ b/arch/arm/plat-mxc/include/mach/i2c.h
@@ -11,14 +11,10 @@
11 11
12/** 12/**
13 * struct imxi2c_platform_data - structure of platform data for MXC I2C driver 13 * struct imxi2c_platform_data - structure of platform data for MXC I2C driver
14 * @init: Initialise gpio's and other board specific things
15 * @exit: Free everything initialised by @init
16 * @bitrate: Bus speed measured in Hz 14 * @bitrate: Bus speed measured in Hz
17 * 15 *
18 **/ 16 **/
19struct imxi2c_platform_data { 17struct imxi2c_platform_data {
20 int (*init)(struct device *dev);
21 void (*exit)(struct device *dev);
22 int bitrate; 18 int bitrate;
23}; 19};
24 20
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
index 892b7f168eb4..5a5cb7386427 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -394,19 +394,6 @@ typedef struct psc_spi {
394#define PSC_SPITXRX_LC (1 << 29) 394#define PSC_SPITXRX_LC (1 << 29)
395#define PSC_SPITXRX_SR (1 << 28) 395#define PSC_SPITXRX_SR (1 << 28)
396 396
397/* PSC in SMBus (I2C) Mode. */
398typedef struct psc_smb {
399 u32 psc_sel;
400 u32 psc_ctrl;
401 u32 psc_smbcfg;
402 u32 psc_smbmsk;
403 u32 psc_smbpcr;
404 u32 psc_smbstat;
405 u32 psc_smbevnt;
406 u32 psc_smbtxrx;
407 u32 psc_smbtmr;
408} psc_smb_t;
409
410/* SMBus Config Register. */ 397/* SMBus Config Register. */
411#define PSC_SMBCFG_RT_MASK (3 << 30) 398#define PSC_SMBCFG_RT_MASK (3 << 30)
412#define PSC_SMBCFG_RT_FIFO1 (0 << 30) 399#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 646068e5100b..1d7ce9c18bff 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -350,15 +350,25 @@ config I2C_DAVINCI
350 devices such as DaVinci NIC. 350 devices such as DaVinci NIC.
351 For details please see http://www.ti.com/davinci 351 For details please see http://www.ti.com/davinci
352 352
353config I2C_DESIGNWARE 353config I2C_DESIGNWARE_PLATFORM
354 tristate "Synopsys DesignWare" 354 tristate "Synopsys DesignWare Platfrom"
355 depends on HAVE_CLK 355 depends on HAVE_CLK
356 help 356 help
357 If you say yes to this option, support will be included for the 357 If you say yes to this option, support will be included for the
358 Synopsys DesignWare I2C adapter. Only master mode is supported. 358 Synopsys DesignWare I2C adapter. Only master mode is supported.
359 359
360 This driver can also be built as a module. If so, the module 360 This driver can also be built as a module. If so, the module
361 will be called i2c-designware. 361 will be called i2c-designware-platform.
362
363config I2C_DESIGNWARE_PCI
364 tristate "Synopsys DesignWare PCI"
365 depends on PCI
366 help
367 If you say yes to this option, support will be included for the
368 Synopsys DesignWare I2C adapter. Only master mode is supported.
369
370 This driver can also be built as a module. If so, the module
371 will be called i2c-designware-pci.
362 372
363config I2C_GPIO 373config I2C_GPIO
364 tristate "GPIO-based bitbanging I2C" 374 tristate "GPIO-based bitbanging I2C"
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index e6cf294d3729..fba6da60aa0e 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -33,7 +33,10 @@ obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
33obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o 33obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
34obj-$(CONFIG_I2C_CPM) += i2c-cpm.o 34obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
35obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o 35obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
36obj-$(CONFIG_I2C_DESIGNWARE) += i2c-designware.o 36obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o
37i2c-designware-platform-objs := i2c-designware-platdrv.o i2c-designware-core.o
38obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
39i2c-designware-pci-objs := i2c-designware-pcidrv.o i2c-designware-core.o
37obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o 40obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
38obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o 41obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
39obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o 42obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
diff --git a/drivers/i2c/busses/i2c-au1550.c b/drivers/i2c/busses/i2c-au1550.c
index 532828bc50e6..4f757a2da8cc 100644
--- a/drivers/i2c/busses/i2c-au1550.c
+++ b/drivers/i2c/busses/i2c-au1550.c
@@ -39,29 +39,41 @@
39#include <asm/mach-au1x00/au1xxx.h> 39#include <asm/mach-au1x00/au1xxx.h>
40#include <asm/mach-au1x00/au1xxx_psc.h> 40#include <asm/mach-au1x00/au1xxx_psc.h>
41 41
42#define PSC_SEL 0x00
43#define PSC_CTRL 0x04
44#define PSC_SMBCFG 0x08
45#define PSC_SMBMSK 0x0C
46#define PSC_SMBPCR 0x10
47#define PSC_SMBSTAT 0x14
48#define PSC_SMBEVNT 0x18
49#define PSC_SMBTXRX 0x1C
50#define PSC_SMBTMR 0x20
51
42struct i2c_au1550_data { 52struct i2c_au1550_data {
43 u32 psc_base; 53 void __iomem *psc_base;
44 int xfer_timeout; 54 int xfer_timeout;
45 int ack_timeout;
46 struct i2c_adapter adap; 55 struct i2c_adapter adap;
47 struct resource *ioarea; 56 struct resource *ioarea;
48}; 57};
49 58
50static int 59static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
51wait_xfer_done(struct i2c_au1550_data *adap)
52{ 60{
53 u32 stat; 61 __raw_writel(v, a->psc_base + r);
54 int i; 62 wmb();
55 volatile psc_smb_t *sp; 63}
56 64
57 sp = (volatile psc_smb_t *)(adap->psc_base); 65static inline unsigned long RD(struct i2c_au1550_data *a, int r)
66{
67 return __raw_readl(a->psc_base + r);
68}
58 69
59 /* Wait for Tx Buffer Empty 70static int wait_xfer_done(struct i2c_au1550_data *adap)
60 */ 71{
72 int i;
73
74 /* Wait for Tx Buffer Empty */
61 for (i = 0; i < adap->xfer_timeout; i++) { 75 for (i = 0; i < adap->xfer_timeout; i++) {
62 stat = sp->psc_smbstat; 76 if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
63 au_sync();
64 if ((stat & PSC_SMBSTAT_TE) != 0)
65 return 0; 77 return 0;
66 78
67 udelay(1); 79 udelay(1);
@@ -70,41 +82,27 @@ wait_xfer_done(struct i2c_au1550_data *adap)
70 return -ETIMEDOUT; 82 return -ETIMEDOUT;
71} 83}
72 84
73static int 85static int wait_ack(struct i2c_au1550_data *adap)
74wait_ack(struct i2c_au1550_data *adap)
75{ 86{
76 u32 stat; 87 unsigned long stat;
77 volatile psc_smb_t *sp;
78 88
79 if (wait_xfer_done(adap)) 89 if (wait_xfer_done(adap))
80 return -ETIMEDOUT; 90 return -ETIMEDOUT;
81 91
82 sp = (volatile psc_smb_t *)(adap->psc_base); 92 stat = RD(adap, PSC_SMBEVNT);
83
84 stat = sp->psc_smbevnt;
85 au_sync();
86
87 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) 93 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
88 return -ETIMEDOUT; 94 return -ETIMEDOUT;
89 95
90 return 0; 96 return 0;
91} 97}
92 98
93static int 99static int wait_master_done(struct i2c_au1550_data *adap)
94wait_master_done(struct i2c_au1550_data *adap)
95{ 100{
96 u32 stat; 101 int i;
97 int i;
98 volatile psc_smb_t *sp;
99 102
100 sp = (volatile psc_smb_t *)(adap->psc_base); 103 /* Wait for Master Done. */
101 104 for (i = 0; i < 2 * adap->xfer_timeout; i++) {
102 /* Wait for Master Done. 105 if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
103 */
104 for (i = 0; i < adap->xfer_timeout; i++) {
105 stat = sp->psc_smbevnt;
106 au_sync();
107 if ((stat & PSC_SMBEVNT_MD) != 0)
108 return 0; 106 return 0;
109 udelay(1); 107 udelay(1);
110 } 108 }
@@ -115,29 +113,20 @@ wait_master_done(struct i2c_au1550_data *adap)
115static int 113static int
116do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q) 114do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
117{ 115{
118 volatile psc_smb_t *sp; 116 unsigned long stat;
119 u32 stat;
120 117
121 sp = (volatile psc_smb_t *)(adap->psc_base); 118 /* Reset the FIFOs, clear events. */
122 119 stat = RD(adap, PSC_SMBSTAT);
123 /* Reset the FIFOs, clear events. 120 WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
124 */
125 stat = sp->psc_smbstat;
126 sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR;
127 au_sync();
128 121
129 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) { 122 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
130 sp->psc_smbpcr = PSC_SMBPCR_DC; 123 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
131 au_sync(); 124 while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
132 do { 125 cpu_relax();
133 stat = sp->psc_smbpcr;
134 au_sync();
135 } while ((stat & PSC_SMBPCR_DC) != 0);
136 udelay(50); 126 udelay(50);
137 } 127 }
138 128
139 /* Write out the i2c chip address and specify operation 129 /* Write out the i2c chip address and specify operation */
140 */
141 addr <<= 1; 130 addr <<= 1;
142 if (rd) 131 if (rd)
143 addr |= 1; 132 addr |= 1;
@@ -146,56 +135,42 @@ do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
146 if (q) 135 if (q)
147 addr |= PSC_SMBTXRX_STP; 136 addr |= PSC_SMBTXRX_STP;
148 137
149 /* Put byte into fifo, start up master. 138 /* Put byte into fifo, start up master. */
150 */ 139 WR(adap, PSC_SMBTXRX, addr);
151 sp->psc_smbtxrx = addr; 140 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
152 au_sync();
153 sp->psc_smbpcr = PSC_SMBPCR_MS;
154 au_sync();
155 if (wait_ack(adap)) 141 if (wait_ack(adap))
156 return -EIO; 142 return -EIO;
157 return (q) ? wait_master_done(adap) : 0; 143 return (q) ? wait_master_done(adap) : 0;
158} 144}
159 145
160static u32 146static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out)
161wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data)
162{ 147{
163 int j; 148 int j;
164 u32 data, stat;
165 volatile psc_smb_t *sp;
166 149
167 if (wait_xfer_done(adap)) 150 if (wait_xfer_done(adap))
168 return -EIO; 151 return -EIO;
169 152
170 sp = (volatile psc_smb_t *)(adap->psc_base);
171
172 j = adap->xfer_timeout * 100; 153 j = adap->xfer_timeout * 100;
173 do { 154 do {
174 j--; 155 j--;
175 if (j <= 0) 156 if (j <= 0)
176 return -EIO; 157 return -EIO;
177 158
178 stat = sp->psc_smbstat; 159 if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
179 au_sync();
180 if ((stat & PSC_SMBSTAT_RE) == 0)
181 j = 0; 160 j = 0;
182 else 161 else
183 udelay(1); 162 udelay(1);
184 } while (j > 0); 163 } while (j > 0);
185 data = sp->psc_smbtxrx; 164
186 au_sync(); 165 *out = RD(adap, PSC_SMBTXRX);
187 *ret_data = data;
188 166
189 return 0; 167 return 0;
190} 168}
191 169
192static int 170static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
193i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
194 unsigned int len) 171 unsigned int len)
195{ 172{
196 int i; 173 int i;
197 u32 data;
198 volatile psc_smb_t *sp;
199 174
200 if (len == 0) 175 if (len == 0)
201 return 0; 176 return 0;
@@ -204,62 +179,46 @@ i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
204 * zero bytes for timing, waiting for bytes to appear in the 179 * zero bytes for timing, waiting for bytes to appear in the
205 * receive fifo, then reading the bytes. 180 * receive fifo, then reading the bytes.
206 */ 181 */
207
208 sp = (volatile psc_smb_t *)(adap->psc_base);
209
210 i = 0; 182 i = 0;
211 while (i < (len-1)) { 183 while (i < (len - 1)) {
212 sp->psc_smbtxrx = 0; 184 WR(adap, PSC_SMBTXRX, 0);
213 au_sync(); 185 if (wait_for_rx_byte(adap, &buf[i]))
214 if (wait_for_rx_byte(adap, &data))
215 return -EIO; 186 return -EIO;
216 187
217 buf[i] = data;
218 i++; 188 i++;
219 } 189 }
220 190
221 /* The last byte has to indicate transfer done. 191 /* The last byte has to indicate transfer done. */
222 */ 192 WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
223 sp->psc_smbtxrx = PSC_SMBTXRX_STP;
224 au_sync();
225 if (wait_master_done(adap)) 193 if (wait_master_done(adap))
226 return -EIO; 194 return -EIO;
227 195
228 data = sp->psc_smbtxrx; 196 buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
229 au_sync();
230 buf[i] = data;
231 return 0; 197 return 0;
232} 198}
233 199
234static int 200static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
235i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
236 unsigned int len) 201 unsigned int len)
237{ 202{
238 int i; 203 int i;
239 u32 data; 204 unsigned long data;
240 volatile psc_smb_t *sp;
241 205
242 if (len == 0) 206 if (len == 0)
243 return 0; 207 return 0;
244 208
245 sp = (volatile psc_smb_t *)(adap->psc_base);
246
247 i = 0; 209 i = 0;
248 while (i < (len-1)) { 210 while (i < (len-1)) {
249 data = buf[i]; 211 data = buf[i];
250 sp->psc_smbtxrx = data; 212 WR(adap, PSC_SMBTXRX, data);
251 au_sync();
252 if (wait_ack(adap)) 213 if (wait_ack(adap))
253 return -EIO; 214 return -EIO;
254 i++; 215 i++;
255 } 216 }
256 217
257 /* The last byte has to indicate transfer done. 218 /* The last byte has to indicate transfer done. */
258 */
259 data = buf[i]; 219 data = buf[i];
260 data |= PSC_SMBTXRX_STP; 220 data |= PSC_SMBTXRX_STP;
261 sp->psc_smbtxrx = data; 221 WR(adap, PSC_SMBTXRX, data);
262 au_sync();
263 if (wait_master_done(adap)) 222 if (wait_master_done(adap))
264 return -EIO; 223 return -EIO;
265 return 0; 224 return 0;
@@ -269,12 +228,10 @@ static int
269au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) 228au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
270{ 229{
271 struct i2c_au1550_data *adap = i2c_adap->algo_data; 230 struct i2c_au1550_data *adap = i2c_adap->algo_data;
272 volatile psc_smb_t *sp = (volatile psc_smb_t *)adap->psc_base;
273 struct i2c_msg *p; 231 struct i2c_msg *p;
274 int i, err = 0; 232 int i, err = 0;
275 233
276 sp->psc_ctrl = PSC_CTRL_ENABLE; 234 WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);
277 au_sync();
278 235
279 for (i = 0; !err && i < num; i++) { 236 for (i = 0; !err && i < num; i++) {
280 p = &msgs[i]; 237 p = &msgs[i];
@@ -293,14 +250,12 @@ au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
293 if (err == 0) 250 if (err == 0)
294 err = num; 251 err = num;
295 252
296 sp->psc_ctrl = PSC_CTRL_SUSPEND; 253 WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);
297 au_sync();
298 254
299 return err; 255 return err;
300} 256}
301 257
302static u32 258static u32 au1550_func(struct i2c_adapter *adap)
303au1550_func(struct i2c_adapter *adap)
304{ 259{
305 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 260 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
306} 261}
@@ -312,57 +267,45 @@ static const struct i2c_algorithm au1550_algo = {
312 267
313static void i2c_au1550_setup(struct i2c_au1550_data *priv) 268static void i2c_au1550_setup(struct i2c_au1550_data *priv)
314{ 269{
315 volatile psc_smb_t *sp = (volatile psc_smb_t *)priv->psc_base; 270 unsigned long cfg;
316 u32 stat;
317
318 sp->psc_ctrl = PSC_CTRL_DISABLE;
319 au_sync();
320 sp->psc_sel = PSC_SEL_PS_SMBUSMODE;
321 sp->psc_smbcfg = 0;
322 au_sync();
323 sp->psc_ctrl = PSC_CTRL_ENABLE;
324 au_sync();
325 do {
326 stat = sp->psc_smbstat;
327 au_sync();
328 } while ((stat & PSC_SMBSTAT_SR) == 0);
329 271
330 sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | 272 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
331 PSC_SMBCFG_DD_DISABLE); 273 WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
274 WR(priv, PSC_SMBCFG, 0);
275 WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
276 while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
277 cpu_relax();
278
279 cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE;
280 WR(priv, PSC_SMBCFG, cfg);
332 281
333 /* Divide by 8 to get a 6.25 MHz clock. The later protocol 282 /* Divide by 8 to get a 6.25 MHz clock. The later protocol
334 * timings are based on this clock. 283 * timings are based on this clock.
335 */ 284 */
336 sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); 285 cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
337 sp->psc_smbmsk = PSC_SMBMSK_ALLMASK; 286 WR(priv, PSC_SMBCFG, cfg);
338 au_sync(); 287 WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);
339 288
340 /* Set the protocol timer values. See Table 71 in the 289 /* Set the protocol timer values. See Table 71 in the
341 * Au1550 Data Book for standard timing values. 290 * Au1550 Data Book for standard timing values.
342 */ 291 */
343 sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \ 292 WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
344 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \ 293 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
345 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \ 294 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
346 PSC_SMBTMR_SET_CH(15); 295 PSC_SMBTMR_SET_CH(15));
347 au_sync();
348 296
349 sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE; 297 cfg |= PSC_SMBCFG_DE_ENABLE;
350 do { 298 WR(priv, PSC_SMBCFG, cfg);
351 stat = sp->psc_smbstat; 299 while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
352 au_sync(); 300 cpu_relax();
353 } while ((stat & PSC_SMBSTAT_SR) == 0);
354 301
355 sp->psc_ctrl = PSC_CTRL_SUSPEND; 302 WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
356 au_sync();
357} 303}
358 304
359static void i2c_au1550_disable(struct i2c_au1550_data *priv) 305static void i2c_au1550_disable(struct i2c_au1550_data *priv)
360{ 306{
361 volatile psc_smb_t *sp = (volatile psc_smb_t *)priv->psc_base; 307 WR(priv, PSC_SMBCFG, 0);
362 308 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
363 sp->psc_smbcfg = 0;
364 sp->psc_ctrl = PSC_CTRL_DISABLE;
365 au_sync();
366} 309}
367 310
368/* 311/*
@@ -396,9 +339,12 @@ i2c_au1550_probe(struct platform_device *pdev)
396 goto out_mem; 339 goto out_mem;
397 } 340 }
398 341
399 priv->psc_base = CKSEG1ADDR(r->start); 342 priv->psc_base = ioremap(r->start, resource_size(r));
343 if (!priv->psc_base) {
344 ret = -EIO;
345 goto out_map;
346 }
400 priv->xfer_timeout = 200; 347 priv->xfer_timeout = 200;
401 priv->ack_timeout = 200;
402 348
403 priv->adap.nr = pdev->id; 349 priv->adap.nr = pdev->id;
404 priv->adap.algo = &au1550_algo; 350 priv->adap.algo = &au1550_algo;
@@ -406,8 +352,7 @@ i2c_au1550_probe(struct platform_device *pdev)
406 priv->adap.dev.parent = &pdev->dev; 352 priv->adap.dev.parent = &pdev->dev;
407 strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); 353 strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
408 354
409 /* Now, set up the PSC for SMBus PIO mode. 355 /* Now, set up the PSC for SMBus PIO mode. */
410 */
411 i2c_au1550_setup(priv); 356 i2c_au1550_setup(priv);
412 357
413 ret = i2c_add_numbered_adapter(&priv->adap); 358 ret = i2c_add_numbered_adapter(&priv->adap);
@@ -417,7 +362,8 @@ i2c_au1550_probe(struct platform_device *pdev)
417 } 362 }
418 363
419 i2c_au1550_disable(priv); 364 i2c_au1550_disable(priv);
420 365 iounmap(priv->psc_base);
366out_map:
421 release_resource(priv->ioarea); 367 release_resource(priv->ioarea);
422 kfree(priv->ioarea); 368 kfree(priv->ioarea);
423out_mem: 369out_mem:
@@ -426,14 +372,14 @@ out:
426 return ret; 372 return ret;
427} 373}
428 374
429static int __devexit 375static int __devexit i2c_au1550_remove(struct platform_device *pdev)
430i2c_au1550_remove(struct platform_device *pdev)
431{ 376{
432 struct i2c_au1550_data *priv = platform_get_drvdata(pdev); 377 struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
433 378
434 platform_set_drvdata(pdev, NULL); 379 platform_set_drvdata(pdev, NULL);
435 i2c_del_adapter(&priv->adap); 380 i2c_del_adapter(&priv->adap);
436 i2c_au1550_disable(priv); 381 i2c_au1550_disable(priv);
382 iounmap(priv->psc_base);
437 release_resource(priv->ioarea); 383 release_resource(priv->ioarea);
438 kfree(priv->ioarea); 384 kfree(priv->ioarea);
439 kfree(priv); 385 kfree(priv);
@@ -441,49 +387,51 @@ i2c_au1550_remove(struct platform_device *pdev)
441} 387}
442 388
443#ifdef CONFIG_PM 389#ifdef CONFIG_PM
444static int 390static int i2c_au1550_suspend(struct device *dev)
445i2c_au1550_suspend(struct platform_device *pdev, pm_message_t state)
446{ 391{
447 struct i2c_au1550_data *priv = platform_get_drvdata(pdev); 392 struct i2c_au1550_data *priv = dev_get_drvdata(dev);
448 393
449 i2c_au1550_disable(priv); 394 i2c_au1550_disable(priv);
450 395
451 return 0; 396 return 0;
452} 397}
453 398
454static int 399static int i2c_au1550_resume(struct device *dev)
455i2c_au1550_resume(struct platform_device *pdev)
456{ 400{
457 struct i2c_au1550_data *priv = platform_get_drvdata(pdev); 401 struct i2c_au1550_data *priv = dev_get_drvdata(dev);
458 402
459 i2c_au1550_setup(priv); 403 i2c_au1550_setup(priv);
460 404
461 return 0; 405 return 0;
462} 406}
407
408static const struct dev_pm_ops i2c_au1550_pmops = {
409 .suspend = i2c_au1550_suspend,
410 .resume = i2c_au1550_resume,
411};
412
413#define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)
414
463#else 415#else
464#define i2c_au1550_suspend NULL 416#define AU1XPSC_SMBUS_PMOPS NULL
465#define i2c_au1550_resume NULL
466#endif 417#endif
467 418
468static struct platform_driver au1xpsc_smbus_driver = { 419static struct platform_driver au1xpsc_smbus_driver = {
469 .driver = { 420 .driver = {
470 .name = "au1xpsc_smbus", 421 .name = "au1xpsc_smbus",
471 .owner = THIS_MODULE, 422 .owner = THIS_MODULE,
423 .pm = AU1XPSC_SMBUS_PMOPS,
472 }, 424 },
473 .probe = i2c_au1550_probe, 425 .probe = i2c_au1550_probe,
474 .remove = __devexit_p(i2c_au1550_remove), 426 .remove = __devexit_p(i2c_au1550_remove),
475 .suspend = i2c_au1550_suspend,
476 .resume = i2c_au1550_resume,
477}; 427};
478 428
479static int __init 429static int __init i2c_au1550_init(void)
480i2c_au1550_init(void)
481{ 430{
482 return platform_driver_register(&au1xpsc_smbus_driver); 431 return platform_driver_register(&au1xpsc_smbus_driver);
483} 432}
484 433
485static void __exit 434static void __exit i2c_au1550_exit(void)
486i2c_au1550_exit(void)
487{ 435{
488 platform_driver_unregister(&au1xpsc_smbus_driver); 436 platform_driver_unregister(&au1xpsc_smbus_driver);
489} 437}
diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware-core.c
index 1b42b50b5992..df8799241009 100644
--- a/drivers/i2c/busses/i2c-designware.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -25,18 +25,15 @@
25 * ---------------------------------------------------------------------------- 25 * ----------------------------------------------------------------------------
26 * 26 *
27 */ 27 */
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/delay.h>
31#include <linux/i2c.h>
32#include <linux/clk.h> 28#include <linux/clk.h>
33#include <linux/errno.h> 29#include <linux/errno.h>
34#include <linux/sched.h>
35#include <linux/err.h> 30#include <linux/err.h>
31#include <linux/i2c.h>
36#include <linux/interrupt.h> 32#include <linux/interrupt.h>
37#include <linux/platform_device.h>
38#include <linux/io.h> 33#include <linux/io.h>
39#include <linux/slab.h> 34#include <linux/pm_runtime.h>
35#include <linux/delay.h>
36#include "i2c-designware-core.h"
40 37
41/* 38/*
42 * Registers offset 39 * Registers offset
@@ -68,15 +65,10 @@
68#define DW_IC_STATUS 0x70 65#define DW_IC_STATUS 0x70
69#define DW_IC_TXFLR 0x74 66#define DW_IC_TXFLR 0x74
70#define DW_IC_RXFLR 0x78 67#define DW_IC_RXFLR 0x78
71#define DW_IC_COMP_PARAM_1 0xf4
72#define DW_IC_TX_ABRT_SOURCE 0x80 68#define DW_IC_TX_ABRT_SOURCE 0x80
73 69#define DW_IC_COMP_PARAM_1 0xf4
74#define DW_IC_CON_MASTER 0x1 70#define DW_IC_COMP_TYPE 0xfc
75#define DW_IC_CON_SPEED_STD 0x2 71#define DW_IC_COMP_TYPE_VALUE 0x44570140
76#define DW_IC_CON_SPEED_FAST 0x4
77#define DW_IC_CON_10BITADDR_MASTER 0x10
78#define DW_IC_CON_RESTART_EN 0x20
79#define DW_IC_CON_SLAVE_DISABLE 0x40
80 72
81#define DW_IC_INTR_RX_UNDER 0x001 73#define DW_IC_INTR_RX_UNDER 0x001
82#define DW_IC_INTR_RX_OVER 0x002 74#define DW_IC_INTR_RX_OVER 0x002
@@ -170,55 +162,23 @@ static char *abort_sources[] = {
170 "lost arbitration", 162 "lost arbitration",
171}; 163};
172 164
173/** 165u32 dw_readl(struct dw_i2c_dev *dev, int offset)
174 * struct dw_i2c_dev - private i2c-designware data 166{
175 * @dev: driver model device node 167 u32 value = readl(dev->base + offset);
176 * @base: IO registers pointer 168
177 * @cmd_complete: tx completion indicator 169 if (dev->swab)
178 * @lock: protect this struct and IO registers 170 return swab32(value);
179 * @clk: input reference clock 171 else
180 * @cmd_err: run time hadware error code 172 return value;
181 * @msgs: points to an array of messages currently being transferred 173}
182 * @msgs_num: the number of elements in msgs 174
183 * @msg_write_idx: the element index of the current tx message in the msgs 175void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
184 * array 176{
185 * @tx_buf_len: the length of the current tx buffer 177 if (dev->swab)
186 * @tx_buf: the current tx buffer 178 b = swab32(b);
187 * @msg_read_idx: the element index of the current rx message in the msgs 179
188 * array 180 writel(b, dev->base + offset);
189 * @rx_buf_len: the length of the current rx buffer 181}
190 * @rx_buf: the current rx buffer
191 * @msg_err: error status of the current transfer
192 * @status: i2c master status, one of STATUS_*
193 * @abort_source: copy of the TX_ABRT_SOURCE register
194 * @irq: interrupt number for the i2c master
195 * @adapter: i2c subsystem adapter node
196 * @tx_fifo_depth: depth of the hardware tx fifo
197 * @rx_fifo_depth: depth of the hardware rx fifo
198 */
199struct dw_i2c_dev {
200 struct device *dev;
201 void __iomem *base;
202 struct completion cmd_complete;
203 struct mutex lock;
204 struct clk *clk;
205 int cmd_err;
206 struct i2c_msg *msgs;
207 int msgs_num;
208 int msg_write_idx;
209 u32 tx_buf_len;
210 u8 *tx_buf;
211 int msg_read_idx;
212 u32 rx_buf_len;
213 u8 *rx_buf;
214 int msg_err;
215 unsigned int status;
216 u32 abort_source;
217 int irq;
218 struct i2c_adapter adapter;
219 unsigned int tx_fifo_depth;
220 unsigned int rx_fifo_depth;
221};
222 182
223static u32 183static u32
224i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) 184i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
@@ -283,13 +243,29 @@ static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
283 * This function is called during I2C init function, and in case of timeout at 243 * This function is called during I2C init function, and in case of timeout at
284 * run time. 244 * run time.
285 */ 245 */
286static void i2c_dw_init(struct dw_i2c_dev *dev) 246int i2c_dw_init(struct dw_i2c_dev *dev)
287{ 247{
288 u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; 248 u32 input_clock_khz;
289 u32 ic_con, hcnt, lcnt; 249 u32 hcnt, lcnt;
250 u32 reg;
251
252 input_clock_khz = dev->get_clk_rate_khz(dev);
253
254 /* Configure register endianess access */
255 reg = dw_readl(dev, DW_IC_COMP_TYPE);
256 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
257 dev->swab = 1;
258 reg = DW_IC_COMP_TYPE_VALUE;
259 }
260
261 if (reg != DW_IC_COMP_TYPE_VALUE) {
262 dev_err(dev->dev, "Unknown Synopsys component type: "
263 "0x%08x\n", reg);
264 return -ENODEV;
265 }
290 266
291 /* Disable the adapter */ 267 /* Disable the adapter */
292 writel(0, dev->base + DW_IC_ENABLE); 268 dw_writel(dev, 0, DW_IC_ENABLE);
293 269
294 /* set standard and fast speed deviders for high/low periods */ 270 /* set standard and fast speed deviders for high/low periods */
295 271
@@ -303,8 +279,8 @@ static void i2c_dw_init(struct dw_i2c_dev *dev)
303 47, /* tLOW = 4.7 us */ 279 47, /* tLOW = 4.7 us */
304 3, /* tf = 0.3 us */ 280 3, /* tf = 0.3 us */
305 0); /* No offset */ 281 0); /* No offset */
306 writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT); 282 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
307 writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT); 283 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
308 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); 284 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
309 285
310 /* Fast-mode */ 286 /* Fast-mode */
@@ -317,18 +293,17 @@ static void i2c_dw_init(struct dw_i2c_dev *dev)
317 13, /* tLOW = 1.3 us */ 293 13, /* tLOW = 1.3 us */
318 3, /* tf = 0.3 us */ 294 3, /* tf = 0.3 us */
319 0); /* No offset */ 295 0); /* No offset */
320 writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT); 296 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
321 writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT); 297 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
322 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); 298 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
323 299
324 /* Configure Tx/Rx FIFO threshold levels */ 300 /* Configure Tx/Rx FIFO threshold levels */
325 writel(dev->tx_fifo_depth - 1, dev->base + DW_IC_TX_TL); 301 dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
326 writel(0, dev->base + DW_IC_RX_TL); 302 dw_writel(dev, 0, DW_IC_RX_TL);
327 303
328 /* configure the i2c master */ 304 /* configure the i2c master */
329 ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | 305 dw_writel(dev, dev->master_cfg , DW_IC_CON);
330 DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; 306 return 0;
331 writel(ic_con, dev->base + DW_IC_CON);
332} 307}
333 308
334/* 309/*
@@ -338,7 +313,7 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
338{ 313{
339 int timeout = TIMEOUT; 314 int timeout = TIMEOUT;
340 315
341 while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { 316 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
342 if (timeout <= 0) { 317 if (timeout <= 0) {
343 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 318 dev_warn(dev->dev, "timeout waiting for bus ready\n");
344 return -ETIMEDOUT; 319 return -ETIMEDOUT;
@@ -356,24 +331,24 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
356 u32 ic_con; 331 u32 ic_con;
357 332
358 /* Disable the adapter */ 333 /* Disable the adapter */
359 writel(0, dev->base + DW_IC_ENABLE); 334 dw_writel(dev, 0, DW_IC_ENABLE);
360 335
361 /* set the slave (target) address */ 336 /* set the slave (target) address */
362 writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR); 337 dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
363 338
364 /* if the slave address is ten bit address, enable 10BITADDR */ 339 /* if the slave address is ten bit address, enable 10BITADDR */
365 ic_con = readl(dev->base + DW_IC_CON); 340 ic_con = dw_readl(dev, DW_IC_CON);
366 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) 341 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
367 ic_con |= DW_IC_CON_10BITADDR_MASTER; 342 ic_con |= DW_IC_CON_10BITADDR_MASTER;
368 else 343 else
369 ic_con &= ~DW_IC_CON_10BITADDR_MASTER; 344 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
370 writel(ic_con, dev->base + DW_IC_CON); 345 dw_writel(dev, ic_con, DW_IC_CON);
371 346
372 /* Enable the adapter */ 347 /* Enable the adapter */
373 writel(1, dev->base + DW_IC_ENABLE); 348 dw_writel(dev, 1, DW_IC_ENABLE);
374 349
375 /* Enable interrupts */ 350 /* Enable interrupts */
376 writel(DW_IC_INTR_DEFAULT_MASK, dev->base + DW_IC_INTR_MASK); 351 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
377} 352}
378 353
379/* 354/*
@@ -382,7 +357,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
382 * messages into the tx buffer. Even if the size of i2c_msg data is 357 * messages into the tx buffer. Even if the size of i2c_msg data is
383 * longer than the size of the tx buffer, it handles everything. 358 * longer than the size of the tx buffer, it handles everything.
384 */ 359 */
385static void 360void
386i2c_dw_xfer_msg(struct dw_i2c_dev *dev) 361i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
387{ 362{
388 struct i2c_msg *msgs = dev->msgs; 363 struct i2c_msg *msgs = dev->msgs;
@@ -420,15 +395,15 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
420 buf_len = msgs[dev->msg_write_idx].len; 395 buf_len = msgs[dev->msg_write_idx].len;
421 } 396 }
422 397
423 tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); 398 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
424 rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); 399 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
425 400
426 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { 401 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
427 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { 402 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
428 writel(0x100, dev->base + DW_IC_DATA_CMD); 403 dw_writel(dev, 0x100, DW_IC_DATA_CMD);
429 rx_limit--; 404 rx_limit--;
430 } else 405 } else
431 writel(*buf++, dev->base + DW_IC_DATA_CMD); 406 dw_writel(dev, *buf++, DW_IC_DATA_CMD);
432 tx_limit--; buf_len--; 407 tx_limit--; buf_len--;
433 } 408 }
434 409
@@ -453,7 +428,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
453 if (dev->msg_err) 428 if (dev->msg_err)
454 intr_mask = 0; 429 intr_mask = 0;
455 430
456 writel(intr_mask, dev->base + DW_IC_INTR_MASK); 431 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
457} 432}
458 433
459static void 434static void
@@ -477,10 +452,10 @@ i2c_dw_read(struct dw_i2c_dev *dev)
477 buf = dev->rx_buf; 452 buf = dev->rx_buf;
478 } 453 }
479 454
480 rx_valid = readl(dev->base + DW_IC_RXFLR); 455 rx_valid = dw_readl(dev, DW_IC_RXFLR);
481 456
482 for (; len > 0 && rx_valid > 0; len--, rx_valid--) 457 for (; len > 0 && rx_valid > 0; len--, rx_valid--)
483 *buf++ = readl(dev->base + DW_IC_DATA_CMD); 458 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
484 459
485 if (len > 0) { 460 if (len > 0) {
486 dev->status |= STATUS_READ_IN_PROGRESS; 461 dev->status |= STATUS_READ_IN_PROGRESS;
@@ -518,7 +493,7 @@ static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
518/* 493/*
519 * Prepare controller for a transaction and call i2c_dw_xfer_msg 494 * Prepare controller for a transaction and call i2c_dw_xfer_msg
520 */ 495 */
521static int 496int
522i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 497i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
523{ 498{
524 struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 499 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
@@ -527,6 +502,7 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
527 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 502 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
528 503
529 mutex_lock(&dev->lock); 504 mutex_lock(&dev->lock);
505 pm_runtime_get_sync(dev->dev);
530 506
531 INIT_COMPLETION(dev->cmd_complete); 507 INIT_COMPLETION(dev->cmd_complete);
532 dev->msgs = msgs; 508 dev->msgs = msgs;
@@ -563,7 +539,7 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
563 /* no error */ 539 /* no error */
564 if (likely(!dev->cmd_err)) { 540 if (likely(!dev->cmd_err)) {
565 /* Disable the adapter */ 541 /* Disable the adapter */
566 writel(0, dev->base + DW_IC_ENABLE); 542 dw_writel(dev, 0, DW_IC_ENABLE);
567 ret = num; 543 ret = num;
568 goto done; 544 goto done;
569 } 545 }
@@ -576,19 +552,16 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
576 ret = -EIO; 552 ret = -EIO;
577 553
578done: 554done:
555 pm_runtime_put(dev->dev);
579 mutex_unlock(&dev->lock); 556 mutex_unlock(&dev->lock);
580 557
581 return ret; 558 return ret;
582} 559}
583 560
584static u32 i2c_dw_func(struct i2c_adapter *adap) 561u32 i2c_dw_func(struct i2c_adapter *adap)
585{ 562{
586 return I2C_FUNC_I2C | 563 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
587 I2C_FUNC_10BIT_ADDR | 564 return dev->functionality;
588 I2C_FUNC_SMBUS_BYTE |
589 I2C_FUNC_SMBUS_BYTE_DATA |
590 I2C_FUNC_SMBUS_WORD_DATA |
591 I2C_FUNC_SMBUS_I2C_BLOCK;
592} 565}
593 566
594static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) 567static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
@@ -601,47 +574,47 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
601 * in the IC_RAW_INTR_STAT register. 574 * in the IC_RAW_INTR_STAT register.
602 * 575 *
603 * That is, 576 * That is,
604 * stat = readl(IC_INTR_STAT); 577 * stat = dw_readl(IC_INTR_STAT);
605 * equals to, 578 * equals to,
606 * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); 579 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
607 * 580 *
608 * The raw version might be useful for debugging purposes. 581 * The raw version might be useful for debugging purposes.
609 */ 582 */
610 stat = readl(dev->base + DW_IC_INTR_STAT); 583 stat = dw_readl(dev, DW_IC_INTR_STAT);
611 584
612 /* 585 /*
613 * Do not use the IC_CLR_INTR register to clear interrupts, or 586 * Do not use the IC_CLR_INTR register to clear interrupts, or
614 * you'll miss some interrupts, triggered during the period from 587 * you'll miss some interrupts, triggered during the period from
615 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). 588 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
616 * 589 *
617 * Instead, use the separately-prepared IC_CLR_* registers. 590 * Instead, use the separately-prepared IC_CLR_* registers.
618 */ 591 */
619 if (stat & DW_IC_INTR_RX_UNDER) 592 if (stat & DW_IC_INTR_RX_UNDER)
620 readl(dev->base + DW_IC_CLR_RX_UNDER); 593 dw_readl(dev, DW_IC_CLR_RX_UNDER);
621 if (stat & DW_IC_INTR_RX_OVER) 594 if (stat & DW_IC_INTR_RX_OVER)
622 readl(dev->base + DW_IC_CLR_RX_OVER); 595 dw_readl(dev, DW_IC_CLR_RX_OVER);
623 if (stat & DW_IC_INTR_TX_OVER) 596 if (stat & DW_IC_INTR_TX_OVER)
624 readl(dev->base + DW_IC_CLR_TX_OVER); 597 dw_readl(dev, DW_IC_CLR_TX_OVER);
625 if (stat & DW_IC_INTR_RD_REQ) 598 if (stat & DW_IC_INTR_RD_REQ)
626 readl(dev->base + DW_IC_CLR_RD_REQ); 599 dw_readl(dev, DW_IC_CLR_RD_REQ);
627 if (stat & DW_IC_INTR_TX_ABRT) { 600 if (stat & DW_IC_INTR_TX_ABRT) {
628 /* 601 /*
629 * The IC_TX_ABRT_SOURCE register is cleared whenever 602 * The IC_TX_ABRT_SOURCE register is cleared whenever
630 * the IC_CLR_TX_ABRT is read. Preserve it beforehand. 603 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
631 */ 604 */
632 dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); 605 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
633 readl(dev->base + DW_IC_CLR_TX_ABRT); 606 dw_readl(dev, DW_IC_CLR_TX_ABRT);
634 } 607 }
635 if (stat & DW_IC_INTR_RX_DONE) 608 if (stat & DW_IC_INTR_RX_DONE)
636 readl(dev->base + DW_IC_CLR_RX_DONE); 609 dw_readl(dev, DW_IC_CLR_RX_DONE);
637 if (stat & DW_IC_INTR_ACTIVITY) 610 if (stat & DW_IC_INTR_ACTIVITY)
638 readl(dev->base + DW_IC_CLR_ACTIVITY); 611 dw_readl(dev, DW_IC_CLR_ACTIVITY);
639 if (stat & DW_IC_INTR_STOP_DET) 612 if (stat & DW_IC_INTR_STOP_DET)
640 readl(dev->base + DW_IC_CLR_STOP_DET); 613 dw_readl(dev, DW_IC_CLR_STOP_DET);
641 if (stat & DW_IC_INTR_START_DET) 614 if (stat & DW_IC_INTR_START_DET)
642 readl(dev->base + DW_IC_CLR_START_DET); 615 dw_readl(dev, DW_IC_CLR_START_DET);
643 if (stat & DW_IC_INTR_GEN_CALL) 616 if (stat & DW_IC_INTR_GEN_CALL)
644 readl(dev->base + DW_IC_CLR_GEN_CALL); 617 dw_readl(dev, DW_IC_CLR_GEN_CALL);
645 618
646 return stat; 619 return stat;
647} 620}
@@ -650,13 +623,19 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
650 * Interrupt service routine. This gets called whenever an I2C interrupt 623 * Interrupt service routine. This gets called whenever an I2C interrupt
651 * occurs. 624 * occurs.
652 */ 625 */
653static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) 626irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
654{ 627{
655 struct dw_i2c_dev *dev = dev_id; 628 struct dw_i2c_dev *dev = dev_id;
656 u32 stat; 629 u32 stat, enabled;
630
631 enabled = dw_readl(dev, DW_IC_ENABLE);
632 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
633 dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
634 dev->adapter.name, enabled, stat);
635 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
636 return IRQ_NONE;
657 637
658 stat = i2c_dw_read_clear_intrbits(dev); 638 stat = i2c_dw_read_clear_intrbits(dev);
659 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
660 639
661 if (stat & DW_IC_INTR_TX_ABRT) { 640 if (stat & DW_IC_INTR_TX_ABRT) {
662 dev->cmd_err |= DW_IC_ERR_TX_ABRT; 641 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
@@ -666,7 +645,7 @@ static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
666 * Anytime TX_ABRT is set, the contents of the tx/rx 645 * Anytime TX_ABRT is set, the contents of the tx/rx
667 * buffers are flushed. Make sure to skip them. 646 * buffers are flushed. Make sure to skip them.
668 */ 647 */
669 writel(0, dev->base + DW_IC_INTR_MASK); 648 dw_writel(dev, 0, DW_IC_INTR_MASK);
670 goto tx_aborted; 649 goto tx_aborted;
671 } 650 }
672 651
@@ -689,159 +668,38 @@ tx_aborted:
689 return IRQ_HANDLED; 668 return IRQ_HANDLED;
690} 669}
691 670
692static struct i2c_algorithm i2c_dw_algo = { 671void i2c_dw_enable(struct dw_i2c_dev *dev)
693 .master_xfer = i2c_dw_xfer,
694 .functionality = i2c_dw_func,
695};
696
697static int __devinit dw_i2c_probe(struct platform_device *pdev)
698{ 672{
699 struct dw_i2c_dev *dev; 673 /* Enable the adapter */
700 struct i2c_adapter *adap; 674 dw_writel(dev, 1, DW_IC_ENABLE);
701 struct resource *mem, *ioarea;
702 int irq, r;
703
704 /* NOTE: driver uses the static register mapping */
705 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
706 if (!mem) {
707 dev_err(&pdev->dev, "no mem resource?\n");
708 return -EINVAL;
709 }
710
711 irq = platform_get_irq(pdev, 0);
712 if (irq < 0) {
713 dev_err(&pdev->dev, "no irq resource?\n");
714 return irq; /* -ENXIO */
715 }
716
717 ioarea = request_mem_region(mem->start, resource_size(mem),
718 pdev->name);
719 if (!ioarea) {
720 dev_err(&pdev->dev, "I2C region already claimed\n");
721 return -EBUSY;
722 }
723
724 dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL);
725 if (!dev) {
726 r = -ENOMEM;
727 goto err_release_region;
728 }
729
730 init_completion(&dev->cmd_complete);
731 mutex_init(&dev->lock);
732 dev->dev = get_device(&pdev->dev);
733 dev->irq = irq;
734 platform_set_drvdata(pdev, dev);
735
736 dev->clk = clk_get(&pdev->dev, NULL);
737 if (IS_ERR(dev->clk)) {
738 r = -ENODEV;
739 goto err_free_mem;
740 }
741 clk_enable(dev->clk);
742
743 dev->base = ioremap(mem->start, resource_size(mem));
744 if (dev->base == NULL) {
745 dev_err(&pdev->dev, "failure mapping io resources\n");
746 r = -EBUSY;
747 goto err_unuse_clocks;
748 }
749 {
750 u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1);
751
752 dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1;
753 dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1;
754 }
755 i2c_dw_init(dev);
756
757 writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */
758 r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev);
759 if (r) {
760 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
761 goto err_iounmap;
762 }
763
764 adap = &dev->adapter;
765 i2c_set_adapdata(adap, dev);
766 adap->owner = THIS_MODULE;
767 adap->class = I2C_CLASS_HWMON;
768 strlcpy(adap->name, "Synopsys DesignWare I2C adapter",
769 sizeof(adap->name));
770 adap->algo = &i2c_dw_algo;
771 adap->dev.parent = &pdev->dev;
772
773 adap->nr = pdev->id;
774 r = i2c_add_numbered_adapter(adap);
775 if (r) {
776 dev_err(&pdev->dev, "failure adding adapter\n");
777 goto err_free_irq;
778 }
779
780 return 0;
781
782err_free_irq:
783 free_irq(dev->irq, dev);
784err_iounmap:
785 iounmap(dev->base);
786err_unuse_clocks:
787 clk_disable(dev->clk);
788 clk_put(dev->clk);
789 dev->clk = NULL;
790err_free_mem:
791 platform_set_drvdata(pdev, NULL);
792 put_device(&pdev->dev);
793 kfree(dev);
794err_release_region:
795 release_mem_region(mem->start, resource_size(mem));
796
797 return r;
798} 675}
799 676
800static int __devexit dw_i2c_remove(struct platform_device *pdev) 677u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
801{ 678{
802 struct dw_i2c_dev *dev = platform_get_drvdata(pdev); 679 return dw_readl(dev, DW_IC_ENABLE);
803 struct resource *mem;
804
805 platform_set_drvdata(pdev, NULL);
806 i2c_del_adapter(&dev->adapter);
807 put_device(&pdev->dev);
808
809 clk_disable(dev->clk);
810 clk_put(dev->clk);
811 dev->clk = NULL;
812
813 writel(0, dev->base + DW_IC_ENABLE);
814 free_irq(dev->irq, dev);
815 kfree(dev);
816
817 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 release_mem_region(mem->start, resource_size(mem));
819 return 0;
820} 680}
821 681
822/* work with hotplug and coldplug */ 682void i2c_dw_disable(struct dw_i2c_dev *dev)
823MODULE_ALIAS("platform:i2c_designware"); 683{
684 /* Disable controller */
685 dw_writel(dev, 0, DW_IC_ENABLE);
824 686
825static struct platform_driver dw_i2c_driver = { 687 /* Disable all interupts */
826 .remove = __devexit_p(dw_i2c_remove), 688 dw_writel(dev, 0, DW_IC_INTR_MASK);
827 .driver = { 689 dw_readl(dev, DW_IC_CLR_INTR);
828 .name = "i2c_designware", 690}
829 .owner = THIS_MODULE,
830 },
831};
832 691
833static int __init dw_i2c_init_driver(void) 692void i2c_dw_clear_int(struct dw_i2c_dev *dev)
834{ 693{
835 return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); 694 dw_readl(dev, DW_IC_CLR_INTR);
836} 695}
837module_init(dw_i2c_init_driver);
838 696
839static void __exit dw_i2c_exit_driver(void) 697void i2c_dw_disable_int(struct dw_i2c_dev *dev)
840{ 698{
841 platform_driver_unregister(&dw_i2c_driver); 699 dw_writel(dev, 0, DW_IC_INTR_MASK);
842} 700}
843module_exit(dw_i2c_exit_driver);
844 701
845MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); 702u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
846MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter"); 703{
847MODULE_LICENSE("GPL"); 704 return dw_readl(dev, DW_IC_COMP_PARAM_1);
705}
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
new file mode 100644
index 000000000000..02d1a2ddd853
--- /dev/null
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -0,0 +1,105 @@
1/*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
26 *
27 */
28
29
30#define DW_IC_CON_MASTER 0x1
31#define DW_IC_CON_SPEED_STD 0x2
32#define DW_IC_CON_SPEED_FAST 0x4
33#define DW_IC_CON_10BITADDR_MASTER 0x10
34#define DW_IC_CON_RESTART_EN 0x20
35#define DW_IC_CON_SLAVE_DISABLE 0x40
36
37
38/**
39 * struct dw_i2c_dev - private i2c-designware data
40 * @dev: driver model device node
41 * @base: IO registers pointer
42 * @cmd_complete: tx completion indicator
43 * @lock: protect this struct and IO registers
44 * @clk: input reference clock
45 * @cmd_err: run time hadware error code
46 * @msgs: points to an array of messages currently being transfered
47 * @msgs_num: the number of elements in msgs
48 * @msg_write_idx: the element index of the current tx message in the msgs
49 * array
50 * @tx_buf_len: the length of the current tx buffer
51 * @tx_buf: the current tx buffer
52 * @msg_read_idx: the element index of the current rx message in the msgs
53 * array
54 * @rx_buf_len: the length of the current rx buffer
55 * @rx_buf: the current rx buffer
56 * @msg_err: error status of the current transfer
57 * @status: i2c master status, one of STATUS_*
58 * @abort_source: copy of the TX_ABRT_SOURCE register
59 * @irq: interrupt number for the i2c master
60 * @adapter: i2c subsystem adapter node
61 * @tx_fifo_depth: depth of the hardware tx fifo
62 * @rx_fifo_depth: depth of the hardware rx fifo
63 */
64struct dw_i2c_dev {
65 struct device *dev;
66 void __iomem *base;
67 struct completion cmd_complete;
68 struct mutex lock;
69 struct clk *clk;
70 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
71 struct dw_pci_controller *controller;
72 int cmd_err;
73 struct i2c_msg *msgs;
74 int msgs_num;
75 int msg_write_idx;
76 u32 tx_buf_len;
77 u8 *tx_buf;
78 int msg_read_idx;
79 u32 rx_buf_len;
80 u8 *rx_buf;
81 int msg_err;
82 unsigned int status;
83 u32 abort_source;
84 int irq;
85 int swab;
86 struct i2c_adapter adapter;
87 u32 functionality;
88 u32 master_cfg;
89 unsigned int tx_fifo_depth;
90 unsigned int rx_fifo_depth;
91};
92
93extern u32 dw_readl(struct dw_i2c_dev *dev, int offset);
94extern void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
95extern int i2c_dw_init(struct dw_i2c_dev *dev);
96extern int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
97 int num);
98extern u32 i2c_dw_func(struct i2c_adapter *adap);
99extern irqreturn_t i2c_dw_isr(int this_irq, void *dev_id);
100extern void i2c_dw_enable(struct dw_i2c_dev *dev);
101extern u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev);
102extern void i2c_dw_disable(struct dw_i2c_dev *dev);
103extern void i2c_dw_clear_int(struct dw_i2c_dev *dev);
104extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
105extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
new file mode 100644
index 000000000000..9e89e7313d62
--- /dev/null
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -0,0 +1,392 @@
1/*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 * Copyright (C) 2011 Intel corporation.
10 *
11 * ----------------------------------------------------------------------------
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * ----------------------------------------------------------------------------
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/errno.h>
35#include <linux/sched.h>
36#include <linux/err.h>
37#include <linux/interrupt.h>
38#include <linux/io.h>
39#include <linux/slab.h>
40#include <linux/pci.h>
41#include <linux/pm_runtime.h>
42#include "i2c-designware-core.h"
43
44#define DRIVER_NAME "i2c-designware-pci"
45
46enum dw_pci_ctl_id_t {
47 moorestown_0,
48 moorestown_1,
49 moorestown_2,
50
51 medfield_0,
52 medfield_1,
53 medfield_2,
54 medfield_3,
55 medfield_4,
56 medfield_5,
57};
58
59struct dw_pci_controller {
60 u32 bus_num;
61 u32 bus_cfg;
62 u32 tx_fifo_depth;
63 u32 rx_fifo_depth;
64 u32 clk_khz;
65};
66
67#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
68 DW_IC_CON_SLAVE_DISABLE | \
69 DW_IC_CON_RESTART_EN)
70
71static struct dw_pci_controller dw_pci_controllers[] = {
72 [moorestown_0] = {
73 .bus_num = 0,
74 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
75 .tx_fifo_depth = 32,
76 .rx_fifo_depth = 32,
77 .clk_khz = 25000,
78 },
79 [moorestown_1] = {
80 .bus_num = 1,
81 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
82 .tx_fifo_depth = 32,
83 .rx_fifo_depth = 32,
84 .clk_khz = 25000,
85 },
86 [moorestown_2] = {
87 .bus_num = 2,
88 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
89 .tx_fifo_depth = 32,
90 .rx_fifo_depth = 32,
91 .clk_khz = 25000,
92 },
93 [medfield_0] = {
94 .bus_num = 0,
95 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
96 .tx_fifo_depth = 32,
97 .rx_fifo_depth = 32,
98 .clk_khz = 25000,
99 },
100 [medfield_1] = {
101 .bus_num = 1,
102 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
103 .tx_fifo_depth = 32,
104 .rx_fifo_depth = 32,
105 .clk_khz = 25000,
106 },
107 [medfield_2] = {
108 .bus_num = 2,
109 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
110 .tx_fifo_depth = 32,
111 .rx_fifo_depth = 32,
112 .clk_khz = 25000,
113 },
114 [medfield_3] = {
115 .bus_num = 3,
116 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
117 .tx_fifo_depth = 32,
118 .rx_fifo_depth = 32,
119 .clk_khz = 25000,
120 },
121 [medfield_4] = {
122 .bus_num = 4,
123 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
124 .tx_fifo_depth = 32,
125 .rx_fifo_depth = 32,
126 .clk_khz = 25000,
127 },
128 [medfield_5] = {
129 .bus_num = 5,
130 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
131 .tx_fifo_depth = 32,
132 .rx_fifo_depth = 32,
133 .clk_khz = 25000,
134 },
135};
136static struct i2c_algorithm i2c_dw_algo = {
137 .master_xfer = i2c_dw_xfer,
138 .functionality = i2c_dw_func,
139};
140
141static int i2c_dw_pci_suspend(struct device *dev)
142{
143 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
144 struct dw_i2c_dev *i2c = pci_get_drvdata(pdev);
145 int err;
146
147
148 i2c_dw_disable(i2c);
149
150 err = pci_save_state(pdev);
151 if (err) {
152 dev_err(&pdev->dev, "pci_save_state failed\n");
153 return err;
154 }
155
156 err = pci_set_power_state(pdev, PCI_D3hot);
157 if (err) {
158 dev_err(&pdev->dev, "pci_set_power_state failed\n");
159 return err;
160 }
161
162 return 0;
163}
164
165static int i2c_dw_pci_resume(struct device *dev)
166{
167 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
168 struct dw_i2c_dev *i2c = pci_get_drvdata(pdev);
169 int err;
170 u32 enabled;
171
172 enabled = i2c_dw_is_enabled(i2c);
173 if (enabled)
174 return 0;
175
176 err = pci_set_power_state(pdev, PCI_D0);
177 if (err) {
178 dev_err(&pdev->dev, "pci_set_power_state() failed\n");
179 return err;
180 }
181
182 pci_restore_state(pdev);
183
184 i2c_dw_init(i2c);
185 i2c_dw_enable(i2c);
186 return 0;
187}
188
189static int i2c_dw_pci_runtime_idle(struct device *dev)
190{
191 int err = pm_schedule_suspend(dev, 500);
192 dev_dbg(dev, "runtime_idle called\n");
193
194 if (err != 0)
195 return 0;
196 return -EBUSY;
197}
198
199static const struct dev_pm_ops i2c_dw_pm_ops = {
200 .resume = i2c_dw_pci_resume,
201 .suspend = i2c_dw_pci_suspend,
202 SET_RUNTIME_PM_OPS(i2c_dw_pci_suspend, i2c_dw_pci_resume,
203 i2c_dw_pci_runtime_idle)
204};
205
206static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
207{
208 return dev->controller->clk_khz;
209}
210
211static int __devinit i2c_dw_pci_probe(struct pci_dev *pdev,
212const struct pci_device_id *id)
213{
214 struct dw_i2c_dev *dev;
215 struct i2c_adapter *adap;
216 unsigned long start, len;
217 void __iomem *base;
218 int r;
219 struct dw_pci_controller *controller;
220
221 if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
222 printk(KERN_ERR "dw_i2c_pci_probe: invalid driver data %ld\n",
223 id->driver_data);
224 return -EINVAL;
225 }
226
227 controller = &dw_pci_controllers[id->driver_data];
228
229 r = pci_enable_device(pdev);
230 if (r) {
231 dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
232 r);
233 goto exit;
234 }
235
236 /* Determine the address of the I2C area */
237 start = pci_resource_start(pdev, 0);
238 len = pci_resource_len(pdev, 0);
239 if (!start || len == 0) {
240 dev_err(&pdev->dev, "base address not set\n");
241 r = -ENODEV;
242 goto exit;
243 }
244
245 r = pci_request_region(pdev, 0, DRIVER_NAME);
246 if (r) {
247 dev_err(&pdev->dev, "failed to request I2C region "
248 "0x%lx-0x%lx\n", start,
249 (unsigned long)pci_resource_end(pdev, 0));
250 goto exit;
251 }
252
253 base = ioremap_nocache(start, len);
254 if (!base) {
255 dev_err(&pdev->dev, "I/O memory remapping failed\n");
256 r = -ENOMEM;
257 goto err_release_region;
258 }
259
260
261 dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL);
262 if (!dev) {
263 r = -ENOMEM;
264 goto err_release_region;
265 }
266
267 init_completion(&dev->cmd_complete);
268 mutex_init(&dev->lock);
269 dev->clk = NULL;
270 dev->controller = controller;
271 dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
272 dev->base = base;
273 dev->dev = get_device(&pdev->dev);
274 dev->functionality =
275 I2C_FUNC_I2C |
276 I2C_FUNC_SMBUS_BYTE |
277 I2C_FUNC_SMBUS_BYTE_DATA |
278 I2C_FUNC_SMBUS_WORD_DATA |
279 I2C_FUNC_SMBUS_I2C_BLOCK;
280 dev->master_cfg = controller->bus_cfg;
281
282 pci_set_drvdata(pdev, dev);
283
284 dev->tx_fifo_depth = controller->tx_fifo_depth;
285 dev->rx_fifo_depth = controller->rx_fifo_depth;
286 r = i2c_dw_init(dev);
287 if (r)
288 goto err_iounmap;
289
290 adap = &dev->adapter;
291 i2c_set_adapdata(adap, dev);
292 adap->owner = THIS_MODULE;
293 adap->class = 0;
294 adap->algo = &i2c_dw_algo;
295 adap->dev.parent = &pdev->dev;
296 adap->nr = controller->bus_num;
297 snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci-%d",
298 adap->nr);
299
300 r = request_irq(pdev->irq, i2c_dw_isr, IRQF_SHARED, adap->name, dev);
301 if (r) {
302 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
303 goto err_iounmap;
304 }
305
306 i2c_dw_disable_int(dev);
307 i2c_dw_clear_int(dev);
308 r = i2c_add_numbered_adapter(adap);
309 if (r) {
310 dev_err(&pdev->dev, "failure adding adapter\n");
311 goto err_free_irq;
312 }
313
314 pm_runtime_put_noidle(&pdev->dev);
315 pm_runtime_allow(&pdev->dev);
316
317 return 0;
318
319err_free_irq:
320 free_irq(pdev->irq, dev);
321err_iounmap:
322 iounmap(dev->base);
323 pci_set_drvdata(pdev, NULL);
324 put_device(&pdev->dev);
325 kfree(dev);
326err_release_region:
327 pci_release_region(pdev, 0);
328exit:
329 return r;
330}
331
332static void __devexit i2c_dw_pci_remove(struct pci_dev *pdev)
333{
334 struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
335
336 i2c_dw_disable(dev);
337 pm_runtime_forbid(&pdev->dev);
338 pm_runtime_get_noresume(&pdev->dev);
339
340 pci_set_drvdata(pdev, NULL);
341 i2c_del_adapter(&dev->adapter);
342 put_device(&pdev->dev);
343
344 free_irq(dev->irq, dev);
345 kfree(dev);
346 pci_release_region(pdev, 0);
347}
348
349/* work with hotplug and coldplug */
350MODULE_ALIAS("i2c_designware-pci");
351
352DEFINE_PCI_DEVICE_TABLE(i2_designware_pci_ids) = {
353 /* Moorestown */
354 { PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
355 { PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
356 { PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
357 /* Medfield */
358 { PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
359 { PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
360 { PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
361 { PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
362 { PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
363 { PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
364 { 0,}
365};
366MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
367
368static struct pci_driver dw_i2c_driver = {
369 .name = DRIVER_NAME,
370 .id_table = i2_designware_pci_ids,
371 .probe = i2c_dw_pci_probe,
372 .remove = __devexit_p(i2c_dw_pci_remove),
373 .driver = {
374 .pm = &i2c_dw_pm_ops,
375 },
376};
377
378static int __init dw_i2c_init_driver(void)
379{
380 return pci_register_driver(&dw_i2c_driver);
381}
382module_init(dw_i2c_init_driver);
383
384static void __exit dw_i2c_exit_driver(void)
385{
386 pci_unregister_driver(&dw_i2c_driver);
387}
388module_exit(dw_i2c_exit_driver);
389
390MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
391MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
392MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
new file mode 100644
index 000000000000..2d3657ab1258
--- /dev/null
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -0,0 +1,215 @@
1/*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
26 *
27 */
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/delay.h>
31#include <linux/i2c.h>
32#include <linux/clk.h>
33#include <linux/errno.h>
34#include <linux/sched.h>
35#include <linux/err.h>
36#include <linux/interrupt.h>
37#include <linux/platform_device.h>
38#include <linux/io.h>
39#include <linux/slab.h>
40#include "i2c-designware-core.h"
41
42static struct i2c_algorithm i2c_dw_algo = {
43 .master_xfer = i2c_dw_xfer,
44 .functionality = i2c_dw_func,
45};
46static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
47{
48 return clk_get_rate(dev->clk)/1000;
49}
50
51static int __devinit dw_i2c_probe(struct platform_device *pdev)
52{
53 struct dw_i2c_dev *dev;
54 struct i2c_adapter *adap;
55 struct resource *mem, *ioarea;
56 int irq, r;
57
58 /* NOTE: driver uses the static register mapping */
59 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
60 if (!mem) {
61 dev_err(&pdev->dev, "no mem resource?\n");
62 return -EINVAL;
63 }
64
65 irq = platform_get_irq(pdev, 0);
66 if (irq < 0) {
67 dev_err(&pdev->dev, "no irq resource?\n");
68 return irq; /* -ENXIO */
69 }
70
71 ioarea = request_mem_region(mem->start, resource_size(mem),
72 pdev->name);
73 if (!ioarea) {
74 dev_err(&pdev->dev, "I2C region already claimed\n");
75 return -EBUSY;
76 }
77
78 dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL);
79 if (!dev) {
80 r = -ENOMEM;
81 goto err_release_region;
82 }
83
84 init_completion(&dev->cmd_complete);
85 mutex_init(&dev->lock);
86 dev->dev = get_device(&pdev->dev);
87 dev->irq = irq;
88 platform_set_drvdata(pdev, dev);
89
90 dev->clk = clk_get(&pdev->dev, NULL);
91 dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
92
93 if (IS_ERR(dev->clk)) {
94 r = -ENODEV;
95 goto err_free_mem;
96 }
97 clk_enable(dev->clk);
98
99 dev->functionality =
100 I2C_FUNC_I2C |
101 I2C_FUNC_10BIT_ADDR |
102 I2C_FUNC_SMBUS_BYTE |
103 I2C_FUNC_SMBUS_BYTE_DATA |
104 I2C_FUNC_SMBUS_WORD_DATA |
105 I2C_FUNC_SMBUS_I2C_BLOCK;
106 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
107 DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST;
108
109 dev->base = ioremap(mem->start, resource_size(mem));
110 if (dev->base == NULL) {
111 dev_err(&pdev->dev, "failure mapping io resources\n");
112 r = -EBUSY;
113 goto err_unuse_clocks;
114 }
115 {
116 u32 param1 = i2c_dw_read_comp_param(dev);
117
118 dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1;
119 dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1;
120 }
121 r = i2c_dw_init(dev);
122 if (r)
123 goto err_iounmap;
124
125 i2c_dw_disable_int(dev);
126 r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev);
127 if (r) {
128 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
129 goto err_iounmap;
130 }
131
132 adap = &dev->adapter;
133 i2c_set_adapdata(adap, dev);
134 adap->owner = THIS_MODULE;
135 adap->class = I2C_CLASS_HWMON;
136 strlcpy(adap->name, "Synopsys DesignWare I2C adapter",
137 sizeof(adap->name));
138 adap->algo = &i2c_dw_algo;
139 adap->dev.parent = &pdev->dev;
140
141 adap->nr = pdev->id;
142 r = i2c_add_numbered_adapter(adap);
143 if (r) {
144 dev_err(&pdev->dev, "failure adding adapter\n");
145 goto err_free_irq;
146 }
147
148 return 0;
149
150err_free_irq:
151 free_irq(dev->irq, dev);
152err_iounmap:
153 iounmap(dev->base);
154err_unuse_clocks:
155 clk_disable(dev->clk);
156 clk_put(dev->clk);
157 dev->clk = NULL;
158err_free_mem:
159 platform_set_drvdata(pdev, NULL);
160 put_device(&pdev->dev);
161 kfree(dev);
162err_release_region:
163 release_mem_region(mem->start, resource_size(mem));
164
165 return r;
166}
167
168static int __devexit dw_i2c_remove(struct platform_device *pdev)
169{
170 struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
171 struct resource *mem;
172
173 platform_set_drvdata(pdev, NULL);
174 i2c_del_adapter(&dev->adapter);
175 put_device(&pdev->dev);
176
177 clk_disable(dev->clk);
178 clk_put(dev->clk);
179 dev->clk = NULL;
180
181 i2c_dw_disable(dev);
182 free_irq(dev->irq, dev);
183 kfree(dev);
184
185 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
186 release_mem_region(mem->start, resource_size(mem));
187 return 0;
188}
189
190/* work with hotplug and coldplug */
191MODULE_ALIAS("platform:i2c_designware");
192
193static struct platform_driver dw_i2c_driver = {
194 .remove = __devexit_p(dw_i2c_remove),
195 .driver = {
196 .name = "i2c_designware",
197 .owner = THIS_MODULE,
198 },
199};
200
201static int __init dw_i2c_init_driver(void)
202{
203 return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe);
204}
205module_init(dw_i2c_init_driver);
206
207static void __exit dw_i2c_exit_driver(void)
208{
209 platform_driver_unregister(&dw_i2c_driver);
210}
211module_exit(dw_i2c_exit_driver);
212
213MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
214MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter");
215MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
index ce1a32b71e47..8cebef49aeac 100644
--- a/drivers/i2c/busses/i2c-eg20t.c
+++ b/drivers/i2c/busses/i2c-eg20t.c
@@ -64,6 +64,7 @@
64#define TEN_BIT_ADDR_DEFAULT 0xF000 64#define TEN_BIT_ADDR_DEFAULT 0xF000
65#define TEN_BIT_ADDR_MASK 0xF0 65#define TEN_BIT_ADDR_MASK 0xF0
66#define PCH_START 0x0020 66#define PCH_START 0x0020
67#define PCH_RESTART 0x0004
67#define PCH_ESR_START 0x0001 68#define PCH_ESR_START 0x0001
68#define PCH_BUFF_START 0x1 69#define PCH_BUFF_START 0x1
69#define PCH_REPSTART 0x0004 70#define PCH_REPSTART 0x0004
@@ -273,23 +274,24 @@ static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
273 s32 timeout) 274 s32 timeout)
274{ 275{
275 void __iomem *p = adap->pch_base_address; 276 void __iomem *p = adap->pch_base_address;
277 ktime_t ns_val;
278
279 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
280 return 0;
276 281
277 /* MAX timeout value is timeout*1000*1000nsec */ 282 /* MAX timeout value is timeout*1000*1000nsec */
278 ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000); 283 ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
279 do { 284 do {
280 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
281 break;
282 msleep(20); 285 msleep(20);
286 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
287 return 0;
283 } while (ktime_lt(ktime_get(), ns_val)); 288 } while (ktime_lt(ktime_get(), ns_val));
284 289
285 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 290 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
291 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
292 pch_i2c_init(adap);
286 293
287 if (timeout == 0) { 294 return -ETIME;
288 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
289 return -ETIME;
290 }
291
292 return 0;
293} 295}
294 296
295/** 297/**
@@ -311,21 +313,19 @@ static void pch_i2c_start(struct i2c_algo_pch_data *adap)
311 */ 313 */
312static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap) 314static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
313{ 315{
314 s32 ret; 316 long ret;
315 ret = wait_event_timeout(pch_event, 317 ret = wait_event_timeout(pch_event,
316 (adap->pch_event_flag != 0), msecs_to_jiffies(50)); 318 (adap->pch_event_flag != 0), msecs_to_jiffies(50));
317 if (ret < 0) {
318 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
319 return ret;
320 }
321 319
322 if (ret == 0) { 320 if (ret == 0) {
323 pch_err(adap, "timeout: %x\n", adap->pch_event_flag); 321 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
322 adap->pch_event_flag = 0;
324 return -ETIMEDOUT; 323 return -ETIMEDOUT;
325 } 324 }
326 325
327 if (adap->pch_event_flag & I2C_ERROR_MASK) { 326 if (adap->pch_event_flag & I2C_ERROR_MASK) {
328 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag); 327 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
328 adap->pch_event_flag = 0;
329 return -EIO; 329 return -EIO;
330 } 330 }
331 331
@@ -394,6 +394,7 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
394 u32 addr_2_msb; 394 u32 addr_2_msb;
395 u32 addr_8_lsb; 395 u32 addr_8_lsb;
396 s32 wrcount; 396 s32 wrcount;
397 s32 rtn;
397 void __iomem *p = adap->pch_base_address; 398 void __iomem *p = adap->pch_base_address;
398 399
399 length = msgs->len; 400 length = msgs->len;
@@ -412,15 +413,29 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
412 } 413 }
413 414
414 if (msgs->flags & I2C_M_TEN) { 415 if (msgs->flags & I2C_M_TEN) {
415 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7); 416 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
416 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 417 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
417 if (first) 418 if (first)
418 pch_i2c_start(adap); 419 pch_i2c_start(adap);
419 if (pch_i2c_wait_for_xfer_complete(adap) == 0 && 420
420 pch_i2c_getack(adap) == 0) { 421 rtn = pch_i2c_wait_for_xfer_complete(adap);
422 if (rtn == 0) {
423 if (pch_i2c_getack(adap)) {
424 pch_dbg(adap, "Receive NACK for slave address"
425 "setting\n");
426 return -EIO;
427 }
421 addr_8_lsb = (addr & I2C_ADDR_MSK); 428 addr_8_lsb = (addr & I2C_ADDR_MSK);
422 iowrite32(addr_8_lsb, p + PCH_I2CDR); 429 iowrite32(addr_8_lsb, p + PCH_I2CDR);
423 } else { 430 } else if (rtn == -EIO) { /* Arbitration Lost */
431 pch_err(adap, "Lost Arbitration\n");
432 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
433 I2CMAL_BIT);
434 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
435 I2CMIF_BIT);
436 pch_i2c_init(adap);
437 return -EAGAIN;
438 } else { /* wait-event timeout */
424 pch_i2c_stop(adap); 439 pch_i2c_stop(adap);
425 return -ETIME; 440 return -ETIME;
426 } 441 }
@@ -431,30 +446,51 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
431 pch_i2c_start(adap); 446 pch_i2c_start(adap);
432 } 447 }
433 448
434 if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && 449 rtn = pch_i2c_wait_for_xfer_complete(adap);
435 (pch_i2c_getack(adap) == 0)) { 450 if (rtn == 0) {
436 for (wrcount = 0; wrcount < length; ++wrcount) { 451 if (pch_i2c_getack(adap)) {
437 /* write buffer value to I2C data register */ 452 pch_dbg(adap, "Receive NACK for slave address"
438 iowrite32(buf[wrcount], p + PCH_I2CDR); 453 "setting\n");
439 pch_dbg(adap, "writing %x to Data register\n", 454 return -EIO;
440 buf[wrcount]); 455 }
456 } else if (rtn == -EIO) { /* Arbitration Lost */
457 pch_err(adap, "Lost Arbitration\n");
458 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
459 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
460 pch_i2c_init(adap);
461 return -EAGAIN;
462 } else { /* wait-event timeout */
463 pch_i2c_stop(adap);
464 return -ETIME;
465 }
441 466
442 if (pch_i2c_wait_for_xfer_complete(adap) != 0) 467 for (wrcount = 0; wrcount < length; ++wrcount) {
443 return -ETIME; 468 /* write buffer value to I2C data register */
469 iowrite32(buf[wrcount], p + PCH_I2CDR);
470 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
444 471
445 if (pch_i2c_getack(adap)) 472 rtn = pch_i2c_wait_for_xfer_complete(adap);
473 if (rtn == 0) {
474 if (pch_i2c_getack(adap)) {
475 pch_dbg(adap, "Receive NACK for slave address"
476 "setting\n");
446 return -EIO; 477 return -EIO;
478 }
479 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
480 I2CMCF_BIT);
481 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
482 I2CMIF_BIT);
483 } else { /* wait-event timeout */
484 pch_i2c_stop(adap);
485 return -ETIME;
447 } 486 }
487 }
448 488
449 /* check if this is the last message */ 489 /* check if this is the last message */
450 if (last) 490 if (last)
451 pch_i2c_stop(adap);
452 else
453 pch_i2c_repstart(adap);
454 } else {
455 pch_i2c_stop(adap); 491 pch_i2c_stop(adap);
456 return -EIO; 492 else
457 } 493 pch_i2c_repstart(adap);
458 494
459 pch_dbg(adap, "return=%d\n", wrcount); 495 pch_dbg(adap, "return=%d\n", wrcount);
460 496
@@ -484,6 +520,19 @@ static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
484} 520}
485 521
486/** 522/**
523 * pch_i2c_restart() - Generate I2C restart condition in normal mode.
524 * @adap: Pointer to struct i2c_algo_pch_data.
525 *
526 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
527 */
528static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
529{
530 void __iomem *p = adap->pch_base_address;
531 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
532 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
533}
534
535/**
487 * pch_i2c_readbytes() - read data from I2C bus in normal mode. 536 * pch_i2c_readbytes() - read data from I2C bus in normal mode.
488 * @i2c_adap: Pointer to the struct i2c_adapter. 537 * @i2c_adap: Pointer to the struct i2c_adapter.
489 * @msgs: Pointer to i2c_msg structure. 538 * @msgs: Pointer to i2c_msg structure.
@@ -500,7 +549,9 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
500 u32 length; 549 u32 length;
501 u32 addr; 550 u32 addr;
502 u32 addr_2_msb; 551 u32 addr_2_msb;
552 u32 addr_8_lsb;
503 void __iomem *p = adap->pch_base_address; 553 void __iomem *p = adap->pch_base_address;
554 s32 rtn;
504 555
505 length = msgs->len; 556 length = msgs->len;
506 buf = msgs->buf; 557 buf = msgs->buf;
@@ -515,9 +566,55 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
515 } 566 }
516 567
517 if (msgs->flags & I2C_M_TEN) { 568 if (msgs->flags & I2C_M_TEN) {
518 addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD)); 569 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
519 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 570 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
571 if (first)
572 pch_i2c_start(adap);
520 573
574 rtn = pch_i2c_wait_for_xfer_complete(adap);
575 if (rtn == 0) {
576 if (pch_i2c_getack(adap)) {
577 pch_dbg(adap, "Receive NACK for slave address"
578 "setting\n");
579 return -EIO;
580 }
581 addr_8_lsb = (addr & I2C_ADDR_MSK);
582 iowrite32(addr_8_lsb, p + PCH_I2CDR);
583 } else if (rtn == -EIO) { /* Arbitration Lost */
584 pch_err(adap, "Lost Arbitration\n");
585 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
586 I2CMAL_BIT);
587 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
588 I2CMIF_BIT);
589 pch_i2c_init(adap);
590 return -EAGAIN;
591 } else { /* wait-event timeout */
592 pch_i2c_stop(adap);
593 return -ETIME;
594 }
595 pch_i2c_restart(adap);
596 rtn = pch_i2c_wait_for_xfer_complete(adap);
597 if (rtn == 0) {
598 if (pch_i2c_getack(adap)) {
599 pch_dbg(adap, "Receive NACK for slave address"
600 "setting\n");
601 return -EIO;
602 }
603 addr_2_msb |= I2C_RD;
604 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK,
605 p + PCH_I2CDR);
606 } else if (rtn == -EIO) { /* Arbitration Lost */
607 pch_err(adap, "Lost Arbitration\n");
608 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
609 I2CMAL_BIT);
610 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
611 I2CMIF_BIT);
612 pch_i2c_init(adap);
613 return -EAGAIN;
614 } else { /* wait-event timeout */
615 pch_i2c_stop(adap);
616 return -ETIME;
617 }
521 } else { 618 } else {
522 /* 7 address bits + R/W bit */ 619 /* 7 address bits + R/W bit */
523 addr = (((addr) << 1) | (I2C_RD)); 620 addr = (((addr) << 1) | (I2C_RD));
@@ -528,56 +625,81 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
528 if (first) 625 if (first)
529 pch_i2c_start(adap); 626 pch_i2c_start(adap);
530 627
531 if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && 628 rtn = pch_i2c_wait_for_xfer_complete(adap);
532 (pch_i2c_getack(adap) == 0)) { 629 if (rtn == 0) {
533 pch_dbg(adap, "return %d\n", 0); 630 if (pch_i2c_getack(adap)) {
631 pch_dbg(adap, "Receive NACK for slave address"
632 "setting\n");
633 return -EIO;
634 }
635 } else if (rtn == -EIO) { /* Arbitration Lost */
636 pch_err(adap, "Lost Arbitration\n");
637 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
638 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
639 pch_i2c_init(adap);
640 return -EAGAIN;
641 } else { /* wait-event timeout */
642 pch_i2c_stop(adap);
643 return -ETIME;
644 }
534 645
535 if (length == 0) { 646 if (length == 0) {
536 pch_i2c_stop(adap); 647 pch_i2c_stop(adap);
537 ioread32(p + PCH_I2CDR); /* Dummy read needs */ 648 ioread32(p + PCH_I2CDR); /* Dummy read needs */
538 649
539 count = length; 650 count = length;
540 } else { 651 } else {
541 int read_index; 652 int read_index;
542 int loop; 653 int loop;
543 pch_i2c_sendack(adap); 654 pch_i2c_sendack(adap);
544 655
545 /* Dummy read */ 656 /* Dummy read */
546 for (loop = 1, read_index = 0; loop < length; loop++) { 657 for (loop = 1, read_index = 0; loop < length; loop++) {
547 buf[read_index] = ioread32(p + PCH_I2CDR); 658 buf[read_index] = ioread32(p + PCH_I2CDR);
548 659
549 if (loop != 1) 660 if (loop != 1)
550 read_index++; 661 read_index++;
551 662
552 if (pch_i2c_wait_for_xfer_complete(adap) != 0) { 663 rtn = pch_i2c_wait_for_xfer_complete(adap);
553 pch_i2c_stop(adap); 664 if (rtn == 0) {
554 return -ETIME; 665 if (pch_i2c_getack(adap)) {
666 pch_dbg(adap, "Receive NACK for slave"
667 "address setting\n");
668 return -EIO;
555 } 669 }
556 } /* end for */ 670 } else { /* wait-event timeout */
671 pch_i2c_stop(adap);
672 return -ETIME;
673 }
557 674
558 pch_i2c_sendnack(adap); 675 } /* end for */
559 676
560 buf[read_index] = ioread32(p + PCH_I2CDR); 677 pch_i2c_sendnack(adap);
561 678
562 if (length != 1) 679 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
563 read_index++;
564 680
565 if (pch_i2c_wait_for_xfer_complete(adap) == 0) { 681 if (length != 1)
566 if (last) 682 read_index++;
567 pch_i2c_stop(adap);
568 else
569 pch_i2c_repstart(adap);
570 683
571 buf[read_index++] = ioread32(p + PCH_I2CDR); 684 rtn = pch_i2c_wait_for_xfer_complete(adap);
572 count = read_index; 685 if (rtn == 0) {
573 } else { 686 if (pch_i2c_getack(adap)) {
574 count = -ETIME; 687 pch_dbg(adap, "Receive NACK for slave"
688 "address setting\n");
689 return -EIO;
575 } 690 }
576 691 } else { /* wait-event timeout */
692 pch_i2c_stop(adap);
693 return -ETIME;
577 } 694 }
578 } else { 695
579 count = -ETIME; 696 if (last)
580 pch_i2c_stop(adap); 697 pch_i2c_stop(adap);
698 else
699 pch_i2c_repstart(adap);
700
701 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
702 count = read_index;
581 } 703 }
582 704
583 return count; 705 return count;
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 4c2a62b75b5c..58832e578fff 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -48,6 +48,9 @@
48#include <linux/platform_device.h> 48#include <linux/platform_device.h>
49#include <linux/clk.h> 49#include <linux/clk.h>
50#include <linux/slab.h> 50#include <linux/slab.h>
51#include <linux/of.h>
52#include <linux/of_device.h>
53#include <linux/of_i2c.h>
51 54
52#include <mach/irqs.h> 55#include <mach/irqs.h>
53#include <mach/hardware.h> 56#include <mach/hardware.h>
@@ -125,6 +128,11 @@ struct imx_i2c_struct {
125 unsigned int ifdr; /* IMX_I2C_IFDR */ 128 unsigned int ifdr; /* IMX_I2C_IFDR */
126}; 129};
127 130
131static const struct of_device_id i2c_imx_dt_ids[] = {
132 { .compatible = "fsl,imx1-i2c", },
133 { /* sentinel */ }
134};
135
128/** Functions for IMX I2C adapter driver *************************************** 136/** Functions for IMX I2C adapter driver ***************************************
129*******************************************************************************/ 137*******************************************************************************/
130 138
@@ -466,10 +474,10 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
466{ 474{
467 struct imx_i2c_struct *i2c_imx; 475 struct imx_i2c_struct *i2c_imx;
468 struct resource *res; 476 struct resource *res;
469 struct imxi2c_platform_data *pdata; 477 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
470 void __iomem *base; 478 void __iomem *base;
471 resource_size_t res_size; 479 resource_size_t res_size;
472 int irq; 480 int irq, bitrate;
473 int ret; 481 int ret;
474 482
475 dev_dbg(&pdev->dev, "<%s>\n", __func__); 483 dev_dbg(&pdev->dev, "<%s>\n", __func__);
@@ -485,19 +493,11 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
485 return -ENOENT; 493 return -ENOENT;
486 } 494 }
487 495
488 pdata = pdev->dev.platform_data;
489
490 if (pdata && pdata->init) {
491 ret = pdata->init(&pdev->dev);
492 if (ret)
493 return ret;
494 }
495
496 res_size = resource_size(res); 496 res_size = resource_size(res);
497 497
498 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) { 498 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
499 ret = -EBUSY; 499 dev_err(&pdev->dev, "request_mem_region failed\n");
500 goto fail0; 500 return -EBUSY;
501 } 501 }
502 502
503 base = ioremap(res->start, res_size); 503 base = ioremap(res->start, res_size);
@@ -520,6 +520,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
520 i2c_imx->adapter.algo = &i2c_imx_algo; 520 i2c_imx->adapter.algo = &i2c_imx_algo;
521 i2c_imx->adapter.dev.parent = &pdev->dev; 521 i2c_imx->adapter.dev.parent = &pdev->dev;
522 i2c_imx->adapter.nr = pdev->id; 522 i2c_imx->adapter.nr = pdev->id;
523 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
523 i2c_imx->irq = irq; 524 i2c_imx->irq = irq;
524 i2c_imx->base = base; 525 i2c_imx->base = base;
525 i2c_imx->res = res; 526 i2c_imx->res = res;
@@ -546,10 +547,12 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
546 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 547 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
547 548
548 /* Set up clock divider */ 549 /* Set up clock divider */
549 if (pdata && pdata->bitrate) 550 bitrate = IMX_I2C_BIT_RATE;
550 i2c_imx_set_clk(i2c_imx, pdata->bitrate); 551 ret = of_property_read_u32(pdev->dev.of_node,
551 else 552 "clock-frequency", &bitrate);
552 i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE); 553 if (ret < 0 && pdata && pdata->bitrate)
554 bitrate = pdata->bitrate;
555 i2c_imx_set_clk(i2c_imx, bitrate);
553 556
554 /* Set up chip registers to defaults */ 557 /* Set up chip registers to defaults */
555 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 558 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
@@ -562,6 +565,8 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
562 goto fail5; 565 goto fail5;
563 } 566 }
564 567
568 of_i2c_register_devices(&i2c_imx->adapter);
569
565 /* Set up platform driver data */ 570 /* Set up platform driver data */
566 platform_set_drvdata(pdev, i2c_imx); 571 platform_set_drvdata(pdev, i2c_imx);
567 572
@@ -586,16 +591,12 @@ fail2:
586 iounmap(base); 591 iounmap(base);
587fail1: 592fail1:
588 release_mem_region(res->start, resource_size(res)); 593 release_mem_region(res->start, resource_size(res));
589fail0:
590 if (pdata && pdata->exit)
591 pdata->exit(&pdev->dev);
592 return ret; /* Return error number */ 594 return ret; /* Return error number */
593} 595}
594 596
595static int __exit i2c_imx_remove(struct platform_device *pdev) 597static int __exit i2c_imx_remove(struct platform_device *pdev)
596{ 598{
597 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 599 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
598 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
599 600
600 /* remove adapter */ 601 /* remove adapter */
601 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 602 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
@@ -611,10 +612,6 @@ static int __exit i2c_imx_remove(struct platform_device *pdev)
611 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 612 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
612 writeb(0, i2c_imx->base + IMX_I2C_I2SR); 613 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
613 614
614 /* Shut down hardware */
615 if (pdata && pdata->exit)
616 pdata->exit(&pdev->dev);
617
618 clk_put(i2c_imx->clk); 615 clk_put(i2c_imx->clk);
619 616
620 iounmap(i2c_imx->base); 617 iounmap(i2c_imx->base);
@@ -628,6 +625,7 @@ static struct platform_driver i2c_imx_driver = {
628 .driver = { 625 .driver = {
629 .name = DRIVER_NAME, 626 .name = DRIVER_NAME,
630 .owner = THIS_MODULE, 627 .owner = THIS_MODULE,
628 .of_match_table = i2c_imx_dt_ids,
631 } 629 }
632}; 630};
633 631
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 16:21:53 -0400